defs.h 46.9 KB
Newer Older
1 2 3 4 5
/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
Cedric Roux's avatar
Cedric Roux committed
6
 * the OAI Public License, Version 1.1  (the "License"); you may not use this file
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */

22
/*! \file LAYER2/MAC/defs.h
23
* \brief MAC data structures, constant, and function prototype
24
* \author Navid Nikaein and Raymond Knopp
25 26
* \date 2011
* \version 0.5
27
* \email navid.nikaein@eurecom.fr
28 29

*/
30 31 32 33
/** @defgroup _oai2  openair2 Reference Implementation
 * @ingroup _ref_implementation_
 * @{
 */
34

35
/*@}*/
36

37 38 39 40 41 42 43 44 45 46 47 48 49
#ifndef __LAYER2_MAC_DEFS_H__
#define __LAYER2_MAC_DEFS_H__



#ifdef USER_MODE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif

//#include "COMMON/openair_defs.h"

50 51 52 53


#include "PHY/defs.h"
#include "PHY/LTE_TRANSPORT/defs.h"
54
#include "COMMON/platform_constants.h"
55
#include "BCCH-BCH-Message.h"
56 57 58
#include "RadioResourceConfigCommon.h"
#include "RadioResourceConfigDedicated.h"
#include "MeasGapConfig.h"
59
#include "SchedulingInfoList.h"
60 61 62
#include "TDD-Config.h"
#include "RACH-ConfigCommon.h"
#include "MeasObjectToAddModList.h"
63
#include "MobilityControlInfo.h"
Cedric Roux's avatar
Cedric Roux committed
64
#if defined(Rel10) || defined(Rel14)
65 66 67
#include "MBSFN-AreaInfoList-r9.h"
#include "MBSFN-SubframeConfigList.h"
#include "PMCH-InfoList-r9.h"
68
#include "SCellToAddMod-r10.h"
69
#endif
70 71
#ifdef Rel14
#include "SystemInformationBlockType1-v1310-IEs.h"
72
#include "SystemInformationBlockType18-r12.h"
73
#endif
74
#include "RadioResourceConfigCommonSIB.h"
75 76
#include "nfapi_interface.h"
#include "PHY_INTERFACE/IF_Module.h"
77

78 79
/** @defgroup _mac  MAC
 * @ingroup _oai2
80 81 82
 * @{
 */

83
#define BCCH_PAYLOAD_SIZE_MAX 128
84
#define CCCH_PAYLOAD_SIZE_MAX 128
85
#define PCCH_PAYLOAD_SIZE_MAX 128
86
#define RAR_PAYLOAD_SIZE_MAX 128
87

88 89 90
#define SCH_PAYLOAD_SIZE_MAX 4096
/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB)

Cedric Roux's avatar
Cedric Roux committed
91
#if defined(Rel10) || defined(Rel14)
92

93
// Mask for identifying subframe for MBMS
94 95 96 97 98 99 100 101 102 103 104 105 106 107
#define MBSFN_TDD_SF3 0x80// for TDD
#define MBSFN_TDD_SF4 0x40
#define MBSFN_TDD_SF7 0x20
#define MBSFN_TDD_SF8 0x10
#define MBSFN_TDD_SF9 0x08
#define MBSFN_FDD_SF1 0x80// for FDD
#define MBSFN_FDD_SF2 0x40
#define MBSFN_FDD_SF3 0x20
#define MBSFN_FDD_SF6 0x10
#define MBSFN_FDD_SF7 0x08
#define MBSFN_FDD_SF8 0x04

#define MAX_MBSFN_AREA 8
#define MAX_PMCH_perMBSFN 15
108
/*!\brief MAX MCCH payload size  */
109
#define MCCH_PAYLOAD_SIZE_MAX 128
110
//#define MCH_PAYLOAD_SIZE_MAX 16384// this value is using in case mcs and TBS index are high
111 112 113 114 115 116
#endif

#ifdef USER_MODE
#define printk printf
#endif //USER_MODE

117
/*!\brief Maximum number of logical channl group IDs */
118
#define MAX_NUM_LCGID 4
119 120 121 122 123 124 125 126 127
/*!\brief logical channl group ID 0 */
#define LCGID0 0
/*!\brief logical channl group ID 1 */
#define LCGID1 1
/*!\brief logical channl group ID 2 */
#define LCGID2 2
/*!\brief logical channl group ID 3 */
#define LCGID3 3
/*!\brief Maximum number of logical chanels */
128
#define MAX_NUM_LCID 11
129
/*!\brief Maximum number od control elemenets */
130
#define MAX_NUM_CE 5
131
/*!\brief Maximum number of random access process */
132
#define NB_RA_PROC_MAX 4
133
/*!\brief size of buffer status report table */
134
#define BSR_TABLE_SIZE 64
135
/*!\brief The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1 */
136
#define PHR_MAPPING_OFFSET 23  // if ( x>= -23 ) val = floor (x + 23) 
137
/*!\brief maximum number of resource block groups */
138
#define N_RBG_MAX 25 // for 20MHz channel BW
139
/*!\brief minimum value for channel quality indicator */
140
#define MIN_CQI_VALUE  0
141
/*!\brief maximum value for channel quality indicator */
142
#define MAX_CQI_VALUE  15
143 144 145 146
/*!\briefmaximum number of supported bandwidth (1.4, 5, 10, 20 MHz) */
#define MAX_SUPPORTED_BW  4  
/*!\brief CQI values range from 1 to 15 (4 bits) */
#define CQI_VALUE_RANGE 16 
147

Bilel's avatar
Bilel committed
148
/*!\brief value for indicating BSR Timer is not running */
Bilel's avatar
Bilel committed
149
#define MAC_UE_BSR_TIMER_NOT_RUNNING   (0xFFFF)
150

151 152 153
#define LCID_EMPTY 0
#define LCID_NOT_EMPTY 1

Bilel's avatar
Bilel committed
154 155 156 157 158 159
/*!\brief minimum RLC PDU size to be transmitted = min RLC Status PDU or RLC UM PDU SN 5 bits */
#define MIN_RLC_PDU_SIZE    (2)

/*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */
#define MIN_MAC_HDR_RLC_SIZE    (1 + MIN_RLC_PDU_SIZE)

160 161 162
/*!\brief maximum number of slices / groups */
#define MAX_NUM_SLICES 4 

163 164 165
/* 
 * eNB part 
 */ 
166

167 168 169 170 171

/* 
 * UE/ENB common part 
 */ 
/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */
172
typedef struct {
173 174 175
  uint8_t RAPID:6;
  uint8_t T:1;
  uint8_t E:1;
176 177
} __attribute__((__packed__))RA_HEADER_RAPID;

178
/*!\brief  MAC header of Random Access Response for backoff indicator (BI)*/
179
typedef struct {
180 181 182 183
  uint8_t BI:4;
  uint8_t R:2;
  uint8_t T:1;
  uint8_t E:1;
184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213
} __attribute__((__packed__))RA_HEADER_BI;
/*
typedef struct {
  uint64_t padding:16;
  uint64_t t_crnti:16;
  uint64_t hopping_flag:1;
  uint64_t rb_alloc:10;
  uint64_t mcs:4;
  uint64_t TPC:3;
  uint64_t UL_delay:1;
  uint64_t cqi_req:1;
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t R:1;                        // octet MSB
  } __attribute__((__packed__))RAR_PDU;

typedef struct {
  uint64_t padding:16;
  uint64_t R:1;                        // octet MSB
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t cqi_req:1;
  uint64_t UL_delay:1;
  uint64_t TPC:3;
  uint64_t mcs:4;
  uint64_t rb_alloc:10;
  uint64_t hopping_flag:1;
  uint64_t t_crnti:16;
  } __attribute__((__packed__))RAR_PDU;

#define sizeof_RAR_PDU 6
*/
214
/*!\brief  MAC subheader short with 7bit Length field */
215
typedef struct {
216 217 218 219 220
  uint8_t LCID:5;  // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;     // octet 1 MSB
  uint8_t L:7;     // octet 2 LSB
  uint8_t F:1;     // octet 2 MSB
221
} __attribute__((__packed__))SCH_SUBHEADER_SHORT;
222
/*!\brief  MAC subheader long  with 15bit Length field */
223
typedef struct {
224 225 226 227 228 229 230
  uint8_t LCID:5;   // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;      // octet 1 MSB
  uint8_t L_MSB:7;
  uint8_t F:1;      // octet 2 MSB
  uint8_t L_LSB:8;
  uint8_t padding;
231
} __attribute__((__packed__))SCH_SUBHEADER_LONG;
232
/*!\brief MAC subheader short without length field */
233
typedef struct {
234 235 236
  uint8_t LCID:5;
  uint8_t E:1;
  uint8_t R:2;
237 238
} __attribute__((__packed__))SCH_SUBHEADER_FIXED;

239

knopp's avatar
knopp committed
240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257

/*!\brief  MAC subheader long  with 24bit DST field */
typedef struct {
  uint8_t   R0:4; 
  uint8_t   V:4;//Version number: Possible values "0001", "0010", "0011" based on TS36.321 section 6.2.3.
  uint8_t  SRC07; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC815; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC1623; //Prose UE source ID. Size 24 bits.
  uint8_t  DST07; //Prose UE destination ID. Size 24 bits.
  uint8_t  DST815; //Prose UE destination ID. Size 24 bits.
  uint8_t  DST1623; //Prose UE destination ID. Size 24 bits.
  uint8_t  LCID:5;
  uint8_t  E:1;
  uint8_t  R1:2;
  uint8_t  L:7;	// Length field indicating the size of the corresponding SDU in bytes. 
  uint8_t  F:1;
}__attribute__((__packed__))SLSCH_SUBHEADER_24_Bit_DST_SHORT;

258 259
/*!\brief  MAC subheader long  with 24bit DST field */
typedef struct {
knopp's avatar
knopp committed
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276
  uint8_t   R0:4; 
  uint8_t   V:4;//Version number: Possible values "0001", "0010", "0011" based on TS36.321 section 6.2.3.
  uint8_t  SRC07; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC815; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC1623; //Prose UE source ID. Size 24 bits.
  uint8_t  DST07; //Prose UE destination ID. Size 24 bits.
  uint8_t  DST815; //Prose UE destination ID. Size 24 bits.
  uint8_t  DST1623; //Prose UE destination ID. Size 24 bits.
  uint8_t  LCID:5;
  uint8_t  E:1;
  uint8_t  R1:2;
  uint8_t  L_MSB:7;	// Length field indicating the size of the corresponding SDU in bytes. 
  uint8_t  F:1;
  uint8_t  L_LSB:8;
}__attribute__((__packed__))SLSCH_SUBHEADER_24_Bit_DST_LONG;

/*!\brief  MAC subheader long  with 24bit DST field */
277
typedef struct {
knopp's avatar
knopp committed
278 279 280 281 282 283 284 285 286 287 288 289
  uint8_t   R0:4; 
  uint8_t   V:4;//Version number: Possible values "0001", "0010", "0011" based on TS36.321 section 6.2.3.
  uint8_t  SRC07; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC815; //Prose UE source ID. Size 24 bits.
  uint8_t  DST07; //Prose UE destination ID. Size 16 bits.
  uint8_t  DST815; //Prose UE destination ID. Size 16 bits.
  uint8_t  LCID:5;
  uint8_t  E:1;
  uint8_t  R1:2;
  uint8_t  L:7;	// Length field indicating the size of the corresponding SDU in bytes. 
  uint8_t  F:1;
}__attribute__((__packed__))SLSCH_SUBHEADER_16_Bit_DST_SHORT;
290

knopp's avatar
knopp committed
291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306
/*!\brief  MAC subheader long  with 24bit DST field */
typedef struct {
  uint8_t   R0:4; 
  uint8_t   V:4;//Version number: Possible values "0001", "0010", "0011" based on TS36.321 section 6.2.3.
  uint8_t  SRC07; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC815; //Prose UE source ID. Size 24 bits.
  uint8_t  SRC1623; //Prose UE source ID. Size 24 bits.
  uint8_t  DST07; //Prose UE destination ID. Size 16 bits.
  uint8_t  DST815; //Prose UE destination ID. Size 16 bits.
  uint8_t  LCID:5;
  uint8_t  E:1;
  uint8_t  R1:2;
  uint8_t  L_MSB:7;	// Length field indicating the size of the corresponding SDU in bytes. 
  uint8_t  F:1;
  uint8_t  L_LSB:8;
}__attribute__((__packed__))SLSCH_SUBHEADER_16_Bit_DST_LONG;
307

308
/*!\brief  mac control element: short buffer status report for a specific logical channel group ID*/
309
typedef struct {
310 311
  uint8_t Buffer_size:6;  // octet 1 LSB
  uint8_t LCGID:2;        // octet 1 MSB
312 313 314
} __attribute__((__packed__))BSR_SHORT;

typedef BSR_SHORT BSR_TRUNCATED;
315
/*!\brief  mac control element: long buffer status report for all logical channel group ID*/
316
typedef struct {
fnabet's avatar
fnabet committed
317 318 319 320
  uint8_t Buffer_size3:6;
  uint8_t Buffer_size2:6;
  uint8_t Buffer_size1:6;
  uint8_t Buffer_size0:6;
321 322
} __attribute__((__packed__))BSR_LONG;

323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346
// Panos:
/*!\brief  mac control element: sidelink buffer status report */
typedef struct {
	uint8_t DST_1:4;
	uint8_t LCGID_1: 2;
	uint8_t Buffer_size_1:6;
	uint8_t DST_2:4;
	uint8_t LCGID_2: 2;
	uint8_t Buffer_size_2:6;
}__attribute__((__packed__))SL_BSR;

/*!\brief  mac control element: truncated sidelink buffer status report */
typedef struct {
	uint8_t DST:4;
	uint8_t LCGID: 2;
	uint8_t Buffer_size:6;
	uint8_t R1:1;
	uint8_t R2:1;
	uint8_t R3:1;
	uint8_t R4:1;
}__attribute__((__packed__))SL_BSR_Truncated;



347
#define BSR_LONG_SIZE  (sizeof(BSR_LONG))
348
/*!\brief  mac control element: timing advance  */
349
typedef struct {
350 351
  uint8_t TA:6;
  uint8_t R:2;
352
} __attribute__((__packed__))TIMING_ADVANCE_CMD;
353
/*!\brief  mac control element: power headroom report  */
354
typedef struct {
355 356
  uint8_t PH:6;
  uint8_t R:2;
357 358
} __attribute__((__packed__))POWER_HEADROOM_CMD;

359
/*! \brief MIB payload */
360
typedef struct {
361 362
  uint8_t payload[3] ;
} __attribute__((__packed__))MIB_PDU;
363
/*! \brief CCCH payload */
364
typedef struct {
365
  uint8_t payload[CCCH_PAYLOAD_SIZE_MAX] ;
366
} __attribute__((__packed__))CCCH_PDU;
367
/*! \brief BCCH payload */
368
typedef struct {
369
  uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ;
370
} __attribute__((__packed__))BCCH_PDU;
371 372 373 374
/*! \brief RAR payload */
typedef struct {
  uint8_t payload[RAR_PAYLOAD_SIZE_MAX];
} __attribute__ ((__packed__)) RAR_PDU;
375 376 377 378
/*! \brief BCCH payload */
typedef struct {
  uint8_t payload[PCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))PCCH_PDU;
379

Cedric Roux's avatar
Cedric Roux committed
380
#if defined(Rel10) || defined(Rel14)
381
/*! \brief MCCH payload */
382
typedef struct {
383
  uint8_t payload[MCCH_PAYLOAD_SIZE_MAX] ;
384
} __attribute__((__packed__))MCCH_PDU;
385
/*!< \brief MAC control element for activation and deactivation of component carriers */
386 387 388 389 390 391 392 393 394 395
typedef struct {
  uint8_t C7:1;/*!< \brief Component carrier 7 */
  uint8_t C6:1;/*!< \brief Component carrier 6 */
  uint8_t C5:1;/*!< \brief Component carrier 5 */
  uint8_t C4:1;/*!< \brief Component carrier 4 */
  uint8_t C3:1;/*!< \brief Component carrier 3 */
  uint8_t C2:1;/*!< \brief Component carrier 2 */
  uint8_t C1:1;/*!< \brief Component carrier 1 */
  uint8_t R:1;/*!< \brief Reserved  */
} __attribute__((__packed__))CC_ELEMENT;
396
/*! \brief MAC control element: MCH Scheduling Information */
397
typedef struct {
398 399 400
  uint8_t stop_sf_MSB:3; // octet 1 LSB
  uint8_t lcid:5;        // octet 2 MSB
  uint8_t stop_sf_LSB:8;
401
} __attribute__((__packed__))MSI_ELEMENT;
402 403
#endif
/*! \brief Values of CCCH LCID for DLSCH */ 
404
#define CCCH_LCHANID 0
405
/*!\brief Values of BCCH logical channel (fake)*/
406
#define BCCH 3  // SI 
407
/*!\brief Values of PCCH logical channel (fake)*/
408
#define PCCH 4  // Paging 
409 410
/*!\brief Values of PCCH logical channel (fake) */
#define MIBCH 5  // MIB 
411 412 413 414
/*!\brief Values of BCCH SIB1_BR logical channel (fake) */
#define BCCH_SIB1_BR 6  // SIB1_BR 
/*!\brief Values of BCCH SIB_BR logical channel (fake) */
#define BCCH_SI_BR 7  // SI-BR 
415 416 417 418 419 420 421 422 423 424 425 426 427 428
/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0  // srb0
/*!\brief DCCH / SRB1 logical channel */
#define DCCH 1  // srb1
/*!\brief DCCH1 / SRB2  logical channel */
#define DCCH1 2 // srb2
/*!\brief DTCH DRB1  logical channel */
#define DTCH 3 // LCID
/*!\brief MCCH logical channel */
#define MCCH 4 
/*!\brief MTCH logical channel */
#define MTCH 1 
// DLSCH LCHAN ID
/*!\brief LCID of UE contention resolution identity for DLSCH*/
429
#define UE_CONT_RES 28
430
/*!\brief LCID of timing advance for DLSCH */
431
#define TIMING_ADV_CMD 29
432
/*!\brief LCID of discontinous reception mode for DLSCH */
433
#define DRX_CMD 30
434
/*!\brief LCID of padding LCID for DLSCH */
435 436
#define SHORT_PADDING 31

Cedric Roux's avatar
Cedric Roux committed
437
#if defined(Rel10) || defined(Rel14)
438
// MCH LCHAN IDs (table6.2.1-4 TS36.321)
439
/*!\brief LCID of MCCH for DL */
440
#define MCCH_LCHANID 0
441 442 443
/*!\brief LCID of MCH scheduling info for DL */
#define MCH_SCHDL_INFO 3
/*!\brief LCID of Carrier component activation/deactivation */
444
#define CC_ACT_DEACT 27
445 446 447
#endif

// ULSCH LCHAN IDs
448
/*!\brief LCID of extended power headroom for ULSCH */
449
#define EXTENDED_POWER_HEADROOM 25
450
/*!\brief LCID of power headroom for ULSCH */
451
#define POWER_HEADROOM 26
452
/*!\brief LCID of CRNTI for ULSCH */
453
#define CRNTI 27
454
/*!\brief LCID of truncated BSR for ULSCH */
455
#define TRUNCATED_BSR 28
456
/*!\brief LCID of short BSR for ULSCH */
457
#define SHORT_BSR 29
458
/*!\brief LCID of long BSR for ULSCH */
459
#define LONG_BSR 30
fnabet's avatar
fnabet committed
460 461 462 463 464
/*!\bitmaps for BSR Triggers */
#define	BSR_TRIGGER_NONE		(0)			/* No BSR Trigger */
#define	BSR_TRIGGER_REGULAR		(1)			/* For Regular and ReTxBSR Expiry Triggers */
#define	BSR_TRIGGER_PERIODIC	(2)			/* For BSR Periodic Timer Expiry Trigger */
#define	BSR_TRIGGER_PADDING		(4)			/* For Padding BSR Trigger */
465 466


467
/*! \brief Downlink SCH PDU Structure */
468
typedef struct {
469
  uint8_t payload[8][SCH_PAYLOAD_SIZE_MAX];
470
  uint16_t Pdu_size[8];
471 472
} __attribute__ ((__packed__)) DLSCH_PDU;

473

474
/*! \brief MCH PDU Structure */
475
typedef struct {
476 477
  int8_t payload[SCH_PAYLOAD_SIZE_MAX];
  uint16_t Pdu_size;
478
  uint8_t mcs;
479 480 481
  uint8_t sync_area;
  uint8_t msi_active;
  uint8_t mcch_active;
482
  uint8_t mtch_active;
483 484
} __attribute__ ((__packed__)) MCH_PDU;

485
/*! \brief Uplink SCH PDU Structure */
486
typedef struct {
487 488
  int8_t payload[SCH_PAYLOAD_SIZE_MAX];         /*!< \brief SACH payload */
  uint16_t Pdu_size;
489 490 491 492
} __attribute__ ((__packed__)) ULSCH_PDU;

#include "PHY/impl_defs_top.h"

493
/*!\brief  UE ULSCH scheduling states*/
494 495 496
typedef enum {
  S_UL_NONE =0,
  S_UL_WAITING,
497 498
  S_UL_SCHEDULED,
  S_UL_BUFFERED,
499 500 501
  S_UL_NUM_STATUS
} UE_ULSCH_STATUS;

502
/*!\brief  UE DLSCH scheduling states*/
503 504 505
typedef enum {
  S_DL_NONE =0,
  S_DL_WAITING,
506 507
  S_DL_SCHEDULED,
  S_DL_BUFFERED,
508 509 510
  S_DL_NUM_STATUS
} UE_DLSCH_STATUS;

511
/*!\brief  scheduling policy for the contention-based access */
512
typedef enum {
513 514 515 516 517
  CBA_ES=0, /// equal share of RB among groups w
  CBA_ES_S,  /// equal share of RB among groups with small allocation
  CBA_PF, /// proportional fair (kind of)
  CBA_PF_S,  /// proportional fair (kind of) with small RB allocation
  CBA_RS /// random allocation
518 519 520
} CBA_POLICY;


521
/*! \brief temporary struct for ULSCH sched */
522
typedef struct {
gauthier's avatar
gauthier committed
523
  rnti_t rnti;
524 525
  uint16_t subframe;
  uint16_t serving_num;
526 527
  UE_ULSCH_STATUS status;
} eNB_ULSCH_INFO;
528
/*! \brief temp struct for DLSCH sched */
529
typedef struct {
gauthier's avatar
gauthier committed
530
  rnti_t rnti;
531 532 533
  uint16_t weight;
  uint16_t subframe;
  uint16_t serving_num;
534 535
  UE_DLSCH_STATUS status;
} eNB_DLSCH_INFO;
536
/*! \brief eNB overall statistics */
537
typedef struct {
538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556
  /// num BCCH PDU per CC 
  uint32_t total_num_bcch_pdu;
  /// BCCH buffer size  
  uint32_t bcch_buffer;
  /// total BCCH buffer size  
  uint32_t total_bcch_buffer;
  /// BCCH MCS
  uint32_t bcch_mcs;

  /// num CCCH PDU per CC 
  uint32_t total_num_ccch_pdu;
  /// BCCH buffer size  
  uint32_t ccch_buffer;
  /// total BCCH buffer size  
  uint32_t total_ccch_buffer;
  /// BCCH MCS
  uint32_t ccch_mcs;

/// num active users
557 558 559 560 561
  uint16_t num_dlactive_UEs;
  ///  available number of PRBs for a give SF
  uint16_t available_prbs;
  /// total number of PRB available for the user plane
  uint32_t total_available_prbs;
562 563
  /// aggregation
  /// total avilable nccc : num control channel element
564
  uint16_t available_ncces;
565 566
  // only for a new transmission, should be extended for retransmission
  // current dlsch  bit rate for all transport channels
567 568 569 570 571
  uint32_t dlsch_bitrate;
  //
  uint32_t dlsch_bytes_tx;
  //
  uint32_t dlsch_pdus_tx;
572
  //
573 574 575 576 577
  uint32_t total_dlsch_bitrate;
  //
  uint32_t total_dlsch_bytes_tx;
  //
  uint32_t total_dlsch_pdus_tx;
578 579
  
  // here for RX
580 581 582 583 584
  //
  uint32_t ulsch_bitrate;
  //
  uint32_t ulsch_bytes_rx;
  //
585 586 587 588 589 590 591 592
  uint64_t ulsch_pdus_rx; 

  uint32_t total_ulsch_bitrate;
  //
  uint32_t total_ulsch_bytes_rx;
  //
  uint32_t total_ulsch_pdus_rx;
  
593 594 595 596 597 598 599
  
  /// MAC agent-related stats
  /// total number of scheduling decisions
  int sched_decisions;
  /// missed deadlines
  int missed_deadlines;

600
} eNB_STATS;
601
/*! \brief eNB statistics for the connected UEs*/
602
typedef struct {
603 604

  /// CRNTI of UE
gauthier's avatar
gauthier committed
605
  rnti_t crnti; ///user id (rnti) of connected UEs
606
  // rrc status
607 608 609
  uint8_t rrc_status;
  /// harq pid
  uint8_t harq_pid;
610
  /// harq rounf
611 612 613 614 615
  uint8_t harq_round;
  /// total available number of PRBs for a new transmission
  uint16_t rbs_used;
  /// total available number of PRBs for a retransmission
  uint16_t rbs_used_retx;
616
  /// total nccc used for a new transmission: num control channel element
617
  uint16_t ncce_used;
618
  /// total avilable nccc for a retransmission: num control channel element
619
  uint16_t ncce_used_retx;
620 621

  // mcs1 before the rate adaptaion
622
  uint8_t dlsch_mcs1;
623
  /// Target mcs2 after rate-adaptation
624
  uint8_t dlsch_mcs2;
625
  //  current TBS with mcs2
626
  uint32_t TBS;
627
  //  total TBS with mcs2
628
  //  uint32_t total_TBS;
629
  //  total rb used for a new transmission
630
  uint32_t total_rbs_used;
631
  //  total rb used for retransmission
632
  uint32_t total_rbs_used_retx;
633

634
   /// TX
635 636 637 638 639 640 641 642
  /// Num pkt
  uint32_t num_pdu_tx[NB_RB_MAX];
  /// num bytes
  uint32_t num_bytes_tx[NB_RB_MAX];
  /// num retransmission / harq
  uint32_t num_retransmission;
  /// instantaneous tx throughput for each TTI
  //  uint32_t tti_throughput[NB_RB_MAX];
643 644

  /// overall
645
  //
646 647 648 649
  uint32_t  dlsch_bitrate;
  //total
  uint32_t  total_dlsch_bitrate;
  /// headers+ CE +  padding bytes for a MAC PDU
650
  uint64_t overhead_bytes;
651
  /// headers+ CE +  padding bytes for a MAC PDU
652
  uint64_t total_overhead_bytes;
653
  /// headers+ CE +  padding bytes for a MAC PDU
654
  uint64_t avg_overhead_bytes;
655
  // MAC multiplexed payload
656 657 658
  uint64_t total_sdu_bytes;
  // total MAC pdu bytes
  uint64_t total_pdu_bytes;
659

660 661 662 663
  // total num pdu
  uint32_t total_num_pdus;
  //
  //  uint32_t avg_pdu_size;
664 665

  /// RX
666

667 668 669 670 671 672
  /// PUCCH1a/b power (dBm)
  int32_t Po_PUCCH_dBm;
  /// Indicator that Po_PUCCH has been updated by PHY
  int32_t Po_PUCCH_update;
  /// Uplink measured RSSI
  int32_t UL_rssi;
673 674 675 676 677
  /// preassigned mcs after rate adaptation
  uint8_t ulsch_mcs1;
  /// adjusted mcs
  uint8_t ulsch_mcs2;

678 679 680 681
  /// estimated average pdu inter-departure time
  uint32_t avg_pdu_idt;
  /// estimated average pdu size
  uint32_t avg_pdu_ps;
682
  ///
683 684
  uint32_t aggregated_pdu_size;
  uint32_t aggregated_pdu_arrival;
685

686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
  ///  uplink transport block size
  uint32_t ulsch_TBS;

  ///  total rb used for a new uplink transmission
  uint32_t num_retransmission_rx;
  ///  total rb used for a new uplink transmission
  uint32_t rbs_used_rx;
   ///  total rb used for a new uplink retransmission
  uint32_t rbs_used_retx_rx;
  ///  total rb used for a new uplink transmission
  uint32_t total_rbs_used_rx;
  /// normalized rx power 
  int32_t      normalized_rx_power;
   /// target rx power 
  int32_t    target_rx_power;

702
  /// num rx pdu
703
  uint32_t num_pdu_rx[NB_RB_MAX];
704
  /// num bytes rx
705
  uint32_t num_bytes_rx[NB_RB_MAX];
706
  /// instantaneous rx throughput for each TTI
707
  //  uint32_t tti_goodput[NB_RB_MAX];
708 709
  /// errors
  uint32_t num_errors_rx;
710 711 712 713 714 715 716 717 718 719
  
  uint64_t overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t total_overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t avg_overhead_bytes_rx;
 //
  uint32_t  ulsch_bitrate;
  //total
  uint32_t  total_ulsch_bitrate;
720
  /// overall
721 722
  ///  MAC pdu bytes
  uint64_t pdu_bytes_rx;
723
  /// total MAC pdu bytes
724
  uint64_t total_pdu_bytes_rx;
725
  /// total num pdu
726
  uint32_t total_num_pdus_rx;
727
  /// num of error pdus
728
  uint32_t total_num_errors_rx;
729

730
} eNB_UE_STATS;
731
/*! \brief eNB template for UE context information  */
732
typedef struct {
733
  /// C-RNTI of UE
gauthier's avatar
gauthier committed
734
  rnti_t rnti;
735 736
  /// NDI from last scheduling
  uint8_t oldNDI[8];
737 738 739 740
  /// mcs1 from last scheduling
  uint8_t oldmcs1[8];
  /// mcs2 from last scheduling
  uint8_t oldmcs2[8];
741 742
  /// NDI from last UL scheduling
  uint8_t oldNDI_UL[8];
743 744 745 746
  /// mcs from last UL scheduling
  uint8_t mcs_UL[8];
  /// TBS from last UL scheduling
  uint8_t TBS_UL[8];
747
  /// Flag to indicate UL has been scheduled at least once
gauthier's avatar
gauthier committed
748
  boolean_t ul_active;
749 750
  /// Flag to indicate UE has been configured (ACK from RRCConnectionSetup received)
  boolean_t configured;
751

752 753 754 755 756 757
  /// MCS from last scheduling
  uint8_t mcs[8];

  /// TPC from last scheduling
  uint8_t oldTPC[8];

758 759 760
  // PHY interface info

  /// Number of Allocated RBs for DL after scheduling (prior to frequency allocation)
761
  uint16_t nb_rb[8]; // num_max_harq
762

763
  /// Number of Allocated RBs for UL after scheduling
764
  uint16_t nb_rb_ul[8]; // num_max_harq
765

766 767 768 769 770 771
  /// Number of Allocated RBs for UL after scheduling
  uint16_t first_rb_ul[8]; // num_max_harq

  /// Cyclic shift for DMRS after scheduling
  uint16_t cshift[8]; // num_max_harq

772 773
  /// Number of Allocated RBs by the ulsch preprocessor
  uint8_t pre_allocated_nb_rb_ul;
774

775 776
  /// index of Allocated RBs by the ulsch preprocessor
  int8_t pre_allocated_rb_table_index_ul;
777

778 779
  /// total allocated RBs
  int8_t total_allocated_rbs;
780

781
  /// pre-assigned MCS by the ulsch preprocessor
782
  uint8_t pre_assigned_mcs_ul;
783 784 785 786

  /// assigned MCS by the ulsch scheduler
  uint8_t assigned_mcs_ul;

787
  /// DL DAI
788
  uint8_t DAI;
789 790

  /// UL DAI
791
  uint8_t DAI_ul[10];
792 793

  /// UL Scheduling Request Received
794
  uint8_t ul_SR;
795

796
  ///Resource Block indication for each sub-band in MU-MIMO
797
  uint8_t rballoc_subband[8][50];
798 799 800

  // Logical channel info for link with RLC

801
  /// Last received UE BSR info for each logical channel group id
802
  uint8_t bsr_info[MAX_NUM_LCGID];
803

804 805 806
  /// LCGID mapping
  long lcgidmap[11];

807
  /// phr information
808
  int8_t phr_info;
809

810 811 812
  /// phr information
  int8_t phr_info_configured;

813
  ///dl buffer info
814
  uint32_t dl_buffer_info[MAX_NUM_LCID];
815
  /// total downlink buffer info
816
  uint32_t dl_buffer_total;
817
  /// total downlink pdus
818
  uint32_t dl_pdus_total;
819
  /// downlink pdus for each LCID
820
  uint32_t dl_pdus_in_buffer[MAX_NUM_LCID];
821
  /// creation time of the downlink buffer head for each LCID
822
  uint32_t dl_buffer_head_sdu_creation_time[MAX_NUM_LCID];
823
  /// maximum creation time of the downlink buffer head across all LCID
824
  uint32_t  dl_buffer_head_sdu_creation_time_max;
825
  /// a flag indicating that the downlink head SDU is segmented  
826
  uint8_t    dl_buffer_head_sdu_is_segmented[MAX_NUM_LCID];
827
  /// size of remaining size to send for the downlink head SDU
828
  uint32_t dl_buffer_head_sdu_remaining_size_to_send[MAX_NUM_LCID];
829

830
  /// total uplink buffer size 
831
  uint32_t ul_total_buffer;
832
  /// uplink buffer creation time for each LCID
833
  uint32_t ul_buffer_creation_time[MAX_NUM_LCGID];
834
  /// maximum uplink buffer creation time across all the LCIDs
835
  uint32_t ul_buffer_creation_time_max;
836
  /// uplink buffer size per LCID
837 838
  uint32_t ul_buffer_info[MAX_NUM_LCGID];

839 840 841
  /// UE tx power
  int32_t ue_tx_power;

kaltenbe's avatar
kaltenbe committed
842
  /// stores the frame where the last TPC was transmitted
knopp's avatar
knopp committed
843 844 845 846
  uint32_t pusch_tpc_tx_frame;
  uint32_t pusch_tpc_tx_subframe;
  uint32_t pucch_tpc_tx_frame;
  uint32_t pucch_tpc_tx_subframe;
kaltenbe's avatar
kaltenbe committed
847

848 849 850
#ifdef LOCALIZATION
  eNB_UE_estimated_distances distance;
#endif
851 852 853

#ifdef Rel14
  uint8_t rach_resource_type;
854
  uint16_t mpdcch_repetition_cnt;
855 856
  frame_t Msg2_frame;
#endif
857 858 859
  sub_frame_t Msg2_subframe;

  PhysicalConfigDedicated_t  *physicalConfigDedicated;
860

861 862
} UE_TEMPLATE;

863
/*! \brief scheduling control information set through an API (not used)*/
864
typedef struct {
865
  ///UL transmission bandwidth in RBs
866
  uint8_t ul_bandwidth[MAX_NUM_LCID];
867
  ///DL transmission bandwidth in RBs
868
  uint8_t dl_bandwidth[MAX_NUM_LCID];
869

870 871
  //To do GBR bearer
  uint8_t min_ul_bandwidth[MAX_NUM_LCID];
872

873
  uint8_t min_dl_bandwidth[MAX_NUM_LCID];
874

875
  ///aggregated bit rate of non-gbr bearer per UE
876
  uint64_t  ue_AggregatedMaximumBitrateDL;
877
  ///aggregated bit rate of non-gbr bearer per UE
878
  uint64_t  ue_AggregatedMaximumBitrateUL;
879
  ///CQI scheduling interval in subframes.
880
  uint16_t cqiSchedInterval;
881
  ///Contention resolution timer used during random access
882
  uint8_t mac_ContentionResolutionTimer;
883

884
  uint16_t max_allowed_rbs[MAX_NUM_LCID];
885

886
  uint8_t max_mcs[MAX_NUM_LCID];
887

888
  uint16_t priority[MAX_NUM_LCID];
889

890
  // resource scheduling information
891 892 893 894 895 896 897
  
  /// Current DL harq round per harq_pid on each CC
  uint8_t       round[MAX_NUM_CCs][10];
  /// Current Active TBs per harq_pid on each CC
  uint8_t       tbcnt[MAX_NUM_CCs][10];
  /// Current UL harq round per harq_pid on each CC
  uint8_t       round_UL[MAX_NUM_CCs][8];
898 899 900
  uint8_t       dl_pow_off[MAX_NUM_CCs];
  uint16_t      pre_nb_available_rbs[MAX_NUM_CCs];
  unsigned char rballoc_sub_UE[MAX_NUM_CCs][N_RBG_MAX];
901
  uint16_t      ta_timer;
902
  int16_t       ta_update;
903
  uint16_t      ul_consecutive_errors;
904
  int32_t       context_active_timer;
905
  int32_t       cqi_req_timer;
906
  int32_t       ul_inactivity_timer;
907
  int32_t       ul_failure_timer; 
908
  int32_t       ul_scheduled;
909
  int32_t       ra_pdcch_order_sent;
910
  int32_t       ul_out_of_sync;
911
  int32_t       phr_received;
912 913
  uint8_t       periodic_ri_received[NFAPI_CC_MAX];
  uint8_t       aperiodic_ri_received[NFAPI_CC_MAX];
914
  uint8_t       pucch1_cqi_update[NFAPI_CC_MAX];
915
  uint8_t       pucch1_snr[NFAPI_CC_MAX];
916
  uint8_t       pucch2_cqi_update[NFAPI_CC_MAX];
917
  uint8_t       pucch2_snr[NFAPI_CC_MAX];
918
  uint8_t       pucch3_cqi_update[NFAPI_CC_MAX];
919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
  uint8_t       pucch3_snr[NFAPI_CC_MAX];
  uint8_t       pusch_snr[NFAPI_CC_MAX];
  uint16_t      feedback_cnt[NFAPI_CC_MAX];
  uint16_t      timing_advance;
  uint16_t      timing_advance_r9;
  uint8_t       periodic_wideband_cqi[NFAPI_CC_MAX];
  uint8_t       periodic_wideband_spatial_diffcqi[NFAPI_CC_MAX];
  uint8_t       periodic_wideband_pmi[NFAPI_CC_MAX];
  uint8_t       periodic_subband_cqi[NFAPI_CC_MAX][16];
  uint8_t       periodic_subband_spatial_diffcqi[NFAPI_CC_MAX][16];
  uint8_t       aperiodic_subband_cqi0[NFAPI_CC_MAX][25];
  uint8_t       aperiodic_subband_pmi[NFAPI_CC_MAX][25];
  uint8_t       aperiodic_subband_diffcqi0[NFAPI_CC_MAX][25];
  uint8_t       aperiodic_subband_cqi1[NFAPI_CC_MAX][25];
  uint8_t       aperiodic_subband_diffcqi1[NFAPI_CC_MAX][25];
  uint8_t       aperiodic_wideband_cqi0[NFAPI_CC_MAX];
  uint8_t       aperiodic_wideband_pmi[NFAPI_CC_MAX];
  uint8_t       aperiodic_wideband_cqi1[NFAPI_CC_MAX];
  uint8_t       aperiodic_wideband_pmi1[NFAPI_CC_MAX];
Cedric Roux's avatar
Cedric Roux committed
938
  uint8_t       dl_cqi[NFAPI_CC_MAX];
939
} UE_sched_ctrl;
940
/*! \brief eNB template for the Random access information */
941 942
typedef struct {
  /// Flag to indicate this process is active
gauthier's avatar
gauthier committed
943
  boolean_t RA_active;
944
  /// Size of DCI for RA-Response (bytes)
945
  uint8_t RA_dci_size_bytes1;
946
  /// Size of DCI for RA-Response (bits)
947
  uint8_t RA_dci_size_bits1;
948
  /// Actual DCI to transmit for RA-Response
949
  uint8_t RA_alloc_pdu1[(MAX_DCI_SIZE_BITS>>3)+1];
950
  /// DCI format for RA-Response (should be 1A)
951
  uint8_t RA_dci_fmt1;
952
  /// Size of DCI for Msg4/ContRes (bytes)
953
  uint8_t RA_dci_size_bytes2;
954
  /// Size of DCI for Msg4/ContRes (bits)
955
  uint8_t RA_dci_size_bits2;
956
  /// Actual DCI to transmit for Msg4/ContRes
957
  uint8_t RA_alloc_pdu2[(MAX_DCI_SIZE_BITS>>3)+1];
958
  /// DCI format for Msg4/ContRes (should be 1A)
959
  uint8_t RA_dci_fmt2;
960
  /// Flag to indicate the eNB should generate RAR.  This is triggered by detection of PRACH
961
  uint8_t generate_rar;
962
  /// Subframe where preamble was received
963
  uint8_t preamble_subframe;
964 965 966
  /// Subframe where Msg2 is to be sent
  uint8_t Msg2_subframe;
  /// Frame where Msg2 is to be sent
967
  frame_t Msg2_frame;
968
  /// Subframe where Msg3 is to be sent
969
  sub_frame_t Msg3_subframe;
970
  /// Frame where Msg3 is to be sent
971
  frame_t Msg3_frame;
972
  /// Subframe where Msg4 is to be sent
973
  sub_frame_t Msg4_subframe;
974
  /// Frame where Msg4 is to be sent
975
  frame_t Msg4_frame;
976
  /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC.  This is triggered by first ULSCH reception at eNB for new user.
977
  uint8_t generate_Msg4;
978
  /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3.
979
  uint8_t wait_ack_Msg4;
980 981
  /// harq_pid used for Msg4 transmission
  uint8_t harq_pid;
982
  /// UE RNTI allocated during RAR
gauthier's avatar
gauthier committed
983
  rnti_t rnti;
984
  /// RA RNTI allocated from received PRACH
985
  uint16_t RA_rnti;
986
  /// Received preamble_index
987
  uint8_t preamble_index;
988
  /// Received UE Contention Resolution Identifier
989
  uint8_t cont_res_id[6];
990
  /// Timing offset indicated by PHY
991
  int16_t timing_offset;
992
  /// Timeout for RRC connection
993
  int16_t RRC_timer;
994 995 996 997 998 999
  /// Msg3 first RB
  uint8_t msg3_first_rb;
  /// Msg3 number of RB
  uint8_t msg3_nb_rb;
  /// Msg3 MCS
  uint8_t msg3_mcs;
1000 1001 1002 1003 1004 1005
  /// Msg3 TPC command
  uint8_t msg3_TPC;
  /// Msg3 ULdelay command
  uint8_t msg3_ULdelay;
  /// Msg3 cqireq command
  uint8_t msg3_cqireq;
1006 1007
  /// Round of Msg3 HARQ
  uint8_t msg3_round;
1008
  /// TBS used for Msg4
1009
  int msg4_TBsize;
1010
  /// MCS used for Msg4
1011
  int msg4_mcs;
1012 1013 1014 1015 1016 1017 1018
#ifdef Rel14
  uint8_t rach_resource_type;
  uint8_t msg2_mpdcch_repetition_cnt;
  uint8_t msg4_mpdcch_repetition_cnt;
  uint8_t msg2_narrowband;
  uint8_t msg34_narrowband;
#endif
1019 1020 1021
} RA_TEMPLATE;


1022
/*! \brief subband bitmap confguration (for ALU icic algo purpose), in test phase */
1023
typedef struct {
1024
  uint8_t sbmap[13]; 
1025 1026 1027 1028 1029
  uint8_t periodicity;
  uint8_t first_subframe;
  uint8_t sb_size;
  uint8_t nb_active_sb;
} SBMAP_CONF;
1030
/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ 
1031
typedef struct {
1032
  /// Dedicated information for UEs
1033
  struct PhysicalConfigDedicated  *physicalConfigDedicated[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
1034
  /// DLSCH pdu 
1035 1036 1037 1038 1039
  DLSCH_PDU DLSCH_pdu[MAX_NUM_CCs][2][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection parameters for UEs
  UE_TEMPLATE UE_template[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection for RA processes
  int pCC_id[NUMBER_OF_UE_MAX];
1040
  /// sorted downlink component carrier for the scheduler 
1041
  int ordered_CCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
1042
  /// number of downlink active component carrier 
1043
  int numactiveCCs[NUMBER_OF_UE_MAX];
1044
  /// sorted uplink component carrier for the scheduler 
1045
  int ordered_ULCCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
1046
  /// number of uplink active component carrier 
1047
  int numactiveULCCs[NUMBER_OF_UE_MAX];
1048
  /// number of downlink active component carrier 
1049
  uint8_t dl_CC_bitmap[NUMBER_OF_UE_MAX];
1050
  /// eNB to UE statistics
1051
  eNB_UE_STATS eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
1052
  /// scheduling control info
1053 1054
  UE_sched_ctrl UE_sched_ctrl[NUMBER_OF_UE_MAX];
  int next[NUMBER_OF_UE_MAX];
1055
  int head;
1056 1057
  int next_ul[NUMBER_OF_UE_MAX];
  int head_ul;
1058 1059 1060 1061
  int avail;
  int num_UEs;
  boolean_t active[NUMBER_OF_UE_MAX];
} UE_list_t;
1062

1063
/*! \brief eNB common channels */ 
1064
typedef struct {
1065 1066 1067 1068 1069 1070
  int                              physCellId;
  int                              p_eNB;
  int                              Ncp;
  int                              eutra_band;
  uint32_t                         dl_CarrierFreq;
  BCCH_BCH_Message_t