1. 07 Aug, 2017 1 commit
    • Cedric Roux's avatar
      fix vcd · 309ca066
      Cedric Roux authored
      several problems were present:
      - there was no comma after "ue0_trx_write_ns_missing" in the array
        eurecomVariablesNames;
        comma was put, and also commas for the last element in the array,
        which doesn't hurt and will prevent future problems
      - bad order of values in eurecomVariablesNames, which
        was different from the enum vcd_signal_dump_variables;
        order was checked and fixed
      - strange/wrong use of VCD_SIGNAL_DUMPER_MODULE_END/LAST;
        the whole logic was removed/simplified
      309ca066
  2. 03 Aug, 2017 6 commits
    • Cedric Roux's avatar
      Merge branch 'develop_integration_w30' into 'develop' · f7466b0e
      Cedric Roux authored
      Summary of changes:
      - UE: new thread idx
      - UE: Pdcch optim
      - UE: slot0 slot1 parallelization
      - bugfixes for RLC AM (see gitlab issue 250)
      - fix bug "unknown UE_id for rnti"
      
      Note: due to the new UE threading architecture,
      oaisim and the phy simulators may not work properly
      anymore. Adaptation in the code has been done, automatic
      tests seem to pass, but it may not be enough.
      
      See merge request !215
      f7466b0e
    • Cedric Roux's avatar
      remove gcc warning when compiling oaisim · 2fbb2678
      Cedric Roux authored
      2fbb2678
    • Cedric Roux's avatar
      fix oaisim (ue structures changed) · ebc8cbf4
      Cedric Roux authored
      ebc8cbf4
    • Cedric Roux's avatar
      remove compilation warnings · 8633d6c2
      Cedric Roux authored
      8633d6c2
    • Cedric Roux's avatar
      bugfix for phy simulators (not sure if enough) · 9e4f700a
      Cedric Roux authored
      With the new threading architecture of the UE dlsim
      (and others) does not work properly anymore.
      
      When looking at the scope, you see a difference
      in PDSCH LLR display. The end is always 0 where
      in the current develop branch (tag 2017.w25) it's not.
      
      This commit attempts to fix it.
      
      We still don't have the same behavior as in 2017.w25.
      I disabled channel simulation (so that UE RX = eNB TX)
      and I have one error where in 2017.w25 I have zero.
      For example, here comes the output of a run of "./dlsim":
      
      **********************SNR = 0.000000 dB (tx_lev 51.000000)**************************
      Errors (1(0)/1000 0/1 0/0 0/0), Pe = (1.000000e-03,0.000000e+00,-nan,-nan), dci_errors 0/1001, Pe = 0.000000e+00 => effective rate 99.900100, normalized delay 0.001472 (1.001000)
      
      And in 2017.w25 we have (with the same hack to disable
      channel simulation):
      
      **********************SNR = 0.000000 dB (tx_lev 51.000000)**************************
      Errors (0(0)/1000 0/0 0/0 0/0), Pe = (0.000000e+00,-nan,-nan,-nan), dci_errors 0/1000, Pe = 0.000000e+00 => effective rate 100.000000, normalized delay 0.001471 (1.000000)
      
      There may be a problem somewhere. Or there was one before and we should
      have had one error and the new UE architecture fixed things and now
      it's as it has to be. Hard to say at this point...
      
      When looking at the scope we quickly see some zeros for the PDSCH
      LLR, at the begining this time, not at the end. This is just when
      the GUI appears and then all is fine, so this seems to be for the
      first frame only. In 2017.w25 this does not happen.
      9e4f700a
    • Cedric Roux's avatar
      more fix for dlsim_tm7 · 2ed9a48d
      Cedric Roux authored
      2ed9a48d
  3. 01 Aug, 2017 2 commits
  4. 31 Jul, 2017 4 commits
    • Cedric Roux's avatar
      bugfix: fix sync for oaisim · 030a3452
      Cedric Roux authored
      With the current implementation of oaisim
      (rxdata and channel simulation), we cannot
      call trx_read_func on a dummy buffer. The
      code will actually modify the rxdata buffers
      of the UE.
      
      This is has to be rewritten properly. In the
      meantime, let's introduce a simple hack. The
      idea of the read at this point is to wait for
      the synch to finish and not lose samples from
      the hardware in the real UE. In the simulator,
      as it is today, we can simply sleep until the
      synch code has finished its work.
      030a3452
    • Cedric Roux's avatar
      integration fix: let oaisim work again · 3ed32a77
      Cedric Roux authored
      In case of oaisim, dl_phy_sync_success has to be called
      by initial_sync, as it used to be.
      
      We introduce an #if OAISIM, this is not elegant, but will
      do it for the moment.
      3ed32a77
    • tct-labo4's avatar
      fix dlsim · 4c2c1a36
      tct-labo4 authored
      4c2c1a36
    • tct-labo4's avatar
  5. 28 Jul, 2017 2 commits
  6. 27 Jul, 2017 1 commit
    • Cedric Roux's avatar
      bugfix: fix bug "Unknown UE_id for rnti" · 8d5901c8
      Cedric Roux authored
      This bug happens when we detect uplink failure for one UE.
      In this case, a DCI format 1A is sent to the UE to ask it
      to do random acces.
      
      The way this DCI is generated was not compatible with how
      the software is organized. It was expected that the DCI are
      added (with add_ue_spec_dci and add_common_dci) in a very
      specific order: first all DCIs in common space are added
      (with add_common_dci) then all DCIs in UE specific space
      are added (with add_ue_spec_dci).
      
      The problem was that the DCI format 1A DCI sent to the UE
      for it to do random access is added (with add_ue_spec_dci)
      before the DCIs in common space.
      
      That totally messed up the logic in add_common_dci and
      add_ue_spec_dci.
      
      The solution is to get rid of Num_common_dci and Num_ue_spec_dci,
      replace those two counters by only one (Num_dci) and add
      "search_space" in the dci_alloc structure to be used later by
      the function "allocate_CCEs" when calling "get_nCCE_offset".
      
      The software had to be adapted to the new var...
      8d5901c8
  7. 26 Jul, 2017 2 commits
  8. 20 Jul, 2017 1 commit
  9. 17 Jul, 2017 6 commits
  10. 06 Jul, 2017 1 commit
  11. 04 Jul, 2017 1 commit
  12. 29 Jun, 2017 2 commits
  13. 28 Jun, 2017 1 commit
  14. 27 Jun, 2017 2 commits
  15. 26 Jun, 2017 2 commits
  16. 23 Jun, 2017 6 commits