diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt
index 179be1fc648dc0ce6d5bb3c4b6ed37fb7f522a92..308e1f5447ca3c74601e3d8c9b13b9d64406fa0b 100644
--- a/cmake_targets/CMakeLists.txt
+++ b/cmake_targets/CMakeLists.txt
@@ -1205,7 +1205,6 @@ set(PHY_SRC_COMMON
${OPENAIR1_DIR}/PHY/LTE_REFSIG/lte_ul_ref.c
${OPENAIR1_DIR}/PHY/CODING/lte_segmentation.c
${OPENAIR1_DIR}/PHY/CODING/nr_segmentation.c
- ${OPENAIR1_DIR}/PHY/CODING/nr_compute_tbs.c
${OPENAIR1_DIR}/PHY/CODING/nr_rate_matching.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c
@@ -1646,6 +1645,7 @@ set (MAC_NR_SRC_UE
${NR_UE_MAC_DIR}/mac_vars.c
${NR_UE_MAC_DIR}/main_ue_nr.c
${NR_UE_MAC_DIR}/nr_ue_procedures.c
+ ${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c
)
set (ENB_APP_SRC
@@ -1700,7 +1700,7 @@ add_dependencies(L2_UE rrc_flag s1ap_flag x2_flag)
add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} )
-add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_mac_common.c )
+add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c)
include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE")
include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE")
diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c
index 7d7c887a3436c3c5ca7fd5deef30603e8ced9084..cdbf59cd7654e2c0f0d97f1f9678e220762925a5 100644
--- a/common/utils/nr/nr_common.c
+++ b/common/utils/nr/nr_common.c
@@ -37,8 +37,8 @@ int NRRIV2BW(int locationAndBandwidth,int N_RB) {
int tmp = locationAndBandwidth/N_RB;
int tmp2 = locationAndBandwidth%N_RB;
- if (tmp <= (N_RB-tmp2+1)) return(tmp);
- else return(N_RB-tmp);
+ if (tmp <= ((N_RB>>1)-tmp2+1)) return(tmp+1);
+ else return(N_RB+1-tmp);
}
@@ -46,15 +46,14 @@ int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB) {
int tmp = locationAndBandwidth/N_RB;
int tmp2 = locationAndBandwidth%N_RB;
- if (tmp <= (N_RB-tmp2+1)) return(tmp2);
- else return(N_RB-tmp2);
+ if (tmp <= ((N_RB>>1)-tmp2+1)) return(tmp2);
+ else return(N_RB-1-tmp2);
}
int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) {
- if (NPRB < 138)
- return(BWPsize*(NPRB-1)+RBstart);
- else
- return(BWPsize*(BWPsize+1-NPRB) + (BWPsize-1-RBstart));
+ AssertFatal(NPRB>0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d)\n",NPRB,RBstart);
+ if (NPRB <= 1+(BWPsize>>1)) return(BWPsize*(NPRB-1)+RBstart);
+ else return(BWPsize*(BWPsize+1-NPRB) + (BWPsize-1-RBstart));
}
int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) {
diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h
index 34b0434fd7b283681e89a6473007b6a573a74be0..979cf863436a91430b0e1e562c71aa9c84f24965 100644
--- a/common/utils/nr/nr_common.h
+++ b/common/utils/nr/nr_common.h
@@ -45,3 +45,21 @@ uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
int get_subband_size(int NPRB,int size);
void SLIV2SL(int SLIV,int *S,int *L);
+
+
+#define CEILIDIV(a,b) ((a+b-1)/b)
+#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1))
+
+#define cmax(a,b) ((a>b) ? (a) : (b))
+#define cmax3(a,b,c) ((cmax(a,b)>c) ? (cmax(a,b)) : (c))
+#define cmin(a,b) ((a<b) ? (a) : (b))
+
+#ifdef __cplusplus
+#ifdef min
+#undef min
+#undef max
+#endif
+#else
+#define max(a,b) cmax(a,b)
+#define min(a,b) cmin(a,b)
+#endif
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
index babcc6404f284804c8efa56f06ba84601215bb30..cbcd26c3e352ba2c9679dbbf4c2f55319577a3ab 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
@@ -8,6 +8,9 @@
#define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16
#define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16
#define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64
+// Constants Defined in 38.213
+#define FAPI_NR_MAX_CORESET_PER_BWP 3
+#define FAPI_NR_MAX_SS_PER_CORESET 10
/// RX_IND
@@ -41,8 +44,8 @@
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
-#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
-#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
+#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
+#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
index c244c61968d2c4159a64f9deaeb664867e963a51..c5b7a0a5ea1a6775f4b26597abdd79ec656db567 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
@@ -31,77 +31,7 @@
typedef signed char int8_t;
*/
-typedef struct {
- uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
- uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
- uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
- uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
- uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
- uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
- uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
- uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
- uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
- uint8_t short_messages ; // 9 SHORT_MESSAGES:
- uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- // (NOTE 1) If DCI format 0_0 is monitored in common search space
- // and if the number of information bits in the DCI format 0_0 prior to padding
- // is larger than the payload size of the DCI format 1_0 monitored in common search space
- // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
- // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
- uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- // where I the number of entries in the higher layer parameter pusch-AllocationList
- uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
- uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
- uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
- uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- uint8_t tb1_mcs ; // 18 TB1_MCS:
- uint8_t tb1_ndi ; // 19 TB1_NDI:
- uint8_t tb1_rv ; // 20 TB1_RV:
- uint8_t tb2_mcs ; // 21 TB2_MCS:
- uint8_t tb2_ndi ; // 22 TB2_NDI:
- uint8_t tb2_rv ; // 23 TB2_RV:
- uint8_t mcs ; // 24 MCS:
- uint8_t ndi ; // 25 NDI:
- uint8_t rv ; // 26 RV:
- uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
- uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
- // 0 otherwise
- uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
- uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
- uint8_t tb_scaling ; // 31 TB_SCALING:
- uint8_t tpc_pusch ; // 32 TPC_PUSCH:
- uint8_t tpc_pucch ; // 33 TPC_PUCCH:
- uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
- uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
- uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
- uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
- uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
- uint8_t srs_request ; // 40 SRS_REQUEST:
- uint8_t tpc_cmd ; // 41 TPC_CMD:
- uint8_t csi_request ; // 42 CSI_REQUEST:
- uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
- uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
- uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
- uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
- uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
- // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
- uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
- uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
- // and if the number of information bits in the DCI format 0_0 prior to padding
- // is less than the payload size of the DCI format 1_0 monitored in common search space
- // zeros shall be appended to the DCI format 0_0
- // until the payload size equals that of the DCI format 1_0
- uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
- uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
- uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
- uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
- uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
- uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
-} fapi_nr_dci_pdu_rel15_t;
+
@@ -120,16 +50,14 @@ typedef struct {
typedef struct {
/// frequency_domain_resource;
- //uint32_t rb_start;
- //uint32_t rb_end;
- uint64_t frequency_domain_resource;
- uint16_t rb_offset;
-
+ uint8_t frequency_domain_resource[6];
+ uint8_t StartSymbolIndex;
uint8_t duration;
- uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
- uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
- uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
- uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
+ uint8_t CceRegMappingType; // interleaved or noninterleaved
+ uint8_t RegBundleSize; // valid if CCE to REG mapping type is interleaved type
+ uint8_t InterleaverSize; // valid if CCE to REG mapping type is interleaved type
+ uint8_t ShiftIndex; // valid if CCE to REG mapping type is interleaved type
+ uint8_t CoreSetType;
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
@@ -154,13 +82,16 @@ typedef struct {
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
- fapi_nr_dci_pdu_rel15_t dci;
+ uint8_t payloadSize;
+ uint8_t payloadBits[16];
+ //fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t;
///
typedef struct {
- uint32_t sfn_slot;
+ uint16_t SFN;
+ uint8_t slot;
uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t;
@@ -381,16 +312,15 @@ typedef struct {
typedef struct {
uint16_t rnti;
-
+ uint16_t BWPSize;
+ uint16_t BWPStart;
+ uint8_t SubcarrierSpacing;
fapi_nr_coreset_t coreset;
- uint16_t N_RB_BWP;
- uint32_t duration;
- uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
- uint16_t monitoring_symbols_within_slot;
- // DCI foramt-specific
- uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
- uint8_t format_2_3_monitorying_periodicity;
- uint8_t format_2_3_number_of_candidates;
+ uint8_t number_of_candidates;
+ uint16_t CCE[64];
+ uint8_t L[64];
+ uint8_t dci_length;
+ uint8_t dci_format;
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
@@ -403,12 +333,16 @@ typedef struct{
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
- uint8_t bandwidth_part_ind;
+ uint16_t BWPSize;
+ uint16_t BWPStart;
+ uint8_t SubcarrierSpacing;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
+ uint16_t dlDmrsSymbPos;
+ uint8_t dmrsConfigType;
uint8_t prb_bundling_size_ind;
uint8_t rate_matching_ind;
uint8_t zp_csi_rs_trigger;
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
index b94b000fb1d06000e8896f2f1cacf0f03a05115d..6e01a05d0f959e80903db894b90e9b7e7028e560 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
@@ -188,7 +188,8 @@ void nr_polar_print_polarParams(t_nrPolar_params *polarParams);
t_nrPolar_params *nr_polar_params (int8_t messageType,
uint16_t messageLength,
uint8_t aggregation_level,
- int decoder_flag);
+ int decoder_flag,
+ t_nrPolar_params **polarList_ext);
uint16_t nr_polar_aggregation_prime (uint8_t aggregation_level);
diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c
index c7cca785818c059935f84744d1e98e36f21a601d..f6a06b3f7fc830ff77084540ded4f556ccf0426b 100644
--- a/openair1/PHY/CODING/nr_polar_init.c
+++ b/openair1/PHY/CODING/nr_polar_init.c
@@ -185,10 +185,12 @@ void nr_polar_print_polarParams(t_nrPolar_params *polarParams) {
t_nrPolar_params *nr_polar_params (int8_t messageType,
uint16_t messageLength,
uint8_t aggregation_level,
- int decoding_flag) {
+ int decoding_flag,
+ t_nrPolar_params **polarList_ext) {
static t_nrPolar_params *polarList = NULL;
- nr_polar_init(&polarList, messageType,messageLength,aggregation_level,decoding_flag);
- t_nrPolar_params *polarParams=polarList;
+ nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList,
+ messageType,messageLength,aggregation_level,decoding_flag);
+ t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList;
const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level);
while (polarParams != NULL) {
diff --git a/openair1/PHY/CODING/nr_segmentation.c b/openair1/PHY/CODING/nr_segmentation.c
index 90586e24d4ab437b56816d08b57fa9a521431aac..462cdee1fcb28ae8f6be054faac831692c5688b4 100644
--- a/openair1/PHY/CODING/nr_segmentation.c
+++ b/openair1/PHY/CODING/nr_segmentation.c
@@ -63,7 +63,7 @@ int32_t nr_segmentation(unsigned char *input_buffer,
#endif
}
- if ((*C)>MAX_NUM_DLSCH_SEGMENTS) {
+ if ((*C)>MAX_NUM_NR_DLSCH_SEGMENTS) {
LOG_E(PHY,"nr_segmentation.c: too many segments %d, B %d, L %d, Bprime %d\n",*C,B,L,Bprime);
return(-1);
}
diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c
index 91af4e18865143db456ee17813c2735dbf9af9e4..28fe9b8f827c1b97d95a57a8347b2b1169c91a1f 100644
--- a/openair1/PHY/INIT/nr_init.c
+++ b/openair1/PHY/INIT/nr_init.c
@@ -86,14 +86,12 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/
int i;
- int P=cfg->carrier_config.num_tx_ant.value;
+ int Ptx=cfg->carrier_config.num_tx_ant.value;
+ int Prx=cfg->carrier_config.num_rx_ant.value;
- AssertFatal(P>0 && P<9,"P %d is not supported\n",P);
+ AssertFatal(Ptx>0 && Ptx<9,"Ptx %d is not supported\n",Ptx);
+ AssertFatal(Prx>0 && Prx<9,"Prx %d is not supported\n",Prx);
LOG_I(PHY,"[gNB %d] %s() About to wait for gNB to be configured\n", gNB->Mod_id, __FUNCTION__);
- gNB->total_dlsch_bitrate = 0;
- gNB->total_transmitted_bits = 0;
- gNB->total_system_throughput = 0;
- gNB->check_for_MUMIMO_transmissions=0;
while(gNB->configured == 0) usleep(10000);
@@ -157,21 +155,24 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
/// Transport init necessary for NR synchro
init_nr_transport(gNB);
- gNB->first_run_I0_measurements =
- 1; ///This flag used to be static. With multiple gNBs this does no longer work, hence we put it in the structure. However it has to be initialized with 1, which is performed here.
- common_vars->rxdata = (int32_t **)malloc16(P*sizeof(int32_t*));
- common_vars->txdataF = (int32_t **)malloc16(P*sizeof(int32_t*));
- common_vars->rxdataF = (int32_t **)malloc16(P*sizeof(int32_t*));
+ gNB->first_run_I0_measurements = 1;
- for (i=0;i<P;i++){
- common_vars->txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP
- common_vars->rxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t));
- common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t));
+ common_vars->rxdata = (int32_t **)malloc16(Prx*sizeof(int32_t*));
+ common_vars->txdataF = (int32_t **)malloc16(Ptx*sizeof(int32_t*));
+ common_vars->rxdataF = (int32_t **)malloc16(Prx*sizeof(int32_t*));
+ for (i=0;i<Ptx;i++){
+ common_vars->txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP
LOG_D(PHY,"[INIT] common_vars->txdataF[%d] = %p (%lu bytes)\n",
- i,common_vars->txdataF[i],
- fp->samples_per_frame_wCP*sizeof(int32_t));
+ i,common_vars->txdataF[i],
+ fp->samples_per_frame_wCP*sizeof(int32_t));
+
}
+ for (i=0;i<Prx;i++){
+ common_vars->rxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t));
+ common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t));
+ }
+
// Channel estimates for SRS
/*
@@ -202,22 +203,24 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
+ printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
for (int ULSCH_id=0; ULSCH_id<NUMBER_OF_NR_ULSCH_MAX; ULSCH_id++) {
-
+ printf("ULSCH_id %d : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) );
- pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_mag0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
- pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t*) );
-
- for (i=0; i<fp->nb_antennas_rx; i++) {
+ pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_mag0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
+ pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear(Prx*sizeof(int32_t*) );
+
+ printf("ULSCH_id %d (before rx antenna alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
+ for (i=0; i<Prx; i++) {
pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
@@ -230,14 +233,15 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) );
}
-
- pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear
+ printf("ULSCH_id %d (before llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
+ pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear
+ printf("ULSCH_id %d (after llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
} //ulsch_id
/*
for (ulsch_id=0; ulsch_id<NUMBER_OF_UE_MAX; ulsch_id++)
gNB->UE_stats_ptr[ulsch_id] = &gNB->UE_stats[ulsch_id];
*/
- gNB->pdsch_config_dedicated->p_a = dB0; //defaul value until overwritten by RRCConnectionReconfiguration
+ printf("After ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
return (0);
}
@@ -249,9 +253,9 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
/*LTE_eNB_SRS *const srs_vars = gNB->srs_vars;
LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/
uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs;
- int P=gNB->gNB_config.carrier_config.num_tx_ant.value;
+ int Ptx=gNB->gNB_config.carrier_config.num_tx_ant.value;
- for (int i = 0; i < P; i++) {
+ for (int i = 0; i < Ptx; i++) {
free_and_zero(common_vars->txdataF[i]);
/* rxdataF[i] is not allocated -> don't free */
}
@@ -440,14 +444,7 @@ void init_nr_transport(PHY_VARS_gNB *gNB) {
for (j=0; j<2; j++) {
gNB->dlsch[i][j] = new_gNB_dlsch(fp,1,16,NSOFT,0,grid_size);
-
- if (!gNB->dlsch[i][j]) {
- LOG_E(PHY,"Can't get gNB dlsch structures for UE %d \n", i);
- exit(-1);
- }/* else {
- gNB->dlsch[i][j]->rnti=0;
- LOG_D(PHY,"dlsch[%d][%d] => %p rnti:%d\n",i,j,gNB->dlsch[i][j], gNB->dlsch[i][j]->rnti);
- }*/
+ AssertFatal(gNB->dlsch[i][j]!=NULL,"Can't initialize dlsch %d \n", i);
}
}
diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c
index 121af20cdd52fd50aed03c46290edfa95bc4700a..a05f8cbc986931d829e4285c1bef64aef7402a68 100644
--- a/openair1/PHY/INIT/nr_init_ru.c
+++ b/openair1/PHY/INIT/nr_init_ru.c
@@ -82,7 +82,7 @@ int nr_phy_init_RU(RU_t *ru) {
// allocate precoding input buffers (TX)
- ru->common.txdataF = (int32_t **)malloc16(ru->nb_tx**sizeof(int32_t*));
+ ru->common.txdataF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*));
for(i=0; i< ru->nb_tx; ++i) ru->common.txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP
// allocate IFFT input buffers (TX)
@@ -126,7 +126,7 @@ int nr_phy_init_RU(RU_t *ru) {
int l_ind = 0;
for (i=0; i<RC.nb_nr_L1_inst; i++) {
- for (p=0;p<nb_logical_antennas;p++) {
+ for (p=0;p<ru->nb_log_antennas;p++) {
if ((fp->L_ssb >> p) & 0x01) {
ru->beam_weights[i][p] = (int32_t **)malloc16_clear(ru->nb_tx*sizeof(int32_t*));
for (j=0; j<ru->nb_tx; j++) {
diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c
index 57bca9e2ec1e259e1b82699ad1951bb57b0a6d29..5c8fce3c3862641ecdd4dc39315e5cd542e0e984 100644
--- a/openair1/PHY/MODULATION/nr_modulation.c
+++ b/openair1/PHY/MODULATION/nr_modulation.c
@@ -51,9 +51,10 @@ void nr_modulation(uint32_t *in,
}
void nr_layer_mapping(int16_t **mod_symbs,
- uint8_t n_layers,
- uint16_t n_symbs,
- int16_t **tx_layers) {
+ uint8_t n_layers,
+ uint16_t n_symbs,
+ int16_t **tx_layers) {
+ LOG_D(PHY,"Doing layer mapping for %d layers, %d symbols\n",n_layers,n_symbs);
switch (n_layers) {
diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c
index 36d8eb81a800841abc0be12853b15e34b876df6a..7057adef2130aa7ac14cfd07f153d69b00536fc1 100644
--- a/openair1/PHY/NR_REFSIG/nr_gold.c
+++ b/openair1/PHY/NR_REFSIG/nr_gold.c
@@ -65,7 +65,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
- x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1));
+ x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1)) + (Nid<<1);
for (uint32_t n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) {
pdcch_dmrs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
@@ -91,6 +91,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid));
+ LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",slot,symb,x2);
for (uint32_t n=0; n<NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD; n++) {
pdsch_dmrs[slot][symb][0][n] = lte_gold_generic(&x1, &x2, reset);
reset = 0;
diff --git a/openair1/PHY/NR_REFSIG/nr_gold_ue.c b/openair1/PHY/NR_REFSIG/nr_gold_ue.c
index 9793899dd43817261920ff8131b445c6a44e1a33..39ab13b1f1e7384089e7c410a1870da743b0c119 100644
--- a/openair1/PHY/NR_REFSIG/nr_gold_ue.c
+++ b/openair1/PHY/NR_REFSIG/nr_gold_ue.c
@@ -100,7 +100,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
ue->nr_gold_pdcch[0][ns][l][n] = x1^x2;
- //printf("n=%d : c %x\n",n,x1^x2);
+ // if (ns==1 && l==0) printf("n=%d : c %x\n",n,x1^x2);
}
}
}
@@ -133,7 +133,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
x2tmp0 = ((14*ns+(lbar+l)+1)*((nid<<1)+1))<<17;
x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit
-
+ LOG_D(PHY,"UE DMRS slot %d, symb %d, lbar %d, x2 %x, nscid %d\n",ns,l,lbar,x2,nscid);
//printf("ns %d gold pdsch x2 %d\n",ns,x2);
x1 = 1+ (1<<31);
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c
index bbc0cf46137333df99b66375ea7130fb791b842e..c661fbd292d6971d67d69ae7b967367297f2fd5e 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c
@@ -137,7 +137,6 @@ void nr_pdcch_scrambling(uint32_t *in,
uint32_t x1, x2, s=0;
reset = 1;
x2 = (n_RNTI<<16) + Nid;
-
for (int i=0; i<size; i++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
@@ -150,10 +149,10 @@ void nr_pdcch_scrambling(uint32_t *in,
}
(*out) ^= ((((*in)>>(i&0x1f))&1) ^ ((s>>(i&0x1f))&1))<<(i&0x1f);
- //printf("nr_pdcch_scrambling: in %d seq 0x%08x => out %d\n",((*in)>>(i&0x1f))&1,s,((*out)>>(i&0x1f))&1);
}
}
+
uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu,
uint32_t **gold_pdcch_dmrs,
@@ -165,9 +164,6 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
uint16_t cset_start_sc;
uint8_t cset_start_symb, cset_nsymb;
int k,l,k_prime,dci_idx, dmrs_idx;
- nr_cce_t cce;
- nr_reg_t reg;
- nr_reg_t reg_mapping_list[NR_MAX_PDCCH_AGG_LEVEL*NR_NB_REG_PER_CCE];
/*First iteration: single DCI*/
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15;
@@ -202,13 +198,15 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex;
cset_nsymb = pdcch_pdu_rel15->DurationSymbols;
dci_idx = 0;
- LOG_D(PHY, "Coreset rb_offset %d\n",rb_offset);
+ LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb);
LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
// DMRS length is per OFDM symbol
- uint32_t dmrs_length = (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS)?
+ AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED,
+ "Interleaved CCE REG MAPPING not supported\n");
+ uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
(n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
- LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d\n", dmrs_length, encoded_length);
+ LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
/// DMRS QPSK modulation
@@ -234,12 +232,12 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE,
pdcch_pdu_rel15->PayloadSizeBits[d],
pdcch_pdu_rel15->AggregationLevel[d],
- 0);
- polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, pdcch_pdu_rel15->RNTI[d],1,currentPtr);
+ 0,NULL);
+ polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr);
#ifdef DEBUG_CHANNEL_CODING
- printf("polar rnti %d\n",pdcch_pdu_rel15->RNTI[d]);
+ printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]);
printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
- pdcch_pdu.Payload[d][0], pdcch_pdu.Payload[d][1]);
+ ((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]);
printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
for (int i=0; i<encoded_length>>5; i++)
@@ -274,74 +272,30 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
/*Reorder REG list for a freq first mapping*/
uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE;
- /*
- for (int cce_idx=pdcch_pdu_rel15->CceIndex;
- cce_idx<(pdcch_pdu_rel15->CceIndex+pdcch_pdu_rel15->AggregationLevel[d]);
- cce_idx++) {
- cce = gNB->cce_list[cce_idx];
-
- for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
- reg = cce.reg_list[reg_idx];
- reg_mapping_list[reg_idx+cce_idx*NR_NB_REG_PER_CCE] = reg;
- }
- }
- */
-
- if (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS) {
- /*in this case the DMRS are mapped on all the coreset*/
- for (l=cset_start_symb; l<cset_start_symb+ cset_nsymb; l++) {
-
- // dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
- if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
- dmrs_idx = 0;
- else
- dmrs_idx = rb_offset*3;
-
- k = cset_start_sc + 1;
-
- while (dmrs_idx<3*n_rb) {
- ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = ((amp>>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15;
- ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
-#ifdef DEBUG_PDCCH_DMRS
- printf("symbol %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
- ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
-#endif
- k+=4;
-
- if (k >= frame_parms.ofdm_symbol_size)
- k -= frame_parms.ofdm_symbol_size;
-
- dmrs_idx++;
- }
- }
- }
-
- /*Now mapping the encoded DCI based on newly constructed REG list
- * and the DMRS for the precoder granularity same as REG bundle*/
+ /*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
- reg = reg_mapping_list[reg_idx];
- k = cset_start_sc + reg.start_sc_idx;
+ k = cset_start_sc + (12*reg_idx/cset_nsymb);
if (k >= frame_parms.ofdm_symbol_size)
k -= frame_parms.ofdm_symbol_size;
- l = cset_start_symb + reg.symb_idx;
+ l = cset_start_symb + ((reg_idx/cset_nsymb)%cset_nsymb);
// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
- dmrs_idx = (reg.reg_idx/cset_nsymb)*3;
+ dmrs_idx = (reg_idx/cset_nsymb)*3;
else
- dmrs_idx = ((reg.reg_idx/cset_nsymb)+rb_offset)*3;
+ dmrs_idx = ((reg_idx/cset_nsymb)+rb_offset)*3;
k_prime = 0;
for (int m=0; m<NR_NB_SC_PER_RB; m++) {
if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
- if (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
- ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = ((amp>>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15;
- ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
+ if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
+ ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
+ ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS
- printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
+ printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif
dmrs_idx++;
@@ -352,7 +306,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dci[dci_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15;
#ifdef DEBUG_DCI
- printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
+ printf("PDCCH: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif
dci_idx++;
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
index 1231fa81270e0caeaba7c3b9cbdf1581e0380838..6acb208ba55267334e4f285adb5558a44e48290b 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
@@ -32,7 +32,7 @@
#include "nr_dci.h"
-#define DEBUG_FILL_DCI
+//#define DEBUG_FILL_DCI
#include "nr_dlsch.h"
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
index 24f8bc7267b5e55f208d2ea955f32ab18240ed3f..993b2a2e97a62d659ad2f6da0fd1d1f7a2f29990 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
@@ -76,7 +76,14 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int xOverhead,
time_stats_t *dlsch_encoding_stats,
time_stats_t *dlsch_scrambling_stats,
- time_stats_t *dlsch_modulation_stats) {
+ time_stats_t *dlsch_modulation_stats,
+ time_stats_t *tinput,
+ time_stats_t *tprep,
+ time_stats_t *tparity,
+ time_stats_t *toutput,
+ time_stats_t *dlsch_rate_matching_stats,
+ time_stats_t *dlsch_interleaving_stats,
+ time_stats_t *dlsch_segmentation_stats) {
int harq_pid = 0;
NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid];
@@ -85,15 +92,23 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs;
int16_t **tx_layers = (int16_t**)dlsch->txdataF;
int8_t Wf[2], Wt[2], l0, l_prime[2], delta;
- uint16_t nb_symbols = rel15->NrOfSymbols;
- uint8_t Qm = rel15->qamModOrder[0];
- uint32_t encoded_length = nb_symbols*Qm;
+ uint8_t dmrs_Type = rel15->dmrsConfigType;
+ int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4;
+ uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1;
+ int16_t mod_dmrs[n_dmrs<<1];
+
+ uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords;
+ uint8_t Qm = rel15->qamModOrder[0];
+ uint32_t encoded_length = nb_re*Qm;
/// CRC, coding, interleaving and rate matching
AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n");
start_meas(dlsch_encoding_stats);
- nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms);
+ nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput,
+ dlsch_rate_matching_stats,
+ dlsch_interleaving_stats,
+ dlsch_segmentation_stats);
stop_meas(dlsch_encoding_stats);
#ifdef DEBUG_DLSCH
printf("PDSCH encoding:\nPayload:\n");
@@ -111,6 +126,8 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
printf("\n");
#endif
+
+
/// scrambling
start_meas(dlsch_scrambling_stats);
for (int q=0; q<rel15->NrOfCodewords; q++)
@@ -142,8 +159,8 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
mod_symbs[q]);
stop_meas(dlsch_modulation_stats);
#ifdef DEBUG_DLSCH
- printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_symbols);
- for (int i=0; i<nb_symbols>>3; i++) {
+ printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_re);
+ for (int i=0; i<nb_re>>3; i++) {
for (int j=0; j<8; j++) {
printf("%d %d\t", mod_symbs[0][((i<<3)+j)<<1], mod_symbs[0][(((i<<3)+j)<<1)+1]);
}
@@ -155,53 +172,50 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
/// Layer mapping
nr_layer_mapping(mod_symbs,
rel15->nrOfLayers,
- nb_symbols,
+ nb_re,
tx_layers);
#ifdef DEBUG_DLSCH
printf("Layer mapping (%d layers):\n", rel15->nrOfLayers);
for (int l=0; l<rel15->nrOfLayers; l++)
- for (int i=0; i<(nb_symbols/rel15->nrOfLayers)>>3; i++) {
+ for (int i=0; i<(nb_re/rel15->nrOfLayers)>>3; i++) {
+ printf("layer %d, Re %d..%d : ",l,i<<3,(i<<3)+7);
for (int j=0; j<8; j++) {
- printf("%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]);
+ printf("l%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]);
}
printf("\n");
}
#endif
/// Antenna port mapping
- //to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007
-
+ //to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007
+
/// DMRS QPSK modulation
- uint8_t dmrs_Type = rel15->dmrsConfigType;
- int nb_re_dmrs = (dmrs_Type==1) ? 6:4;
- uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1;
- int16_t mod_dmrs[n_dmrs<<1];
-
-
- l0 = get_l0(rel15->dlDmrsSymbPos);
- nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated
-
+
+
+ l0 = get_l0(rel15->dlDmrsSymbPos);
+ nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated
+
#ifdef DEBUG_DLSCH
-printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_Type);
-for (int i=0; i<n_dmrs>>4; i++) {
- for (int j=0; j<8; j++) {
- printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]);
+ printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_Type);
+ for (int i=0; i<n_dmrs>>4; i++) {
+ for (int j=0; j<8; j++) {
+ printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]);
+ }
+ printf("\n");
}
- printf("\n");
-}
#endif
-
-
+
+
/// Resource mapping
-
+
// Non interleaved VRB to PRB mapping
uint16_t start_sc = frame_parms->first_carrier_offset + rel15->rbStart*NR_NB_SC_PER_RB;
if (start_sc >= frame_parms->ofdm_symbol_size)
start_sc -= frame_parms->ofdm_symbol_size;
#ifdef DEBUG_DLSCH_MAPPING
- printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_symbols %d)\n",
- start_sc, rel15->StartSymbolIndex, rel15->rbSize, rel15->NrOfSymbols);
+ printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_re %d,nb_layers %d)\n",
+ start_sc, rel15->StartSymbolIndex, rel15->rbSize, nb_re,rel15->nrOfLayers);
#endif
for (int ap=0; ap<rel15->nrOfLayers; ap++) {
@@ -212,8 +226,8 @@ for (int i=0; i<n_dmrs>>4; i++) {
l_prime[0] = 0; // single symbol ap 0
uint8_t dmrs_symbol = l0+l_prime[0];
#ifdef DEBUG_DLSCH_MAPPING
- printf("DMRS params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n",
- ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol);
+ printf("DMRS Type %d params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n",
+ 1+dmrs_Type,ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol);
#endif
uint8_t k_prime=0;
uint16_t m=0, n=0, dmrs_idx=0, k=0;
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
index 065353b35e9545f7d941407756d9544a812cd881..bbb9783d3f7bb1770a7c96e0a4dc1a3278899898 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
@@ -79,7 +79,14 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int xOverhead,
time_stats_t *dlsch_encoding_stats,
time_stats_t *dlsch_scrambling_stats,
- time_stats_t *dlsch_modulation_stats);
+ time_stats_t *dlsch_modulation_stats,
+ time_stats_t *tinput,
+ time_stats_t *tprep,
+ time_stats_t *tparity,
+ time_stats_t *toutput,
+ time_stats_t *dlsch_rate_matching_stats,
+ time_stats_t *dlsch_interleaving_stats,
+ time_stats_t *dlsch_segmentation_stats);
void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch);
@@ -91,9 +98,16 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch);
int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type);
int nr_dlsch_encoding(unsigned char *a,int frame,
- uint8_t slot,
- NR_gNB_DLSCH_t *dlsch,
- NR_DL_FRAME_PARMS* frame_parms);
+ uint8_t slot,
+ NR_gNB_DLSCH_t *dlsch,
+ NR_DL_FRAME_PARMS* frame_parms,
+ time_stats_t *tinput,
+ time_stats_t *tprep,
+ time_stats_t *tparity,
+ time_stats_t *toutput,
+ time_stats_t *dlsch_rate_matching_stats,
+ time_stats_t *dlsch_interleaving_stats,
+ time_stats_t *dlsch_segmentation_stats);
void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size);
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
index 08cefcab46827609d51dc82ca4122951dbe9f0f7..a2fd4ee1bc0d76722a80463ed3e21eccebc9d119 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
@@ -70,7 +70,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
#endif
if (dlsch->harq_processes[i]->b) {
- free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES); //this should be MAX_NR_DLSCH_PAYLOAD_BYTES
+ free16(dlsch->harq_processes[i]->b,MAX_NR_DLSCH_PAYLOAD_BYTES); //this should be MAX_NR_DLSCH_PAYLOAD_BYTES
dlsch->harq_processes[i]->b = NULL;
#ifdef DEBUG_DLSCH_FREE
LOG_D(PHY,"Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b);
@@ -81,7 +81,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
LOG_D(PHY,"Freeing dlsch process %d c (%p)\n",i,dlsch->harq_processes[i]->c);
#endif
- for (r=0; r<MAX_NUM_DLSCH_SEGMENTS; r++) {
+ for (r=0; r<MAX_NUM_NR_DLSCH_SEGMENTS; r++) {
#ifdef DEBUG_DLSCH_FREE
LOG_D(PHY,"Freeing dlsch process %d c[%d] (%p)\n",i,r,dlsch->harq_processes[i]->c[r]);
@@ -121,17 +121,8 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms,
int re;
unsigned char bw_scaling =1;
- switch (N_RB) {
-
- case 106:
- bw_scaling =2;
- break;
-
- default:
- bw_scaling =1;
- break;
- }
-
+ if (N_RB <= 107) bw_scaling =2;
+
dlsch = (NR_gNB_DLSCH_t *)malloc16(sizeof(NR_gNB_DLSCH_t));
if (dlsch) {
@@ -260,7 +251,7 @@ void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
dlsch->harq_processes[i]->round = 0;
for (j=0; j<96; j++)
- for (r=0; r<MAX_NUM_DLSCH_SEGMENTS; r++)
+ for (r=0; r<MAX_NUM_NR_DLSCH_SEGMENTS; r++)
if (dlsch->harq_processes[i]->d[r])
dlsch->harq_processes[i]->d[r][j] = NR_NULL;
@@ -273,7 +264,10 @@ int nr_dlsch_encoding(unsigned char *a,
int frame,
uint8_t slot,
NR_gNB_DLSCH_t *dlsch,
- NR_DL_FRAME_PARMS* frame_parms)
+ NR_DL_FRAME_PARMS* frame_parms,
+ time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput,
+ time_stats_t *dlsch_rate_matching_stats,time_stats_t *dlsch_interleaving_stats,
+ time_stats_t *dlsch_segmentation_stats)
{
unsigned int G;
@@ -293,7 +287,7 @@ int nr_dlsch_encoding(unsigned char *a,
uint32_t E;
uint8_t Ilbrm = 1;
uint32_t Tbslbrm = 950984; //max tbs
- uint8_t nb_re_dmrs = rel15->dmrsConfigType==1 ? 6:4;
+ uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4;
uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos);
uint16_t R=rel15->targetCodeRate[0];
float Coderate = 0.0;
@@ -339,7 +333,7 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->B = A+24;
// dlsch->harq_processes[harq_pid]->b = a;
- AssertFatal((A/8)+4 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_DLSCH_PAYLOAD_BYTES);
+ AssertFatal((A/8)+3 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_NR_DLSCH_PAYLOAD_BYTES);
memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+4); // why is this +4 if the CRC is only 3 bytes?
}
@@ -354,7 +348,7 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->B = A+16;
// dlsch->harq_processes[harq_pid]->b = a;
- AssertFatal((A/8)+3 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_DLSCH_PAYLOAD_BYTES);
+ AssertFatal((A/8)+3 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_NR_DLSCH_PAYLOAD_BYTES);
memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc
}
@@ -368,6 +362,7 @@ int nr_dlsch_encoding(unsigned char *a,
else
BG = 1;
+ start_meas(dlsch_segmentation_stats);
Kb = nr_segmentation(dlsch->harq_processes[harq_pid]->b,
dlsch->harq_processes[harq_pid]->c,
dlsch->harq_processes[harq_pid]->B,
@@ -376,7 +371,7 @@ int nr_dlsch_encoding(unsigned char *a,
Zc,
&dlsch->harq_processes[harq_pid]->F,
BG);
-
+ stop_meas(dlsch_segmentation_stats);
F = dlsch->harq_processes[harq_pid]->F;
Kr = dlsch->harq_processes[harq_pid]->K;
@@ -405,7 +400,9 @@ int nr_dlsch_encoding(unsigned char *a,
}
for(int j=0;j<(dlsch->harq_processes[harq_pid]->C/8+1);j++) {
- ldpc_encoder_optim_8seg_multi(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,dlsch->harq_processes[harq_pid]->C,j,NULL,NULL,NULL,NULL);
+ ldpc_encoder_optim_8seg_multi(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,
+ dlsch->harq_processes[harq_pid]->C,j,
+ tinput,tprep,tparity,toutput);
}
@@ -446,6 +443,7 @@ int nr_dlsch_encoding(unsigned char *a,
Tbslbrm = nr_compute_tbslbrm(rel15->mcsTable[0],nb_rb,Nl,dlsch->harq_processes[harq_pid]->C);
+ start_meas(dlsch_rate_matching_stats);
nr_rate_matching_ldpc(Ilbrm,
Tbslbrm,
BG,
@@ -455,17 +453,18 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->C,
rel15->rvIndex[0],
E);
-
+ stop_meas(dlsch_rate_matching_stats);
#ifdef DEBUG_DLSCH_CODING
for (int i =0; i<16; i++)
LOG_D(PHY,"output ratematching e[%d]= %d r_offset %d\n", i,dlsch->harq_processes[harq_pid]->e[i+r_offset], r_offset);
#endif
- nr_interleaving_ldpc(E,
- mod_order,
- dlsch->harq_processes[harq_pid]->e+r_offset,
- dlsch->harq_processes[harq_pid]->f+r_offset);
-
+ start_meas(dlsch_interleaving_stats);
+ nr_interleaving_ldpc(E,
+ mod_order,
+ dlsch->harq_processes[harq_pid]->e+r_offset,
+ dlsch->harq_processes[harq_pid]->f+r_offset);
+ stop_meas(dlsch_interleaving_stats);
#ifdef DEBUG_DLSCH_CODING
for (int i =0; i<16; i++)
diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c
index 1323b9fa0fb4d7d3ab178fe08217d970729aa668..c8bdb8beb5b0c10a690489e73d0bd510fcbd6b84 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c
@@ -299,7 +299,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch,
/// CRC, coding and rate matching
polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0,
- nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0)
+ nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL)
);
#ifdef DEBUG_PBCH_ENCODING
printf("Channel coding:\n");
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
index ec6a77d5610e89c3eed2c3c021900598655c062a..762346048f94f9e62e7733ecdbb4010ffa107dd1 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
@@ -36,9 +36,6 @@
#include "PHY/defs_nr_common.h"
-#define MAX_NUM_NR_DLSCH_SEGMENTS 16
-#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS
-
#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1
#define NR_PUSCH_y 3 // UCI placeholder bit
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
index e7af6323277b05b70cc85096775e69e869b8c9ef..15e66477c3ab80aa7c19aa945c1af900b455ce37 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
@@ -1728,41 +1728,6 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8
uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset);
-uint8_t nr_dci_decoding_procedure(int s,
- int p,
- PHY_VARS_NR_UE *ue,
- NR_DCI_ALLOC_t *dci_alloc,
- NR_SEARCHSPACE_TYPE_t searchSpacetype,
- int16_t eNB_id,
- uint8_t nr_tti_rx,
- uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- crc_scrambled_t *crc_scrambled,
- format_found_t *format_found,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
-
-int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- int frame,
- uint8_t nr_tti_rx,
- uint64_t dci_pdu[2],
- uint16_t rnti,
- uint8_t dci_length,
- NR_DCI_format_t dci_format,
- NR_UE_PDCCH *pdcch_vars,
- NR_UE_PDSCH *pdsch_vars,
- NR_UE_DLSCH_t **dlsch,
- NR_UE_ULSCH_t *ulsch,
- NR_DL_FRAME_PARMS *frame_parms,
- PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- uint8_t beamforming_mode,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
- NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted);
-
int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
PDSCH_t type,
unsigned char eNB_id,
@@ -1789,20 +1754,5 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t is_crnti,
uint8_t llr8_flag);
-int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- lte_frame_type_t frame_type,
- uint8_t dci_length,
- uint16_t rnti,
- uint64_t dci_pdu[2],
- fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- NR_DCI_format_t dci_format,
- uint8_t nr_tti_rx,
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
-
-
/**@}*/
#endif
diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
index aaa304ec6373c1c194e41ddbc5a2fc735be928b4..72ab04c492d55cc0fd259b7580ac5c17fed40e34 100644
--- a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
+++ b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
@@ -475,7 +475,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
unsigned short coreset_start_subcarrier,
unsigned short nb_rb_coreset)
{
- int pilot[200] __attribute__((aligned(16)));
+
unsigned char aarx;
unsigned short k;
unsigned int pilot_cnt;
@@ -484,12 +484,9 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
- uint8_t nushift;
int **dl_ch_estimates =ue->pdcch_vars[ue->current_thread_id[Ns]][eNB_offset]->dl_ch_estimates;
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF;
- nushift = 1;
- ue->frame_parms.nushift = nushift;
if (ue->high_speed_flag == 0) // use second channel estimate position for temporary storage
ch_offset = ue->frame_parms.ofdm_symbol_size ;
@@ -510,14 +507,15 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
fr = filt16a_r1;
- // generate pilot
+ // generate pilot
+ int pilot[nb_rb_coreset * 3] __attribute__((aligned(16)));
nr_pdcch_dmrs_rx(ue,eNB_offset,Ns,ue->nr_gold_pdcch[eNB_offset][Ns][symbol], &pilot[0],2000,nb_rb_coreset);
for (aarx=0; aarx<ue->frame_parms.nb_antennas_rx; aarx++) {
pil = (int16_t *)&pilot[0];
- rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)];
+ rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)];
dl_ch = (int16_t *)&dl_ch_estimates[aarx][ch_offset];
memset(dl_ch,0,4*(ue->frame_parms.ofdm_symbol_size));
@@ -588,7 +586,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
if (k >= ue->frame_parms.ofdm_symbol_size){
k-=ue->frame_parms.ofdm_symbol_size;
- rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)];}
+ rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)];}
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
@@ -622,7 +620,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PDCCH
- printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
#endif
multadd_real_vector_complex_scalar(fr,
diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
index d97c6fdc6b804bf1a5d3e7ef68f007b0f2eb4def..96d446272489be264d6e9fb1d7aef78afc91937f 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
@@ -43,7 +43,7 @@
#include "assertions.h"
#include "T.h"
-#define DEBUG_DCI_DECODING 1
+//#define DEBUG_DCI_DECODING 1
//#define NR_LTE_PDCCH_DCI_SWITCH
#define NR_PDCCH_DCI_RUN // activates new nr functions
@@ -300,9 +300,8 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
int32_t **rxdataF_ext,
int32_t **dl_ch_estimates_ext,
uint8_t symbol,
- uint32_t high_speed_flag,
NR_DL_FRAME_PARMS *frame_parms,
- uint64_t coreset_freq_dom,
+ uint8_t *coreset_freq_dom,
uint32_t coreset_nbr_rb,
uint32_t n_BWP_start) {
/*
@@ -329,21 +328,14 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
uint8_t i, j, aarx, bitcnt_coreset_freq_dom=0;
int32_t *dl_ch0, *dl_ch0_ext, *rxF, *rxF_ext;
- c_rb = n_BWP_start; // c_rb is the common resource block: RB within the BWP
#ifdef DEBUG_DCI_DECODING
uint8_t symbol_mod = (symbol >= (7 - frame_parms->Ncp)) ? symbol - (7 - frame_parms->Ncp) : symbol;
LOG_I(PHY, "extract_rbs_single: symbol_mod %d\n",symbol_mod);
#endif
for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) {
- if (high_speed_flag == 1) {
- dl_ch0 = &dl_ch_estimates[aarx][(symbol * (frame_parms->ofdm_symbol_size))];
- LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][ (symbol * (frame_parms->ofdm_symbol_size (%d))) = (%d)]\n",
- aarx,frame_parms->ofdm_symbol_size,(symbol * (frame_parms->ofdm_symbol_size)));
- } else {
- dl_ch0 = &dl_ch_estimates[aarx][0];
- LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n",aarx);
- }
+ dl_ch0 = &dl_ch_estimates[aarx][0];
+ LOG_DDD("dl_ch0 = &dl_ch_estimates[aarx = (%d)][0]\n",aarx);
dl_ch0_ext = &dl_ch_estimates_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)];
LOG_DDD("dl_ch0_ext = &dl_ch_estimates_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n",
@@ -351,10 +343,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
rxF_ext = &rxdataF_ext[aarx][symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS)];
LOG_DDD("rxF_ext = &rxdataF_ext[aarx = (%d)][symbol * (frame_parms->N_RB_DL * 9) = (%d)]\n",
aarx,symbol * (coreset_nbr_rb * NBR_RE_PER_RB_WITH_DMRS));
- LOG_DDD("(for symbol=%d, aarx=%d), symbol_mod=%d, nushiftmod3=%d \n",
- symbol,aarx,
- (symbol >= (7 - frame_parms->Ncp)) ? symbol - (7 - frame_parms->Ncp) : symbol,
- frame_parms->nushift % 3);
+
/*
* The following for loop handles treatment of PDCCH contained in table rxdataF (in frequency domain)
* In NR the PDCCH IQ symbols are contained within RBs in the CORESET defined by higher layers which is located within the BWP
@@ -373,24 +362,13 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
* we have to point the pointer at (1+c_rb-N_RB_DL/2) in rxdataF
*/
LOG_DDD("n_BWP_start=%d, coreset_nbr_rb=%d\n",n_BWP_start,coreset_nbr_rb);
+ int c_rb_by6;
+ c_rb = n_BWP_start;
+ for (int rb=0;rb<coreset_nbr_rb;rb++,c_rb++) {
+ c_rb_by6 = c_rb/6;
+ // skip zeros in frequency domain bitmap
+ while ((coreset_freq_dom[c_rb_by6>>3] & (1<<(c_rb_by6&7))) == 0) c_rb+=6;
- for (c_rb = n_BWP_start; c_rb < (n_BWP_start + coreset_nbr_rb + (BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN * offset_discontiguous)); c_rb++) {
- //c_rb_tmp = 0;
- if (((c_rb - n_BWP_start) % BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN)==0) {
- bitcnt_coreset_freq_dom ++;
-
- while ((((coreset_freq_dom & 0x1FFFFFFFFFFF) >> (CORESET_FREQ_DOMAIN_BITMAP_SIZE - (n_BWP_start/BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN) - bitcnt_coreset_freq_dom)) & 0x1)== 0) { // 46 -> 45 is number of bits in coreset_freq_dom
- // next 6 RB are not part of the CORESET within the BWP as bit in coreset_freq_dom is set to 0
- bitcnt_coreset_freq_dom ++;
- //c_rb_tmp = c_rb_tmp + 6;
- c_rb = c_rb + BIT_TO_NBR_RB_CORESET_FREQ_DOMAIN;
- offset_discontiguous ++;
- LOG_DDD("we entered here as coreset_freq_dom=%lx (bit %d) is 0, coreset_freq_domain is discontiguous\n",coreset_freq_dom,
- (46 - bitcnt_coreset_freq_dom));
- }
- }
-
- //c_rb = c_rb + c_rb_tmp;
LOG_DDD("c_rb=%d\n",c_rb);
rxF=NULL;
@@ -418,45 +396,30 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
//if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): odd case
rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))];
- LOG_DDD("in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
+#endif
}
if ((c_rb > (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
// number of RBs is odd and c_rb is higher than half system bandwidth + 1
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF just after the first IQ symbols of the RB containing DC
rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol
- LOG_DDD("in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size))));
+#endif
}
if ((c_rb == (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // treatment of RB containing the DC
// if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC)
// we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the end of the table)
rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))];
- LOG_DDD("in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
- /*if (symbol_mod > 300) { // this if is going to be removed as DM-RS signals are present in all symbols of PDCCH
- for (i = 0; i < 6; i++) {
- dl_ch0_ext[i] = dl_ch0[i];
- rxF_ext[i] = rxF[i];
- }
- rxF = &rxdataF[aarx][(symbol * (frame_parms->ofdm_symbol_size))]; // we point at the 1st part of the rxdataF in symbol
- #ifdef NR_PDCCH_DCI_DEBUG
- LOG_DDD("in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n",
- c_rb,aarx,(symbol * (frame_parms->ofdm_symbol_size)));
- #endif
- for (; i < 12; i++) {
- dl_ch0_ext[i] = dl_ch0[i];
- rxF_ext[i] = rxF[(1 + i - 6)];
- }
- nb_rb++;
- dl_ch0_ext += 12;
- rxF_ext += 12;
- dl_ch0 += 12;
- rxF += 7;
- c_rb++;
- } else {*/
+#endif
j = 0;
for (i = 0; i < 6; i++) { //treating first part of the RB note that i=5 would correspond to DC. We treat it in NR
@@ -469,9 +432,10 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
// then we point at the begining of the symbol part of rxdataF do process second part of RB
rxF = &rxdataF[aarx][((symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol
- LOG_DDD("in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL +1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(symbol * (frame_parms->ofdm_symbol_size)) = (%d)]\n",
c_rb,aarx,(symbol * (frame_parms->ofdm_symbol_size)));
-
+#endif
for (; i < 12; i++) {
if ((i != 9)) {
dl_ch0_ext[j] = dl_ch0[i];
@@ -489,33 +453,27 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
//n_BWP_start++; // We have to increment this variable here to be consequent in the for loop afterwards
//}
} else { // treatment of any RB that does not contain the DC
- /*if (symbol_mod > 300) {
- memcpy(dl_ch0_ext, dl_ch0, 12 * sizeof(int32_t));
- for (i = 0; i < 12; i++) {
- rxF_ext[i] = rxF[i];
- }
- nb_rb++;
- dl_ch0_ext += 12;
- rxF_ext += 12;
- dl_ch0 += 12;
- //rxF += 12;
- } else {*/
j = 0;
for (i = 0; i < 12; i++) {
if ((i != 1) && (i != 5) && (i != 9)) {
rxF_ext[j] = rxF[i];
- LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d)\n",
c_rb, i, j, *(short *) &rxF_ext[j],*(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
+#endif
dl_ch0_ext[j] = dl_ch0[i];
+
//LOG_DDD("ch %d => dl_ch0(%d,%d)\n", i, *(short *) &dl_ch0[i], *(1 + (short*) &dl_ch0[i]));
//printf("\t-> dl_ch0[%d] => dl_ch0_ext[%d](%d,%d)\n", i,j, *(short *) &dl_ch0[i], *(1 + (short*) &dl_ch0[i]));
j++;
} else {
- LOG_DDD("RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n",
+#ifdef NR_PDCCH_DCI_DEBUG
+ LOG_D(PHY,"RB[c_rb %d] \t RE[re %d] => rxF_ext[%d]=(%d,%d)\t rxF[%d]=(%d,%d) \t\t <==> DM-RS PDCCH, this is a pilot symbol\n",
c_rb, i, j, *(short *) &rxF_ext[j], *(1 + (short *) &rxF_ext[j]), i,
*(short *) &rxF[i], *(1 + (short *) &rxF[i]));
+#endif
}
}
@@ -703,6 +661,116 @@ void pdcch_siso(NR_DL_FRAME_PARMS *frame_parms,
#ifdef NR_PDCCH_DCI_RUN
+int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
+ uint32_t frame,
+ uint32_t slot) {
+
+ NR_UE_COMMON *common_vars = &ue->common_vars;
+ NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
+ NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[slot]][0];
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15;
+
+ uint8_t log2_maxh, aarx;
+ int32_t avgs;
+ int32_t avgP[4];
+ for (int i=0;i<pdcch_vars->nb_search_space;i++) {
+
+ rel15 = &pdcch_vars->pdcch_config[i];
+ int n_rb,rb_offset;
+ get_coreset_rballoc(rel15->coreset.frequency_domain_resource,&n_rb,&rb_offset);
+ for (int s=rel15->coreset.StartSymbolIndex;
+ s<(rel15->coreset.StartSymbolIndex+rel15->coreset.duration);
+ s++) {
+
+ nr_pdcch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[slot]].rxdataF,
+ pdcch_vars->dl_ch_estimates,
+ pdcch_vars->rxdataF_ext,
+ pdcch_vars->dl_ch_estimates_ext,
+ s,
+ frame_parms,
+ rel15->coreset.frequency_domain_resource,
+ n_rb,
+ rel15->BWPStart);
+
+ LOG_DD("we enter pdcch_channel_level(avgP=%d) => compute channel level based on ofdm symbol 0, pdcch_vars[eNB_id]->dl_ch_estimates_ext\n",*avgP);
+ LOG_DD("in pdcch_channel_level(dl_ch_estimates_ext -> dl_ch_estimates_ext)\n");
+ // compute channel level based on ofdm symbol 0
+ pdcch_channel_level(pdcch_vars->dl_ch_estimates_ext,
+ frame_parms,
+ avgP,
+ n_rb);
+ avgs = 0;
+
+ for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++)
+ avgs = cmax(avgs, avgP[aarx]);
+
+ log2_maxh = (log2_approx(avgs) / 2) + 5; //+frame_parms->nb_antennas_rx;
+#ifdef UE_DEBUG_TRACE
+ LOG_D(PHY,"slot %d: pdcch log2_maxh = %d (%d,%d)\n",slot,log2_maxh,avgP[0],avgs);
+#endif
+#if T_TRACER
+ T(T_UE_PHY_PDCCH_ENERGY, T_INT(0), T_INT(0), T_INT(frame%1024), T_INT(slot),
+ T_INT(avgP[0]), T_INT(avgP[1]), T_INT(avgP[2]), T_INT(avgP[3]));
+#endif
+ LOG_DD("we enter nr_pdcch_channel_compensation(log2_maxh=%d)\n",log2_maxh);
+ LOG_DD("in nr_pdcch_channel_compensation(rxdataF_ext x dl_ch_estimates_ext -> rxdataF_comp)\n");
+ // compute LLRs for ofdm symbol 0 only
+ nr_pdcch_channel_compensation(pdcch_vars->rxdataF_ext,
+ pdcch_vars->dl_ch_estimates_ext,
+ pdcch_vars->rxdataF_comp,
+ NULL,
+ frame_parms,
+ s,
+ log2_maxh,
+ n_rb); // log2_maxh+I0_shift
+ if (frame_parms->nb_antennas_rx > 1) {
+ LOG_DD("we enter pdcch_detection_mrc(frame_parms->nb_antennas_rx=%d)\n",
+ frame_parms->nb_antennas_rx);
+ pdcch_detection_mrc(frame_parms, pdcch_vars->rxdataF_comp,s);
+ }
+
+ LOG_DD("we enter nr_pdcch_llr(for symbol %d), pdcch_vars[eNB_id]->rxdataF_comp ---> pdcch_vars[eNB_id]->llr \n",s);
+ LOG_DD("in nr_pdcch_llr(rxdataF_comp -> llr)\n");
+ nr_pdcch_llr(frame_parms,
+ pdcch_vars->rxdataF_comp,
+ pdcch_vars->llr,
+ s,
+ n_rb);
+#if T_TRACER
+
+ // T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL),
+ // T_INT(n_pdcch_symbols),
+ // T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4));
+
+#endif
+#ifdef DEBUG_DCI_DECODING
+ printf("demapping: slot %d, mi %d\n",slot,get_mi(frame_parms,slot));
+#endif
+ }
+
+ LOG_DD("we enter nr_pdcch_demapping_deinterleaving()\n");
+ nr_pdcch_demapping_deinterleaving((uint32_t *) pdcch_vars->llr,
+ (uint32_t *) pdcch_vars->e_rx,
+ frame_parms,
+ rel15->coreset.duration,
+ n_rb,
+ rel15->coreset.RegBundleSize,
+ rel15->coreset.InterleaverSize,
+ rel15->coreset.ShiftIndex);
+ nr_pdcch_unscrambling(rel15->rnti,
+ frame_parms,
+ slot,
+ pdcch_vars->e_rx,
+ rel15->coreset.duration*n_rb*9*2,
+ // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72,
+ rel15->coreset.pdcch_dmrs_scrambling_id);
+ LOG_DD("we end nr_pdcch_unscrambling()\n");
+ LOG_DD("Ending nr_rx_pdcch() function\n");
+ return (0);
+ }
+
+}
+ /*
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
uint32_t frame,
uint8_t nr_tti_rx,
@@ -745,7 +813,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
// For each BWP the number of CORESETs is limited to 3 (including initial CORESET Id=0 -> ControlResourceSetId (0..maxNrofControlReourceSets-1) (0..12-1)
//uint32_t n_BWP_start = 0;
//uint32_t n_rb_offset = 0;
- uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset;/*+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB);*/
+ uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset;//+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB);
// start time position for CORESET
// parameter symbol_mon is a 14 bits bitmap indicating monitoring symbols within a slot
uint8_t start_symbol = 0;
@@ -860,11 +928,11 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
s,
coreset_nbr_rb);
#if T_TRACER
- /*
- T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL),
- T_INT(n_pdcch_symbols),
- T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4));
- */
+
+ // T(T_UE_PHY_PDCCH_IQ, T_INT(frame_parms->N_RB_DL), T_INT(frame_parms->N_RB_DL),
+ // T_INT(n_pdcch_symbols),
+ // T_BUFFER(pdcch_vars[eNB_id]->rxdataF_comp, frame_parms->N_RB_DL*12*n_pdcch_symbols* 4));
+
#endif
#ifdef DEBUG_DCI_DECODING
printf("demapping: nr_tti_rx %d, mi %d\n",nr_tti_rx,get_mi(frame_parms,nr_tti_rx));
@@ -892,6 +960,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
LOG_DD("Ending nr_rx_pdcch() function\n");
return (0);
}
+ */
#endif
@@ -923,64 +992,28 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms,
#ifdef NR_PDCCH_DCI_RUN
-void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx,
- int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common) {
+void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
+ int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id) {
int i;
uint8_t reset;
uint32_t x1, x2, s = 0;
uint16_t n_id; //{0,1,...,65535}
uint32_t n_rnti;
reset = 1;
-
// x1 is set in first call to lte_gold_generic
//do_common=1;
- if (do_common) {
- n_id = frame_parms->Nid_cell;
- n_rnti = 0;
- } else {
n_id = pdcch_DMRS_scrambling_id;
n_rnti = (uint32_t)crnti;
- }
- //x2 = ((n_rnti * (1 << 16)) + n_id)%(1 << 31);
- //uint32_t puissance_2_16 = ((1<<16)*n_rnti)+n_id;
- //uint32_t puissance_2_31= (1<<30)*2;
- //uint32_t calc_x2=puissance_2_16%puissance_2_31;
x2 = (((1<<16)*n_rnti)+n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3
- // x2 = (nr_tti_rx << 9) + frame_parms->Nid_cell; //this is c_init in 36.211 Sec 6.8.2
- //LOG_DDD(" (c_init=%d, n_id=%d, n_rnti=%d, length=%d)\n",x2,n_id,n_rnti,length);
for (i = 0; i < length; i++) {
if ((i & 0x1f) == 0) {
s = lte_gold_generic(&x1, &x2, reset);
- //LOG_DDD("lte_gold[%d]=%x\n",i,s);
reset = 0;
}
- /*
- #ifdef NR_PDCCH_DCI_DEBUG
- if (i%2 == 0) LOG_DDD(" unscrambling %d : scrambled_z=%d, => ",
- i,*(char*) &z[(int)floor(i/2)]);
- if (i%2 == 1) LOG_DDD(" unscrambling %d : scrambled_z=%d, => ",
- i,*(1 + (char*) &z[(int)floor(i/2)]));
- #endif
- if (((s >> (i % 32)) & 1) == 1){
- if (i%2 == 0) *(char*) &z[(int)floor(i/2)] = -(*(char*) &z[(int)floor(i/2)]);
- if (i%2 == 1) *(1 + (char*) &z[(int)floor(i/2)]) = -(*(1 + (char*) &z[(int)floor(i/2)]));
- }
- //llr[i] = -llr[i];
- //llr[i] = (-1)*llr[i];
- #ifdef NR_PDCCH_DCI_DEBUG
- if (i%2 == 0) printf("unscrambled_z=%d\n",*(char*) &z[(int)floor(i/2)]);
- if (i%2 == 1) printf("unscrambled_z=%d\n",*(1 + (char*) &z[(int)floor(i/2)]));
- #endif
- */
- LOG_DDD(" unscrambling %d : scrambled_z=%d, => ",
- i,z[i]);
-
if (((s >> (i % 32)) & 1) == 1) z[i] = -z[i];
-
- LOG_DDD("unscrambled_z=%d\n",z[i]);
}
}
@@ -988,6 +1021,42 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8
#ifdef NR_PDCCH_DCI_RUN
+uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
+ int frame,
+ int slot,
+ fapi_nr_dci_indication_t *dci_ind) {
+
+ NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[slot]][0];
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15;
+ for (int i=0;i<pdcch_vars->nb_search_space;i++) {
+
+ rel15 = &pdcch_vars->pdcch_config[i];
+ int dci_length = rel15->dci_length;
+ for (int j=0;j<rel15->number_of_candidates;j++) {
+ int CCEind = rel15->CCE[j];
+ int L = rel15->L[j];
+ uint64_t dci_estimation[2]= {0};
+ const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList);
+ uint16_t crc = polar_decoder_int16(&pdcch_vars->e_rx[CCEind*9*6*2],
+ dci_estimation,
+ 1,
+ currentPtrDCI);
+ if (crc == rel15->rnti) {
+ dci_ind->SFN = frame;
+ dci_ind->slot = slot;
+ dci_ind->dci_list[dci_ind->number_of_dcis].rnti = rel15->rnti;
+ dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind;
+ dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format;
+ dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length;
+ memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8);
+ dci_ind->number_of_dcis++;
+ }
+ }
+ }
+ return(dci_ind->number_of_dcis);
+}
+
+/*
void nr_dci_decoding_procedure0(int s,
int p,
int coreset_time_dur,
@@ -1050,24 +1119,24 @@ void nr_dci_decoding_procedure0(int s,
// (1 bit set to '1' corresponds to 6 RB and 1 CCE = 6 RB)
LOG_DDD("nCCE[%d]=%d\n",p,nCCE[p]);
- /* if (nCCE > get_nCCE(3, frame_parms, 1)) {
- LOG_D(PHY,
- "skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n",
- nCCE, get_nCCE(3, frame_parms, 1));
- return;
- }
+ // if (nCCE > get_nCCE(3, frame_parms, 1)) {
+ //LOG_D(PHY,
+ //"skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n",
+ //nCCE, get_nCCE(3, frame_parms, 1));
+ //return;
+ // }
- if (nCCE < L2) {
- LOG_D(PHY, "skip DCI decoding: nCCE=%d < L2=%d\n", nCCE, L2);
- return;
- }
+// if (nCCE < L2) {
+// LOG_D(PHY, "skip DCI decoding: nCCE=%d < L2=%d\n", nCCE, L2);
+// return;
+// }
+
+// if (mode == NO_DCI) {
+// LOG_D(PHY, "skip DCI decoding: expect no DCIs at nr_tti_rx %d\n",
+// nr_tti_rx);
+// return;
+// }
- if (mode == NO_DCI) {
- LOG_D(PHY, "skip DCI decoding: expect no DCIs at nr_tti_rx %d\n",
- nr_tti_rx);
- return;
- }
- */
if (do_common == 1) {
Yk = 0;
@@ -1140,9 +1209,9 @@ void nr_dci_decoding_procedure0(int s,
}
LOG_DDD("L2(%d) | nCCE[%d](%d) | Yk(%u) | nb_candidates(%u)\n", L2, p, nCCE[p], Yk, nb_candidates);
- /* for (CCEind=0;
- CCEind<nCCE2;
- CCEind+=(1<<L)) {*/
+ // for (CCEind=0;
+ // CCEind<nCCE2;
+ // CCEind+=(1<<L)) {
// if (nb_candidates * L2 > nCCE[p])
// nb_candidates = nCCE[p] / L2;
// In the next code line there is maybe a bug. The spec is not comparing Table 10.1-2 with nb_candidates, but with total number of candidates for all s and all p
@@ -1219,33 +1288,33 @@ void nr_dci_decoding_procedure0(int s,
// for (int m=0; m < (nCCE[p]*6*9*2); m++)
LOG_DDD("(polar decoding)-> polar intput (with coreset_time_dur=%d, coreset_nbr_rb=%d, p=%d, CCEind=%d): \n",
coreset_time_dur,coreset_nbr_rb,p,CCEind);
- /*
- int reg_p=0,reg_e=0;
- for (int m=0; m < (L2*6); m++){
- reg_p = (((int)floor(m/coreset_time_dur))+((m%coreset_time_dur)*(L2*6/coreset_time_dur)))*9*2;
- reg_e = m*9*2;
- for (int i=0; i<9*2; i++){
+
+ //int reg_p=0,reg_e=0;
+ //for (int m=0; m < (L2*6); m++){
+ //reg_p = (((int)floor(m/coreset_time_dur))+((m%coreset_time_dur)*(L2*6/coreset_time_dur)))*9*2;
+ //reg_e = m*9*2;
+ //for (int i=0; i<9*2; i++){
//polar_input[reg_p+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1.0):(-1.0);
- polar_input[reg_e+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1/sqrt(2)):((-1)/sqrt(2));
+ //polar_input[reg_e+i] = (pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]>0) ? (1/sqrt(2)):((-1)/sqrt(2));
//printf("\t m=%d \tpolar_input[%d]=%lf <-> e_rx[%d]=%d\n",m,reg_e+i,polar_input[reg_e+i],
// ((CCEind*9*6*2) + reg_e + i),pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]);
//printf("\t m=%d \tpolar_input[%d]=%lf <-> e_rx[%d]=%d\n",m,reg_p+i,polar_input[reg_p+i],
// ((CCEind*9*6*2) + reg_e + i),pdcch_vars[eNB_id]->e_rx[((CCEind*9*6*2) + reg_e + i)]);
- }
- }
+ //}
+ //}
- #ifdef NR_PDCCH_DCI_DEBUG
- printf("\n");
- int j=0;
- uint32_t polar_hex[27] = {0};
- for (int i=0; i<L2*9*6*2; i++){2
- if ((i%32 == 0) && (i!=0)) j++;
+ //#ifdef NR_PDCCH_DCI_DEBUG
+ //printf("\n");
+ //int j=0;
+ //uint32_t polar_hex[27] = {0};
+ //for (int i=0; i<L2*9*6*2; i++){2
+ //if ((i%32 == 0) && (i!=0)) j++;
//polar_hex[j] = (polar_hex[j]<<1) + ((polar_input[i]==-1)? 1:0);
- polar_hex[j] = polar_hex[j] + (((polar_input[i]==((-1)/sqrt(2)))?1:0)<<(i%32));
- }
- for (j=0;j<27;j++) LOG_DDD("polar_hex[%d]=%x\n",j,polar_hex[j]);
- #endif
- */
+ //polar_hex[j] = polar_hex[j] + (((polar_input[i]==((-1)/sqrt(2)))?1:0)<<(i%32));
+ //}
+ //for (j=0;j<27;j++) LOG_DDD("polar_hex[%d]=%x\n",j,polar_hex[j]);
+ //#endif
+
uint64_t dci_estimation[2]= {0};
const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, sizeof_bits, L2,1);
decoderState = polar_decoder_int16(&pdcch_vars[eNB_id]->e_rx[CCEind*9*6*2],
@@ -1406,42 +1475,42 @@ void nr_dci_decoding_procedure0(int s,
// store first nCCE of group for PUCCH transmission of ACK/NAK
pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
- /* if (crc == si_rnti) {
- dci_alloc[*dci_cnt].format = format_si;
- *dci_cnt = *dci_cnt + 1;
- } else if (crc == p_rnti) {
- dci_alloc[*dci_cnt].format = format_p;
- *dci_cnt = *dci_cnt + 1;
- } else if (crc == ra_rnti) {
- dci_alloc[*dci_cnt].format = format_ra;
- // store first nCCE of group for PUCCH transmission of ACK/NAK
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
- *dci_cnt = *dci_cnt + 1;
- } else if (crc == pdcch_vars[eNB_id]->crnti) {
-
- if ((mode & UL_DCI) && (format_c == format0)
- && ((dci_decoded_output[current_thread_id][0] & 0x80)
- == 0)) { // check if pdu is format 0 or 1A
- if (*format0_found == 0) {
- dci_alloc[*dci_cnt].format = format0;
- *format0_found = 1;
- *dci_cnt = *dci_cnt + 1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
- }
- } else if (format_c == format0) { // this is a format 1A DCI
- dci_alloc[*dci_cnt].format = format1A;
- *dci_cnt = *dci_cnt + 1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
- } else {
- // store first nCCE of group for PUCCH transmission of ACK/NAK
- if (*format_c_found == 0) {
- dci_alloc[*dci_cnt].format = format_c;
- *dci_cnt = *dci_cnt + 1;
- *format_c_found = 1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
- }
- }
- }*/
+ // if (crc == si_rnti) {
+ // dci_alloc[*dci_cnt].format = format_si;
+ // *dci_cnt = *dci_cnt + 1;
+ // } else if (crc == p_rnti) {
+ // dci_alloc[*dci_cnt].format = format_p;
+ // *dci_cnt = *dci_cnt + 1;
+ // } else if (crc == ra_rnti) {
+ // dci_alloc[*dci_cnt].format = format_ra;
+ // // store first nCCE of group for PUCCH transmission of ACK/NAK
+ // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
+ // *dci_cnt = *dci_cnt + 1;
+ // } else if (crc == pdcch_vars[eNB_id]->crnti) {
+
+ // if ((mode & UL_DCI) && (format_c == format0)
+ // && ((dci_decoded_output[current_thread_id][0] & 0x80)
+ // == 0)) { // check if pdu is format 0 or 1A
+ // if (*format0_found == 0) {
+ // dci_alloc[*dci_cnt].format = format0;
+ // *format0_found = 1;
+ // *dci_cnt = *dci_cnt + 1;
+ // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
+ // }
+ // } else if (format_c == format0) { // this is a format 1A DCI
+ // dci_alloc[*dci_cnt].format = format1A;
+ // *dci_cnt = *dci_cnt + 1;
+ // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
+ // } else {
+ // // store first nCCE of group for PUCCH transmission of ACK/NAK
+ // if (*format_c_found == 0) {
+ // dci_alloc[*dci_cnt].format = format_c;
+ // *dci_cnt = *dci_cnt + 1;
+ // *format_c_found = 1;
+ // pdcch_vars[eNB_id]->nCCE[nr_tti_rx] = CCEind;
+ // }
+ // }
+ // }
//LOG_I(PHY,"DCI decoding CRNTI [format: %d, nCCE[nr_tti_rx: %d]: %d ], AggregationLevel %d \n",format_c, nr_tti_rx, pdcch_vars[eNB_id]->nCCE[nr_tti_rx],L2);
// memcpy(&dci_alloc[*dci_cnt].dci_pdu[0],dci_decoded_output,sizeof_bytes);
switch (1 << L) {
@@ -1478,1045 +1547,30 @@ void nr_dci_decoding_procedure0(int s,
printf("\n");
}
- /*
- if ( agregationLevel != 0xFF &&
- (format_c == format0 && m==0 && si_rnti != SI_RNTI))
- {
- //Only valid for OAI : Save some processing time when looking for DCI format0. From the log we see the DCI only on candidate 0.
- return;
- }
- */
+
+ // if ( agregationLevel != 0xFF &&
+ // (format_c == format0 && m==0 && si_rnti != SI_RNTI))
+ // {
+ // //Only valid for OAI : Save some processing time when looking for DCI format0. From the log we see the DCI only on candidate 0.
+ // return;
+ // }
+
} // candidate loop
LOG_DDD("end candidate loop\n");
}
-
-#endif
-
-
-
-
-
-/*void dci_decoding_procedure0(NR_UE_PDCCH **pdcch_vars,
- int do_common,
- dci_detect_mode_t mode,
- uint8_t nr_tti_rx,
- DCI_ALLOC_t *dci_alloc,
- int16_t eNB_id,
- uint8_t current_thread_id,
- NR_DL_FRAME_PARMS *frame_parms,
- uint8_t mi,
- uint16_t si_rnti,
- uint16_t ra_rnti,
- uint16_t p_rnti,
- uint8_t L,
- uint8_t format_si,
- uint8_t format_p,
- uint8_t format_ra,
- uint8_t format_c,
- uint8_t sizeof_bits,
- uint8_t sizeof_bytes,
- uint8_t *dci_cnt,
- uint8_t *format0_found,
- uint8_t *format_c_found,
- uint32_t *CCEmap0,
- uint32_t *CCEmap1,
- uint32_t *CCEmap2)
- {
-
- uint16_t crc,CCEind,nCCE;
- uint32_t *CCEmap=NULL,CCEmap_mask=0;
- int L2=(1<<L);
- unsigned int Yk,nb_candidates = 0,i,m;
- unsigned int CCEmap_cand;
- #ifdef NR_PDCCH_DCI_DEBUG
- LOG_DDD("\n");
- #endif
- nCCE = get_nCCE(pdcch_vars[eNB_id]->num_pdcch_symbols,frame_parms,mi);
-
- if (nCCE > get_nCCE(3,frame_parms,1)) {
- LOG_D(PHY,"skip DCI decoding: nCCE=%d > get_nCCE(3,frame_parms,1)=%d\n", nCCE, get_nCCE(3,frame_parms,1));
- return;
- }
-
- if (nCCE<L2) {
- LOG_D(PHY,"skip DCI decoding: nCCE=%d < L2=%d\n", nCCE, L2);
- return;
- }
-
- if (mode == NO_DCI) {
- LOG_D(PHY, "skip DCI decoding: expect no DCIs at nr_tti_rx %d\n", nr_tti_rx);
- return;
- }
-
- if (do_common == 1) {
- nb_candidates = (L2==4) ? 4 : 2;
- Yk=0;
- } else {
- // Find first available in ue specific search space
- // according to procedure in Section 9.1.1 of 36.213 (v. 8.6)
- // compute Yk
- Yk = (unsigned int)pdcch_vars[eNB_id]->crnti;
-
- for (i=0; i<=nr_tti_rx; i++)
- Yk = (Yk*39827)%65537;
-
- Yk = Yk % (nCCE/L2);
-
- switch (L2) {
- case 1:
- case 2:
- nb_candidates = 6;
- break;
-
- case 4:
- case 8:
- nb_candidates = 2;
- break;
-
- default:
- DevParam(L2, do_common, eNB_id);
- break;
- }
- }
-
- // for (CCEind=0;
- // CCEind<nCCE2;
- // CCEind+=(1<<L)) {
-
- if (nb_candidates*L2 > nCCE)
- nb_candidates = nCCE/L2;
-
- for (m=0; m<nb_candidates; m++) {
-
- CCEind = (((Yk+m)%(nCCE/L2))*L2);
-
- if (CCEind<32)
- CCEmap = CCEmap0;
- else if (CCEind<64)
- CCEmap = CCEmap1;
- else if (CCEind<96)
- CCEmap = CCEmap2;
- else {
- LOG_E(PHY,"Illegal CCEind %d (Yk %d, m %d, nCCE %d, L2 %d\n",CCEind,Yk,m,nCCE,L2);
- mac_xface->macphy_exit("Illegal CCEind\n");
- return; // not reached
- }
-
- switch (L2) {
- case 1:
- CCEmap_mask = (1<<(CCEind&0x1f));
- break;
-
- case 2:
- CCEmap_mask = (3<<(CCEind&0x1f));
- break;
-
- case 4:
- CCEmap_mask = (0xf<<(CCEind&0x1f));
- break;
-
- case 8:
- CCEmap_mask = (0xff<<(CCEind&0x1f));
- break;
-
- default:
- LOG_E( PHY, "Illegal L2 value %d\n", L2 );
- mac_xface->macphy_exit( "Illegal L2\n" );
- return; // not reached
- }
-
- CCEmap_cand = (*CCEmap)&CCEmap_mask;
-
- // CCE is not allocated yet
-
- if (CCEmap_cand == 0) {
- #ifdef DEBUG_DCI_DECODING
-
- if (do_common == 1)
- LOG_I(PHY,"[DCI search nPdcch %d - common] Attempting candidate %d Aggregation Level %d DCI length %d at CCE %d/%d (CCEmap %x,CCEmap_cand %x)\n",
- pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask);
- else
- LOG_I(PHY,"[DCI search nPdcch %d - ue spec] Attempting candidate %d Aggregation Level %d DCI length %d at CCE %d/%d (CCEmap %x,CCEmap_cand %x) format %d\n",
- pdcch_vars[eNB_id]->num_pdcch_symbols,m,L2,sizeof_bits,CCEind,nCCE,*CCEmap,CCEmap_mask,format_c);
-
- #endif
-
- dci_decoding(sizeof_bits,
- L,
- &pdcch_vars[eNB_id]->e_rx[CCEind*72],
- &dci_decoded_output[current_thread_id][0]);
-
- // for (i=0;i<3+(sizeof_bits>>3);i++)
- // printf("dci_decoded_output[%d] => %x\n",i,dci_decoded_output[i]);
-
- crc = (crc16(&dci_decoded_output[current_thread_id][0],sizeof_bits)>>16) ^ extract_crc(&dci_decoded_output[current_thread_id][0],sizeof_bits);
- #ifdef DEBUG_DCI_DECODING
- printf("crc =>%x\n",crc);
- #endif
-
- if (((L>1) && ((crc == si_rnti)|| (crc == p_rnti)|| (crc == ra_rnti)))||
- (crc == pdcch_vars[eNB_id]->crnti)) {
- dci_alloc[*dci_cnt].dci_length = sizeof_bits;
- dci_alloc[*dci_cnt].rnti = crc;
- dci_alloc[*dci_cnt].L = L;
- dci_alloc[*dci_cnt].firstCCE = CCEind;
-
- //printf("DCI FOUND !!! crc =>%x, sizeof_bits %d, sizeof_bytes %d \n",crc, sizeof_bits, sizeof_bytes);
- if (sizeof_bytes<=4) {
- dci_alloc[*dci_cnt].dci_pdu[3] = dci_decoded_output[current_thread_id][0];
- dci_alloc[*dci_cnt].dci_pdu[2] = dci_decoded_output[current_thread_id][1];
- dci_alloc[*dci_cnt].dci_pdu[1] = dci_decoded_output[current_thread_id][2];
- dci_alloc[*dci_cnt].dci_pdu[0] = dci_decoded_output[current_thread_id][3];
- #ifdef DEBUG_DCI_DECODING
- printf("DCI => %x,%x,%x,%x\n",dci_decoded_output[current_thread_id][0],
- dci_decoded_output[current_thread_id][1],
- dci_decoded_output[current_thread_id][2],
- dci_decoded_output[current_thread_id][3]);
- #endif
- } else {
- dci_alloc[*dci_cnt].dci_pdu[7] = dci_decoded_output[current_thread_id][0];
- dci_alloc[*dci_cnt].dci_pdu[6] = dci_decoded_output[current_thread_id][1];
- dci_alloc[*dci_cnt].dci_pdu[5] = dci_decoded_output[current_thread_id][2];
- dci_alloc[*dci_cnt].dci_pdu[4] = dci_decoded_output[current_thread_id][3];
- dci_alloc[*dci_cnt].dci_pdu[3] = dci_decoded_output[current_thread_id][4];
- dci_alloc[*dci_cnt].dci_pdu[2] = dci_decoded_output[current_thread_id][5];
- dci_alloc[*dci_cnt].dci_pdu[1] = dci_decoded_output[current_thread_id][6];
- dci_alloc[*dci_cnt].dci_pdu[0] = dci_decoded_output[current_thread_id][7];
- #ifdef DEBUG_DCI_DECODING
- printf("DCI => %x,%x,%x,%x,%x,%x,%x,%x\n",
- dci_decoded_output[current_thread_id][0],dci_decoded_output[current_thread_id][1],dci_decoded_output[current_thread_id][2],dci_decoded_output[current_thread_id][3],
- dci_decoded_output[current_thread_id][4],dci_decoded_output[current_thread_id][5],dci_decoded_output[current_thread_id][6],dci_decoded_output[current_thread_id][7]);
- #endif
- }
-
- if (crc==si_rnti) {
- dci_alloc[*dci_cnt].format = format_si;
- *dci_cnt = *dci_cnt+1;
- } else if (crc==p_rnti) {
- dci_alloc[*dci_cnt].format = format_p;
- *dci_cnt = *dci_cnt+1;
- } else if (crc==ra_rnti) {
- dci_alloc[*dci_cnt].format = format_ra;
- // store first nCCE of group for PUCCH transmission of ACK/NAK
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind;
- *dci_cnt = *dci_cnt+1;
- } else if (crc==pdcch_vars[eNB_id]->crnti) {
-
- if ((mode&UL_DCI)&&(format_c == format0)&&((dci_decoded_output[current_thread_id][0]&0x80)==0)) {// check if pdu is format 0 or 1A
- if (*format0_found == 0) {
- dci_alloc[*dci_cnt].format = format0;
- *format0_found = 1;
- *dci_cnt = *dci_cnt+1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind;
- }
- } else if (format_c == format0) { // this is a format 1A DCI
- dci_alloc[*dci_cnt].format = format1A;
- *dci_cnt = *dci_cnt+1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind;
- } else {
- // store first nCCE of group for PUCCH transmission of ACK/NAK
- if (*format_c_found == 0) {
- dci_alloc[*dci_cnt].format = format_c;
- *dci_cnt = *dci_cnt+1;
- *format_c_found = 1;
- pdcch_vars[eNB_id]->nCCE[nr_tti_rx]=CCEind;
- }
- }
- }
-
- //LOG_I(PHY,"DCI decoding CRNTI [format: %d, nCCE[nr_tti_rx: %d]: %d ], AggregationLevel %d \n",format_c, nr_tti_rx, pdcch_vars[eNB_id]->nCCE[nr_tti_rx],L2);
- // memcpy(&dci_alloc[*dci_cnt].dci_pdu[0],dci_decoded_output,sizeof_bytes);
-
-
-
- switch (1<<L) {
- case 1:
- *CCEmap|=(1<<(CCEind&0x1f));
- break;
-
- case 2:
- *CCEmap|=(1<<(CCEind&0x1f));
- break;
-
- case 4:
- *CCEmap|=(1<<(CCEind&0x1f));
- break;
-
- case 8:
- *CCEmap|=(1<<(CCEind&0x1f));
- break;
- }
-
- #ifdef DEBUG_DCI_DECODING
- LOG_I(PHY,"[DCI search] Found DCI %d rnti %x Aggregation %d length %d format %s in CCE %d (CCEmap %x) candidate %d / %d \n",
- *dci_cnt,crc,1<<L,sizeof_bits,dci_format_strings[dci_alloc[*dci_cnt-1].format],CCEind,*CCEmap,m,nb_candidates );
- dump_dci(frame_parms,&dci_alloc[*dci_cnt-1]);
-
- #endif
- return;
- } // rnti match
- } // CCEmap_cand == 0
-
- // if ( agregationLevel != 0xFF &&
- // (format_c == format0 && m==0 && si_rnti != SI_RNTI))
- // {
- // //Only valid for OAI : Save some processing time when looking for DCI format0. From the log we see the DCI only on candidate 0.
- // return;
- // }
-
- } // candidate loop
- }
-
- uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_NR_UE *ue,
- DCI_ALLOC_t *dci_alloc,
- uint8_t DCIFormat,
- uint8_t agregationLevel,
- int16_t eNB_id,
- uint8_t nr_tti_rx)
- {
-
- uint8_t dci_cnt=0,old_dci_cnt=0;
- uint32_t CCEmap0=0,CCEmap1=0,CCEmap2=0;
- NR_UE_PDCCH **pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]];
- NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
- uint8_t mi = get_mi(&ue->frame_parms,nr_tti_rx);
- uint16_t ra_rnti=99;
- uint8_t format0_found=0,format_c_found=0;
- uint8_t tmode = ue->transmission_mode[eNB_id];
- uint8_t frame_type = frame_parms->frame_type;
- uint8_t format0_size_bits=0,format0_size_bytes=0;
- uint8_t format1_size_bits=0,format1_size_bytes=0;
- dci_detect_mode_t mode = dci_detect_mode_select(&ue->frame_parms,nr_tti_rx);
-
- switch (frame_parms->N_RB_DL) {
- case 6:
- if (frame_type == TDD) {
- format0_size_bits = sizeof_DCI0_1_5MHz_TDD_1_6_t;
- format0_size_bytes = sizeof(DCI0_1_5MHz_TDD_1_6_t);
- format1_size_bits = sizeof_DCI1_1_5MHz_TDD_t;
- format1_size_bytes = sizeof(DCI1_1_5MHz_TDD_t);
-
- } else {
- format0_size_bits = sizeof_DCI0_1_5MHz_FDD_t;
- format0_size_bytes = sizeof(DCI0_1_5MHz_FDD_t);
- format1_size_bits = sizeof_DCI1_1_5MHz_FDD_t;
- format1_size_bytes = sizeof(DCI1_1_5MHz_FDD_t);
- }
-
- break;
-
- case 25:
- default:
- if (frame_type == TDD) {
- format0_size_bits = sizeof_DCI0_5MHz_TDD_1_6_t;
- format0_size_bytes = sizeof(DCI0_5MHz_TDD_1_6_t);
- format1_size_bits = sizeof_DCI1_5MHz_TDD_t;
- format1_size_bytes = sizeof(DCI1_5MHz_TDD_t);
- } else {
- format0_size_bits = sizeof_DCI0_5MHz_FDD_t;
- format0_size_bytes = sizeof(DCI0_5MHz_FDD_t);
- format1_size_bits = sizeof_DCI1_5MHz_FDD_t;
- format1_size_bytes = sizeof(DCI1_5MHz_FDD_t);
- }
-
- break;
-
- case 50:
- if (frame_type == TDD) {
- format0_size_bits = sizeof_DCI0_10MHz_TDD_1_6_t;
- format0_size_bytes = sizeof(DCI0_10MHz_TDD_1_6_t);
- format1_size_bits = sizeof_DCI1_10MHz_TDD_t;
- format1_size_bytes = sizeof(DCI1_10MHz_TDD_t);
-
- } else {
- format0_size_bits = sizeof_DCI0_10MHz_FDD_t;
- format0_size_bytes = sizeof(DCI0_10MHz_FDD_t);
- format1_size_bits = sizeof_DCI1_10MHz_FDD_t;
- format1_size_bytes = sizeof(DCI1_10MHz_FDD_t);
- }
-
- break;
-
- case 100:
- if (frame_type == TDD) {
- format0_size_bits = sizeof_DCI0_20MHz_TDD_1_6_t;
- format0_size_bytes = sizeof(DCI0_20MHz_TDD_1_6_t);
- format1_size_bits = sizeof_DCI1_20MHz_TDD_t;
- format1_size_bytes = sizeof(DCI1_20MHz_TDD_t);
- } else {
- format0_size_bits = sizeof_DCI0_20MHz_FDD_t;
- format0_size_bytes = sizeof(DCI0_20MHz_FDD_t);
- format1_size_bits = sizeof_DCI1_20MHz_FDD_t;
- format1_size_bytes = sizeof(DCI1_20MHz_FDD_t);
- }
-
- break;
- }
-
- if (ue->prach_resources[eNB_id])
- ra_rnti = ue->prach_resources[eNB_id]->ra_RNTI;
-
- // Now check UE_SPEC format0/1A ue_spec search spaces at aggregation 8
- dci_decoding_procedure0(pdcch_vars,0,mode,
- nr_tti_rx,
- dci_alloc,
- eNB_id,
- ue->current_thread_id[nr_tti_rx],
- frame_parms,
- mi,
- ((ue->decode_SIB == 1) ? SI_RNTI : 0),
- ra_rnti,
- P_RNTI,
- agregationLevel,
- format1A,
- format1A,
- format1A,
- format0,
- format0_size_bits,
- format0_size_bytes,
- &dci_cnt,
- &format0_found,
- &format_c_found,
- &CCEmap0,
- &CCEmap1,
- &CCEmap2);
-
- if ((CCEmap0==0xffff)||
- ((format0_found==1)&&(format_c_found==1)))
- return(dci_cnt);
-
- if (DCIFormat == 1)
- {
- if ((tmode < 3) || (tmode == 7)) {
- //printf("Crnti decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat);
-
- // Now check UE_SPEC format 1 search spaces at aggregation 1
-
- //printf("[DCI search] Format 1/1A aggregation 1\n");
-
- old_dci_cnt=dci_cnt;
- dci_decoding_procedure0(pdcch_vars,0,mode,nr_tti_rx,
- dci_alloc,
- eNB_id,
- ue->current_thread_id[nr_tti_rx],
- frame_parms,
- mi,
- ((ue->decode_SIB == 1) ? SI_RNTI : 0),
- ra_rnti,
- P_RNTI,
- 0,
- format1A,
- format1A,
- format1A,
- format1,
- format1_size_bits,
- format1_size_bytes,
- &dci_cnt,
- &format0_found,
- &format_c_found,
- &CCEmap0,
- &CCEmap1,
- &CCEmap2);
-
- if ((CCEmap0==0xffff) ||
- (format_c_found==1))
- return(dci_cnt);
-
- if (dci_cnt>old_dci_cnt)
- return(dci_cnt);
-
- //printf("Crnti 1 decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat);
-
- }
- else
- {
- AssertFatal(0,"Other Transmission mode not yet coded\n");
- }
- }
- else
- {
- AssertFatal(0,"DCI format %d not yet implemented \n",DCIFormat);
- }
-
- return(dci_cnt);
-
- }
*/
-
-#ifdef NR_PDCCH_DCI_RUN
-
-uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue,
- uint16_t eNB_id,
- uint8_t nr_tti_rx,
- int p,
- crc_scrambled_t crc_scrambled,
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint8_t format) {
- LOG_DDD("crc_scrambled=%d, n_RB_ULBWP=%d, n_RB_DLBWP=%d\n",crc_scrambled,n_RB_ULBWP,n_RB_DLBWP);
- /*
- * function nr_dci_format_size calculates and returns the size in bits of a determined format
- * it also returns an bi-dimensional array 'dci_fields_sizes' with x rows and y columns, where:
- * x is the number of fields defined in TS 38.212 subclause 7.3.1 (Each field is mapped in the order in which it appears in the description in the specification)
- * y is the number of formats
- * e.g.: dci_fields_sizes[10][0] contains the size in bits of the field FREQ_DOM_RESOURCE_ASSIGNMENT_UL for format 0_0
- */
- // pdsch_config contains the PDSCH-Config IE is used to configure the UE specific PDSCH parameters (TS 38.331)
- PDSCH_Config_t pdsch_config = ue->PDSCH_Config;
- // pusch_config contains the PUSCH-Config IE is used to configure the UE specific PUSCH parameters (TS 38.331)
- PUSCH_Config_t pusch_config = ue->pusch_config;
- PUCCH_Config_t pucch_config_dedicated = ue->pucch_config_dedicated_nr[eNB_id];
- crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig = ue->crossCarrierSchedulingConfig;
- dmrs_UplinkConfig_t dmrs_UplinkConfig = ue->dmrs_UplinkConfig;
- dmrs_DownlinkConfig_t dmrs_DownlinkConfig = ue->dmrs_DownlinkConfig;
- csi_MeasConfig_t csi_MeasConfig = ue->csi_MeasConfig;
- PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig= ue->PUSCH_ServingCellConfig;
- PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig= ue->PDSCH_ServingCellConfig;
- NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id];
- // 1 CARRIER_IN
- // crossCarrierSchedulingConfig from higher layers, variable crossCarrierSchedulingConfig indicates if 'cross carrier scheduling' is enabled or not:
- // if No cross carrier scheduling: number of bits for CARRIER_IND is 0
- // if Cross carrier scheduling: number of bits for CARRIER_IND is 3
- // The IE CrossCarrierSchedulingConfig is used to specify the configuration when the cross-carrier scheduling is used in a cell
- uint8_t crossCarrierSchedulingConfig_ind = 0;
-
- if (crossCarrierSchedulingConfig.schedulingCellInfo.other.cif_InSchedulingCell !=0 ) crossCarrierSchedulingConfig_ind=1;
-
- // 2 SUL_IND_0_1, // 40 SRS_REQUEST, // 50 SUL_IND_0_0
- // UL/SUL indicator (TS 38.331, supplementary uplink is indicated in higher layer parameter ServCellAdd-SUL from IE ServingCellConfig and ServingCellConfigCommon):
- // 0 bit for UEs not configured with SUL in the cell or UEs configured with SUL in the cell but only PUCCH carrier in the cell is configured for PUSCH transmission
- // 1 bit for UEs configured with SUL in the cell as defined in Table 7.3.1.1.1-1
- // sul_ind indicates whether SUL is configured in cell or not
- uint8_t sul_ind=ue->supplementaryUplink.supplementaryUplink; // this value will be 0 or 1 depending on higher layer parameter ServCellAdd-SUL. FIXME!!!
- // 7 BANDWIDTH_PART_IND
- // number of UL BWPs configured by higher layers
- uint8_t n_UL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!!
- n_UL_BWP_RRC = ((n_UL_BWP_RRC > 3)?n_UL_BWP_RRC:(n_UL_BWP_RRC+1));
- // number of DL BWPs configured by higher layers
- uint8_t n_DL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!!
- n_DL_BWP_RRC = ((n_DL_BWP_RRC > 3)?n_DL_BWP_RRC:(n_DL_BWP_RRC+1));
- // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL
- // if format0_0, only resource allocation type 1 is allowed
- // if format0_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 6.1.2.2.1
- // for PUSCH hopping with resource allocation type 1
- // n_UL_hopping = 1 if the higher layer parameter frequencyHoppingOffsetLists contains two offset values
- // n_UL_hopping = 2 if the higher layer parameter frequencyHoppingOffsetLists contains four offset values
- uint8_t n_UL_hopping=pusch_config.n_frequencyHoppingOffsetLists;
-
- if (n_UL_hopping == 2) {
- n_UL_hopping = 1;
- } else if (n_UL_hopping == 4) {
- n_UL_hopping = 2;
- } else {
- n_UL_hopping = 0;
- }
-
- ul_resourceAllocation_t ul_resource_allocation_type = pusch_config.ul_resourceAllocation;
- uint8_t ul_res_alloc_type_0 = 0;
- uint8_t ul_res_alloc_type_1 = 0;
-
- if (ul_resource_allocation_type == ul_resourceAllocationType0) ul_res_alloc_type_0 = 1;
-
- if (ul_resource_allocation_type == ul_resourceAllocationType1) ul_res_alloc_type_1 = 1;
-
- if (ul_resource_allocation_type == ul_dynamicSwitch) {
- ul_res_alloc_type_0 = 1;
- ul_res_alloc_type_1 = 1;
- }
-
- uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp;
-
- if (ul_res_alloc_type_0 == 1) { // implementation of Table 6.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1
- // config1: PUSCH-Config IE contains rbg-Size ENUMERATED {config1 config2}
- ul_rgb_Size_t config = pusch_config.ul_rgbSize;
- uint8_t nominal_RBG_P = (config==ul_rgb_config1?2:4);
-
- if (n_RB_ULBWP > 36) nominal_RBG_P = (config==ul_rgb_config1?4:8);
-
- if (n_RB_ULBWP > 72) nominal_RBG_P = (config==ul_rgb_config1?8:16);
-
- if (n_RB_ULBWP > 144) nominal_RBG_P = 16;
-
- n_bits_freq_dom_res_assign_ul = (uint8_t)ceil((n_RB_ULBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0???
- n_ul_RGB_tmp = n_bits_freq_dom_res_assign_ul;
- }
-
- if (ul_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_ul = (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping;
-
- if ((ul_res_alloc_type_0 == 1) && (ul_res_alloc_type_1 == 1))
- n_bits_freq_dom_res_assign_ul = ((n_bits_freq_dom_res_assign_ul>n_ul_RGB_tmp)?(n_bits_freq_dom_res_assign_ul+1):(n_ul_RGB_tmp+1));
-
- // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL
- // if format1_0, only resource allocation type 1 is allowed
- // if format1_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 5.1.2.2.1
- dl_resourceAllocation_t dl_resource_allocation_type = pdsch_config.dl_resourceAllocation;
- uint8_t dl_res_alloc_type_0 = 0;
- uint8_t dl_res_alloc_type_1 = 0;
-
- if (dl_resource_allocation_type == dl_resourceAllocationType0) dl_res_alloc_type_0 = 1;
-
- if (dl_resource_allocation_type == dl_resourceAllocationType1) dl_res_alloc_type_1 = 1;
-
- if (dl_resource_allocation_type == dl_dynamicSwitch) {
- dl_res_alloc_type_0 = 1;
- dl_res_alloc_type_1 = 1;
- }
-
- uint8_t n_bits_freq_dom_res_assign_dl=0,n_dl_RGB_tmp;
-
- if (dl_res_alloc_type_0 == 1) { // implementation of Table 5.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1
- // config1: PDSCH-Config IE contains rbg-Size ENUMERATED {config1, config2}
- dl_rgb_Size_t config = pdsch_config.dl_rgbSize;
- uint8_t nominal_RBG_P = (config==dl_rgb_config1?2:4);
-
- if (n_RB_DLBWP > 36) nominal_RBG_P = (config==dl_rgb_config1?4:8);
-
- if (n_RB_DLBWP > 72) nominal_RBG_P = (config==dl_rgb_config1?8:16);
-
- if (n_RB_DLBWP > 144) nominal_RBG_P = 16;
-
- n_bits_freq_dom_res_assign_dl = (uint8_t)ceil((n_RB_DLBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0???
- n_dl_RGB_tmp = n_bits_freq_dom_res_assign_dl;
- }
-
- if (dl_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_dl = (uint8_t)(ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)));
-
- if ((dl_res_alloc_type_0 == 1) && (dl_res_alloc_type_1 == 1))
- n_bits_freq_dom_res_assign_dl = ((n_bits_freq_dom_res_assign_dl>n_dl_RGB_tmp)?(n_bits_freq_dom_res_assign_dl+1):(n_dl_RGB_tmp+1));
-
- // 12 TIME_DOM_RESOURCE_ASSIGNMENT
- uint8_t pusch_alloc_list = pusch_config.n_push_alloc_list;
- uint8_t pdsch_alloc_list = pdsch_config.n_pdsh_alloc_list;
- // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
- static_bundleSize_t static_prb_BundlingType = pdsch_config.prbBundleType.staticBundling;
- bundleSizeSet1_t dynamic_prb_BundlingType1 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet1;
- bundleSizeSet2_t dynamic_prb_BundlingType2 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet2;
- uint8_t prb_BundlingType_size=0;
-
- if ((static_prb_BundlingType==st_n4)||(static_prb_BundlingType==st_wideband)) prb_BundlingType_size=0;
-
- if ((dynamic_prb_BundlingType1==dy_1_n4)||(dynamic_prb_BundlingType1==dy_1_wideband)||(dynamic_prb_BundlingType1==dy_1_n2_wideband)||(dynamic_prb_BundlingType1==dy_1_n4_wideband)||
- (dynamic_prb_BundlingType2==dy_2_n4)||(dynamic_prb_BundlingType2==dy_2_wideband)) prb_BundlingType_size=1;
-
- // 15 RATE_MATCHING_IND FIXME!!!
- // according to TS 38.212: Rate matching indicator – 0, 1, or 2 bits according to higher layer parameter rateMatchPattern
- uint8_t rateMatching_bits = pdsch_config.n_rateMatchPatterns;
- // 16 ZP_CSI_RS_TRIGGER FIXME!!!
- // 0, 1, or 2 bits as defined in Subclause 5.1.4.2 of [6, TS 38.214].
- // is the number of ZP CSI-RS resource sets in the higher layer parameter zp-CSI-RS-Resource
- uint8_t n_zp_bits = pdsch_config.n_zp_CSI_RS_ResourceId;
- // 17 FREQ_HOPPING_FLAG
- // freqHopping is defined by higher layer parameter frequencyHopping from IE PUSCH-Config. Values are ENUMERATED{mode1, mode2}
- frequencyHopping_t f_hopping = pusch_config.frequencyHopping;
- uint8_t freqHopping = 0;
-
- if ((f_hopping==f_hop_mode1)||(f_hopping==f_hop_mode2)) freqHopping = 1;
-
- // 28 DAI
- pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook = pdsch_config.pdsch_HARQ_ACK_Codebook;
- uint8_t n_dai = 0;
- uint8_t n_serving_cell_dl = 1; // this is hardcoded to 1 as we need to get this value from RRC higher layers parameters. FIXME!!!
-
- if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl == 1)) n_dai = 2;
-
- if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl > 1)) n_dai = 4;
-
- // 29 FIRST_DAI
- uint8_t codebook_HARQ_ACK = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI.
-
- if (pdsch_HARQ_ACK_Codebook == semiStatic) codebook_HARQ_ACK = 1;
-
- if (pdsch_HARQ_ACK_Codebook == dynamic) codebook_HARQ_ACK = 2;
-
- // 30 SECOND_DAI
- uint8_t n_HARQ_ACK_sub_codebooks = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. FIXME!!!
- // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND
- uint8_t pdsch_harq_t_ind = (uint8_t)ceil(log2(pucch_config_dedicated.dl_DataToUL_ACK[0]));
- // 36 SRS_RESOURCE_IND
- // n_SRS is the number of configured SRS resources in the SRS resource set associated with the higher layer parameter usage of value 'codeBook' or 'nonCodeBook'
- // from SRS_ResourceSet_t type we should get the information of the usage parameter (with possible values beamManagement, codebook, nonCodebook, antennaSwitching)
- // at frame_parms->srs_nr->p_SRS_ResourceSetList[]->usage
- uint8_t n_SRS = ue->srs.number_srs_Resource_Set;
- // 37 PRECOD_NBR_LAYERS
- // 38 ANTENNA_PORTS
- txConfig_t txConfig = pusch_config.txConfig;
- transformPrecoder_t transformPrecoder = pusch_config.transformPrecoder;
- codebookSubset_t codebookSubset = pusch_config.codebookSubset;
- uint8_t maxRank = pusch_config.maxRank;
- uint8_t num_antenna_ports = 1; // this is hardcoded. We need to get the real value FIXME!!!
- uint8_t precond_nbr_layers_bits = 0;
- uint8_t antenna_ports_bits_ul = 0;
-
- // searching number of bits at tables 7.3.1.1.2-2/3/4/5 from TS 38.212 subclause 7.3.1.1.2
- if (txConfig == txConfig_codebook) {
- if (num_antenna_ports == 4) {
- if ((transformPrecoder == transformPrecoder_disabled) && ((maxRank == 2)||(maxRank == 3)||(maxRank == 4))) { // Table 7.3.1.1.2-2
- if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=6;
-
- if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=5;
-
- if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=4;
- }
-
- if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-3
- if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=5;
-
- if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=4;
-
- if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2;
- }
- }
-
- if (num_antenna_ports == 2) {
- if ((transformPrecoder == transformPrecoder_disabled) && (maxRank == 2)) { // Table 7.3.1.1.2-4
- if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=4;
-
- if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2;
- }
-
- if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-5
- if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=3;
-
- if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=1;
- }
- }
- }
-
- if (txConfig == txConfig_nonCodebook) {
- }
-
- // searching number of bits at tables 7.3.1.1.2-6/7/8/9/10/11/12/13/14/15/16/17/18/19
- if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)) {
- if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 2;
-
- if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4;
-
- if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 3;
-
- if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4;
- }
-
- if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type2)) {
- if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 4;
-
- if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 5;
- }
-
- // for format 1_1 number of bits as defined by Tables 7.3.1.2.2-1/2/3/4
- uint8_t antenna_ports_bits_dl = 0;
-
- if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 4; // Table 7.3.1.2.2-1
-
- if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-2
-
- if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-3
-
- if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 6; // Table 7.3.1.2.2-4
-
- // 39 TCI
- uint8_t tci_bits=0;
-
- if (pdcch_vars2->coreset[p].tciPresentInDCI == tciPresentInDCI_enabled) tci_bits=3;
-
- // 42 CSI_REQUEST
- // reportTriggerSize is defined in the CSI-MeasConfig IE (TS 38.331).
- // Size of CSI request field in DCI (bits). Corresponds to L1 parameter 'ReportTriggerSize' (see 38.214, section 5.2)
- uint8_t reportTriggerSize = csi_MeasConfig.reportTriggerSize; // value from 0..6
- // 43 CBGTI
- // for format 0_1
- uint8_t maxCodeBlockGroupsPerTransportBlock = 0;
-
- if (PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock != 0)
- maxCodeBlockGroupsPerTransportBlock = (uint8_t)PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock;
-
- // for format 1_1, as defined in Subclause 5.1.7 of [6, TS38.214]
- uint8_t maxCodeBlockGroupsPerTransportBlock_dl = 0;
-
- if (PDSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock_dl != 0)
- maxCodeBlockGroupsPerTransportBlock_dl = pdsch_config.maxNrofCodeWordsScheduledByDCI; // FIXME!!!
-
- // 44 CBGFI
- uint8_t cbgfi_bit = PDSCH_ServingCellConfig.codeBlockGroupFlushIndicator;
- // 45 PTRS_DMRS
- // 0 bit if PTRS-UplinkConfig is not configured and transformPrecoder=disabled, or if transformPrecoder=enabled, or if maxRank=1
- // 2 bits otherwise
- uint8_t ptrs_dmrs_bits=0; //FIXME!!!
- // 46 BETA_OFFSET_IND
- // at IE PUSCH-Config, beta_offset indicator – 0 if the higher layer parameter betaOffsets = semiStatic; otherwise 2 bits
- // uci-OnPUSCH
- // Selection between and configuration of dynamic and semi-static beta-offset. If the field is absent or released, the UE applies the value 'semiStatic' and the BetaOffsets
- uint8_t betaOffsets = 0;
-
- if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_semiStatic);
-
- if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_dynamic) betaOffsets = 2;
-
- // 47 DMRS_SEQ_INI
- uint8_t dmrs_seq_ini_bits_ul = 0;
- uint8_t dmrs_seq_ini_bits_dl = 0;
-
- //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-UplinkConfig
- if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.scramblingID0 != 0) && (dmrs_UplinkConfig.scramblingID1 != 0)) dmrs_seq_ini_bits_ul = 1;
-
- //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-DownlinkConfig
- if ((dmrs_DownlinkConfig.scramblingID0 != 0) && (dmrs_DownlinkConfig.scramblingID0 != 0)) dmrs_seq_ini_bits_dl = 1;
-
- /*
- * For format 2_2
- *
- * This format supports power control commands for semi-persistent scheduling.
- * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH)
- *
- * This format will be implemented in the future FIXME!!!
- *
- */
- // 5 BLOCK_NUMBER: The parameter tpc-PUSCH or tpc-PUCCH provided by higher layers determines the index to the block number for an UL of a cell
- // The following fields are defined for each block: Closed loop indicator and TPC command
- // 6 CLOSE_LOOP_IND
- // 41 TPC_CMD
- uint8_t tpc_cmd_bit_2_2 = 2;
- /*
- * For format 2_3
- *
- * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control
- * either because independent control is desirable or because the device is configured without PUCCH and PUSCH
- *
- * This format will be implemented in the future FIXME!!!
- *
- */
- // 40 SRS_REQUEST
- // 41 TPC_CMD
- uint8_t tpc_cmd_bit_2_3 = 0;
- uint8_t dci_field_size_table [NBR_NR_DCI_FIELDS][NBR_NR_FORMATS] = { // This table contains the number of bits for each field (row) contained in each dci format (column).
- // The values of the variables indicate field sizes in number of bits
- //Format0_0 Format0_1 Format1_0 Format1_1 Formats2_0/1/2/3
- {
- 1, 1, (((crc_scrambled == _p_rnti) || (crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti)) ? 0:1),
- 1, 0,0,0,0
- }, // 0 IDENTIFIER_DCI_FORMATS:
- {
- 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3),
- 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3),
- 0,0,0,0
- }, // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
- {0, (sul_ind == 0)?0:1, 0, 0, 0,0,0,0}, // 2 SUL_IND_0_1:
- {0, 0, 0, 0, 1,0,0,0}, // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
- {0, 0, 0, 0, 0,1,0,0}, // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
- {0, 0, 0, 0, 0,0,0,0}, // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
- {0, 0, 0, 0, 0,0,1,0}, // 6 CLOSE_LOOP_IND
- {
- 0, (uint8_t)ceil(log2(n_UL_BWP_RRC)),
- 0, (uint8_t)ceil(log2(n_DL_BWP_RRC)),
- 0,0,0,0
- }, // 7 BANDWIDTH_PART_IND:
- {
- 0, 0, ((crc_scrambled == _p_rnti) ? 2:0),
- 0, 0,0,0,0
- }, // 8 SHORT_MESSAGE_IND 2 bits if crc scrambled with P-RNTI
- {
- 0, 0, ((crc_scrambled == _p_rnti) ? 8:0),
- 0, 0,0,0,0
- }, // 9 SHORT_MESSAGES 8 bit8 if crc scrambled with P-RNTI
- {
- (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping,
- n_bits_freq_dom_res_assign_ul,
- 0, 0, 0,0,0,0
- }, // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- // (NOTE 1) If DCI format 0_0 is monitored in common search space
- // and if the number of information bits in the DCI format 0_0 prior to padding
- // is larger than the payload size of the DCI format 1_0 monitored in common search space
- // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
- // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
- {
- 0, 0, (uint8_t)ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)),
- n_bits_freq_dom_res_assign_dl,
- 0,0,0,0
- }, // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- {
- 4, (uint8_t)log2(pusch_alloc_list),
- 4, (uint8_t)log2(pdsch_alloc_list),
- 0,0,0,0
- }, // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- // where I the number of entries in the higher layer parameter pusch-AllocationList
- {
- 0, 0, 1, (((dl_res_alloc_type_0==1) &&(dl_res_alloc_type_1==0))?0:1),
- 0,0,0,0
- }, // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- {0, 0, 0, prb_BundlingType_size, 0,0,0,0}, // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
- {0, 0, 0, rateMatching_bits, 0,0,0,0}, // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
- {0, 0, 0, n_zp_bits, 0,0,0,0}, // 16 ZP_CSI_RS_TRIGGER:
- {
- 1, (((ul_res_alloc_type_0==1) &&(ul_res_alloc_type_1==0))||(freqHopping == 0))?0:1,
- 0, 0, 0,0,0,0
- }, // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- {0, 0, 0, 5, 0,0,0,0}, // 18 TB1_MCS:
- {0, 0, 0, 1, 0,0,0,0}, // 19 TB1_NDI:
- {0, 0, 0, 2, 0,0,0,0}, // 20 TB1_RV:
- {0, 0, 0, 5, 0,0,0,0}, // 21 TB2_MCS:
- {0, 0, 0, 1, 0,0,0,0}, // 22 TB2_NDI:
- {0, 0, 0, 2, 0,0,0,0}, // 23 TB2_RV:
- {5, 5, 5, 0, 0,0,0,0}, // 24 MCS:
- {1, 1, (crc_scrambled == _c_rnti)?1:0,0, 0,0,0,0}, // 25 NDI:
- {
- 2, 2, (((crc_scrambled == _c_rnti) || (crc_scrambled == _si_rnti)) ? 2:0),
- 0, 0,0,0,0
- }, // 26 RV:
- {4, 4, (crc_scrambled == _c_rnti)?4:0,4, 0,0,0,0}, // 27 HARQ_PROCESS_NUMBER:
- {0, 0, (crc_scrambled == _c_rnti)?2:0,n_dai, 0,0,0,0}, // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
- // 0 otherwise
- {0, codebook_HARQ_ACK, 0, 0, 0,0,0,0}, // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK // 2 bits for dynamic HARQ-ACK codebook with single HARQ-ACK codebook
- {
- 0, (((codebook_HARQ_ACK == 2) &&(n_HARQ_ACK_sub_codebooks==2))?2:0),
- 0, 0, 0,0,0,0
- }, // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks // 0 bits otherwise
- {
- 0, 0, (((crc_scrambled == _p_rnti) || (crc_scrambled == _ra_rnti)) ? 2:0),
- 0, 0,0,0,0
- }, // 31 TB_SCALING
- {2, 2, 0, 0, 0,0,0,0}, // 32 TPC_PUSCH:
- {0, 0, (crc_scrambled == _c_rnti)?2:0,2, 0,0,0,0}, // 33 TPC_PUCCH:
- {0, 0, (crc_scrambled == _c_rnti)?3:0,3, 0,0,0,0}, // 34 PUCCH_RESOURCE_IND:
- {0, 0, (crc_scrambled == _c_rnti)?3:0,pdsch_harq_t_ind, 0,0,0,0}, // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- {0, (uint8_t)log2(n_SRS), 0, 0, 0,0,0,0}, // 36 SRS_RESOURCE_IND:
- {0, precond_nbr_layers_bits, 0, 0, 0,0,0,0}, // 37 PRECOD_NBR_LAYERS:
- {0, antenna_ports_bits_ul, 0, antenna_ports_bits_dl, 0,0,0,0}, // 38 ANTENNA_PORTS:
- {0, 0, 0, tci_bits, 0,0,0,0}, // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
- {0, (sul_ind == 0)?2:3, 0, (sul_ind == 0)?2:3, 0,0,0,2}, // 40 SRS_REQUEST:
- {
- 0, 0, 0, 0, 0,0,tpc_cmd_bit_2_2,
- tpc_cmd_bit_2_3
- },
- // 41 TPC_CMD:
- {0, reportTriggerSize, 0, 0, 0,0,0,0}, // 42 CSI_REQUEST:
- {
- 0, maxCodeBlockGroupsPerTransportBlock,
- 0, maxCodeBlockGroupsPerTransportBlock_dl,
- 0,0,0,0
- }, // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
- {0, 0, 0, cbgfi_bit, 0,0,0,0}, // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
- {0, ptrs_dmrs_bits, 0, 0, 0,0,0,0}, // 45 PTRS_DMRS:
- {0, betaOffsets, 0, 0, 0,0,0,0}, // 46 BETA_OFFSET_IND:
- {0, dmrs_seq_ini_bits_ul, 0, dmrs_seq_ini_bits_dl, 0,0,0,0}, // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
- // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
- {0, 1, 0, 0, 0,0,0,0}, // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
- {0, 0, 0, 0, 0,0,0,0}, // 49 PADDING_NR_DCI:
- // (NOTE 2) If DCI format 0_0 is monitored in common search space
- // and if the number of information bits in the DCI format 0_0 prior to padding
- // is less than the payload size of the DCI format 1_0 monitored in common search space
- // zeros shall be appended to the DCI format 0_0
- // until the payload size equals that of the DCI format 1_0
- {(sul_ind == 0)?0:1, 0, 0, 0, 0,0,0,0}, // 50 SUL_IND_0_0:
- {0, 0, 0, 0, 0,0,0,0}, // 51 RA_PREAMBLE_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
- {0, 0, 0, 0, 0,0,0,0}, // 52 SUL_IND_1_0 (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
- {0, 0, 0, 0, 0,0,0,0}, // 53 SS_PBCH_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
- {0, 0, 0, 0, 0,0,0,0}, // 54 PRACH_MASK_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
- {
- 0, 0, ((crc_scrambled == _p_rnti)?6:(((crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti))?16:0)),
- 0, 0,0,0,0
- } // 55 RESERVED_NR_DCI
- };
- // NOTE 1: adjustments in freq_dom_resource_assignment_UL to be done if necessary
- // NOTE 2: adjustments in padding to be done if necessary
- uint8_t dci_size [8] = {0,0,0,0,0,0,0,0}; // will contain size for each format
-
- for (int i=0 ; i<NBR_NR_FORMATS ; i++) {
- //#ifdef NR_PDCCH_DCI_DEBUG
- // LOG_DDD("i=%d, j=%d\n", i, j);
- //#endif
- for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
- dci_size [i] = dci_size [i] + dci_field_size_table[j][i]; // dci_size[i] contains the size in bits of the dci pdu format i
- //if (i==(int)format-15) { // (int)format-15 indicates the position of each format in the table (e.g. format1_0=17 -> position in table is 2)
- dci_fields_sizes[j][i] = dci_field_size_table[j][i]; // dci_fields_sizes[j] contains the sizes of each field (j) for a determined format i
- //}
- }
-
- LOG_DDD("(nr_dci_format_size) dci_size[%d]=%d for n_RB_ULBWP=%d\n",
- i,dci_size[i],n_RB_ULBWP);
- }
-
- LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n");
-
-#ifdef NR_PDCCH_DCI_DEBUG
- for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
- printf("\t\t");
-
- for (int i=0; i<NBR_NR_FORMATS ; i++) printf("%d\t",dci_fields_sizes[j][i]);
-
- printf("\n");
- }
-
- printf(" }\n");
#endif
- LOG_DNL("(nr_dci_format_size) dci_size[0_0]=%d, dci_size[0_1]=%d, dci_size[1_0]=%d, dci_size[1_1]=%d,\n",dci_size[0],dci_size[1],dci_size[2],dci_size[3]);
-
- //UL/SUL indicator format0_0 (TS 38.212 subclause 7.3.1.1.1)
- // - 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding is larger than the number of bits for DCI format 0_0 before padding;
- // - 0 bit otherwise.
- // The UL/SUL indicator, if present, locates in the last bit position of DCI format 0_0, after the padding bit(s)
- if ((dci_field_size_table[SUL_IND_0_0][0] == 1) && (dci_size[0] > dci_size[2])) {
- dci_field_size_table[SUL_IND_0_0][0] = 0;
- dci_size[0]=dci_size[0]-1;
- }
- // if ((format == format0_0) || (format == format1_0)) {
- // According to Section 7.3.1.1.1 in TS 38.212
- // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding
- // is less than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell,
- // zeros shall be appended to the DCI format 0_0 until the payload size equals that of the DCI format 1_0.
- if (dci_size[0] < dci_size[2]) { // '0' corresponding to index for format0_0 and '2' corresponding to index of format1_0
- //if (format == format0_0) {
- dci_fields_sizes[PADDING_NR_DCI][0] = dci_size[2] - dci_size[0];
- dci_size[0] = dci_size[2];
- LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]);
- //}
- }
- // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding
- // is larger than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell,
- // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 is reduced
- // such that the size of DCI format 0_0 equals to the size of the DCI format 1_0..
- if (dci_size[0] > dci_size[2]) {
- //if (format == format0_0) {
- dci_fields_sizes[FREQ_DOM_RESOURCE_ASSIGNMENT_UL][0] -= (dci_size[0] - dci_size[2]);
- dci_size[0] = dci_size[2];
- LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]);
- //}
- }
- /*
- * TS 38.212 subclause 7.3.1.1.2
- * For a UE configured with SUL in a cell:
- * if PUSCH is configured to be transmitted on both the SUL and the non-SUL of the cell and
- * if the number of information bits in format 0_1 for the SUL
- * is not equal to the number of information bits in format 0_1 for the non-SUL,
- * zeros shall be appended to smaller format 0_1 until the payload size equals that of the larger format 0_1
- *
- * Not implemented. FIXME!!!
- *
- */
- // }
- LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n");
-#ifdef NR_PDCCH_DCI_DEBUG
- for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
- printf("\t\t");
- for (int i=0; i<NBR_NR_FORMATS ; i++) printf("%d\t",dci_fields_sizes[j][i]);
- printf("\n");
- }
- printf(" }\n");
-#endif
- return dci_size[format];
-}
-#endif
+#if 0
-#ifdef NR_PDCCH_DCI_RUN
uint8_t nr_dci_decoding_procedure(int s,
int p,
@@ -2845,6 +1899,3 @@ uint8_t nr_dci_decoding_procedure(int s,
}
#endif
-
-
-
diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
index 88e1884c1289abebda0d9ffad8b4ad82700bd832..17ecce714a6a654e280198b6f1c8aabc05872098 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
@@ -53,924 +53,11 @@
//#define DEBUG_DCI
#define NR_PDCCH_DCI_TOOLS
//#define NR_PDCCH_DCI_TOOLS_DEBUG
-#ifdef NR_PDCCH_DCI_TOOLS_DEBUG
-#define LOG_DCI_D(a...) printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) ->" a)
-#else
-#define LOG_DCI_D(a...)
-#endif
-#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a)
-
-typedef unsigned __int128 uint128_t;
-
-int8_t nr_delta_PUSCH_abs[4] = {-4,-1,1,4};
-int8_t nr_delta_PUSCH_acc[4] = {-1,0,1,3};
-int8_t *nr_delta_PUCCH_lut = nr_delta_PUSCH_acc;
-
-
-
-#ifdef NR_PDCCH_DCI_TOOLS
-
-uint16_t nr_dci_field(uint64_t dci_pdu[2],
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS],
- uint8_t dci_field) {
- int dci_size=0;
-
- for (int i=0; i<NBR_NR_DCI_FIELDS; i++) dci_size+=dci_fields_sizes[i];
-
- AssertFatal(dci_size<65,"DCI has %d > 64 bits, not supported for now\n",
- dci_size);
- uint16_t first_bit_position = dci_size;
-
- for (int i=0; i<=dci_field ; i++) {
- first_bit_position = first_bit_position - dci_fields_sizes[i];
- }
-
- /*uint16_t tmp1 = ((*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
- uint16_t tmp2 = 0;
- for (int i=0; i<dci_fields_sizes[dci_field]; i++)
- tmp2 |= ((tmp1>>i)&1)<<(dci_fields_sizes[dci_field]-i-1);*/
- return ((uint16_t)(*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
-}
-
-int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- lte_frame_type_t frame_type,
- uint8_t dci_length,
- uint16_t rnti,
- uint64_t dci_pdu[2],
- fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- NR_DCI_format_t dci_format,
- uint8_t nr_tti_rx,
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]) {
- /*
- * This function will extract the different elements of the dci pdu and interpret the values extracted to update correctly the parameters in:
- * NR_DL_UE_HARQ_t *pdlsch0_harq,
- * NR_UE_DLSCH_t *pdlsch0,
- *
- * We need to know the dci length and the dci_fields_sizes (array containing each field size in number of bits)
- * In order to get the value of a specific field we will proceed as follows (let's have a look to an example:
- * If the length of the pdu is 38 bits and the content of the dci_pdu is 0x3A8900789A (pdu is 11 1010 1000 1001 0000 0000 0111 1000 1001 1010)
- * If the dci_fields_sizes is {0 0 1 0 0 0 0 0 0 13 0 1 0 0 0 0 0 0 0 0 0 0 5 1 2 4 2 0 0 0 2 3 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...}
- * This means:
- * number bits for carrier_ind field is 0
- * number bits for sul_ind_0_1 field is 0
- * number bits for identifier_dci_formats field is 0
- * number bits for slot_format_ind field is 0
- * number bits for pre_emption_ind field is 0
- * ...
- * number bits for freq_dom_resource_assignment_DL field is 13
- * ...
- * number bits for padding is 0
- * In order to extract the information of (e.g.) freq_dom_resource_assignment_DL field,
- * we will do a left-shift of 1 position (because previous to this field, and according to the dci_fields_sizes array, there is only one non-empty field of size 1 bit) -> (1 1010 1000 1001 0000 0000 0111 1000 1001 1010 0)
- * then we will do a right-shit of dci_length-13 positions -> (1 1010 1000 1001). And this is the content of the freq_dom_resource_assignment_DL field
- *
- *
- * At the moment we have implemented the following formats:
- *
- * Format 0_0, that contains the following fields according to Specification 38.212 V15.1.1 Section 7.3.1
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 32 TPC_PUSCH:
- * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
- * 50 SUL_IND_0_0:
- *
- * Format 0_1, that contains the following fields
- * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 1 CARRIER_IND
- * 2 SUL_IND_0_1
- * 7 BANDWIDTH_PART_IND
- * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 29 FIRST_DAI
- * 30 SECOND_DAI
- * 32 TPC_PUSCH:
- * 36 SRS_RESOURCE_IND:
- * 37 PRECOD_NBR_LAYERS:
- * 38 ANTENNA_PORTS:
- * 40 SRS_REQUEST:
- * 42 CSI_REQUEST:
- * 43 CBGTI
- * 45 PTRS_DMRS
- * 46 BETA_OFFSET_IND
- * 47 DMRS_SEQ_INI
- * 48 UL_SCH_IND
- * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
- *
- * Format 1_0, that contains the following fields
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- * 34 PUCCH_RESOURCE_IND:
- * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- * 55 RESERVED_NR_DCI
- *
- * If the CRC of the DCI format 1_0 is scrambled by C-RNTI and the "Frequency domain resource assignment" field are of all ones,
- * the DCI format 1_0 is for random access procedure initiated by a PDCCH order.
- * This is not implemented, but the fields are already included: FIXME!!!
- *
- * with CRC scrambled by P-RNTI
- * 8 SHORT_MESSAGE_IND
- * 9 SHORT_MESSAGES
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 31 TB_SCALING
- * 55 RESERVED_NR_DCI
- *
- * with CRC scrambled by SI-RNTI
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 26 RV:
- * 55 RESERVED_NR_DCI
- *
- * with CRC scrambled by RA-RNTI
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 31 TB_SCALING
- * 55 RESERVED_NR_DCI
- *
- * with CRC scrambled by TC-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- *
- * Format 1_1, that contains the following fields
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 1 CARRIER_IND:
- * 7 BANDWIDTH_PART_IND:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 14 PRB_BUNDLING_SIZE_IND:
- * 15 RATE_MATCHING_IND:
- * 16 ZP_CSI_RS_TRIGGER:
- * 18 TB1_MCS:
- * 19 TB1_NDI:
- * 20 TB1_RV:
- * 21 TB2_MCS:
- * 22 TB2_NDI:
- * 23 TB2_RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- * 34 PUCCH_RESOURCE_IND:
- * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- * 38 ANTENNA_PORTS:
- * 39 TCI:
- * 40 SRS_REQUEST:
- * 43 CBGTI:
- * 44 CBGFI:
- * 47 DMRS_SEQ_INI:
- *
- * We have not implemented the following formats:
- *
- * Format 2_0
- * Used for notifying the slot format
- *
- * Format 2_1
- * Used for notifying the PRB(s) and OFDM symbol(s) where UE may assume no transmission is intended for the UE
- *
- * Format 2_2
- * This format supports power control commands for semi-persistent scheduling.
- * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH)
- * This format will be implemented in the future FIXME!!!
- *
- * Format 2_3
- * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control
- * either because independent control is desirable or because the device is configured without PUCCH and PUSCH
- * This format will be implemented in the future FIXME!!!
- *
- */
- uint8_t dci_fields_sizes_format[NBR_NR_DCI_FIELDS] = {0};
-
- for (int m=0; m<NBR_NR_DCI_FIELDS; m++) dci_fields_sizes_format[m]=dci_fields_sizes[m][dci_format];
-
- // uint64_t pdu_bitmap = 0xFFFFFFFFFFFFFFFF;
- // uint128_t pdu_bitmap = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
- //#define DCI_MAX_SIZE 128
- // pdu_bitmap = (pdu_bitmap << (DCI_MAX_SIZE - dci_length)) >> (DCI_MAX_SIZE - dci_length); // this variable will help to remove the bits of other fields when left-switching
- uint8_t dci_field=0;
- // uint8_t sizes_count=0;
- // uint8_t left_shift=0;
- LOG_DCI_D("Entering function nr_extract_dci_info() with dci_pdu=%lx %lx dci_length=%d\n",
- dci_pdu[0],dci_pdu[1], dci_length);
- LOG_DCI_D("for format %d, dci_fields_sizes {",dci_format);
-#ifdef NR_PDCCH_DCI_TOOLS_DEBUG
-
- for (int i=0; i<NBR_NR_DCI_FIELDS; i++) printf("%d ",dci_fields_sizes[i][dci_format]);
-
- printf("}\n");
-#endif
-
- // uint8_t prev_ndi = pdlsch0_harq->DCINdi;
-
- /*
- * Some dci fields need to be interpreted before the others.
- */
- if (dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format] != 0) { // E.g: 27 HARQ_PROCESS_NUMBER (27 is the position in dci_fields_sizes array for field HARQ_PROCESS_NUMBER)
- //for (int i=0; i<=HARQ_PROCESS_NUMBER; i++) left_shift = left_shift + dci_fields_sizes[i][dci_format];
- nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,HARQ_PROCESS_NUMBER);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format]));
- //left_shift = 0;
- LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number);
- }
-
- /*
- if ((dci_format == format1_0) || (dci_format == format1_1)) {
- if (rnti==crc_scrambled_values[_SI_RNTI_]) {
- ue->dlsch_SI[eNB_id]->active = 1;
- } else if (rnti==crc_scrambled_values[_P_RNTI_]) {
- ue->dlsch_p[eNB_id]->active = 1;
- } else if (rnti==crc_scrambled_values[_RA_RNTI_]) {
- ue->dlsch_ra[eNB_id]->active = 1;
- } else {
- pdlsch0->active = 1;
- }
- pdlsch0->rnti = rnti;
- pdlsch0_harq->codeword = 0;
- pdlsch0_harq->Nl = 1;
- // pdlsch0_harq->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI;
- pdlsch0_harq->dl_power_off = 1; //no power offset
-
- if ((rnti==crc_scrambled_values[_SI_RNTI_]) || (rnti==crc_scrambled_values[_P_RNTI_]) || (rnti==crc_scrambled_values[_RA_RNTI_])) {
- pdlsch0_harq->round = 0;
- pdlsch0_harq->status = ACTIVE;
- } else {
- }
- }
- */
- for (dci_field=0; dci_field<NBR_NR_DCI_FIELDS; dci_field++) {
- //left_shift = left_shift + dci_fields_sizes[dci_field][dci_format];
- if (dci_fields_sizes[dci_field][dci_format] != 0) {
- //sizes_count = dci_fields_sizes[dci_field][dci_format];
- LOG_DCI_D("dci_fields_sizes[%d][%d] = %d\n",dci_field,dci_format,dci_fields_sizes[dci_field][dci_format]);
-
- switch (dci_field) {
- case IDENTIFIER_DCI_FORMATS: // 0 IDENTIFIER_DCI_FORMATS: (field defined for format0_0,format0_1,format1_0,format1_1,format2_0,format2_1,format2_2,format2_3)
- // if format 0_0: The value of this bit field is always set to 0, indicating an UL DCI format (TS38.212 Section 7.3.1.1.1)
- // if format 1_0: The value of this bit field is always set to 1, indicating a DL DCI format (TS38.212 Section 7.3.1.2.1)
- nr_pdci_info_extracted->identifier_dci_formats = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->identifier_dci_formats=%x\n",nr_pdci_info_extracted->identifier_dci_formats);
- break;
-
- case CARRIER_IND: // 1 CARRIER_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-)
- // 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
- nr_pdci_info_extracted->carrier_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->carrier_ind=%x\n",nr_pdci_info_extracted->carrier_ind);
- break;
-
- case SUL_IND_0_1: // 2 SUL_IND_0_1: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->sul_ind_0_1 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_1=%x\n",nr_pdci_info_extracted->sul_ind_0_1);
- break;
-
- case SLOT_FORMAT_IND: // 3 SLOT_FORMAT_IND: (field defined for -,-,-,-,format2_0,-,-,-)
- // size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
- nr_pdci_info_extracted->slot_format_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->slot_format_ind=%x\n",nr_pdci_info_extracted->slot_format_ind);
- break;
-
- case PRE_EMPTION_IND: // 4 PRE_EMPTION_IND: (field defined for -,-,-,-,-,format2_1,-,-)
- // size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
- nr_pdci_info_extracted->pre_emption_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->pre_emption_ind=%x\n",nr_pdci_info_extracted->pre_emption_ind);
- break;
-
- case BLOCK_NUMBER: // 5 BLOCK_NUMBER: (field defined for -,-,-,-,-,-,-,format2_3)
- // starting position of a block is determined by the parameter startingBitOfFormat2_3
- nr_pdci_info_extracted->block_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->block_number=%x\n",nr_pdci_info_extracted->block_number);
- break;
-
- case CLOSE_LOOP_IND: // 6 CLOSE_LOOP_IND: (field defined for -,-,-,-,-,-,format2_2,-)
- // The parameter xxx provided by higher layers determines the index to the TPC command number for an UL of a cell. Each TPC command number is 2 bits
- nr_pdci_info_extracted->close_loop_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->close_loop_ind=%x\n",nr_pdci_info_extracted->close_loop_ind);
- break;
-
- case BANDWIDTH_PART_IND: // 7 BANDWIDTH_PART_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->bandwidth_part_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->bandwidth_part_ind=%x\n",nr_pdci_info_extracted->bandwidth_part_ind);
- break;
-
- case SHORT_MESSAGE_IND: // 8 SHORT_MESSAGE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- nr_pdci_info_extracted->short_message_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->short_message_ind=%x\n",nr_pdci_info_extracted->short_message_ind);
- break;
-
- case SHORT_MESSAGES: // 9 SHORT_MESSAGES: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- nr_pdci_info_extracted->short_messages = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->short_messages=%x\n",nr_pdci_info_extracted->short_messages);
- break;
-
- case FREQ_DOM_RESOURCE_ASSIGNMENT_UL: // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: (field defined for format0_0,format0_1,-,-,-,-,-,-)
- // PUSCH hopping with resource allocation type 1 not considered
- // According to 38.214 V15.1.0 Section 6.1.2.2 Two uplink resource allocation schemes, type 0 and type 1, are supported.
- // The UE shall assume that when the scheduling PDCCH is received with DCI format 0_0, then uplink resource allocation type 1 is used.
- nr_pdci_info_extracted->freq_dom_resource_assignment_UL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- /*if (dci_format == format0_1){ // uplink resource allocation type 0 or 1 can be used
- }
- if (dci_format == format0_0){ // only uplink resource allocation type 1
- // At the moment we are supporting only format 1_0 (and not format 1_1), so we only support resource allocation type 1 (and not type 0).
- // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
- // RIV = n_RB_ULBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_ULBWP/2)
- // RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_ULBWP/2)
- // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2)
- l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_ULBWP) + 1;
- start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_ULBWP;
- // if (l_RB - 1) > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines
- tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB;
- if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB
- l_RB = n_RB_ULBWP - l_RB + 2;
- start_RB = n_RB_ULBWP - start_RB - 1;
- }
- ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_rb = start_RB;
- ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->nb_rb = l_RB;
- }*/
- LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_UL=%x\n",nr_pdci_info_extracted->freq_dom_resource_assignment_UL);
- //LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_ULBWP);
- break;
-
- case FREQ_DOM_RESOURCE_ASSIGNMENT_DL: // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- // According to 38.214 V15.1.0 Section 5.1.2.2 Two downlink resource allocation schemes, type 0 and type 1, are supported.
- // The UE shall assume that when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used.
- nr_pdci_info_extracted->freq_dom_resource_assignment_DL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- /*if (dci_format == format1_1){ // uplink resource allocation type 0 or 1 can be used
- }
- if (dci_format == format1_0){ // only uplink resource allocation type 1
- // At the moment we are supporting only format 0_0 (and not format 0_1), so we only support resource allocation type 1 (and not type 0).
- // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
- // RIV = n_RB_DLBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_DLBWP/2)
- // RIV = n_RB_DLBWP * (n_RB_DLBWP - l_RB + 1) + (n_RB_DLBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_DLBWP/2)
- // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2)
- l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_DLBWP) + 1;
- start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_DLBWP;
- // if (l_RB - 1) > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines
- tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB;
- if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB
- l_RB = n_RB_DLBWP - l_RB + 2;
- start_RB = n_RB_DLBWP - start_RB - 1;
- }
- pdlsch0_harq->nb_rb = l_RB;
- pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number;
- pdlsch0->active = 1;
- pdlsch0->rnti = rnti;
- }*/
- LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_DL=%x, RIV = %d\n",nr_pdci_info_extracted->freq_dom_resource_assignment_DL,nr_pdci_info_extracted->freq_dom_resource_assignment_DL);
- //LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_DLBWP);
- /*
- * According to TC 38.212 Subclause 7.3.1.2.1 (V15.2.0) (not implemented FIXME!!!)
- * If the CRC of the DCI format 1_0 is scrambled by C-RNTI
- * and the "Frequency domain resource assignment" field are of all ones,
- * the DCI format 1_0 is for random access procedure initiated by a PDCCH order,
- * with all remaining fields set as follows:
- * - Random Access Preamble index (6 bits)
- * - UL/SUL indicator (1 bit)
- * - SS/PBCH index (6 bits)
- * - PRACH Mask index (4 bits)
- * - Reserved bits (10 bits)
- *
- */
- /*
- * The following commented code is used to verify that l_RB and start_RB are correctly calculated
- *
- *
- printf("\ns_RB\t");
- n_RB_DLBWP = 20;
- for (int k = 0 ; k < n_RB_DLBWP; k++) printf("%d\t",k);
- printf("\nl_RB");
- for (int j = 1 ; j <= n_RB_DLBWP; j++){ // l_RB
- printf("\n%d\t",j);
- for (int i = 0 ; i < n_RB_DLBWP; i++) { // start_RB
- if ((j-1) <= (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) {
- tmp_RIV = n_RB_DLBWP * (j - 1) + i;
- l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1;
- start_RB = tmp_RIV%n_RB_DLBWP;
- printf("%d(%d,%d) ",tmp_RIV,l_RB,start_RB);
- }
- if ((j-1) > (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) {
- tmp_RIV = n_RB_DLBWP * (n_RB_DLBWP - j + 1) + (n_RB_DLBWP - 1 - i);
- //l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1;
- //start_RB = tmp_RIV%n_RB_DLBWP;
- l_RB = n_RB_DLBWP - (floor(tmp_RIV/n_RB_DLBWP) + 1) + 2;
- start_RB = n_RB_DLBWP - (tmp_RIV%n_RB_DLBWP) - 1;
- printf("%d*(%d,%d) ",tmp_RIV,l_RB,start_RB);
- }
- }
- }*/
- break;
-
- case TIME_DOM_RESOURCE_ASSIGNMENT: // 12 TIME_DOM_RESOURCE_ASSIGNMENT: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-)
- // 0, 1, 2, 3, or 4 bits as defined in:
- // Subclause 6.1.2.1 of [6, TS 38.214] for formats format0_0,format0_1
- // Subclause 5.1.2.1 of [6, TS 38.214] for formats format1_0,format1_1
- // The bitwidth for this field is determined as log2(I) bits,
- // where I the number of entries in the higher layer parameter pusch-AllocationList
- nr_pdci_info_extracted->time_dom_resource_assignment = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- /*if (dci_format == format0_0 || dci_format == format0_1){ // Subclause 6.1.2.1 of [6, TS 38.214]
- k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- // k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- // sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- // sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
-
- }
- if (dci_format == format1_0 || dci_format == format1_1){ // Subclause 5.1.2.1 of [6, TS 38.214]
- // the Time domain resource assignment field of the DCI provides a row index of a higher layer configured table pdsch-symbolAllocation
- // FIXME! To clarify which parameters to update after reception of row index
- k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- sliv_S = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- sliv_L = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- // k_offset = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- // sliv_S = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- // sliv_L = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- // k_offset = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- // sliv_S = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- // sliv_L = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- // k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0];
- // sliv_S = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1];
- // sliv_L = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- }*/
- LOG_DCI_D("nr_pdci_info_extracted->time_dom_resource_assignment=%x\n",nr_pdci_info_extracted->time_dom_resource_assignment);
- break;
-
- case VRB_TO_PRB_MAPPING: // 13 VRB_TO_PRB_MAPPING: (field defined for -,format0_1,format1_0,format1_1,-,-,-,-)
- //0 bit if resource allocation type 0
- //1 bit if resource allocation type 1
- //Table 7.3.1.1.2-33: VRB-to-PRB mapping
- // 0 Non-interleaved
- // 1 Interleaved
- nr_pdci_info_extracted->vrb_to_prb_mapping = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (nr_pdci_info_extracted->vrb_to_prb_mapping == 0) { // Non-interleaved
- //} else { // Interleaved
- // format 0_1 defined in TS 38.211 Section 6.3.1.7
- // formats 1_0 and 1_1 not defined yet
- //}
- LOG_DCI_D("nr_pdci_info_extracted->vrb_to_prb_mapping=%x\n",nr_pdci_info_extracted->vrb_to_prb_mapping);
- break;
-
- case PRB_BUNDLING_SIZE_IND: // 14 PRB_BUNDLING_SIZE_IND: (field defined for -,-,-,format1_1,-,-,-,-)
- // 0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
- nr_pdci_info_extracted->prb_bundling_size_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->prb_bundling_size_ind=%x\n",nr_pdci_info_extracted->prb_bundling_size_ind);
- break;
-
- case RATE_MATCHING_IND: // 15 RATE_MATCHING_IND: (field defined for -,-,-,format1_1,-,-,-,-)
- // 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
- nr_pdci_info_extracted->rate_matching_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->rate_matching_ind=%x\n",nr_pdci_info_extracted->rate_matching_ind);
- break;
-
- case ZP_CSI_RS_TRIGGER: // 16 ZP_CSI_RS_TRIGGER: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->zp_csi_rs_trigger = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->zp_csi_rs_trigger=%x\n",nr_pdci_info_extracted->zp_csi_rs_trigger);
- break;
-
- case FREQ_HOPPING_FLAG: // 17 FREQ_HOPPING_FLAG: (field defined for format0_0,format0_1,-,-,-,-,-,-)
- // 0 bit if only resource allocation type 0
- // 1 bit otherwise, only applicable to resource allocation type 1, as defined in Subclause 6.3 of [6, TS 38.214]
- nr_pdci_info_extracted->freq_hopping_flag = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (nr_pdci_info_extracted->freq_hopping_flag != 0) { // PUSCH frequency hopping is performed (only resource allocation type 1)
- //} else { // PUSCH frequency hopping is not performed (only resource allocation type 1)
- // At the moment PUSCH hopping is not implemented. We are considering that the bit is present and the value is '0'
- //}
- LOG_DCI_D("nr_pdci_info_extracted->freq_hopping_flag=%x\n",nr_pdci_info_extracted->freq_hopping_flag);
- break;
-
- case TB1_MCS: // 18 TB1_MCS: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb1_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb1_mcs;
- LOG_DCI_D("nr_pdci_info_extracted->tb1_mcs=%x\n",nr_pdci_info_extracted->tb1_mcs);
- break;
- case TB1_NDI: // 19 TB1_NDI: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb1_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb1_ndi;
- LOG_DCI_D("nr_pdci_info_extracted->tb1_ndi=%x\n",nr_pdci_info_extracted->tb1_ndi);
- break;
- case TB1_RV: // 20 TB1_RV: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb1_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb1_rv;
- LOG_DCI_D("nr_pdci_info_extracted->tb1_rv=%x\n",nr_pdci_info_extracted->tb1_rv);
- break;
- case TB2_MCS: // 21 TB2_MCS: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb2_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb2_mcs;
- LOG_DCI_D("nr_pdci_info_extracted->tb2_mcs=%x\n",nr_pdci_info_extracted->tb2_mcs);
- break;
- case TB2_NDI: // 22 TB2_NDI: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb2_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb2_ndi;
- LOG_DCI_D("nr_pdci_info_extracted->tb2_ndi=%x\n",nr_pdci_info_extracted->tb2_ndi);
- break;
- case TB2_RV: // 23 TB2_RV: (field defined for -,-,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->tb2_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb2_rv;
- LOG_DCI_D("nr_pdci_info_extracted->tb2_rv=%x\n",nr_pdci_info_extracted->tb2_rv);
- break;
-
- case MCS: // 24 MCS: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
- nr_pdci_info_extracted->mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (nr_pdci_info_extracted->mcs < 29) {
- // if (dci_format == format0_0 || dci_format == format0_1)
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->mcs = nr_pdci_info_extracted->mcs;
- // else
- // pdlsch0_harq->mcs = nr_pdci_info_extracted->mcs;
- //} else {
- // return(0);
- //}
- LOG_DCI_D("nr_pdci_info_extracted->mcs=%x\n",nr_pdci_info_extracted->mcs);
- break;
-
- case NDI: // 25 NDI: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
- nr_pdci_info_extracted->ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (dci_format == format0_0 || dci_format == format0_1) {
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi = nr_pdci_info_extracted->ndi;
- // if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx==1) {
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx=0;
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi;
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0;
- // } else {
- // if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi != nr_pdci_info_extracted->ndi) { // new SDU opportunity
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi;
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0;
- // }
- // }
- //} else {
- // if (rnti == crc_scrambled_values[_TC_RNTI_]) { //fix for standalone Contention Resolution Id
- // pdlsch0_harq->DCINdi = (uint8_t)-1;
- // } else {
- // if ((prev_ndi != nr_pdci_info_extracted->ndi) || (pdlsch0_harq->first_tx==1)) {
- // pdlsch0_harq->round = 0;
- // pdlsch0_harq->first_tx = 0;
- // pdlsch0_harq->status = ACTIVE;
- // }
- // pdlsch0_harq->DCINdi = nr_pdci_info_extracted->ndi;
- // }
- //}
- LOG_DCI_D("nr_pdci_info_extracted->ndi=%x\n",nr_pdci_info_extracted->ndi);
- break;
-
- case RV: // 26 RV: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
- nr_pdci_info_extracted->rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //if (dci_format == format0_0 || dci_format == format0_1)
- // ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->rvidx = nr_pdci_info_extracted->rv;
- //else
- // pdlsch0_harq->rvidx = nr_pdci_info_extracted->rv;
- //if ((prev_ndi == nr_pdci_info_extracted->ndi) && (pdlsch0_harq->rvidx != 0)) { // NDI has not been toggled but rv was increased by eNB: retransmission
- // if (pdlsch0_harq->status == SCH_IDLE) {
- // packet was actually decoded in previous transmission (ACK was missed by eNB)
- // however, the round is not a good check as it might have been decoded in a retransmission prior to this one.
- // skip pdsch decoding and report ack
- // pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.ack = 1;
- // pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.send_harq_status;
-#if 0
- // pdlsch0->active = 0;
- // pdlsch0->harq_ack[nr_tti_rx].ack = 1;
- // pdlsch0->harq_ack[nr_tti_rx].harq_id = nr_pdci_info_extracted->harq_process_number;
- // pdlsch0->harq_ack[nr_tti_rx].send_harq_status = 1;
-#endif
- // } else { // normal retransmission, nothing special to do
- // }
- //} else {
- // pdlsch0_harq->status = ACTIVE;
- //}
- LOG_DCI_D("nr_pdci_info_extracted->rv=%x\n",nr_pdci_info_extracted->rv);
- break;
-
- case HARQ_PROCESS_NUMBER: // 27 HARQ_PROCESS_NUMBER: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-)
- nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number;
- LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number);
- break;
-
- case DAI_: // 28 DAI_: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- // For format1_0: 2 bits as defined in Subclause 9.1.3 at TS 38.213
- // For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
- // 0 otherwise
- nr_pdci_info_extracted->dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.vDAI_DL = nr_pdci_info_extracted->dai+1;
- //pdlsch0->harq_ack[nr_tti_rx].vDAI_DL = nr_pdci_info_extracted->dai+1;
- LOG_DCI_D("nr_pdci_info_extracted->dai=%x\n",nr_pdci_info_extracted->dai);
- break;
-
- case FIRST_DAI: // 29 FIRST_DAI: (field defined for -,format0_1,-,-,-,-,-,-)
- // (1 or 2 bits) 1 bit for semi-static HARQ-ACK
- nr_pdci_info_extracted->first_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->first_dai=%x\n",nr_pdci_info_extracted->first_dai);
- break;
-
- case SECOND_DAI: // 30 SECOND_DAI: (field defined for -,format0_1,-,-,-,-,-,-)
- // (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
- nr_pdci_info_extracted->second_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->second_dai=%x\n",nr_pdci_info_extracted->second_dai);
- break;
-
- case TB_SCALING: // 31 TB_SCALING: (field defined for -,format0_1,-,-,-,-,-,-)
- // (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
- nr_pdci_info_extracted->tb_scaling = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->tb_scaling=%x\n",nr_pdci_info_extracted->tb_scaling);
- break;
-
- case TPC_PUSCH: // 32 TPC_PUSCH: (field defined for format0_0,format0_1,-,-,-,-,-,-)
- // defined in Subclause 7.1.1 TS 38.213
- nr_pdci_info_extracted->tpc_pusch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC = nr_pdci_info_extracted->tpc_pusch;
- //if (ue->ul_power_control_dedicated[eNB_id].accumulationEnabled == 1) {
- // ulsch0->f_pusch += nr_delta_PUSCH_acc[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC];
- //} else {
- // ulsch0->f_pusch = nr_delta_PUSCH_abs[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC];
- //}
- LOG_DCI_D("nr_pdci_info_extracted->tpc_pusch=%x\n",nr_pdci_info_extracted->tpc_pusch);
- break;
-
- case TPC_PUCCH: // 33 TPC_PUCCH: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- // defined in Subclause 7.2.1 TS 38.213
- nr_pdci_info_extracted->tpc_pucch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- //pdlsch0_harq->delta_PUCCH = nr_delta_PUCCH_lut[nr_pdci_info_extracted->tpc_pucch &3];
- LOG_DCI_D("nr_pdci_info_extracted->tpc_pucch=%x\n",nr_pdci_info_extracted->tpc_pucch);
- break;
-
- case PUCCH_RESOURCE_IND: // 34 PUCCH_RESOURCE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- // defined in Subclause 9.2.3 TS 38.213
- // PUCCH_RESOURCE_IND points to PUCCH-ResourceId, but PUCCH-ResourceId is not defined yet
- nr_pdci_info_extracted->pucch_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->pucch_resource_ind=%x\n",nr_pdci_info_extracted->pucch_resource_ind);
- break;
-
- case PDSCH_TO_HARQ_FEEDBACK_TIME_IND: // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
- // defined in Subclause 9.2.3 TS 38.213
- // PDSCH_TO_HARQ_FEEDBACK_TIME_IND points to DL-data-DL-acknowledgement, but DL-data-DL-acknowledgement is not defined yet
- nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind=%x\n",nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind);
- break;
-
- case SRS_RESOURCE_IND: // 36 SRS_RESOURCE_IND: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->srs_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->srs_resource_ind=%x\n",nr_pdci_info_extracted->srs_resource_ind);
- break;
-
- case PRECOD_NBR_LAYERS: // 37 PRECOD_NBR_LAYERS: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->precod_nbr_layers = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->precod_nbr_layers=%x\n",nr_pdci_info_extracted->precod_nbr_layers);
- break;
-
- case ANTENNA_PORTS: // 38 ANTENNA_PORTS: (field defined for -,format0_1,-,format1_1,-,-,-,-)
- nr_pdci_info_extracted->antenna_ports = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->antenna_ports=%x\n",nr_pdci_info_extracted->antenna_ports);
- break;
-
- case TCI: // 39 TCI: (field defined for -,-,-,format1_1,-,-,-,-)
- // 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
- nr_pdci_info_extracted->tci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->tci=%x\n",nr_pdci_info_extracted->tci);
- break;
-
- case SRS_REQUEST: // 40 SRS_REQUEST: (field defined for -,format0_1,-,format1_1,-,-,-,format2_3)
- nr_pdci_info_extracted->srs_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->srs_request=%x\n",nr_pdci_info_extracted->srs_request);
- break;
-
- case TPC_CMD: // 41 TPC_CMD: (field defined for -,-,-,-,-,-,-,format2_3)
- nr_pdci_info_extracted->tpc_cmd = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->tpc_cmd=%x\n",nr_pdci_info_extracted->tpc_cmd);
- break;
-
- case CSI_REQUEST: // 42 CSI_REQUEST: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->csi_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->csi_request=%x\n",nr_pdci_info_extracted->csi_request);
- break;
-
- case CBGTI: // 43 CBGTI: (field defined for -,format0_1,-,format1_1,-,-,-,-)
- // 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
- nr_pdci_info_extracted->cbgti = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->cbgti=%x\n",nr_pdci_info_extracted->cbgti);
- break;
-
- case CBGFI: // 44 CBGFI: (field defined for -,-,-,format1_1,-,-,-,-)
- // 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
- nr_pdci_info_extracted->cbgfi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->cbgfi=%x\n",nr_pdci_info_extracted->cbgfi);
- break;
-
- case PTRS_DMRS: // 45 PTRS_DMRS: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->ptrs_dmrs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->ptrs_dmrs=%x\n",nr_pdci_info_extracted->ptrs_dmrs);
- break;
-
- case BETA_OFFSET_IND: // 46 BETA_OFFSET_IND: (field defined for -,format0_1,-,-,-,-,-,-)
- nr_pdci_info_extracted->beta_offset_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->beta_offset_ind=%x\n",nr_pdci_info_extracted->beta_offset_ind);
- break;
-
- case DMRS_SEQ_INI: // 47 DMRS_SEQ_INI: (field defined for -,format0_1,-,format1_1,-,-,-,-)
- // 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
- nr_pdci_info_extracted->dmrs_seq_ini = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->dmrs_seq_ini);
- break;
-
- case UL_SCH_IND: // 48 UL_SCH_IND: (field defined for -,format0_1,-,-,-,-,-,-)
- // value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
- nr_pdci_info_extracted->ul_sch_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->ul_sch_ind);
- break;
-
- case PADDING_NR_DCI: // 49 PADDING_NR_DCI: (field defined for format0_0,-,format1_0,-,-,-,-,-)
- // (Note 2) If DCI format 0_0 is monitored in common search space
- nr_pdci_info_extracted->padding_nr_dci = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->padding=%x\n",nr_pdci_info_extracted->padding_nr_dci);
- break;
-
- case SUL_IND_0_0: // 50 SUL_IND_0_0: (field defined for format0_0,-,-,-,-,-,-,-)
- nr_pdci_info_extracted->sul_ind_0_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_0=%x\n",nr_pdci_info_extracted->sul_ind_0_0);
- break;
-
- case RA_PREAMBLE_INDEX: // 51 RA_PREAMBLE_INDEX: (field defined for format0_0,-,-,-,-,-,-,-)
- nr_pdci_info_extracted->ra_preamble_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->ra_preamble_index=%x\n",nr_pdci_info_extracted->ra_preamble_index);
- break;
-
- case SUL_IND_1_0: // 52 SUL_IND_1_0: (field defined for -,-,format1_0,-,-,-,-,-)
- nr_pdci_info_extracted->sul_ind_1_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->sul_ind_1_0=%x\n",nr_pdci_info_extracted->sul_ind_1_0);
- break;
-
- case SS_PBCH_INDEX: // 53 SS_PBCH_INDEX: (field defined for -,-,format1_0,-,-,-,-,-)
- nr_pdci_info_extracted->ss_pbch_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->ss_pbch_index=%x\n",nr_pdci_info_extracted->ss_pbch_index);
- break;
-
- case PRACH_MASK_INDEX: // 54 PRACH_MASK_INDEX: (field defined for -,-,-,format1_0,-,-,-,-)
- nr_pdci_info_extracted->prach_mask_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->prach_mask_index=%x\n",nr_pdci_info_extracted->prach_mask_index);
- break;
-
- case RESERVED_NR_DCI: // 55 RESERVED_NR_DCI: (field defined for -,-,-,format1_0,-,-,-,-)
- nr_pdci_info_extracted->reserved_nr_dci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
- //(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
- LOG_DCI_D("nr_pdci_info_extracted->reserved_nr_dci=%x\n",nr_pdci_info_extracted->reserved_nr_dci);
- break;
- }
- }
- }
-
- LOG_DCI_D("Ending function nr_extract_dci_info()\n");
- return(1);
-}
-
-#endif
-
-#ifdef NR_PDCCH_DCI_TOOLS
-
-int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- int frame,
- uint8_t nr_tti_rx,
- uint64_t dci_pdu[2],
- uint16_t rnti,
- uint8_t dci_length,
- NR_DCI_format_t dci_format,
- NR_DL_FRAME_PARMS *frame_parms,
- PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
- fapi_nr_dci_pdu_rel15_t *nr_dci_info_extracted) {
- /*
- * Note only format0_0 and format1_0 are implemented
- */
- uint8_t frame_type=frame_parms->frame_type;
- uint8_t status=0;
- LOG_DCI_PARM("dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_format,rnti,dci_length,dci_pdu[0],
- dci_pdu[1]);
- memset(nr_dci_info_extracted,0,sizeof(*nr_dci_info_extracted));
- LOG_DCI_PARM("Entering function nr_extract_dci_info(dci_format=%d) \n",dci_format);
- status = nr_extract_dci_info(ue,
- eNB_id,
- frame_type,
- dci_length,
- rnti,
- dci_pdu,
- nr_dci_info_extracted,//&nr_dci_info_extracted,
- dci_fields_sizes,
- dci_format,
- nr_tti_rx,
- n_RB_ULBWP,
- n_RB_DLBWP,
- crc_scrambled_values);
-
- if(status == 0) {
- LOG_DCI_PARM("bad DCI %d !!! \n",dci_format);
- return(-1);
- }
-
- LOG_DCI_PARM("Ending function nr_extract_dci_info()\n");
- //fill
- return(0);
-}
-
-#endif
uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t nr_tti_rx) {
/*
@@ -1000,7 +87,6 @@ uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8
return ret;
}
-
uint8_t nr_pdcch_alloc2ul_subframe(NR_DL_FRAME_PARMS *frame_parms,uint8_t n) {
uint8_t ul_subframe = 255;
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
index 4dbd14ba9751c5d2ee4ff71cfd891bd696826558..d526b2f5440bae8402047fbd63d3cf494dee93a3 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
@@ -65,7 +65,7 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr)
for (i=0; i<dlsch->Mdlharq; i++) {
if (dlsch->harq_processes[i]) {
if (dlsch->harq_processes[i]->b) {
- free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES);
+ free16(dlsch->harq_processes[i]->b,MAX_NR_DLSCH_PAYLOAD_BYTES);
dlsch->harq_processes[i]->b = NULL;
}
@@ -140,10 +140,10 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint
if (dlsch->harq_processes[i]) {
memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t));
dlsch->harq_processes[i]->first_tx=1;
- dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
+ dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b)
- memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
+ memset(dlsch->harq_processes[i]->b,0,MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling);
else
exit_flag=3;
@@ -238,6 +238,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
return(dlsch->max_ldpc_iterations + 1);
}
t_nrLDPC_procBuf** p_nrLDPC_procBuf = harq_process->p_nrLDPC_procBuf;
+
+ AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"Entry. llProcBuf is null!\n");
int16_t z [68*384];
int8_t l [68*384];
@@ -251,11 +253,10 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
double Coderate;// = 0.0;
- nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dl_config_pdu = &harq_process->dl_config_pdu;
- uint8_t dmrs_Type = dl_config_pdu->dmrsConfigType;
+ uint8_t dmrs_Type = harq_process->dmrsConfigType;
AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type);
uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4;
- uint16_t dmrs_length = get_num_dmrs(dl_config_pdu->dlDmrsSymbPos);
+ uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos);
AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length);
uint32_t i,j;
@@ -315,7 +316,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
- LOG_I(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
+ LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_SEGMENTATION, VCD_FUNCTION_IN);
@@ -431,11 +432,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DEINTERLEAVING, VCD_FUNCTION_IN);
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"10. llProcBuf is null!\n");
+
nr_deinterleaving_ldpc(E,
harq_process->Qm,
harq_process->w[r], // [hna] w is e
dlsch_llr+r_offset);
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"11. llProcBuf is null!\n");
+
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DEINTERLEAVING, VCD_FUNCTION_OUT);
//for (int i =0; i<16; i++)
@@ -468,6 +473,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
else
Tbslbrm = nr_compute_tbslbrm(harq_process->mcs_table,nb_rb,4,harq_process->C);
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"0. llProcBuf is null!\n");
+
if (nr_rate_matching_ldpc_rx(Ilbrm,
Tbslbrm,
p_decParams->BG,
@@ -492,6 +499,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
#endif
}
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"1. llProcBuf is null!\n");
+
//for (int i =0; i<16; i++)
// printf("rx output ratematching d[%d]= %d r_offset %d\n", i,harq_process->d[r][i], r_offset);
@@ -558,27 +567,29 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
}
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_IN);
-
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"2. llProcBuf is null!\n");
no_iteration_ldpc = nrLDPC_decoder(p_decParams,
(int8_t*)&pl[0],
llrProcBuf,
p_nrLDPC_procBuf[r],
p_procTime);
-
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"3. llProcBuf is null!\n");
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_OUT);
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
- printf("\x1B[34m" "Segment %u CRC OK\n\033[0m",r);
+ LOG_D(PHY,"Segment %u CRC OK\n\033[0m",r);
//Temporary hack
no_iteration_ldpc = dlsch->max_ldpc_iterations;
ret = no_iteration_ldpc;
}
else {
- printf("\x1B[33m" "CRC NOK\n\033[0m");
+ LOG_D(PHY,"CRC NOK\n\033[0m");
ret = 1 + dlsch->max_ldpc_iterations;
}
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"4. llProcBuf is null!\n");
+
nb_total_decod++;
if (no_iteration_ldpc > dlsch->max_ldpc_iterations){
nb_error_decod++;
@@ -594,6 +605,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
{
harq_process->c[r][m]= (uint8_t) llrProcBuf[m];
}
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"5. llProcBuf is null!\n");
#ifdef DEBUG_DLSCH_DECODING
//printf("output decoder %d %d %d %d %d \n", harq_process->c[r][0], harq_process->c[r][1], harq_process->c[r][2],harq_process->c[r][3], harq_process->c[r][4]);
@@ -620,7 +632,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if ((err_flag == 0) && (ret>=(1+dlsch->max_ldpc_iterations))) {// a Code segment is in error so break;
- LOG_I(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1);
+ LOG_D(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1);
err_flag = 1;
}
}
@@ -635,7 +647,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 1) {
//#if UE_DEBUG_TRACE
- LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
+ LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round);
//#endif
harq_process->harq_ack.ack = 0;
@@ -652,15 +664,16 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if(is_crnti)
{
- LOG_I(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
+ LOG_D(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,dlsch->Mdlharq,harq_process->TBS);
}
+ AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"Exit 1. llProcBuf is null!\n");
return((1 + dlsch->max_ldpc_iterations));
} else {
//#if UE_DEBUG_TRACE
- LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n",
- phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round);
+ LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n",
+ phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round);
//#endif
harq_process->status = SCH_IDLE;
@@ -669,12 +682,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
harq_process->harq_ack.harq_id = harq_pid;
harq_process->harq_ack.send_harq_status = 1;
- //LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n",
+ //LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n",
// phy_vars_ue->Mod_id, frame, subframe, harq_pid, harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs);
if(is_crnti)
{
- LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
+ LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
}
//LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for subframe %d (pid %d, round %d)\n",phy_vars_ue->Mod_id,subframe,harq_pid,harq_process->round);
@@ -695,10 +708,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
for (r=0; r<harq_process->C; r++) {
+ AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"7. llProcBuf is null (r %d)!\n",r);
memcpy(harq_process->b+offset,
- harq_process->c[r],
- Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0));
+ harq_process->c[r],
+ Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0));
offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0));
+ AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"8. llProcBuf is null (r %d)!\n",r);
#ifdef DEBUG_DLSCH_DECODING
printf("Segment %u : Kr= %u bytes\n",r,Kr_bytes);
@@ -730,6 +745,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
dlsch->last_iteration_cnt = ret;
+ AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"Exit 2. llProcBuf is null!\n");
return(ret);
}
@@ -850,7 +866,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
G = harq_process->G;
- LOG_I(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
+ LOG_D(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
proc->decoder_main_available = 1;
@@ -1109,7 +1125,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 0) {
/*
- LOG_I(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
+ LOG_D(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS,
harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations);
*/
@@ -1222,7 +1238,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 1) {
#if UE_DEBUG_TRACE
- LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
+ LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round);
#endif
harq_process->harq_ack.ack = 0;
@@ -1246,7 +1262,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
return((1+dlsch->max_ldpc_iterations));
} else {
#if UE_DEBUG_TRACE
- LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n",
+ LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb);
#endif
@@ -1429,7 +1445,7 @@ void *nr_dlsch_decoding_process(void *arg)
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
- LOG_I(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
+ LOG_D(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
if ((harq_process->R)<1024)
Coderate = (float) (harq_process->R) /(float) 1024;
@@ -1646,7 +1662,7 @@ void *nr_dlsch_decoding_process(void *arg)
if (err_flag == 0) {
/*
- LOG_I(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
+ LOG_D(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS,
harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations);
*/
@@ -1690,16 +1706,16 @@ void *nr_dlsch_decoding_process(void *arg)
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
- printf("Segment %u CRC OK\n",r);
+ LOG_D(PHY,"Segment %u CRC OK\n",r);
ret = 2;
}
else {
- printf("CRC NOK\n");
+ LOG_D(PHY,"Segment %u CRC NOK\n",r);
ret = 1+dlsch->max_ldpc_iterations;
}
if (no_iteration_ldpc > 10)
- printf("Error number of iteration LPDC %d\n", no_iteration_ldpc);
+ LOG_D(PHY,"Error number of iteration LPDC %d\n", no_iteration_ldpc);
//else
//printf("OK number of iteration LPDC %d\n", no_iteration_ldpc);
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
index 8f810d36d317d658e02f910684ba292cc21af1eb..ad10d693ac313cd146c8348cb3813448a385c118 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
@@ -101,16 +101,16 @@ static void nr_dlsch_layer_demapping(int16_t **llr_cw,
int16_t **llr_layers);
int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
- PDSCH_t type,
- unsigned char eNB_id,
- unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference
- uint32_t frame,
- uint8_t nr_tti_rx,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- RX_type_t rx_type,
- unsigned char i_mod,
- unsigned char harq_pid)
+ PDSCH_t type,
+ unsigned char eNB_id,
+ unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference
+ uint32_t frame,
+ uint8_t nr_tti_rx,
+ unsigned char symbol,
+ unsigned char first_symbol_flag,
+ RX_type_t rx_type,
+ unsigned char i_mod,
+ unsigned char harq_pid)
{
NR_UE_COMMON *common_vars = &ue->common_vars;
@@ -151,7 +151,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
//int16_t *pllr_symbol_cw1_deint;
uint32_t llr_offset_symbol;
//uint16_t bundle_L = 2;
- uint8_t l0 =2, pilots=0;
+ uint8_t pilots=0;
uint16_t n_tx=1, n_rx=1;
int32_t median[16];
uint32_t len;
@@ -234,7 +234,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
start_rb = dlsch0_harq->start_rb;
nb_rb_pdsch = dlsch0_harq->nb_rb;
- l0 = dlsch0_harq->start_symbol;
+ int lbar;
DevAssert(dlsch0_harq);
round = dlsch0_harq->round;
@@ -286,7 +286,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
printf("Demod dlsch0_harq->pmi_alloc %d\n", dlsch0_harq->pmi_alloc);
#endif
- pilots = (symbol==l0) ? 1 : 0;
+ pilots = ((1<<symbol)&dlsch0_harq->dlDmrsSymbPos)>0 ? 1 : 0;
if (frame_parms->nb_antenna_ports_eNB>1 && beamforming_mode==0) {
#ifdef DEBUG_DLSCH_MOD
@@ -297,19 +297,19 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
#endif
nb_rb = nr_dlsch_extract_rbs_dual(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF,
- pdsch_vars[eNB_id]->dl_ch_estimates,
- pdsch_vars[eNB_id]->rxdataF_ext,
- pdsch_vars[eNB_id]->dl_ch_estimates_ext,
- dlsch0_harq->pmi_alloc,
- pdsch_vars[eNB_id]->pmi_ext,
- symbol,
- pilots,
- start_rb,
- nb_rb_pdsch,
- nr_tti_rx,
- ue->high_speed_flag,
- frame_parms,
- dlsch0_harq->mimo_mode);
+ pdsch_vars[eNB_id]->dl_ch_estimates,
+ pdsch_vars[eNB_id]->rxdataF_ext,
+ pdsch_vars[eNB_id]->dl_ch_estimates_ext,
+ dlsch0_harq->pmi_alloc,
+ pdsch_vars[eNB_id]->pmi_ext,
+ symbol,
+ pilots,
+ start_rb,
+ nb_rb_pdsch,
+ nr_tti_rx,
+ ue->high_speed_flag,
+ frame_parms,
+ dlsch0_harq->mimo_mode);
#ifdef DEBUG_DLSCH_MOD
printf("dlsch: using pmi %lx, pmi_ext ",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc));
for (rb=0;rb<nb_rb;rb++)
@@ -352,18 +352,18 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
} else if (beamforming_mode==0) { //else if nb_antennas_ports_eNB==1 && beamforming_mode == 0
//printf("start nr dlsch extract nr_tti_rx %d thread id %d \n", nr_tti_rx, ue->current_thread_id[nr_tti_rx]);
nb_rb = nr_dlsch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF,
- pdsch_vars[eNB_id]->dl_ch_estimates,
- pdsch_vars[eNB_id]->rxdataF_ext,
- pdsch_vars[eNB_id]->dl_ch_estimates_ext,
- dlsch0_harq->pmi_alloc,
- pdsch_vars[eNB_id]->pmi_ext,
- symbol,
- pilots,
- start_rb,
- nb_rb_pdsch,
- nr_tti_rx,
- ue->high_speed_flag,
- frame_parms);
+ pdsch_vars[eNB_id]->dl_ch_estimates,
+ pdsch_vars[eNB_id]->rxdataF_ext,
+ pdsch_vars[eNB_id]->dl_ch_estimates_ext,
+ dlsch0_harq->pmi_alloc,
+ pdsch_vars[eNB_id]->pmi_ext,
+ symbol,
+ pilots,
+ start_rb,
+ nb_rb_pdsch,
+ nr_tti_rx,
+ ue->high_speed_flag,
+ frame_parms);
} /*else if(beamforming_mode>7) {
LOG_W(PHY,"dlsch_demodulation: beamforming mode not supported yet.\n");
@@ -375,7 +375,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
return(-1);
}
- len = (symbol==l0)? (nb_rb*6):(nb_rb*12);
+ len = (pilots==1)? (nb_rb*6):(nb_rb*12);
#if UE_TIMING_TRACE
stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
@@ -395,11 +395,11 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
n_rx = frame_parms->nb_antennas_rx;
nr_dlsch_scale_channel(pdsch_vars[eNB_id]->dl_ch_estimates_ext,
- frame_parms,
- dlsch,
- symbol,
- pilots,
- nb_rb);
+ frame_parms,
+ dlsch,
+ symbol,
+ pilots,
+ nb_rb);
#if UE_TIMING_TRACE
stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
@@ -648,13 +648,14 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
#endif
#if UE_TIMING_TRACE
+
start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
#endif
//printf("LLR dlsch0_harq->Qm %d rx_type %d cw0 %d cw1 %d symbol %d \n",dlsch0_harq->Qm,rx_type,codeword_TB0,codeword_TB1,symbol);
// compute LLRs
// -> // compute @pointer where llrs should filled for this ofdm-symbol
- pdsch_vars[eNB_id]->llr_offset[l0-1] = 0;
+ if (first_symbol_flag==1) pdsch_vars[eNB_id]->llr_offset[symbol-1] = 0;
llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1];
//pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0];
//pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1];
@@ -1788,11 +1789,11 @@ void nr_dlsch_channel_compensation_core(int **rxdataF_ext,
void nr_dlsch_scale_channel(int **dl_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t **dlsch_ue,
- uint8_t symbol,
- uint8_t pilots,
- unsigned short nb_rb)
+ NR_DL_FRAME_PARMS *frame_parms,
+ NR_UE_DLSCH_t **dlsch_ue,
+ uint8_t symbol,
+ uint8_t pilots,
+ unsigned short nb_rb)
{
#if defined(__x86_64__)||defined(__i386__)
@@ -1808,7 +1809,7 @@ void nr_dlsch_scale_channel(int **dl_ch_estimates_ext,
// Determine scaling amplitude based the symbol
-ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a));
+ ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a));
LOG_D(PHY,"Scaling PDSCH Chest in OFDM symbol %d by %d, pilots %d nb_rb %d NCP %d symbol %d\n",symbol,ch_amp,pilots,nb_rb,frame_parms->Ncp,symbol);
// printf("Scaling PDSCH Chest in OFDM symbol %d by %d\n",symbol_mod,ch_amp);
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
index 1f397c26c0ee7f49a21bab9ebc0f9fd96c21ce64..d23d2302556457b83e6fdb5a1cbcf7e9c6cd8543 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
@@ -538,7 +538,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
uint32_t unscrambling_mask = (Lmax==64)?0x100006D:0x1000041;
nr_pbch_unscrambling(nr_ue_pbch_vars,frame_parms->Nid_cell,nushift,M,NR_POLAR_PBCH_E,0,0);
//polar decoding de-rate matching
- const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,1);
+ const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,1,ue->polarList);
decoderState = polar_decoder_int16(pbch_e_rx,(uint64_t *)&nr_ue_pbch_vars->pbch_a_prime,0,currentPtr);
if(decoderState) return(decoderState);
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
index 439c3d29f27af0f24a1a5ce34593bfc596a72889..3c531856824784432bc285fd7ce6a6007a647fe7 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
@@ -1113,6 +1113,7 @@ void *nr_dlsch_decoding_2thread0(void *arg);
void *nr_dlsch_decoding_2thread1(void *arg);
+
void nr_dlsch_unscrambling(int16_t* llr,
uint32_t size,
uint8_t q,
@@ -1124,17 +1125,10 @@ uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue,
PDSCH_t dlsch_id,
uint8_t eNB_id);
-
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
uint32_t frame,
- uint8_t nr_tti_rx,
- uint8_t eNB_id,
- MIMO_mode_t mimo_mode,
- uint32_t high_speed_flag,
- uint8_t is_secondary_ue,
- int nb_coreset_active,
- uint16_t symbol_mon,
- NR_SEARCHSPACE_TYPE_t searchSpaceType);
+ uint32_t slot);
+
/*! \brief Extract PSS and SSS resource elements
@param phy_vars_ue Pointer to UE variables
@@ -1544,10 +1538,9 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME
void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi);
-void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
- uint8_t subframe,
- int8_t* llr,
- uint32_t length);
+void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
+ int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id);
+
@@ -1711,46 +1704,14 @@ uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms,
uint8_t n_ra_prboffset,
uint8_t tdd_mapindex, uint16_t Nf);
-void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx,
- int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common);
-
uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset);
-uint8_t nr_dci_decoding_procedure(int s,
- int p,
- PHY_VARS_NR_UE *ue,
- NR_DCI_ALLOC_t *dci_alloc,
- NR_SEARCHSPACE_TYPE_t searchSpacetype,
- int16_t eNB_id,
- uint8_t nr_tti_rx,
- uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- crc_scrambled_t *crc_scrambled,
- format_found_t *format_found,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
-
-int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- int frame,
- uint8_t nr_tti_rx,
- uint64_t dci_pdu[2],
- uint16_t rnti,
- uint8_t dci_length,
- NR_DCI_format_t dci_format,
- NR_UE_PDCCH *pdcch_vars,
- NR_UE_PDSCH *pdsch_vars,
- NR_UE_DLSCH_t **dlsch,
- NR_UE_ULSCH_t *ulsch,
- NR_DL_FRAME_PARMS *frame_parms,
- PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- uint8_t beamforming_mode,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
- NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted);
+uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
+ int frame,
+ int slot,
+ fapi_nr_dci_indication_t *dci_ind);
+
/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs
- RB extraction (signal and channel estimates)
@@ -1794,22 +1755,11 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t is_crnti,
uint8_t llr8_flag);
-int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
- uint8_t eNB_id,
- lte_frame_type_t frame_type,
- uint8_t dci_length,
- uint16_t rnti,
- uint64_t dci_pdu[2],
- fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
- uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- NR_DCI_format_t dci_format,
- uint8_t nr_tti_rx,
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
+
int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf );
void *dlsch_thread(void *arg);
/**@}*/
#endif
+
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
index dd0cd4cf01826d5f96c8e063c63f62ac75f8850a..cfd364ac92129a3ed05b3bd8e6a3dc4ac36f711c 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
@@ -255,8 +255,6 @@ typedef struct {
uint8_t DCINdi;
/// DLSCH status flag indicating
SCH_status_t status;
- /// Dynamic Configuration from FAPI
- nfapi_nr_dl_tti_pdsch_pdu_rel15_t dl_config_pdu;
/// Transport block size
uint32_t TBS;
/// The payload + CRC size in bits
@@ -301,12 +299,20 @@ typedef struct {
int8_t delta_PUCCH;
/// Number of soft channel bits
uint32_t G;
+ /// Start PRB of BWP
+ uint16_t BWPStart;
+ /// Number of PRBs in BWP
+ uint16_t BWPSize;
/// Current Number of RBs
uint16_t nb_rb;
/// Starting RB number
uint16_t start_rb;
/// Number of Symbols
uint16_t nb_symbols;
+ /// DMRS symbol positions
+ uint16_t dlDmrsSymbPos;
+ /// DMRS Configuration Type
+ uint8_t dmrsConfigType;
/// Starting Symbol number
uint16_t start_symbol;
/// Current subband PMI allocation
diff --git a/openair1/PHY/TOOLS/lte_dfts.c b/openair1/PHY/TOOLS/lte_dfts.c
index ccd09b34be01143b664726e5f679b75da2b60327..2de8653ab3900652e4e0ca8d95f0919c989709bd 100644
--- a/openair1/PHY/TOOLS/lte_dfts.c
+++ b/openair1/PHY/TOOLS/lte_dfts.c
@@ -4836,22 +4836,22 @@ void idft4096(int16_t *x,int16_t *y,int scale)
if (scale>0) {
for (i=0; i<64; i++) {
- y128[0] = shiftright_int16(y128[0],1);
- y128[1] = shiftright_int16(y128[1],1);
- y128[2] = shiftright_int16(y128[2],1);
- y128[3] = shiftright_int16(y128[3],1);
- y128[4] = shiftright_int16(y128[4],1);
- y128[5] = shiftright_int16(y128[5],1);
- y128[6] = shiftright_int16(y128[6],1);
- y128[7] = shiftright_int16(y128[7],1);
- y128[8] = shiftright_int16(y128[8],1);
- y128[9] = shiftright_int16(y128[9],1);
- y128[10] = shiftright_int16(y128[10],1);
- y128[11] = shiftright_int16(y128[11],1);
- y128[12] = shiftright_int16(y128[12],1);
- y128[13] = shiftright_int16(y128[13],1);
- y128[14] = shiftright_int16(y128[14],1);
- y128[15] = shiftright_int16(y128[15],1);
+ y128[0] = shiftright_int16(y128[0],scale);
+ y128[1] = shiftright_int16(y128[1],scale);
+ y128[2] = shiftright_int16(y128[2],scale);
+ y128[3] = shiftright_int16(y128[3],scale);
+ y128[4] = shiftright_int16(y128[4],scale);
+ y128[5] = shiftright_int16(y128[5],scale);
+ y128[6] = shiftright_int16(y128[6],scale);
+ y128[7] = shiftright_int16(y128[7],scale);
+ y128[8] = shiftright_int16(y128[8],scale);
+ y128[9] = shiftright_int16(y128[9],scale);
+ y128[10] = shiftright_int16(y128[10],scale);
+ y128[11] = shiftright_int16(y128[11],scale);
+ y128[12] = shiftright_int16(y128[12],scale);
+ y128[13] = shiftright_int16(y128[13],scale);
+ y128[14] = shiftright_int16(y128[14],scale);
+ y128[15] = shiftright_int16(y128[15],scale);
y128+=16;
}
@@ -8591,6 +8591,8 @@ void dft1200(int16_t *x,int16_t *y,unsigned char scale_flag)
}
+//#define round trunc
+
void init_rad4(int N,int16_t *tw) {
int16_t *twa = tw;
@@ -8760,6 +8762,8 @@ void init_dfts(void)
init_rad4_rep(1200,twa1200,twb1200,twc1200);
}
+//#undef round
+
#ifdef MR_MAIN
#include <string.h>
#include <stdio.h>
diff --git a/openair1/PHY/TOOLS/tools_defs.h b/openair1/PHY/TOOLS/tools_defs.h
index e5233efb63429b6a1cc32b0e25d73fb812a392bb..4253eb28d303420c443b90fcba34c8d303222235 100644
--- a/openair1/PHY/TOOLS/tools_defs.h
+++ b/openair1/PHY/TOOLS/tools_defs.h
@@ -32,8 +32,6 @@
#include <stdint.h>
#include "PHY/sse_intrin.h"
-#define CEILIDIV(a,b) ((a+b-1)/b)
-#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1))
struct complex {
double x;
diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h
index 7b64002a887c8fbe86383db91b0b143cc4990483..3a0f5728ae47c9849c9cdda56d3a4bacf476225a 100644
--- a/openair1/PHY/defs_gNB.h
+++ b/openair1/PHY/defs_gNB.h
@@ -632,17 +632,12 @@ typedef struct PHY_VARS_gNB_s {
nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL];
NR_gNB_COMMON common_vars;
NR_gNB_PRACH prach_vars;
- NR_gNB_PUSCH *pusch_vars[NUMBER_OF_UE_MAX];
+ NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX];
NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams
NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords]
NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p;
NR_gNB_DLSCH_t *dlsch_PCH;
-/*
- LTE_eNB_UE_stats UE_stats[NUMBER_OF_UE_MAX];
- LTE_eNB_UE_stats *UE_stats_ptr[NUMBER_OF_UE_MAX];
-*/
uint8_t pbch_configured;
- // uint8_t pbch_pdu[4]; //PBCH_PDU_SIZE
char gNB_generate_rar;
/// NR synchronization sequences
@@ -665,7 +660,7 @@ typedef struct PHY_VARS_gNB_s {
uint32_t nr_gold_pusch[2][20][2][NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD];
/// Indicator set to 0 after first SR
- uint8_t first_sr[NUMBER_OF_UE_MAX];
+ uint8_t first_sr[NUMBER_OF_NR_SR_MAX];
/// PRACH root sequence
uint32_t X_u[64][839];
@@ -679,7 +674,6 @@ typedef struct PHY_VARS_gNB_s {
/// N0 (used for abstraction)
double N0;
- unsigned char first_run_timing_advance[NUMBER_OF_UE_MAX];
unsigned char first_run_I0_measurements;
@@ -697,89 +691,29 @@ typedef struct PHY_VARS_gNB_s {
/// counter to average prach energh over first 100 prach opportunities
int prach_energy_counter;
- // PDSCH Variables
- PDSCH_CONFIG_DEDICATED pdsch_config_dedicated[NUMBER_OF_UE_MAX];
-
- // PUSCH Varaibles
- PUSCH_CONFIG_DEDICATED pusch_config_dedicated[NUMBER_OF_UE_MAX];
-
- // PUCCH variables
- PUCCH_CONFIG_DEDICATED pucch_config_dedicated[NUMBER_OF_UE_MAX];
-
- // UL-POWER-Control
- UL_POWER_CONTROL_DEDICATED ul_power_control_dedicated[NUMBER_OF_UE_MAX];
-
- // TPC
- TPC_PDCCH_CONFIG tpc_pdcch_config_pucch[NUMBER_OF_UE_MAX];
- TPC_PDCCH_CONFIG tpc_pdcch_config_pusch[NUMBER_OF_UE_MAX];
-
- // CQI reporting
- CQI_REPORT_CONFIG cqi_report_config[NUMBER_OF_UE_MAX];
-
- // SRS Variables
- SOUNDINGRS_UL_CONFIG_DEDICATED soundingrs_ul_config_dedicated[NUMBER_OF_UE_MAX];
- uint8_t ncs_cell[20][7];
-
- // Scheduling Request Config
- SCHEDULING_REQUEST_CONFIG scheduling_request_config[NUMBER_OF_UE_MAX];
-
- // Transmission mode per UE
- uint8_t transmission_mode[NUMBER_OF_UE_MAX];
-
- /// cba_last successful reception for each group, used for collision detection
- uint8_t cba_last_reception[4];
-
- // Pointers for active physicalConfigDedicated to be applied in current slot
- struct PhysicalConfigDedicated *physicalConfigDedicated[NUMBER_OF_UE_MAX];
-
-
- uint32_t rb_mask_ul[4];
-
- /// Information regarding TM5
- MU_MIMO_mode mu_mimo_mode[NUMBER_OF_UE_MAX];
-
-
- /// target_ue_dl_mcs : only for debug purposes
- uint32_t target_ue_dl_mcs;
- /// target_ue_ul_mcs : only for debug purposes
- uint32_t target_ue_ul_mcs;
- /// target_ue_dl_rballoc : only for debug purposes
- uint32_t ue_dl_rb_alloc;
- /// target ul PRBs : only for debug
- uint32_t ue_ul_nb_rb;
-
- ///check for Total Transmissions
- uint32_t check_for_total_transmissions;
-
- ///check for MU-MIMO Transmissions
- uint32_t check_for_MUMIMO_transmissions;
-
- ///check for SU-MIMO Transmissions
- uint32_t check_for_SUMIMO_transmissions;
-
- ///check for FULL MU-MIMO Transmissions
- uint32_t FULL_MUMIMO_transmissions;
-
- /// Counter for total bitrate, bits and throughput in downlink
- uint32_t total_dlsch_bitrate;
- uint32_t total_transmitted_bits;
- uint32_t total_system_throughput;
-
- int hw_timing_advance;
-
+ /*
time_stats_t phy_proc;
+ */
time_stats_t phy_proc_tx;
+ /*
time_stats_t phy_proc_rx;
+ */
time_stats_t rx_prach;
-
+ /*
time_stats_t ofdm_mod_stats;
+ */
time_stats_t dlsch_encoding_stats;
time_stats_t dlsch_modulation_stats;
time_stats_t dlsch_scrambling_stats;
+ time_stats_t tinput;
+ time_stats_t tprep;
+ time_stats_t tparity;
+ time_stats_t toutput;
+
time_stats_t dlsch_rate_matching_stats;
- time_stats_t dlsch_turbo_encoding_stats;
time_stats_t dlsch_interleaving_stats;
-
+ time_stats_t dlsch_segmentation_stats;
+ /*
time_stats_t rx_dft_stats;
time_stats_t ulsch_channel_estimation_stats;
time_stats_t ulsch_freq_offset_estimation_stats;
@@ -790,29 +724,7 @@ typedef struct PHY_VARS_gNB_s {
time_stats_t ulsch_deinterleaving_stats;
time_stats_t ulsch_demultiplexing_stats;
time_stats_t ulsch_llr_stats;
- time_stats_t ulsch_tc_init_stats;
- time_stats_t ulsch_tc_alpha_stats;
- time_stats_t ulsch_tc_beta_stats;
- time_stats_t ulsch_tc_gamma_stats;
- time_stats_t ulsch_tc_ext_stats;
- time_stats_t ulsch_tc_intl1_stats;
- time_stats_t ulsch_tc_intl2_stats;
-
-#ifdef LOCALIZATION
- /// time state for localization
- time_stats_t localization_stats;
-#endif
-
- int32_t pucch1_stats_cnt[NUMBER_OF_UE_MAX][10];
- int32_t pucch1_stats[NUMBER_OF_UE_MAX][10*1024];
- int32_t pucch1_stats_thres[NUMBER_OF_UE_MAX][10*1024];
- int32_t pucch1ab_stats_cnt[NUMBER_OF_UE_MAX][10];
- int32_t pucch1ab_stats[NUMBER_OF_UE_MAX][2*10*1024];
- int32_t pusch_stats_rb[NUMBER_OF_UE_MAX][10240];
- int32_t pusch_stats_round[NUMBER_OF_UE_MAX][10240];
- int32_t pusch_stats_mcs[NUMBER_OF_UE_MAX][10240];
- int32_t pusch_stats_bsr[NUMBER_OF_UE_MAX][10240];
- int32_t pusch_stats_BO[NUMBER_OF_UE_MAX][10240];
+ */
} PHY_VARS_gNB;
#endif
diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h
index 1fa1bf3fe434c1b3091ff52ef5b5d2651df0bf86..a1f9ca9bdca9078d278a5530b4866b8cd8c52e40 100644
--- a/openair1/PHY/defs_nr_UE.h
+++ b/openair1/PHY/defs_nr_UE.h
@@ -45,6 +45,7 @@
#include <math.h>
#include "common_lib.h"
#include "msc.h"
+#include "fapi_nr_ue_interface.h"
//#include <complex.h>
#include "assertions.h"
@@ -470,65 +471,7 @@ typedef struct {
#ifdef NR_PDCCH_DEFS_NR_UE
#define MAX_NR_DCI_DECODED_SLOT 10 // This value is not specified
-#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3)
-#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1
-
-#define IDENTIFIER_DCI_FORMATS 0
-#define CARRIER_IND 1
-#define SUL_IND_0_1 2
-#define SLOT_FORMAT_IND 3
-#define PRE_EMPTION_IND 4
-#define BLOCK_NUMBER 5
-#define CLOSE_LOOP_IND 6
-#define BANDWIDTH_PART_IND 7
-#define SHORT_MESSAGE_IND 8
-#define SHORT_MESSAGES 9
-#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10
-#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11
-#define TIME_DOM_RESOURCE_ASSIGNMENT 12
-#define VRB_TO_PRB_MAPPING 13
-#define PRB_BUNDLING_SIZE_IND 14
-#define RATE_MATCHING_IND 15
-#define ZP_CSI_RS_TRIGGER 16
-#define FREQ_HOPPING_FLAG 17
-#define TB1_MCS 18
-#define TB1_NDI 19
-#define TB1_RV 20
-#define TB2_MCS 21
-#define TB2_NDI 22
-#define TB2_RV 23
-#define MCS 24
-#define NDI 25
-#define RV 26
-#define HARQ_PROCESS_NUMBER 27
-#define DAI_ 28
-#define FIRST_DAI 29
-#define SECOND_DAI 30
-#define TB_SCALING 31
-#define TPC_PUSCH 32
-#define TPC_PUCCH 33
-#define PUCCH_RESOURCE_IND 34
-#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35
-#define SRS_RESOURCE_IND 36
-#define PRECOD_NBR_LAYERS 37
-#define ANTENNA_PORTS 38
-#define TCI 39
-#define SRS_REQUEST 40
-#define TPC_CMD 41
-#define CSI_REQUEST 42
-#define CBGTI 43
-#define CBGFI 44
-#define PTRS_DMRS 45
-#define BETA_OFFSET_IND 46
-#define DMRS_SEQ_INI 47
-#define UL_SCH_IND 48
-#define PADDING_NR_DCI 49
-#define SUL_IND_0_0 50
-#define RA_PREAMBLE_INDEX 51
-#define SUL_IND_1_0 52
-#define SS_PBCH_INDEX 53
-#define PRACH_MASK_INDEX 54
-#define RESERVED_NR_DCI 55
+
typedef enum {
@@ -759,12 +702,6 @@ typedef struct {
/// \brief PDCCH/DCI e-sequence (input to rate matching).
/// - first index: ? [0..96*N_RB_DL[
int16_t *e_rx;
- /// number of PDCCH symbols in current subframe
- uint8_t num_pdcch_symbols;
- /// Allocated CRNTI for UE
- uint16_t crnti;
- /// 1: the allocated crnti is Temporary C-RNTI / 0: otherwise
- uint8_t crnti_is_temporary;
/// Total number of PDU errors (diagnostic mode)
uint32_t dci_errors;
/// Total number of PDU received
@@ -773,11 +710,14 @@ typedef struct {
uint32_t dci_false;
/// Total number of DCI missed (diagnostic mode)
uint32_t dci_missed;
- /// nCCE for PUCCH per subframe
+ /// nCCE for PDCCH per subframe
uint8_t nCCE[10];
//Check for specific DCIFormat and AgregationLevel
uint8_t dciFormat;
uint8_t agregationLevel;
+ int nb_search_space;
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t pdcch_config[FAPI_NR_MAX_SS_PER_CORESET];
+ /*
#ifdef NR_PDCCH_DEFS_NR_UE
int nb_searchSpaces;
// CORESET structure, where maximum number of CORESETs to be handled is 3 (according to 38.331 V15.1.0)
@@ -788,7 +728,7 @@ typedef struct {
int n_RB_BWP[NR_NBR_SEARCHSPACE_ACT_BWP];
uint32_t nb_search_space;
-#endif
+ #endif*/
} NR_UE_PDCCH;
#define PBCH_A 24
@@ -949,6 +889,7 @@ typedef struct {
// point to the current rxTx thread index
uint8_t current_thread_id[40];
+ t_nrPolar_params *polarList;
NR_UE_PDSCH *pdsch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX+1]; // two RxTx Threads
NR_UE_PDSCH_FLP *pdsch_vars_flp[NUMBER_OF_CONNECTED_eNB_MAX+1];
NR_UE_PDSCH *pdsch_vars_SI[NUMBER_OF_CONNECTED_eNB_MAX+1];
diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h
index baf5915dadd8b320494d6ead5b5ef204f90c3869..bf57f0ab0701978f613b545abe097255a38eb4da 100644
--- a/openair1/PHY/defs_nr_common.h
+++ b/openair1/PHY/defs_nr_common.h
@@ -102,7 +102,7 @@
#define NR_MAX_PUSCH_ENCODED_LENGTH NR_MAX_PDSCH_ENCODED_LENGTH
#define NR_MAX_PDSCH_TBS 3824
-#define MAX_NUM_NR_DLSCH_SEGMENTS 16
+#define MAX_NUM_NR_DLSCH_SEGMENTS 24
#define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056)
#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS
diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
index b4cc540cc711307a5d2227a570c1ce82bad657ff..d672472c612ecefcb93f0e1e90e8637fe3343338 100644
--- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c
+++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
@@ -207,7 +207,14 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
AMP, frame, slot, fp, 0,
&gNB->dlsch_encoding_stats,
&gNB->dlsch_scrambling_stats,
- &gNB->dlsch_modulation_stats);
+ &gNB->dlsch_modulation_stats,
+ &gNB->tinput,
+ &gNB->tprep,
+ &gNB->tparity,
+ &gNB->toutput,
+ &gNB->dlsch_rate_matching_stats,
+ &gNB->dlsch_interleaving_stats,
+ &gNB->dlsch_segmentation_stats);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
}
diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
index 39230a3bf6005c43c15da48721a05b505484286e..b8c6412238877b43300d9477ebdfbf10eb62b7b3 100644
--- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
@@ -54,7 +54,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
// Note: we have to handle the thread IDs for this. To be revisited completely.
uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
- NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
+ NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0];
//NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms;
@@ -66,40 +66,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
if(scheduled_response->dl_config != NULL){
fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config;
+ LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus);
+ pdcch_vars->nb_search_space = 0;
for(i=0; i<dl_config->number_pdus; ++i){
if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){
- pdcch_vars2->nb_search_space = pdcch_vars2->nb_search_space + 1;
- fapi_nr_dl_config_dci_dl_pdu_rel15_t *dci_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
-
- pdcch_vars2->n_RB_BWP[i] = dci_config->N_RB_BWP;
- pdcch_vars2->searchSpace[i].monitoringSymbolWithinSlot = dci_config->monitoring_symbols_within_slot;
-
- pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel1 = dci_config->number_of_candidates[0];
- pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel2 = dci_config->number_of_candidates[1];
- pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel4 = dci_config->number_of_candidates[2];
- pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel8 = dci_config->number_of_candidates[3];
- pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config->number_of_candidates[4];
-
- pdcch_vars2->coreset[i].duration = dci_config->coreset.duration;
-
- pdcch_vars2->coreset[i].frequencyDomainResources = dci_config->coreset.frequency_domain_resource;
- pdcch_vars2->coreset[i].rb_offset = dci_config->coreset.rb_offset;
-
- if(dci_config->coreset.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){
- pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = dci_config->coreset.cce_reg_interleaved_shift_index;
- pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = dci_config->coreset.cce_reg_interleaved_reg_bundle_size;
- pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size;
- }else{ //CCE_REG_MAPPING_TYPE_NON_INTERLEAVED
- pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = 0;
- pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 6;
- pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 1;
- }
-
- pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity;
- //pdcch_vars2->coreset[i].tciStatesPDCCH;
- //pdcch_vars2->coreset[i].tciPresentInDCI;
- pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config->coreset.pdcch_dmrs_scrambling_id;
-
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
+ memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config));
+ pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1;
+ LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space);
}else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
// dlsch config pdu
@@ -113,11 +87,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid];
-
+ dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart;
+ dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize;
dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs;
dlsch0_harq->start_rb = dlsch_config_pdu->start_rb;
dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols;
dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol;
+ dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos;
+ dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType;
dlsch0_harq->mcs = dlsch_config_pdu->mcs;
dlsch0_harq->DCINdi = dlsch_config_pdu->ndi;
dlsch0_harq->rvidx = dlsch_config_pdu->rv;
@@ -132,7 +109,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
}
}
}else{
- pdcch_vars2->nb_search_space = 0;
+ pdcch_vars->nb_search_space = 0;
}
if(scheduled_response->ul_config != NULL){
diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
index 52db68aebc583c6bb4cb0c25ebb16cddd8d36ca3..d3c0f9e2917ea14121b4a85ba8fb3a65b7de0de6 100644
--- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
@@ -94,30 +94,15 @@ char mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"};
extern double cpuf;
+
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
uint32_t frame,
- uint8_t nr_tti_rx,
- uint8_t eNB_id,
- MIMO_mode_t mimo_mode,
- uint32_t high_speed_flag,
- uint8_t is_secondary_ue,
- int nb_coreset_active,
- uint16_t symbol_mon,
- NR_SEARCHSPACE_TYPE_t searchSpaceType);
-
-uint8_t nr_dci_decoding_procedure(int s,
- int p,
- PHY_VARS_NR_UE *ue,
- NR_DCI_ALLOC_t *dci_alloc,
- NR_SEARCHSPACE_TYPE_t searchSpacetype,
- int16_t eNB_id,
- uint8_t nr_tti_rx,
- uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- crc_scrambled_t *crc_scrambled,
- format_found_t *format_found,
- uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
+ uint32_t slot);
+
+uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
+ int frame,
+ int nr_tti_rx,
+ fapi_nr_dci_indication_t *dci_ind);
/*
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
@@ -2803,10 +2788,15 @@ unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb
#ifdef NR_PDCCH_SCHED
-int nr_ue_pdcch_procedures(uint8_t eNB_id,
- PHY_VARS_NR_UE *ue,
- UE_nr_rxtx_proc_t *proc)
+int nr_ue_pdcch_procedures(uint8_t gNB_id,
+ PHY_VARS_NR_UE *ue,
+ UE_nr_rxtx_proc_t *proc)
{
+ int frame_rx = proc->frame_rx;
+ int nr_tti_rx = proc->nr_tti_rx;
+ unsigned int dci_cnt=0;
+
+ /*
// unsigned int dci_cnt=0, i; //removed for nr_ue_pdcch_procedures and added in the loop for nb_coreset_active
#ifdef NR_PDCCH_SCHED_DEBUG
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_ue_pdcch_procedures() \n");
@@ -2815,10 +2805,10 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
int frame_rx = proc->frame_rx;
int nr_tti_rx = proc->nr_tti_rx;
NR_DCI_ALLOC_t dci_alloc_rx[8];
- /*
- uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1);
- uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
- */
+
+ //uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1);
+ //uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
+
// table dci_fields_sizes_cnt contains dci_fields_sizes for each time a dci is decoded in the slot
// each element represents the size in bits for each dci field, for each decoded dci -> [dci_cnt-1]
@@ -2871,22 +2861,22 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
for (nb_searchspace_active=0; nb_searchspace_active<nb_searchspace_total; nb_searchspace_active++){
int nb_coreset_active=nb_searchspace_active;
//int do_pdcch_monitoring_current_slot=1; // this variable can be removed and fapi is handling
- /*
- * The following code has been removed as it is handled by higher layers (fapi)
- *
+
+ // The following code has been removed as it is handled by higher layers (fapi)
+ //
// Verify that monitoring is required at the slot nr_tti_rx. We will run pdcch procedure only if do_pdcch_monitoring_current_slot=1
// For Type0-PDCCH searchspace, we need to calculate the monitoring slot from Tables 13-1 .. 13-15 in TS 38.213 Subsection 13
- NR_UE_SLOT_PERIOD_OFFSET_t sl_period_offset_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset;
- if (sl_period_offset_mon == nr_sl1) {
- do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot
- } else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) {
- do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset
- }*/
- /*
- * FIXME
- * For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10
- * To be implemented LATER !!!
- */
+ //NR_UE_SLOT_PERIOD_OFFSET_t sl_period_offset_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset;
+ //if (sl_period_offset_mon == nr_sl1) {
+ //do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot
+ //} else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) {
+ //do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset
+ //}
+
+ // FIXME
+ // For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10
+ // To be implemented LATER !!!
+
//int _offset,_index,_M;
//int searchSpace_id = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceId;
@@ -2906,11 +2896,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
// at the moment we will not take into consideration this variable and we will consider that the OFDM symbol offset is always the first OFDM in a symbol
uint16_t symbol_within_slot_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSymbolWithinSlot;
// get the remaining parameters describing the current SEARCHSPACE: // FIXME! To be defined where we get this information from
- /*NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1;
- NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2;
- NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4;
- NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8;
- NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16;*/
+ //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1;
+ //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2;
+ //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4;
+ //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8;
+ //NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16;
// FIXME! A table of five enum elements
// searchSpaceType indicates whether this is a common search space or a UE-specific search space
//int searchSpaceType = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceType.type;
@@ -2920,27 +2910,27 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
searchSpaceType);
#endif
- /*while ((searchSpace_coreset_id != pdcch_vars2->coreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_active<nb_coreset_total)) {
+ //while ((searchSpace_coreset_id != pdcch_vars2->coreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_active<nb_coreset_total)) {
// we need to identify the CORESET associated to the active searchSpace
- nb_coreset_active++;
+ //nb_coreset_active++;
if (nb_coreset_active >= nb_coreset_total) return 0; // the coreset_id could not be found. There is a problem
- }*/
+ }
- /*
- * we do not need these parameters yet
- *
+
+ //we do not need these parameters yet
+
// get the parameters describing the current CORESET
- int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration;
- uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources;
- int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex;
- NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize;
- NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize;
- NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity;
- int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH;
- int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI;
- uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID;
- */
+ //int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration;
+ //uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources;
+ //int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex;
+ // NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize;
+ // NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize;
+ // NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity;
+ // int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH;
+ // int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI;
+ // uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID;
+
// A set of PDCCH candidates for a UE to monitor is defined in terms of PDCCH search spaces.
// Searchspace types:
@@ -2987,108 +2977,53 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
searchSpaceType);
#endif
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN);
+ */
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_IN);
+ nr_rx_pdcch(ue,
+ proc->frame_rx,
+ nr_tti_rx);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT);
+
- crc_scrambled_t crc_scrambled;
- format_found_t format_found=255;
-
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN);
#ifdef NR_PDCCH_SCHED_DEBUG
- printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with eNB_id=%d (n_RB_ULBWP=%d, n_RB_DLBWP=%d, searchSpaceType=%d, nb_searchspace_active=%d, nb_coreset_active=%d)\n",
- eNB_id,
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- searchSpaceType,
- nb_searchspace_active,
- nb_coreset_active);
-
+ printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with (nb_searchspace_active=%d)\n",
+ pdcch_vars->nb_search_space);
#endif
- dci_cnt += nr_dci_decoding_procedure(nb_searchspace_active,
- nb_coreset_active,
- ue,
- &dci_alloc_rx[dci_cnt],
- searchSpaceType, // if we're in PUSCH don't listen to common search space,
- // later when we need paging or RA during connection, update this ...
- eNB_id,
- nr_tti_rx,
- dci_fields_sizes_cnt,
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- &crc_scrambled,
- &format_found,
- crc_scrambled_values);
+ fapi_nr_dci_indication_t dci_ind;
+ nr_downlink_indication_t dl_indication;
+ memset((void*)&dci_ind,0,sizeof(dci_ind));
+ memset((void*)&dl_indication,0,sizeof(dl_indication));
+ dci_cnt = nr_dci_decoding_procedure(ue,
+ proc->frame_rx,
+ nr_tti_rx,
+ &dci_ind);
+
#ifdef NR_PDCCH_SCHED_DEBUG
- printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
+ LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
#endif
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT);
+ //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
+
+ for (int i=0; i<dci_cnt; i++) {
+ LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x : format %d\n",
+ ue->Mod_id,frame_rx%1024,nr_tti_rx,mode_string[ue->UE_mode[0]],
+ i,
+ dci_ind.dci_list[i].rnti,
+ dci_ind.dci_list[i].dci_format);
+ }
+ ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt;
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT);
- //LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
-
- /*
- uint8_t *nCCE_current = &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->nCCE[nr_tti_rx];
- uint8_t *nCCE_dest = &ue->pdcch_vars[next1_thread_id][eNB_id]->nCCE[nr_tti_rx];
- uint8_t *nCCE_dest1 = &ue->pdcch_vars[next2_thread_id][eNB_id]->nCCE[nr_tti_rx];
- memcpy(nCCE_dest, nCCE_current, sizeof(uint8_t));
- memcpy(nCCE_dest1, nCCE_current, sizeof(uint8_t));
-
- LOG_D(PHY,"current_thread %d next1_thread %d next2_thread %d \n", ue->current_thread_id[nr_tti_rx], next1_thread_id, next2_thread_id);
- */
-
- LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x / crnti %x : format %d\n",
- ue->Mod_id,frame_rx%1024,nr_tti_rx,mode_string[ue->UE_mode[eNB_id]],
- dci_cnt,
- dci_alloc_rx[0].rnti,
- ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti,
- dci_alloc_rx[0].format );
- ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dci_received += dci_cnt;
-
-#ifdef EMOS
- //emos_dump_UE.dci_cnt[nr_tti_rx] = dci_cnt;
-#endif
dci_ind.number_of_dcis = dci_cnt;
-
+ /*
for (int i=0; i<dci_cnt; i++) {
- /*
- * This is the NR part
- */
- if ((dci_alloc_rx[i].format == format0_0)){
- }
-
- if (dci_alloc_rx[i].format == format1_0) {
- if ((dci_alloc_rx[i].rnti != crc_scrambled_values[_P_RNTI_]) &&
- (dci_alloc_rx[i].rnti != crc_scrambled_values[_SI_RNTI_]) &&
- (dci_alloc_rx[i].rnti != crc_scrambled_values[_RA_RNTI_]))
- ue->dlsch_received[eNB_id]++;
-
- if (dci_alloc_rx[i].rnti == crc_scrambled_values[_SI_RNTI_])
- ue->dlsch_SI_received[eNB_id]++;
- if (dci_alloc_rx[i].rnti == crc_scrambled_values[_P_RNTI_])
- ue->dlsch_p_received[eNB_id]++;
- if (dci_alloc_rx[i].rnti == crc_scrambled_values[_RA_RNTI_])
- ue->dlsch_ra_received[eNB_id]++;
- }
-
- if ((dci_alloc_rx[i].format == format2_0)){
- }
- if ((dci_alloc_rx[i].format == format2_1)){
- }
- if ((dci_alloc_rx[i].format == format2_2)){
- }
- if ((dci_alloc_rx[i].format == format2_3)){
- }
- if ((dci_alloc_rx[i].format == format0_1)){ // This format not implemented at a first time. FIXME
- }
- if ((dci_alloc_rx[i].format == format1_1)){ // This format not implemented at a first time. FIXME
- }
- uint8_t status=0;
-
- LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_alloc_rx[i].format,dci_alloc_rx[i].rnti,dci_alloc_rx[i].dci_length,dci_alloc_rx[i].dci_pdu[0],dci_alloc_rx[i].dci_pdu[1]);
-
memset(&dci_ind.dci_list[i].dci,0,sizeof(fapi_nr_dci_pdu_rel15_t));
dci_ind.dci_list[i].rnti = dci_alloc_rx[i].rnti;
@@ -3117,36 +3052,15 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> Ending function nr_extract_dci_info()\n");
- /*
- nr_generate_ue_ul_dlsch_params_from_dci(ue,
- eNB_id,
- frame_rx,
- nr_tti_rx,
- dci_alloc_rx[i].dci_pdu,
- dci_alloc_rx[i].rnti,
- dci_alloc_rx[i].dci_length,
- dci_alloc_rx[i].format,
- ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id],
- ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id],
- ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id],
- ue->ulsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0],
- &ue->frame_parms,
- ue->pdsch_config_dedicated,
- ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id],
- dci_fields_sizes_cnt[i],
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- pdcch_vars2->n_RB_BWP[nb_searchspace_active],
- crc_scrambled_values,
- &nr_dci_info_extracted);
- */
} // end for loop dci_cnt
+ */
// fill dl_indication message
dl_indication.module_id = ue->Mod_id;
dl_indication.cc_id = ue->CC_id;
- dl_indication.gNB_index = eNB_id;
+ dl_indication.gNB_index = gNB_id;
dl_indication.frame = frame_rx;
dl_indication.slot = nr_tti_rx;
dl_indication.rx_ind = NULL; //no data, only dci for now
@@ -3158,10 +3072,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
#if UE_TIMING_TRACE
stop_meas(&ue->dlsch_rx_pdcch_stats);
#endif
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT);
- } // end for loop nb_searchspace_active
+
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT);
return(dci_cnt);
}
#endif // NR_PDCCH_SCHED
@@ -3355,25 +3270,31 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
if (dlsch0 && (!dlsch1)) {
int harq_pid = dlsch0->current_harq_pid;
+ uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart;
+ uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize;
uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb;
uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb;
uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol;
uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols;
- LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1);
+ LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos);
- for (m = s0; m < (s1 + s0); m++) {
-
- if (m==s0)
+ // do channel estimation for first DMRS only
+ for (m = s0; m < 3; m++) {
+ if (((1<<m)&dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos) > 0) {
nr_pdsch_channel_estimation(ue,
0 /*eNB_id*/,
nr_tti_rx,
0 /*p*/,
m,
- ue->frame_parms.first_carrier_offset+pdsch_start_rb*12,
+ ue->frame_parms.first_carrier_offset+(BWPStart + pdsch_start_rb)*12,
pdsch_nb_rb);
-
-
+ LOG_D(PHY,"Channel Estimation in symbol %d\n",m);
+ break;
+ }
+ }
+ for (m = s0; m < (s1 + s0); m++) {
+
dual_stream_UE = 0;
eNB_id_i = eNB_id+1;
i_mod = 0;
@@ -3773,7 +3694,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx);
- LOG_I(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS);
+ LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS);
if(ret<dlsch0->max_ldpc_iterations+1){
// fill dl_indication message
@@ -4140,7 +4061,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
uint16_t start_symb_sch = dlsch0_harq->start_symbol;
- uint8_t nb_symb_pdcch = pdcch_vars->coreset[0].duration;
+ uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0;
uint8_t ssb_periodicity = 10;// ue->ssb_periodicity; // initialized to 5ms in nr_init_ue for scenarios where UE is not configured (otherwise acquired by cell configuration from gNB or LTE)
uint8_t dci_cnt = 0;
fapi_nr_pbch_config_t *pbch_config = &ue->nrUE_config.pbch_config;
@@ -4152,20 +4073,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
*/
- uint8_t coreset_start=0, coreset_start_set=0;
- uint16_t coreset_count = 0;
- uint64_t coreset_freq_dom = pdcch_vars->coreset[0].frequencyDomainResources;
- for (int i = 0; i < 45; i++) {
- if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> (44-i)) & 0x1) {
- if (!coreset_start_set) {
- coreset_start = i;
- coreset_start_set = 1;
- }
- coreset_count++;
- }
- }
- uint16_t coreset_nb_rb = 6 * coreset_count;
- uint16_t coreset_start_rb = 6 * coreset_start;
+
+ int coreset_nb_rb=0;
+ int coreset_start_rb=0;
+ if (pdcch_vars->nb_search_space > 0)
+ get_coreset_rballoc(pdcch_vars->pdcch_config[0].coreset.frequency_domain_resource,&coreset_nb_rb,&coreset_start_rb);
slot_pbch = is_pbch_in_slot(pbch_config, frame_rx, nr_tti_rx, ssb_periodicity, ue->frame_parms.slots_per_frame);
@@ -4220,12 +4132,16 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
0,
0);
- nr_pdcch_channel_estimation(ue,
- 0,
- nr_tti_rx,
- l,
- ue->frame_parms.first_carrier_offset+coreset_start_rb*12,
- coreset_nb_rb);
+ // note: this only works if RBs for PDCCH are contigous!
+ LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n",
+ ue->frame_parms.first_carrier_offset,pdcch_vars->pdcch_config[0].BWPStart,coreset_start_rb);
+ if (coreset_nb_rb > 0)
+ nr_pdcch_channel_estimation(ue,
+ 0,
+ nr_tti_rx,
+ l,
+ ue->frame_parms.first_carrier_offset+(pdcch_vars->pdcch_config[0].BWPStart + coreset_start_rb)*12,
+ coreset_nb_rb);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_OUT);
#if UE_TIMING_TRACE
@@ -4241,7 +4157,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if (dci_cnt > 0) {
- LOG_I(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt);
+ LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt);
} else {
LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx);
@@ -4253,7 +4169,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
//to update from pdsch config
start_symb_sch = dlsch0_harq->start_symbol;
- nr_gold_pdsch(ue,start_symb_sch,0, 1);
+ int symb_dmrs=-1;
+ for (int i=0;i<4;i++) if (((1<<i)&dlsch0_harq->dlDmrsSymbPos) > 0) {symb_dmrs=i;break;}
+ AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n");
+ LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos);
+ nr_gold_pdsch(ue,symb_dmrs,0, 1);
nb_symb_sch = dlsch0_harq->nb_symbols;
@@ -4342,7 +4262,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
// do procedures for C-RNTI
if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) {
- LOG_I(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx);
+ LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN);
#if UE_TIMING_TRACE
diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
index 8236c71c0164019c104e6414289155a8dfa752e6..74a2ea5cbc2c01d2b7f7d19f14874c9f809281d1 100644
--- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
+++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
@@ -211,11 +211,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
/* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */
sr_payload = nr_ue_get_SR(Mod_id,
- CC_id,
- frame_tx,
- gNB_id,
- ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
- nr_tti_tx); // nr_tti_rx used for meas gap
+ CC_id,
+ frame_tx,
+ gNB_id,
+ 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
+ nr_tti_tx); // nr_tti_rx used for meas gap
}
else {
sr_payload = 1;
@@ -590,7 +590,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
case pucch_format2_nr:
{
nr_generate_pucch2(ue,
- ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
+ 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
ue->common_vars.txdataF,
&ue->frame_parms,
&ue->pucch_config_dedicated[gNB_id],
@@ -608,7 +608,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
case pucch_format4_nr:
{
nr_generate_pucch3_4(ue,
- ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
+ 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
ue->common_vars.txdataF,
&ue->frame_parms,
format,
diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c
index f1991e5f739ba389f66a29763747971ce4032f53..e9f26feaca389fb3769e335af7e88ee4c3554a08 100644
--- a/openair1/SIMULATION/NR_PHY/dlsim.c
+++ b/openair1/SIMULATION/NR_PHY/dlsim.c
@@ -64,6 +64,10 @@
//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "NR_RRCReconfiguration.h"
+#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0))
+#include "SIMULATION/LTE_PHY/common_sim.h"
+
+
PHY_VARS_gNB *gNB;
PHY_VARS_NR_UE *UE;
@@ -204,7 +208,6 @@ int main(int argc, char **argv)
uint16_t ssb_periodicity = 10;
//unsigned char frame_type = 0;
- unsigned char pbch_phase = 0;
int frame=0,slot=1;
int frame_length_complex_samples;
@@ -234,8 +237,10 @@ int main(int argc, char **argv)
randominit(0);
+ int mcsIndex_set=0,rbStart_set=0,rbSize_set=0,StartSymbolIndex_set=0,NrOfSymbols_set=0;
+ int print_perf = 0;
- while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dP:IL:Eo:a:b:c:j:e:")) != -1) {
+ while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Eo:a:b:c:j:e:")) != -1) {
switch (c) {
/*case 'f':
write_output_file=1;
@@ -384,11 +389,8 @@ int main(int argc, char **argv)
break;
case 'P':
- pbch_phase = atoi(optarg);
-
- if (pbch_phase>3)
- printf("Illegal PBCH phase (0-3) got %d\n",pbch_phase);
-
+ print_perf=1;
+ opp_enabled=1;
break;
case 'I':
@@ -411,22 +413,27 @@ int main(int argc, char **argv)
case 'a':
dlsch_config.rbStart = atoi(optarg);
+ rbStart_set=1;
break;
case 'b':
dlsch_config.rbSize = atoi(optarg);
+ rbSize_set=1;
break;
case 'c':
dlsch_config.StartSymbolIndex = atoi(optarg);
+ StartSymbolIndex_set=1;
break;
case 'j':
dlsch_config.NrOfSymbols = atoi(optarg);
+ NrOfSymbols_set=1;
break;
case 'e':
dlsch_config.mcsIndex[0] = atoi(optarg);
+ mcsIndex_set=1;
break;
@@ -442,11 +449,10 @@ int main(int argc, char **argv)
printf("-S Ending SNR, runs from SNR0 to SNR1\n");
printf("-t Delay spread for multipath channel\n");
printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n");
- printf("-x Transmission mode (1,2,6 for the moment)\n");
- printf("-y Number of TX antennas used in eNB\n");
+ printf("-y Number of TX antennas used in gNB\n");
printf("-z Number of RX antennas used in UE\n");
- //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n");
- //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n");
+ //printf("-i Relative strength of first intefering gNB (in dB) - cell_id mod 3 = 1\n");
+ //printf("-j Relative strength of second intefering gNB (in dB) - cell_id mod 3 = 2\n");
printf("-M Multiple SSB positions in burst\n");
printf("-N Nid_cell\n");
printf("-R N_RB_DL\n");
@@ -544,9 +550,9 @@ int main(int argc, char **argv)
// common configuration
rrc_mac_config_req_gNB(0,0,scc,0,0,NULL);
// UE dedicated configuration
- rrc_mac_config_req_gNB(0,0,NULL,1,0x1234,secondaryCellGroup);
+ rrc_mac_config_req_gNB(0,0,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup);
phy_init_nr_gNB(gNB,0,0);
-
+ N_RB_DL = gNB->frame_parms.N_RB_DL;
// stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
// call MAC to configure common parameters
@@ -649,8 +655,6 @@ int main(int argc, char **argv)
nr_l2_init_ue();
UE_mac = get_mac_inst(0);
- UE->pdcch_vars[0][0]->crnti = 0x1234;
-
UE->if_inst = nr_ue_if_module_init(0);
UE->if_inst->scheduled_response = nr_ue_scheduled_response;
UE->if_inst->phy_config_request = nr_ue_phy_config_request;
@@ -666,87 +670,19 @@ int main(int argc, char **argv)
unsigned int errors_bit = 0;
uint32_t errors_scrambling = 0;
+
test_input_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384);
estimated_output_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384);
// generate signal
- if (input_fd==NULL) {
- gNB->pbch_configured = 1;
- gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234;
-
- if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config);
- else nr_schedule_css_dlsch_phytest(0,frame,slot);
-
-
- Sched_INFO.module_id = 0;
- Sched_INFO.CC_id = 0;
- Sched_INFO.frame = frame;
- Sched_INFO.slot = slot;
- Sched_INFO.DL_req = &gNB_mac->DL_req[0];
- Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
- Sched_INFO.UL_dci_req = NULL;
- Sched_INFO.TX_req = &gNB_mac->TX_req[0];
- nr_schedule_response(&Sched_INFO);
-
- phy_procedures_gNB_TX(gNB,frame,slot,0);
-
- //nr_common_signal_procedures (gNB,frame,subframe);
- int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
-
- LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
- if (gNB->frame_parms.nb_antennas_tx>1)
- LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
-
- int tx_offset = slot*frame_parms->samples_per_slot;
- printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
-
- //TODO: loop over slots
- for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
-
- if (cyclic_prefix_type == 1) {
- PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
- &txdata[aa][tx_offset],
- frame_parms->ofdm_symbol_size,
- 12,
- frame_parms->nb_prefix_samples,
- CYCLIC_PREFIX);
- } else {
- nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
- &txdata[aa][tx_offset],
- 14,
- frame_parms);
- }
- }
- } else {
- printf("Reading %d samples from file to antenna buffer %d\n",frame_length_complex_samples,0);
-
- if (fread(txdata[0],
- sizeof(int32_t),
- frame_length_complex_samples,
- input_fd) != frame_length_complex_samples) {
- printf("error reading from file\n");
- //exit(-1);
- }
- }
-
- LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
- if (gNB->frame_parms.nb_antennas_tx>1)
- LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
-
- if (output_fd)
- fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
-
- int txlev = signal_energy(&txdata[0][5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
- frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
-
- // printf("txlev %d (%f)\n",txlev,10*log10(txlev));
-
- for (i=0; i<frame_length_complex_samples; i++) {
- for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
- r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
- r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
- }
- }
+ AssertFatal(input_fd==NULL,"Not ready for input signal file\n");
+ gNB->pbch_configured = 1;
+ gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234;
+
+ if (mcsIndex_set==0) dlsch_config.mcsIndex[0]=9;
+ if (rbSize_set==0) dlsch_config.rbSize=N_RB_DL;
+ if (rbStart_set==0) dlsch_config.rbStart=0;
+
//Configure UE
@@ -755,207 +691,221 @@ int main(int argc, char **argv)
rrc.carrier.MIB = (uint8_t*) malloc(4);
rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0);
- nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,scc,NULL,NULL,NULL);
+ nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,scc,secondaryCellGroup->spCellConfig);
- // Initial bandwidth part configuration -- full carrier bandwidth
- UE_mac->initial_bwp_dl.bwp_id = 0;
- UE_mac->initial_bwp_dl.location = 0;
- UE_mac->initial_bwp_dl.scs = UE->frame_parms.subcarrier_spacing;
- UE_mac->initial_bwp_dl.N_RB = UE->frame_parms.N_RB_DL;
- UE_mac->initial_bwp_dl.cyclic_prefix = UE->frame_parms.Ncp;
-
- fapi_nr_dl_config_request_t *dl_config = &UE_mac->dl_config_request;
- // Type0 PDCCH search space
- dl_config->number_pdus = 1;
- dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234;
-
- uint64_t mask = 0x0;
- uint16_t num_rbs;
- uint16_t rb_offset;
-
- get_coreset_rballoc(gNB->pdcch_pdu->pdcch_pdu_rel15.FreqDomainResource,&num_rbs,&rb_offset);
- uint16_t cell_id=0;
- uint16_t num_symbols=2;
- for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
- mask = mask >> 1;
- mask = mask | 0x100000000000;
- }
- uint16_t UE_rb_offset_count = rb_offset/6;
- mask = mask >> UE_rb_offset_count;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset
-
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id;
-
- uint32_t number_of_search_space_per_slot=1;
- uint32_t first_symbol_index=0;
- uint32_t search_space_duration=0; // element of search space
- uint32_t coreset_duration; // element of coreset
+
+ nr_dcireq_t dcireq;
+ nr_scheduled_response_t scheduled_response;
+ memset((void*)&dcireq,0,sizeof(dcireq));
+ memset((void*)&scheduled_response,0,sizeof(scheduled_response));
+ dcireq.module_id = 0;
+ dcireq.gNB_index = 0;
+ dcireq.cc_id = 0;
- coreset_duration = num_symbols * number_of_search_space_per_slot;
+ scheduled_response.dl_config = &dcireq.dl_config_req;
+ scheduled_response.ul_config = &dcireq.ul_config_req;
+ scheduled_response.tx_request = NULL;
+ scheduled_response.module_id = 0;
+ scheduled_response.CC_id = 0;
+ scheduled_response.frame = frame;
+ scheduled_response.slot = slot;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0];
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1];
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
-
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = N_RB_DL;
-
- UE_mac->scheduled_response.dl_config = dl_config;
- UE_mac->scheduled_response.ul_config = NULL;
- UE_mac->scheduled_response.tx_request = NULL;
- UE_mac->scheduled_response.module_id = 0;
- UE_mac->scheduled_response.CC_id = 0;
- UE_mac->scheduled_response.frame = frame;
- UE_mac->scheduled_response.slot = slot;
-
nr_ue_phy_config_request(&UE_mac->phy_config);
for (SNR = snr0; SNR < snr1; SNR += .2) {
+ varArray_t *table_tx=initVarArray(1000,sizeof(double));
+ varArray_t *table_tx_ifft=initVarArray(1000,sizeof(double));
+ reset_meas(&gNB->phy_proc_tx); // total gNB tx
+ reset_meas(&gNB->dlsch_scrambling_stats);
+ reset_meas(&gNB->dlsch_interleaving_stats);
+ reset_meas(&gNB->dlsch_rate_matching_stats);
+ reset_meas(&gNB->dlsch_segmentation_stats);
+ reset_meas(&gNB->dlsch_modulation_stats);
+ reset_meas(&gNB->dlsch_encoding_stats);
+ reset_meas(&gNB->tinput);
+ reset_meas(&gNB->tprep);
+ reset_meas(&gNB->tparity);
+ reset_meas(&gNB->toutput);
+
n_errors = 0;
//n_errors2 = 0;
//n_alamouti = 0;
-
+ errors_scrambling=0;
n_false_positive = 0;
for (trial = 0; trial < n_trials; trial++) {
errors_bit = 0;
//multipath channel
//multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0);
+
+ memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
+ clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
+ if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config);
+ else nr_schedule_css_dlsch_phytest(0,frame,slot);
+
+
+ Sched_INFO.module_id = 0;
+ Sched_INFO.CC_id = 0;
+ Sched_INFO.frame = frame;
+ Sched_INFO.slot = slot;
+ Sched_INFO.DL_req = &gNB_mac->DL_req[0];
+ Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
+ Sched_INFO.UL_dci_req = NULL;
+ Sched_INFO.TX_req = &gNB_mac->TX_req[0];
+ nr_schedule_response(&Sched_INFO);
+
+ phy_procedures_gNB_TX(gNB,frame,slot,0);
+
+ //nr_common_signal_procedures (gNB,frame,subframe);
+ int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
+
+ if (n_trials==1) {
+ LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
+ if (gNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
+ }
+ int tx_offset = slot*frame_parms->samples_per_slot;
+ if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
+
+ //TODO: loop over slots
+ for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
+
+ if (cyclic_prefix_type == 1) {
+ PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
+ &txdata[aa][tx_offset],
+ frame_parms->ofdm_symbol_size,
+ 12,
+ frame_parms->nb_prefix_samples,
+ CYCLIC_PREFIX);
+ } else {
+ nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
+ &txdata[aa][tx_offset],
+ 14,
+ frame_parms);
+ }
+ }
+
+ if (n_trials==1) {
+ LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
+ if (gNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
+ }
+ if (output_fd)
+ fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
+
+ int txlev = signal_energy(&txdata[0][(slot*frame_parms->samples_per_slot)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
+ frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
+
+ // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev));
+
+ for (i=0; i<frame_length_complex_samples; i++) {
+ for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
+ r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
+ r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
+ }
+ }
+
+ NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
+ nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15;
//AWGN
- sigma2_dB = 10 * log10((double)txlev) - SNR;
+ sigma2_dB = 10 * log10((double)txlev * (N_RB_DL/rel15.rbSize)) - SNR;
sigma2 = pow(10, sigma2_dB/10);
- // printf("sigma2 %f (%f dB)\n",sigma2,sigma2_dB);
-
+ if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev* (N_RB_DL/rel15.rbSize)),(double)N_RB_DL/rel15.rbSize);
+
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
}
}
-
- if (n_trials == 1) {
-
- LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
- if (UE->frame_parms.nb_antennas_rx>1)
- LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
-
- }
-
- if (UE->is_synchronized == 0) {
-
- UE_nr_rxtx_proc_t proc={0};
- ret = nr_initial_sync(&proc, UE, normal_txrx,1);
- printf("nr_initial_sync1 returns %d\n",ret);
- if (ret<0) n_errors++;
- }
- else {
- UE->rx_offset=0;
- UE_proc.frame_rx = frame;
- UE_proc.nr_tti_rx= slot;
- UE_proc.subframe_rx = slot;
-
- nr_ue_scheduled_response(&UE_mac->scheduled_response);
-
- printf("Running phy procedures UE RX %d.%d\n",frame,slot);
- phy_procedures_nrUE_RX(UE,
- &UE_proc,
- 0,
- do_pdcch_flag,
- normal_txrx);
-
- if (n_trials==1) {
- LOG_M("rxsigF0.m","rxsF0", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[0],slot_length_complex_samples_no_prefix,1,1);
- if (UE->frame_parms.nb_antennas_rx>1)
- LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[1],slot_length_complex_samples_no_prefix,1,1);
- }
-
- if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
- UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
- n_errors++;
-
- //----------------------------------------------------------
- //---------------------- count errors ----------------------
- //----------------------------------------------------------
-
- NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
-
- NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
- int harq_pid = dlsch0->current_harq_pid;
- NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
-
- NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]];
- int16_t *UE_llr = pdsch_vars[0]->llr[0];
-
- nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15;
- uint32_t TBS = rel15.TBSize[0];
- uint16_t length_dmrs = 1;
- uint16_t nb_rb = rel15.rbSize;
- uint8_t nb_re_dmrs = rel15.dmrsConfigType == 1 ? 6 : 4;
- uint8_t mod_order = rel15.qamModOrder[0];
- uint8_t nb_symb_sch = rel15.NrOfSymbols;
-
- available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers);
-
- printf("\n");
- printf("available_bits = %u\n", available_bits);
+
+ UE->rx_offset=0;
+ UE_proc.frame_rx = frame;
+ UE_proc.nr_tti_rx= slot;
+ UE_proc.subframe_rx = slot;
+
+ dcireq.frame = frame;
+ dcireq.slot = slot;
+
+ nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
+ nr_ue_scheduled_response(&scheduled_response);
+
+ phy_procedures_nrUE_RX(UE,
+ &UE_proc,
+ 0,
+ do_pdcch_flag,
+ normal_txrx);
+
+ if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
+ UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
+ n_errors++;
+
+ //----------------------------------------------------------
+ //---------------------- count errors ----------------------
+ //----------------------------------------------------------
+
+
+
+ NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
+
+ int harq_pid = dlsch0->current_harq_pid;
+ NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
+
+ NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]];
+ int16_t *UE_llr = pdsch_vars[0]->llr[0];
+
+
+ uint32_t TBS = rel15.TBSize[0];
+ uint16_t length_dmrs = 1;
+ uint16_t nb_rb = rel15.rbSize;
+ uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4;
+ uint8_t mod_order = rel15.qamModOrder[0];
+ uint8_t nb_symb_sch = rel15.NrOfSymbols;
+
+ available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers);
+
+ for (i = 0; i < available_bits; i++) {
- for (i = 0; i < available_bits; i++) {
-
- if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) ||
- ((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0)))
- {
- if(errors_scrambling == 0) {
- printf("\n");
- printf("First bit in error in unscrambling = %d\n",i);
- }
- errors_scrambling++;
+ if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) ||
+ ((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0)))
+ {
+ if(errors_scrambling == 0) {
+ LOG_D(PHY,"\n");
+ LOG_D(PHY,"First bit in error in unscrambling = %d\n",i);
}
-
- }
-
- for (i = 0; i < TBS; i++) {
-
- estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7);
- test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments
-
- if (estimated_output_bit[i] != test_input_bit[i]) {
- if(errors_bit == 0)
- printf("First bit in error in decoding = %d\n",i);
- errors_bit++;
+ errors_scrambling++;
}
-
- }
- ////////////////////////////////////////////////////////////
+ }
+
+ for (i = 0; i < TBS; i++) {
- if (errors_scrambling > 0) {
- if (n_trials == 1)
- printf("errors_scrambling = %d (trial %d)\n", errors_scrambling, trial);
- }
+ estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7);
+ test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments
- if (errors_bit > 0) {
- n_false_positive++;
- if (n_trials == 1)
- printf("errors_bit = %u (trial %d)\n", errors_bit, trial);
+ if (estimated_output_bit[i] != test_input_bit[i]) {
+ if(errors_bit == 0)
+ LOG_D(PHY,"First bit in error in decoding = %d (errors scrambling %d)\n",i,errors_scrambling);
+ errors_bit++;
}
- printf("\n");
-
- } // if (UE->is_synchronized == 0)
+ }
+
+ ////////////////////////////////////////////////////////////
+
+ if (errors_scrambling > 0) {
+ if (n_trials == 1)
+ printf("errors_scrambling = %d (trial %d)\n", errors_scrambling, trial);
+ }
+
+ if (errors_bit > 0) {
+ n_false_positive++;
+ if (n_trials == 1)
+ printf("errors_bit = %u (trial %d)\n", errors_bit, trial);
+ }
} // noise trials
@@ -964,14 +914,71 @@ int main(int argc, char **argv)
(float) n_errors / (float) n_trials);
printf("*****************************************\n");
printf("\n");
- printf("SNR %f : n_errors (negative CRC) = %d/%d\n", SNR, n_errors, n_trials);
+ printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials);
printf("\n");
+ if (n_trials == 1) {
+
+ LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
+ if (UE->frame_parms.nb_antennas_rx>1)
+ LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
+ LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1);
+ write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1);
+ break;
+ }
+
if ((float)n_errors/(float)n_trials <= target_error_rate) {
printf("PDSCH test OK\n");
break;
}
+
+ if (print_perf==1) {
+ printf("\ngNB TX function statistics (per %d us slot)\n",1000>>*scc->ssbSubcarrierSpacing);
+ printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx");
+ printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time");
+ printStatIndent3(&gNB->dlsch_segmentation_stats,"DLSCH segmentation time");
+ printStatIndent3(&gNB->tinput,"DLSCH LDPC input processing time");
+ printStatIndent3(&gNB->tprep,"DLSCH LDPC input preparation time");
+ printStatIndent3(&gNB->tparity,"DLSCH LDPC parity generation time");
+ printStatIndent3(&gNB->toutput,"DLSCH LDPC output generation time");
+ printStatIndent3(&gNB->dlsch_rate_matching_stats,"DLSCH Rate Mataching time");
+ printStatIndent3(&gNB->dlsch_interleaving_stats, "DLSCH Interleaving time");
+ printStatIndent2(&gNB->dlsch_modulation_stats,"DLSCH modulation time");
+ printStatIndent2(&gNB->dlsch_scrambling_stats, "DLSCH scrambling time");
+
+
+ printf("\nUE RX function statistics (per %d us slot)\n",1000>>*scc->ssbSubcarrierSpacing);
+ /*
+ printDistribution(&phy_proc_rx_tot, table_rx,"Total PHY proc rx");
+ printStatIndent(&ue_front_end_tot,"Front end processing");
+ printStatIndent(&dlsch_llr_tot,"rx_pdsch processing");
+ printStatIndent2(&pdsch_procedures_tot,"pdsch processing");
+ printStatIndent2(&dlsch_procedures_tot,"dlsch processing");
+ printStatIndent2(&UE->crnti_procedures_stats,"C-RNTI processing");
+ printStatIndent(&UE->ofdm_demod_stats,"ofdm demodulation");
+ printStatIndent(&UE->dlsch_channel_estimation_stats,"DLSCH channel estimation time");
+ printStatIndent(&UE->dlsch_freq_offset_estimation_stats,"DLSCH frequency offset estimation time");
+ printStatIndent(&dlsch_decoding_tot, "DLSCH Decoding time ");
+ printStatIndent(&UE->dlsch_unscrambling_stats,"DLSCH unscrambling time");
+ printStatIndent(&UE->dlsch_rate_unmatching_stats,"DLSCH Rate Unmatching");
+ printf("|__ DLSCH Turbo Decoding(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n",
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus ?
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus :
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus,
+ UE->dlsch_tc_intl1_stats.trials/(double)UE->dlsch_tc_init_stats.trials,
+ (double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials*timeBase,
+ (int)((double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials),
+ UE->dlsch_turbo_decoding_stats.trials);
+ printStatIndent2(&UE->dlsch_tc_init_stats,"init");
+ printStatIndent2(&UE->dlsch_tc_alpha_stats,"alpha");
+ printStatIndent2(&UE->dlsch_tc_beta_stats,"beta");
+ printStatIndent2(&UE->dlsch_tc_gamma_stats,"gamma");
+ printStatIndent2(&UE->dlsch_tc_ext_stats,"ext");
+ printStatIndent2(&UE->dlsch_tc_intl1_stats,"turbo internal interleaver");
+ printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
+ */
+ }
} // NSR
for (i = 0; i < 2; i++) {
diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h
index aeeb3932457aa6e1fcb514600eaa96fc744b93f1..1784098b7915be424635e1cbbe9b95165e3e35ae 100644
--- a/openair2/COMMON/platform_constants.h
+++ b/openair2/COMMON/platform_constants.h
@@ -99,6 +99,7 @@
#define NUMBER_OF_NR_DLSCH_MAX 2//16
#define NUMBER_OF_NR_ULSCH_MAX 2//16
+#define NUMBER_OF_NR_SR_MAX 16
#define MAX_MANAGED_ENB_PER_MOBILE 2
diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c
index 759b8fd78225ed4f9891ac449b547fc48d6a2e6f..eb8866869ec87adac18e951a401007dae413d858 100755
--- a/openair2/LAYER2/NR_MAC_UE/config_ue.c
+++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c
@@ -135,8 +135,8 @@ int nr_rrc_mac_config_req_ue(
uint8_t gNB_index,
NR_MIB_t *mibP,
NR_ServingCellConfigCommon_t *sccP,
- NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
- NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
+ // NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
+ // NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
NR_SpCellConfig_t *spCell_ConfigP ){
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
@@ -147,123 +147,87 @@ int nr_rrc_mac_config_req_ue(
NR_ServingCellConfigCommon_t *scc;
if(mibP != NULL){
- mac->mib = mibP; // update by every reception
+ mac->mib = mibP; // update by every reception
}
- if(mac_cell_group_configP != NULL){
- if(mac_cell_group_configP->drx_Config != NULL ){
- switch(mac_cell_group_configP->drx_Config->present){
- case NR_SetupRelease_DRX_Config_PR_NOTHING:
- break;
- case NR_SetupRelease_DRX_Config_PR_release:
- mac->drx_Config = NULL;
- break;
- case NR_SetupRelease_DRX_Config_PR_setup:
- mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup;
- break;
- default:
- break;
- }
- }
-
- if(mac_cell_group_configP->schedulingRequestConfig != NULL ){
- mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig;
- }
-
- if(mac_cell_group_configP->bsr_Config != NULL ){
- mac->bsr_Config = mac_cell_group_configP->bsr_Config;
- }
-
- if(mac_cell_group_configP->tag_Config != NULL ){
- mac->tag_Config = mac_cell_group_configP->tag_Config;
- }
-
- if(mac_cell_group_configP->phr_Config != NULL ){
- switch(mac_cell_group_configP->phr_Config->present){
- case NR_SetupRelease_PHR_Config_PR_NOTHING:
- break;
- case NR_SetupRelease_PHR_Config_PR_release:
- mac->phr_Config = NULL;
- break;
- case NR_SetupRelease_PHR_Config_PR_setup:
- mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup;
- break;
- default:
- break;
- }
-
- }
-
- if(phy_cell_group_configP->cs_RNTI != NULL ){
- switch(phy_cell_group_configP->cs_RNTI->present){
- case NR_SetupRelease_RNTI_Value_PR_NOTHING:
- break;
- case NR_SetupRelease_RNTI_Value_PR_release:
- mac->cs_RNTI = NULL;
- break;
- case NR_SetupRelease_RNTI_Value_PR_setup:
- mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup;
- break;
- default:
- break;
- }
-
- }
-
- }
-
- if(phy_cell_group_configP != NULL ){
- //config_phy(phy_cell_group_config, NULL);
- }
-
-// TODO check
+
+
if(spCell_ConfigP != NULL ){
- mac->servCellIndex = spCell_ConfigP->servCellIndex;
- if (spCell_ConfigP->reconfigurationWithSync) {
- mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
- config_common_ue(mac);
+ mac->servCellIndex = spCell_ConfigP->servCellIndex;
+ if (spCell_ConfigP->reconfigurationWithSync) {
+ mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
+ config_common_ue(mac);
+ mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity;
+ LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti);
+ }
+ mac->scd = spCell_ConfigP->spCellConfigDedicated;
+
+ /*
+ if(mac_cell_group_configP != NULL){
+ if(mac_cell_group_configP->drx_Config != NULL ){
+ switch(mac_cell_group_configP->drx_Config->present){
+ case NR_SetupRelease_DRX_Config_PR_NOTHING:
+ break;
+ case NR_SetupRelease_DRX_Config_PR_release:
+ mac->drx_Config = NULL;
+ break;
+ case NR_SetupRelease_DRX_Config_PR_setup:
+ mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup;
+ break;
+ default:
+ break;
+ }
}
- mac->scd = spCell_ConfigP->spCellConfigDedicated;
- }
-
-
-#if 0
- if(serving_cell_config != NULL ){
- if(serving_cell_config->tdd_UL_DL_ConfigurationDedicated != NULL ){
- mac->tdd_UL_DL_ConfigurationDedicated = serving_cell_config->tdd_UL_DL_ConfigurationDedicated;
- }
-
- if(spcell_config->initialDownlinkBWP != NULL ){
- mac->init_DL_BWP = spcell_config->initialDownlinkBWP;
- }
-
- // storage list of DL BWP config. TODO should be modify to maintain(add/release) a list inside MAC instance, this implementation just use for one-shot RRC configuration setting.
- if(spcell_config->downlinkBWP_ToAddModList != NULL ){
- mac->BWP_Downlink_list = spcell_config->downlinkBWP_ToAddModList->list;
- mac->BWP_Downlink_count = spcell_config->downlinkBWP_ToAddModList->count;
- }
-
- if(spcell_config->bwp_InactivityTimer != NULL ){
- mac->bwp_InactivityTimer = spcell_config->bwp_InactivityTimer;
- }
-
- if(spcell_config->defaultDownlinkBWP_Id != NULL ){
- mac->defaultDownlinkBWP_Id = spcell_config->defaultDownlinkBWP_Id;
- }
-
- if(spcell_config->pdsch_ServingCellConfig != NULL ){
- mac->pdsch_ServingCellConfig = spcell_config->pdsch_ServingCellConfig;
- }
-
- if(spcell_config->csi_MeasConfig != NULL ){
- mac->csi_MeasConfig = spcell_config->csi_MeasConfig;
- }
-
- spcell_config->tag_Id = spcell_config.tag_Id;
- }
-#endif
- //scell config not yet
-
+
+ if(mac_cell_group_configP->schedulingRequestConfig != NULL ){
+ mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig;
+ }
+
+ if(mac_cell_group_configP->bsr_Config != NULL ){
+ mac->bsr_Config = mac_cell_group_configP->bsr_Config;
+ }
+
+ if(mac_cell_group_configP->tag_Config != NULL ){
+ mac->tag_Config = mac_cell_group_configP->tag_Config;
+ }
+
+ if(mac_cell_group_configP->phr_Config != NULL ){
+ switch(mac_cell_group_configP->phr_Config->present){
+ case NR_SetupRelease_PHR_Config_PR_NOTHING:
+ break;
+ case NR_SetupRelease_PHR_Config_PR_release:
+ mac->phr_Config = NULL;
+ break;
+ case NR_SetupRelease_PHR_Config_PR_setup:
+ mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+
+ if(phy_cell_group_configP != NULL ){
+ if(phy_cell_group_configP->cs_RNTI != NULL ){
+ switch(phy_cell_group_configP->cs_RNTI->present){
+ case NR_SetupRelease_RNTI_Value_PR_NOTHING:
+ break;
+ case NR_SetupRelease_RNTI_Value_PR_release:
+ mac->cs_RNTI = NULL;
+ break;
+ case NR_SetupRelease_RNTI_Value_PR_setup:
+ mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ */
+ }
+
return 0;
+
}
diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h
index 76077aaeaa7a13273e8c514927c44ed5a439b74e..ac9ead3d9110fb6efaee21981484ee39820aaf39 100755
--- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h
+++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h
@@ -56,6 +56,7 @@
#include "NR_ServingCellConfig.h"
#include "fapi_nr_ue_interface.h"
#include "NR_IF_Module.h"
+#include "../NR_MAC_gNB/nr_mac_common.h"
#include "PHY/defs_nr_common.h"
@@ -68,6 +69,13 @@ typedef enum {
} SFN_C_TYPE;
+#define MAX_NUM_BWP 2
+
+typedef enum {
+ RA_IDLE=0,
+ WAIT_RAR=1,
+ WAIT_CONTENTION_RESOLUTION=2
+} RA_state_t;
/*!\brief Top level UE MAC structure */
typedef struct {
@@ -82,20 +90,27 @@ typedef struct {
NR_PHR_Config_t *phr_Config;
NR_RNTI_Value_t *cs_RNTI;
NR_MIB_t *mib;
-
+
+ NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP];
+ NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP];
+ NR_ControlResourceSet_t *coreset[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP];
+ NR_SearchSpace_t *SSpace[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP][FAPI_NR_MAX_SS_PER_CORESET];
+
/// Type0-PDCCH seach space
fapi_nr_dl_config_dci_dl_pdu_rel15_t type0_pdcch_dci_config;
uint32_t type0_pdcch_ss_mux_pattern;
SFN_C_TYPE type0_pdcch_ss_sfn_c;
uint32_t type0_pdcch_ss_n_c;
uint32_t type0_pdcch_consecutive_slots;
-
- /// Random access parameter
+ /// state of RA procedure
+ RA_state_t ra_state;
+ /// RA-rnti
uint16_t ra_rnti;
- //BWP params
- NR_BWP_PARMS initial_bwp_dl;
- NR_BWP_PARMS initial_bwp_ul;
+ /// Temporary CRNTI
+ uint16_t t_crnti;
+ /// CRNTI
+ uint16_t crnti;
//// FAPI-like interface message
fapi_nr_tx_request_t tx_request;
@@ -138,7 +153,139 @@ typedef enum frequency_range_e {
FR2
} frequency_range_t;
+typedef struct {
+ uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
+ uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
+ uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
+ uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
+ uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
+ uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
+ uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
+ uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
+ uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
+ uint8_t short_messages ; // 9 SHORT_MESSAGES:
+ uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
+ // (NOTE 1) If DCI format 0_0 is monitored in common search space
+ // and if the number of information bits in the DCI format 0_0 prior to padding
+ // is larger than the payload size of the DCI format 1_0 monitored in common search space
+ // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
+ // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
+ uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ // where I the number of entries in the higher layer parameter pusch-AllocationList
+ uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
+ uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
+ uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
+ uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
+ uint8_t tb1_mcs ; // 18 TB1_MCS:
+ uint8_t tb1_ndi ; // 19 TB1_NDI:
+ uint8_t tb1_rv ; // 20 TB1_RV:
+ uint8_t tb2_mcs ; // 21 TB2_MCS:
+ uint8_t tb2_ndi ; // 22 TB2_NDI:
+ uint8_t tb2_rv ; // 23 TB2_RV:
+ uint8_t mcs ; // 24 MCS:
+ uint8_t ndi ; // 25 NDI:
+ uint8_t rv ; // 26 RV:
+ uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
+ uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
+ // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
+ // 0 otherwise
+ uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
+ uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
+ uint8_t tb_scaling ; // 31 TB_SCALING:
+ uint8_t tpc_pusch ; // 32 TPC_PUSCH:
+ uint8_t tpc_pucch ; // 33 TPC_PUCCH:
+ uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
+ uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
+ uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
+ uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
+ uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
+ uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
+ uint8_t srs_request ; // 40 SRS_REQUEST:
+ uint8_t tpc_cmd ; // 41 TPC_CMD:
+ uint8_t csi_request ; // 42 CSI_REQUEST:
+ uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
+ uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
+ uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
+ uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
+ uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
+ // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
+ uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
+ uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
+ // and if the number of information bits in the DCI format 0_0 prior to padding
+ // is less than the payload size of the DCI format 1_0 monitored in common search space
+ // zeros shall be appended to the DCI format 0_0
+ // until the payload size equals that of the DCI format 1_0
+ uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
+ uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
+ uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
+ uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
+ uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
+ uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
+} nr_dci_pdu_rel15_t;
+
#define NUM_SLOT_FRAME 10
+#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3)
+#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1
+
+#define IDENTIFIER_DCI_FORMATS 0
+#define CARRIER_IND 1
+#define SUL_IND_0_1 2
+#define SLOT_FORMAT_IND 3
+#define PRE_EMPTION_IND 4
+#define BLOCK_NUMBER 5
+#define CLOSE_LOOP_IND 6
+#define BANDWIDTH_PART_IND 7
+#define SHORT_MESSAGE_IND 8
+#define SHORT_MESSAGES 9
+#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10
+#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11
+#define TIME_DOM_RESOURCE_ASSIGNMENT 12
+#define VRB_TO_PRB_MAPPING 13
+#define PRB_BUNDLING_SIZE_IND 14
+#define RATE_MATCHING_IND 15
+#define ZP_CSI_RS_TRIGGER 16
+#define FREQ_HOPPING_FLAG 17
+#define TB1_MCS 18
+#define TB1_NDI 19
+#define TB1_RV 20
+#define TB2_MCS 21
+#define TB2_NDI 22
+#define TB2_RV 23
+#define MCS 24
+#define NDI 25
+#define RV 26
+#define HARQ_PROCESS_NUMBER 27
+#define DAI_ 28
+#define FIRST_DAI 29
+#define SECOND_DAI 30
+#define TB_SCALING 31
+#define TPC_PUSCH 32
+#define TPC_PUCCH 33
+#define PUCCH_RESOURCE_IND 34
+#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35
+#define SRS_RESOURCE_IND 36
+#define PRECOD_NBR_LAYERS 37
+#define ANTENNA_PORTS 38
+#define TCI 39
+#define SRS_REQUEST 40
+#define TPC_CMD 41
+#define CSI_REQUEST 42
+#define CBGTI 43
+#define CBGFI 44
+#define PTRS_DMRS 45
+#define BETA_OFFSET_IND 46
+#define DMRS_SEQ_INI 47
+#define UL_SCH_IND 48
+#define PADDING_NR_DCI 49
+#define SUL_IND_0_0 50
+#define RA_PREAMBLE_INDEX 51
+#define SUL_IND_1_0 52
+#define SS_PBCH_INDEX 53
+#define PRACH_MASK_INDEX 54
+#define RESERVED_NR_DCI 55
+
/*@}*/
#endif /*__LAYER2_MAC_DEFS_H__ */
diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h
index aa469b84a97eb09c1592ee0012a2c5dc89de38c1..485327a9ae0c51dea7bb50d1bb5324bea031dcb9 100755
--- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h
+++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h
@@ -20,7 +20,7 @@
*/
/* \file proto.h
- * \brief MAC functions prototypes for eNB and UE
+ * \brief MAC functions prototypes for gNB and UE
* \author R. Knopp, K.H. HSU
* \date 2018
* \version 0.1
@@ -64,18 +64,14 @@ int8_t nr_ue_decode_mib(
\param gNB_index gNB index
\param mibP pointer to RRC message MIB
\param sccP pointer to ServingCellConfigCommon structure,
- \param mac_cell_group_configP pointer to RRC message MAC-related in cell group config
- \param phy_cell_group_configP pointer to RRC message PHY-related in cell group config
\param spcell_configP pointer to RRC message serving cell config*/
-int nr_rrc_mac_config_req_ue(
- module_id_t module_id,
- int cc_id,
- uint8_t gNB_index,
- NR_MIB_t *mibP,
+int nr_rrc_mac_config_req_ue(
+ module_id_t module_id,
+ int cc_idP,
+ uint8_t gNB_index,
+ NR_MIB_t *mibP,
NR_ServingCellConfigCommon_t *sccP,
- NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
- NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
- NR_SpCellConfig_t *spcell_configP );
+ NR_SpCellConfig_t *spCell_ConfigP);
/**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/
int nr_l2_init_ue(void);
@@ -118,7 +114,8 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
-int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
+int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
+int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci);
uint32_t get_ssb_frame(uint32_t test);
uint32_t get_ssb_slot(uint32_t ssb_index);
@@ -132,11 +129,23 @@ void nr_ue_process_mac_pdu(
uint8_t CC_id,
uint8_t *pduP,
uint16_t mac_pdu_len,
- uint8_t eNB_index);
+ uint8_t gNB_index);
int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len);
-void nr_ue_send_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_frame_t subframeP, uint8_t * sdu, uint16_t sdu_len, uint8_t eNB_index);
+void nr_ue_send_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_frame_t subframeP, uint8_t * sdu, uint16_t sdu_len, uint8_t gNB_index);
+
+void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot);
+
+int nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
+ int dci_format,
+ uint8_t dci_length,
+ uint16_t rnti,
+ uint64_t *dci_pdu,
+ nr_dci_pdu_rel15_t *nr_pdci_info_extracted);
+
+
+
#endif
/** @}*/
diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
index 9e4a0873ff1cbaf5347eaee5b1e789d78058d631..ee09bb4eb4f540a7d70ecfd52eeff47b7ee45847 100644
--- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
@@ -36,598 +36,603 @@
#include "assertions.h"
#include "PHY/defs_nr_UE.h"
#include "common/utils/LOG/log.h"
-#include "openair2/LAYER2/MAC/mac.h"
+#include "mac_defs.h"
+#include "../MAC/mac.h"
+#include "../NR_MAC_gNB/nr_mac_common.h"
+#include "common/utils/nr/nr_common.h"
#include <stdio.h>
#include <math.h>
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
+#define DEBUG_EXTRACT_DCI 1
extern void mac_rlc_data_ind (
- const module_id_t module_idP,
- const rnti_t rntiP,
- const eNB_index_t eNB_index,
- const frame_t frameP,
- const eNB_flag_t enb_flagP,
- const MBMS_flag_t MBMS_flagP,
- const logical_chan_id_t channel_idP,
- char *buffer_pP,
- const tb_size_t tb_sizeP,
- num_tb_t num_tbP,
- crc_t *crcs_pP);
+ const module_id_t module_idP,
+ const rnti_t rntiP,
+ const eNB_index_t eNB_index,
+ const frame_t frameP,
+ const eNB_flag_t enb_flagP,
+ const MBMS_flag_t MBMS_flagP,
+ const logical_chan_id_t channel_idP,
+ char *buffer_pP,
+ const tb_size_t tb_sizeP,
+ num_tb_t num_tbP,
+ crc_t *crcs_pP);
uint32_t get_ssb_slot(uint32_t ssb_index){
- // this function now only support f <= 3GHz
- return ssb_index & 0x3 ;
+ // this function now only support f <= 3GHz
+ return ssb_index & 0x3 ;
- // return first_symbol(case, freq, ssb_index) / 14
+ // return first_symbol(case, freq, ssb_index) / 14
}
uint8_t table_9_2_2_1[16][8]={
-{0,12,2, 0, 0,3,0,0},
-{0,12,2, 0, 0,4,8,0},
-{0,12,2, 3, 0,4,8,0},
-{1,10,4, 0, 0,6,0,0},
-{1,10,4, 0, 0,3,6,9},
-{1,10,4, 2, 0,3,6,9},
-{1,10,4, 4, 0,3,6,9},
-{1,4, 10,0, 0,6,0,0},
-{1,4, 10,0, 0,3,6,9},
-{1,4, 10,2, 0,3,6,9},
-{1,4, 10,4, 0,3,6,9},
-{1,0, 14,0, 0,6,0,0},
-{1,0, 14,0, 0,3,6,9},
-{1,0, 14,2, 0,3,6,9},
-{1,0, 14,4, 0,3,6,9},
-{1,0, 14,26,0,3,0,0}
+ {0,12,2, 0, 0,3,0,0},
+ {0,12,2, 0, 0,4,8,0},
+ {0,12,2, 3, 0,4,8,0},
+ {1,10,4, 0, 0,6,0,0},
+ {1,10,4, 0, 0,3,6,9},
+ {1,10,4, 2, 0,3,6,9},
+ {1,10,4, 4, 0,3,6,9},
+ {1,4, 10,0, 0,6,0,0},
+ {1,4, 10,0, 0,3,6,9},
+ {1,4, 10,2, 0,3,6,9},
+ {1,4, 10,4, 0,3,6,9},
+ {1,0, 14,0, 0,6,0,0},
+ {1,0, 14,0, 0,3,6,9},
+ {1,0, 14,2, 0,3,6,9},
+ {1,0, 14,4, 0,3,6,9},
+ {1,0, 14,26,0,3,0,0}
};
int8_t nr_ue_process_dlsch(module_id_t module_id,
- int cc_id,
- uint8_t gNB_index,
- fapi_nr_dci_indication_t *dci_ind,
- void *pduP,
- uint32_t pdu_len)
+ int cc_id,
+ uint8_t gNB_index,
+ fapi_nr_dci_indication_t *dci_ind,
+ void *pduP,
+ uint32_t pdu_len)
{
- NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
- //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
- nr_phy_config_t *phy_config = &mac->phy_config;
-
- //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
- // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ.
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
+ //fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
+ nr_phy_config_t *phy_config = &mac->phy_config;
+
+ //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
+ // First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ.
+ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
+ for (int i=0; i<10; i++) {
+ if(dci_ind!=NULL){
+ if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
+ }
+ }
+ if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
+ // fill in the elements in config request inside P5 message
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0;
+ for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0;
+ //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0;
+ } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
- for (int i=0; i<10; i++) {
- if(dci_ind!=NULL){
- if (dci_ind->dci_list[i].dci_format < 2) ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- }
+ // If we handle PUCCH common
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0]; /* format 0 1 2 3 4 */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4]; /* x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2]; /* x x x x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /* x x x x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0; /* x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3]; /* maxNrofPhysicalResourceBlocks = 275 */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
+ for (int i=0;i<NUMBER_PUCCH_FORMAT_NR;i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;
+ // If we handle PUCCH dedicated
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format; /* format 0 1 2 3 4 */
+ switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){
+ case pucch_format1_nr:
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi;
+ break;
+ case pucch_format2_nr:
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi;
+ break;
+ case pucch_format3_nr:
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi;
+ break;
+ case pucch_format4_nr:
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi;
+ break;
+ default:
+ break;
}
- if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
- // fill in the elements in config request inside P5 message
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0;
- for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0;
- //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0;
- } else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ
- ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
- // If we handle PUCCH common
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][0]; /* format 0 1 2 3 4 */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][4]; /* x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][2]; /* x x x x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][1]; /* x x x x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = 0; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = 0; /* x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = table_9_2_2_1[phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_resource_common][3]; /* maxNrofPhysicalResourceBlocks = 275 */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = 0; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = 0; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
- for (int i=0;i<NUMBER_PUCCH_FORMAT_NR;i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;
- // If we handle PUCCH dedicated
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].format; /* format 0 1 2 3 4 */
- switch (ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.format){
- case pucch_format1_nr:
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.inter_slot_frequency_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.additional_dmrs;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.max_code_rate;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.number_of_slots;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.pi2bpsk;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format1.simultaneous_harq_ack_csi;
- break;
- case pucch_format2_nr:
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.inter_slot_frequency_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.additional_dmrs;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.max_code_rate;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.number_of_slots;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.pi2bpsk;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format2.simultaneous_harq_ack_csi;
- break;
- case pucch_format3_nr:
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.inter_slot_frequency_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.additional_dmrs;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.max_code_rate;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.number_of_slots;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.pi2bpsk;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format3.simultaneous_harq_ack_csi;
- break;
- case pucch_format4_nr:
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.interslotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.inter_slot_frequency_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.additionalDMRS = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.additional_dmrs;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.maxCodeRate = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.max_code_rate;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSlots = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.number_of_slots;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pi2PBSK = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.pi2bpsk;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.simultaneousHARQ_ACK_CSI = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.format4.simultaneous_harq_ack_csi;
- break;
- default:
- break;
- }
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift; /* x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols; /* x x x x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /* x x x x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs; /* x x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb; /* maxNrofPhysicalResourceBlocks = 275 */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index; /* x */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
- for (int i=0;i<NUMBER_PUCCH_FORMAT_NR; i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
- ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.initialCyclicShift = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].initial_cyclic_shift; /* x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofSymbols = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_symbols; /* x x x x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingSymbolIndex = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_symbol_index; /* x x x x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.timeDomainOCC = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].time_domain_occ; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.nrofPRBs = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].number_of_prbs; /* x x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.startingPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].starting_prb; /* maxNrofPhysicalResourceBlocks = 275 */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_length = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_length; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.occ_Index = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].occ_index; /* x */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.intraSlotFrequencyHopping = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].intra_slot_frequency_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.secondHopPRB = phy_config->config_req.ul_bwp_dedicated.pucch_config_dedicated.multi_csi_pucch_resources[0].second_hop_prb;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.pucch_GroupHopping = phy_config->config_req.ul_bwp_common.pucch_config_common.pucch_group_hopping;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.hoppingId = phy_config->config_req.ul_bwp_common.pucch_config_common.hopping_id;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_nominal = phy_config->config_req.ul_bwp_common.pucch_config_common.p0_nominal;
+ for (int i=0;i<NUMBER_PUCCH_FORMAT_NR; i++) ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.deltaF_PUCCH_f[i] = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Id = 0; /* INTEGER (1..8) */
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.p0_PUCCH_Value = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pucch_config_pdu.twoPUCCH_PC_AdjustmentStates = 0;
- }
- if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){
- mac->if_module->scheduled_response(&mac->scheduled_response);
- }
- return 0;
+ }
+ if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){
+ mac->if_module->scheduled_response(&mac->scheduled_response);
+ }
+ return 0;
}
int8_t nr_ue_decode_mib(
- UE_nr_rxtx_proc_t *proc,
- module_id_t module_id,
- int cc_id,
- uint8_t gNB_index,
- uint8_t extra_bits, // 8bits 38.212 c7.1.1
- uint32_t ssb_length,
- uint32_t ssb_index,
- void *pduP,
- uint16_t cell_id ){
+ UE_nr_rxtx_proc_t *proc,
+ module_id_t module_id,
+ int cc_id,
+ uint8_t gNB_index,
+ uint8_t extra_bits, // 8bits 38.212 c7.1.1
+ uint32_t ssb_length,
+ uint32_t ssb_index,
+ void *pduP,
+ uint16_t cell_id ){
- LOG_I(MAC,"[L2][MAC] decode mib\n");
+ LOG_D(MAC,"[L2][MAC] decode mib\n");
- NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 ); // fixed 3 bytes MIB PDU
+ nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 ); // fixed 3 bytes MIB PDU
- AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n");
- //if(mac->mib != NULL){
- uint16_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused);
- uint16_t frame_number_4lsb = 0;
- for (int i=0; i<4; i++)
- frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i);
- uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4]
- uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5]
+ AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n");
+ //if(mac->mib != NULL){
+ uint16_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused);
+ uint16_t frame_number_4lsb = 0;
+ for (int i=0; i<4; i++)
+ frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i);
+ uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4]
+ uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5]
- uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset;
+ uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset;
- //uint32_t ssb_index = 0; // TODO: ssb_index should obtain from L1 in case Lssb != 64
+ //uint32_t ssb_index = 0; // TODO: ssb_index should obtain from L1 in case Lssb != 64
- frame = frame << 4;
- frame = frame | frame_number_4lsb;
+ frame = frame << 4;
+ frame = frame | frame_number_4lsb;
- if(ssb_length == 64){
- ssb_index = ssb_index & (( extra_bits >> 2 ) & 0x1C ); // { extra_bits[5:7], ssb_index[2:0] }
- }else{
- if(ssb_subcarrier_offset_msb){
- ssb_subcarrier_offset = ssb_subcarrier_offset | 0x10;
- }
- }
+ if(ssb_length == 64){
+ ssb_index = ssb_index & (( extra_bits >> 2 ) & 0x1C ); // { extra_bits[5:7], ssb_index[2:0] }
+ }else{
+ if(ssb_subcarrier_offset_msb){
+ ssb_subcarrier_offset = ssb_subcarrier_offset | 0x10;
+ }
+ }
#ifdef DEBUG_MIB
- LOG_I(MAC,"system frame number(6 MSB bits): %d\n", mac->mib->systemFrameNumber.buf[0]);
- LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame);
- LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon);
- LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset);
- LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position);
- LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1);
- LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
- LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
- LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit);
- LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
+ LOG_I(MAC,"system frame number(6 MSB bits): %d\n", mac->mib->systemFrameNumber.buf[0]);
+ LOG_I(MAC,"system frame number(with LSB): %d\n", (int)frame);
+ LOG_I(MAC,"subcarrier spacing (0=15or60, 1=30or120): %d\n", (int)mac->mib->subCarrierSpacingCommon);
+ LOG_I(MAC,"ssb carrier offset(with MSB): %d\n", (int)ssb_subcarrier_offset);
+ LOG_I(MAC,"dmrs type A position (0=pos2,1=pos3): %d\n", (int)mac->mib->dmrs_TypeA_Position);
+ LOG_I(MAC,"pdcch config sib1: %d\n", (int)mac->mib->pdcch_ConfigSIB1);
+ LOG_I(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
+ LOG_I(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
+ LOG_I(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit);
+ LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
#endif
- subcarrier_spacing_t scs_ssb = scs_30kHz; // default for
- //const uint32_t scs_index = 0;
- const uint32_t num_slot_per_frame = 20;
- subcarrier_spacing_t scs_pdcch;
+ subcarrier_spacing_t scs_ssb = scs_30kHz; // default for
+ //const uint32_t scs_index = 0;
+ const uint32_t num_slot_per_frame = 20;
+ subcarrier_spacing_t scs_pdcch;
- // assume carrier frequency < 6GHz
- if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){
- scs_pdcch = scs_15kHz;
- }else{ //NR_MIB__subCarrierSpacingCommon_scs30or120
- scs_pdcch = scs_30kHz;
- }
+ // assume carrier frequency < 6GHz
+ if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){
+ scs_pdcch = scs_15kHz;
+ }else{ //NR_MIB__subCarrierSpacingCommon_scs30or120
+ scs_pdcch = scs_30kHz;
+ }
- channel_bandwidth_t min_channel_bw = bw_10MHz; // deafult for testing
+ channel_bandwidth_t min_channel_bw = bw_10MHz; // deafult for testing
- uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13
- frequency_range_t frequency_range = FR1;
- uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero);
- uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
- int32_t num_rbs = -1;
- int32_t num_symbols = -1;
- int32_t rb_offset = -1;
- //LOG_I(MAC,"<<<<<<<<<configSIB1 %d index_4msb %d index_4lsb %d scs_ssb %d scs_pdcch %d switch %d ",
- //mac->mib->pdcch_ConfigSIB1,index_4msb,index_4lsb,scs_ssb,scs_pdcch, (scs_ssb << 5)|scs_pdcch);
-
- // type0-pdcch coreset
- switch( (scs_ssb << 5)|scs_pdcch ){
- case (scs_15kHz << 5) | scs_15kHz :
- AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_1_c2[index_4msb];
- num_symbols = table_38213_13_1_c3[index_4msb];
- rb_offset = table_38213_13_1_c4[index_4msb];
- break;
-
- case (scs_15kHz << 5) | scs_30kHz:
- AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_2_c2[index_4msb];
- num_symbols = table_38213_13_2_c3[index_4msb];
- rb_offset = table_38213_13_2_c4[index_4msb];
- break;
-
- case (scs_30kHz << 5) | scs_15kHz:
- if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
- AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_3_c2[index_4msb];
- num_symbols = table_38213_13_3_c3[index_4msb];
- rb_offset = table_38213_13_3_c4[index_4msb];
- }else if(min_channel_bw & bw_40MHz){
- AssertFatal(index_4msb < 9, "38.213 Table 13-5 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_5_c2[index_4msb];
- num_symbols = table_38213_13_5_c3[index_4msb];
- rb_offset = table_38213_13_5_c4[index_4msb];
- }else{ ; }
-
- break;
-
- case (scs_30kHz << 5) | scs_30kHz:
- if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_4_c2[index_4msb];
- num_symbols = table_38213_13_4_c3[index_4msb];
- rb_offset = table_38213_13_4_c4[index_4msb];
- LOG_I(MAC,"<<<<<<<<<index_4msb %d num_rbs %d num_symb %d rb_offset %d\n",index_4msb,num_rbs,num_symbols,rb_offset );
- }else if(min_channel_bw & bw_40MHz){
- AssertFatal(index_4msb < 10, "38.213 Table 13-6 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_6_c2[index_4msb];
- num_symbols = table_38213_13_6_c3[index_4msb];
- rb_offset = table_38213_13_6_c4[index_4msb];
- }else{ ; }
- break;
-
- case (scs_120kHz << 5) | scs_60kHz:
- AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n");
- if(index_4msb & 0x7){
- mac->type0_pdcch_ss_mux_pattern = 1;
- }else if(index_4msb & 0x18){
- mac->type0_pdcch_ss_mux_pattern = 2;
- }else{ ; }
-
- num_rbs = table_38213_13_7_c2[index_4msb];
- num_symbols = table_38213_13_7_c3[index_4msb];
- if(!is_condition_A && (index_4msb == 8 || index_4msb == 10)){
- rb_offset = table_38213_13_7_c4[index_4msb] - 1;
- }else{
- rb_offset = table_38213_13_7_c4[index_4msb];
- }
- break;
-
- case (scs_120kHz << 5) | scs_120kHz:
- AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n");
- if(index_4msb & 0x3){
- mac->type0_pdcch_ss_mux_pattern = 1;
- }else if(index_4msb & 0x0c){
- mac->type0_pdcch_ss_mux_pattern = 3;
- }
-
- num_rbs = table_38213_13_8_c2[index_4msb];
- num_symbols = table_38213_13_8_c3[index_4msb];
- if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
- rb_offset = table_38213_13_8_c4[index_4msb] - 1;
- }else{
- rb_offset = table_38213_13_8_c4[index_4msb];
- }
- break;
-
- case (scs_240kHz << 5) | scs_60kHz:
- AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n");
- mac->type0_pdcch_ss_mux_pattern = 1;
- num_rbs = table_38213_13_9_c2[index_4msb];
- num_symbols = table_38213_13_9_c3[index_4msb];
- rb_offset = table_38213_13_9_c4[index_4msb];
- break;
-
- case (scs_240kHz << 5) | scs_120kHz:
- AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n");
- if(index_4msb & 0x3){
- mac->type0_pdcch_ss_mux_pattern = 1;
- }else if(index_4msb & 0x0c){
- mac->type0_pdcch_ss_mux_pattern = 2;
- }
- num_rbs = table_38213_13_10_c2[index_4msb];
- num_symbols = table_38213_13_10_c3[index_4msb];
- if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
- rb_offset = table_38213_13_10_c4[index_4msb]-1;
- }else{
- rb_offset = table_38213_13_10_c4[index_4msb];
- }
+ uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13
+ frequency_range_t frequency_range = FR1;
+ uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero);
+ uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
+ int32_t num_rbs = -1;
+ int32_t num_symbols = -1;
+ int32_t rb_offset = -1;
+ //LOG_I(MAC,"<<<<<<<<<configSIB1 %d index_4msb %d index_4lsb %d scs_ssb %d scs_pdcch %d switch %d ",
+ //mac->mib->pdcch_ConfigSIB1,index_4msb,index_4lsb,scs_ssb,scs_pdcch, (scs_ssb << 5)|scs_pdcch);
+
+ // type0-pdcch coreset
+ switch( (scs_ssb << 5)|scs_pdcch ){
+ case (scs_15kHz << 5) | scs_15kHz :
+ AssertFatal(index_4msb < 15, "38.213 Table 13-1 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_1_c2[index_4msb];
+ num_symbols = table_38213_13_1_c3[index_4msb];
+ rb_offset = table_38213_13_1_c4[index_4msb];
+ break;
+
+ case (scs_15kHz << 5) | scs_30kHz:
+ AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_2_c2[index_4msb];
+ num_symbols = table_38213_13_2_c3[index_4msb];
+ rb_offset = table_38213_13_2_c4[index_4msb];
+ break;
+
+ case (scs_30kHz << 5) | scs_15kHz:
+ if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
+ AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_3_c2[index_4msb];
+ num_symbols = table_38213_13_3_c3[index_4msb];
+ rb_offset = table_38213_13_3_c4[index_4msb];
+ }else if(min_channel_bw & bw_40MHz){
+ AssertFatal(index_4msb < 9, "38.213 Table 13-5 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_5_c2[index_4msb];
+ num_symbols = table_38213_13_5_c3[index_4msb];
+ rb_offset = table_38213_13_5_c4[index_4msb];
+ }else{ ; }
+
+ break;
+
+ case (scs_30kHz << 5) | scs_30kHz:
+ if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)){
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_4_c2[index_4msb];
+ num_symbols = table_38213_13_4_c3[index_4msb];
+ rb_offset = table_38213_13_4_c4[index_4msb];
+ LOG_I(MAC,"<<<<<<<<<index_4msb %d num_rbs %d num_symb %d rb_offset %d\n",index_4msb,num_rbs,num_symbols,rb_offset );
+ }else if(min_channel_bw & bw_40MHz){
+ AssertFatal(index_4msb < 10, "38.213 Table 13-6 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_6_c2[index_4msb];
+ num_symbols = table_38213_13_6_c3[index_4msb];
+ rb_offset = table_38213_13_6_c4[index_4msb];
+ }else{ ; }
+ break;
+
+ case (scs_120kHz << 5) | scs_60kHz:
+ AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n");
+ if(index_4msb & 0x7){
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ }else if(index_4msb & 0x18){
+ mac->type0_pdcch_ss_mux_pattern = 2;
+ }else{ ; }
+
+ num_rbs = table_38213_13_7_c2[index_4msb];
+ num_symbols = table_38213_13_7_c3[index_4msb];
+ if(!is_condition_A && (index_4msb == 8 || index_4msb == 10)){
+ rb_offset = table_38213_13_7_c4[index_4msb] - 1;
+ }else{
+ rb_offset = table_38213_13_7_c4[index_4msb];
+ }
+ break;
+
+ case (scs_120kHz << 5) | scs_120kHz:
+ AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n");
+ if(index_4msb & 0x3){
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ }else if(index_4msb & 0x0c){
+ mac->type0_pdcch_ss_mux_pattern = 3;
+ }
+
+ num_rbs = table_38213_13_8_c2[index_4msb];
+ num_symbols = table_38213_13_8_c3[index_4msb];
+ if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
+ rb_offset = table_38213_13_8_c4[index_4msb] - 1;
+ }else{
+ rb_offset = table_38213_13_8_c4[index_4msb];
+ }
+ break;
+
+ case (scs_240kHz << 5) | scs_60kHz:
+ AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n");
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ num_rbs = table_38213_13_9_c2[index_4msb];
+ num_symbols = table_38213_13_9_c3[index_4msb];
+ rb_offset = table_38213_13_9_c4[index_4msb];
+ break;
+
+ case (scs_240kHz << 5) | scs_120kHz:
+ AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n");
+ if(index_4msb & 0x3){
+ mac->type0_pdcch_ss_mux_pattern = 1;
+ }else if(index_4msb & 0x0c){
+ mac->type0_pdcch_ss_mux_pattern = 2;
+ }
+ num_rbs = table_38213_13_10_c2[index_4msb];
+ num_symbols = table_38213_13_10_c3[index_4msb];
+ if(!is_condition_A && (index_4msb == 4 || index_4msb == 6)){
+ rb_offset = table_38213_13_10_c4[index_4msb]-1;
+ }else{
+ rb_offset = table_38213_13_10_c4[index_4msb];
+ }
- break;
+ break;
- default:
- break;
- }
+ default:
+ break;
+ }
- AssertFatal(num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined");
- AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
- AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
+ AssertFatal(num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined");
+ AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
+ AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
- //uint32_t cell_id = 0; // obtain from L1 later
-
- //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset;
- //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1;
- uint64_t mask = 0x0;
- uint8_t i;
- for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
- mask = mask >> 1;
- mask = mask | 0x100000000000;
- }
- //LOG_I(MAC,">>>>>>>>mask %x num_rbs %d rb_offset %d\n", mask, num_rbs, rb_offset);
- mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask;
- mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset; // additional parameter other than coreset
-
- //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols;
- mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED;
- mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2
- mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2
- mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id;
- mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
- mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id;
-
-
-
- // type0-pdcch search space
- float big_o;
- float big_m;
- uint32_t temp;
- SFN_C_TYPE sfn_c=SFN_C_IMPOSSIBLE; // only valid for mux=1
- uint32_t n_c=UINT_MAX;
- uint32_t number_of_search_space_per_slot=UINT_MAX;
- uint32_t first_symbol_index=UINT_MAX;
- uint32_t search_space_duration; // element of search space
- uint32_t coreset_duration; // element of coreset
+ //uint32_t cell_id = 0; // obtain from L1 later
+
+ //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset;
+ //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1;
+ uint64_t mask = 0x0;
+ uint8_t i;
+ for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
+ mask = mask >> 1;
+ mask = mask | 0x100000000000;
+ }
+ //LOG_I(MAC,">>>>>>>>mask %x num_rbs %d rb_offset %d\n", mask, num_rbs, rb_offset);
+ /*
+ mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask;
+ mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset; // additional parameter other than coreset
+
+ //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols;
+ mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED;
+ mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2
+ mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2
+ mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id;
+ mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
+ mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id;
+ */
+
+
+ // type0-pdcch search space
+ float big_o;
+ float big_m;
+ uint32_t temp;
+ SFN_C_TYPE sfn_c=SFN_C_IMPOSSIBLE; // only valid for mux=1
+ uint32_t n_c=UINT_MAX;
+ uint32_t number_of_search_space_per_slot=UINT_MAX;
+ uint32_t first_symbol_index=UINT_MAX;
+ uint32_t search_space_duration; // element of search space
+ uint32_t coreset_duration; // element of coreset
- // 38.213 table 10.1-1
-
- /// MUX PATTERN 1
- if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR1){
- big_o = table_38213_13_11_c1[index_4lsb];
- number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
- big_m = table_38213_13_11_c3[index_4lsb];
-
- temp = (uint32_t)(big_o*pow(2, scs_pdcch)) + (uint32_t)(ssb_index*big_m);
- n_c = temp / num_slot_per_frame;
- if((temp/num_slot_per_frame) & 0x1){
- sfn_c = SFN_C_MOD_2_EQ_1;
- }else{
- sfn_c = SFN_C_MOD_2_EQ_0;
- }
-
- if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (ssb_index&1)){
- first_symbol_index = num_symbols;
- }else{
- first_symbol_index = table_38213_13_11_c4[index_4lsb];
- }
- // 38.213 chapter 13: over two consecutive slots
- search_space_duration = 2;
- }
-
- if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){
- big_o = table_38213_13_12_c1[index_4lsb];
- number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
- big_m = table_38213_13_12_c3[index_4lsb];
-
- if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (ssb_index&1)){
- first_symbol_index = 7;
- }else if((index_4lsb == 6 || index_4lsb == 7 || index_4lsb == 8 || index_4lsb == 11) && (ssb_index&1)){
- first_symbol_index = num_symbols;
- }else{
- first_symbol_index = 0;
- }
- // 38.213 chapter 13: over two consecutive slots
- search_space_duration = 2;
- }
-
- /// MUX PATTERN 2
- if(mac->type0_pdcch_ss_mux_pattern == 2){
+ // 38.213 table 10.1-1
+
+ /// MUX PATTERN 1
+ if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR1){
+ big_o = table_38213_13_11_c1[index_4lsb];
+ number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
+ big_m = table_38213_13_11_c3[index_4lsb];
+
+ temp = (uint32_t)(big_o*pow(2, scs_pdcch)) + (uint32_t)(ssb_index*big_m);
+ n_c = temp / num_slot_per_frame;
+ if((temp/num_slot_per_frame) & 0x1){
+ sfn_c = SFN_C_MOD_2_EQ_1;
+ }else{
+ sfn_c = SFN_C_MOD_2_EQ_0;
+ }
+
+ if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (ssb_index&1)){
+ first_symbol_index = num_symbols;
+ }else{
+ first_symbol_index = table_38213_13_11_c4[index_4lsb];
+ }
+ // 38.213 chapter 13: over two consecutive slots
+ search_space_duration = 2;
+ }
+
+ if(mac->type0_pdcch_ss_mux_pattern == 1 && frequency_range == FR2){
+ big_o = table_38213_13_12_c1[index_4lsb];
+ number_of_search_space_per_slot = table_38213_13_11_c2[index_4lsb];
+ big_m = table_38213_13_12_c3[index_4lsb];
+
+ if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (ssb_index&1)){
+ first_symbol_index = 7;
+ }else if((index_4lsb == 6 || index_4lsb == 7 || index_4lsb == 8 || index_4lsb == 11) && (ssb_index&1)){
+ first_symbol_index = num_symbols;
+ }else{
+ first_symbol_index = 0;
+ }
+ // 38.213 chapter 13: over two consecutive slots
+ search_space_duration = 2;
+ }
+
+ /// MUX PATTERN 2
+ if(mac->type0_pdcch_ss_mux_pattern == 2){
- if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_60kHz)){
- // 38.213 Table 13-13
- AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n");
- // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
-// sfn_c = SFN_C_EQ_SFN_SSB;
- n_c = get_ssb_slot(ssb_index);
- switch(ssb_index & 0x3){ // ssb_index(i) mod 4
- case 0:
- first_symbol_index = 0;
- break;
- case 1:
- first_symbol_index = 1;
- break;
- case 2:
- first_symbol_index = 6;
- break;
- case 3:
- first_symbol_index = 7;
- break;
- default: break;
- }
+ if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_60kHz)){
+ // 38.213 Table 13-13
+ AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n");
+ // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
+ // sfn_c = SFN_C_EQ_SFN_SSB;
+ n_c = get_ssb_slot(ssb_index);
+ switch(ssb_index & 0x3){ // ssb_index(i) mod 4
+ case 0:
+ first_symbol_index = 0;
+ break;
+ case 1:
+ first_symbol_index = 1;
+ break;
+ case 2:
+ first_symbol_index = 6;
+ break;
+ case 3:
+ first_symbol_index = 7;
+ break;
+ default: break;
+ }
- }else if((scs_ssb == scs_240kHz) && (scs_pdcch == scs_120kHz)){
- // 38.213 Table 13-14
- AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
- // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
-// sfn_c = SFN_C_EQ_SFN_SSB;
- n_c = get_ssb_slot(ssb_index);
- switch(ssb_index & 0x7){ // ssb_index(i) mod 8
- case 0:
- first_symbol_index = 0;
- break;
- case 1:
- first_symbol_index = 1;
- break;
- case 2:
- first_symbol_index = 2;
- break;
- case 3:
- first_symbol_index = 3;
- break;
- case 4:
- first_symbol_index = 12;
- n_c = get_ssb_slot(ssb_index) - 1;
- break;
- case 5:
- first_symbol_index = 13;
- n_c = get_ssb_slot(ssb_index) - 1;
- break;
- case 6:
- first_symbol_index = 0;
- break;
- case 7:
- first_symbol_index = 1;
- break;
- default: break;
- }
- }else{ ; }
- // 38.213 chapter 13: over one slot
- search_space_duration = 1;
- }
-
- /// MUX PATTERN 3
- if(mac->type0_pdcch_ss_mux_pattern == 3){
- if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_120kHz)){
- // 38.213 Table 13-15
- AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n");
- // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
-// sfn_c = SFN_C_EQ_SFN_SSB;
- n_c = get_ssb_slot(ssb_index);
- switch(ssb_index & 0x3){ // ssb_index(i) mod 4
- case 0:
- first_symbol_index = 4;
- break;
- case 1:
- first_symbol_index = 8;
- break;
- case 2:
- first_symbol_index = 2;
- break;
- case 3:
- first_symbol_index = 6;
- break;
- default: break;
- }
- }else{ ; }
- // 38.213 chapter 13: over one slot
- search_space_duration = 1;
- }
-
- AssertFatal(number_of_search_space_per_slot!=UINT_MAX,"");
- coreset_duration = num_symbols * number_of_search_space_per_slot;
-
- mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0];
- mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1];
- mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
- mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
- mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
- mac->type0_pdcch_dci_config.duration = search_space_duration;
- mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset
- AssertFatal(first_symbol_index!=UINT_MAX,"");
- mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
-
- AssertFatal(sfn_c!=SFN_C_IMPOSSIBLE,"");
- AssertFatal(n_c!=UINT_MAX,"");
- mac->type0_pdcch_ss_sfn_c = sfn_c;
- mac->type0_pdcch_ss_n_c = n_c;
+ }else if((scs_ssb == scs_240kHz) && (scs_pdcch == scs_120kHz)){
+ // 38.213 Table 13-14
+ AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
+ // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
+ // sfn_c = SFN_C_EQ_SFN_SSB;
+ n_c = get_ssb_slot(ssb_index);
+ switch(ssb_index & 0x7){ // ssb_index(i) mod 8
+ case 0:
+ first_symbol_index = 0;
+ break;
+ case 1:
+ first_symbol_index = 1;
+ break;
+ case 2:
+ first_symbol_index = 2;
+ break;
+ case 3:
+ first_symbol_index = 3;
+ break;
+ case 4:
+ first_symbol_index = 12;
+ n_c = get_ssb_slot(ssb_index) - 1;
+ break;
+ case 5:
+ first_symbol_index = 13;
+ n_c = get_ssb_slot(ssb_index) - 1;
+ break;
+ case 6:
+ first_symbol_index = 0;
+ break;
+ case 7:
+ first_symbol_index = 1;
+ break;
+ default: break;
+ }
+ }else{ ; }
+ // 38.213 chapter 13: over one slot
+ search_space_duration = 1;
+ }
+
+ /// MUX PATTERN 3
+ if(mac->type0_pdcch_ss_mux_pattern == 3){
+ if((scs_ssb == scs_120kHz) && (scs_pdcch == scs_120kHz)){
+ // 38.213 Table 13-15
+ AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n");
+ // PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
+ // sfn_c = SFN_C_EQ_SFN_SSB;
+ n_c = get_ssb_slot(ssb_index);
+ switch(ssb_index & 0x3){ // ssb_index(i) mod 4
+ case 0:
+ first_symbol_index = 4;
+ break;
+ case 1:
+ first_symbol_index = 8;
+ break;
+ case 2:
+ first_symbol_index = 2;
+ break;
+ case 3:
+ first_symbol_index = 6;
+ break;
+ default: break;
+ }
+ }else{ ; }
+ // 38.213 chapter 13: over one slot
+ search_space_duration = 1;
+ }
+
+ AssertFatal(number_of_search_space_per_slot!=UINT_MAX,"");
+ coreset_duration = num_symbols * number_of_search_space_per_slot;
+ /*
+ mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0];
+ mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1];
+ mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
+ mac->type0_pdcch_dci_config.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
+ mac->type0_pdcch_dci_config.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
+ mac->type0_pdcch_dci_config.duration = search_space_duration;
+ mac->type0_pdcch_dci_config.coreset.duration = coreset_duration; // coreset
+ AssertFatal(first_symbol_index!=UINT_MAX,"");
+ mac->type0_pdcch_dci_config.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
+ */
+ AssertFatal(sfn_c!=SFN_C_IMPOSSIBLE,"");
+ AssertFatal(n_c!=UINT_MAX,"");
+ mac->type0_pdcch_ss_sfn_c = sfn_c;
+ mac->type0_pdcch_ss_n_c = n_c;
- // fill in the elements in config request inside P5 message
- mac->phy_config.Mod_id = module_id;
- mac->phy_config.CC_id = cc_id;
-
- mac->phy_config.config_req.pbch_config.system_frame_number = frame; // after calculation
- mac->phy_config.config_req.pbch_config.subcarrier_spacing_common = mac->mib->subCarrierSpacingCommon;
- mac->phy_config.config_req.pbch_config.ssb_subcarrier_offset = ssb_subcarrier_offset; // after calculation
- mac->phy_config.config_req.pbch_config.dmrs_type_a_position = mac->mib->dmrs_TypeA_Position;
- mac->phy_config.config_req.pbch_config.pdcch_config_sib1 = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero) * 16 + (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
- mac->phy_config.config_req.pbch_config.cell_barred = mac->mib->cellBarred;
- mac->phy_config.config_req.pbch_config.intra_frequency_reselection = mac->mib->intraFreqReselection;
- mac->phy_config.config_req.pbch_config.half_frame_bit = half_frame_bit;
- mac->phy_config.config_req.pbch_config.ssb_index = ssb_index;
- mac->phy_config.config_req.config_mask |= FAPI_NR_CONFIG_REQUEST_MASK_PBCH;
-
- if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL){
- mac->if_module->phy_config_request(&mac->phy_config);
- }
- proc->decoded_frame_rx=frame;
- //}
- return 0;
+ // fill in the elements in config request inside P5 message
+ mac->phy_config.Mod_id = module_id;
+ mac->phy_config.CC_id = cc_id;
+
+ mac->phy_config.config_req.pbch_config.system_frame_number = frame; // after calculation
+ mac->phy_config.config_req.pbch_config.subcarrier_spacing_common = mac->mib->subCarrierSpacingCommon;
+ mac->phy_config.config_req.pbch_config.ssb_subcarrier_offset = ssb_subcarrier_offset; // after calculation
+ mac->phy_config.config_req.pbch_config.dmrs_type_a_position = mac->mib->dmrs_TypeA_Position;
+ mac->phy_config.config_req.pbch_config.pdcch_config_sib1 = (mac->mib->pdcch_ConfigSIB1.controlResourceSetZero) * 16 + (mac->mib->pdcch_ConfigSIB1.searchSpaceZero);
+ mac->phy_config.config_req.pbch_config.cell_barred = mac->mib->cellBarred;
+ mac->phy_config.config_req.pbch_config.intra_frequency_reselection = mac->mib->intraFreqReselection;
+ mac->phy_config.config_req.pbch_config.half_frame_bit = half_frame_bit;
+ mac->phy_config.config_req.pbch_config.ssb_index = ssb_index;
+ mac->phy_config.config_req.config_mask |= FAPI_NR_CONFIG_REQUEST_MASK_PBCH;
+
+ if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL){
+ mac->if_module->phy_config_request(&mac->phy_config);
+ }
+ proc->decoded_frame_rx=frame;
+ //}
+ return 0;
}
// TODO: change to UE parameter, scs: 15KHz, slot duration: 1ms
uint32_t get_ssb_frame(uint32_t test){
- return test;
+ return test;
}
// Performs :
@@ -635,86 +640,668 @@ uint32_t get_ssb_frame(uint32_t test){
// 2. TODO: Perform SR/BSR procedures for scheduling feedback
// 3. TODO: Perform PHR procedures
NR_UE_L2_STATE_t nr_ue_scheduler(
- const module_id_t module_id,
- const uint8_t gNB_index,
- const int cc_id,
- const frame_t rx_frame,
- const slot_t rx_slot,
- const int32_t ssb_index,
- const frame_t tx_frame,
- const slot_t tx_slot ){
-
- uint32_t search_space_mask = 0;
- NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ const module_id_t module_id,
+ const uint8_t gNB_index,
+ const int cc_id,
+ const frame_t rx_frame,
+ const slot_t rx_slot,
+ const int32_t ssb_index,
+ const frame_t tx_frame,
+ const slot_t tx_slot ){
+
+ uint32_t search_space_mask = 0;
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+
+ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
- // check type0 from 38.213 13
- if(ssb_index != -1){
-
- if(mac->type0_pdcch_ss_mux_pattern == 1){
- // 38.213 chapter 13
- if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
- }
- if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
- }
- }
- if(mac->type0_pdcch_ss_mux_pattern == 2){
- // 38.213 Table 13-13, 13-14
- if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
- }
- }
- if(mac->type0_pdcch_ss_mux_pattern == 3){
- // 38.213 Table 13-15
- if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
- }
- }
- }
-
- fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
- // Type0 PDCCH search space
+ // check type0 from 38.213 13 if we have no CellGroupConfig
+ if ( mac->scd == NULL) {
+ if( ssb_index != -1){
+
+ if(mac->type0_pdcch_ss_mux_pattern == 1){
+ // 38.213 chapter 13
+ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ if(mac->type0_pdcch_ss_mux_pattern == 2){
+ // 38.213 Table 13-13, 13-14
+ if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ if(mac->type0_pdcch_ss_mux_pattern == 3){
+ // 38.213 Table 13-15
+ if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ } // ssb_index != -1
+
+ // Type0 PDCCH search space
if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
-
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
+
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
- /*
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set
-
+ /*
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set
+
LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n",
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti,
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP);
- */
- dl_config->number_pdus = dl_config->number_pdus + 1;
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti,
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP);
+ */
+ dl_config->number_pdus = dl_config->number_pdus + 1;
}
+ }
+ else { // get PDCCH configuration(s) from SCGConfig
+
- if(search_space_mask & type0a_pdcch){
- }
+
+
+ // get Coreset and SearchSpace Information from spCellConfigDedicated
+
+
+
+ /*
+ if(search_space_mask & type0a_pdcch){
+ }
+
+ if(search_space_mask & type1_pdcch){
+ }
+
+ if(search_space_mask & type2_pdcch){
+ }
+
+ if(search_space_mask & type3_pdcch){
+ }
+ */
+ }
+
+
+ mac->scheduled_response.dl_config = dl_config;
+
+
+ return UE_CONNECTION_OK;
+}
+
+#if 0
+uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue,
+ uint8_t slot,
+ int p,
+ crc_scrambled_t crc_scrambled,
+ uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
+ uint8_t format) {
+ LOG_DDD("crc_scrambled=%d, n_RB_ULBWP=%d, n_RB_DLBWP=%d\n",crc_scrambled,n_RB_ULBWP,n_RB_DLBWP);
+ /*
+ * function nr_dci_format_size calculates and returns the size in bits of a determined format
+ * it also returns an bi-dimensional array 'dci_fields_sizes' with x rows and y columns, where:
+ * x is the number of fields defined in TS 38.212 subclause 7.3.1 (Each field is mapped in the order in which it appears in the description in the specification)
+ * y is the number of formats
+ * e.g.: dci_fields_sizes[10][0] contains the size in bits of the field FREQ_DOM_RESOURCE_ASSIGNMENT_UL for format 0_0
+ */
+ // pdsch_config contains the PDSCH-Config IE is used to configure the UE specific PDSCH parameters (TS 38.331)
+ PDSCH_Config_t pdsch_config = ue->PDSCH_Config;
+ // pusch_config contains the PUSCH-Config IE is used to configure the UE specific PUSCH parameters (TS 38.331)
+ PUSCH_Config_t pusch_config = ue->pusch_config;
+ PUCCH_Config_t pucch_config_dedicated = ue->pucch_config_dedicated_nr[eNB_id];
+ crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig = ue->crossCarrierSchedulingConfig;
+ dmrs_UplinkConfig_t dmrs_UplinkConfig = ue->dmrs_UplinkConfig;
+ dmrs_DownlinkConfig_t dmrs_DownlinkConfig = ue->dmrs_DownlinkConfig;
+ csi_MeasConfig_t csi_MeasConfig = ue->csi_MeasConfig;
+ PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig= ue->PUSCH_ServingCellConfig;
+ PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig= ue->PDSCH_ServingCellConfig;
+ NR_UE_PDCCH *pdcch_vars2 = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id];
+ // 1 CARRIER_IN
+ // crossCarrierSchedulingConfig from higher layers, variable crossCarrierSchedulingConfig indicates if 'cross carrier scheduling' is enabled or not:
+ // if No cross carrier scheduling: number of bits for CARRIER_IND is 0
+ // if Cross carrier scheduling: number of bits for CARRIER_IND is 3
+ // The IE CrossCarrierSchedulingConfig is used to specify the configuration when the cross-carrier scheduling is used in a cell
+ uint8_t crossCarrierSchedulingConfig_ind = 0;
+
+ if (crossCarrierSchedulingConfig.schedulingCellInfo.other.cif_InSchedulingCell !=0 ) crossCarrierSchedulingConfig_ind=1;
+
+ // 2 SUL_IND_0_1, // 40 SRS_REQUEST, // 50 SUL_IND_0_0
+ // UL/SUL indicator (TS 38.331, supplementary uplink is indicated in higher layer parameter ServCellAdd-SUL from IE ServingCellConfig and ServingCellConfigCommon):
+ // 0 bit for UEs not configured with SUL in the cell or UEs configured with SUL in the cell but only PUCCH carrier in the cell is configured for PUSCH transmission
+ // 1 bit for UEs configured with SUL in the cell as defined in Table 7.3.1.1.1-1
+ // sul_ind indicates whether SUL is configured in cell or not
+ uint8_t sul_ind=ue->supplementaryUplink.supplementaryUplink; // this value will be 0 or 1 depending on higher layer parameter ServCellAdd-SUL. FIXME!!!
+ // 7 BANDWIDTH_PART_IND
+ // number of UL BWPs configured by higher layers
+ uint8_t n_UL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!!
+ n_UL_BWP_RRC = ((n_UL_BWP_RRC > 3)?n_UL_BWP_RRC:(n_UL_BWP_RRC+1));
+ // number of DL BWPs configured by higher layers
+ uint8_t n_DL_BWP_RRC=1; // initialized to 1 but it has to be initialized by higher layers FIXME!!!
+ n_DL_BWP_RRC = ((n_DL_BWP_RRC > 3)?n_DL_BWP_RRC:(n_DL_BWP_RRC+1));
+ // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL
+ // if format0_0, only resource allocation type 1 is allowed
+ // if format0_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 6.1.2.2.1
+ // for PUSCH hopping with resource allocation type 1
+ // n_UL_hopping = 1 if the higher layer parameter frequencyHoppingOffsetLists contains two offset values
+ // n_UL_hopping = 2 if the higher layer parameter frequencyHoppingOffsetLists contains four offset values
+ uint8_t n_UL_hopping=pusch_config.n_frequencyHoppingOffsetLists;
+
+ if (n_UL_hopping == 2) {
+ n_UL_hopping = 1;
+ } else if (n_UL_hopping == 4) {
+ n_UL_hopping = 2;
+ } else {
+ n_UL_hopping = 0;
+ }
+
+ ul_resourceAllocation_t ul_resource_allocation_type = pusch_config.ul_resourceAllocation;
+ uint8_t ul_res_alloc_type_0 = 0;
+ uint8_t ul_res_alloc_type_1 = 0;
+
+ if (ul_resource_allocation_type == ul_resourceAllocationType0) ul_res_alloc_type_0 = 1;
+
+ if (ul_resource_allocation_type == ul_resourceAllocationType1) ul_res_alloc_type_1 = 1;
+
+ if (ul_resource_allocation_type == ul_dynamicSwitch) {
+ ul_res_alloc_type_0 = 1;
+ ul_res_alloc_type_1 = 1;
+ }
+
+ uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp;
+
+ if (ul_res_alloc_type_0 == 1) { // implementation of Table 6.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1
+ // config1: PUSCH-Config IE contains rbg-Size ENUMERATED {config1 config2}
+ ul_rgb_Size_t config = pusch_config.ul_rgbSize;
+ uint8_t nominal_RBG_P = (config==ul_rgb_config1?2:4);
+
+ if (n_RB_ULBWP > 36) nominal_RBG_P = (config==ul_rgb_config1?4:8);
+
+ if (n_RB_ULBWP > 72) nominal_RBG_P = (config==ul_rgb_config1?8:16);
+
+ if (n_RB_ULBWP > 144) nominal_RBG_P = 16;
+
+ n_bits_freq_dom_res_assign_ul = (uint8_t)ceil((n_RB_ULBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0???
+ n_ul_RGB_tmp = n_bits_freq_dom_res_assign_ul;
+ }
+
+ if (ul_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_ul = (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping;
+
+ if ((ul_res_alloc_type_0 == 1) && (ul_res_alloc_type_1 == 1))
+ n_bits_freq_dom_res_assign_ul = ((n_bits_freq_dom_res_assign_ul>n_ul_RGB_tmp)?(n_bits_freq_dom_res_assign_ul+1):(n_ul_RGB_tmp+1));
+
+ // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL
+ // if format1_0, only resource allocation type 1 is allowed
+ // if format1_1, then resource allocation type 0 can be configured and N_RBG is defined in TS 38.214 subclause 5.1.2.2.1
+ dl_resourceAllocation_t dl_resource_allocation_type = pdsch_config.dl_resourceAllocation;
+ uint8_t dl_res_alloc_type_0 = 0;
+ uint8_t dl_res_alloc_type_1 = 0;
+
+ if (dl_resource_allocation_type == dl_resourceAllocationType0) dl_res_alloc_type_0 = 1;
+
+ if (dl_resource_allocation_type == dl_resourceAllocationType1) dl_res_alloc_type_1 = 1;
+
+ if (dl_resource_allocation_type == dl_dynamicSwitch) {
+ dl_res_alloc_type_0 = 1;
+ dl_res_alloc_type_1 = 1;
+ }
+
+ uint8_t n_bits_freq_dom_res_assign_dl=0,n_dl_RGB_tmp;
+
+ if (dl_res_alloc_type_0 == 1) { // implementation of Table 5.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1
+ // config1: PDSCH-Config IE contains rbg-Size ENUMERATED {config1, config2}
+ dl_rgb_Size_t config = pdsch_config.dl_rgbSize;
+ uint8_t nominal_RBG_P = (config==dl_rgb_config1?2:4);
+
+ if (n_RB_DLBWP > 36) nominal_RBG_P = (config==dl_rgb_config1?4:8);
+
+ if (n_RB_DLBWP > 72) nominal_RBG_P = (config==dl_rgb_config1?8:16);
+
+ if (n_RB_DLBWP > 144) nominal_RBG_P = 16;
- if(search_space_mask & type1_pdcch){
+ n_bits_freq_dom_res_assign_dl = (uint8_t)ceil((n_RB_DLBWP+(0%nominal_RBG_P))/nominal_RBG_P); //FIXME!!! what is 0???
+ n_dl_RGB_tmp = n_bits_freq_dom_res_assign_dl;
+ }
+
+ if (dl_res_alloc_type_1 == 1) n_bits_freq_dom_res_assign_dl = (uint8_t)(ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)));
+
+ if ((dl_res_alloc_type_0 == 1) && (dl_res_alloc_type_1 == 1))
+ n_bits_freq_dom_res_assign_dl = ((n_bits_freq_dom_res_assign_dl>n_dl_RGB_tmp)?(n_bits_freq_dom_res_assign_dl+1):(n_dl_RGB_tmp+1));
+
+ // 12 TIME_DOM_RESOURCE_ASSIGNMENT
+ uint8_t pusch_alloc_list = pusch_config.n_push_alloc_list;
+ uint8_t pdsch_alloc_list = pdsch_config.n_pdsh_alloc_list;
+ // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
+ static_bundleSize_t static_prb_BundlingType = pdsch_config.prbBundleType.staticBundling;
+ bundleSizeSet1_t dynamic_prb_BundlingType1 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet1;
+ bundleSizeSet2_t dynamic_prb_BundlingType2 = pdsch_config.prbBundleType.dynamicBundlig.bundleSizeSet2;
+ uint8_t prb_BundlingType_size=0;
+
+ if ((static_prb_BundlingType==st_n4)||(static_prb_BundlingType==st_wideband)) prb_BundlingType_size=0;
+
+ if ((dynamic_prb_BundlingType1==dy_1_n4)||(dynamic_prb_BundlingType1==dy_1_wideband)||(dynamic_prb_BundlingType1==dy_1_n2_wideband)||(dynamic_prb_BundlingType1==dy_1_n4_wideband)||
+ (dynamic_prb_BundlingType2==dy_2_n4)||(dynamic_prb_BundlingType2==dy_2_wideband)) prb_BundlingType_size=1;
+
+ // 15 RATE_MATCHING_IND FIXME!!!
+ // according to TS 38.212: Rate matching indicator – 0, 1, or 2 bits according to higher layer parameter rateMatchPattern
+ uint8_t rateMatching_bits = pdsch_config.n_rateMatchPatterns;
+ // 16 ZP_CSI_RS_TRIGGER FIXME!!!
+ // 0, 1, or 2 bits as defined in Subclause 5.1.4.2 of [6, TS 38.214].
+ // is the number of ZP CSI-RS resource sets in the higher layer parameter zp-CSI-RS-Resource
+ uint8_t n_zp_bits = pdsch_config.n_zp_CSI_RS_ResourceId;
+ // 17 FREQ_HOPPING_FLAG
+ // freqHopping is defined by higher layer parameter frequencyHopping from IE PUSCH-Config. Values are ENUMERATED{mode1, mode2}
+ frequencyHopping_t f_hopping = pusch_config.frequencyHopping;
+ uint8_t freqHopping = 0;
+
+ if ((f_hopping==f_hop_mode1)||(f_hopping==f_hop_mode2)) freqHopping = 1;
+
+ // 28 DAI
+ pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook = pdsch_config.pdsch_HARQ_ACK_Codebook;
+ uint8_t n_dai = 0;
+ uint8_t n_serving_cell_dl = 1; // this is hardcoded to 1 as we need to get this value from RRC higher layers parameters. FIXME!!!
+
+ if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl == 1)) n_dai = 2;
+
+ if ((pdsch_HARQ_ACK_Codebook == dynamic) && (n_serving_cell_dl > 1)) n_dai = 4;
+
+ // 29 FIRST_DAI
+ uint8_t codebook_HARQ_ACK = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI.
+
+ if (pdsch_HARQ_ACK_Codebook == semiStatic) codebook_HARQ_ACK = 1;
+
+ if (pdsch_HARQ_ACK_Codebook == dynamic) codebook_HARQ_ACK = 2;
+
+ // 30 SECOND_DAI
+ uint8_t n_HARQ_ACK_sub_codebooks = 0; // We need to get this value to calculate number of bits of fields 1st DAI and 2nd DAI. FIXME!!!
+ // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND
+ uint8_t pdsch_harq_t_ind = (uint8_t)ceil(log2(pucch_config_dedicated.dl_DataToUL_ACK[0]));
+ // 36 SRS_RESOURCE_IND
+ // n_SRS is the number of configured SRS resources in the SRS resource set associated with the higher layer parameter usage of value 'codeBook' or 'nonCodeBook'
+ // from SRS_ResourceSet_t type we should get the information of the usage parameter (with possible values beamManagement, codebook, nonCodebook, antennaSwitching)
+ // at frame_parms->srs_nr->p_SRS_ResourceSetList[]->usage
+ uint8_t n_SRS = ue->srs.number_srs_Resource_Set;
+ // 37 PRECOD_NBR_LAYERS
+ // 38 ANTENNA_PORTS
+ txConfig_t txConfig = pusch_config.txConfig;
+ transformPrecoder_t transformPrecoder = pusch_config.transformPrecoder;
+ codebookSubset_t codebookSubset = pusch_config.codebookSubset;
+ uint8_t maxRank = pusch_config.maxRank;
+ uint8_t num_antenna_ports = 1; // this is hardcoded. We need to get the real value FIXME!!!
+ uint8_t precond_nbr_layers_bits = 0;
+ uint8_t antenna_ports_bits_ul = 0;
+
+ // searching number of bits at tables 7.3.1.1.2-2/3/4/5 from TS 38.212 subclause 7.3.1.1.2
+ if (txConfig == txConfig_codebook) {
+ if (num_antenna_ports == 4) {
+ if ((transformPrecoder == transformPrecoder_disabled) && ((maxRank == 2)||(maxRank == 3)||(maxRank == 4))) { // Table 7.3.1.1.2-2
+ if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=6;
+
+ if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=5;
+
+ if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=4;
+ }
+
+ if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-3
+ if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=5;
+
+ if (codebookSubset == codebookSubset_partialAndNonCoherent) precond_nbr_layers_bits=4;
+
+ if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2;
+ }
}
- if(search_space_mask & type2_pdcch){
+ if (num_antenna_ports == 2) {
+ if ((transformPrecoder == transformPrecoder_disabled) && (maxRank == 2)) { // Table 7.3.1.1.2-4
+ if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=4;
+
+ if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=2;
+ }
+
+ if (((transformPrecoder == transformPrecoder_enabled)||(transformPrecoder == transformPrecoder_disabled)) && (maxRank == 1)) { // Table 7.3.1.1.2-5
+ if (codebookSubset == codebookSubset_fullyAndPartialAndNonCoherent) precond_nbr_layers_bits=3;
+
+ if (codebookSubset == codebookSubset_nonCoherent) precond_nbr_layers_bits=1;
+ }
}
+ }
+
+ if (txConfig == txConfig_nonCodebook) {
+ }
+
+ // searching number of bits at tables 7.3.1.1.2-6/7/8/9/10/11/12/13/14/15/16/17/18/19
+ if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)) {
+ if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 2;
+
+ if ((transformPrecoder == transformPrecoder_enabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4;
+
+ if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 3;
+
+ if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 4;
+ }
- if(search_space_mask & type3_pdcch){
+ if((dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type2)) {
+ if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len1)) antenna_ports_bits_ul = 4;
+
+ if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.pusch_maxLength == pusch_len2)) antenna_ports_bits_ul = 5;
+ }
+
+ // for format 1_1 number of bits as defined by Tables 7.3.1.2.2-1/2/3/4
+ uint8_t antenna_ports_bits_dl = 0;
+
+ if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 4; // Table 7.3.1.2.2-1
+
+ if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type1) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-2
+
+ if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len1)) antenna_ports_bits_dl = 5; // Table 7.3.1.2.2-3
+
+ if((dmrs_DownlinkConfig.pdsch_dmrs_type == pdsch_dmrs_type2) && (dmrs_DownlinkConfig.pdsch_maxLength == pdsch_len2)) antenna_ports_bits_dl = 6; // Table 7.3.1.2.2-4
+
+ // 39 TCI
+ uint8_t tci_bits=0;
+
+ if (pdcch_vars2->coreset[p].tciPresentInDCI == tciPresentInDCI_enabled) tci_bits=3;
+
+ // 42 CSI_REQUEST
+ // reportTriggerSize is defined in the CSI-MeasConfig IE (TS 38.331).
+ // Size of CSI request field in DCI (bits). Corresponds to L1 parameter 'ReportTriggerSize' (see 38.214, section 5.2)
+ uint8_t reportTriggerSize = csi_MeasConfig.reportTriggerSize; // value from 0..6
+ // 43 CBGTI
+ // for format 0_1
+ uint8_t maxCodeBlockGroupsPerTransportBlock = 0;
+
+ if (PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock != 0)
+ maxCodeBlockGroupsPerTransportBlock = (uint8_t)PUSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock;
+
+ // for format 1_1, as defined in Subclause 5.1.7 of [6, TS38.214]
+ uint8_t maxCodeBlockGroupsPerTransportBlock_dl = 0;
+
+ if (PDSCH_ServingCellConfig.maxCodeBlockGroupsPerTransportBlock_dl != 0)
+ maxCodeBlockGroupsPerTransportBlock_dl = pdsch_config.maxNrofCodeWordsScheduledByDCI; // FIXME!!!
+
+ // 44 CBGFI
+ uint8_t cbgfi_bit = PDSCH_ServingCellConfig.codeBlockGroupFlushIndicator;
+ // 45 PTRS_DMRS
+ // 0 bit if PTRS-UplinkConfig is not configured and transformPrecoder=disabled, or if transformPrecoder=enabled, or if maxRank=1
+ // 2 bits otherwise
+ uint8_t ptrs_dmrs_bits=0; //FIXME!!!
+ // 46 BETA_OFFSET_IND
+ // at IE PUSCH-Config, beta_offset indicator – 0 if the higher layer parameter betaOffsets = semiStatic; otherwise 2 bits
+ // uci-OnPUSCH
+ // Selection between and configuration of dynamic and semi-static beta-offset. If the field is absent or released, the UE applies the value 'semiStatic' and the BetaOffsets
+ uint8_t betaOffsets = 0;
+
+ if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_semiStatic);
+
+ if (pusch_config.uci_onPusch.betaOffset_type == betaOffset_dynamic) betaOffsets = 2;
+
+ // 47 DMRS_SEQ_INI
+ uint8_t dmrs_seq_ini_bits_ul = 0;
+ uint8_t dmrs_seq_ini_bits_dl = 0;
+
+ //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-UplinkConfig
+ if ((transformPrecoder == transformPrecoder_disabled) && (dmrs_UplinkConfig.scramblingID0 != 0) && (dmrs_UplinkConfig.scramblingID1 != 0)) dmrs_seq_ini_bits_ul = 1;
+
+ //1 bit if both scramblingID0 and scramblingID1 are configured in DMRS-DownlinkConfig
+ if ((dmrs_DownlinkConfig.scramblingID0 != 0) && (dmrs_DownlinkConfig.scramblingID0 != 0)) dmrs_seq_ini_bits_dl = 1;
+
+ /*
+ * For format 2_2
+ *
+ * This format supports power control commands for semi-persistent scheduling.
+ * As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH)
+ *
+ * This format will be implemented in the future FIXME!!!
+ *
+ */
+ // 5 BLOCK_NUMBER: The parameter tpc-PUSCH or tpc-PUCCH provided by higher layers determines the index to the block number for an UL of a cell
+ // The following fields are defined for each block: Closed loop indicator and TPC command
+ // 6 CLOSE_LOOP_IND
+ // 41 TPC_CMD
+ uint8_t tpc_cmd_bit_2_2 = 2;
+ /*
+ * For format 2_3
+ *
+ * This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control
+ * either because independent control is desirable or because the device is configured without PUCCH and PUSCH
+ *
+ * This format will be implemented in the future FIXME!!!
+ *
+ */
+ // 40 SRS_REQUEST
+ // 41 TPC_CMD
+ uint8_t tpc_cmd_bit_2_3 = 0;
+ uint8_t dci_field_size_table [NBR_NR_DCI_FIELDS][NBR_NR_FORMATS] = { // This table contains the number of bits for each field (row) contained in each dci format (column).
+ // The values of the variables indicate field sizes in number of bits
+ //Format0_0 Format0_1 Format1_0 Format1_1 Formats2_0/1/2/3
+ {
+ 1, 1, (((crc_scrambled == _p_rnti) || (crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti)) ? 0:1),
+ 1, 0,0,0,0
+ }, // 0 IDENTIFIER_DCI_FORMATS:
+ {
+ 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3),
+ 0, ((crossCarrierSchedulingConfig_ind == 0) ? 0:3),
+ 0,0,0,0
+ }, // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
+ {0, (sul_ind == 0)?0:1, 0, 0, 0,0,0,0}, // 2 SUL_IND_0_1:
+ {0, 0, 0, 0, 1,0,0,0}, // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
+ {0, 0, 0, 0, 0,1,0,0}, // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
+ {0, 0, 0, 0, 0,0,0,0}, // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
+ {0, 0, 0, 0, 0,0,1,0}, // 6 CLOSE_LOOP_IND
+ {
+ 0, (uint8_t)ceil(log2(n_UL_BWP_RRC)),
+ 0, (uint8_t)ceil(log2(n_DL_BWP_RRC)),
+ 0,0,0,0
+ }, // 7 BANDWIDTH_PART_IND:
+ {
+ 0, 0, ((crc_scrambled == _p_rnti) ? 2:0),
+ 0, 0,0,0,0
+ }, // 8 SHORT_MESSAGE_IND 2 bits if crc scrambled with P-RNTI
+ {
+ 0, 0, ((crc_scrambled == _p_rnti) ? 8:0),
+ 0, 0,0,0,0
+ }, // 9 SHORT_MESSAGES 8 bit8 if crc scrambled with P-RNTI
+ {
+ (uint8_t)(ceil(log2(n_RB_ULBWP*(n_RB_ULBWP+1)/2)))-n_UL_hopping,
+ n_bits_freq_dom_res_assign_ul,
+ 0, 0, 0,0,0,0
+ }, // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
+ // (NOTE 1) If DCI format 0_0 is monitored in common search space
+ // and if the number of information bits in the DCI format 0_0 prior to padding
+ // is larger than the payload size of the DCI format 1_0 monitored in common search space
+ // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
+ // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
+ {
+ 0, 0, (uint8_t)ceil(log2(n_RB_DLBWP*(n_RB_DLBWP+1)/2)),
+ n_bits_freq_dom_res_assign_dl,
+ 0,0,0,0
+ }, // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ {
+ 4, (uint8_t)log2(pusch_alloc_list),
+ 4, (uint8_t)log2(pdsch_alloc_list),
+ 0,0,0,0
+ }, // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ // where I the number of entries in the higher layer parameter pusch-AllocationList
+ {
+ 0, 0, 1, (((dl_res_alloc_type_0==1) &&(dl_res_alloc_type_1==0))?0:1),
+ 0,0,0,0
+ }, // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ {0, 0, 0, prb_BundlingType_size, 0,0,0,0}, // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
+ {0, 0, 0, rateMatching_bits, 0,0,0,0}, // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
+ {0, 0, 0, n_zp_bits, 0,0,0,0}, // 16 ZP_CSI_RS_TRIGGER:
+ {
+ 1, (((ul_res_alloc_type_0==1) &&(ul_res_alloc_type_1==0))||(freqHopping == 0))?0:1,
+ 0, 0, 0,0,0,0
+ }, // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
+ {0, 0, 0, 5, 0,0,0,0}, // 18 TB1_MCS:
+ {0, 0, 0, 1, 0,0,0,0}, // 19 TB1_NDI:
+ {0, 0, 0, 2, 0,0,0,0}, // 20 TB1_RV:
+ {0, 0, 0, 5, 0,0,0,0}, // 21 TB2_MCS:
+ {0, 0, 0, 1, 0,0,0,0}, // 22 TB2_NDI:
+ {0, 0, 0, 2, 0,0,0,0}, // 23 TB2_RV:
+ {5, 5, 5, 0, 0,0,0,0}, // 24 MCS:
+ {1, 1, (crc_scrambled == _c_rnti)?1:0,0, 0,0,0,0}, // 25 NDI:
+ {
+ 2, 2, (((crc_scrambled == _c_rnti) || (crc_scrambled == _si_rnti)) ? 2:0),
+ 0, 0,0,0,0
+ }, // 26 RV:
+ {4, 4, (crc_scrambled == _c_rnti)?4:0,4, 0,0,0,0}, // 27 HARQ_PROCESS_NUMBER:
+ {0, 0, (crc_scrambled == _c_rnti)?2:0,n_dai, 0,0,0,0}, // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
+ // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
+ // 0 otherwise
+ {0, codebook_HARQ_ACK, 0, 0, 0,0,0,0}, // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK // 2 bits for dynamic HARQ-ACK codebook with single HARQ-ACK codebook
+ {
+ 0, (((codebook_HARQ_ACK == 2) &&(n_HARQ_ACK_sub_codebooks==2))?2:0),
+ 0, 0, 0,0,0,0
+ }, // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks // 0 bits otherwise
+ {
+ 0, 0, (((crc_scrambled == _p_rnti) || (crc_scrambled == _ra_rnti)) ? 2:0),
+ 0, 0,0,0,0
+ }, // 31 TB_SCALING
+ {2, 2, 0, 0, 0,0,0,0}, // 32 TPC_PUSCH:
+ {0, 0, (crc_scrambled == _c_rnti)?2:0,2, 0,0,0,0}, // 33 TPC_PUCCH:
+ {0, 0, (crc_scrambled == _c_rnti)?3:0,3, 0,0,0,0}, // 34 PUCCH_RESOURCE_IND:
+ {0, 0, (crc_scrambled == _c_rnti)?3:0,pdsch_harq_t_ind, 0,0,0,0}, // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
+ {0, (uint8_t)log2(n_SRS), 0, 0, 0,0,0,0}, // 36 SRS_RESOURCE_IND:
+ {0, precond_nbr_layers_bits, 0, 0, 0,0,0,0}, // 37 PRECOD_NBR_LAYERS:
+ {0, antenna_ports_bits_ul, 0, antenna_ports_bits_dl, 0,0,0,0}, // 38 ANTENNA_PORTS:
+ {0, 0, 0, tci_bits, 0,0,0,0}, // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
+ {0, (sul_ind == 0)?2:3, 0, (sul_ind == 0)?2:3, 0,0,0,2}, // 40 SRS_REQUEST:
+ {
+ 0, 0, 0, 0, 0,0,tpc_cmd_bit_2_2,
+ tpc_cmd_bit_2_3
+ },
+ // 41 TPC_CMD:
+ {0, reportTriggerSize, 0, 0, 0,0,0,0}, // 42 CSI_REQUEST:
+ {
+ 0, maxCodeBlockGroupsPerTransportBlock,
+ 0, maxCodeBlockGroupsPerTransportBlock_dl,
+ 0,0,0,0
+ }, // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
+ {0, 0, 0, cbgfi_bit, 0,0,0,0}, // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
+ {0, ptrs_dmrs_bits, 0, 0, 0,0,0,0}, // 45 PTRS_DMRS:
+ {0, betaOffsets, 0, 0, 0,0,0,0}, // 46 BETA_OFFSET_IND:
+ {0, dmrs_seq_ini_bits_ul, 0, dmrs_seq_ini_bits_dl, 0,0,0,0}, // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
+ // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
+ {0, 1, 0, 0, 0,0,0,0}, // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
+ {0, 0, 0, 0, 0,0,0,0}, // 49 PADDING_NR_DCI:
+ // (NOTE 2) If DCI format 0_0 is monitored in common search space
+ // and if the number of information bits in the DCI format 0_0 prior to padding
+ // is less than the payload size of the DCI format 1_0 monitored in common search space
+ // zeros shall be appended to the DCI format 0_0
+ // until the payload size equals that of the DCI format 1_0
+ {(sul_ind == 0)?0:1, 0, 0, 0, 0,0,0,0}, // 50 SUL_IND_0_0:
+ {0, 0, 0, 0, 0,0,0,0}, // 51 RA_PREAMBLE_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
+ {0, 0, 0, 0, 0,0,0,0}, // 52 SUL_IND_1_0 (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
+ {0, 0, 0, 0, 0,0,0,0}, // 53 SS_PBCH_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
+ {0, 0, 0, 0, 0,0,0,0}, // 54 PRACH_MASK_INDEX (random access procedure initiated by a PDCCH order not implemented, FIXME!!!)
+ {
+ 0, 0, ((crc_scrambled == _p_rnti)?6:(((crc_scrambled == _si_rnti) || (crc_scrambled == _ra_rnti))?16:0)),
+ 0, 0,0,0,0
+ } // 55 RESERVED_NR_DCI
+ };
+ // NOTE 1: adjustments in freq_dom_resource_assignment_UL to be done if necessary
+ // NOTE 2: adjustments in padding to be done if necessary
+ uint8_t dci_size [8] = {0,0,0,0,0,0,0,0}; // will contain size for each format
+
+ for (int i=0 ; i<NBR_NR_FORMATS ; i++) {
+ //#ifdef NR_PDCCH_DCI_DEBUG
+ // LOG_DDD("i=%d, j=%d\n", i, j);
+ //#endif
+ for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
+ dci_size [i] = dci_size [i] + dci_field_size_table[j][i]; // dci_size[i] contains the size in bits of the dci pdu format i
+ //if (i==(int)format-15) { // (int)format-15 indicates the position of each format in the table (e.g. format1_0=17 -> position in table is 2)
+ dci_fields_sizes[j][i] = dci_field_size_table[j][i]; // dci_fields_sizes[j] contains the sizes of each field (j) for a determined format i
+ //}
}
+ LOG_DDD("(nr_dci_format_size) dci_size[%d]=%d for n_RB_ULBWP=%d\n",
+ i,dci_size[i],n_RB_ULBWP);
+ }
- mac->scheduled_response.dl_config = dl_config;
-
+ LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n");
+
+#ifdef NR_PDCCH_DCI_DEBUG
+ for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
+ printf("\t\t");
+
+ for (int i=0; i<NBR_NR_FORMATS ; i++) printf("%d\t",dci_fields_sizes[j][i]);
+
+ printf("\n");
+ }
+
+ printf(" }\n");
+#endif
+ LOG_DNL("(nr_dci_format_size) dci_size[0_0]=%d, dci_size[0_1]=%d, dci_size[1_0]=%d, dci_size[1_1]=%d,\n",dci_size[0],dci_size[1],dci_size[2],dci_size[3]);
+
+ //UL/SUL indicator format0_0 (TS 38.212 subclause 7.3.1.1.1)
+ // - 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding is larger than the number of bits for DCI format 0_0 before padding;
+ // - 0 bit otherwise.
+ // The UL/SUL indicator, if present, locates in the last bit position of DCI format 0_0, after the padding bit(s)
+ if ((dci_field_size_table[SUL_IND_0_0][0] == 1) && (dci_size[0] > dci_size[2])) {
+ dci_field_size_table[SUL_IND_0_0][0] = 0;
+ dci_size[0]=dci_size[0]-1;
+ }
+
+ // if ((format == format0_0) || (format == format1_0)) {
+ // According to Section 7.3.1.1.1 in TS 38.212
+ // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding
+ // is less than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell,
+ // zeros shall be appended to the DCI format 0_0 until the payload size equals that of the DCI format 1_0.
+ if (dci_size[0] < dci_size[2]) { // '0' corresponding to index for format0_0 and '2' corresponding to index of format1_0
+ //if (format == format0_0) {
+ dci_fields_sizes[PADDING_NR_DCI][0] = dci_size[2] - dci_size[0];
+ dci_size[0] = dci_size[2];
+ LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]);
+ //}
+ }
+
+ // If DCI format 0_0 is monitored in common search space and if the number of information bits in the DCI format 0_0 prior to padding
+ // is larger than the payload size of the DCI format 1_0 monitored in common search space for scheduling the same serving cell,
+ // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 is reduced
+ // such that the size of DCI format 0_0 equals to the size of the DCI format 1_0..
+ if (dci_size[0] > dci_size[2]) {
+ //if (format == format0_0) {
+ dci_fields_sizes[FREQ_DOM_RESOURCE_ASSIGNMENT_UL][0] -= (dci_size[0] - dci_size[2]);
+ dci_size[0] = dci_size[2];
+ LOG_DDD("(nr_dci_format_size) new dci_size[format0_0]=%d\n",dci_size[0]);
+ //}
+ }
- return UE_CONNECTION_OK;
+ /*
+ * TS 38.212 subclause 7.3.1.1.2
+ * For a UE configured with SUL in a cell:
+ * if PUSCH is configured to be transmitted on both the SUL and the non-SUL of the cell and
+ * if the number of information bits in format 0_1 for the SUL
+ * is not equal to the number of information bits in format 0_1 for the non-SUL,
+ * zeros shall be appended to smaller format 0_1 until the payload size equals that of the larger format 0_1
+ *
+ * Not implemented. FIXME!!!
+ *
+ */
+ // }
+ LOG_DDD("(nr_dci_format_size) dci_fields_sizes[][] = { \n");
+
+#ifdef NR_PDCCH_DCI_DEBUG
+ for (int j=0; j<NBR_NR_DCI_FIELDS; j++) {
+ printf("\t\t");
+
+ for (int i=0; i<NBR_NR_FORMATS ; i++) printf("%d\t",dci_fields_sizes[j][i]);
+
+ printf("\n");
+ }
+
+ printf(" }\n");
+#endif
+ return dci_size[format];
}
+#endif
+
//////////////
/*
* This code contains all the functions needed to process all dci fields.
@@ -726,549 +1313,549 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
// next four columns contain table 7.3.1.1.2-4: Precoding information and number of layers, for 2 antenna ports, if transformPrecoder=disabled and maxRank = 2
// next four columns contain table 7.3.1.1.2-5: Precoding information and number of layers, for 2 antenna ports, if transformPrecoder= enabled, or if transformPrecoder= disabled and maxRank = 1
uint8_t table_7_3_1_1_2_2_3_4_5[64][20] = {
-{1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0},
-{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
-{1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 2, 0, 2, 0, 1, 2, 0, 0},
-{1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 2, 0, 0, 1, 3, 0, 0},
-{2, 0, 2, 0, 2, 0, 1, 4, 1, 4, 0, 0, 1, 3, 0, 0, 1, 4, 0, 0},
-{2, 1, 2, 1, 2, 1, 1, 5, 1, 5, 0, 0, 1, 4, 0, 0, 1, 5, 0, 0},
-{2, 2, 2, 2, 2, 2, 1, 6, 1, 6, 0, 0, 1, 5, 0, 0, 0, 0, 0, 0},
-{2, 3, 2, 3, 2, 3, 1, 7, 1, 7, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0},
-{2, 4, 2, 4, 2, 4, 1, 8, 1, 8, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0},
-{2, 5, 2, 5, 2, 5, 1, 9, 1, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 0, 3, 0, 3, 0, 1, 10, 1, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{4, 0, 4, 0, 4, 0, 1, 11, 1, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 4, 1, 4, 0, 0, 1, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 5, 1, 5, 0, 0, 1, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 6, 1, 6, 0, 0, 1, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 7, 1, 7, 0, 0, 1, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 8, 1, 8, 0, 0, 1, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 9, 1, 9, 0, 0, 1, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 10, 1, 10, 0, 0, 1, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 11, 1, 11, 0, 0, 1, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 6, 2, 6, 0, 0, 1, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 7, 2, 7, 0, 0, 1, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 8, 2, 8, 0, 0, 1, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 9, 2, 9, 0, 0, 1, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 10, 2, 10, 0, 0, 1, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 11, 2, 11, 0, 0, 1, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 12, 2, 12, 0, 0, 1, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 13, 2, 13, 0, 0, 1, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 2, 3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{4, 1, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{4, 2, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{1, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{2, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{3, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+ {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0},
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
+ {1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 2, 0, 2, 0, 1, 2, 0, 0},
+ {1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 2, 0, 0, 1, 3, 0, 0},
+ {2, 0, 2, 0, 2, 0, 1, 4, 1, 4, 0, 0, 1, 3, 0, 0, 1, 4, 0, 0},
+ {2, 1, 2, 1, 2, 1, 1, 5, 1, 5, 0, 0, 1, 4, 0, 0, 1, 5, 0, 0},
+ {2, 2, 2, 2, 2, 2, 1, 6, 1, 6, 0, 0, 1, 5, 0, 0, 0, 0, 0, 0},
+ {2, 3, 2, 3, 2, 3, 1, 7, 1, 7, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0},
+ {2, 4, 2, 4, 2, 4, 1, 8, 1, 8, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0},
+ {2, 5, 2, 5, 2, 5, 1, 9, 1, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 0, 3, 0, 3, 0, 1, 10, 1, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 0, 4, 0, 4, 0, 1, 11, 1, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 4, 1, 4, 0, 0, 1, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 5, 1, 5, 0, 0, 1, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 6, 1, 6, 0, 0, 1, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 7, 1, 7, 0, 0, 1, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 8, 1, 8, 0, 0, 1, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 9, 1, 9, 0, 0, 1, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 10, 1, 10, 0, 0, 1, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 11, 1, 11, 0, 0, 1, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 6, 2, 6, 0, 0, 1, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 7, 2, 7, 0, 0, 1, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 8, 2, 8, 0, 0, 1, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 9, 2, 9, 0, 0, 1, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 10, 2, 10, 0, 0, 1, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 11, 2, 11, 0, 0, 1, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 12, 2, 12, 0, 0, 1, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 13, 2, 13, 0, 0, 1, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 2, 3, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 1, 4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 2, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {1, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {2, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {3, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
uint8_t table_7_3_1_1_2_12[14][3] = {
-{1,0,1},
-{1,1,1},
-{2,0,1},
-{2,1,1},
-{2,2,1},
-{2,3,1},
-{2,0,2},
-{2,1,2},
-{2,2,2},
-{2,3,2},
-{2,4,2},
-{2,5,2},
-{2,6,2},
-{2,7,2}
+ {1,0,1},
+ {1,1,1},
+ {2,0,1},
+ {2,1,1},
+ {2,2,1},
+ {2,3,1},
+ {2,0,2},
+ {2,1,2},
+ {2,2,2},
+ {2,3,2},
+ {2,4,2},
+ {2,5,2},
+ {2,6,2},
+ {2,7,2}
};
uint8_t table_7_3_1_1_2_13[10][4] = {
-{1,0,1,1},
-{2,0,1,1},
-{2,2,3,1},
-{2,0,2,1},
-{2,0,1,2},
-{2,2,3,2},
-{2,4,5,2},
-{2,6,7,2},
-{2,0,4,2},
-{2,2,6,2}
+ {1,0,1,1},
+ {2,0,1,1},
+ {2,2,3,1},
+ {2,0,2,1},
+ {2,0,1,2},
+ {2,2,3,2},
+ {2,4,5,2},
+ {2,6,7,2},
+ {2,0,4,2},
+ {2,2,6,2}
};
uint8_t table_7_3_1_1_2_14[3][5] = {
-{2,0,1,2,1},
-{2,0,1,4,2},
-{2,2,3,6,2}
+ {2,0,1,2,1},
+ {2,0,1,4,2},
+ {2,2,3,6,2}
};
uint8_t table_7_3_1_1_2_15[4][6] = {
-{2,0,1,2,3,1},
-{2,0,1,4,5,2},
-{2,2,3,6,7,2},
-{2,0,2,4,6,2}
+ {2,0,1,2,3,1},
+ {2,0,1,4,5,2},
+ {2,2,3,6,7,2},
+ {2,0,2,4,6,2}
};
uint8_t table_7_3_1_1_2_16[12][2] = {
-{1,0},
-{1,1},
-{2,0},
-{2,1},
-{2,2},
-{2,3},
-{3,0},
-{3,1},
-{3,2},
-{3,3},
-{3,4},
-{3,5}
+ {1,0},
+ {1,1},
+ {2,0},
+ {2,1},
+ {2,2},
+ {2,3},
+ {3,0},
+ {3,1},
+ {3,2},
+ {3,3},
+ {3,4},
+ {3,5}
};
uint8_t table_7_3_1_1_2_17[7][3] = {
-{1,0,1},
-{2,0,1},
-{2,2,3},
-{3,0,1},
-{3,2,3},
-{3,4,5},
-{2,0,2}
+ {1,0,1},
+ {2,0,1},
+ {2,2,3},
+ {3,0,1},
+ {3,2,3},
+ {3,4,5},
+ {2,0,2}
};
uint8_t table_7_3_1_1_2_18[3][4] = {
-{2,0,1,2},
-{3,0,1,2},
-{3,3,4,5}
+ {2,0,1,2},
+ {3,0,1,2},
+ {3,3,4,5}
};
uint8_t table_7_3_1_1_2_19[2][5] = {
-{2,0,1,2,3},
-{3,0,1,2,3}
+ {2,0,1,2,3},
+ {3,0,1,2,3}
};
uint8_t table_7_3_1_1_2_20[28][3] = {
-{1,0,1},
-{1,1,1},
-{2,0,1},
-{2,1,1},
-{2,2,1},
-{2,3,1},
-{3,0,1},
-{3,1,1},
-{3,2,1},
-{3,3,1},
-{3,4,1},
-{3,5,1},
-{3,0,2},
-{3,1,2},
-{3,2,2},
-{3,3,2},
-{3,4,2},
-{3,5,2},
-{3,6,2},
-{3,7,2},
-{3,8,2},
-{3,9,2},
-{3,10,2},
-{3,11,2},
-{1,0,2},
-{1,1,2},
-{1,6,2},
-{1,7,2}
+ {1,0,1},
+ {1,1,1},
+ {2,0,1},
+ {2,1,1},
+ {2,2,1},
+ {2,3,1},
+ {3,0,1},
+ {3,1,1},
+ {3,2,1},
+ {3,3,1},
+ {3,4,1},
+ {3,5,1},
+ {3,0,2},
+ {3,1,2},
+ {3,2,2},
+ {3,3,2},
+ {3,4,2},
+ {3,5,2},
+ {3,6,2},
+ {3,7,2},
+ {3,8,2},
+ {3,9,2},
+ {3,10,2},
+ {3,11,2},
+ {1,0,2},
+ {1,1,2},
+ {1,6,2},
+ {1,7,2}
};
uint8_t table_7_3_1_1_2_21[19][4] = {
-{1,0,1,1},
-{2,0,1,1},
-{2,2,3,1},
-{3,0,1,1},
-{3,2,3,1},
-{3,4,5,1},
-{2,0,2,1},
-{3,0,1,2},
-{3,2,3,2},
-{3,4,5,2},
-{3,6,7,2},
-{3,8,9,2},
-{3,10,11,2},
-{1,0,1,2},
-{1,6,7,2},
-{2,0,1,2},
-{2,2,3,2},
-{2,6,7,2},
-{2,8,9,2}
+ {1,0,1,1},
+ {2,0,1,1},
+ {2,2,3,1},
+ {3,0,1,1},
+ {3,2,3,1},
+ {3,4,5,1},
+ {2,0,2,1},
+ {3,0,1,2},
+ {3,2,3,2},
+ {3,4,5,2},
+ {3,6,7,2},
+ {3,8,9,2},
+ {3,10,11,2},
+ {1,0,1,2},
+ {1,6,7,2},
+ {2,0,1,2},
+ {2,2,3,2},
+ {2,6,7,2},
+ {2,8,9,2}
};
uint8_t table_7_3_1_1_2_22[6][5] = {
-{2,0,1,2,1},
-{3,0,1,2,1},
-{3,3,4,5,1},
-{3,0,1,6,2},
-{3,2,3,8,2},
-{3,4,5,10,2}
+ {2,0,1,2,1},
+ {3,0,1,2,1},
+ {3,3,4,5,1},
+ {3,0,1,6,2},
+ {3,2,3,8,2},
+ {3,4,5,10,2}
};
uint8_t table_7_3_1_1_2_23[5][6] = {
-{2,0,1,2,3,1},
-{3,0,1,2,3,1},
-{3,0,1,6,7,2},
-{3,2,3,8,9,2},
-{3,4,5,10,11,2}
+ {2,0,1,2,3,1},
+ {3,0,1,2,3,1},
+ {3,0,1,6,7,2},
+ {3,2,3,8,9,2},
+ {3,4,5,10,11,2}
};
uint8_t table_7_3_2_3_3_1[12][5] = {
-{1,0,0,0,0},
-{1,1,0,0,0},
-{1,0,1,0,0},
-{2,0,0,0,0},
-{2,1,0,0,0},
-{2,2,0,0,0},
-{2,3,0,0,0},
-{2,0,1,0,0},
-{2,2,3,0,0},
-{2,0,1,2,0},
-{2,0,1,2,3},
-{2,0,2,0,0}
+ {1,0,0,0,0},
+ {1,1,0,0,0},
+ {1,0,1,0,0},
+ {2,0,0,0,0},
+ {2,1,0,0,0},
+ {2,2,0,0,0},
+ {2,3,0,0,0},
+ {2,0,1,0,0},
+ {2,2,3,0,0},
+ {2,0,1,2,0},
+ {2,0,1,2,3},
+ {2,0,2,0,0}
};
uint8_t table_7_3_2_3_3_2_oneCodeword[31][6] = {
-{1,0,0,0,0,1},
-{1,1,0,0,0,1},
-{1,0,1,0,0,1},
-{2,0,0,0,0,1},
-{2,1,0,0,0,1},
-{2,2,0,0,0,1},
-{2,3,0,0,0,1},
-{2,0,1,0,0,1},
-{2,2,3,0,0,1},
-{2,0,1,2,0,1},
-{2,0,1,2,3,1},
-{2,0,2,0,0,1},
-{2,0,0,0,0,2},
-{2,1,0,0,0,2},
-{2,2,0,0,0,2},
-{2,3,0,0,0,2},
-{2,4,0,0,0,2},
-{2,5,0,0,0,2},
-{2,6,0,0,0,2},
-{2,7,0,0,0,2},
-{2,0,1,0,0,2},
-{2,2,3,0,0,2},
-{2,4,5,0,0,2},
-{2,6,7,0,0,2},
-{2,0,4,0,0,2},
-{2,2,6,0,0,2},
-{2,0,1,4,0,2},
-{2,2,3,6,0,2},
-{2,0,1,4,5,2},
-{2,2,3,6,7,2},
-{2,0,2,4,6,2}
+ {1,0,0,0,0,1},
+ {1,1,0,0,0,1},
+ {1,0,1,0,0,1},
+ {2,0,0,0,0,1},
+ {2,1,0,0,0,1},
+ {2,2,0,0,0,1},
+ {2,3,0,0,0,1},
+ {2,0,1,0,0,1},
+ {2,2,3,0,0,1},
+ {2,0,1,2,0,1},
+ {2,0,1,2,3,1},
+ {2,0,2,0,0,1},
+ {2,0,0,0,0,2},
+ {2,1,0,0,0,2},
+ {2,2,0,0,0,2},
+ {2,3,0,0,0,2},
+ {2,4,0,0,0,2},
+ {2,5,0,0,0,2},
+ {2,6,0,0,0,2},
+ {2,7,0,0,0,2},
+ {2,0,1,0,0,2},
+ {2,2,3,0,0,2},
+ {2,4,5,0,0,2},
+ {2,6,7,0,0,2},
+ {2,0,4,0,0,2},
+ {2,2,6,0,0,2},
+ {2,0,1,4,0,2},
+ {2,2,3,6,0,2},
+ {2,0,1,4,5,2},
+ {2,2,3,6,7,2},
+ {2,0,2,4,6,2}
};
uint8_t table_7_3_2_3_3_2_twoCodeword[4][10] = {
-{2,0,1,2,3,4,0,0,0,2},
-{2,0,1,2,3,4,6,0,0,2},
-{2,0,1,2,3,4,5,6,0,2},
-{2,0,1,2,3,4,5,6,7,2}
+ {2,0,1,2,3,4,0,0,0,2},
+ {2,0,1,2,3,4,6,0,0,2},
+ {2,0,1,2,3,4,5,6,0,2},
+ {2,0,1,2,3,4,5,6,7,2}
};
uint8_t table_7_3_2_3_3_3_oneCodeword[24][5] = {
-{1,0,0,0,0},
-{1,1,0,0,0},
-{1,0,1,0,0},
-{2,0,0,0,0},
-{2,1,0,0,0},
-{2,2,0,0,0},
-{2,3,0,0,0},
-{2,0,1,0,0},
-{2,2,3,0,0},
-{2,0,1,2,0},
-{2,0,1,2,3},
-{3,0,0,0,0},
-{3,1,0,0,0},
-{3,2,0,0,0},
-{3,3,0,0,0},
-{3,4,0,0,0},
-{3,5,0,0,0},
-{3,0,1,0,0},
-{3,2,3,0,0},
-{3,4,5,0,0},
-{3,0,1,2,0},
-{3,3,4,5,0},
-{3,0,1,2,3},
-{2,0,2,0,0}
+ {1,0,0,0,0},
+ {1,1,0,0,0},
+ {1,0,1,0,0},
+ {2,0,0,0,0},
+ {2,1,0,0,0},
+ {2,2,0,0,0},
+ {2,3,0,0,0},
+ {2,0,1,0,0},
+ {2,2,3,0,0},
+ {2,0,1,2,0},
+ {2,0,1,2,3},
+ {3,0,0,0,0},
+ {3,1,0,0,0},
+ {3,2,0,0,0},
+ {3,3,0,0,0},
+ {3,4,0,0,0},
+ {3,5,0,0,0},
+ {3,0,1,0,0},
+ {3,2,3,0,0},
+ {3,4,5,0,0},
+ {3,0,1,2,0},
+ {3,3,4,5,0},
+ {3,0,1,2,3},
+ {2,0,2,0,0}
};
uint8_t table_7_3_2_3_3_3_twoCodeword[2][7] = {
-{3,0,1,2,3,4,0},
-{3,0,1,2,3,4,5}
+ {3,0,1,2,3,4,0},
+ {3,0,1,2,3,4,5}
};
uint8_t table_7_3_2_3_3_4_oneCodeword[58][6] = {
-{1,0,0,0,0,1},
-{1,1,0,0,0,1},
-{1,0,1,0,0,1},
-{2,0,0,0,0,1},
-{2,1,0,0,0,1},
-{2,2,0,0,0,1},
-{2,3,0,0,0,1},
-{2,0,1,0,0,1},
-{2,2,3,0,0,1},
-{2,0,1,2,0,1},
-{2,0,1,2,3,1},
-{3,0,0,0,0,1},
-{3,1,0,0,0,1},
-{3,2,0,0,0,1},
-{3,3,0,0,0,1},
-{3,4,0,0,0,1},
-{3,5,0,0,0,1},
-{3,0,1,0,0,1},
-{3,2,3,0,0,1},
-{3,4,5,0,0,1},
-{3,0,1,2,0,1},
-{3,3,4,5,0,1},
-{3,0,1,2,3,1},
-{2,0,2,0,0,1},
-{3,0,0,0,0,2},
-{3,1,0,0,0,2},
-{3,2,0,0,0,2},
-{3,3,0,0,0,2},
-{3,4,0,0,0,2},
-{3,5,0,0,0,2},
-{3,6,0,0,0,2},
-{3,7,0,0,0,2},
-{3,8,0,0,0,2},
-{3,9,0,0,0,2},
-{3,10,0,0,0,2},
-{3,11,0,0,0,2},
-{3,0,1,0,0,2},
-{3,2,3,0,0,2},
-{3,4,5,0,0,2},
-{3,6,7,0,0,2},
-{3,8,9,0,0,2},
-{3,10,11,0,0,2},
-{3,0,1,6,0,2},
-{3,2,3,8,0,2},
-{3,4,5,10,0,2},
-{3,0,1,6,7,2},
-{3,2,3,8,9,2},
-{3,4,5,10,11,2},
-{1,0,0,0,0,2},
-{1,1,0,0,0,2},
-{1,6,0,0,0,2},
-{1,7,0,0,0,2},
-{1,0,1,0,0,2},
-{1,6,7,0,0,2},
-{2,0,1,0,0,2},
-{2,2,3,0,0,2},
-{2,6,7,0,0,2},
-{2,8,9,0,0,2}
+ {1,0,0,0,0,1},
+ {1,1,0,0,0,1},
+ {1,0,1,0,0,1},
+ {2,0,0,0,0,1},
+ {2,1,0,0,0,1},
+ {2,2,0,0,0,1},
+ {2,3,0,0,0,1},
+ {2,0,1,0,0,1},
+ {2,2,3,0,0,1},
+ {2,0,1,2,0,1},
+ {2,0,1,2,3,1},
+ {3,0,0,0,0,1},
+ {3,1,0,0,0,1},
+ {3,2,0,0,0,1},
+ {3,3,0,0,0,1},
+ {3,4,0,0,0,1},
+ {3,5,0,0,0,1},
+ {3,0,1,0,0,1},
+ {3,2,3,0,0,1},
+ {3,4,5,0,0,1},
+ {3,0,1,2,0,1},
+ {3,3,4,5,0,1},
+ {3,0,1,2,3,1},
+ {2,0,2,0,0,1},
+ {3,0,0,0,0,2},
+ {3,1,0,0,0,2},
+ {3,2,0,0,0,2},
+ {3,3,0,0,0,2},
+ {3,4,0,0,0,2},
+ {3,5,0,0,0,2},
+ {3,6,0,0,0,2},
+ {3,7,0,0,0,2},
+ {3,8,0,0,0,2},
+ {3,9,0,0,0,2},
+ {3,10,0,0,0,2},
+ {3,11,0,0,0,2},
+ {3,0,1,0,0,2},
+ {3,2,3,0,0,2},
+ {3,4,5,0,0,2},
+ {3,6,7,0,0,2},
+ {3,8,9,0,0,2},
+ {3,10,11,0,0,2},
+ {3,0,1,6,0,2},
+ {3,2,3,8,0,2},
+ {3,4,5,10,0,2},
+ {3,0,1,6,7,2},
+ {3,2,3,8,9,2},
+ {3,4,5,10,11,2},
+ {1,0,0,0,0,2},
+ {1,1,0,0,0,2},
+ {1,6,0,0,0,2},
+ {1,7,0,0,0,2},
+ {1,0,1,0,0,2},
+ {1,6,7,0,0,2},
+ {2,0,1,0,0,2},
+ {2,2,3,0,0,2},
+ {2,6,7,0,0,2},
+ {2,8,9,0,0,2}
};
uint8_t table_7_3_2_3_3_4_twoCodeword[6][10] = {
-{3,0,1,2,3,4,0,0,0,1},
-{3,0,1,2,3,4,5,0,0,1},
-{2,0,1,2,3,6,0,0,0,2},
-{2,0,1,2,3,6,8,0,0,2},
-{2,0,1,2,3,6,7,8,0,2},
-{2,0,1,2,3,6,7,8,9,2}
+ {3,0,1,2,3,4,0,0,0,1},
+ {3,0,1,2,3,4,5,0,0,1},
+ {2,0,1,2,3,6,0,0,0,2},
+ {2,0,1,2,3,6,8,0,0,2},
+ {2,0,1,2,3,6,7,8,0,2},
+ {2,0,1,2,3,6,7,8,9,2}
};
int8_t nr_ue_process_dci_freq_dom_resource_assignment(
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
- uint16_t n_RB_ULBWP,
- uint16_t n_RB_DLBWP,
- uint16_t riv
-){
+ fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
+ fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
+ uint16_t n_RB_ULBWP,
+ uint16_t n_RB_DLBWP,
+ uint16_t riv
+ ){
uint16_t l_RB;
uint16_t start_RB;
uint16_t tmp_RIV;
-/*
- * TS 38.214 subclause 5.1.2.2 Resource allocation in frequency domain (downlink)
- * when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used
- */
- if(dlsch_config_pdu != NULL){
- /*
- * TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
- */
/*
- * TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1
+ * TS 38.214 subclause 5.1.2.2 Resource allocation in frequency domain (downlink)
+ * when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used
*/
- // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
- // RIV = n_RB_DLBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_DLBWP/2)
- // RIV = n_RB_DLBWP * (n_RB_DLBWP - l_RB + 1) + (n_RB_DLBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_DLBWP/2)
- // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2)
- l_RB = floor(riv/n_RB_DLBWP) + 1;
- start_RB = riv%n_RB_DLBWP;
- // if (l_RB - 1) > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines
- tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB;
- if ((tmp_RIV != riv) || ((start_RB+l_RB)>n_RB_DLBWP)) { // then (l_RB - 1) > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB
- l_RB = n_RB_DLBWP - l_RB + 2;
- start_RB = n_RB_DLBWP - start_RB - 1;
- }
- dlsch_config_pdu->number_rbs = l_RB;
- dlsch_config_pdu->start_rb = start_RB;
+ if(dlsch_config_pdu != NULL){
+
+ /*
+ * TS 38.214 subclause 5.1.2.2.1 Downlink resource allocation type 0
+ */
+ /*
+ * TS 38.214 subclause 5.1.2.2.2 Downlink resource allocation type 1
+ */
+
+ dlsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_DLBWP);
+ dlsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_DLBWP);
+
}
if(ulsch_config_pdu != NULL){
-/*
- * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink)
- */
- /*
- * TS 38.214 subclause 6.1.2.2.1 Uplink resource allocation type 0
- */
- /*
- * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1
- */
- // For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
- // RIV = n_RB_ULBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_ULBWP/2)
- // RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_ULBWP/2)
- // the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2)
- l_RB = floor(riv/n_RB_ULBWP) + 1;
- start_RB = riv%n_RB_ULBWP;
- // if (l_RB - 1) > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines
- tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB;
- if (tmp_RIV != riv) { // then (l_RB - 1) > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB
- l_RB = n_RB_ULBWP - l_RB + 2;
- start_RB = n_RB_ULBWP - start_RB - 1;
- }
- ulsch_config_pdu->number_rbs = l_RB;
- ulsch_config_pdu->start_rb = start_RB;
+ /*
+ * TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink)
+ */
+ /*
+ * TS 38.214 subclause 6.1.2.2.1 Uplink resource allocation type 0
+ */
+ /*
+ * TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1
+ */
+
+ ulsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_ULBWP);
+ ulsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_ULBWP);
}
return 0;
}
-int8_t nr_ue_process_dci_time_dom_resource_assignment(
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
- uint8_t time_domain_ind,
- long dmrs_typeA_pos //0=pos2,1=pos3
-){
+int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
+ fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
+ fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
+ uint8_t time_domain_ind
+ ){
+ int dmrs_typeA_pos = mac->scc->dmrs_TypeA_Position;
uint8_t k_offset=0;
uint8_t sliv_S=0;
uint8_t sliv_L=0;
uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?12:11}, // row index 1
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5
- {0,(dmrs_typeA_pos == 0)?9:10,(dmrs_typeA_pos == 0)?4:4}, // row index 6
- {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7
- {0,5,7}, // row index 8
- {0,5,2}, // row index 9
- {0,9,2}, // row index 10
- {0,12,2}, // row index 11
- {0,1,13}, // row index 12
- {0,1,6}, // row index 13
- {0,2,4}, // row index 14
- {0,4,7}, // row index 15
- {0,8,4} // row index 16
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?12:11}, // row index 1
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5
+ {0,(dmrs_typeA_pos == 0)?9:10,(dmrs_typeA_pos == 0)?4:4}, // row index 6
+ {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7
+ {0,5,7}, // row index 8
+ {0,5,2}, // row index 9
+ {0,9,2}, // row index 10
+ {0,12,2}, // row index 11
+ {0,1,13}, // row index 12
+ {0,1,6}, // row index 13
+ {0,2,4}, // row index 14
+ {0,4,7}, // row index 15
+ {0,8,4} // row index 16
};
/*uint8_t table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5}, // row index 1
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4
- {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5
- {0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2}, // row index 6
- {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7
- {0,5,6}, // row index 8
- {0,5,2}, // row index 9
- {0,9,2}, // row index 10
- {0,10,2}, // row index 11
- {0,1,11}, // row index 12
- {0,1,6}, // row index 13
- {0,2,4}, // row index 14
- {0,4,6}, // row index 15
- {0,8,4} // row index 16
- };*/
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?6:5}, // row index 1
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?10:9}, // row index 2
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?9:8}, // row index 3
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?7:6}, // row index 4
+ {0,(dmrs_typeA_pos == 0)?2:3, (dmrs_typeA_pos == 0)?5:4}, // row index 5
+ {0,(dmrs_typeA_pos == 0)?6:8, (dmrs_typeA_pos == 0)?4:2}, // row index 6
+ {0,(dmrs_typeA_pos == 0)?4:6, (dmrs_typeA_pos == 0)?4:4}, // row index 7
+ {0,5,6}, // row index 8
+ {0,5,2}, // row index 9
+ {0,9,2}, // row index 10
+ {0,10,2}, // row index 11
+ {0,1,11}, // row index 12
+ {0,1,6}, // row index 13
+ {0,2,4}, // row index 14
+ {0,4,6}, // row index 15
+ {0,8,4} // row index 16
+ };*/
/*uint8_t table_5_1_2_1_1_4_time_dom_res_alloc_B[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
- {0,2,2}, // row index 1
- {0,4,2}, // row index 2
- {0,6,2}, // row index 3
- {0,8,2}, // row index 4
- {0,10,2}, // row index 5
- {1,2,2}, // row index 6
- {1,4,2}, // row index 7
- {0,2,4}, // row index 8
- {0,4,4}, // row index 9
- {0,6,4}, // row index 10
- {0,8,4}, // row index 11
- {0,10,4}, // row index 12
- {0,2,7}, // row index 13
- {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
- {1,2,4}, // row index 15
- {0,0,0} // row index 16
- };*/
+ {0,2,2}, // row index 1
+ {0,4,2}, // row index 2
+ {0,6,2}, // row index 3
+ {0,8,2}, // row index 4
+ {0,10,2}, // row index 5
+ {1,2,2}, // row index 6
+ {1,4,2}, // row index 7
+ {0,2,4}, // row index 8
+ {0,4,4}, // row index 9
+ {0,6,4}, // row index 10
+ {0,8,4}, // row index 11
+ {0,10,4}, // row index 12
+ {0,2,7}, // row index 13
+ {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
+ {1,2,4}, // row index 15
+ {0,0,0} // row index 16
+ };*/
/*uint8_t table_5_1_2_1_1_5_time_dom_res_alloc_C[16][3]={ // for PDSCH from TS 38.214 subclause 5.1.2.1.1
- {0,2,2}, // row index 1
- {0,4,2}, // row index 2
- {0,6,2}, // row index 3
- {0,8,2}, // row index 4
- {0,10,2}, // row index 5
- {0,0,0}, // row index 6
- {0,0,0}, // row index 7
- {0,2,4}, // row index 8
- {0,4,4}, // row index 9
- {0,6,4}, // row index 10
- {0,8,4}, // row index 11
- {0,10,4}, // row index 12
- {0,2,7}, // row index 13
- {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
- {0,0,6}, // row index 15
- {0,2,6} // row index 16
- };*/
+ {0,2,2}, // row index 1
+ {0,4,2}, // row index 2
+ {0,6,2}, // row index 3
+ {0,8,2}, // row index 4
+ {0,10,2}, // row index 5
+ {0,0,0}, // row index 6
+ {0,0,0}, // row index 7
+ {0,2,4}, // row index 8
+ {0,4,4}, // row index 9
+ {0,6,4}, // row index 10
+ {0,8,4}, // row index 11
+ {0,10,4}, // row index 12
+ {0,2,7}, // row index 13
+ {0,(dmrs_typeA_pos == 0)?2:3,(dmrs_typeA_pos == 0)?12:11}, // row index 14
+ {0,0,6}, // row index 15
+ {0,2,6} // row index 16
+ };*/
uint8_t mu_pusch = 1;
// definition table j Table 6.1.2.1.1-4
uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1;
uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1
- {j, 0,14}, // row index 1
- {j, 0,12}, // row index 2
- {j, 0,10}, // row index 3
- {j, 2,10}, // row index 4
- {j, 4,10}, // row index 5
- {j, 4,8}, // row index 6
- {j, 4,6}, // row index 7
- {j+1,0,14}, // row index 8
- {j+1,0,12}, // row index 9
- {j+1,0,10}, // row index 10
- {j+2,0,14}, // row index 11
- {j+2,0,12}, // row index 12
- {j+2,0,10}, // row index 13
- {j, 8,6}, // row index 14
- {j+3,0,14}, // row index 15
- {j+3,0,10} // row index 16
+ {j, 0,14}, // row index 1
+ {j, 0,12}, // row index 2
+ {j, 0,10}, // row index 3
+ {j, 2,10}, // row index 4
+ {j, 4,10}, // row index 5
+ {j, 4,8}, // row index 6
+ {j, 4,6}, // row index 7
+ {j+1,0,14}, // row index 8
+ {j+1,0,12}, // row index 9
+ {j+1,0,10}, // row index 10
+ {j+2,0,14}, // row index 11
+ {j+2,0,12}, // row index 12
+ {j+2,0,10}, // row index 13
+ {j, 8,6}, // row index 14
+ {j+3,0,14}, // row index 15
+ {j+3,0,10} // row index 16
};
/*uint8_t table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1
- {j, 0,8}, // row index 1
- {j, 0,12}, // row index 2
- {j, 0,10}, // row index 3
- {j, 2,10}, // row index 4
- {j, 4,4}, // row index 5
- {j, 4,8}, // row index 6
- {j, 4,6}, // row index 7
- {j+1,0,8}, // row index 8
- {j+1,0,12}, // row index 9
- {j+1,0,10}, // row index 10
- {j+2,0,6}, // row index 11
- {j+2,0,12}, // row index 12
- {j+2,0,10}, // row index 13
- {j, 8,4}, // row index 14
- {j+3,0,8}, // row index 15
- {j+3,0,10} // row index 16
- };*/
+ {j, 0,8}, // row index 1
+ {j, 0,12}, // row index 2
+ {j, 0,10}, // row index 3
+ {j, 2,10}, // row index 4
+ {j, 4,4}, // row index 5
+ {j, 4,8}, // row index 6
+ {j, 4,6}, // row index 7
+ {j+1,0,8}, // row index 8
+ {j+1,0,12}, // row index 9
+ {j+1,0,10}, // row index 10
+ {j+2,0,6}, // row index 11
+ {j+2,0,12}, // row index 12
+ {j+2,0,10}, // row index 13
+ {j, 8,4}, // row index 14
+ {j+3,0,8}, // row index 15
+ {j+3,0,10} // row index 16
+ };*/
-/*
- * TS 38.214 subclause 5.1.2.1 Resource allocation in time domain (downlink)
- */
+ /*
+ * TS 38.214 subclause 5.1.2.1 Resource allocation in time domain (downlink)
+ */
if(dlsch_config_pdu != NULL){
+ NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = NULL;
+ if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList)
+ pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList;
+ else if (mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList)
+ pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
+ if (pdsch_TimeDomainAllocationList) {
+
+ AssertFatal(pdsch_TimeDomainAllocationList->list.count > time_domain_ind,
+ "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n",
+ time_domain_ind,pdsch_TimeDomainAllocationList->list.count);
+ int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength;
+ int S,L;
+ SLIV2SL(startSymbolAndLength,&S,&L);
+ dlsch_config_pdu->start_symbol=S;
+ dlsch_config_pdu->number_symbols=L;
+ dlsch_config_pdu->frame_offset = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0!=NULL ?
+ *pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0 :
+ 0;
+ }
+ else {// Default configuration from tables
k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
sliv_S = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1];
sliv_L = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2];
@@ -1284,10 +1871,30 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(
dlsch_config_pdu->frame_offset = k_offset;
dlsch_config_pdu->number_symbols = sliv_L;
dlsch_config_pdu->start_symbol = sliv_S;
+ }
} /*
- * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink)
- */
+ * TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink)
+ */
if(ulsch_config_pdu != NULL){
+ NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL;
+ if (mac->ULbwp[0]->bwp_Dedicated->pusch_Config)
+ pusch_TimeDomainAllocationList = mac->ULbwp[0]->bwp_Dedicated->pusch_Config->choice.setup->pusch_TimeDomainAllocationList;
+
+ if (pusch_TimeDomainAllocationList) {
+ AssertFatal(pusch_TimeDomainAllocationList->list.count > time_domain_ind,
+ "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n",
+ time_domain_ind,pusch_TimeDomainAllocationList->list.count);
+ int startSymbolAndLength = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength;
+ int S,L;
+ SLIV2SL(startSymbolAndLength,&S,&L);
+ ulsch_config_pdu->start_symbol=S;
+ ulsch_config_pdu->number_symbols=L;
+ ulsch_config_pdu->frame_offset = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2!=NULL ?
+ *pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2 :
+ mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz60 ? 1 :
+ mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz120 ? 2 : 3;
+ }
+ else {
k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][1];
sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][2];
@@ -1297,913 +1904,946 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(
ulsch_config_pdu->frame_offset = k_offset;
ulsch_config_pdu->number_symbols = sliv_L;
ulsch_config_pdu->start_symbol = sliv_S;
+ }
}
return 0;
}
//////////////
+int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci) {
-int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ nr_dci_pdu_rel15_t dci_pdu_rel15;
- NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
- fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
-
- //const uint16_t n_RB_DLBWP = dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP; //make sure this has been set
- const uint16_t n_RB_DLBWP = mac->initial_bwp_dl.N_RB;
- const uint16_t n_RB_ULBWP = mac->initial_bwp_ul.N_RB;
+ LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
+ dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits);
- LOG_I(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP);
+ nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15);
+ nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format);
+}
- switch(dci_format){
- case format0_0:
-/*
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 32 TPC_PUSCH:
- * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
- * 50 SUL_IND_0_0:
- */
- ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
- /* IDENTIFIER_DCI_FORMATS */
- /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
- nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
- /* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
- /* FREQ_HOPPING_FLAG */
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
- ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
- /* MCS */
- ulsch_config_pdu_0_0->mcs = dci->mcs;
- /* NDI */
- ulsch_config_pdu_0_0->ndi = dci->ndi;
- /* RV */
- ulsch_config_pdu_0_0->rv = dci->rv;
- /* HARQ_PROCESS_NUMBER */
- ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number;
- /* TPC_PUSCH */
- // according to TS 38.213 Table Table 7.1.1-1
- if (dci->tpc_pusch == 0) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4;
- }
- if (dci->tpc_pusch == 1) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1;
- }
- if (dci->tpc_pusch == 2) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1;
- }
- if (dci->tpc_pusch == 3) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4;
- }
- /* SUL_IND_0_0 */ // To be implemented, FIXME!!!
-
- ul_config->number_pdus = ul_config->number_pdus + 1;
- break;
-
- case format0_1:
-/*
- * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 1 CARRIER_IND
- * 2 SUL_IND_0_1
- * 7 BANDWIDTH_PART_IND
- * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 29 FIRST_DAI
- * 30 SECOND_DAI
- * 32 TPC_PUSCH:
- * 36 SRS_RESOURCE_IND:
- * 37 PRECOD_NBR_LAYERS:
- * 38 ANTENNA_PORTS:
- * 40 SRS_REQUEST:
- * 42 CSI_REQUEST:
- * 43 CBGTI
- * 45 PTRS_DMRS
- * 46 BETA_OFFSET_IND
- * 47 DMRS_SEQ_INI
- * 48 UL_SCH_IND
- * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
- */
- ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
- /* IDENTIFIER_DCI_FORMATS */
- /* CARRIER_IND */
- /* SUL_IND_0_1 */
- /* BANDWIDTH_PART_IND */
- ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind;
- /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
- nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
- /* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
- /* FREQ_HOPPING_FLAG */
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
- ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
- /* MCS */
- ulsch_config_pdu_0_1->mcs = dci->mcs;
- /* NDI */
- ulsch_config_pdu_0_1->ndi = dci->ndi;
- /* RV */
- ulsch_config_pdu_0_1->rv = dci->rv;
- /* HARQ_PROCESS_NUMBER */
- ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number;
- /* FIRST_DAI */ //To be implemented, FIXME!!!
- /* SECOND_DAI */ //To be implemented, FIXME!!!
- /* TPC_PUSCH */
- // according to TS 38.213 Table Table 7.1.1-1
- if (dci->tpc_pusch == 0) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4;
- }
- if (dci->tpc_pusch == 1) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1;
- }
- if (dci->tpc_pusch == 2) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1;
- }
- if (dci->tpc_pusch == 3) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4;
- }
- /* SRS_RESOURCE_IND */
- //FIXME!!
- /* PRECOD_NBR_LAYERS */
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_nonCodebook));
- // 0 bits if the higher layer parameter txConfig = nonCodeBook
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_codebook)){
- uint8_t n_antenna_port = 0; //FIXME!!!
- if (n_antenna_port == 1); // 1 antenna port and the higher layer parameter txConfig = codebook 0 bits
- if (n_antenna_port == 4){ // 4 antenna port and the higher layer parameter txConfig = codebook
- // Table 7.3.1.1.2-2: transformPrecoder=disabled and maxRank = 2 or 3 or 4
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
- && ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2) ||
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) ||
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5];
- }
- }
- // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1
- if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
- || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
- && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11];
- }
- }
- }
- if (n_antenna_port == 4){ // 2 antenna port and the higher layer parameter txConfig = codebook
- // Table 7.3.1.1.2-4: transformPrecoder=disabled and maxRank = 2
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
- && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15];
- }
- }
- // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1
- if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
- || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
- && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17];
- }
- if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19];
- }
- }
- }
- }
- /* ANTENNA_PORTS */
- uint8_t rank=0; // We need to initialize rank FIXME!!!
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports;
- }
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports);
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
- }
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11
- if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports);
- }
- if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1;
- }
- if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
- }
- if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
- ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
- }
- }
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15
- if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1;
- }
- if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
- }
- if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
- }
- if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
- }
- }
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19
- if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
- }
- if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2];
- }
- if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3];
- }
- if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
- ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
- }
- }
- if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23
- if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2];
- }
- if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3];
- }
- if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4];
- }
- if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5];
- }
- }
- /* SRS_REQUEST */
- // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
- ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
- /* CSI_REQUEST */
- ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request;
- /* CBGTI */
- ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti;
- /* PTRS_DMRS */
- if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) ||
- ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
- (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){
- } else {
- ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs;
- }
- /* BETA_OFFSET_IND */
- // Table 9.3-3 in [5, TS 38.213]
- ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind;
- /* DMRS_SEQ_INI */
- // FIXME!!
- /* UL_SCH_IND */
- // A value of "1" indicates UL-SCH shall be transmitted on the PUSCH and
- // a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
-
- ul_config->number_pdus = ul_config->number_pdus + 1;
- break;
-
- case format1_0:
-/*
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- * 34 PUCCH_RESOURCE_IND:
- * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- * 55 RESERVED_NR_DCI
- * with CRC scrambled by P-RNTI
- * 8 SHORT_MESSAGE_IND
- * 9 SHORT_MESSAGES
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 31 TB_SCALING
- * 55 RESERVED_NR_DCI
- * with CRC scrambled by SI-RNTI
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 26 RV:
- * 55 RESERVED_NR_DCI
- * with CRC scrambled by RA-RNTI
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 31 TB_SCALING
- * 55 RESERVED_NR_DCI
- * with CRC scrambled by TC-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 24 MCS:
- * 25 NDI:
- * 26 RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- */
- dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
- //fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_pdu_1_0 = dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
- /* IDENTIFIER_DCI_FORMATS */
- /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
- nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
- /* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
- /* VRB_TO_PRB_MAPPING */
- dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
- /* MCS */
- dlsch_config_pdu_1_0->mcs = dci->mcs;
- /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->ndi = dci->ndi;
- /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->rv = dci->rv;
- /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number;
- /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->dai = dci ->dai;
- /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */
- // according to TS 38.214 Table 5.1.3.2-3
- if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1;
- if (dci->tb_scaling == 1) dlsch_config_pdu_1_0->scaling_factor_S = 0.5;
- if (dci->tb_scaling == 2) dlsch_config_pdu_1_0->scaling_factor_S = 0.25;
- if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table
- /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- // according to TS 38.213 Table 7.2.1-1
- if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1;
- if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0;
- if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1;
- if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3;
- /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
- //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
- //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
- dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind;
- /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
- dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind;
-
- LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n",
- dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti,
- dl_config->number_pdus);
- LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n",
- dci->freq_dom_resource_assignment_DL,
- dlsch_config_pdu_1_0->number_rbs,
- dlsch_config_pdu_1_0->start_rb);
- LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n",
- dci->time_dom_resource_assignment,
- dlsch_config_pdu_1_0->number_symbols,
- dlsch_config_pdu_1_0->start_symbol);
- LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n",
- dlsch_config_pdu_1_0->vrb_to_prb_mapping,
- dlsch_config_pdu_1_0->mcs,
- dlsch_config_pdu_1_0->ndi,
- dlsch_config_pdu_1_0->rv,
- dlsch_config_pdu_1_0->harq_process_nbr,
- dlsch_config_pdu_1_0->dai,
- dlsch_config_pdu_1_0->scaling_factor_S,
- dlsch_config_pdu_1_0->accumulated_delta_PUCCH,
- dlsch_config_pdu_1_0->pucch_resource_id,
- dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind);
-
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
+int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
+ fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
+
+ //const uint16_t n_RB_DLBWP = dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP; //make sure this has been set
+ AssertFatal(mac->DLbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n");
+ AssertFatal(mac->ULbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n");
+
+ const uint16_t n_RB_DLBWP = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+ const uint16_t n_RB_ULBWP = NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+
+ LOG_D(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP);
+
+ NR_PDSCH_Config_t *pdsch_config=mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup;
+
+ switch(dci_format){
+ case NR_UL_DCI_FORMAT_0_0:
+ /*
+ * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI
+ * 0 IDENTIFIER_DCI_FORMATS:
+ * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 25 NDI:
+ * 26 RV:
+ * 27 HARQ_PROCESS_NUMBER:
+ * 32 TPC_PUSCH:
+ * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
+ * 50 SUL_IND_0_0:
+ */
+ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
+ fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
+ /* IDENTIFIER_DCI_FORMATS */
+ /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
+ nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
+ /* TIME_DOM_RESOURCE_ASSIGNMENT */
+ nr_ue_process_dci_time_dom_resource_assignment(mac,
+ ulsch_config_pdu_0_0,NULL,
+ dci->time_dom_resource_assignment);
+
+ /* FREQ_HOPPING_FLAG */
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
+ ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
+ /* MCS */
+ ulsch_config_pdu_0_0->mcs = dci->mcs;
+ /* NDI */
+ ulsch_config_pdu_0_0->ndi = dci->ndi;
+ /* RV */
+ ulsch_config_pdu_0_0->rv = dci->rv;
+ /* HARQ_PROCESS_NUMBER */
+ ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number;
+ /* TPC_PUSCH */
+ // according to TS 38.213 Table Table 7.1.1-1
+ if (dci->tpc_pusch == 0) {
+ ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1;
+ ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4;
+ }
+ if (dci->tpc_pusch == 1) {
+ ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0;
+ ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1;
+ }
+ if (dci->tpc_pusch == 2) {
+ ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1;
+ ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1;
+ }
+ if (dci->tpc_pusch == 3) {
+ ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3;
+ ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4;
+ }
+ /* SUL_IND_0_0 */ // To be implemented, FIXME!!!
+
+ ul_config->number_pdus = ul_config->number_pdus + 1;
+ break;
+
+ case NR_UL_DCI_FORMAT_0_1:
+ /*
+ * with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI
+ * 0 IDENTIFIER_DCI_FORMATS:
+ * 1 CARRIER_IND
+ * 2 SUL_IND_0_1
+ * 7 BANDWIDTH_PART_IND
+ * 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 25 NDI:
+ * 26 RV:
+ * 27 HARQ_PROCESS_NUMBER:
+ * 29 FIRST_DAI
+ * 30 SECOND_DAI
+ * 32 TPC_PUSCH:
+ * 36 SRS_RESOURCE_IND:
+ * 37 PRECOD_NBR_LAYERS:
+ * 38 ANTENNA_PORTS:
+ * 40 SRS_REQUEST:
+ * 42 CSI_REQUEST:
+ * 43 CBGTI
+ * 45 PTRS_DMRS
+ * 46 BETA_OFFSET_IND
+ * 47 DMRS_SEQ_INI
+ * 48 UL_SCH_IND
+ * 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
+ */
+ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
+ ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
+ fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
+ /* IDENTIFIER_DCI_FORMATS */
+ /* CARRIER_IND */
+ /* SUL_IND_0_1 */
+ /* BANDWIDTH_PART_IND */
+ ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind;
+ /* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
+ nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
+ /* TIME_DOM_RESOURCE_ASSIGNMENT */
+ nr_ue_process_dci_time_dom_resource_assignment(mac,ulsch_config_pdu_0_1,NULL,
+ dci->time_dom_resource_assignment);
+ /* FREQ_HOPPING_FLAG */
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
+ ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
+ /* MCS */
+ ulsch_config_pdu_0_1->mcs = dci->mcs;
+ /* NDI */
+ ulsch_config_pdu_0_1->ndi = dci->ndi;
+ /* RV */
+ ulsch_config_pdu_0_1->rv = dci->rv;
+ /* HARQ_PROCESS_NUMBER */
+ ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number;
+ /* FIRST_DAI */ //To be implemented, FIXME!!!
+ /* SECOND_DAI */ //To be implemented, FIXME!!!
+ /* TPC_PUSCH */
+ // according to TS 38.213 Table Table 7.1.1-1
+ if (dci->tpc_pusch == 0) {
+ ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1;
+ ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4;
+ }
+ if (dci->tpc_pusch == 1) {
+ ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0;
+ ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1;
+ }
+ if (dci->tpc_pusch == 2) {
+ ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1;
+ ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1;
+ }
+ if (dci->tpc_pusch == 3) {
+ ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3;
+ ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4;
+ }
+ /* SRS_RESOURCE_IND */
+ //FIXME!!
+ /* PRECOD_NBR_LAYERS */
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_nonCodebook));
+ // 0 bits if the higher layer parameter txConfig = nonCodeBook
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.tx_config == tx_config_codebook)){
+ uint8_t n_antenna_port = 0; //FIXME!!!
+ if (n_antenna_port == 1); // 1 antenna port and the higher layer parameter txConfig = codebook 0 bits
+ if (n_antenna_port == 4){ // 4 antenna port and the higher layer parameter txConfig = codebook
+ // Table 7.3.1.1.2-2: transformPrecoder=disabled and maxRank = 2 or 3 or 4
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
+ && ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2) ||
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) ||
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5];
+ }
+ }
+ // Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1
+ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
+ || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
+ && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11];
+ }
+ }
+ }
+ if (n_antenna_port == 4){ // 2 antenna port and the higher layer parameter txConfig = codebook
+ // Table 7.3.1.1.2-4: transformPrecoder=disabled and maxRank = 2
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
+ && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15];
+ }
+ }
+ // Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1
+ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled)
+ || (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
+ && (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17];
+ }
+ if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
+ ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18];
+ ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19];
+ }
+ }
+ }
+ }
+ /* ANTENNA_PORTS */
+ uint8_t rank=0; // We need to initialize rank FIXME!!!
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports;
+ }
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports);
+ ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
+ }
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11
+ if (rank == 1){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports);
+ }
+ if (rank == 2){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0;
+ ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1;
+ }
+ if (rank == 3){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
+ ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
+ ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
+ }
+ if (rank == 4){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
+ ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
+ ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
+ }
+ }
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15
+ if (rank == 1){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
+ ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1;
+ }
+ if (rank == 2){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
+ }
+ if (rank == 3){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3];
+ ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
+ }
+ if (rank == 4){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3];
+ ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4];
+ ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
+ }
+ }
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19
+ if (rank == 1){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
+ }
+ if (rank == 2){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2];
+ }
+ if (rank == 3){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3];
+ }
+ if (rank == 4){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2;
+ ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
+ ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
+ ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
+ ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
+ }
+ }
+ if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23
+ if (rank == 1){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0];
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2];
+ }
+ if (rank == 2){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0];
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3];
+ }
+ if (rank == 3){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0];
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3];
+ ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4];
+ }
+ if (rank == 4){
+ ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0];
+ ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1];
+ ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2];
+ ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3];
+ ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4];
+ ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5];
+ }
+ }
+ /* SRS_REQUEST */
+ // if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
+ ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
+ /* CSI_REQUEST */
+ ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request;
+ /* CBGTI */
+ ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti;
+ /* PTRS_DMRS */
+ if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) ||
+ ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
+ (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){
+ } else {
+ ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs;
+ }
+ /* BETA_OFFSET_IND */
+ // Table 9.3-3 in [5, TS 38.213]
+ ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind;
+ /* DMRS_SEQ_INI */
+ // FIXME!!
+ /* UL_SCH_IND */
+ // A value of "1" indicates UL-SCH shall be transmitted on the PUSCH and
+ // a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
+
+ ul_config->number_pdus = ul_config->number_pdus + 1;
+ break;
+
+ case NR_DL_DCI_FORMAT_1_0:
+ /*
+ * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
+ * 0 IDENTIFIER_DCI_FORMATS:
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 25 NDI:
+ * 26 RV:
+ * 27 HARQ_PROCESS_NUMBER:
+ * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
+ * 33 TPC_PUCCH:
+ * 34 PUCCH_RESOURCE_IND:
+ * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
+ * 55 RESERVED_NR_DCI
+ * with CRC scrambled by P-RNTI
+ * 8 SHORT_MESSAGE_IND
+ * 9 SHORT_MESSAGES
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 31 TB_SCALING
+ * 55 RESERVED_NR_DCI
+ * with CRC scrambled by SI-RNTI
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 26 RV:
+ * 55 RESERVED_NR_DCI
+ * with CRC scrambled by RA-RNTI
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 31 TB_SCALING
+ * 55 RESERVED_NR_DCI
+ * with CRC scrambled by TC-RNTI
+ * 0 IDENTIFIER_DCI_FORMATS:
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 24 MCS:
+ * 25 NDI:
+ * 26 RV:
+ * 27 HARQ_PROCESS_NUMBER:
+ * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
+ * 33 TPC_PUCCH:
+ */
+
+ dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
+ //fapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_config_pdu_1_0 = dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
+ fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
+ dlsch_config_pdu_1_0->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+ dlsch_config_pdu_1_0->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+ dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing;
+ /* IDENTIFIER_DCI_FORMATS */
+ /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
+ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
+ /* TIME_DOM_RESOURCE_ASSIGNMENT */
+ nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0,
+ dci->time_dom_resource_assignment);
+
+ /* dmrs symbol positions*/
+ dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config,
+ mac->scc->dmrs_TypeA_Position,
+ dlsch_config_pdu_1_0->number_symbols);
+ dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2;
+ /* VRB_TO_PRB_MAPPING */
+ dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
+ /* MCS */
+ dlsch_config_pdu_1_0->mcs = dci->mcs;
+ /* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
+ dlsch_config_pdu_1_0->ndi = dci->ndi;
+ /* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
+ dlsch_config_pdu_1_0->rv = dci->rv;
+ /* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
+ dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number;
+ /* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
+ dlsch_config_pdu_1_0->dai = dci ->dai;
+ /* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */
+ // according to TS 38.214 Table 5.1.3.2-3
+ if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1;
+ if (dci->tb_scaling == 1) dlsch_config_pdu_1_0->scaling_factor_S = 0.5;
+ if (dci->tb_scaling == 2) dlsch_config_pdu_1_0->scaling_factor_S = 0.25;
+ if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table
+ /* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
+ // according to TS 38.213 Table 7.2.1-1
+ if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1;
+ if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0;
+ if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1;
+ if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3;
+ /* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
+ //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
+ //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
+ //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
+ dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind;
+ /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
+ dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind;
+
+ LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n",
+ dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti,
+ dl_config->number_pdus);
+ LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n",
+ dci->freq_dom_resource_assignment_DL,
+ dlsch_config_pdu_1_0->number_rbs,
+ dlsch_config_pdu_1_0->start_rb);
+ LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n",
+ dci->time_dom_resource_assignment,
+ dlsch_config_pdu_1_0->number_symbols,
+ dlsch_config_pdu_1_0->start_symbol);
+ LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n",
+ dlsch_config_pdu_1_0->vrb_to_prb_mapping,
+ dlsch_config_pdu_1_0->mcs,
+ dlsch_config_pdu_1_0->ndi,
+ dlsch_config_pdu_1_0->rv,
+ dlsch_config_pdu_1_0->harq_process_nbr,
+ dlsch_config_pdu_1_0->dai,
+ dlsch_config_pdu_1_0->scaling_factor_S,
+ dlsch_config_pdu_1_0->accumulated_delta_PUCCH,
+ dlsch_config_pdu_1_0->pucch_resource_id,
+ dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind);
+
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
+ // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
- LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
+ LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
- dl_config->number_pdus = dl_config->number_pdus + 1;
- break;
-
- case format1_1:
-/*
- * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
- * 0 IDENTIFIER_DCI_FORMATS:
- * 1 CARRIER_IND:
- * 7 BANDWIDTH_PART_IND:
- * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
- * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
- * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
- * 14 PRB_BUNDLING_SIZE_IND:
- * 15 RATE_MATCHING_IND:
- * 16 ZP_CSI_RS_TRIGGER:
- * 18 TB1_MCS:
- * 19 TB1_NDI:
- * 20 TB1_RV:
- * 21 TB2_MCS:
- * 22 TB2_NDI:
- * 23 TB2_RV:
- * 27 HARQ_PROCESS_NUMBER:
- * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
- * 33 TPC_PUCCH:
- * 34 PUCCH_RESOURCE_IND:
- * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
- * 38 ANTENNA_PORTS:
- * 39 TCI:
- * 40 SRS_REQUEST:
- * 43 CBGTI:
- * 44 CBGFI:
- * 47 DMRS_SEQ_INI:
- */
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
- dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_1 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
- /* IDENTIFIER_DCI_FORMATS */
- /* CARRIER_IND */
- /* BANDWIDTH_PART_IND */
- dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind;
- /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
- nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
- /* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,dci->time_dom_resource_assignment,mac->mib->dmrs_TypeA_Position);
- /* VRB_TO_PRB_MAPPING */
- if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0)
- dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
- /* PRB_BUNDLING_SIZE_IND */
- dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind;
- /* RATE_MATCHING_IND */
- dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind;
- /* ZP_CSI_RS_TRIGGER */
- dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger;
- /* MCS (for transport block 1)*/
- dlsch_config_pdu_1_1->mcs = dci->tb1_mcs;
- /* NDI (for transport block 1)*/
- dlsch_config_pdu_1_1->ndi = dci->tb1_ndi;
- /* RV (for transport block 1)*/
- dlsch_config_pdu_1_1->rv = dci->tb1_rv;
- /* MCS (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs;
- /* NDI (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi;
- /* RV (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv;
- /* HARQ_PROCESS_NUMBER */
- dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number;
- /* DAI */
- dlsch_config_pdu_1_1->dai = dci ->dai;
- /* TPC_PUCCH */
- // according to TS 38.213 Table 7.2.1-1
- if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1;
- if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0;
- if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1;
- if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3;
- /* PUCCH_RESOURCE_IND */
- if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
- if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
- /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */
- // according to TS 38.213 Table 9.2.3-1
- dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind];
- /* ANTENNA_PORTS */
- uint8_t n_codewords = 1; // FIXME!!!
- if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
- // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4];
- }
- if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
- (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
- // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5];
- }
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6];
- dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7];
- dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9];
- }
- }
- if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
- (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
- // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4];
- }
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6];
- }
- }
- if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
- (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
- // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5];
- }
- if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6];
- dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7];
- dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9];
- }
- }
- /* TCI */
- if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){
- // 0 bit if higher layer parameter tci-PresentInDCI is not enabled
- // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214]
- dlsch_config_pdu_1_1->tci_state = dci->tci;
- }
- /* SRS_REQUEST */
- // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
- dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
- /* CBGTI */
- dlsch_config_pdu_1_1->cbgti = dci->cbgti;
- /* CBGFI */
- dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi;
- /* DMRS_SEQ_INI */
- //FIXME!!!
-
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
+ dl_config->number_pdus = dl_config->number_pdus + 1;
+ break;
+
+ case NR_DL_DCI_FORMAT_1_1:
+ /*
+ * with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
+ * 0 IDENTIFIER_DCI_FORMATS:
+ * 1 CARRIER_IND:
+ * 7 BANDWIDTH_PART_IND:
+ * 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
+ * 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
+ * 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
+ * 14 PRB_BUNDLING_SIZE_IND:
+ * 15 RATE_MATCHING_IND:
+ * 16 ZP_CSI_RS_TRIGGER:
+ * 18 TB1_MCS:
+ * 19 TB1_NDI:
+ * 20 TB1_RV:
+ * 21 TB2_MCS:
+ * 22 TB2_NDI:
+ * 23 TB2_RV:
+ * 27 HARQ_PROCESS_NUMBER:
+ * 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
+ * 33 TPC_PUCCH:
+ * 34 PUCCH_RESOURCE_IND:
+ * 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
+ * 38 ANTENNA_PORTS:
+ * 39 TCI:
+ * 40 SRS_REQUEST:
+ * 43 CBGTI:
+ * 44 CBGFI:
+ * 47 DMRS_SEQ_INI:
+ */
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
+ dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti;
+ fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_1 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
+ /* IDENTIFIER_DCI_FORMATS */
+ /* CARRIER_IND */
+ /* BANDWIDTH_PART_IND */
+ // dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind;
+ /* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
+ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
+ /* TIME_DOM_RESOURCE_ASSIGNMENT */
+ nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1,
+ dci->time_dom_resource_assignment);
+ /* VRB_TO_PRB_MAPPING */
+ if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0)
+ dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
+ /* PRB_BUNDLING_SIZE_IND */
+ dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind;
+ /* RATE_MATCHING_IND */
+ dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind;
+ /* ZP_CSI_RS_TRIGGER */
+ dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger;
+ /* MCS (for transport block 1)*/
+ dlsch_config_pdu_1_1->mcs = dci->tb1_mcs;
+ /* NDI (for transport block 1)*/
+ dlsch_config_pdu_1_1->ndi = dci->tb1_ndi;
+ /* RV (for transport block 1)*/
+ dlsch_config_pdu_1_1->rv = dci->tb1_rv;
+ /* MCS (for transport block 2)*/
+ dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs;
+ /* NDI (for transport block 2)*/
+ dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi;
+ /* RV (for transport block 2)*/
+ dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv;
+ /* HARQ_PROCESS_NUMBER */
+ dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number;
+ /* DAI */
+ dlsch_config_pdu_1_1->dai = dci ->dai;
+ /* TPC_PUCCH */
+ // according to TS 38.213 Table 7.2.1-1
+ if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1;
+ if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0;
+ if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1;
+ if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3;
+ /* PUCCH_RESOURCE_IND */
+ if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
+ if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
+ if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
+ /* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */
+ // according to TS 38.213 Table 9.2.3-1
+ dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind];
+ /* ANTENNA_PORTS */
+ uint8_t n_codewords = 1; // FIXME!!!
+ if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
+ // Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4];
+ }
+ if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
+ (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
+ // Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5];
+ }
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6];
+ dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7];
+ dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9];
+ }
+ }
+ if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
+ (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
+ // Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4];
+ }
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6];
+ }
+ }
+ if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
+ (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
+ // Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5];
+ }
+ if (n_codewords == 1) {
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6];
+ dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7];
+ dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9];
+ }
+ }
+ /* TCI */
+ if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){
+ // 0 bit if higher layer parameter tci-PresentInDCI is not enabled
+ // otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214]
+ dlsch_config_pdu_1_1->tci_state = dci->tci;
+ }
+ /* SRS_REQUEST */
+ // if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
+ dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
+ /* CBGTI */
+ dlsch_config_pdu_1_1->cbgti = dci->cbgti;
+ /* CBGFI */
+ dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi;
+ /* DMRS_SEQ_INI */
+ //FIXME!!!
+
+ // dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
- LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
+ LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
- dl_config->number_pdus = dl_config->number_pdus + 1;
+ dl_config->number_pdus = dl_config->number_pdus + 1;
- break;
+ break;
- case format2_0:
- break;
+ case NR_DL_DCI_FORMAT_2_0:
+ break;
- case format2_1:
- break;
+ case NR_DL_DCI_FORMAT_2_1:
+ break;
- case format2_2:
- break;
+ case NR_DL_DCI_FORMAT_2_2:
+ break;
- case format2_3:
- break;
+ case NR_DL_DCI_FORMAT_2_3:
+ break;
- default:
- break;
- }
+ default:
+ break;
+ }
- if(rnti == SI_RNTI){
+ if(rnti == SI_RNTI){
- }else if(rnti == mac->ra_rnti){
+ // }else if(rnti == mac->ra_rnti){
- }else if(rnti == P_RNTI){
+ }else if(rnti == P_RNTI){
- }else{ // c-rnti
+ }else{ // c-rnti
- /// check if this is pdcch order
- //dci->random_access_preamble_index;
- //dci->ss_pbch_index;
- //dci->prach_mask_index;
+ /// check if this is pdcch order
+ //dci->random_access_preamble_index;
+ //dci->ss_pbch_index;
+ //dci->prach_mask_index;
- /// else normal DL-SCH grant
- }
- return 0;
+ /// else normal DL-SCH grant
+ }
+ return 0;
}
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){
- return 0;
+ return 0;
}
void nr_ue_process_mac_pdu(
- module_id_t module_idP,
- uint8_t CC_id,
- uint8_t *pduP,
- uint16_t mac_pdu_len,
- uint8_t eNB_index){
-
- uint8_t *pdu_ptr = pduP;
- uint16_t pdu_len = mac_pdu_len;
-
- uint16_t mac_ce_len;
- uint16_t mac_subheader_len;
- uint16_t mac_sdu_len;
-
- // For both DL/UL-SCH
- // Except:
- // - UL/DL-SCH: fixed-size MAC CE(known by LCID)
- // - UL/DL-SCH: padding
- // - UL-SCH: MSG3 48-bits
- // |0|1|2|3|4|5|6|7| bit-wise
- // |R|F| LCID |
- // | L |
- // |0|1|2|3|4|5|6|7| bit-wise
- // |R|F| LCID |
- // | L |
- // | L |
-
- // For both DL/UL-SCH
- // For:
- // - UL/DL-SCH: fixed-size MAC CE(known by LCID)
- // - UL/DL-SCH: padding, for single/multiple 1-oct padding CE(s)
- // - UL-SCH: MSG3 48-bits
- // |0|1|2|3|4|5|6|7| bit-wise
- // |R|R| LCID |
- // LCID: The Logical Channel ID field identifies the logical channel instance of the corresponding MAC SDU or the type of the corresponding MAC CE or padding as described in Tables 6.2.1-1 and 6.2.1-2 for the DL-SCH and UL-SCH respectively. There is one LCID field per MAC subheader. The LCID field size is 6 bits;
- // L: The Length field indicates the length of the corresponding MAC SDU or variable-sized MAC CE in bytes. There is one L field per MAC subheader except for subheaders corresponding to fixed-sized MAC CEs and padding. The size of the L field is indicated by the F field;
- // F: lenght of L is 0:8 or 1:16 bits wide
- // R: Reserved bit, set to zero.
-
- uint8_t done = 0;
+ module_id_t module_idP,
+ uint8_t CC_id,
+ uint8_t *pduP,
+ uint16_t mac_pdu_len,
+ uint8_t eNB_index){
+
+ uint8_t *pdu_ptr = pduP;
+ uint16_t pdu_len = mac_pdu_len;
+
+ uint16_t mac_ce_len;
+ uint16_t mac_subheader_len;
+ uint16_t mac_sdu_len;
+
+ // For both DL/UL-SCH
+ // Except:
+ // - UL/DL-SCH: fixed-size MAC CE(known by LCID)
+ // - UL/DL-SCH: padding
+ // - UL-SCH: MSG3 48-bits
+ // |0|1|2|3|4|5|6|7| bit-wise
+ // |R|F| LCID |
+ // | L |
+ // |0|1|2|3|4|5|6|7| bit-wise
+ // |R|F| LCID |
+ // | L |
+ // | L |
+
+ // For both DL/UL-SCH
+ // For:
+ // - UL/DL-SCH: fixed-size MAC CE(known by LCID)
+ // - UL/DL-SCH: padding, for single/multiple 1-oct padding CE(s)
+ // - UL-SCH: MSG3 48-bits
+ // |0|1|2|3|4|5|6|7| bit-wise
+ // |R|R| LCID |
+ // LCID: The Logical Channel ID field identifies the logical channel instance of the corresponding MAC SDU or the type of the corresponding MAC CE or padding as described in Tables 6.2.1-1 and 6.2.1-2 for the DL-SCH and UL-SCH respectively. There is one LCID field per MAC subheader. The LCID field size is 6 bits;
+ // L: The Length field indicates the length of the corresponding MAC SDU or variable-sized MAC CE in bytes. There is one L field per MAC subheader except for subheaders corresponding to fixed-sized MAC CEs and padding. The size of the L field is indicated by the F field;
+ // F: lenght of L is 0:8 or 1:16 bits wide
+ // R: Reserved bit, set to zero.
+
+ uint8_t done = 0;
- while (!done || pdu_len <= 0){
- mac_ce_len = 0x0000;
- mac_subheader_len = 0x0001; // default to fixed-length subheader = 1-oct
- mac_sdu_len = 0x0000;
- switch(((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID){
- // MAC CE
- case DL_SCH_LCID_CCCH:
- // MSG4 RRC Connection Setup 38.331
- // varialbe length
- mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- break;
- case DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH:
- // 38.321 Ch6.1.3.14
- // varialbe length
- mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- break;
- case DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL:
- // 38.321 Ch6.1.3.13
- // varialbe length
- mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- break;
- case DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT:
- // 38.321 Ch6.1.3.12
- // varialbe length
- mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- break;
- case DL_SCH_LCID_SP_SRS_ACTIVATION:
- // 38.321 Ch6.1.3.17
- // varialbe length
- mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- break;
+ while (!done || pdu_len <= 0){
+ mac_ce_len = 0x0000;
+ mac_subheader_len = 0x0001; // default to fixed-length subheader = 1-oct
+ mac_sdu_len = 0x0000;
+ switch(((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID){
+ // MAC CE
+ case DL_SCH_LCID_CCCH:
+ // MSG4 RRC Connection Setup 38.331
+ // varialbe length
+ mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ break;
+ case DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH:
+ // 38.321 Ch6.1.3.14
+ // varialbe length
+ mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ break;
+ case DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL:
+ // 38.321 Ch6.1.3.13
+ // varialbe length
+ mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ break;
+ case DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT:
+ // 38.321 Ch6.1.3.12
+ // varialbe length
+ mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ break;
+ case DL_SCH_LCID_SP_SRS_ACTIVATION:
+ // 38.321 Ch6.1.3.17
+ // varialbe length
+ mac_ce_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_ce_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ break;
- case DL_SCH_LCID_RECOMMENDED_BITRATE:
- // 38.321 Ch6.1.3.20
- mac_ce_len = 2;
- break;
- case DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT:
- // 38.321 Ch6.1.3.19
- mac_ce_len = 2;
- break;
- case DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT:
- // 38.321 Ch6.1.3.18
- mac_ce_len = 3;
- break;
- case DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT:
- // 38.321 Ch6.1.3.16
- mac_ce_len = 2;
- break;
- case DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH:
- // 38.321 Ch6.1.3.15
- mac_ce_len = 2;
- break;
- case DL_SCH_LCID_DUPLICATION_ACT:
- // 38.321 Ch6.1.3.11
- mac_ce_len = 1;
- break;
- case DL_SCH_LCID_SCell_ACT_4_OCT:
- // 38.321 Ch6.1.3.10
- mac_ce_len = 4;
- break;
- case DL_SCH_LCID_SCell_ACT_1_OCT:
- // 38.321 Ch6.1.3.10
- mac_ce_len = 1;
- break;
- case DL_SCH_LCID_L_DRX:
- // 38.321 Ch6.1.3.6
- // fixed length but not yet specify.
- mac_ce_len = 0;
- break;
- case DL_SCH_LCID_DRX:
- // 38.321 Ch6.1.3.5
- // fixed length but not yet specify.
- mac_ce_len = 0;
- break;
- case DL_SCH_LCID_TA_COMMAND:
- // 38.321 Ch6.1.3.4
- mac_ce_len = 1;
- break;
- case DL_SCH_LCID_CON_RES_ID:
- // 38.321 Ch6.1.3.3
- mac_ce_len = 6;
- break;
- case DL_SCH_LCID_PADDING:
- done = 1;
- // end of MAC PDU, can ignore the rest.
- break;
-
- // MAC SDU
- case DL_SCH_LCID_SRB1:
- // check if LCID is valid at current time.
- case UL_SCH_LCID_SRB2:
- // check if LCID is valid at current time.
- case UL_SCH_LCID_SRB3:
- // check if LCID is valid at current time.
- default:
- // check if LCID is valid at current time.
- mac_sdu_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
- mac_subheader_len = 2;
- if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
- mac_sdu_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
- mac_subheader_len = 3;
- }
- // DRB LCID by RRC
- break;
- }
- pdu_ptr += ( mac_subheader_len + mac_ce_len + mac_sdu_len );
- pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len );
- AssertFatal(pdu_len >= 0, "[MAC] nr_ue_process_mac_pdu, residual mac pdu length < 0!\n");
+ case DL_SCH_LCID_RECOMMENDED_BITRATE:
+ // 38.321 Ch6.1.3.20
+ mac_ce_len = 2;
+ break;
+ case DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT:
+ // 38.321 Ch6.1.3.19
+ mac_ce_len = 2;
+ break;
+ case DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT:
+ // 38.321 Ch6.1.3.18
+ mac_ce_len = 3;
+ break;
+ case DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT:
+ // 38.321 Ch6.1.3.16
+ mac_ce_len = 2;
+ break;
+ case DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH:
+ // 38.321 Ch6.1.3.15
+ mac_ce_len = 2;
+ break;
+ case DL_SCH_LCID_DUPLICATION_ACT:
+ // 38.321 Ch6.1.3.11
+ mac_ce_len = 1;
+ break;
+ case DL_SCH_LCID_SCell_ACT_4_OCT:
+ // 38.321 Ch6.1.3.10
+ mac_ce_len = 4;
+ break;
+ case DL_SCH_LCID_SCell_ACT_1_OCT:
+ // 38.321 Ch6.1.3.10
+ mac_ce_len = 1;
+ break;
+ case DL_SCH_LCID_L_DRX:
+ // 38.321 Ch6.1.3.6
+ // fixed length but not yet specify.
+ mac_ce_len = 0;
+ break;
+ case DL_SCH_LCID_DRX:
+ // 38.321 Ch6.1.3.5
+ // fixed length but not yet specify.
+ mac_ce_len = 0;
+ break;
+ case DL_SCH_LCID_TA_COMMAND:
+ // 38.321 Ch6.1.3.4
+ mac_ce_len = 1;
+ break;
+ case DL_SCH_LCID_CON_RES_ID:
+ // 38.321 Ch6.1.3.3
+ mac_ce_len = 6;
+ break;
+ case DL_SCH_LCID_PADDING:
+ done = 1;
+ // end of MAC PDU, can ignore the rest.
+ break;
+
+ // MAC SDU
+ case DL_SCH_LCID_SRB1:
+ // check if LCID is valid at current time.
+ case UL_SCH_LCID_SRB2:
+ // check if LCID is valid at current time.
+ case UL_SCH_LCID_SRB3:
+ // check if LCID is valid at current time.
+ default:
+ // check if LCID is valid at current time.
+ mac_sdu_len |= (uint16_t)((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->L;
+ mac_subheader_len = 2;
+ if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
+ mac_sdu_len |= (uint16_t)(((NR_MAC_SUBHEADER_LONG *)pdu_ptr)->L2)<<8;
+ mac_subheader_len = 3;
+ }
+ // DRB LCID by RRC
+ break;
}
+ pdu_ptr += ( mac_subheader_len + mac_ce_len + mac_sdu_len );
+ pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len );
+ AssertFatal(pdu_len >= 0, "[MAC] nr_ue_process_mac_pdu, residual mac pdu length < 0!\n");
+ }
}
//---------------------------------------------------------------------------------
@@ -2218,201 +2858,550 @@ unsigned char *parse_header(unsigned char *mac_header,
unsigned short tb_length)
{
- unsigned char not_done = 1, num_ces = 0, num_cont_res =
- 0, num_padding = 0, num_sdus = 0, lcid, num_sdu_cnt;
- unsigned char *mac_header_ptr = mac_header;
- unsigned short length, ce_len = 0;
+ unsigned char not_done = 1, num_ces = 0, num_cont_res =
+ 0, num_padding = 0, num_sdus = 0, lcid, num_sdu_cnt;
+ unsigned char *mac_header_ptr = mac_header;
+ unsigned short length, ce_len = 0;
- while (not_done == 1) {
+ while (not_done == 1) {
- if (((SCH_SUBHEADER_FIXED *) mac_header_ptr)->E == 0) {
- // printf("E=0\n");
- not_done = 0;
- }
+ if (((SCH_SUBHEADER_FIXED *) mac_header_ptr)->E == 0) {
+ // printf("E=0\n");
+ not_done = 0;
+ }
+
+ lcid = ((SCH_SUBHEADER_FIXED *) mac_header_ptr)->LCID;
+
+ if (lcid < UE_CONT_RES) {
+ //printf("[MAC][UE] header %x.%x.%x\n",mac_header_ptr[0],mac_header_ptr[1],mac_header_ptr[2]);
+ if (not_done == 0) { // last MAC SDU, length is implicit
+ mac_header_ptr++;
+ length =
+ tb_length - (mac_header_ptr - mac_header) - ce_len;
- lcid = ((SCH_SUBHEADER_FIXED *) mac_header_ptr)->LCID;
-
- if (lcid < UE_CONT_RES) {
- //printf("[MAC][UE] header %x.%x.%x\n",mac_header_ptr[0],mac_header_ptr[1],mac_header_ptr[2]);
- if (not_done == 0) { // last MAC SDU, length is implicit
- mac_header_ptr++;
- length =
- tb_length - (mac_header_ptr - mac_header) - ce_len;
-
- for (num_sdu_cnt = 0; num_sdu_cnt < num_sdus;
- num_sdu_cnt++) {
- length -= rx_lengths[num_sdu_cnt];
- }
- } else {
- if (((SCH_SUBHEADER_LONG *) mac_header_ptr)->F == 1) {
- length =
- ((((SCH_SUBHEADER_LONG *) mac_header_ptr)->
- L_MSB & 0x7f)
- << 8) | (((SCH_SUBHEADER_LONG *) mac_header_ptr)->
- L_LSB & 0xff);
- mac_header_ptr += 3;
+ for (num_sdu_cnt = 0; num_sdu_cnt < num_sdus;
+ num_sdu_cnt++) {
+ length -= rx_lengths[num_sdu_cnt];
+ }
+ } else {
+ if (((SCH_SUBHEADER_LONG *) mac_header_ptr)->F == 1) {
+ length =
+ ((((SCH_SUBHEADER_LONG *) mac_header_ptr)->
+ L_MSB & 0x7f)
+ << 8) | (((SCH_SUBHEADER_LONG *) mac_header_ptr)->
+ L_LSB & 0xff);
+ mac_header_ptr += 3;
#ifdef DEBUG_HEADER_PARSING
- LOG_D(MAC, "[UE] parse long sdu, size %x \n", length);
+ LOG_D(MAC, "[UE] parse long sdu, size %x \n", length);
#endif
- } else { //if (((SCH_SUBHEADER_SHORT *)mac_header_ptr)->F == 0) {
- length = ((SCH_SUBHEADER_SHORT *) mac_header_ptr)->L;
- mac_header_ptr += 2;
- }
- }
+ } else { //if (((SCH_SUBHEADER_SHORT *)mac_header_ptr)->F == 0) {
+ length = ((SCH_SUBHEADER_SHORT *) mac_header_ptr)->L;
+ mac_header_ptr += 2;
+ }
+ }
#ifdef DEBUG_HEADER_PARSING
- LOG_D(MAC, "[UE] sdu %d lcid %d length %d (offset now %ld)\n",
- num_sdus, lcid, length, mac_header_ptr - mac_header);
+ LOG_D(MAC, "[UE] sdu %d lcid %d length %d (offset now %ld)\n",
+ num_sdus, lcid, length, mac_header_ptr - mac_header);
#endif
- rx_lcids[num_sdus] = lcid;
- rx_lengths[num_sdus] = length;
- num_sdus++;
- } else { // This is a control element subheader
- if (lcid == SHORT_PADDING) {
- num_padding++;
- mac_header_ptr++;
- } else {
- rx_ces[num_ces] = lcid;
- num_ces++;
- mac_header_ptr++;
-
- if (lcid == TIMING_ADV_CMD) {
- ce_len++;
- } else if (lcid == UE_CONT_RES) {
-
- // FNA: check MAC Header is one of thoses defined in Annex B of 36.321
- // Check there is only 1 Contention Resolution
- if (num_cont_res) {
- LOG_W(MAC,
- "[UE] Msg4 Wrong received format: More than 1 Contention Resolution\n");
- // exit parsing
- return NULL;
-
- }
- // UE_CONT_RES shall never be the last subheader unless this is the only MAC subheader
- if ((not_done == 0)
- && ((num_sdus) || (num_ces > 1) || (num_padding))) {
- LOG_W(MAC,
- "[UE] Msg4 Wrong received format: Contention Resolution after num_ces=%d num_sdus=%d num_padding=%d\n",
- num_ces, num_sdus, num_padding);
- // exit parsing
- return NULL;
- }
- num_cont_res++;
- ce_len += 6;
- }
- }
+ rx_lcids[num_sdus] = lcid;
+ rx_lengths[num_sdus] = length;
+ num_sdus++;
+ } else { // This is a control element subheader
+ if (lcid == SHORT_PADDING) {
+ num_padding++;
+ mac_header_ptr++;
+ } else {
+ rx_ces[num_ces] = lcid;
+ num_ces++;
+ mac_header_ptr++;
+
+ if (lcid == TIMING_ADV_CMD) {
+ ce_len++;
+ } else if (lcid == UE_CONT_RES) {
+
+ // FNA: check MAC Header is one of thoses defined in Annex B of 36.321
+ // Check there is only 1 Contention Resolution
+ if (num_cont_res) {
+ LOG_W(MAC,
+ "[UE] Msg4 Wrong received format: More than 1 Contention Resolution\n");
+ // exit parsing
+ return NULL;
+
+ }
+ // UE_CONT_RES shall never be the last subheader unless this is the only MAC subheader
+ if ((not_done == 0)
+ && ((num_sdus) || (num_ces > 1) || (num_padding))) {
+ LOG_W(MAC,
+ "[UE] Msg4 Wrong received format: Contention Resolution after num_ces=%d num_sdus=%d num_padding=%d\n",
+ num_ces, num_sdus, num_padding);
+ // exit parsing
+ return NULL;
+ }
+ num_cont_res++;
+ ce_len += 6;
+ }
+ }
#ifdef DEBUG_HEADER_PARSING
- LOG_D(MAC, "[UE] ce %d lcid %d (offset now %ld)\n", num_ces,
- lcid, mac_header_ptr - mac_header);
+ LOG_D(MAC, "[UE] ce %d lcid %d (offset now %ld)\n", num_ces,
+ lcid, mac_header_ptr - mac_header);
#endif
- }
}
+ }
- *num_ce = num_ces;
- *num_sdu = num_sdus;
+ *num_ce = num_ces;
+ *num_sdu = num_sdus;
- return (mac_header_ptr);
+ return (mac_header_ptr);
}
//------------------------------------------------------------------------------
void
nr_ue_send_sdu(module_id_t module_idP,
- uint8_t CC_id,
- frame_t frameP,
- sub_frame_t subframeP,
- uint8_t * sdu, uint16_t sdu_len, uint8_t eNB_index)
+ uint8_t CC_id,
+ frame_t frameP,
+ sub_frame_t subframeP,
+ uint8_t * sdu, uint16_t sdu_len, uint8_t eNB_index)
//------------------------------------------------------------------------------
{
- unsigned char rx_ces[MAX_NUM_CE], num_ce, num_sdu, i, *payload_ptr;
- unsigned char rx_lcids[NB_RB_MAX];
- unsigned short rx_lengths[NB_RB_MAX];
+ unsigned char rx_ces[MAX_NUM_CE], num_ce, num_sdu, i, *payload_ptr;
+ unsigned char rx_lcids[NB_RB_MAX];
+ unsigned short rx_lengths[NB_RB_MAX];
//LOG_D(MAC,"sdu: %x.%x.%x\n",sdu[0],sdu[1],sdu[2]);
- payload_ptr =
- parse_header(sdu, &num_ce, &num_sdu, rx_ces, rx_lcids, rx_lengths,
- sdu_len);
+ payload_ptr =
+ parse_header(sdu, &num_ce, &num_sdu, rx_ces, rx_lcids, rx_lengths,
+ sdu_len);
#ifdef DEBUG_HEADER_PARSING
- LOG_D(MAC,
- "[UE %d] ue_send_sdu : Frame %d eNB_index %d : num_ce %d num_sdu %d\n",
- module_idP, frameP, eNB_index, num_ce, num_sdu);
+ LOG_D(MAC,
+ "[UE %d] ue_send_sdu : Frame %d eNB_index %d : num_ce %d num_sdu %d\n",
+ module_idP, frameP, eNB_index, num_ce, num_sdu);
#endif
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
- LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP);
+ LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP);
- for (i = 0; i < 32; i++) {
- LOG_T(MAC, "%x.", sdu[i]);
- }
+ for (i = 0; i < 32; i++) {
+ LOG_T(MAC, "%x.", sdu[i]);
+ }
- LOG_T(MAC, "\n");
+ LOG_T(MAC, "\n");
#endif
- if (payload_ptr != NULL) {
+ if (payload_ptr != NULL) {
- for (i = 0; i < num_ce; i++) {
- // printf("ce %d : %d\n",i,rx_ces[i]);
- switch (rx_ces[i]) {
- case UE_CONT_RES:
+ for (i = 0; i < num_ce; i++) {
+ // printf("ce %d : %d\n",i,rx_ces[i]);
+ switch (rx_ces[i]) {
+ case UE_CONT_RES:
- break;
+ break;
- case TIMING_ADV_CMD:
+ case TIMING_ADV_CMD:
break;
- case DRX_CMD:
+ case DRX_CMD:
- break;
- }
- }
+ break;
+ }
+ }
- for (i = 0; i < num_sdu; i++) {
+ for (i = 0; i < num_sdu; i++) {
#ifdef DEBUG_HEADER_PARSING
- LOG_I(MAC, "[UE] SDU %d : LCID %d, length %d\n", i,
- rx_lcids[i], rx_lengths[i]);
+ LOG_I(MAC, "[UE] SDU %d : LCID %d, length %d\n", i,
+ rx_lcids[i], rx_lengths[i]);
#endif
- if ((rx_lcids[i] < NB_RB_MAX) && (rx_lcids[i] > DCCH1)) {
+ if ((rx_lcids[i] < NB_RB_MAX) && (rx_lcids[i] > DCCH1)) {
- LOG_D(MAC,
- "[UE %d] Frame %d : DLSCH -> DL-DTCH%d (eNB %d, %d bytes)\n",
- module_idP, frameP, rx_lcids[i], eNB_index,
- rx_lengths[i]);
+ LOG_D(MAC,
+ "[UE %d] Frame %d : DLSCH -> DL-DTCH%d (eNB %d, %d bytes)\n",
+ module_idP, frameP, rx_lcids[i], eNB_index,
+ rx_lengths[i]);
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
- LOG_I(MAC, "Printing MAC PDU contents at slot: %d \n", subframeP);
- int j;
- for (j = 0; j < 20; j++) //rx_lengths[i]
- LOG_I(MAC, "%x.", (unsigned char) payload_ptr[j]);
- LOG_I(MAC, "\n");
+ LOG_I(MAC, "Printing MAC PDU contents at slot: %d \n", subframeP);
+ int j;
+ for (j = 0; j < 20; j++) //rx_lengths[i]
+ LOG_I(MAC, "%x.", (unsigned char) payload_ptr[j]);
+ LOG_I(MAC, "\n");
#endif
- mac_rlc_data_ind(module_idP,
- 4660, //UE_mac_inst[module_idP].crnti //hardcode value corresponding to the one from the eNB
- eNB_index,
- frameP,
- ENB_FLAG_NO,
- MBMS_FLAG_NO,
- rx_lcids[i],
- (char *) payload_ptr, rx_lengths[i], 1,
- NULL);
- } else {
- LOG_E(MAC, "[UE %d] Frame %d : unknown LCID %d (eNB %d)\n",
- module_idP, frameP, rx_lcids[i], eNB_index);
- }
- payload_ptr += rx_lengths[i];
- }
- } // end if (payload_ptr != NULL)
+ mac_rlc_data_ind(module_idP,
+ 4660, //UE_mac_inst[module_idP].crnti //hardcode value corresponding to the one from the eNB
+ eNB_index,
+ frameP,
+ ENB_FLAG_NO,
+ MBMS_FLAG_NO,
+ rx_lcids[i],
+ (char *) payload_ptr, rx_lengths[i], 1,
+ NULL);
+ } else {
+ LOG_E(MAC, "[UE %d] Frame %d : unknown LCID %d (eNB %d)\n",
+ module_idP, frameP, rx_lcids[i], eNB_index);
+ }
+ payload_ptr += rx_lengths[i];
+ }
+ } // end if (payload_ptr != NULL)
}
+int nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
+ int dci_format,
+ uint8_t dci_size,
+ uint16_t rnti,
+ uint64_t *dci_pdu,
+ nr_dci_pdu_rel15_t *dci_pdu_rel15) {
+ int rnti_type=-1;
+
+ if (rnti == mac->ra_rnti) rnti_type = NR_RNTI_RA;
+ else if (rnti == mac->crnti) rnti_type = NR_RNTI_C;
+ else if (rnti == mac->t_crnti) rnti_type = NR_RNTI_TC;
+ else if (rnti == 0xFFFE) rnti_type = NR_RNTI_P;
+ else if (rnti == 0xFFFF) rnti_type = NR_RNTI_SI;
+
+ AssertFatal(rnti_type!=-1,"no identified/handled rnti\n");
+ AssertFatal(mac->DLbwp[0] != NULL, "DLbwp[0] shouldn't be null here!\n");
+ AssertFatal(mac->ULbwp[0] != NULL, "ULbwp[0] shouldn't be null here!\n");
+ int N_RB = (mac->scd != NULL) ?
+ NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) :
+ NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275);
+ int N_RB_UL = (mac->scd != NULL) ?
+ NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) :
+ NRRIV2BW(mac->scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275);
+
+ int pos;
+ int fsize=0;
+ switch(dci_format) {
+
+ case NR_DL_DCI_FORMAT_1_0:
+ switch(rnti_type) {
+ case NR_RNTI_RA:
+ // Freq domain assignment
+ fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ pos=fsize;
+ dci_pdu_rel15->freq_dom_resource_assignment_DL = *dci_pdu>>(dci_size-pos)&((1<<fsize)-1);
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,N_RB,dci_size-pos,*dci_pdu);
+#endif
+ // Time domain assignment
+ pos+=4;
+ dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu);
+#endif
+ // VRB to PRB mapping
+
+ pos++;
+ dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&0x1;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu);
+#endif
+ // MCS
+ pos+=5;
+ dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
+#endif
+ // TB scaling
+ pos+=2;
+ dci_pdu_rel15->tb_scaling = (*dci_pdu>>(dci_size-pos))&0x3;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
+#endif
+ break;
+
+ case NR_RNTI_C:
+
+ // indicating a DL DCI format 1bit
+ pos++;
+ dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->identifier_dci_formats,1,N_RB,dci_size-pos,*dci_pdu);
+#endif
+
+ // Freq domain assignment (275rb >> fsize = 16)
+ fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ pos+=fsize;
+ dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,dci_size-pos,*dci_pdu);
+#endif
+
+ uint16_t is_ra = 1;
+ for (int i=0; i<fsize; i++)
+ if (!((dci_pdu_rel15->freq_dom_resource_assignment_DL>>i)&1)) {
+ is_ra = 0;
+ break;
+ }
+ if (is_ra) //fsize are all 1 38.212 p86
+ {
+ // ra_preamble_index 6 bits
+ pos+=6;
+ dci_pdu_rel15->ra_preamble_index = (*dci_pdu>>(dci_size-pos))&0x3f;
+
+ // UL/SUL indicator 1 bit
+ pos++;
+ dci_pdu_rel15->sul_ind_0_1 = (*dci_pdu>>(dci_size-pos))&1;
+
+ // SS/PBCH index 6 bits
+ pos+=6;
+ dci_pdu_rel15->ss_pbch_index = (*dci_pdu>>(dci_size-pos))&0x3f;
+
+ // prach_mask_index 4 bits
+ pos+=4;
+ dci_pdu_rel15->prach_mask_index = (*dci_pdu>>(dci_size-pos))&0xf;
+
+ } //end if
+ else {
+
+ // Time domain assignment 4bit
+
+ pos+=4;
+ dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,4,dci_size-pos,*dci_pdu);
+#endif
+
+ // VRB to PRB mapping 1bit
+ pos++;
+ dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu);
+#endif
+
+ // MCS 5bit //bit over 32, so dci_pdu ++
+ pos+=5;
+ dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu);
+#endif
+
+ // New data indicator 1bit
+ pos++;
+ dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu);
+#endif
+
+ // Redundancy version 2bit
+ pos+=2;
+ dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu);
+#endif
+
+ // HARQ process number 4bit
+ pos+=4;
+ dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_process_number,4,dci_size-pos,*dci_pdu);
+#endif
+
+ // Downlink assignment index 2bit
+ pos+=2;
+ dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu);
+#endif
+
+ // TPC command for scheduled PUCCH 2bit
+ pos+=2;
+ dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc_pucch,2,dci_size-pos,*dci_pdu);
+#endif
+
+ // PUCCH resource indicator 3bit
+ pos+=3;
+ dci_pdu_rel15->pucch_resource_ind = (*dci_pdu>>(dci_size-pos))&0x7;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_ind,3,dci_size-pos,*dci_pdu);
+#endif
+
+ // PDSCH-to-HARQ_feedback timing indicator 3bit
+ pos+=3;
+ dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&0x7;
+#ifdef DEBUG_EXTRACT_DCI
+ LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_time_ind,3,dci_size-pos,*dci_pdu);
+#endif
+
+ } //end else
+ break;
+
+ case NR_RNTI_P:
+ /*
+ // Short Messages Indicator – 2 bits
+ for (int i=0; i<2; i++)
+ dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++);
+ // Short Messages – 8 bits
+ for (int i=0; i<8; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++);
+ // Freq domain assignment 0-16 bit
+ fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ for (int i=0; i<fsize; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ // Time domain assignment 4 bit
+ for (int i=0; i<4; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ // VRB to PRB mapping 1 bit
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ // MCS 5 bit
+ for (int i=0; i<5; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
+
+ // TB scaling 2 bit
+ for (int i=0; i<2; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++);
+ */
+
+ break;
+
+ case NR_RNTI_SI:
+ /*
+ // Freq domain assignment 0-16 bit
+ fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ for (int i=0; i<fsize; i++)
+ *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ // Time domain assignment 4 bit
+ for (int i=0; i<4; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ // VRB to PRB mapping 1 bit
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ // MCS 5bit //bit over 32, so dci_pdu ++
+ for (int i=0; i<5; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
+ // Redundancy version 2bit
+ for (int i=0; i<2; i++)
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++);
+ */
+ break;
+
+ case NR_RNTI_TC:
+ // indicating a DL DCI format 1bit
+ pos++;
+ dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+ // Freq domain assignment 0-16 bit
+ fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ pos+=fsize;
+ dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+ // Time domain assignment 4 bit
+ pos+=4;
+ dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+ // VRB to PRB mapping 1 bit
+ dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1;
+ // MCS 5bit //bit over 32, so dci_pdu ++
+ pos+=5;
+ dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
+ // New data indicator 1bit
+ dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&1;
+ // Redundancy version 2bit
+ pos+=2;
+ dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3;
+ // HARQ process number 4bit
+ pos+=4;
+ dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+ // Downlink assignment index – 2 bits
+ pos+=2;
+ dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3;
+ // TPC command for scheduled PUCCH – 2 bits
+ pos+=2;
+ dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3;
+ // PDSCH-to-HARQ_feedback timing indicator – 3 bits
+ pos+=3;
+ dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&7;
+
+ break;
+ }
+ break;
+
+ case NR_UL_DCI_FORMAT_0_0:
+ switch(rnti_type)
+ {
+ case NR_RNTI_C:
+ // indicating a DL DCI format 1bit
+ dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+ // Freq domain assignment max 16 bit
+ fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
+ pos+=fsize;
+ dci_pdu_rel15->freq_dom_resource_assignment_UL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+ // Time domain assignment 4bit
+ pos+=4;
+ dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+ // Frequency hopping flag – 1 bit
+ pos++;
+ dci_pdu_rel15->freq_hopping_flag= (*dci_pdu>>(dci_size-pos))&1;
+ // MCS 5 bit
+ pos+=5;
+ dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
+ // New data indicator 1bit
+ pos++;
+ dci_pdu_rel15->ndi= (*dci_pdu>>(dci_size-pos))&1;
+ // Redundancy version 2bit
+ pos+=2;
+ dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
+ // HARQ process number 4bit
+ pos+=4;
+ dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+ // TPC command for scheduled PUSCH – 2 bits
+ pos+=2;
+ dci_pdu_rel15->tpc_pusch = (*dci_pdu>>(dci_size-pos))&3;
+ // UL/SUL indicator – 1 bit
+ /* commented for now (RK): need to get this from BWP descriptor
+ if (cfg->pucch_config.pucch_GroupHopping.value)
+ dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
+ */
+ break;
+
+ case NR_RNTI_TC:
+ /*
+ // indicating a DL DCI format 1bit
+ dci_pdu->= (*dci_pdu>>(dci_size-pos)format_indicator&1)<<(dci_size-pos++);
+ // Freq domain assignment max 16 bit
+ fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
+ for (int i=0; i<fsize; i++)
+ dci_pdu->= ((*dci_pdu>>(dci_size-pos)frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ // Time domain assignment 4bit
+ for (int i=0; i<4; i++)
+ dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ // Frequency hopping flag – 1 bit
+ dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)frequency_hopping_flag&1)<<(dci_size-pos++);
+ // MCS 5 bit
+ for (int i=0; i<5; i++)
+ dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)mcs>>(4-i))&1)<<(dci_size-pos++);
+ // New data indicator 1bit
+ dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ndi&1)<<(dci_size-pos++);
+ // Redundancy version 2bit
+ for (int i=0; i<2; i++)
+ dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)rv>>(1-i))&1)<<(dci_size-pos++);
+ // HARQ process number 4bit
+ for (int i=0; i<4; i++)
+ *dci_pdu |= (((uint64_t)*dci_pdu>>(dci_size-pos)harq_pid>>(3-i))&1)<<(dci_size-pos++);
+
+ // TPC command for scheduled PUSCH – 2 bits
+ for (int i=0; i<2; i++)
+ dci_pdu->= (((uint64_t)*dci_pdu>>(dci_size-pos)tpc>>(1-i))&1)<<(dci_size-pos++);
+ */
+ // UL/SUL indicator – 1 bit
+ /*
+ commented for now (RK): need to get this information from BWP descriptor
+ if (cfg->pucch_config.pucch_GroupHopping.value)
+ dci_pdu->= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
+ */
+ break;
+
+ }
+ break;
+ }
+}
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
index 6b6f738f2fde294af12d4c00e921f252bee58bc7..f1302fd1d18ad5dc62e1df50bcb567e1a600dbe9 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
@@ -328,7 +328,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// Check if there are downlink symbols in the slot, if not return, no scheduling opportunities
- if (is_nr_DL_slot(cc,slot_txP)==0) return;
+ if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)==0) return;
RC.nrmac[module_idP]->frame = frame_rxP;
RC.nrmac[module_idP]->slot = slot_rxP;
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
index e54de70352c438abcd718c4e5f0dd7c4c5de41a8..5307794b4c86f0565b759c690966ae92599c1c7c 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
@@ -126,7 +126,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0; // Point A
- pdsch_pdu_rel15->dmrsConfigType = 1; // 1 by default for InitialBWP
+ pdsch_pdu_rel15->dmrsConfigType = 0; // Type 1 by default for InitialBWP
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
@@ -173,9 +173,9 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
dlBWP_carrier_bandwidth);
- pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbStart,
- pdsch_pdu_rel15->rbSize,
- dlBWP_carrier_bandwidth);
+ pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
+ pdsch_pdu_rel15->rbStart,
+ dlBWP_carrier_bandwidth);
pdu_rel15->time_domain_assignment = time_domain_assignment;
pdu_rel15->vrb_to_prb_mapping = 1;
@@ -248,7 +248,10 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
int configure_fapi_dl_Tx(int Mod_idP,
int *CCEIndex,
nfapi_nr_dl_tti_request_body_t *dl_req,
- nfapi_nr_pdu_t *TX_req) {
+ nfapi_nr_pdu_t *TX_req,
+ int *mcsIndex,
+ int *rbSize,
+ int *rbStart) {
gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
@@ -266,8 +269,6 @@ int configure_fapi_dl_Tx(int Mod_idP,
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
- LOG_I(PHY,"UE_id %d\n",UE_id);
-
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
"downlinkBWP_ToAddModList has %d BWP!\n",
@@ -301,10 +302,10 @@ int configure_fapi_dl_Tx(int Mod_idP,
else pdsch_pdu_rel15->CyclicPrefix=0;
pdsch_pdu_rel15->NrOfCodewords = 1;
- int mcsIndex = 9;
+ int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
- pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
+ pdsch_pdu_rel15->mcsIndex[0] = mcs;
pdsch_pdu_rel15->mcsTable[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = 0;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
@@ -312,14 +313,14 @@ int configure_fapi_dl_Tx(int Mod_idP,
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0; // Point A
- pdsch_pdu_rel15->dmrsConfigType = 1; // 1 by default for InitialBWP
+ pdsch_pdu_rel15->dmrsConfigType = bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
pdsch_pdu_rel15->dmrsPorts = 1;
pdsch_pdu_rel15->resourceAlloc = 1;
- pdsch_pdu_rel15->rbStart = 0;
- pdsch_pdu_rel15->rbSize = 50;
+ pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0;
+ pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize;
pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP
// choose shortest PDSCH
int startSymbolAndLength=0;
@@ -333,14 +334,14 @@ int configure_fapi_dl_Tx(int Mod_idP,
pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
// k0 = *bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0;
- pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL,
+ pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(bwp->bwp_Dedicated->pdsch_Config->choice.setup,
scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
- dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbStart,
- pdsch_pdu_rel15->rbSize,
+ dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
+ pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
@@ -357,7 +358,7 @@ int configure_fapi_dl_Tx(int Mod_idP,
dci_pdu_rel15[0].pucch_resource_indicator = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7;
- LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
+ LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
@@ -392,8 +393,9 @@ int configure_fapi_dl_Tx(int Mod_idP,
rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
-
- LOG_I(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
+ fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
+
+ LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
pdcch_pdu_rel15->RNTI[0],
rnti_types[0],
@@ -407,7 +409,7 @@ int configure_fapi_dl_Tx(int Mod_idP,
x_Overhead);
// Hardcode it for now
TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0];
- LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n",
+ LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n",
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
startSymbolAndLength,
@@ -433,8 +435,8 @@ int configure_fapi_dl_Tx(int Mod_idP,
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
- dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_start,
- pusch_pdu->rb_size,
+ dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
+ pusch_pdu->rb_start,
NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
@@ -447,7 +449,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
dci_pdu_rel15->harq_pid = 0;
dci_pdu_rel15->tpc = 2;
- LOG_I(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
+ LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment,
dci_pdu_rel15->time_domain_assignment,
@@ -633,8 +635,10 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
TBS_bytes = configure_fapi_dl_Tx(module_idP,
CCEIndices,
dl_req,
- TX_req);
-
+ TX_req,
+ dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
+ dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
+ dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, , TBS size: %d \n \n", frameP, slotP, TBS_bytes);
for(int i = 0; i < 10; i++) { // TBS_bytes dlsch_pdu_rel15->transport_block_size/8 6784/8
@@ -668,10 +672,13 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
int CCEIndices[2];
CCEIndices[0] = CCEIndex;
- LOG_I(MAC,"Configuring DL_TX in %d.%d\n",frameP,slotP);
- TBS_bytes = configure_fapi_dl_Tx(module_idP,CCEIndices,dl_req, TX_req);
- // HOT FIX for all zero pdu problem
- // ------------------------------------------------------------------------------------------------
+ LOG_D(MAC,"Configuring DL_TX in %d.%d\n",frameP,slotP);
+ TBS_bytes = configure_fapi_dl_Tx(module_idP,CCEIndices,dl_req, TX_req,
+ dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
+ dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
+ dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
+// HOT FIX for all zero pdu problem
+// ------------------------------------------------------------------------------------------------
for(int i = 0; i < TBS_bytes; i++) { //
((uint8_t *)nr_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) rand();
@@ -679,10 +686,10 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
}
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
if (frameP%100 == 0){
- LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes);
- for(int i = 0; i < 10; i++) {
- LOG_I(MAC, "%x. ", ((uint8_t *)nr_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]);
- }
+ LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes);
+ for(int i = 0; i < 10; i++) {
+ LOG_I(MAC, "%x. ", ((uint8_t *)nr_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]);
+ }
}
#endif
@@ -827,7 +834,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
rnti_types[0] = NR_RNTI_C;
- LOG_I(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
+ LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific,
scc,
@@ -839,7 +846,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
AssertFatal(CCEIndex>=0,"CCEIndex is negative \n");
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex;
- LOG_I(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]);
+ LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]);
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
index 9c84b975337cc5107ccf0f8a49ae016ce85333ac..df9c37f68718128e84e6601fa08bce911de7b9e4 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
@@ -39,6 +39,7 @@
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
+#include "common/utils/nr/nr_common.h"
#include "UTIL/OPT/opt.h"
#include "OCG.h"
#include "OCG_extern.h"
@@ -64,7 +65,6 @@
#define ENABLE_MAC_PAYLOAD_DEBUG
#define DEBUG_gNB_SCHEDULER 1
-#define CEILIDIV(a,b) ((a+b-1)/b)
#include "common/ran_context.h"
@@ -1367,146 +1367,8 @@ int add_new_nr_ue(module_id_t mod_idP,
}
}
*/
-int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols) {
-
- int l0;
- if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2) l0=2;
- else if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3) l0=3;
- else AssertFatal(1==0,"Illegal dmrs_TypeA_Position %d\n",(int)dmrs_TypeA_Position);
- if (pdsch_Config == NULL) { // Initial BWP
- return(1<<l0);
- }
- else {
- if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA &&
- pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
- // Relative to start of slot
- NR_DMRS_DownlinkConfig_t *dmrs_config = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
- AssertFatal(NrOfSymbols>1 && NrOfSymbols < 15,"Illegal NrOfSymbols %d\n",NrOfSymbols);
- int pos2=0;
- if (dmrs_config->maxLength == NULL) {
- // this is Table 7.4.1.1.2-3: PDSCH DM-RS positions l for single-symbol DM-RS
- if (dmrs_config->dmrs_AdditionalPosition == NULL) pos2=1;
- else if (dmrs_config->dmrs_AdditionalPosition && *dmrs_config->dmrs_AdditionalPosition == NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0 )
- return(1<<l0);
-
-
- switch (NrOfSymbols) {
- case 2 :
- case 3 :
- case 4 :
- case 5 :
- case 6 :
- case 7 :
- AssertFatal(1==0,"Incoompatible NrOfSymbols %d and dmrs_Additional_Position %d\n",
- NrOfSymbols,(int)*dmrs_config->dmrs_AdditionalPosition);
- break;
- case 8 :
- case 9:
- return(1<<l0 | 1<<7);
- break;
- case 10:
- case 11:
- if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
- return(1<<l0 | 1<<9);
- else
- return(1<<l0 | 1<<6 | 1<<9);
- break;
- case 12:
- if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
- return(1<<l0 | 1<<9);
- else if (pos2==1)
- return(1<<l0 | 1<<6 | 1<<9);
- else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
- return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
- break;
- case 13:
- case 14:
- if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
- return(1<<l0 | 1<<11);
- else if (pos2==1)
- return(1<<l0 | 1<<7 | 1<<11);
- else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
- return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
- break;
- }
- }
- else {
- // Table 7.4.1.1.2-4: PDSCH DM-RS positions l for double-symbol DM-RS.
- AssertFatal(NrOfSymbols>3,"Illegal NrOfSymbols %d for len2 DMRS\n",NrOfSymbols);
- if (NrOfSymbols < 10) return(1<<l0);
- if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
- if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0 || 1<<8);
- if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
- if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) return(1<<l0 || 1<<10);
- }
- }
- else if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB &&
- pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
- // Relative to start of PDSCH resource
- AssertFatal(1==0,"TypeB DMRS not supported yet\n");
- }
- }
- AssertFatal(1==0,"Shouldn't get here\n");
- return(-1);
-}
-int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000};
-
-int is_nr_DL_slot(NR_COMMON_channels_t *cc,slot_t slot) {
-
- NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
- int period,period1,period2=0;
-
- if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
-
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
- scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
- period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
- else
- period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
-
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
- scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
- period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
- else
- period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
- }
- period = period1+period2;
- int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
- int slots=period*(1<<scs)/1000;
- int slots1=period1*(1<<scs)/1000;
- int slot_in_period = slot % slots;
- if (slot_in_period < slots1) return(slot_in_period <= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
- else return(slot_in_period <= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
-}
-int is_nr_UL_slot(NR_COMMON_channels_t *cc,slot_t slot) {
-
- NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
- int period,period1,period2=0;
-
- if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
-
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
- scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
- period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
- else
- period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
-
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
- if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
- scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
- period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
- else
- period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
- }
- period = period1+period2;
- int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
- int slots=period*(1<<scs)/1000;
- int slots1=period1*(1<<scs)/1000;
- int slot_in_period = slot % slots;
- if (slot_in_period < slots1) return(slot_in_period >= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
- else return(slot_in_period >= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
-}
+
+
diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
index d7fce03dc2e777c0712664ed591039ac544fd4d2..60392b11dcfce0adb358143321ccff0c56735eea 100644
--- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
@@ -67,7 +67,10 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
int configure_fapi_dl_Tx(int Mod_id,
int *CCEIndeces,
nfapi_nr_dl_tti_request_body_t *dl_req,
- nfapi_nr_pdu_t *TX_req);
+ nfapi_nr_pdu_t *TX_req,
+ int *mcsIndex,
+ int *rbSize,
+ int *rbStart);
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types);
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
@@ -160,7 +163,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int m
);
-int is_nr_DL_slot(NR_COMMON_channels_t *cc,slot_t slotP);
-int is_nr_UL_slot(NR_COMMON_channels_t *cc,slot_t slotP);
+int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
+int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
#endif /*__LAYER2_NR_MAC_PROTO_H__*/
diff --git a/openair1/PHY/CODING/nr_compute_tbs.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
similarity index 97%
rename from openair1/PHY/CODING/nr_compute_tbs.c
rename to openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
index 055f697f41d33f760f727c691dc95f87abec25cf..e6127fb57ed5c5309d8784fa1aaf0b4382e0ffd6 100644
--- a/openair1/PHY/CODING/nr_compute_tbs.c
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
@@ -23,9 +23,10 @@
purpose: Compute NR TBS
author: Hongzhi WANG (TCL)
*/
-#include "PHY/defs_nr_UE.h"
#define INDEX_MAX_TBS_TABLE (93)
+#include "common/utils/nr/nr_common.h"
+
//Table 5.1.2.2-2
uint16_t Tbstable_nr[INDEX_MAX_TBS_TABLE] = {24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,208,224,240,256,272,288,304,320,336,352,368,384,408,432,456,480,504,528,552,576,608,640,672,704,736,768,808,848,888,928,984,1032,1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1736,1800,1864,1928,2024,2088,2152,2216,2280,2408,2472,2536,2600,2664,2728,2792,2856,2976,3104,3240,3368,3496,3624,3752,3824};
@@ -45,7 +46,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint32_t Ninfo, Np_info, C;
uint8_t n, scale;
- nbp_re = NR_NB_SC_PER_RB * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
+ nbp_re = 12 * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
nb_re = min(156, nbp_re) * nb_rb;
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c
index fc20b668f638ae59d824bfe15131862f9bf3782c..bbaf1d705d6a0334c4ba0638d2de7687781091a8 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c
@@ -211,7 +211,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
N_sh_symb,
N_PRB_DMRS,
N_PRB_oh,
- pdsch_rel15->nrOfLayers);
+ pdsch_rel15->nrOfLayers)>>3;
pdsch_rel15->targetCodeRate[0] = R;
pdsch_rel15->qamModOrder[0] = Qm;
@@ -219,7 +219,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
// pdsch_rel15->nb_mod_symbols = N_RE_prime*pdsch_rel15->n_prb*pdsch_rel15->nb_codewords;
pdsch_rel15->mcsTable[0] = table_idx;
- LOG_D(MAC, "TBS %d : N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n",
+ LOG_D(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n",
TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords );
}
@@ -455,3 +455,143 @@ uint16_t nr_dci_size(nr_dci_format_t format,
return size;
}
+int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000};
+
+int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) {
+
+ int period,period1,period2=0;
+
+ if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
+
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
+ scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
+ period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
+ else
+ period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
+
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
+ scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
+ period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
+ else
+ period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
+ }
+ period = period1+period2;
+ int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
+ int slots=period*(1<<scs)/1000;
+ int slots1=period1*(1<<scs)/1000;
+ int slot_in_period = slot % slots;
+ if (slot_in_period < slots1) return(slot_in_period <= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
+ else return(slot_in_period <= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
+}
+
+int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) {
+
+ int period,period1,period2=0;
+
+ if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
+
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
+ scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
+ period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
+ else
+ period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
+
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
+ scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
+ period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
+ else
+ period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
+ }
+ period = period1+period2;
+ int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
+ int slots=period*(1<<scs)/1000;
+ int slots1=period1*(1<<scs)/1000;
+ int slot_in_period = slot % slots;
+ if (slot_in_period < slots1) return(slot_in_period >= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
+ else return(slot_in_period >= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
+}
+
+int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols) {
+
+ int l0;
+ if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2) l0=2;
+ else if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3) l0=3;
+ else AssertFatal(1==0,"Illegal dmrs_TypeA_Position %d\n",(int)dmrs_TypeA_Position);
+ if (pdsch_Config == NULL) { // Initial BWP
+ return(1<<l0);
+ }
+ else {
+ if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA &&
+ pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
+ // Relative to start of slot
+ NR_DMRS_DownlinkConfig_t *dmrs_config = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
+ AssertFatal(NrOfSymbols>1 && NrOfSymbols < 15,"Illegal NrOfSymbols %d\n",NrOfSymbols);
+ int pos2=0;
+ if (dmrs_config->maxLength == NULL) {
+ // this is Table 7.4.1.1.2-3: PDSCH DM-RS positions l for single-symbol DM-RS
+ if (dmrs_config->dmrs_AdditionalPosition == NULL) pos2=1;
+ else if (dmrs_config->dmrs_AdditionalPosition && *dmrs_config->dmrs_AdditionalPosition == NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0 )
+ return(1<<l0);
+
+
+ switch (NrOfSymbols) {
+ case 2 :
+ case 3 :
+ case 4 :
+ case 5 :
+ case 6 :
+ case 7 :
+ AssertFatal(1==0,"Incoompatible NrOfSymbols %d and dmrs_Additional_Position %d\n",
+ NrOfSymbols,(int)*dmrs_config->dmrs_AdditionalPosition);
+ break;
+ case 8 :
+ case 9:
+ return(1<<l0 | 1<<7);
+ break;
+ case 10:
+ case 11:
+ if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
+ return(1<<l0 | 1<<9);
+ else
+ return(1<<l0 | 1<<6 | 1<<9);
+ break;
+ case 12:
+ if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
+ return(1<<l0 | 1<<9);
+ else if (pos2==1)
+ return(1<<l0 | 1<<6 | 1<<9);
+ else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
+ return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
+ break;
+ case 13:
+ case 14:
+ if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
+ return(1<<l0 | 1<<11);
+ else if (pos2==1)
+ return(1<<l0 | 1<<7 | 1<<11);
+ else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
+ return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
+ break;
+ }
+ }
+ else {
+ // Table 7.4.1.1.2-4: PDSCH DM-RS positions l for double-symbol DM-RS.
+ AssertFatal(NrOfSymbols>3,"Illegal NrOfSymbols %d for len2 DMRS\n",NrOfSymbols);
+ if (NrOfSymbols < 10) return(1<<l0);
+ if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
+ if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0 || 1<<8);
+ if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
+ if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) return(1<<l0 || 1<<10);
+ }
+ }
+ else if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB &&
+ pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
+ // Relative to start of PDSCH resource
+ AssertFatal(1==0,"TypeB DMRS not supported yet\n");
+ }
+ }
+ AssertFatal(1==0,"Shouldn't get here\n");
+ return(-1);
+}
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h
new file mode 100644
index 0000000000000000000000000000000000000000..9bca4e669c457363a711e9bac9a58ebc97bc1ccb
--- /dev/null
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h
@@ -0,0 +1,62 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file mac.h
+* \brief MAC data structures, constant, and function prototype
+* \author Navid Nikaein and Raymond Knopp, WIE-TAI CHEN
+* \date Dec. 2019
+* \version 0.1
+* \company Eurecom
+* \email raymond.knopp@eurecom.fr
+
+*/
+
+#ifndef __LAYER2_NR_MAC_COMMON_H__
+#define __LAYER2_NR_MAC_COMMON_H__
+
+typedef enum {
+ NR_DL_DCI_FORMAT_1_0 = 0,
+ NR_DL_DCI_FORMAT_1_1,
+ NR_DL_DCI_FORMAT_2_0,
+ NR_DL_DCI_FORMAT_2_1,
+ NR_DL_DCI_FORMAT_2_2,
+ NR_DL_DCI_FORMAT_2_3,
+ NR_UL_DCI_FORMAT_0_0,
+ NR_UL_DCI_FORMAT_0_1
+} nr_dci_format_t;
+
+typedef enum {
+ NR_RNTI_new = 0,
+ NR_RNTI_C,
+ NR_RNTI_RA,
+ NR_RNTI_P,
+ NR_RNTI_CS,
+ NR_RNTI_TC,
+ NR_RNTI_SP_CSI,
+ NR_RNTI_SI,
+ NR_RNTI_SFI,
+ NR_RNTI_INT,
+ NR_RNTI_TPC_PUSCH,
+ NR_RNTI_TPC_PUCCH,
+ NR_RNTI_TPC_SRS
+} nr_rnti_type_t;
+
+#endif
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
index 5afc142c6815b83b1fa099e46a4038bba0b1114b..18bc034ae4ee75587eb5fde94d2660574136de39 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
@@ -59,6 +59,8 @@
#include "PHY/TOOLS/time_meas.h"
#include "targets/ARCH/COMMON/common_lib.h"
+#include "nr_mac_common.h"
+
#define MAX_NUM_BWP 2
#define MAX_NUM_CORESET 2
#define MAX_NUM_CCE 90
@@ -241,31 +243,6 @@ uint16_t padding;
} dci_pdu_rel15_t;
-typedef enum {
- NR_DL_DCI_FORMAT_1_0 = 0,
- NR_DL_DCI_FORMAT_1_1,
- NR_DL_DCI_FORMAT_2_0,
- NR_DL_DCI_FORMAT_2_1,
- NR_DL_DCI_FORMAT_2_2,
- NR_DL_DCI_FORMAT_2_3,
- NR_UL_DCI_FORMAT_0_0,
- NR_UL_DCI_FORMAT_0_1
-} nr_dci_format_t;
-
-typedef enum {
- NR_RNTI_new = 0,
- NR_RNTI_C,
- NR_RNTI_RA,
- NR_RNTI_P,
- NR_RNTI_CS,
- NR_RNTI_TC,
- NR_RNTI_SP_CSI,
- NR_RNTI_SI,
- NR_RNTI_SFI,
- NR_RNTI_INT,
- NR_RNTI_TPC_PUSCH,
- NR_RNTI_TPC_PUCCH,
- NR_RNTI_TPC_SRS
-} nr_rnti_type_t;
+
#endif /*__LAYER2_NR_MAC_GNB_H__ */
diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
index eb7527ff4443ed357528a366450244cec3124315..6f43813e9dcc10e5c0a4dc1a0b2a3812b6522061 100644
--- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
@@ -64,22 +64,22 @@ int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index,
return 0;
}
// L2 Abstraction Layer
-int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){
+int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci){
//printf("handle_dci: rnti %x,dci_type %d\n",rnti,dci_type);
- return nr_ue_process_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type);
+ return nr_ue_process_dci_indication_pdu(module_id, cc_id, gNB_index, dci);
}
// L2 Abstraction Layer
int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len, frame_t frame, int slot){
- LOG_I(MAC, "handle_dlsch at MAC layer \n");
- if (IS_SOFTMODEM_NOS1)
- nr_ue_send_sdu(module_id, 0, frame, slot,
- pduP,
- pdu_len,
+LOG_D(MAC, "handle_dlsch at MAC layer \n");
+if (IS_SOFTMODEM_NOS1)
+ nr_ue_send_sdu(module_id, 0, frame, slot,
+ pduP,
+ pdu_len,
0);
- return 0;
+return 0;
/*
return nr_ue_process_dlsch( module_id,
cc_id,
@@ -154,15 +154,13 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
for(i=0; i<dl_info->dci_ind->number_of_dcis; ++i){
LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis);
- fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci;
+ // fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci;
ret_mask |= (handle_dci(
dl_info->module_id,
dl_info->cc_id,
dl_info->gNB_index,
- dci,
- (dl_info->dci_ind->dci_list+i)->rnti,
- (dl_info->dci_ind->dci_list+i)->dci_format)) << FAPI_NR_DCI_IND;
+ dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND);
AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
@@ -216,7 +214,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
}
if(dl_info->rx_ind != NULL){
- LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
for(i=0; i<dl_info->rx_ind->number_pdus; ++i){
switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){
case FAPI_NR_RX_PDU_TYPE_MIB:
@@ -227,7 +225,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index,
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length,
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;
- LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
/*ret_mask |= (handle_bcch_bch( dl_info->proc,
dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu,
@@ -248,7 +246,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu,
(dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
- LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
/*
// dl_config structure just stores what was received - not really needed
@@ -307,48 +305,11 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
fapi_nr_dl_config_request_t *dl_config=&dcireq->dl_config_req;
NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0);
-
- // Type0 PDCCH search space
- dl_config->number_pdus = 1;
- dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234; // to be set
-
- uint64_t mask = 0x0;
- uint16_t num_rbs=24;
- uint16_t rb_offset=0;
- uint16_t cell_id=0;
- uint16_t num_symbols=2;
- for(int i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
- mask = mask >> 1;
- mask = mask | 0x100000000000;
- }
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset
-
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id;
-
- uint32_t number_of_search_space_per_slot=1;
- uint32_t first_symbol_index=0;
- uint32_t search_space_duration=0; // element of search space
- uint32_t coreset_duration; // element of coreset
-
- coreset_duration = num_symbols * number_of_search_space_per_slot;
-
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0];
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1];
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration;
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
-
- dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = UE_mac->initial_bwp_dl.N_RB;
+
+ dl_config->number_pdus=0;
+
+ ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot);
+
return 0;
diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
index 5873c84d8fd7902cbeace7cb2ea3b93abc297a9d..b0565c6f69e6ba5c50d07e76f07d8bda561769c1 100755
--- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
+++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
@@ -223,7 +223,7 @@ int handle_bcch_bch(UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, u
\param pduP pointer to pdu*/
int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index, uint32_t sibs_mask, uint8_t *pduP, uint32_t pdu_len);
-int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type);
+int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci);
#endif
diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c
index ea3e33f16d7f386c95c6c62946e8cc98363c3e2c..43e94041f68db58e76eadb557e6b15778b758ea9 100644
--- a/openair2/RRC/NR/rrc_gNB_nsa.c
+++ b/openair2/RRC/NR/rrc_gNB_nsa.c
@@ -41,7 +41,6 @@
void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) {
struct rrc_gNB_ue_context_s *ue_context_p = NULL;
- int rnti = taus()&65535;
OCTET_STRING_t *ueCapabilityRAT_Container_nr;
OCTET_STRING_t *ueCapabilityRAT_Container_MRDC;
int list_size;
@@ -56,7 +55,6 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerL
AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n");
// decode and store capabilities
ue_context_p = rrc_gNB_allocate_new_UE_context(rrc);
- ue_context_p->ue_id_rnti = rnti;
asn_dec_rval_t dec_rval = uper_decode(NULL,
&asn_DEF_NR_UE_NR_Capability,
@@ -127,7 +125,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_
ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t));
fill_default_rbconfig(ue_context_p->ue_context.rb_config);
-
+ ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity;
NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config));
memset((void*)CG_Config,0,sizeof(*CG_Config));
generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config);