diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index eacc8d14b88b59410346886e1727e6fb7725c085..b7c6a6a5619d3760fd8c8ac7d4af3a7c214e2509 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -444,8 +444,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, //mbsfn_status[CC_id] = 0; // clear vrb_maps - memset(cc[CC_id].vrb_map, 0, 100); - memset(cc[CC_id].vrb_map_UL, 0, 100); + memset(cc[CC_id].vrb_map, 0, 275); + memset(cc[CC_id].vrb_map_UL, 0, 275); clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame, slot); } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index 5f7ae0c7ddd48df18c8c43046ca8d16d11ab708b..b073029da0cf4685f236c36828a218ca87bdfd78 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -550,7 +550,6 @@ void nr_generate_Msg2(module_id_t module_idP, uint16_t RA_rnti = ra->RA_rnti; long locationAndBandwidth; - // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id; // check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD // get the BW of the PDCCH for PDCCH size and RAR PDSCH size @@ -740,6 +739,11 @@ void nr_generate_Msg2(module_id_t module_idP, nr_mac->TX_req[CC_id].Number_of_PDUs++; nr_mac->TX_req[CC_id].Slot = slotP; memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length); + + /* mark the corresponding RBs as used */ + uint8_t *vrb_map = cc[CC_id].vrb_map; + for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) + vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1; } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c index 0e8fb0aca2412e72f538e5d6af77c036aa33d59c..989d6fb9527cba12f1dfefe3a433b2843909f6cf 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c @@ -137,6 +137,11 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){ dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag = 1; dl_config_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload = (*(uint32_t*)cc->MIB_pdu.payload) & ((1<<24)-1); dl_req->nPDUs++; + + uint8_t *vrb_map = cc[CC_id].vrb_map; + const int rbStart = dl_config_pdu->ssb_pdu.ssb_pdu_rel15.ssbOffsetPointA; + for (int rb = 0; rb < 20; rb++) + vrb_map[rbStart + rb] = 1; } } } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index c666cc66da28138b539b293b62e8f651b59d2fc1..61015c27eb3f880814c4747cbaf6009b2274b186 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -517,9 +517,19 @@ void nr_simple_dlsch_preprocessor(module_id_t module_id, sched_ctrl->time_domain_allocation = 2; // Freq-demain allocation + uint8_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map; const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275); - sched_ctrl->rbSize = bwpSize; - sched_ctrl->rbStart = 0; + int rbStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, 275); + while (rbStart < bwpSize && vrb_map[rbStart]) rbStart++; + int rbSize = 1; + while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize]) rbSize++; + DevAssert(rbSize >= 3); /* just ensure we have at least 3 RBs */ + sched_ctrl->rbSize = rbSize; + sched_ctrl->rbStart = rbStart; + + /* mark the corresponding RBs as used */ + for (int rb = 0; rb < sched_ctrl->rbSize; rb++) + vrb_map[rb + sched_ctrl->rbStart] = 1; // modulation scheme sched_ctrl->mcsTableIdx = 0; diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h index 4c1c440617fbcfe365d944405aa45d7ec51a153d..2bedb0750f0e0e18d756914df9c6127c08e53746 100644 --- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h +++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h @@ -172,9 +172,9 @@ typedef struct { /// Template for RA computations NR_RA_t ra[NR_NB_RA_PROC_MAX]; /// VRB map for common channels - uint8_t vrb_map[100]; + uint8_t vrb_map[275]; /// VRB map for common channels and retransmissions by PHICH - uint8_t vrb_map_UL[100]; + uint8_t vrb_map_UL[275]; /// number of subframe allocation pattern available for MBSFN sync area uint8_t num_sf_allocation_pattern; } NR_COMMON_channels_t;