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dyyu
openairinterface5G
Commits
ce29fca6
Commit
ce29fca6
authored
Jun 12, 2017
by
Elena Lukashova
Browse files
Enabling new code for dci format 2 and incrementing round in UE->dlsch[subframe&0x1][0][1].
parent
39e74bc8
Changes
2
Hide whitespace changes
Inline
Side-by-side
openair1/PHY/LTE_TRANSPORT/dci_tools.c
View file @
ce29fca6
...
...
@@ -5045,13 +5045,6 @@ int check_dci_format2_2a_coherency(DCI_format_t dci_format,
}
/*
if((pdlsch0_harq->round > 0) && (mcs1 != pdlsch0_harq->mcs))
{
// DCI false detection
return(0);
}*/
if
((
pdlsch0_harq
->
round
==
0
)
&&
(
rv1
>
0
))
{
...
...
@@ -5667,14 +5660,11 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
uint8_t
ndi1
=
pdci_info_extarcted
->
ndi1
;
uint8_t
ndi2
=
pdci_info_extarcted
->
ndi2
;
uint8_t
TB0_active
=
0
;
uint8_t
TB1_active
=
0
;
uint8_t
TB0_active
=
1
;
uint8_t
TB1_active
=
1
;
// printf("inside prepare pdlsch1->pmi_alloc %d \n",pdlsch1->pmi_alloc);
// check if either TB is disabled (see 36-213 V8.6 p. 26)
TB0_active
=
1
;
TB1_active
=
1
;
if
((
rv1
==
1
)
&&
(
mcs1
==
0
))
{
TB0_active
=
0
;
...
...
@@ -5722,6 +5712,16 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
dlsch1_harq
->
codeword
=
0
;
}
if
(
!
TB0_active
&&
TB1_active
){
dlsch1_harq
->
codeword
=
0
;
}
if
(
TB0_active
&&
!
TB1_active
){
dlsch0_harq
->
codeword
=
0
;
}
if
(
TB0_active
==
0
)
{
dlsch0_harq
->
status
=
SCH_IDLE
;
pdlsch0
->
active
=
0
;
...
...
@@ -5798,7 +5798,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
compute_precoding_info_1cw
(
tpmi
,
pdlsch0
->
pmi_alloc
,
frame_parms
,
dlsch0_harq
);
}
else
{
compute_precoding_info_1cw
(
tpmi
,
pdlsch1
->
pmi_alloc
,
frame_parms
,
dlsch1_harq
);
printf
(
"I am doing compute_precoding_info_1cw with tpmi %d
\n
"
,
tpmi
);
//
printf("I am doing compute_precoding_info_1cw with tpmi %d \n", tpmi);
}
//printf(" UE DCI harq0 MIMO mode = %d\n", dlsch0_harq->mimo_mode);
if
((
frame_parms
->
mode1_flag
==
1
)
&&
(
TB0_active
))
...
...
@@ -5829,7 +5829,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
dlsch0_harq
->
first_tx
=
0
;
}
}
else
if
(
rv1
!=
0
)
/*
else if (rv1 != 0 )
//NDI has not been toggled but rv was increased by eNB: retransmission
{
if(dlsch0_harq->status == SCH_IDLE) {
...
...
@@ -5839,8 +5839,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
pdlsch0->harq_ack[subframe].ack = 1;
pdlsch0->harq_ack[subframe].harq_id = harq_pid;
pdlsch0->harq_ack[subframe].send_harq_status = 1;
}
}
}*/
// if Imcs in [29..31] TBS is assumed to be as determined from DCI transported in the latest
// PDCCH for the same trasport block using Imcs in [0 .. 28]
...
...
@@ -5865,10 +5864,12 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
// printf("[DCI UE 3]: dlsch0_harq status %d , dlsch1_harq status %d\n", dlsch0_harq->status, dlsch1_harq->status);
if
(
(
TB1_active
)
&&
(
pdlsch1
->
active
==
1
))
{
if
(
TB1_active
)
{
// printf("TB1 ndi2 =%d, dlsch1_harq->DCINdi =%d, dlsch1_harq->first_tx = %d\n", ndi2, dlsch1_harq->DCINdi, dlsch1_harq->first_tx);
if
((
ndi2
!=
dlsch1_harq
->
DCINdi
)
||
(
dlsch1_harq
->
first_tx
==
1
))
{
dlsch1_harq
->
round
=
0
;
dlsch1_harq
->
status
=
ACTIVE
;
dlsch1_harq
->
DCINdi
=
ndi2
;
//LOG_I(PHY,"[UE] DLSCH: New Data Indicator CW1 subframe %d (pid %d, round %d)\n",
// subframe,harq_pid,dlsch0_harq->round);
if
(
dlsch1_harq
->
first_tx
==
1
)
{
...
...
@@ -5876,7 +5877,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
dlsch1_harq
->
first_tx
=
0
;
}
}
else
if
(
rv1
!=
0
)
/*
else if (rv1 != 0 )
//NDI has not been toggled but rv was increased by eNB: retransmission
{
if(dlsch1_harq->status == SCH_IDLE) {
...
...
@@ -5887,7 +5888,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
pdlsch1->harq_ack[subframe].harq_id = harq_pid;
pdlsch1->harq_ack[subframe].send_harq_status = 1;
}
}
}
*/
// if Imcs in [29..31] TBS is assumed to be as determined from DCI transported in the latest
// PDCCH for the same trasport block using Imcs in [0 .. 28]
...
...
@@ -5909,7 +5910,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
}
#ifdef DEBUG_HARQ
/*
#ifdef DEBUG_HARQ
printf("[DCI UE]: TB0_active %d , TB1_active %d\n", TB0_active, TB1_active);
if (dlsch0 != NULL && dlsch1 != NULL)
printf("[DCI UE] dlsch0_harq status = %d, dlsch1_harq status = %d\n", dlsch0_harq->status, dlsch1_harq->status);
...
...
@@ -5917,7 +5918,7 @@ void prepare_dl_decoding_format2_2A(DCI_format_t dci_format,
printf("[DCI UE] dlsch0_harq NULL dlsch1_harq status = %d\n", dlsch1_harq->status);
else if (dlsch0 != NULL && dlsch1 == NULL)
printf("[DCI UE] dlsch1_harq NULL dlsch0_harq status = %d\n", dlsch0_harq->status);
#endif
#endif
*/
}
int
generate_ue_dlsch_params_from_dci
(
int
frame
,
...
...
@@ -6138,626 +6139,7 @@ int generate_ue_dlsch_params_from_dci(int frame,
case
format2
:
{
switch
(
frame_parms
->
N_RB_DL
)
{
case
6
:
if
(
frame_parms
->
nb_antenna_ports_eNB
==
2
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rv1
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_1_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rv1
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_1_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
if
(
frame_parms
->
nb_antenna_ports_eNB
==
4
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rv1
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_1_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rv1
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_1_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
{
LOG_E
(
PHY
,
"UE: subframe %d Format2 DCI: unsupported number of TX antennas %d
\n
"
,
subframe
,
frame_parms
->
nb_antenna_ports_eNB
);
}
break
;
case
25
:
if
(
frame_parms
->
nb_antenna_ports_eNB
==
2
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_5MHz_2A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_5MHz_2A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
if
(
frame_parms
->
nb_antenna_ports_eNB
==
4
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_5MHz_4A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_5MHz_4A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
break
;
case
50
:
if
(
frame_parms
->
nb_antenna_ports_eNB
==
2
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_10MHz_2A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_10MHz_2A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
if
(
frame_parms
->
nb_antenna_ports_eNB
==
4
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_10MHz_4A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_10MHz_4A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
{
LOG_E
(
PHY
,
"UE: Format2 DCI: unsupported number of TX antennas %d
\n
"
,
frame_parms
->
nb_antenna_ports_eNB
);
}
break
;
case
100
:
if
(
frame_parms
->
nb_antenna_ports_eNB
==
2
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_20MHz_2A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_20MHz_2A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
if
(
frame_parms
->
nb_antenna_ports_eNB
==
4
)
{
if
(
frame_type
==
TDD
)
{
mcs1
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_20MHz_4A_TDD_t
*
)
dci_pdu
)
->
tpmi
;
}
else
{
mcs1
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs1
;
mcs2
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
mcs2
;
rballoc
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
rballoc
;
rah
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
rah
;
rv1
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv1
;
rv2
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
rv2
;
ndi1
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi1
;
ndi2
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
ndi2
;
harq_pid
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
harq_pid
;
tbswap
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
tb_swap
;
tpmi
=
((
DCI2_20MHz_4A_FDD_t
*
)
dci_pdu
)
->
tpmi
;
}
}
else
{
LOG_E
(
PHY
,
"UE: Format2 DCI: unsupported number of TX antennas %d
\n
"
,
frame_parms
->
nb_antenna_ports_eNB
);
}
break
;
}
if
(
harq_pid
>=
8
)
{
LOG_E
(
PHY
,
"Format 2_2A: harq_pid=%d >= 8
\n
"
,
harq_pid
);
return
(
-
1
);
}
// check if either TB is disabled (see 36-213 V8.6 p. 26)
TB0_active
=
1
;
TB1_active
=
1
;
if
((
rv1
==
1
)
&&
(
mcs1
==
0
))
{
TB0_active
=
0
;
}
if
((
rv2
==
1
)
&&
(
mcs2
==
0
))
{
TB1_active
=
0
;
}
#ifdef DEBUG_HARQ
printf
(
"[DCI UE]: TB0 status %d , TB1 status %d
\n
"
,
TB0_active
,
TB1_active
);
#endif
//printf("RV TB0 = %d\n", rv1);
if
(
TB0_active
&&
TB1_active
&&
tbswap
==
0
)
{
//dlsch0, dlsch0_harq are at the TB level
dlsch0
=
dlsch
[
0
];
dlsch1
=
dlsch
[
1
];
dlsch0
->
active
=
1
;
dlsch1
->
active
=
1
;
dlsch0_harq
=
dlsch0
->
harq_processes
[
harq_pid
];
dlsch1_harq
=
dlsch1
->
harq_processes
[
harq_pid
];
dlsch0_harq
->
mcs
=
mcs1
;
dlsch1_harq
->
mcs
=
mcs2
;
dlsch0_harq
->
rvidx
=
rv1
;
dlsch1_harq
->
rvidx
=
rv2
;
dlsch0_harq
->
status
=
ACTIVE
;
dlsch1_harq
->
status
=
ACTIVE
;
dlsch0_harq
->
codeword
=
0
;
dlsch1_harq
->
codeword
=
1
;
#ifdef DEBUG_HARQ
printf
(
"[DCI UE]: BOTH ACTIVE
\n
"
);
#endif
}
else
if
(
TB0_active
&&
TB1_active
&&
tbswap
==
1
)
{
dlsch0
=
dlsch
[
0
];
dlsch1
=
dlsch
[
1
];
dlsch0
->
active
=
1
;
dlsch1
->
active
=
1
;
dlsch0_harq
=
dlsch0
->
harq_processes
[
harq_pid
];
dlsch1_harq
=
dlsch1
->
harq_processes
[
harq_pid
];
dlsch0_harq
->
mcs
=
mcs1
;
dlsch1_harq
->
mcs
=
mcs2
;
dlsch0_harq
->
rvidx
=
rv1
;
dlsch1_harq
->
rvidx
=
rv2
;
dlsch0_harq
->
status
=
ACTIVE
;
dlsch1_harq
->
status
=
ACTIVE
;
dlsch0_harq
->
codeword
=
1
;
dlsch1_harq
->
codeword
=
0
;
}
else
if
(
TB0_active
&&
(
TB1_active
==
0
))
{
dlsch0
=
dlsch
[
0
];
dlsch0
->
active
=
1
;
dlsch0_harq
=
dlsch0
->
harq_processes
[
harq_pid
];
dlsch0_harq
->
mcs
=
mcs1
;
dlsch0_harq
->
rvidx
=
rv1
;
dlsch0_harq
->
status
=
ACTIVE
;
dlsch0_harq
->
codeword
=
0
;
dlsch1
=
NULL
;
dlsch1_harq
=
NULL
;
#ifdef DEBUG_HARQ
printf
(
"[DCI UE]: TB1 is deactivated, retransmit TB0 transmit in TM6
\n
"
);
#endif
}
else
if
((
TB0_active
==
0
)
&&
TB1_active
)
{
dlsch1
=
dlsch
[
1
];
dlsch1
->
active
=
1
;
dlsch1_harq
=
dlsch1
->
harq_processes
[
harq_pid
];
dlsch1_harq
->
mcs
=
mcs2
;
dlsch1_harq
->
rvidx
=
rv2
;
dlsch1_harq
->
status
=
ACTIVE
;
dlsch1_harq
->
codeword
=
0
;
dlsch0
=
NULL
;
dlsch0_harq
=
NULL
;
#ifdef DEBUG_HARQ
printf
(
"[DCI UE]: TB0 is deactivated, retransmit TB1 transmit in TM6
\n
"
);
#endif
}
if
(
dlsch0
!=
NULL
){
dlsch0
->
current_harq_pid
=
harq_pid
;
dlsch0
->
harq_ack
[
subframe
].
harq_id
=
harq_pid
;
}
if
(
dlsch1
!=
NULL
){
dlsch1
->
current_harq_pid
=
harq_pid
;
dlsch1
->
harq_ack
[
subframe
].
harq_id
=
harq_pid
;
}
if
(
dlsch0_harq
!=
NULL
){
conv_rballoc
(
rah
,
rballoc
,
frame_parms
->
N_RB_DL
,
dlsch0_harq
->
rb_alloc_even
);
dlsch0_harq
->
rb_alloc_odd
[
0
]
=
dlsch0_harq
->
rb_alloc_even
[
0
];
dlsch0_harq
->
rb_alloc_odd
[
1
]
=
dlsch0_harq
->
rb_alloc_even
[
1
];
dlsch0_harq
->
rb_alloc_odd
[
2
]
=
dlsch0_harq
->
rb_alloc_even
[
2
];
dlsch0_harq
->
rb_alloc_odd
[
3
]
=
dlsch0_harq
->
rb_alloc_even
[
3
];
if
(
dlsch1_harq
!=
NULL
){
dlsch1_harq
->
rb_alloc_even
[
0
]
=
dlsch0_harq
->
rb_alloc_even
[
0
];
dlsch1_harq
->
rb_alloc_even
[
1
]
=
dlsch0_harq
->
rb_alloc_even
[
1
];
dlsch1_harq
->
rb_alloc_even
[
2
]
=
dlsch0_harq
->
rb_alloc_even
[
2
];
dlsch1_harq
->
rb_alloc_even
[
3
]
=
dlsch0_harq
->
rb_alloc_even
[
3
];
dlsch1_harq
->
rb_alloc_odd
[
0
]
=
dlsch0_harq
->
rb_alloc_odd
[
0
];
dlsch1_harq
->
rb_alloc_odd
[
1
]
=
dlsch0_harq
->
rb_alloc_odd
[
1
];
dlsch1_harq
->
rb_alloc_odd
[
2
]
=
dlsch0_harq
->
rb_alloc_odd
[
2
];
dlsch1_harq
->
rb_alloc_odd
[
3
]
=
dlsch0_harq
->
rb_alloc_odd
[
3
];
dlsch1_harq
->
nb_rb
=
dlsch0_harq
->
nb_rb
;
}
dlsch0_harq
->
nb_rb
=
conv_nprb
(
rah
,
rballoc
,
frame_parms
->
N_RB_DL
);
}
else
if
((
dlsch0_harq
==
NULL
)
&&
(
dlsch1_harq
!=
NULL
)){
conv_rballoc
(
rah
,
rballoc
,
frame_parms
->
N_RB_DL
,
dlsch1_harq
->
rb_alloc_even
);
dlsch1_harq
->
rb_alloc_odd
[
0
]
=
dlsch1_harq
->
rb_alloc_even
[
0
];
dlsch1_harq
->
rb_alloc_odd
[
1
]
=
dlsch1_harq
->
rb_alloc_even
[
1
];
dlsch1_harq
->
rb_alloc_odd
[
2
]
=
dlsch1_harq
->
rb_alloc_even
[
2
];
dlsch1_harq
->
rb_alloc_odd
[
3
]
=
dlsch1_harq
->
rb_alloc_even
[
3
];
dlsch1_harq
->
nb_rb
=
conv_nprb
(
rah
,
rballoc
,
frame_parms
->
N_RB_DL
);
}
if
(
dlsch0_harq
!=
NULL
)
{
dlsch0_harq
->
delta_PUCCH
=
delta_PUCCH_lut
[
TPC
&
3
];
}
if
(
dlsch1_harq
!=
NULL
)
{
dlsch1_harq
->
delta_PUCCH
=
delta_PUCCH_lut
[
TPC
&
3
];
}
// assume one layer per codeword (2 antenna port case)
if
(
dlsch0_harq
!=
NULL
)
dlsch0_harq
->
Nl
=
1
;
if
(
dlsch1_harq
!=
NULL
)
dlsch1_harq
->
Nl
=
1
;
#ifdef DEBUG_HARQ
printf
(
"[DCI UE] tpmi = %d
\n
"
,
tpmi
);
#endif
if
((
dlsch0
!=
NULL
)
&&
(
dlsch1
!=
NULL
)){
//two CW active
dlsch0_harq
->
dl_power_off
=
1
;
dlsch1_harq
->
dl_power_off
=
1
;
switch
(
tpmi
)
{
case
0
:
dlsch0_harq
->
mimo_mode
=
DUALSTREAM_UNIFORM_PRECODING1
;
dlsch1_harq
->
mimo_mode
=
DUALSTREAM_UNIFORM_PRECODING1
;
dlsch0_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
0
,
1
);
dlsch1_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
0
,
1
);
break
;
case
1
:
dlsch0_harq
->
mimo_mode
=
DUALSTREAM_UNIFORM_PRECODINGj
;
dlsch1_harq
->
mimo_mode
=
DUALSTREAM_UNIFORM_PRECODINGj
;
dlsch0_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
1
,
1
);
dlsch1_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
1
,
1
);
break
;
case
2
:
// PUSCH precoding
dlsch0_harq
->
mimo_mode
=
DUALSTREAM_PUSCH_PRECODING
;
dlsch1_harq
->
mimo_mode
=
DUALSTREAM_PUSCH_PRECODING
;
if
(
tbswap
==
0
){
dlsch0_harq
->
pmi_alloc
=
dlsch0
->
pmi_alloc
;
dlsch1_harq
->
pmi_alloc
=
dlsch0
->
pmi_alloc
^
0x1555
;
}
else
{
dlsch1_harq
->
pmi_alloc
=
dlsch0
->
pmi_alloc
;
dlsch0_harq
->
pmi_alloc
=
dlsch0
->
pmi_alloc
^
0x1555
;
}
break
;
default:
break
;
}
}
else
if
((
dlsch0
!=
NULL
)
&&
(
dlsch1
==
NULL
))
{
// only CW 0 active
dlsch0_harq
->
dl_power_off
=
1
;
switch
(
tpmi
)
{
case
0
:
dlsch0_harq
->
mimo_mode
=
ALAMOUTI
;
break
;
case
1
:
dlsch0_harq
->
mimo_mode
=
UNIFORM_PRECODING11
;
dlsch0_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
0
,
0
);
break
;
case
2
:
dlsch0_harq
->
mimo_mode
=
UNIFORM_PRECODING1m1
;
dlsch0_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
1
,
0
);
break
;
case
3
:
dlsch0_harq
->
mimo_mode
=
UNIFORM_PRECODING1j
;
dlsch0_harq
->
pmi_alloc
=
pmi_extend
(
frame_parms
,
2
,
0
);
break
;
case
4
: