1. 25 Sep, 2017 1 commit
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  3. 22 Sep, 2017 2 commits
  4. 21 Sep, 2017 4 commits
  5. 19 Sep, 2017 1 commit
  6. 15 Sep, 2017 1 commit
  7. 14 Sep, 2017 1 commit
  8. 17 Aug, 2017 3 commits
  9. 14 Aug, 2017 1 commit
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  11. 11 Aug, 2017 1 commit
  12. 10 Aug, 2017 1 commit
  13. 08 Aug, 2017 1 commit
    • knopp's avatar
      L1/L2 scheduling extensions for BL/CE operation, BR random-access procedure,... · ad98f5aa
      knopp authored
      L1/L2 scheduling extensions for BL/CE operation, BR random-access procedure, BR PRACH detection. Still untested, but compilation succeeds. Missing elements in L2 - PUSCH programming for Msg3, Msg4 retransmission programming for BL/CE. DLSCH/ULSCH programming for UE-specific DLSCH/ULSCH for BL/CE
      ad98f5aa
  14. 25 Jul, 2017 2 commits
  15. 24 Jul, 2017 1 commit
  16. 19 Jul, 2017 1 commit
  17. 06 Jul, 2017 1 commit
  18. 04 Jun, 2017 1 commit
  19. 22 May, 2017 1 commit
  20. 19 May, 2017 4 commits
  21. 18 May, 2017 2 commits
  22. 15 May, 2017 2 commits
  23. 12 May, 2017 1 commit
    • Gabriel's avatar
      bug fixes from Fujitsu (bug 37) · ad6d0ac5
      Gabriel authored and Cedric Roux's avatar Cedric Roux committed
      ----------------------------------------------------------
      bug 37
      
      Ttile:
      Sending side is as follows.
      rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
      So, 2 bit shift looks correct.
      
      Bug Location:
      ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
      ----------------------------------------------------------
      ad6d0ac5
  24. 03 May, 2017 4 commits