Gabriel authored May 11, 2017 and Cédric Roux committed May 12, 2017

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bug 37

Ttile:
Sending side is as follows.
rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
So, 2 bit shift looks correct.

Bug Location:
ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
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