Commit b7b057a1 authored by INOUE Yoshio's avatar INOUE Yoshio

Merge remote-tracking branch 'origin/develop' into issue-232-pucch3

parents 63b10db6 c124e32a
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......@@ -230,7 +230,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t;
/// DCI Format Type 0 (20 MHz,TDD1-6, 27 bits)
struct DCI0_20MHz_TDD_1_6 {
/// Padding
uint32_t padding:2;
uint32_t padding:3;
/// CQI request
uint32_t cqi_req:1;
/// DAI
......
......@@ -70,7 +70,7 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
uint32_t bcch_pdu;
uint64_t dlsch_pdu;
LOG_I(PHY,"frame %d, subframe %d, transmission_mode %d\n",proc->frame_tx,proc->subframe_tx,transmission_mode);
LOG_D(PHY,"frame %d, subframe %d, transmission_mode %d\n",proc->frame_tx,proc->subframe_tx,transmission_mode);
DCI_pdu->Num_common_dci = 0;
DCI_pdu->Num_ue_spec_dci=0;
......@@ -380,25 +380,25 @@ void fill_dci(DCI_PDU *DCI_pdu,PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc)
if (eNB->frame_parms.frame_type == FDD) {
DCI_pdu->dci_alloc[0].dci_length = sizeof_DCI1_20MHz_FDD_t;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->rballoc = rballoc; //computeRIV(100,10,3);
harq_pid_value = ( ((proc->frame_tx * 10) + subframe) % 8 );
if (!(subframe&1)) // even subframe
dci_ndi_toggle_tmp = &(dci_ndi_toggle_even[harq_pid_value]);
else // odd subframe
dci_ndi_toggle_tmp = &(dci_ndi_toggle_odd[harq_pid_value]);
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->rballoc = 0x1ffffff; //rballoc; //computeRIV(100,10,3);
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->TPC = 0;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->harq_pid = subframe % 5;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->harq_pid = harq_pid_value;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->mcs = eNB->target_ue_dl_mcs;
//((DCI1_5MHz_FDD_t *)&dlsch_pdu)->mcs = (unsigned char) ((eNB->frame%1024)%28);
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->ndi = subframe / 5;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->ndi = (*dci_ndi_toggle_tmp);
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->rv = 0;
((DCI1_20MHz_FDD_t *)&dlsch_pdu)->rah = 0;
(*dci_ndi_toggle_tmp) = ((*dci_ndi_toggle_tmp) + 1) & 1;
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&dlsch_pdu,sizeof(DCI1_20MHz_FDD_t));
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->rballoc = rballoc;
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->TPC = 0;
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->harq_pid = subframe % 5;
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->mcs = eNB->target_ue_dl_mcs;
//((DCI1_5MHz_FDD_t *)&dlsch_pdu)->mcs = (unsigned char) ((eNB->frame%1024)%28);
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->ndi = subframe/5;
((DCI1_5MHz_FDD_t *)&dlsch_pdu)->rv = 0;
memcpy((void*)&DCI_pdu->dci_alloc[0].dci_pdu[0],(void *)&dlsch_pdu,sizeof(DCI1_5MHz_TDD_t));
/*
//user2
DCI_pdu->dci_alloc[1].dci_length = sizeof_DCI1_5MHz_TDD_t;
......
......@@ -63,7 +63,7 @@
# define RLC_AM_MIN_SEGMENT_SIZE_REQUEST 8
/** Max SDUs that can fit in a PDU. */
# define RLC_AM_MAX_SDU_IN_PDU 32
# define RLC_AM_MAX_SDU_IN_PDU 128
/** Max fragments for a SDU. */
# define RLC_AM_MAX_SDU_FRAGMENTS 32
......
......@@ -53,7 +53,7 @@
// UM_Window_Size = 512 when a 10 bit SN is configured and UM_Window_Size = 0
// when the receiving UM RLC entity is configured for MCCH or MTCH.
// li field (values shifted 1 bit left)
# define RLC_UM_SEGMENT_NB_MAX_LI_PER_PDU 24
# define RLC_UM_SEGMENT_NB_MAX_LI_PER_PDU 128
//----------------------------------------------------------
// Events defined for state model of the acknowledged mode entity
/** Internal event defined for state model of the RLC UM. */
......
......@@ -183,7 +183,7 @@ int rlc_um_read_length_indicators(unsigned char**data_ppP, rlc_um_e_li_t* e_liP,
// AssertFatal(*data_size_pP >= 0, "Invalid data_size!");
}
if (*num_li_pP >= RLC_UM_SEGMENT_NB_MAX_LI_PER_PDU) {
if (*num_li_pP > RLC_UM_SEGMENT_NB_MAX_LI_PER_PDU) {
return -1;
}
}
......
......@@ -34,7 +34,7 @@ eNBs =
downlink_frequency = 2680000000L;
uplink_frequency_offset = -120000000;
Nid_cell = 0;
N_RB_DL = 50;
N_RB_DL = 25;
Nid_cell_mbsfn = 0;
nb_antenna_ports = 1;
nb_antennas_tx = 1;
......@@ -62,7 +62,7 @@ eNBs =
pusch_nDMRS1 = 0;
phich_duration = "NORMAL";
phich_resource = "ONESIXTH";
srs_enable = "ENABLE";
srs_enable = "DISABLE";
srs_BandwidthConfig =2;
srs_SubframeConfig =13;
srs_ackNackST ="DISABLE";
......
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