1. 12 Jun, 2017 3 commits
  2. 08 Jun, 2017 3 commits
  3. 07 Jun, 2017 3 commits
  4. 22 May, 2017 1 commit
  5. 19 May, 2017 4 commits
  6. 18 May, 2017 2 commits
  7. 15 May, 2017 2 commits
  8. 12 May, 2017 1 commit
    • Gabriel's avatar
      bug fixes from Fujitsu (bug 37) · ad6d0ac5
      Gabriel authored
      ```-------------------------------------------------------
      bug 37
      
      Ttile:
      Sending side is as follows.
      rar[3] = (((mcs&0x7)<<5)) | ((TPC&7)<<2) | ((ULdelay&1)<<1) | (cqireq&1);
      So, 2 bit shift looks correct.
      
      Bug Location:
      ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>3)&7;//rar->TPC;
      ```
      
      -------------------------------------------------------
      ad6d0ac5
  9. 03 May, 2017 4 commits
  10. 02 May, 2017 1 commit
  11. 26 Apr, 2017 1 commit
  12. 25 Apr, 2017 3 commits
  13. 24 Apr, 2017 2 commits
  14. 21 Apr, 2017 1 commit
  15. 14 Apr, 2017 1 commit
    • Cedric Roux's avatar
      hotfix: fix TDD 20MHz DCI0 structure · 20a2bfd1
      Cedric Roux authored
      In 20MHz the UE didn't do any uplink granted by DCI0.
      It was replying to RAR, so uplink decoding was okay.
      
      Turns out the DCI0 structure for TDD was wrong.
      20a2bfd1
  16. 12 Apr, 2017 1 commit
  17. 08 Apr, 2017 1 commit
  18. 04 Apr, 2017 1 commit
  19. 28 Mar, 2017 4 commits
  20. 27 Mar, 2017 1 commit
    • Elena Lukashova's avatar
      Fixing a bug in HARQ for SIC. · 800f66b3
      Elena Lukashova authored
      Now the llrs after SIC procedure are updated.
      In dlsim_tm in case of TB0_active==-1,
      the llr were taken from the wrong buffer, and in dlsch_demodulation
      the SIC llrs were written into the wrong buffer in the same case.
      800f66b3