[GITLAB] - A technical upgrade is planned today at 6PM on our GITLAB server.

Commit 2d4cd8bf authored by aynie's avatar aynie

add scripts

parent 765ceb93
Pipeline #1622 skipped
image:
{
[bootloader]build/fsbl/executable.elf
build/vv/top.runs/impl_1/top_wrapper.bit
build/uboot/u-boot.elf
}
#
# Copyright (C) Telecom ParisTech
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
if { $argc != 3 } {
puts "usage: hsi -mode batch -quiet -notrace -source dts.tcl -tclargs <hardware-description-file> <path-to-device-tree-xlnx> <local-device-tree-directory>"
} else {
set hdf [lindex $argv 0]
set xdts [lindex $argv 1]
set ldts [lindex $argv 2]
open_hw_design $hdf
set_repo_path $xdts
create_sw_design device-tree -os device_tree -proc ps7_cortexa9_0
generate_target -dir $ldts
}
#
# Copyright (C) Telecom ParisTech
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
if { $argc != 2 } {
puts "usage: hsi -mode batch -quiet -notrace -source fsbl.tcl -tclargs <hardware-description-file> <fsbl-build-directory>"
} else {
set hdf [lindex $argv 0]
set dir [lindex $argv 1]
set design [ open_hw_design ${hdf} ]
generate_app -hw $design -os standalone -proc ps7_cortexa9_0 -app zynq_fsbl -sw fsbl -dir ${dir}
}
#
# Copyright (C) Telecom ParisTech
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
# Create new ILA core named $name, with clock $clock and connect it to all nets in list $nets. Add to ILA core as many debug ports as needed. ILA core properties have reasonable default values but can also be passed different values
proc add_ila_core { name clock nets { data_depth 1024 } { trigin_en false } { trigout_en false } { input_pipe_stages 1 } { en_strg_qual true } { adv_trigger true } { all_probe_same_mu true } { all_probe_same_mu_cnt 4 } } {
puts "Instanciating ILA debug core"
# Create ILA debug core
set debug_core [ create_debug_core $name ila ]
# Set ILA debug core properties
set_property C_DATA_DEPTH $data_depth $debug_core
set_property C_TRIGIN_EN $trigin_en $debug_core
set_property C_TRIGOUT_EN $trigout_en $debug_core
set_property C_INPUT_PIPE_STAGES $input_pipe_stages $debug_core
set_property C_EN_STRG_QUAL $en_strg_qual $debug_core
set_property C_ADV_TRIGGER $adv_trigger $debug_core
set_property ALL_PROBE_SAME_MU $all_probe_same_mu $debug_core
set_property ALL_PROBE_SAME_MU_CNT $all_probe_same_mu_cnt $debug_core
# Connect clock $clock to ILA debug core. Create debug port if needed
set clock_debug_port [ get_debug_ports $debug_core/clk ]
if { [ llength $clock_debug_port ] == 0 } {
set clock_debug_port [ create_debug_port $debug_core clk ]
}
connect_debug_port $clock_debug_port $clock
# Number of nets to connect
set num_nets [ llength $nets ]
# Create missing debug ports if needed
for { set num_debug_ports [ llength [ get_debug_ports $debug_core/probe* ] ] } { $num_debug_ports < $num_nets } { incr num_debug_ports 1 } {
create_debug_port $debug_core probe
}
# List of debug ports
set debug_ports [ get_debug_ports $debug_core/probe* ]
# For each net to connect
foreach net $nets {
# Pick first debug port
set debug_port [ lindex $debug_ports 0 ]
# Search net in design
set real_net [ get_nets -quiet ${net} ]
# If net not found, search bus
if { [ llength $real_net ] == 0 } {
set real_net [ lsort -dictionary [ get_nets -quiet ${net}[*] ] ]
}
# Width of net or bus
set net_width [ llength $real_net ]
# If width not 0 (net or bus found)
if { $net_width != 0 } {
# Set width of debug port
set_property port_width $net_width $debug_port
puts " Connecting $net ($net_width bits) to ILA debug core $debug_core, debug port $debug_port"
# Connect net or bus
connect_debug_port $debug_port $real_net
# Remove debug port from list
set debug_ports [ lreplace $debug_ports 0 0 ]
} else {
puts " Warning: ${net} not found"
}
}
}
devicetree_load_address=0x8a000000
kernel_load_address=0x8a080000
ramdisk_load_address=0x8c000000
fdt_high=0xffffffff
initrd_high=0xffffffff
#
# Copyright (C) Telecom ParisTech
#
# This file must be used under the terms of the CeCILL. This source
# file is licensed as described in the file COPYING, which you should
# have received as part of this distribution. The terms are also
# available at:
# http://www.cecill.info/licences/Licence_CeCILL_V1.1-US.txt
#
proc usage {} {
puts "usage: vivado -mode batch -source <script> -tclargs <rootdir> <builddir> \[<ila>\]"
puts " <rootdir>: absolute path of sab4z root directory"
puts " <builddir>: absolute path of build directory"
puts " <ila>: embed Integrated Logic Analyzer (0 or 1, default 0)"
exit -1
}
if { $argc == 3 } {
set rootdir [lindex $argv 0]
set builddir [lindex $argv 1]
set ila [lindex $argv 2]
if { $ila != 0 && $ila != 1 } {
usage
}
} else {
usage
}
cd $builddir
source $rootdir/scripts/ila.tcl
###################
# Create SAB4Z IP #
###################
create_project -part xc7z010clg400-1 -force sab4z sab4z
add_files $rootdir/hdl/axi_pkg.vhd $rootdir/hdl/debouncer.vhd $rootdir/hdl/sab4z.vhd
import_files -force -norecurse
ipx::package_project -root_dir sab4z -vendor www.telecom-paristech.fr -library SAB4Z -force sab4z
close_project
############################
## Create top level design #
############################
set top top
create_project -part xc7z010clg400-1 -force $top .
set_property board_part digilentinc.com:zybo:part0:1.0 [current_project]
set_property ip_repo_paths { ./sab4z } [current_fileset]
update_ip_catalog
create_bd_design "$top"
set sab4z [create_bd_cell -type ip -vlnv [get_ipdefs *www.telecom-paristech.fr:SAB4Z:sab4z:*] sab4z]
set ps7 [create_bd_cell -type ip -vlnv [get_ipdefs *xilinx.com:ip:processing_system7:*] ps7]
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $ps7
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.000000}] $ps7
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {1}] $ps7
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP1 {1}] $ps7
set_property -dict [list CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {1}] $ps7
set_property -dict [list CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {1}] $ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $ps7
set_property -dict [list CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32}] $ps7
# Interconnections
# Primary IOs
create_bd_port -dir O -from 3 -to 0 led
connect_bd_net [get_bd_pins /sab4z/led] [get_bd_ports led]
create_bd_port -dir I -from 3 -to 0 sw
connect_bd_net [get_bd_pins /sab4z/sw] [get_bd_ports sw]
create_bd_port -dir I btn
connect_bd_net [get_bd_pins /sab4z/btn] [get_bd_ports btn]
# ps7 - sab4z
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/ps7/M_AXI_GP0" Clk "Auto" } [get_bd_intf_pins /sab4z/s0_axi]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/ps7/M_AXI_GP1" Clk "Auto" } [get_bd_intf_pins /sab4z/s1_axi]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {Master "/sab4z/m_axi" Clk "Auto" } [get_bd_intf_pins /ps7/S_AXI_HP0]
# Addresses ranges
set_property offset 0x40000000 [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP0]]
set_property range 1G [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP0]]
set_property offset 0x80000000 [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP1]]
set_property range 1G [get_bd_addr_segs -of_object [get_bd_intf_pins /ps7/M_AXI_GP1]]
set_property offset 0x00000000 [get_bd_addr_segs -of_object [get_bd_intf_pins /sab4z/m_axi]]
set_property range 1G [get_bd_addr_segs -of_object [get_bd_intf_pins /sab4z/m_axi]]
# In-circuit debugging
if { $ila == 1 } {
set_property HDL_ATTRIBUTE.MARK_DEBUG true [get_bd_intf_nets -of_objects [get_bd_intf_pins /sab4z/m_axi]]
}
# Synthesis flow
validate_bd_design
set files [get_files *$top.bd]
generate_target all $files
add_files -norecurse -force [make_wrapper -files $files -top]
save_bd_design
set run [get_runs synth*]
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none $run
launch_runs $run
wait_on_run $run
open_run $run
# In-circuit debugging
if { $ila == 1 } {
set topcell [get_cells $top*]
set nets {}
set suffixes {
ARID ARADDR ARLEN ARSIZE ARBURST ARLOCK ARCACHE ARPROT ARQOS ARVALID
RREADY
AWID AWADDR AWLEN AWSIZE AWBURST AWLOCK AWCACHE AWPROT AWQOS AWVALID
WID WDATA WSTRB WLAST WVALID
BREADY
ARREADY
RID RDATA RRESP RLAST RVALID
AWREADY
WREADY
BID BRESP BVALID
}
foreach suffix $suffixes {
lappend nets $topcell/sab4z_m_axi_${suffix}
}
add_ila_core dc $topcell/ps7_FCLK_CLK0 $nets
}
# IOs
array set ios {
"sw[0]" { "G15" "LVCMOS33" }
"sw[1]" { "P15" "LVCMOS33" }
"sw[2]" { "W13" "LVCMOS33" }
"sw[3]" { "T16" "LVCMOS33" }
"led[0]" { "M14" "LVCMOS33" }
"led[1]" { "M15" "LVCMOS33" }
"led[2]" { "G14" "LVCMOS33" }
"led[3]" { "D18" "LVCMOS33" }
"btn" { "R18" "LVCMOS33" }
}
foreach io [ array names ios ] {
set pin [ lindex $ios($io) 0 ]
set std [ lindex $ios($io) 1 ]
set_property package_pin $pin [get_ports $io]
set_property iostandard $std [get_ports [list $io]]
}
# Timing constraints
set clock [get_clocks]
set_false_path -from $clock -to [get_ports {led[*]}]
set_false_path -from [get_ports {btn sw[*]}] -to $clock
# Implementation
save_constraints
set run [get_runs impl*]
reset_run $run
set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true $run
launch_runs -to_step write_bitstream $run
wait_on_run $run
# Messages
set rundir ${builddir}/$top.runs/$run
puts ""
puts "\[VIVADO\]: done"
puts " bitstream in $rundir/${top}_wrapper.bit"
puts " resource utilization report in $rundir/${top}_wrapper_utilization_placed.rpt"
puts " timing report in $rundir/${top}_wrapper_timing_summary_routed.rpt"
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