Commit d4fe5b50 authored by knopp's avatar knopp

Added NR FAPI for PDCCH and moved DCI filling to MAC accordingly.

compiles, still needs to be tested gNB alone with rf-simulator / RF bench.
parent b6246f77
......@@ -40,7 +40,7 @@ typedef struct {
// nFAPI enums
typedef enum {
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE = 0,
NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_DLSCH_PDU_TYPE,
NFAPI_NR_DL_CONFIG_PCH_PDU_TYPE,
......@@ -464,6 +464,7 @@ typedef enum {
// P7 Sub Structures
/*
typedef struct {
nfapi_tl_t tl;
......@@ -526,9 +527,21 @@ uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16
uint16_t padding;
} nfapi_nr_dl_config_dci_dl_pdu_rel15_t;
*/
//#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x????
typedef struct {
/// Number of PRGs spanning this allocation. Value : 1->275
uint16_t numPRGs;
/// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275
uint16_t prgSize;
/// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255
uint8_t digBFInterfaces;
uint16_t PMIdx[275];
uint16_t *beamIdx[275];
} nr_beamforming_t;
/*
typedef struct{
nfapi_tl_t tl;
uint8_t coreset_id;
......@@ -562,6 +575,7 @@ typedef struct{
uint32_t monitoring_symbols_in_slot;
uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS];
} nfapi_nr_search_space_t;
*/
typedef struct {
nfapi_tl_t tl;
......@@ -593,6 +607,60 @@ typedef struct {
nfapi_bf_vector_t bf_vector;
} nfapi_nr_dl_config_pdcch_parameters_rel15_t;
#define MAX_DCI_CORESET 8
#define DCI_PAYLOAD_BYTE_LEN 8
typedef struct {
///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275
uint16_t BWPSize;
///bandwidth part start RB index from reference CRB, [TS38.213 sec 12], Value: 0->274
uint16_t BWPStart;
///subcarrierSpacing [TS38.211 sec 4.2], Value:0->4
uint8_t SubcarrierSpacing;
///Cyclic prefix type [TS38.211 sec 4.2], 0: Normal; 1: Extended
uint8_t CyclicPrefix;
///Starting OFDM symbol for the CORESET, Value: 0->13
uint8_t StartSymbolIndex;
///Contiguous time duration of the CORESET in number of symbols. Corresponds to L1 parameter 𝑁𝑠𝑦𝑚𝑏_𝐶𝑂𝑅𝐸𝑆𝐸𝑇 [TS38.211 sec 7.3.2.2] Value: 1,2,3
uint8_t DurationSymbols;
///Frequency domain resources. This is a bitmap defining non-overlapping groups of 6 PRBs in ascending order. [TS38.213 10.1]. Also, corresponds to L1 parameter CORE SET RB N [TS38.211 sec 7.3.2.2] Bitmap of uint8 array. 45 bits.
uint8_t FreqDomainResource[6];
///CORESET-CCE-to-REG-mapping-type [TS38.211 sec 7.3.2.2] 0: non-interleaved 1: interleaved
uint8_t CceRegMappingType;
///The number of REGs in a bundle. Must be 6 for cceRegMappingType = nonInterleaved. For cceRegMappingType = interleaved, must belong to {2,6} if duration = 1,2 and must belong to {3,6} if duration = 3. Corresponds to parameter L. [TS38.211 sec 7.3.2.2] Value: 2,3,6
uint8_t RegBundleSize;
///The interleaver size. For interleaved mapping belongs to {2,3,6} and for non-interleaved mapping is NA. Corresponds to parameter R. [TS38.211 sec 7.3.2.2] Value: 2,3,6 CoreSetType
uint8_t InterleaverSize;
///[TS38.211 sec 7.3.2.2 and sec 7.4.1.3.2] 0: CORESET is configured by the PBCH or SIB1 (subcarrier 0 of CRB0 for DMRS mapping) 1: otherwise (subcarrier 0 of CORESET)
uint8_t CoreSetType;
///[TS38.211 sec 7.3.2.2] Not applicable for non-interleaved mapping. For interleaved mapping and a PDCCH transmitted in a CORESET configured by the PBCH or SIB1 this should be set to phy cell ID. Value: 10 bits Otherwise, for interleaved mapping this is set to 0-> max num of PRBs. Value 0-> 275
uint16_t ShiftIndex;
///Granularity of precoding [TS38.211 sec 7.3.2.2] Field Type Description 0: sameAsRegBundle 1: allContiguousRBs
uint8_t precoderGranularity;
///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot
uint16_t numDlDci;
///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
uint16_t RNTI[MAX_DCI_CORESET];
///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
uint16_t ScramblingId[MAX_DCI_CORESET];
///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
uint16_t ScramblingRNTI[MAX_DCI_CORESET];
///CCE start Index used to send the DCI Value: 0->135
uint8_t CceIndex[MAX_DCI_CORESET];
///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
uint8_t AggregationLevel[MAX_DCI_CORESET];
///Precoding and Beamforming structure See Table 3-43
nr_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8
uint16_t PayloadSizeBits[MAX_DCI_CORESET];
///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_config_pdcch_pdu_rel15_t;
typedef struct {
nfapi_tl_t tl;
uint16_t length;
......@@ -605,16 +673,7 @@ typedef struct {
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
} nfapi_nr_dl_config_bch_pdu;
typedef struct {
/// Number of PRGs spanning this allocation. Value : 1->275
uint16_t numPRGs;
/// Size in RBs of a precoding resource block group (PRG) – to which same precoding and digital beamforming gets applied. Value: 1->275
uint16_t prgSize;
/// Number of STD ant ports (parallel streams) feeding into the digBF Value: 0->255
uint8_t digBFInterfaces;
uint16_t PMIdx[275];
uint16_t *beamIdx[275];
} nr_beamforming_t;
typedef struct {
nfapi_tl_t tl;
......@@ -699,30 +758,37 @@ typedef struct {
#define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG
typedef struct {
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
} nfapi_nr_dl_config_dlsch_pdu;
typedef struct {
nfapi_tl_t tl;
nfapi_nr_search_space_t pagingSearchSpace;
nfapi_nr_coreset_t pagingControlResourceSets;
// nfapi_nr_search_space_t pagingSearchSpace;
// nfapi_nr_coreset_t pagingControlResourceSets;
}nfapi_nr_dl_config_pch_pdu_rel15_t;
typedef struct {
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
} nfapi_nr_dl_config_pch_pdu;
/*typedef struct {
nfapi_nr_dl_config_dci_dl_pdu_rel15_t dci_dl_pdu_rel15;
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params_rel15;
} nfapi_nr_dl_config_dci_dl_pdu;
} nfapi_nr_dl_config_dci_dl_pdu;*/
typedef struct {
nfapi_nr_dl_config_pdcch_pdu_rel15_t pdcch_pdu_rel15;
} nfapi_nr_dl_config_pdcch_pdu;
typedef struct {
uint8_t pdu_type;
uint8_t pdu_size;
union {
nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu;
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
nfapi_nr_dl_config_pdcch_pdu pdcch_pdu;
nfapi_nr_dl_config_bch_pdu bch_pdu;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu pch_pdu;
};
} nfapi_nr_dl_config_request_pdu_t;
......
......@@ -47,7 +47,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
int frame,
int slot,
NR_gNB_DCI_ALLOC_t *dci_alloc,
nfapi_nr_dl_config_dci_dl_pdu *pdu);
nfapi_nr_dl_config_pdcch_pdu *pdu);
void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t *dci_alloc, uint16_t n_shift, uint8_t m);
......
This diff is collapsed.
......@@ -36,7 +36,7 @@
#include "PHY/defs_gNB.h"
void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config,
nfapi_nr_dl_config_dci_dl_pdu dci_pdu,
nfapi_nr_dl_config_pdcch_pdu dci_pdu,
nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu);
void nr_check_time_alloc(uint8_t S, uint8_t L,nfapi_nr_dl_config_dlsch_pdu_rel15_t *rel15,nfapi_nr_config_request_t *cfg);
......
......@@ -43,8 +43,8 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB,
uint8_t *sdu)
{
AssertFatal(dl_config_pdu->bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n",
dl_config_pdu->bch_pdu_rel15.length);
AssertFatal(dl_config_pdu->bch_pdu.bch_pdu_rel15.length == 3, "BCH PDU has length %d != 3\n",
dl_config_pdu->bch_pdu.bch_pdu_rel15.length);
LOG_D(PHY,"pbch_pdu[0]: %x,pbch_pdu[1]: %x,gNB->pbch_pdu[2]: %x\n",sdu[0],sdu[1],sdu[2]);
gNB->pbch_pdu[0] = sdu[2];
......@@ -93,16 +93,16 @@ void handle_nr_nfapi_bch_pdu(PHY_VARS_gNB *gNB,
}*/
void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
int frame, int slot,
nfapi_nr_dl_config_dci_dl_pdu *dci_dl_pdu) {
void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB,
int frame, int slot,
nfapi_nr_dl_config_pdcch_pdu *pdcch_pdu) {
int idx = slot&1;
NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars;
LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci);
// copy dci configuration into gNB structure
nr_fill_dci(gNB,frame,slot,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],dci_dl_pdu);
nr_fill_dci(gNB,frame,slot,&pdcch_vars->dci_alloc[pdcch_vars->num_dci],pdcch_pdu);
LOG_D(PHY,"Frame %d, Slot %d: DCI processing - populated pdcch_vars->dci_alloc[%d] proc:slot_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,slot, pdcch_vars->num_dci, slot, idx, pdcch_vars->num_dci);
......@@ -158,22 +158,22 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
LOG_D(PHY,"NFAPI: dl_pdu %d : type %d\n",i,dl_config_pdu->pdu_type);
switch (dl_config_pdu->pdu_type) {
case NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE:
AssertFatal(dl_config_pdu->bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus,
"bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n",
dl_config_pdu->bch_pdu_rel15.pdu_index,
AssertFatal(dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index < TX_req->tx_request_body.number_of_pdus,
"bch_pdu.bch_pdu_rel8.pdu_index>=TX_req->number_of_pdus (%d>%d)\n",
dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index,
TX_req->tx_request_body.number_of_pdus);
gNB->pbch_configured=1;
do_oai=1;
handle_nr_nfapi_bch_pdu(gNB,
dl_config_pdu,
TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu_rel15.pdu_index].segments[0].segment_data);
TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index].segments[0].segment_data);
break;
case NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE:
handle_nfapi_nr_dci_dl_pdu(gNB,
frame, slot,
&dl_config_pdu->dci_dl_pdu);
case NFAPI_NR_DL_CONFIG_PDCCH_PDU_TYPE:
handle_nfapi_nr_pdcch_pdu(gNB,
frame, slot,
&dl_config_pdu->pdcch_pdu);
gNB->pdcch_vars.num_dci++;
gNB->pdcch_vars.num_pdsch_rnti++;
do_oai=1;
......
......@@ -37,9 +37,9 @@
void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO);
void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
int frame, int subframe,
nfapi_nr_dl_config_dci_dl_pdu *dcl_dl_pdu);
void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB,
int frame, int subframe,
nfapi_nr_dl_config_pdcch_pdu *dcl_dl_pdu);
void handle_nr_nfapi_dlsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot,
nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu,
......
......@@ -249,9 +249,6 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup;
LOG_I(PHY,"Modified UE_id %d/%x with secondaryCellGroup\n",UE_id,rnti);
}
fill_nfapi_coresets_and_searchspaces(secondaryCellGroup,
UE_list->coreset[UE_id],
UE_list->search_space[UE_id]);
}
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT);
......
......@@ -97,10 +97,10 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
memset((void *) dl_config_pdu, 0,sizeof(nfapi_nr_dl_config_request_pdu_t));
dl_config_pdu->pdu_type = NFAPI_NR_DL_CONFIG_BCH_PDU_TYPE;
dl_config_pdu->pdu_size =2 + sizeof(nfapi_nr_dl_config_bch_pdu_rel15_t);
dl_config_pdu->bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG;
dl_config_pdu->bch_pdu_rel15.length = mib_sdu_length;
dl_config_pdu->bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id];
dl_config_pdu->bch_pdu_rel15.transmission_power = 6000;
dl_config_pdu->bch_pdu.bch_pdu_rel15.tl.tag = NFAPI_NR_DL_CONFIG_REQUEST_BCH_PDU_REL15_TAG;
dl_config_pdu->bch_pdu.bch_pdu_rel15.length = mib_sdu_length;
dl_config_pdu->bch_pdu.bch_pdu_rel15.pdu_index = gNB->pdu_index[CC_id];
dl_config_pdu->bch_pdu.bch_pdu_rel15.transmission_power = 6000;
dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG;
dl_req->number_pdu++;
dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST;
......
......@@ -66,9 +66,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
int configure_fapi_dl_Tx(int Mod_id,
nfapi_nr_dl_config_request_body_t *dl_req,
nfapi_tx_request_pdu_t *TX_req,
nfapi_nr_config_request_t *cfg,
nfapi_nr_coreset_t* coreset,
nfapi_nr_search_space_t* search_space,
int16_t pdu_index);
......@@ -88,20 +85,22 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
uint8_t n_ssb,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
/*
int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space,
nfapi_nr_coreset_t coreset,
uint16_t frame,
uint16_t slot,
nfapi_nr_config_request_t cfg);
void nr_configure_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
int ss_type,
int target_aggregation_level,
int cce_index,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp);
*/
void nr_configure_pdcch(nfapi_nr_dl_config_pdcch_pdu_rel15_t* pdcch_pdu,
int ss_type,
NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(nfapi_nr_dl_config_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types
);
int get_dlscs(nfapi_nr_config_request_t *cfg);
int get_ulscs(nfapi_nr_config_request_t *cfg);
......@@ -120,7 +119,6 @@ uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint32_t bw);
void nr_get_tbs_dl(nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu,
nfapi_nr_dl_config_dci_dl_pdu dci_pdu,
int x_overhead);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
......
......@@ -183,16 +183,12 @@ int32_t get_nr_uldl_offset(int nr_bandP)
void nr_get_tbs_dl(nfapi_nr_dl_config_dlsch_pdu *dlsch_pdu,
nfapi_nr_dl_config_dci_dl_pdu dci_pdu,
int x_overhead) {
LOG_D(MAC, "TBS calculation\n");
nfapi_nr_dl_config_pdcch_parameters_rel15_t params_rel15 = dci_pdu.pdcch_params_rel15;
nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_rel15 = &dlsch_pdu->dlsch_pdu_rel15;
uint8_t rnti_type = params_rel15.rnti_type;
uint16_t N_PRB_oh = ((rnti_type==NFAPI_NR_RNTI_SI)||(rnti_type==NFAPI_NR_RNTI_RA)||(rnti_type==NFAPI_NR_RNTI_P))? 0 : \
(x_overhead);
uint16_t N_PRB_oh = x_overhead;
uint8_t N_PRB_DMRS = (dlsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000
uint8_t N_sh_symb = dlsch_rel15->NrOfSymbols;
uint8_t Imcs = dlsch_rel15->mcsIndex[0];
......
......@@ -116,12 +116,6 @@ typedef struct {
boolean_t active[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
/// NFAPI coreset structure
nfapi_nr_coreset_t coreset[MAX_MOBILES_PER_GNB][NFAPI_NR_MAX_NB_CORESETS];
/// NFAPI search space structure
nfapi_nr_search_space_t search_space[MAX_MOBILES_PER_GNB][NFAPI_NR_MAX_NB_SEARCH_SPACES];
} NR_UE_list_t;
/*! \brief top level eNB MAC structure */
......@@ -193,4 +187,93 @@ typedef struct gNB_MAC_INST_s {
time_stats_t schedule_pch;
} gNB_MAC_INST;
typedef struct {
uint8_t format_indicator; //1 bit
uint16_t frequency_domain_assignment; //up to 16 bits
uint8_t time_domain_assignment; // 4 bits
uint8_t frequency_hopping_flag; //1 bit
uint8_t ra_preamble_index; //6 bits
uint8_t ss_pbch_index; //6 bits
uint8_t prach_mask_index; //4 bits
uint8_t vrb_to_prb_mapping; //0 or 1 bit
uint8_t mcs; //5 bits
uint8_t ndi; //1 bit
uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits
uint8_t dai; //0, 2 or 4 bits
uint8_t dai1; //1 or 2 bits
uint8_t dai2; //0 or 2 bits
uint8_t tpc; //2 bits
uint8_t pucch_resource_indicator; //3 bits
uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
uint8_t short_messages_indicator; //2 bits
uint8_t short_messages; //8 bits
uint8_t tb_scaling; //2 bits
uint8_t carrier_indicator; //0 or 3 bits
uint8_t bwp_indicator; //0, 1 or 2 bits
uint8_t prb_bundling_size_indicator; //0 or 1 bits
uint8_t rate_matching_indicator; //0, 1 or 2 bits
uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits
uint8_t transmission_configuration_indication; //0 or 3 bits
uint8_t srs_request; //2 bits
uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
uint8_t dmrs_sequence_initialization; //0 or 1 bit
uint8_t srs_resource_indicator;
uint8_t precoding_information;
uint8_t csi_request;
uint8_t ptrs_dmrs_association;
uint8_t beta_offset_indicator; //0 or 2 bits
uint8_t slot_format_indicator_count;
uint8_t *slot_format_indicators;
uint8_t pre_emption_indication_count;
uint16_t *pre_emption_indications; //14 bit
uint8_t block_number_count;
uint8_t *block_numbers;
uint8_t ul_sul_indicator; //0 or 1 bit
uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding;
} dci_pdu_rel15_t;
typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0,
NR_DL_DCI_FORMAT_1_1,
NR_DL_DCI_FORMAT_2_0,
NR_DL_DCI_FORMAT_2_1,
NR_DL_DCI_FORMAT_2_2,
NR_DL_DCI_FORMAT_2_3,
NR_UL_DCI_FORMAT_0_0,
NR_UL_DCI_FORMAT_0_1
} nr_dci_format_t;
typedef enum {
NR_RNTI_new = 0,
NR_RNTI_C,
NR_RNTI_RA,
NR_RNTI_P,
NR_RNTI_CS,
NR_RNTI_TC,
NR_RNTI_SP_CSI,
NR_RNTI_SI,
NR_RNTI_SFI,
NR_RNTI_INT,
NR_RNTI_TPC_PUSCH,
NR_RNTI_TPC_PUCCH,
NR_RNTI_TPC_SRS
} nr_rnti_type_t;
#endif /*__LAYER2_NR_MAC_GNB_H__ */
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