sky2.c 115 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12
/*
 * New driver for Marvell Yukon 2 chipset.
 * Based on earlier sk98lin, and skge driver.
 *
 * This driver intentionally does not support all the features
 * of the original driver such as link fail-over and link management because
 * those should be done at higher levels.
 *
 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
13
 * the Free Software Foundation; either version 2 of the License.
14 15 16
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 19 20 21 22 23 24
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

25
#include <linux/crc32.h>
26 27 28 29
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/netdevice.h>
30
#include <linux/dma-mapping.h>
31 32 33
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/pci.h>
34
#include <linux/aer.h>
35
#include <linux/ip.h>
36
#include <net/ip.h>
37 38 39
#include <linux/tcp.h>
#include <linux/in.h>
#include <linux/delay.h>
40
#include <linux/workqueue.h>
41
#include <linux/if_vlan.h>
42
#include <linux/prefetch.h>
Stephen Hemminger's avatar
Stephen Hemminger committed
43
#include <linux/debugfs.h>
44
#include <linux/mii.h>
45 46 47

#include <asm/irq.h>

48 49 50 51
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define SKY2_VLAN_TAG_USED 1
#endif

52 53 54
#include "sky2.h"

#define DRV_NAME		"sky2"
Stephen Hemminger's avatar
Stephen Hemminger committed
55
#define DRV_VERSION		"1.18"
56 57 58 59 60
#define PFX			DRV_NAME " "

/*
 * The Yukon II chipset takes 64 bit command blocks (called list elements)
 * that are organized into three (receive, transmit, status) different rings
61
 * similar to Tigon3.
62 63
 */

64
#define RX_LE_SIZE	    	1024
65
#define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
66
#define RX_MAX_PENDING		(RX_LE_SIZE/6 - 2)
67
#define RX_DEF_PENDING		RX_MAX_PENDING
68
#define RX_SKB_ALIGN		8
69 70 71 72

#define TX_RING_SIZE		512
#define TX_DEF_PENDING		(TX_RING_SIZE - 1)
#define TX_MIN_PENDING		64
73
#define MAX_SKB_TX_LE		(4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74

75
#define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
76 77 78 79 80
#define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))
#define TX_WATCHDOG		(5 * HZ)
#define NAPI_WEIGHT		64
#define PHY_RETRIES		1000

81 82 83
#define SKY2_EEPROM_MAGIC	0x9955aabb


84 85
#define RING_NEXT(x,s)	(((x)+1) & ((s)-1))

86
static const u32 default_msg =
87 88
    NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
    | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89
    | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90

91
static int debug = -1;		/* defaults above */
92 93 94
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

95
static int copybreak __read_mostly = 128;
96 97 98
module_param(copybreak, int, 0);
MODULE_PARM_DESC(copybreak, "Receive copy threshold");

99 100 101 102
static int disable_msi = 0;
module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

103
static const struct pci_device_id sky2_id_table[] = {
104 105
	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },	/* DGE-560T */
107
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, 	/* DGE-550SX */
108
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) },	/* DGE-560SX */
Stephen Hemminger's avatar
Stephen Hemminger committed
109
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) },	/* DGE-550T */
110 111 112 113 114 115 116 117 118 119 120 121
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
Stephen Hemminger's avatar
Stephen Hemminger committed
122
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
Stephen Hemminger's avatar
Stephen Hemminger committed
124
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
125 126 127 128 129
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
Stephen Hemminger's avatar
Stephen Hemminger committed
130
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
131 132 133
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
Stephen Hemminger's avatar
Stephen Hemminger committed
134 135
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
136
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
137 138
	{ 0 }
};
139

140 141 142 143 144
MODULE_DEVICE_TABLE(pci, sky2_id_table);

/* Avoid conditionals by using array */
static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
145
static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146

147 148 149 150
/* This driver supports yukon2 chipset only */
static const char *yukon2_name[] = {
	"XL",		/* 0xb3 */
	"EC Ultra", 	/* 0xb4 */
151
	"Extreme",	/* 0xb5 */
152 153
	"EC",		/* 0xb6 */
	"FE",		/* 0xb7 */
Stephen Hemminger's avatar
Stephen Hemminger committed
154
	"FE+",		/* 0xb8 */
155 156
};

157 158
static void sky2_set_multicast(struct net_device *dev);

159
/* Access to external PHY */
160
static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 162 163 164 165 166 167 168 169
{
	int i;

	gma_write16(hw, port, GM_SMI_DATA, val);
	gma_write16(hw, port, GM_SMI_CTRL,
		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

	for (i = 0; i < PHY_RETRIES; i++) {
		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
170
			return 0;
171
		udelay(1);
172
	}
173

174
	printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
175
	return -ETIMEDOUT;
176 177
}

178
static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
179 180 181
{
	int i;

182
	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
183 184 185
		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

	for (i = 0; i < PHY_RETRIES; i++) {
186 187 188 189 190
		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
			*val = gma_read16(hw, port, GM_SMI_DATA);
			return 0;
		}

191
		udelay(1);
192 193
	}

194 195 196 197 198 199 200 201 202 203
	return -ETIMEDOUT;
}

static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
{
	u16 v;

	if (__gm_phy_read(hw, port, reg, &v) != 0)
		printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
	return v;
204 205
}

206

207 208 209 210 211
static void sky2_power_on(struct sky2_hw *hw)
{
	/* switch power to VCC (WA for VAUX problem) */
	sky2_write8(hw, B0_POWER_CTRL,
		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212

213 214
	/* disable Core Clock Division, */
	sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215

216 217 218 219 220 221 222 223
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
		/* enable bits are inverted */
		sky2_write8(hw, B2_Y2_CLK_GATE,
			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
	else
		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224

225
	if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
226
		struct pci_dev *pdev = hw->pdev;
227
		u32 reg;
228

229
		pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
230

231
		pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
232 233
		/* set all bits to 0 except bits 15..12 and 8 */
		reg &= P_ASPM_CONTROL_MSK;
234
		pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
235

236
		pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
237 238
		/* set all bits to 0 except bits 28 & 27 */
		reg &= P_CTL_TIM_VMAIN_AV_MSK;
239
		pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
240

241
		pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
Stephen Hemminger's avatar
Stephen Hemminger committed
242 243 244 245 246

		/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
		reg = sky2_read32(hw, B2_GP_IO);
		reg |= GLB_GPIO_STAT_RACE_DIS;
		sky2_write32(hw, B2_GP_IO, reg);
247 248

		sky2_read32(hw, B2_GP_IO);
249
	}
250
}
251

252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267
static void sky2_power_aux(struct sky2_hw *hw)
{
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
	else
		/* enable bits are inverted */
		sky2_write8(hw, B2_Y2_CLK_GATE,
			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

	/* switch power to VAUX */
	if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
		sky2_write8(hw, B0_POWER_CTRL,
			    (PC_VAUX_ENA | PC_VCC_ENA |
			     PC_VAUX_ON | PC_VCC_OFF));
268 269
}

270
static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
271 272 273 274 275 276 277
{
	u16 reg;

	/* disable all GMAC IRQ's */
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
	/* disable PHY IRQs */
	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
278

279 280 281 282 283 284 285 286 287 288
	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
	gma_write16(hw, port, GM_MC_ADDR_H4, 0);

	reg = gma_read16(hw, port, GM_RX_CTRL);
	reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
	gma_write16(hw, port, GM_RX_CTRL, reg);
}

289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313
/* flow control to advertise bits */
static const u16 copper_fc_adv[] = {
	[FC_NONE]	= 0,
	[FC_TX]		= PHY_M_AN_ASP,
	[FC_RX]		= PHY_M_AN_PC,
	[FC_BOTH]	= PHY_M_AN_PC | PHY_M_AN_ASP,
};

/* flow control to advertise bits when using 1000BaseX */
static const u16 fiber_fc_adv[] = {
	[FC_BOTH] = PHY_M_P_BOTH_MD_X,
	[FC_TX]   = PHY_M_P_ASYM_MD_X,
	[FC_RX]	  = PHY_M_P_SYM_MD_X,
	[FC_NONE] = PHY_M_P_NO_PAUSE_X,
};

/* flow control to GMA disable bits */
static const u16 gm_fc_disable[] = {
	[FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
	[FC_TX]	  = GM_GPCR_FC_RX_DIS,
	[FC_RX]	  = GM_GPCR_FC_TX_DIS,
	[FC_BOTH] = 0,
};


314 315 316
static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
317
	u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
318

319 320
	if (sky2->autoneg == AUTONEG_ENABLE &&
	    !(hw->flags & SKY2_HW_NEWER_PHY)) {
321 322 323
		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
324
			   PHY_M_EC_MAC_S_MSK);
325 326
		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

327
		/* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
328
		if (hw->chip_id == CHIP_ID_YUKON_EC)
329
			/* set downshift counter to 3x and enable downshift */
330 331
			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
		else
332 333
			/* set master & slave downshift counter to 1x */
			ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
334 335 336 337 338

		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
	}

	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
339
	if (sky2_is_copper(hw)) {
Stephen Hemminger's avatar
Stephen Hemminger committed
340
		if (!(hw->flags & SKY2_HW_GIGABIT)) {
341 342
			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
343 344 345 346 347 348 349 350 351 352

			if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
			    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
				u16 spec;

				/* Enable Class A driver for FE+ A0 */
				spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
				spec |= PHY_M_FESC_SEL_CL_A;
				gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
			}
353 354 355 356 357 358 359
		} else {
			/* disable energy detect */
			ctrl &= ~PHY_M_PC_EN_DET_MSK;

			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

360
			/* downshift on PHY 88E1112 and 88E1149 is changed */
361
			if (sky2->autoneg == AUTONEG_ENABLE
362
			    && (hw->flags & SKY2_HW_NEWER_PHY)) {
363
				/* set downshift counter to 3x and enable downshift */
364 365 366 367 368 369 370 371 372
				ctrl &= ~PHY_M_PC_DSC_MSK;
				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
			}
		}
	} else {
		/* workaround for deviation #4.88 (CRC errors) */
		/* disable Automatic Crossover */

		ctrl &= ~PHY_M_PC_MDIX_MSK;
373
	}
374

375 376 377
	gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

	/* special setup for PHY 88E1112 Fiber */
378
	if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
379
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
380

381 382 383 384 385 386 387 388
		/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
		ctrl &= ~PHY_M_MAC_MD_MSK;
		ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

		if (hw->pmd_type  == 'P') {
389 390
			/* select page 1 to access Fiber registers */
			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
391 392 393 394

			/* for SFP-module set SIGDET polarity to low */
			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
			ctrl |= PHY_M_FIB_SIGD_POL;
395
			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
396
		}
397 398

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
399 400
	}

401
	ctrl = PHY_CT_RESET;
402 403
	ct1000 = 0;
	adv = PHY_AN_CSMA;
404
	reg = 0;
405 406

	if (sky2->autoneg == AUTONEG_ENABLE) {
407
		if (sky2_is_copper(hw)) {
408 409 410 411 412 413 414 415 416 417 418 419
			if (sky2->advertising & ADVERTISED_1000baseT_Full)
				ct1000 |= PHY_M_1000C_AFD;
			if (sky2->advertising & ADVERTISED_1000baseT_Half)
				ct1000 |= PHY_M_1000C_AHD;
			if (sky2->advertising & ADVERTISED_100baseT_Full)
				adv |= PHY_M_AN_100_FD;
			if (sky2->advertising & ADVERTISED_100baseT_Half)
				adv |= PHY_M_AN_100_HD;
			if (sky2->advertising & ADVERTISED_10baseT_Full)
				adv |= PHY_M_AN_10_FD;
			if (sky2->advertising & ADVERTISED_10baseT_Half)
				adv |= PHY_M_AN_10_HD;
Stephen Hemminger's avatar
Stephen Hemminger committed
420

421
			adv |= copper_fc_adv[sky2->flow_mode];
422 423 424 425 426
		} else {	/* special defines for FIBER (88E1040S only) */
			if (sky2->advertising & ADVERTISED_1000baseT_Full)
				adv |= PHY_M_AN_1000X_AFD;
			if (sky2->advertising & ADVERTISED_1000baseT_Half)
				adv |= PHY_M_AN_1000X_AHD;
427

428
			adv |= fiber_fc_adv[sky2->flow_mode];
Stephen Hemminger's avatar
Stephen Hemminger committed
429
		}
430 431 432 433 434 435 436

		/* Restart Auto-negotiation */
		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
	} else {
		/* forced speed/duplex settings */
		ct1000 = PHY_M_1000C_MSE;

437 438
		/* Disable auto update for duplex flow control and speed */
		reg |= GM_GPCR_AU_ALL_DIS;
439 440 441 442

		switch (sky2->speed) {
		case SPEED_1000:
			ctrl |= PHY_CT_SP1000;
443
			reg |= GM_GPCR_SPEED_1000;
444 445 446
			break;
		case SPEED_100:
			ctrl |= PHY_CT_SP100;
447
			reg |= GM_GPCR_SPEED_100;
448 449 450
			break;
		}

451 452 453
		if (sky2->duplex == DUPLEX_FULL) {
			reg |= GM_GPCR_DUP_FULL;
			ctrl |= PHY_CT_DUP_MD;
454 455
		} else if (sky2->speed < SPEED_1000)
			sky2->flow_mode = FC_NONE;
456 457


458
 		reg |= gm_fc_disable[sky2->flow_mode];
459 460

		/* Forward pause packets to GMAC? */
461
		if (sky2->flow_mode & FC_RX)
462 463 464
			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
		else
			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
465 466
	}

467 468
	gma_write16(hw, port, GM_GP_CTRL, reg);

Stephen Hemminger's avatar
Stephen Hemminger committed
469
	if (hw->flags & SKY2_HW_GIGABIT)
470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492
		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

	/* Setup Phy LED's */
	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
	ledover = 0;

	switch (hw->chip_id) {
	case CHIP_ID_YUKON_FE:
		/* on 88E3082 these bits are at 11..9 (shifted left) */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

		ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

		/* delete ACT LED control bits */
		ctrl &= ~PHY_M_FELP_LED1_MSK;
		/* change ACT LED control to blink mode */
		ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
		break;

Stephen Hemminger's avatar
Stephen Hemminger committed
493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509
	case CHIP_ID_YUKON_FE_P:
		/* Enable Link Partner Next Page */
		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
		ctrl |= PHY_M_PC_ENA_LIP_NP;

		/* disable Energy Detect and enable scrambler */
		ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

		/* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
		ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
			PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
			PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);

		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
		break;

510
	case CHIP_ID_YUKON_XL:
511
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
512 513 514 515 516

		/* select page 3 to access LED control register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
517 518 519 520 521
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			      PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
			      PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */
522 523 524

		/* set Polarity Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
525 526 527 528 529 530
			     (PHY_M_POLC_LS1_P_MIX(4) |
			      PHY_M_POLC_IS0_P_MIX(4) |
			      PHY_M_POLC_LOS_CTRL(2) |
			      PHY_M_POLC_INIT_CTRL(2) |
			      PHY_M_POLC_STA1_CTRL(2) |
			      PHY_M_POLC_STA0_CTRL(2)));
531 532

		/* restore page register */
533
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
534
		break;
535

536
	case CHIP_ID_YUKON_EC_U:
537
	case CHIP_ID_YUKON_EX:
538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

		/* select page 3 to access LED control register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			      PHY_M_LEDC_INIT_CTRL(8) |	/* 10 Mbps */
			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
			      PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */

		/* set Blink Rate in LED Timer Control Register */
		gm_phy_write(hw, port, PHY_MARV_INT_MASK,
			     ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
		/* restore page register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
		break;
556 557 558 559 560

	default:
		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
		/* turn off the Rx LED (LED_RX) */
561
		ledover &= ~PHY_M_LED_MO_RX;
562 563
	}

564 565
	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
	    hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
566
		/* apply fixes in PHY AFE */
567 568
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);

569
		/* increase differential signal amplitude in 10BASE-T */
570 571
		gm_phy_write(hw, port, 0x18, 0xaa99);
		gm_phy_write(hw, port, 0x17, 0x2011);
572

573
		/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
574 575
		gm_phy_write(hw, port, 0x18, 0xa204);
		gm_phy_write(hw, port, 0x17, 0x2002);
576 577

		/* set page register to 0 */
578
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
Stephen Hemminger's avatar
Stephen Hemminger committed
579 580 581 582 583
	} else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
		   hw->chip_rev == CHIP_REV_YU_FE2_A0) {
		/* apply workaround for integrated resistors calibration */
		gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
		gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
584
	} else if (hw->chip_id != CHIP_ID_YUKON_EX) {
Stephen Hemminger's avatar
Stephen Hemminger committed
585
		/* no effect on Yukon-XL */
586
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
587

588 589
		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
			/* turn on 100 Mbps LED (LED_LINK100) */
590
			ledover |= PHY_M_LED_MO_100;
591
		}
592

593 594 595 596
		if (ledover)
			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

	}
597

598
	/* Enable phy interrupt on auto-negotiation complete (or link up) */
599 600 601 602 603 604
	if (sky2->autoneg == AUTONEG_ENABLE)
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
	else
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
}

605 606
static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
{
607
	struct pci_dev *pdev = hw->pdev;
608
	u32 reg1;
609 610
	static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
	static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
611

612
	pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
613
	/* Turn on/off phy power saving */
614 615 616 617 618
	if (onoff)
		reg1 &= ~phy_power[port];
	else
		reg1 |= phy_power[port];

619 620 621
	if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
		reg1 |= coma_mode[port];

622 623 624
	pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
	pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);

625 626 627
	udelay(100);
}

628 629 630
/* Force a renegotiation */
static void sky2_phy_reinit(struct sky2_port *sky2)
{
631
	spin_lock_bh(&sky2->phy_lock);
632
	sky2_phy_init(sky2->hw, sky2->port);
633
	spin_unlock_bh(&sky2->phy_lock);
634 635
}

636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691
/* Put device in state to listen for Wake On Lan */
static void sky2_wol_init(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	enum flow_control save_mode;
	u16 ctrl;
	u32 reg1;

	/* Bring hardware out of reset */
	sky2_write16(hw, B0_CTST, CS_RST_CLR);
	sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);

	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

	/* Force to 10/100
	 * sky2_reset will re-enable on resume
	 */
	save_mode = sky2->flow_mode;
	ctrl = sky2->advertising;

	sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
	sky2->flow_mode = FC_NONE;
	sky2_phy_power(hw, port, 1);
	sky2_phy_reinit(sky2);

	sky2->flow_mode = save_mode;
	sky2->advertising = ctrl;

	/* Set GMAC to no flow control and auto update for speed/duplex */
	gma_write16(hw, port, GM_GP_CTRL,
		    GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
		    GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);

	/* Set WOL address */
	memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
		    sky2->netdev->dev_addr, ETH_ALEN);

	/* Turn on appropriate WOL control bits */
	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
	ctrl = 0;
	if (sky2->wol & WAKE_PHY)
		ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
	else
		ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;

	if (sky2->wol & WAKE_MAGIC)
		ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
	else
		ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;

	ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);

	/* Turn on legacy PCI-Express PME mode */
692
	pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
693
	reg1 |= PCI_Y2_PME_LEGACY;
694
	pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
695 696 697 698 699 700

	/* block receiver */
	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);

}

701 702
static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
{
Stephen Hemminger's avatar
Stephen Hemminger committed
703 704 705
	struct net_device *dev = hw->dev[port];

	if (dev->mtu <= ETH_DATA_LEN)
706
		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
Stephen Hemminger's avatar
Stephen Hemminger committed
707 708 709 710 711 712 713 714 715
			     TX_JUMBO_DIS | TX_STFW_ENA);

	else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
			     TX_STFW_ENA | TX_JUMBO_ENA);
	else {
		/* set Tx GMAC FIFO Almost Empty Threshold */
		sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
			     (ECU_JUMBO_WM << 16) | ECU_AE_THR);
716

Stephen Hemminger's avatar
Stephen Hemminger committed
717 718
		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
			     TX_JUMBO_ENA | TX_STFW_DIS);
719

Stephen Hemminger's avatar
Stephen Hemminger committed
720 721
		/* Can't do offload because of lack of store/forward */
		dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
722 723 724
	}
}

725 726 727 728
static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
	u16 reg;
Al Viro's avatar
Al Viro committed
729
	u32 rx_reg;
730 731 732
	int i;
	const u8 *addr = hw->dev[port]->dev_addr;

733 734
	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
735 736 737

	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

738
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
739 740 741 742 743 744 745 746 747 748 749
		/* WA DEV_472 -- looks like crossed wires on port 2 */
		/* clear GMAC 1 Control reset */
		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
		do {
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
	}

750
	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
751

752 753 754
	/* Enable Transmit FIFO Underrun */
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);

755
	spin_lock_bh(&sky2->phy_lock);
756
	sky2_phy_init(hw, port);
757
	spin_unlock_bh(&sky2->phy_lock);
758 759 760 761 762

	/* MIB clear */
	reg = gma_read16(hw, port, GM_PHY_ADDR);
	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

763 764
	for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
		gma_read16(hw, port, i);
765 766 767 768 769 770 771
	gma_write16(hw, port, GM_PHY_ADDR, reg);

	/* transmit control */
	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

	/* receive control reg: unicast + multicast + no FCS  */
	gma_write16(hw, port, GM_RX_CTRL,
772
		    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
773 774 775 776 777 778 779 780 781 782 783 784 785

	/* transmit flow control */
	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

	/* transmit parameter */
	gma_write16(hw, port, GM_TX_PARAM,
		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

	/* serial mode register */
	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
786
		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
787

788
	if (hw->dev[port]->mtu > ETH_DATA_LEN)
789 790 791 792 793 794 795
		reg |= GM_SMOD_JUMBO_ENA;

	gma_write16(hw, port, GM_SERIAL_MODE, reg);

	/* virtual address for data */
	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

796 797 798 799
	/* physical address: used for pause frames */
	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

	/* ignore counter overflows */
800 801 802 803 804 805
	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

	/* Configure Rx MAC FIFO */
	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
Al Viro's avatar
Al Viro committed
806
	rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
Stephen Hemminger's avatar
Stephen Hemminger committed
807 808
	if (hw->chip_id == CHIP_ID_YUKON_EX ||
	    hw->chip_id == CHIP_ID_YUKON_FE_P)
Al Viro's avatar
Al Viro committed
809
		rx_reg |= GMF_RX_OVER_ON;
810

Al Viro's avatar
Al Viro committed
811
	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
812

813
	/* Flush Rx MAC FIFO on any flow control or error */
814
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
815

816
	/* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug  */
Stephen Hemminger's avatar
Stephen Hemminger committed
817 818 819 820 821 822
	reg = RX_GMF_FL_THR_DEF + 1;
	/* Another magic mystery workaround from sk98lin */
	if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
	    hw->chip_rev == CHIP_REV_YU_FE2_A0)
		reg = 0x178;
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
823 824 825 826

	/* Configure Tx MAC FIFO */
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
827

828 829
	/* On chips without ram buffer, pause is controled by MAC level */
	if (sky2_read8(hw, B2_E_0) == 0) {
830
		sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
831
		sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
832

833
		sky2_set_tx_stfwd(hw, port);
834 835
	}

836 837
}

838 839
/* Assign Ram Buffer allocation to queue */
static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
840
{
841 842 843 844 845 846
	u32 end;

	/* convert from K bytes to qwords used for hw register */
	start *= 1024/8;
	space *= 1024/8;
	end = start + space - 1;
847

848 849 850 851 852 853 854
	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
	sky2_write32(hw, RB_ADDR(q, RB_START), start);
	sky2_write32(hw, RB_ADDR(q, RB_END), end);
	sky2_write32(hw, RB_ADDR(q, RB_WP), start);
	sky2_write32(hw, RB_ADDR(q, RB_RP), start);

	if (q == Q_R1 || q == Q_R2) {
855
		u32 tp = space - space/4;
856

857 858 859 860 861 862
		/* On receive queue's set the thresholds
		 * give receiver priority when > 3/4 full
		 * send pause when down to 2K
		 */
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
863

864 865 866
		tp = space - 2048/8;
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
867 868 869 870 871 872 873 874
	} else {
		/* Enable store & forward on Tx queue's because
		 * Tx FIFO is only 1K on Yukon
		 */
		sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
	}

	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
875
	sky2_read8(hw, RB_ADDR(q, RB_CTRL));
876 877 878
}

/* Setup Bus Memory Interface */
879
static void sky2_qset(struct sky2_hw *hw, u16 q)
880 881 882 883
{
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
884
	sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
885 886 887 888 889
}

/* Setup prefetch unit registers. This is the interface between
 * hardware and driver list elements
 */
890
static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
891 892 893 894 895 896 897 898
				      u64 addr, u32 last)
{
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
	sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
899 900

	sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
901 902
}

903 904 905 906
static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
{
	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

907
	sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
908
	le->ctrl = 0;
909 910
	return le;
}
911

912 913 914 915 916 917 918 919 920 921 922 923 924 925
static void tx_init(struct sky2_port *sky2)
{
	struct sky2_tx_le *le;

	sky2->tx_prod = sky2->tx_cons = 0;
	sky2->tx_tcpsum = 0;
	sky2->tx_last_mss = 0;

	le = get_tx_le(sky2);
	le->addr = 0;
	le->opcode = OP_ADDR64 | HW_OWNER;
	sky2->tx_addr64 = 0;
}

926 927 928 929 930 931
static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
					    struct sky2_tx_le *le)
{
	return sky2->tx_ring + (le - sky2->tx_le);
}

932 933
/* Update chip's next pointer */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
934
{
935
	/* Make sure write' to descriptors are complete before we tell hardware */
936
	wmb();
937 938 939 940
	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);

	/* Synchronize I/O on since next processor may write to tail */
	mmiowb();
941 942
}

943

944 945 946
static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
{
	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
947
	sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
948
	le->ctrl = 0;
949 950 951
	return le;
}

952 953 954
/* Build description to hardware for one receive segment */
static void sky2_rx_add(struct sky2_port *sky2,  u8 op,
			dma_addr_t map, unsigned len)
955 956
{
	struct sky2_rx_le *le;
957
	u32 hi = upper_32_bits(map);
958

959
	if (sky2->rx_addr64 != hi) {
960
		le = sky2_next_rx(sky2);
961
		le->addr = cpu_to_le32(hi);
962
		le->opcode = OP_ADDR64 | HW_OWNER;
963
		sky2->rx_addr64 = upper_32_bits(map + len);
964
	}
965

966
	le = sky2_next_rx(sky2);
967 968
	le->addr = cpu_to_le32((u32) map);
	le->length = cpu_to_le16(len);
969
	le->opcode = op | HW_OWNER;
970 971
}

972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014
/* Build description to hardware for one possibly fragmented skb */
static void sky2_rx_submit(struct sky2_port *sky2,
			   const struct rx_ring_info *re)
{
	int i;

	sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);

	for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
		sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
}


static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
			    unsigned size)
{
	struct sk_buff *skb = re->skb;
	int i;

	re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
	pci_unmap_len_set(re, data_size, size);

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
		re->frag_addr[i] = pci_map_page(pdev,
						skb_shinfo(skb)->frags[i].page,
						skb_shinfo(skb)->frags[i].page_offset,
						skb_shinfo(skb)->frags[i].size,
						PCI_DMA_FROMDEVICE);
}

static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
{
	struct sk_buff *skb = re->skb;
	int i;

	pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
			 PCI_DMA_FROMDEVICE);

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
		pci_unmap_page(pdev, re->frag_addr[i],
			       skb_shinfo(skb)->frags[i].size,
			       PCI_DMA_FROMDEVICE);
}
1015

1016 1017 1018 1019
/* Tell chip where to start receive checksum.
 * Actually has two checksums, but set both same to avoid possible byte
 * order problems.
 */
1020
static void rx_set_checksum(struct sky2_port *sky2)
1021
{
1022
	struct sky2_rx_le *le = sky2_next_rx(sky2);
1023

1024 1025 1026
	le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
	le->ctrl = 0;
	le->opcode = OP_TCPSTART | HW_OWNER;
1027

1028 1029 1030
	sky2_write32(sky2->hw,
		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
		     sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1031 1032
}

1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
/*
 * The RX Stop command will not work for Yukon-2 if the BMU does not
 * reach the end of packet and since we can't make sure that we have
 * incoming data, we must reset the BMU while it is not doing a DMA
 * transfer. Since it is possible that the RX path is still active,
 * the RX RAM buffer will be stopped first, so any possible incoming
 * data will not trigger a DMA. After the RAM buffer is stopped, the
 * BMU is polled until any DMA in progress is ended and only then it
 * will be reset.
 */
static void sky2_rx_stop(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned rxq = rxqaddr[sky2->port];
	int i;

	/* disable the RAM Buffer receive queue */
	sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

	for (i = 0; i < 0xffff; i++)
		if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
		    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
			goto stopped;

	printk(KERN_WARNING PFX "%s: receiver stop failed\n",
	       sky2->netdev->name);
stopped:
	sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

	/* reset the Rx prefetch unit */
	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1064
	mmiowb();
1065
}
1066

1067
/* Clean out receive buffer area, assumes receiver hardware stopped */
1068 1069 1070 1071 1072
static void sky2_rx_clean(struct sky2_port *sky2)
{
	unsigned i;

	memset(sky2->rx_le, 0, RX_LE_BYTES);
1073
	for (i = 0; i < sky2->rx_pending; i++) {
1074
		struct rx_ring_info *re = sky2->rx_ring + i;
1075 1076

		if (re->skb) {
1077
			sky2_rx_unmap_skb(sky2->hw->pdev, re);
1078 1079 1080 1081 1082 1083
			kfree_skb(re->skb);
			re->skb = NULL;
		}
	}
}

1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
/* Basic MII support */
static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	int err = -EOPNOTSUPP;

	if (!netif_running(dev))
		return -ENODEV;	/* Phy still in reset */

1095
	switch (cmd) {
1096 1097 1098 1099 1100 1101
	case SIOCGMIIPHY:
		data->phy_id = PHY_ADDR_MARV;

		/* fallthru */
	case SIOCGMIIREG: {
		u16 val = 0;
1102

1103
		spin_lock_bh(&sky2->phy_lock);
1104
		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1105
		spin_unlock_bh(&sky2->phy_lock);
1106

1107 1108 1109 1110 1111 1112 1113 1114
		data->val_out = val;
		break;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

1115
		spin_lock_bh(&sky2->phy_lock);
1116 1117
		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
				   data->val_in);
1118
		spin_unlock_bh(&sky2->phy_lock);
1119 1120 1121 1122 1123
		break;
	}
	return err;
}

1124 1125 1126 1127 1128 1129 1130
#ifdef SKY2_VLAN_TAG_USED
static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

1131
	netif_tx_lock_bh(dev);
1132
	napi_disable(&hw->napi);
1133 1134

	sky2->vlgrp = grp;
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
	if (grp) {
		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
			     RX_VLAN_STRIP_ON);
		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
			     TX_VLAN_TAG_ON);
	} else {
		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
			     RX_VLAN_STRIP_OFF);
		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
			     TX_VLAN_TAG_OFF);
	}
1146

1147
	napi_enable(&hw->napi);
1148
	netif_tx_unlock_bh(dev);
1149 1150 1151
}
#endif

1152
/*
1153 1154 1155
 * Allocate an skb for receiving. If the MTU is large enough
 * make the skb non-linear with a fragment list of pages.
 *
1156 1157
 * It appears the hardware has a bug in the FIFO logic that
 * cause it to hang if the FIFO gets overrun and the receive buffer
1158 1159
 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
 * aligned except if slab debugging is enabled.
1160
 */
1161
static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1162 1163
{
	struct sk_buff *skb;
1164 1165
	unsigned long p;
	int i;
1166

1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
	skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
	if (!skb)
		goto nomem;

	p = (unsigned long) skb->data;
	skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);

	for (i = 0; i < sky2->rx_nfrags; i++) {
		struct page *page = alloc_page(GFP_ATOMIC);

		if (!page)
			goto free_partial;
		skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1180 1181 1182
	}

	return skb;
1183 1184 1185 1186
free_partial:
	kfree_skb(skb);
nomem:
	return NULL;
1187 1188
}

Stephen Hemminger's avatar
Stephen Hemminger committed
1189 1190 1191 1192 1193
static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
{
	sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
}