Commit 9b1283be authored by Russell King's avatar Russell King Committed by Russell King
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[ARM] Add support for Realview with MPcore tile



Add uniprocessor support for Realview platform fitted with the
MPcore (SMP) tile.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 01bbaf0b
......@@ -8,4 +8,13 @@ config MACH_REALVIEW_EB
help
Include support for the ARM(R) RealView Emulation Baseboard platform.
config REALVIEW_MPCORE
bool "Support MPcore tile"
depends on MACH_REALVIEW_EB
help
Enable support for the MPCore tile on the Realview platform.
Since there are device address and interrupt differences, a
kernel built with this option enabled is not compatible with
other tiles.
endmenu
......@@ -136,6 +136,11 @@ static struct amba_device *amba_devs[] __initdata = {
static void __init gic_init_irq(void)
{
#ifdef CONFIG_REALVIEW_MPCORE
writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
writel(0x008003c0, __io_address(REALVIEW_SYS_BASE) + 0xd8);
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
#endif
gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));
gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
}
......
......@@ -203,8 +203,13 @@
/* Reserved 0x1001A000 - 0x1001FFFF */
#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
#ifndef CONFIG_REALVIEW_MPCORE
#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
#else
#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
#endif
#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
/* Reserved 0x10090000 - 0x100EFFFF */
......@@ -265,6 +270,7 @@
* Interrupts - bit assignment (primary)
* ------------------------------------------------------------------------
*/
#ifndef CONFIG_REALVIEW_MPCORE
#define INT_WDOGINT 0 /* Watchdog timer */
#define INT_SOFTINT 1 /* Software interrupt */
#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
......@@ -297,6 +303,55 @@
#define INT_USB 29 /* USB controller */
#define INT_TSPENINT 30 /* Touchscreen pen */
#define INT_TSKPADINT 31 /* Touchscreen keypad */
#else
#define INT_LOCALTIMER 29
#define INT_LOCALWDOG 30
#define INT_AACI 0
#define INT_TIMERINT0_1 1
#define INT_TIMERINT2_3 2
#define INT_USB 3
#define INT_UARTINT0 4
#define INT_UARTINT1 5
#define INT_RTCINT 6
#define INT_KMI0 7
#define INT_KMI1 8
#define INT_ETH 9
#define INT_EB_IRQ1 10 /* main GIC */
#define INT_EB_IRQ2 11 /* tile GIC */
#define INT_EB_FIQ1 12 /* main GIC */
#define INT_EB_FIQ2 13 /* tile GIC */
#define INT_MMCI0A 14
#define INT_MMCI0B 15
#define INT_PMU_CPU0 17
#define INT_PMU_CPU1 18
#define INT_PMU_CPU2 19
#define INT_PMU_CPU3 20
#define INT_PMU_SCU0 21
#define INT_PMU_SCU1 22
#define INT_PMU_SCU2 23
#define INT_PMU_SCU3 24
#define INT_PMU_SCU4 25
#define INT_PMU_SCU5 26
#define INT_PMU_SCU6 27
#define INT_PMU_SCU7 28
#define INT_L220_EVENT 29
#define INT_L220_SLAVE 30
#define INT_L220_DECODE 31
#define INT_UARTINT2 -1
#define INT_UARTINT3 -1
#define INT_CLCDINT -1
#define INT_DMAINT -1
#define INT_WDOGINT -1
#define INT_GPIOINT0 -1
#define INT_GPIOINT1 -1
#define INT_GPIOINT2 -1
#define INT_SCIINT -1
#define INT_SSPINT -1
#endif
/*
* Interrupt bit positions
......
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