sata_nv.c 68.1 KB
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/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
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 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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 *
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 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
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 *  CK804/MCP04 controllers support an alternate programming interface
 *  similar to the ADMA specification (with some modifications).
 *  This allows the use of NCQ. Non-DMA-mapped ATA commands are still
 *  sent through the legacy interface.
 *
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 */

#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_device.h>
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#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
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#define DRV_VERSION			"3.5"
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#define NV_ADMA_DMA_BOUNDARY		0xffffffffUL
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enum {
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	NV_MMIO_BAR			= 5,

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	NV_PORTS			= 2,
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	NV_PIO_MASK			= ATA_PIO4,
	NV_MWDMA_MASK			= ATA_MWDMA2,
	NV_UDMA_MASK			= ATA_UDMA6,
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	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,
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	/* INT_STATUS/ENABLE */
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	NV_INT_STATUS			= 0x10,
	NV_INT_ENABLE			= 0x11,
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	NV_INT_STATUS_CK804		= 0x440,
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	NV_INT_ENABLE_CK804		= 0x441,
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	/* INT_STATUS/ENABLE bits */
	NV_INT_DEV			= 0x01,
	NV_INT_PM			= 0x02,
	NV_INT_ADDED			= 0x04,
	NV_INT_REMOVED			= 0x08,

	NV_INT_PORT_SHIFT		= 4,	/* each port occupies 4 bits */

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	NV_INT_ALL			= 0x0f,
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	NV_INT_MASK			= NV_INT_DEV |
					  NV_INT_ADDED | NV_INT_REMOVED,
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	/* INT_CONFIG */
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	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI
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	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
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	NV_MCP_SATA_CFG_20_PORT0_EN	= (1 << 17),
	NV_MCP_SATA_CFG_20_PORT1_EN	= (1 << 16),
	NV_MCP_SATA_CFG_20_PORT0_PWB_EN	= (1 << 14),
	NV_MCP_SATA_CFG_20_PORT1_PWB_EN	= (1 << 12),

	NV_ADMA_MAX_CPBS		= 32,
	NV_ADMA_CPB_SZ			= 128,
	NV_ADMA_APRD_SZ			= 16,
	NV_ADMA_SGTBL_LEN		= (1024 - NV_ADMA_CPB_SZ) /
					   NV_ADMA_APRD_SZ,
	NV_ADMA_SGTBL_TOTAL_LEN		= NV_ADMA_SGTBL_LEN + 5,
	NV_ADMA_SGTBL_SZ                = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
	NV_ADMA_PORT_PRIV_DMA_SZ        = NV_ADMA_MAX_CPBS *
					   (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),

	/* BAR5 offset to ADMA general registers */
	NV_ADMA_GEN			= 0x400,
	NV_ADMA_GEN_CTL			= 0x00,
	NV_ADMA_NOTIFIER_CLEAR		= 0x30,

	/* BAR5 offset to ADMA ports */
	NV_ADMA_PORT			= 0x480,

	/* size of ADMA port register space  */
	NV_ADMA_PORT_SIZE		= 0x100,

	/* ADMA port registers */
	NV_ADMA_CTL			= 0x40,
	NV_ADMA_CPB_COUNT		= 0x42,
	NV_ADMA_NEXT_CPB_IDX		= 0x43,
	NV_ADMA_STAT			= 0x44,
	NV_ADMA_CPB_BASE_LOW		= 0x48,
	NV_ADMA_CPB_BASE_HIGH		= 0x4C,
	NV_ADMA_APPEND			= 0x50,
	NV_ADMA_NOTIFIER		= 0x68,
	NV_ADMA_NOTIFIER_ERROR		= 0x6C,

	/* NV_ADMA_CTL register bits */
	NV_ADMA_CTL_HOTPLUG_IEN		= (1 << 0),
	NV_ADMA_CTL_CHANNEL_RESET	= (1 << 5),
	NV_ADMA_CTL_GO			= (1 << 7),
	NV_ADMA_CTL_AIEN		= (1 << 8),
	NV_ADMA_CTL_READ_NON_COHERENT	= (1 << 11),
	NV_ADMA_CTL_WRITE_NON_COHERENT	= (1 << 12),

	/* CPB response flag bits */
	NV_CPB_RESP_DONE		= (1 << 0),
	NV_CPB_RESP_ATA_ERR		= (1 << 3),
	NV_CPB_RESP_CMD_ERR		= (1 << 4),
	NV_CPB_RESP_CPB_ERR		= (1 << 7),

	/* CPB control flag bits */
	NV_CPB_CTL_CPB_VALID		= (1 << 0),
	NV_CPB_CTL_QUEUE		= (1 << 1),
	NV_CPB_CTL_APRD_VALID		= (1 << 2),
	NV_CPB_CTL_IEN			= (1 << 3),
	NV_CPB_CTL_FPDMA		= (1 << 4),

	/* APRD flags */
	NV_APRD_WRITE			= (1 << 1),
	NV_APRD_END			= (1 << 2),
	NV_APRD_CONT			= (1 << 3),

	/* NV_ADMA_STAT flags */
	NV_ADMA_STAT_TIMEOUT		= (1 << 0),
	NV_ADMA_STAT_HOTUNPLUG		= (1 << 1),
	NV_ADMA_STAT_HOTPLUG		= (1 << 2),
	NV_ADMA_STAT_CPBERR		= (1 << 4),
	NV_ADMA_STAT_SERROR		= (1 << 5),
	NV_ADMA_STAT_CMD_COMPLETE	= (1 << 6),
	NV_ADMA_STAT_IDLE		= (1 << 8),
	NV_ADMA_STAT_LEGACY		= (1 << 9),
	NV_ADMA_STAT_STOPPED		= (1 << 10),
	NV_ADMA_STAT_DONE		= (1 << 12),
	NV_ADMA_STAT_ERR		= NV_ADMA_STAT_CPBERR |
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					  NV_ADMA_STAT_TIMEOUT,
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	/* port flags */
	NV_ADMA_PORT_REGISTER_MODE	= (1 << 0),
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	NV_ADMA_ATAPI_SETUP_COMPLETE	= (1 << 1),
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	/* MCP55 reg offset */
	NV_CTL_MCP55			= 0x400,
	NV_INT_STATUS_MCP55		= 0x440,
	NV_INT_ENABLE_MCP55		= 0x444,
	NV_NCQ_REG_MCP55		= 0x448,

	/* MCP55 */
	NV_INT_ALL_MCP55		= 0xffff,
	NV_INT_PORT_SHIFT_MCP55		= 16,	/* each port occupies 16 bits */
	NV_INT_MASK_MCP55		= NV_INT_ALL_MCP55 & 0xfffd,

	/* SWNCQ ENABLE BITS*/
	NV_CTL_PRI_SWNCQ		= 0x02,
	NV_CTL_SEC_SWNCQ		= 0x04,

	/* SW NCQ status bits*/
	NV_SWNCQ_IRQ_DEV		= (1 << 0),
	NV_SWNCQ_IRQ_PM			= (1 << 1),
	NV_SWNCQ_IRQ_ADDED		= (1 << 2),
	NV_SWNCQ_IRQ_REMOVED		= (1 << 3),

	NV_SWNCQ_IRQ_BACKOUT		= (1 << 4),
	NV_SWNCQ_IRQ_SDBFIS		= (1 << 5),
	NV_SWNCQ_IRQ_DHREGFIS		= (1 << 6),
	NV_SWNCQ_IRQ_DMASETUP		= (1 << 7),

	NV_SWNCQ_IRQ_HOTPLUG		= NV_SWNCQ_IRQ_ADDED |
					  NV_SWNCQ_IRQ_REMOVED,

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};

/* ADMA Physical Region Descriptor - one SG segment */
struct nv_adma_prd {
	__le64			addr;
	__le32			len;
	u8			flags;
	u8			packet_len;
	__le16			reserved;
};

enum nv_adma_regbits {
	CMDEND	= (1 << 15),		/* end of command list */
	WNB	= (1 << 14),		/* wait-not-BSY */
	IGN	= (1 << 13),		/* ignore this entry */
	CS1n	= (1 << (4 + 8)),	/* std. PATA signals follow... */
	DA2	= (1 << (2 + 8)),
	DA1	= (1 << (1 + 8)),
	DA0	= (1 << (0 + 8)),
};

/* ADMA Command Parameter Block
   The first 5 SG segments are stored inside the Command Parameter Block itself.
   If there are more than 5 segments the remainder are stored in a separate
   memory area indicated by next_aprd. */
struct nv_adma_cpb {
	u8			resp_flags;    /* 0 */
	u8			reserved1;     /* 1 */
	u8			ctl_flags;     /* 2 */
	/* len is length of taskfile in 64 bit words */
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	u8			len;		/* 3  */
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	u8			tag;           /* 4 */
	u8			next_cpb_idx;  /* 5 */
	__le16			reserved2;     /* 6-7 */
	__le16			tf[12];        /* 8-31 */
	struct nv_adma_prd	aprd[5];       /* 32-111 */
	__le64			next_aprd;     /* 112-119 */
	__le64			reserved3;     /* 120-127 */
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};
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struct nv_adma_port_priv {
	struct nv_adma_cpb	*cpb;
	dma_addr_t		cpb_dma;
	struct nv_adma_prd	*aprd;
	dma_addr_t		aprd_dma;
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	void __iomem		*ctl_block;
	void __iomem		*gen_block;
	void __iomem		*notifier_clear_block;
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	u64			adma_dma_mask;
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	u8			flags;
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	int			last_issue_ncq;
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};

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struct nv_host_priv {
	unsigned long		type;
};

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struct defer_queue {
	u32		defer_bits;
	unsigned int	head;
	unsigned int	tail;
	unsigned int	tag[ATA_MAX_QUEUE];
};

enum ncq_saw_flag_list {
	ncq_saw_d2h	= (1U << 0),
	ncq_saw_dmas	= (1U << 1),
	ncq_saw_sdb	= (1U << 2),
	ncq_saw_backout	= (1U << 3),
};

struct nv_swncq_port_priv {
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	struct ata_bmdma_prd *prd;	 /* our SG list */
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	dma_addr_t	prd_dma; /* and its DMA mapping */
	void __iomem	*sactive_block;
	void __iomem	*irq_block;
	void __iomem	*tag_block;
	u32		qc_active;

	unsigned int	last_issue_tag;

	/* fifo circular queue to store deferral command */
	struct defer_queue defer_queue;

	/* for NCQ interrupt analysis */
	u32		dhfis_bits;
	u32		dmafis_bits;
	u32		sdbfis_bits;

	unsigned int	ncq_flags;
};


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#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
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static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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#ifdef CONFIG_PM
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static int nv_pci_device_resume(struct pci_dev *pdev);
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#endif
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static void nv_ck804_host_stop(struct ata_host *host);
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
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static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
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static int nv_hardreset(struct ata_link *link, unsigned int *class,
			unsigned long deadline);
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static void nv_nf2_freeze(struct ata_port *ap);
static void nv_nf2_thaw(struct ata_port *ap);
static void nv_ck804_freeze(struct ata_port *ap);
static void nv_ck804_thaw(struct ata_port *ap);
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static int nv_adma_slave_config(struct scsi_device *sdev);
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static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
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static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
static void nv_adma_irq_clear(struct ata_port *ap);
static int nv_adma_port_start(struct ata_port *ap);
static void nv_adma_port_stop(struct ata_port *ap);
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#ifdef CONFIG_PM
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static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int nv_adma_port_resume(struct ata_port *ap);
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#endif
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static void nv_adma_freeze(struct ata_port *ap);
static void nv_adma_thaw(struct ata_port *ap);
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static void nv_adma_error_handler(struct ata_port *ap);
static void nv_adma_host_stop(struct ata_host *host);
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static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
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static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
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static void nv_mcp55_thaw(struct ata_port *ap);
static void nv_mcp55_freeze(struct ata_port *ap);
static void nv_swncq_error_handler(struct ata_port *ap);
static int nv_swncq_slave_config(struct scsi_device *sdev);
static int nv_swncq_port_start(struct ata_port *ap);
static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
#ifdef CONFIG_PM
static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int nv_swncq_port_resume(struct ata_port *ap);
#endif

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enum nv_host_type
{
	GENERIC,
	NFORCE2,
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	NFORCE3 = NFORCE2,	/* NF2 == NF3 as far as sata_nv is concerned */
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	CK804,
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	ADMA,
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	MCP5x,
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	SWNCQ,
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};

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static const struct pci_device_id nv_pci_tbl[] = {
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x },
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
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	{ } /* terminate list */
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};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
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#ifdef CONFIG_PM
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	.suspend		= ata_pci_device_suspend,
	.resume			= nv_pci_device_resume,
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#endif
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	.remove			= ata_pci_remove_one,
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};

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static struct scsi_host_template nv_sht = {
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	ATA_BMDMA_SHT(DRV_NAME),
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};

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static struct scsi_host_template nv_adma_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= NV_ADMA_MAX_CPBS,
	.sg_tablesize		= NV_ADMA_SGTBL_TOTAL_LEN,
	.dma_boundary		= NV_ADMA_DMA_BOUNDARY,
	.slave_configure	= nv_adma_slave_config,
};

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static struct scsi_host_template nv_swncq_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= ATA_MAX_QUEUE,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= nv_swncq_slave_config,
};

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/*
 * NV SATA controllers have various different problems with hardreset
 * protocol depending on the specific controller and device.
 *
 * GENERIC:
 *
 *  bko11195 reports that link doesn't come online after hardreset on
 *  generic nv's and there have been several other similar reports on
 *  linux-ide.
 *
 *  bko12351#c23 reports that warmplug on MCP61 doesn't work with
 *  softreset.
 *
 * NF2/3:
 *
 *  bko3352 reports nf2/3 controllers can't determine device signature
 *  reliably after hardreset.  The following thread reports detection
 *  failure on cold boot with the standard debouncing timing.
 *
 *  http://thread.gmane.org/gmane.linux.ide/34098
 *
 *  bko12176 reports that hardreset fails to bring up the link during
 *  boot on nf2.
 *
 * CK804:
 *
 *  For initial probing after boot and hot plugging, hardreset mostly
 *  works fine on CK804 but curiously, reprobing on the initial port
 *  by rescanning or rmmod/insmod fails to acquire the initial D2H Reg
 *  FIS in somewhat undeterministic way.
 *
 * SWNCQ:
 *
 *  bko12351 reports that when SWNCQ is enabled, for hotplug to work,
 *  hardreset should be used and hardreset can't report proper
 *  signature, which suggests that mcp5x is closer to nf2 as long as
 *  reset quirkiness is concerned.
 *
 *  bko12703 reports that boot probing fails for intel SSD with
 *  hardreset.  Link fails to come online.  Softreset works fine.
 *
 * The failures are varied but the following patterns seem true for
 * all flavors.
 *
 * - Softreset during boot always works.
 *
 * - Hardreset during boot sometimes fails to bring up the link on
 *   certain comibnations and device signature acquisition is
 *   unreliable.
 *
 * - Hardreset is often necessary after hotplug.
 *
 * So, preferring softreset for boot probing and error handling (as
 * hardreset might bring down the link) but using hardreset for
 * post-boot probing should work around the above issues in most
 * cases.  Define nv_hardreset() which only kicks in for post-boot
 * probing and use it for all variants.
 */
static struct ata_port_operations nv_generic_ops = {
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	.inherits		= &ata_bmdma_port_ops,
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	.lost_interrupt		= ATA_OP_NULL,
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	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
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	.hardreset		= nv_hardreset,
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};

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static struct ata_port_operations nv_nf2_ops = {
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	.inherits		= &nv_generic_ops,
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	.freeze			= nv_nf2_freeze,
	.thaw			= nv_nf2_thaw,
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};

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static struct ata_port_operations nv_ck804_ops = {
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	.inherits		= &nv_generic_ops,
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	.freeze			= nv_ck804_freeze,
	.thaw			= nv_ck804_thaw,
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	.host_stop		= nv_ck804_host_stop,
};

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static struct ata_port_operations nv_adma_ops = {
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	.inherits		= &nv_ck804_ops,
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	.check_atapi_dma	= nv_adma_check_atapi_dma,
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	.sff_tf_read		= nv_adma_tf_read,
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	.qc_defer		= ata_std_qc_defer,
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	.qc_prep		= nv_adma_qc_prep,
	.qc_issue		= nv_adma_qc_issue,
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	.sff_irq_clear		= nv_adma_irq_clear,
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	.freeze			= nv_adma_freeze,
	.thaw			= nv_adma_thaw,
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	.error_handler		= nv_adma_error_handler,
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	.post_internal_cmd	= nv_adma_post_internal_cmd,
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	.port_start		= nv_adma_port_start,
	.port_stop		= nv_adma_port_stop,
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#ifdef CONFIG_PM
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	.port_suspend		= nv_adma_port_suspend,
	.port_resume		= nv_adma_port_resume,
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#endif
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	.host_stop		= nv_adma_host_stop,
};

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static struct ata_port_operations nv_swncq_ops = {
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	.inherits		= &nv_generic_ops,
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	.qc_defer		= ata_std_qc_defer,
	.qc_prep		= nv_swncq_qc_prep,
	.qc_issue		= nv_swncq_qc_issue,
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	.freeze			= nv_mcp55_freeze,
	.thaw			= nv_mcp55_thaw,
	.error_handler		= nv_swncq_error_handler,
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#ifdef CONFIG_PM
	.port_suspend		= nv_swncq_port_suspend,
	.port_resume		= nv_swncq_port_resume,
#endif
	.port_start		= nv_swncq_port_start,
};

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struct nv_pi_priv {
	irq_handler_t			irq_handler;
	struct scsi_host_template	*sht;
};

#define NV_PI_PRIV(_irq_handler, _sht) \
	&(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht }

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static const struct ata_port_info nv_port_info[] = {
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	/* generic */
	{
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		.flags		= ATA_FLAG_SATA,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_generic_ops,
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		.private_data	= NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
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	},
	/* nforce2/3 */
	{
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		.flags		= ATA_FLAG_SATA,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_nf2_ops,
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		.private_data	= NV_PI_PRIV(nv_nf2_interrupt, &nv_sht),
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	},
	/* ck804 */
	{
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		.flags		= ATA_FLAG_SATA,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_ck804_ops,
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		.private_data	= NV_PI_PRIV(nv_ck804_interrupt, &nv_sht),
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	},
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	/* ADMA */
	{
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NCQ,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_adma_ops,
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		.private_data	= NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht),
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	},
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	/* MCP5x */
	{
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		.flags		= ATA_FLAG_SATA,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
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		.port_ops	= &nv_generic_ops,
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		.private_data	= NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
	},
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	/* SWNCQ */
	{
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		.flags	        = ATA_FLAG_SATA | ATA_FLAG_NCQ,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_swncq_ops,
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		.private_data	= NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht),
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	},
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};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

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static bool adma_enabled;
static bool swncq_enabled = 1;
static bool msi_enabled;
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static void nv_adma_register_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
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	void __iomem *mmio = pp->ctl_block;
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	u16 tmp, status;
	int count = 0;
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	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
		return;

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	status = readw(mmio + NV_ADMA_STAT);
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	while (!(status & NV_ADMA_STAT_IDLE) && count < 20) {
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		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
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	if (count == 20)
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		ata_port_warn(ap, "timeout waiting for ADMA IDLE, stat=0x%hx\n",
			      status);
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	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

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	count = 0;
	status = readw(mmio + NV_ADMA_STAT);
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	while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
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		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
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	if (count == 20)
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		ata_port_warn(ap,
			      "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
			      status);
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	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
}

static void nv_adma_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
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	void __iomem *mmio = pp->ctl_block;
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	u16 tmp, status;
	int count = 0;
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	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
		return;
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	WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

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	status = readw(mmio + NV_ADMA_STAT);
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	while (((status & NV_ADMA_STAT_LEGACY) ||
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	      !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
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	if (count == 20)
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		ata_port_warn(ap,
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			"timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
			status);

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	pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
}

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static int nv_adma_slave_config(struct scsi_device *sdev)
{
	struct ata_port *ap = ata_shost_to_port(sdev->host);
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	struct nv_adma_port_priv *pp = ap->private_data;
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	struct nv_adma_port_priv *port0, *port1;
	struct scsi_device *sdev0, *sdev1;
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	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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	unsigned long segment_boundary, flags;
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	unsigned short sg_tablesize;
	int rc;
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	int adma_enable;
	u32 current_reg, new_reg, config_mask;
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	rc = ata_scsi_slave_config(sdev);

	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
		/* Not a proper libata device, ignore */
		return rc;

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	spin_lock_irqsave(ap->lock, flags);

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	if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
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		/*
		 * NVIDIA reports that ADMA mode does not support ATAPI commands.
		 * Therefore ATAPI commands are sent through the legacy interface.
		 * However, the legacy interface only supports 32-bit DMA.
		 * Restrict DMA parameters as required by the legacy interface
		 * when an ATAPI device is connected.
		 */
		segment_boundary = ATA_DMA_BOUNDARY;
		/* Subtract 1 since an extra entry may be needed for padding, see
		   libata-scsi.c */
		sg_tablesize = LIBATA_MAX_PRD - 1;
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		/* Since the legacy DMA engine is in use, we need to disable ADMA
		   on the port. */
		adma_enable = 0;
		nv_adma_register_mode(ap);
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	} else {
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		segment_boundary = NV_ADMA_DMA_BOUNDARY;
		sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
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		adma_enable = 1;
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	}
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	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);

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	if (ap->port_no == 1)
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		config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
			      NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
	else
		config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
			      NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
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	if (adma_enable) {
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		new_reg = current_reg | config_mask;
		pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
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	} else {
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		new_reg = current_reg & ~config_mask;
		pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
	}
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	if (current_reg != new_reg)
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		pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
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	port0 = ap->host->ports[0]->private_data;
	port1 = ap->host->ports[1]->private_data;
	sdev0 = ap->host->ports[0]->link.device[0].sdev;
	sdev1 = ap->host->ports[1]->link.device[0].sdev;
	if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
	    (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
		/** We have to set the DMA mask to 32-bit if either port is in
		    ATAPI mode, since they are on the same PCI device which is
		    used for DMA mapping. If we set the mask we also need to set
		    the bounce limit on both ports to ensure that the block
		    layer doesn't feed addresses that cause DMA mapping to
		    choke. If either SCSI device is not allocated yet, it's OK
		    since that port will discover its correct setting when it
		    does get allocated.
		    Note: Setting 32-bit mask should not fail. */
		if (sdev0)
			blk_queue_bounce_limit(sdev0->request_queue,
					       ATA_DMA_MASK);
		if (sdev1)
			blk_queue_bounce_limit(sdev1->request_queue,
					       ATA_DMA_MASK);

		pci_set_dma_mask(pdev, ATA_DMA_MASK);
	} else {
		/** This shouldn't fail as it was set to this value before */
		pci_set_dma_mask(pdev, pp->adma_dma_mask);
		if (sdev0)
			blk_queue_bounce_limit(sdev0->request_queue,
					       pp->adma_dma_mask);
		if (sdev1)
			blk_queue_bounce_limit(sdev1->request_queue,
					       pp->adma_dma_mask);
	}

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	blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
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	blk_queue_max_segments(sdev->request_queue, sg_tablesize);
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	ata_port_info(ap,
		      "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
		      (unsigned long long)*ap->host->dev->dma_mask,
		      segment_boundary, sg_tablesize);
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	spin_unlock_irqrestore(ap->lock, flags);

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	return rc;
}

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static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
}

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static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
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	/* Other than when internal or pass-through commands are executed,
	   the only time this function will be called in ADMA mode will be
	   if a command fails. In the failure case we don't care about going
	   into register mode with ADMA commands pending, as the commands will
	   all shortly be aborted anyway. We assume that NCQ commands are not
	   issued via passthrough, which is the only way that switching into
	   ADMA mode could abort outstanding commands. */
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	nv_adma_register_mode(ap);

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	ata_sff_tf_read(ap, tf);
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}

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static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
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{
	unsigned int idx = 0;

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	if (tf->flags & ATA_TFLAG_ISADDR) {
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		if (tf->flags & ATA_TFLAG_LBA48) {
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR   << 8) | tf->hob_feature | WNB);
			cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAL  << 8) | tf->hob_lbal);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAM  << 8) | tf->hob_lbam);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAH  << 8) | tf->hob_lbah);
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature);
		} else
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature | WNB);
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		cpb[idx++] = cpu_to_le16((ATA_REG_NSECT  << 8) | tf->nsect);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAL   << 8) | tf->lbal);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAM   << 8) | tf->lbam);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAH   << 8) | tf->lbah);
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	}
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	if (tf->flags & ATA_TFLAG_DEVICE)
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		cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
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	cpb[idx++] = cpu_to_le16((ATA_REG_CMD    << 8) | tf->command | CMDEND);
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	while (idx < 12)
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		cpb[idx++] = cpu_to_le16(IGN);
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	return idx;
}

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static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
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{
	struct nv_adma_port_priv *pp = ap->private_data;
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	u8 flags = pp->cpb[cpb_num].resp_flags;
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	VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);

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	if (unlikely((force_err ||
		     flags & (NV_CPB_RESP_ATA_ERR |
			      NV_CPB_RESP_CMD_ERR |
			      NV_CPB_RESP_CPB_ERR)))) {
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		struct ata_eh_info *ehi = &ap->link.eh_info;
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		int freeze = 0;

		ata_ehi_clear_desc(ehi);
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		__ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags);
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		if (flags & NV_CPB_RESP_ATA_ERR) {
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			ata_ehi_push_desc(ehi, "ATA error");
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			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CMD_ERR) {
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			ata_ehi_push_desc(ehi, "CMD error");
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			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CPB_ERR) {
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			ata_ehi_push_desc(ehi, "CPB error");
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			ehi->err_mask |= AC_ERR_SYSTEM;
			freeze = 1;
		} else {
			/* notifier error, but no error in CPB flags? */
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			ata_ehi_push_desc(ehi, "unknown");
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			ehi->err_mask |= AC_ERR_OTHER;
			freeze = 1;
		}
		/* Kill all commands. EH will determine what actually failed. */
		if (freeze)
			ata_port_freeze(ap);
		else
			ata_port_abort(ap);
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		return -1;
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	}
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	if (likely(flags & NV_CPB_RESP_DONE))
		return 1;
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	return 0;
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}

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static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
{
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	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
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	/* freeze if hotplugged */
	if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
		ata_port_freeze(ap);
		return 1;
	}

	/* bail out if not our interrupt */
	if (!(irq_stat & NV_INT_DEV))
		return 0;

	/* DEV interrupt w/ no active qc? */
	if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
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		ata_sff_check_status(ap);
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		return 1;
	}

	/* handle interrupt */
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	return ata_bmdma_port_intr(ap, qc);
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}

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static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	int i, handled = 0;
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	u32 notifier_clears[2];
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	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
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		struct nv_adma_port_priv *pp = ap->private_data;
		void __iomem *mmio = pp->ctl_block;
		u16 status;
		u32 gen_ctl;
		u32 notifier, notifier_error;

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		notifier_clears[i] = 0;
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		/* if ADMA is disabled, use standard ata interrupt handler */
		if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
			u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
				>> (NV_INT_PORT_SHIFT * i);
			handled += nv_host_intr(ap, irq_stat);
			continue;
		}
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		/* if in ATA register mode, check for standard interrupts */
		if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
			u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
				>> (NV_INT_PORT_SHIFT * i);
			if (ata_tag_valid(ap->link.active_tag))
				/** NV_INT_DEV indication seems unreliable
				    at times at least in ADMA mode. Force it
				    on always when a command is active, to
				    prevent losing interrupts. */
				irq_stat |= NV_INT_DEV;
			handled += nv_host_intr(ap, irq_stat);
		}

		notifier = readl(mmio + NV_ADMA_NOTIFIER);
		notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
		notifier_clears[i] = notifier | notifier_error;

		gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);

		if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
		    !notifier_error)
			/* Nothing to do */
			continue;

		status = readw(mmio + NV_ADMA_STAT);

		/*
		 * Clear status. Ensure the controller sees the
		 * clearing before we start looking at any of the CPB
		 * statuses, so that any CPB completions after this
		 * point in the handler will raise another interrupt.
		 */
		writew(status, mmio + NV_ADMA_STAT);
		readw(mmio + NV_ADMA_STAT); /* flush posted write */
		rmb();
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		handled++; /* irq handled if we got here */

		/* freeze if hotplugged or controller error */
		if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
				       NV_ADMA_STAT_HOTUNPLUG |
				       NV_ADMA_STAT_TIMEOUT |
				       NV_ADMA_STAT_SERROR))) {
			struct ata_eh_info *ehi = &ap->link.eh_info;

			ata_ehi_clear_desc(ehi);
			__ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
			if (status & NV_ADMA_STAT_TIMEOUT) {
				ehi->err_mask |= AC_ERR_SYSTEM;
				ata_ehi_push_desc(ehi, "timeout");
			} else if (status & NV_ADMA_STAT_HOTPLUG) {
				ata_ehi_hotplugged(ehi);
				ata_ehi_push_desc(ehi, "hotplug");
			} else if (status & NV_ADMA_STAT_HOTUNPLUG) {
				ata_ehi_hotplugged(ehi);
				ata_ehi_push_desc(ehi, "hot unplug");
			} else if (status & NV_ADMA_STAT_SERROR) {
				/* let EH analyze SError and figure out cause */
				ata_ehi_push_desc(ehi, "SError");
			} else
				ata_ehi_push_desc(ehi, "unknown");
			ata_port_freeze(ap);
			continue;
		}

		if (status & (NV_ADMA_STAT_DONE |
			      NV_ADMA_STAT_CPBERR |
			      NV_ADMA_STAT_CMD_COMPLETE)) {
			u32 check_commands = notifier_clears[i];
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			u32 done_mask = 0;
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			int pos, rc;
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			if (status & NV_ADMA_STAT_CPBERR) {
				/* check all active commands */
				if (ata_tag_valid(ap->link.active_tag))
					check_commands = 1 <<
						ap->link.active_tag;
				else
					check_commands = ap->link.sactive;
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			}

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			/* check CPBs for completed commands */
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			while ((pos = ffs(check_commands))) {
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				pos--;
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				rc = nv_adma_check_cpb(ap, pos,
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						notifier_error & (1 << pos));
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				if (rc > 0)
					done_mask |= 1 << pos;
				else if (unlikely(rc < 0))
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					check_commands = 0;
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				check_commands &= ~(1 << pos);
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			}
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			ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
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		}
	}
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	if (notifier_clears[0] || notifier_clears[1]) {
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		/* Note: Both notifier clear registers must be written
		   if either is set, even if one is zero, according to NVIDIA. */
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		struct nv_adma_port_priv *pp = host->ports[0]->private_data;
		writel(notifier_clears[0], pp->notifier_clear_block);
		pp = host->ports[1]->private_data;
		writel(notifier_clears[1], pp->notifier_clear_block);
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	}
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	spin_unlock(&host->lock);

	return IRQ_RETVAL(handled);
}

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static void nv_adma_freeze(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_freeze(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* clear any outstanding CK804 notifications */
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	writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
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		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);

	/* Disable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
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	writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
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		mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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}

static void nv_adma_thaw(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_thaw(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* Enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
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	writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
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		mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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}

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static void nv_adma_irq_clear(struct ata_port *ap)
{
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	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
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	u32 notifier_clears[2];
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	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
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		ata_bmdma_irq_clear(ap);
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		return;
	}

	/* clear any outstanding CK804 notifications */
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	writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
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		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
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	/* clear ADMA status */
	writew(0xffff, mmio + NV_ADMA_STAT);
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	/* clear notifiers - note both ports need to be written with
	   something even though we are only clearing on one */
	if (ap->port_no == 0) {
		notifier_clears[0] = 0xFFFFFFFF;
		notifier_clears[1] = 0;
	} else {
		notifier_clears[0] = 0;
		notifier_clears[1] = 0xFFFFFFFF;
	}
	pp = ap->host->ports[0]->private_data;
	writel(notifier_clears[0], pp->notifier_clear_block);
	pp = ap->host->ports[1]->private_data;
	writel(notifier_clears[1], pp->notifier_clear_block);
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}

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static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
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{
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	struct nv_adma_port_priv *pp = qc->ap->private_data;
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	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
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		ata_bmdma_post_internal_cmd(qc);
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}

static int nv_adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct nv_adma_port_priv *pp;
	int rc;
	void *mem;
	dma_addr_t mem_dma;
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	void __iomem *mmio;
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	struct pci_dev *pdev = to_pci_dev(dev);
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	u16 tmp;

	VPRINTK("ENTER\n");

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	/* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
	   pad buffers */
	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;

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	/* we might fallback to bmdma, allocate bmdma resources */
	rc = ata_bmdma_port_start(ap);
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	if (rc)
		return rc;

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	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
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	mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
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	       ap->port_no * NV_ADMA_PORT_SIZE;
	pp->ctl_block = mmio;
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	pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
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	pp->notifier_clear_block = pp->gen_block +
	       NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);

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	/* Now that the legacy PRD and padding buffer are allocated we can
	   safely raise the DMA mask to allocate the CPB/APRD table.
	   These are allowed to fail since we store the value that ends up
	   being used to set as the bounce limit in slave_config later if
	   needed. */
	pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
	pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
	pp->adma_dma_mask = *dev->dma_mask;

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	mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
				  &mem_dma, GFP_KERNEL);
	if (!mem)
		return -ENOMEM;
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	memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory:
	 * 128-byte command parameter block (CPB)
	 * one for each command tag
	 */
	pp->cpb     = mem;
	pp->cpb_dma = mem_dma;

	writel(mem_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
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	writel((mem_dma >> 16) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);
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	mem     += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
	mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;

	/*
	 * Second item: block of ADMA_SGTBL_LEN s/g entries
	 */
	pp->aprd = mem;
	pp->aprd_dma = mem_dma;

	ap->private_data = pp;

	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags = NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

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	/* clear GO for register mode, enable interrupt */
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	tmp = readw(mmio + NV_ADMA_CTL);
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	writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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	return 0;
}

static void nv_adma_port_stop(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
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	void __iomem *mmio = pp->ctl_block;
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	VPRINTK("ENTER\n");
	writew(0, mmio + NV_ADMA_CTL);
}

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#ifdef CONFIG_PM
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static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;

	/* Go to register mode - clears GO */
	nv_adma_register_mode(ap);

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* disable interrupt, shut down port */
	writew(0, mmio + NV_ADMA_CTL);

	return 0;
}

static int nv_adma_port_resume(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	/* set CPB block location */
	writel(pp->cpb_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
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	writel((pp->cpb_dma >> 16) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);
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	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* clear GO for register mode, enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
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	writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
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	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
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	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
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	return 0;
}
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#endif
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static void nv_adma_setup_port(struct ata_port *ap)
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{
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	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	struct ata_ioports *ioport = &ap->ioaddr;
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	VPRINTK("ENTER\n");

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	mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
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	ioport->cmd_addr	= mmio;
	ioport->data_addr	= mmio + (ATA_REG_DATA * 4);
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	ioport->error_addr	=
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	ioport->feature_addr	= mmio + (ATA_REG_ERR * 4);
	ioport->nsect_addr	= mmio + (ATA_REG_NSECT * 4);
	ioport->lbal_addr	= mmio + (ATA_REG_LBAL * 4);
	ioport->lbam_addr	= mmio + (ATA_REG_LBAM * 4);
	ioport->lbah_addr	= mmio + (ATA_REG_LBAH * 4);
	ioport->device_addr	= mmio + (ATA_REG_DEVICE * 4);
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	ioport->status_addr	=
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	ioport->command_addr	= mmio + (ATA_REG_STATUS * 4);
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	ioport->altstatus_addr	=
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	ioport->ctl_addr	= mmio + 0x20;
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}

1307
static int nv_adma_host_init(struct ata_host *host)
1308
{
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	struct pci_dev *pdev = to_pci_dev(host->dev);
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	unsigned int i;
	u32 tmp32;

	VPRINTK("ENTER\n");

	/* enable ADMA on the ports */
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
	tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
		 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
		 NV_MCP_SATA_CFG_20_PORT1_EN |
		 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;

	pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);

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	for (i = 0; i < host->n_ports; i++)
		nv_adma_setup_port(host->ports[i]);
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	return 0;
}

static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
			      struct scatterlist *sg,
			      int idx,
			      struct nv_adma_prd *aprd)
{
1335
	u8 flags = 0;
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	if (qc->tf.flags & ATA_TFLAG_WRITE)
		flags |= NV_APRD_WRITE;
	if (idx == qc->n_elem - 1)
		flags |= NV_APRD_END;
	else if (idx != 4)
		flags |= NV_APRD_CONT;

	aprd->addr  = cpu_to_le64(((u64)sg_dma_address(sg)));
	aprd->len   = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
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	aprd->flags = flags;
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	aprd->packet_len = 0;
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}

static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	struct nv_adma_prd *aprd;
	struct scatterlist *sg;
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	unsigned int si;
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	VPRINTK("ENTER\n");

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	for_each_sg(qc->sg, sg, qc->n_elem, si) {
		aprd = (si < 5) ? &cpb->aprd[si] :
			       &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
		nv_adma_fill_aprd(qc, sg, si, aprd);
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	}
1363
	if (si > 5)
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		cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
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	else
		cpb->next_aprd = cpu_to_le64(0);
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}

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static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;

	/* ADMA engine can only be used for non-ATAPI DMA commands,
1374
	   or interrupt-driven no-data commands. */
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	if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
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	   (qc->tf.flags & ATA_TFLAG_POLLING))
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		return 1;

1379
	if ((qc->flags & ATA_QCFLAG_DMAMAP) ||
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	   (qc->tf.protocol == ATA_PROT_NODATA))
		return 0;

	return 1;
}

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static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
	u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
		       NV_CPB_CTL_IEN;

1393
	if (nv_adma_use_reg_mode(qc)) {
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		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
			(qc->flags & ATA_QCFLAG_DMAMAP));
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		nv_adma_register_mode(qc->ap);
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		ata_bmdma_qc_prep(qc);
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		return;
	}

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	cpb->resp_flags = NV_CPB_RESP_DONE;
	wmb();
	cpb->ctl_flags = 0;
	wmb();
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	cpb->len		= 3;
	cpb->tag		= qc->tag;
	cpb->next_cpb_idx	= 0;

	/* turn on NCQ flags for NCQ commands */
	if (qc->tf.protocol == ATA_PROT_NCQ)
		ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;

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	VPRINTK("qc->flags = 0x%lx\n", qc->flags);

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	nv_adma_tf_to_cpb(&qc->tf, cpb->tf);

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	if (qc->flags & ATA_QCFLAG_DMAMAP) {
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		nv_adma_fill_sg(qc, cpb);
		ctl_flags |= NV_CPB_CTL_APRD_VALID;
	} else
		memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
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	/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
	   until we are finished filling in all of the contents */
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	wmb();
	cpb->ctl_flags = ctl_flags;
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	wmb();
	cpb->resp_flags = 0;
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}

static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
{
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	struct nv_adma_port_priv *pp = qc->ap->private_data;
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	void __iomem *mmio = pp->ctl_block;
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	int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
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	VPRINTK("ENTER\n");

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	/* We can't handle result taskfile with NCQ commands, since
	   retrieving the taskfile switches us out of ADMA mode and would abort
	   existing commands. */
	if (unlikely(qc->tf.protocol == ATA_PROT_NCQ &&
		     (qc->flags & ATA_QCFLAG_RESULT_TF))) {
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		ata_dev_err(qc->dev, "NCQ w/ RESULT_TF not allowed\n");
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		return AC_ERR_SYSTEM;
	}

1449
	if (nv_adma_use_reg_mode(qc)) {
1450
		/* use ATA register mode */
1451
		VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
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		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
			(qc->flags & ATA_QCFLAG_DMAMAP));
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		nv_adma_register_mode(qc->ap);
1455
		return ata_bmdma_qc_issue(qc);
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	} else