Commit d4b2bab4 authored by Tejun Heo's avatar Tejun Heo Committed by Jeff Garzik

libata: add deadline support to prereset and reset methods

Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function.  This patch is in preparation for EH timing
improvements.

* ata_wait_ready() never does busy sleep.  It's only used from EH and
  no wait in EH is that urgent.  This function also prints 'be
  patient' message automatically after 5 secs of waiting if more than
  3 secs is remaining till deadline.

* ata_bus_post_reset() now fails with error code if any of its wait
  fails.  This is important because earlier reset tries will have
  shorter timeout than the spec requires.  If a device fails to
  respond before the short timeout, reset should be retried with
  longer timeout rather than silently ignoring the device.

  There are three behavior differences.

  1. Timeout is applied to both devices at once, not separately.  This
     is more consistent with what the spec says.

  2. When a device passes devchk but fails to become ready before
     deadline.  Previouly, post_reset would just succeed and let
     device classification remove the device.  New code fails the
     reset thus causing reset retry.  After a few times, EH will give
     up disabling the port.

  3. When slave device passes devchk but fails to become accessible
     (TF-wise) after reset.  Original code disables dev1 after 30s
     timeout and continues as if the device doesn't exist, while the
     patched code fails reset.  When this happens, new code fails
     reset on whole port rather than proceeding with only the primary
     device.

  If the failing device is suffering transient problems, new code
  retries reset which is a better behavior.  If the failing device is
  actually broken, the net effect is identical to it, but not to the
  other device sharing the channel.  In the previous code, reset would
  have succeeded after 30s thus detecting the working one.  In the new
  code, reset fails and whole port gets disabled.  IMO, it's a
  pathological case anyway (broken device sharing bus with working
  one) and doesn't really matter.

* ata_bus_softreset() is changed to return error code from
  ata_bus_post_reset().  It used to return 0 unconditionally.

* Spin up waiting is to be removed and not converted to honor
  deadline.

* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: 's avatarTejun Heo <htejun@gmail.com>
Signed-off-by: 's avatarJeff Garzik <jeff@garzik.org>
parent dc87c398
......@@ -874,7 +874,8 @@ static int ahci_clo(struct ata_port *ap)
return 0;
}
static int ahci_softreset(struct ata_port *ap, unsigned int *class)
static int ahci_softreset(struct ata_port *ap, unsigned int *class,
unsigned long deadline)
{
struct ahci_port_priv *pp = ap->private_data;
void __iomem *port_mmio = ahci_port_base(ap);
......@@ -961,8 +962,8 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
*class = ATA_DEV_NONE;
if (ata_port_online(ap)) {
if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
rc = -EIO;
rc = ata_wait_ready(ap, deadline);
if (rc && rc != -ENODEV) {
reason = "device not ready";
goto fail;
}
......@@ -979,7 +980,8 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
return rc;
}
static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
unsigned long deadline)
{
struct ahci_port_priv *pp = ap->private_data;
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
......@@ -995,7 +997,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
tf.command = 0x80;
ata_tf_to_fis(&tf, d2h_fis, 0);
rc = sata_std_hardreset(ap, class);
rc = sata_std_hardreset(ap, class, deadline);
ahci_start_engine(ap);
......@@ -1008,7 +1010,8 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
return rc;
}
static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
unsigned long deadline)
{
int rc;
......@@ -1016,7 +1019,8 @@ static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
ahci_stop_engine(ap);
rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
deadline);
/* vt8251 needs SError cleared for the port to operate */
ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
......
......@@ -625,17 +625,18 @@ static int ich_pata_cable_detect(struct ata_port *ap)
/**
* piix_pata_prereset - prereset for PATA host controller
* @ap: Target port
* @deadline: deadline jiffies for the operation
*
* LOCKING:
* None (inherited from caller).
*/
static int piix_pata_prereset(struct ata_port *ap)
static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
static void piix_pata_error_handler(struct ata_port *ap)
......@@ -644,7 +645,6 @@ static void piix_pata_error_handler(struct ata_port *ap)
ata_std_postreset);
}
static void piix_sata_error_handler(struct ata_port *ap)
{
ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
......
This diff is collapsed.
......@@ -1558,14 +1558,14 @@ static void ata_eh_report(struct ata_port *ap)
}
static int ata_do_reset(struct ata_port *ap, ata_reset_fn_t reset,
unsigned int *classes)
unsigned int *classes, unsigned long deadline)
{
int i, rc;
for (i = 0; i < ATA_MAX_DEVICES; i++)
classes[i] = ATA_DEV_UNKNOWN;
rc = reset(ap, classes);
rc = reset(ap, classes, deadline);
if (rc)
return rc;
......@@ -1624,7 +1624,7 @@ static int ata_eh_reset(struct ata_port *ap, int classify,
ehc->i.action |= ATA_EH_HARDRESET;
if (prereset) {
rc = prereset(ap);
rc = prereset(ap, jiffies + 40 * HZ);
if (rc) {
if (rc == -ENOENT) {
ata_port_printk(ap, KERN_DEBUG,
......@@ -1676,7 +1676,7 @@ static int ata_eh_reset(struct ata_port *ap, int classify,
else
ehc->i.flags |= ATA_EHI_DID_SOFTRESET;
rc = ata_do_reset(ap, reset, classes);
rc = ata_do_reset(ap, reset, classes, jiffies + 40 * HZ);
did_followup_srst = 0;
if (reset == hardreset &&
......@@ -1693,7 +1693,7 @@ static int ata_eh_reset(struct ata_port *ap, int classify,
}
ata_eh_about_to_do(ap, NULL, ATA_EH_RESET_MASK);
rc = ata_do_reset(ap, reset, classes);
rc = ata_do_reset(ap, reset, classes, jiffies + 40 * HZ);
if (rc == 0 && classify &&
classes[0] == ATA_DEV_UNKNOWN) {
......
......@@ -121,12 +121,13 @@ static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offse
/**
* amd_probe_init - perform reset handling
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Reset sequence checking enable bits to see which ports are
* active.
*/
static int amd_pre_reset(struct ata_port *ap)
static int amd_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits amd_enable_bits[] = {
{ 0x40, 1, 0x02, 0x02 },
......@@ -138,8 +139,7 @@ static int amd_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
static void amd_error_handler(struct ata_port *ap)
......@@ -227,7 +227,8 @@ static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
* space for us.
*/
static int nv_pre_reset(struct ata_port *ap) {
static int nv_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits nv_enable_bits[] = {
{ 0x50, 1, 0x02, 0x02 },
{ 0x50, 1, 0x01, 0x01 }
......@@ -238,7 +239,7 @@ static int nv_pre_reset(struct ata_port *ap) {
if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
static void nv_error_handler(struct ata_port *ap)
......
......@@ -39,7 +39,7 @@
static int clock = 0;
static int artop6210_pre_reset(struct ata_port *ap)
static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
const struct pci_bits artop_enable_bits[] = {
......@@ -49,7 +49,8 @@ static int artop6210_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......@@ -70,12 +71,13 @@ static void artop6210_error_handler(struct ata_port *ap)
/**
* artop6260_pre_reset - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* The ARTOP hardware reports the cable detect bits in register 0x49.
* Nothing complicated needed here.
*/
static int artop6260_pre_reset(struct ata_port *ap)
static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits artop_enable_bits[] = {
{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
......
......@@ -33,7 +33,7 @@ enum {
ATIIXP_IDE_UDMA_MODE = 0x56
};
static int atiixp_pre_reset(struct ata_port *ap)
static int atiixp_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits atiixp_enable_bits[] = {
{ 0x48, 1, 0x01, 0x00 },
......@@ -44,7 +44,7 @@ static int atiixp_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
static void atiixp_error_handler(struct ata_port *ap)
......
......@@ -72,6 +72,7 @@
/**
* cs5535_cable_detect - detect cable type
* @ap: Port to detect on
* @deadline: deadline jiffies for the operation
*
* Perform cable detection for ATA66 capable cable. Return a libata
* cable type.
......
......@@ -27,12 +27,13 @@
/**
* efar_pre_reset - Enable bits
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Perform cable detection for the EFAR ATA interface. This is
* different to the PIIX arrangement
*/
static int efar_pre_reset(struct ata_port *ap)
static int efar_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits efar_enable_bits[] = {
{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
......@@ -43,7 +44,7 @@ static int efar_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -220,7 +220,7 @@ static int hpt36x_cable_detect(struct ata_port *ap)
return ATA_CBL_PATA80;
}
static int hpt36x_pre_reset(struct ata_port *ap)
static int hpt36x_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits hpt36x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
......@@ -231,7 +231,7 @@ static int hpt36x_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -307,11 +307,12 @@ static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
/**
* hpt37x_pre_reset - reset the hpt37x bus
* @ap: ATA port to reset
* @deadline: deadline jiffies for the operation
*
* Perform the initial reset handling for the 370/372 and 374 func 0
*/
static int hpt37x_pre_reset(struct ata_port *ap)
static int hpt37x_pre_reset(struct ata_port *ap, unsigned long deadline)
{
u8 scr2, ata66;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
......@@ -338,7 +339,7 @@ static int hpt37x_pre_reset(struct ata_port *ap)
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......@@ -353,7 +354,7 @@ static void hpt37x_error_handler(struct ata_port *ap)
ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}
static int hpt374_pre_reset(struct ata_port *ap)
static int hpt374_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits hpt37x_enable_bits[] = {
{ 0x50, 1, 0x04, 0x04 },
......@@ -388,7 +389,7 @@ static int hpt374_pre_reset(struct ata_port *ap)
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -148,13 +148,14 @@ static int hpt3x2n_cable_detect(struct ata_port *ap)
* Reset the hardware and state machine,
*/
static int hpt3xn_pre_reset(struct ata_port *ap)
static int hpt3xn_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
/* Reset the state machine */
pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
udelay(100);
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -24,12 +24,13 @@
/**
* it8213_pre_reset - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Filter out ports by the enable bits before doing the normal reset
* and probe.
*/
static int it8213_pre_reset(struct ata_port *ap)
static int it8213_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits it8213_enable_bits[] = {
{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
......@@ -37,7 +38,8 @@ static int it8213_pre_reset(struct ata_port *ap)
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -30,16 +30,17 @@ typedef enum {
/**
* jmicron_pre_reset - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Perform the PATA port setup we need.
*
* On the Jmicron 361/363 there is a single PATA port that can be mapped
* either as primary or secondary (or neither). We don't do any policy
* and setup here. We assume that has been done by init_one and the
* BIOS.
*/
static int jmicron_pre_reset(struct ata_port *ap)
static int jmicron_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u32 control;
......@@ -102,7 +103,7 @@ static int jmicron_pre_reset(struct ata_port *ap)
ap->cbl = ATA_CBL_SATA;
break;
}
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -25,11 +25,12 @@
/**
* marvell_pre_reset - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Perform the PATA port setup we need.
*/
static int marvell_pre_reset(struct ata_port *ap)
static int marvell_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u32 devices;
......@@ -67,6 +68,7 @@ static int marvell_cable_detect(struct ata_port *ap)
case 1: /* Legacy SATA port */
return ATA_CBL_SATA;
}
BUG();
return 0; /* Our BUG macro needs the right markup */
}
......
......@@ -46,14 +46,15 @@ enum {
SECONDARY = (1 << 14)
};
static int mpiix_pre_reset(struct ata_port *ap)
static int mpiix_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -33,11 +33,12 @@
/**
* ns87410_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Check enabled ports
*/
static int ns87410_pre_reset(struct ata_port *ap)
static int ns87410_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits ns87410_enable_bits[] = {
......@@ -47,7 +48,8 @@ static int ns87410_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &ns87410_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -30,11 +30,12 @@
/**
* oldpiix_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int oldpiix_pre_reset(struct ata_port *ap)
static int oldpiix_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits oldpiix_enable_bits[] = {
......@@ -44,7 +45,8 @@ static int oldpiix_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -47,11 +47,12 @@ enum {
/**
* opti_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int opti_pre_reset(struct ata_port *ap)
static int opti_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits opti_enable_bits[] = {
......@@ -61,7 +62,8 @@ static int opti_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &opti_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -48,11 +48,12 @@ static int pci_clock; /* 0 = 33 1 = 25 */
/**
* optidma_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int optidma_pre_reset(struct ata_port *ap)
static int optidma_pre_reset(struct ata_port *ap, unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
static const struct pci_bits optidma_enable_bits = {
......@@ -62,7 +63,7 @@ static int optidma_pre_reset(struct ata_port *ap)
if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -301,6 +301,7 @@ static inline int pdc2027x_port_enabled(struct ata_port *ap)
/**
* pdc2027x_prereset - prereset for PATA host controller
* @ap: Target port
* @deadline: deadline jiffies for the operation
*
* Probeinit including cable detection.
*
......@@ -308,12 +309,12 @@ static inline int pdc2027x_port_enabled(struct ata_port *ap)
* None (inherited from caller).
*/
static int pdc2027x_prereset(struct ata_port *ap)
static int pdc2027x_prereset(struct ata_port *ap, unsigned long deadline)
{
/* Check whether port enabled */
if (!pdc2027x_port_enabled(ap))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
/**
......
......@@ -139,12 +139,14 @@ static struct sv_cable_table cable_detect[] = {
/**
* serverworks_cable_detect - cable detection
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Perform cable detection according to the device and subvendor
* identifications
*/
static int serverworks_cable_detect(struct ata_port *ap) {
static int serverworks_cable_detect(struct ata_port *ap)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
struct sv_cable_table *cb = cable_detect;
......
......@@ -94,11 +94,13 @@ static int sil680_cable_detect(struct ata_port *ap) {
/**
* sil680_bus_reset - reset the SIL680 bus
* @ap: ATA port to reset
* @deadline: deadline jiffies for the operation
*
* Perform the SIL680 housekeeping when doing an ATA bus reset
*/
static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes,
unsigned long deadline)
{
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
unsigned long addr = sil680_selreg(ap, 0);
......@@ -108,7 +110,7 @@ static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
pci_write_config_byte(pdev, addr, reset | 0x03);
udelay(25);
pci_write_config_byte(pdev, addr, reset);
return ata_std_softreset(ap, classes);
return ata_std_softreset(ap, classes, deadline);
}
static void sil680_error_handler(struct ata_port *ap)
......
......@@ -88,6 +88,7 @@ static int sis_port_base(struct ata_device *adev)
/**
* sis_133_cable_detect - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Perform cable detection for the later UDMA133 capable
* SiS chipset.
......@@ -108,6 +109,7 @@ static int sis_133_cable_detect(struct ata_port *ap)
/**
* sis_66_cable_detect - check for 40/80 pin
* @ap: Port
* @deadline: deadline jiffies for the operation
*
* Perform cable detection on the UDMA66, UDMA100 and early UDMA133
* SiS IDE controllers.
......@@ -130,11 +132,12 @@ static int sis_66_cable_detect(struct ata_port *ap)
/**
* sis_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int sis_pre_reset(struct ata_port *ap)
static int sis_old_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits sis_enable_bits[] = {
{ 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
......@@ -145,7 +148,8 @@ static int sis_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
......
......@@ -44,11 +44,12 @@ enum {
/**
* sl82c105_pre_reset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int sl82c105_pre_reset(struct ata_port *ap)
static int sl82c105_pre_reset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits sl82c105_enable_bits[] = {
{ 0x40, 1, 0x01, 0x01 },
......@@ -58,7 +59,7 @@ static int sl82c105_pre_reset(struct ata_port *ap)
if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
......
......@@ -48,11 +48,12 @@
/**
* triflex_prereset - probe begin
* @ap: ATA port
* @deadline: deadline jiffies for the operation
*
* Set up cable type and use generic probe init
*/
static int triflex_prereset(struct ata_port *ap)
static int triflex_prereset(struct ata_port *ap, unsigned long deadline)
{
static const struct pci_bits triflex_enable_bits[] = {
{ 0x80, 1, 0x01, 0x01 },
......@@ -63,7 +64,8 @@ static int triflex_prereset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no]))
return -ENOENT;
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
......
......@@ -154,7 +154,7 @@ static int via_cable_detect(struct ata_port *ap) {
return ATA_CBL_PATA40;
}
static int via_pre_reset(struct ata_port *ap)
static int via_pre_reset(struct ata_port *ap, unsigned long deadline)
{
const struct via_isa_bridge *config = ap->host->private_data;
......@@ -167,7 +167,8 @@ static int via_pre_reset(struct ata_port *ap)
if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
return -ENOENT;
}
return ata_std_prereset(ap);
return ata_std_prereset(ap, deadline);
}
......
......@@ -420,7 +420,8 @@ static void inic_thaw(struct ata_port *ap)
* SRST and SControl hardreset don't give valid signature on this
* controller. Only controller specific hardreset mechanism works.
*/
static int inic_hardreset(struct ata_port *ap, unsigned int *class)
static int inic_hardreset(struct ata_port *ap, unsigned int *class,
unsigned long deadline)
{
void __iomem *port_base = inic_port_base(ap);
void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
......@@ -437,7 +438,7 @@ static int inic_hardreset(struct ata_port *ap, unsigned int *class)
msleep(1);
writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
rc = sata_phy_resume(ap, timing);
rc = sata_phy_resume(ap, timing, deadline);
if (rc) {
ata_port_printk(ap, KERN_WARNING, "failed to resume "
"link after reset (errno=%d)\n", rc);
......@@ -451,10 +452,11 @@ static int inic_hardreset(struct ata_port *ap, unsigned int *class)
/* wait a while before checking status */
msleep(150);
if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
ata_port_printk(ap, KERN_WARNING,
"device busy after hardreset\n");
return -EIO;
rc = ata_wait_ready(ap, deadline);
if (rc && rc != -ENODEV) {
ata_port_printk(ap, KERN_WARNING, "device not ready "
"after hardreset (errno=%d)\n", rc);
return rc;
}
ata_tf_read(ap, &tf);
......
......@@ -1405,7 +1405,8 @@ static void nv_ck804_thaw(struct ata_port *ap)