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/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
 * the OAI Public License, Version 1.0  (the "License"); you may not use this file
 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */
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/*! \file LAYER2/MAC/defs.h
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* \brief MAC data structures, constant, and function prototype
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* \author Navid Nikaein and Raymond Knopp
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* \date 2011
* \version 0.5
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* \email navid.nikaein@eurecom.fr
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*/
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/** @defgroup _oai2  openair2 Reference Implementation
 * @ingroup _ref_implementation_
 * @{
 */
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/*@}*/
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#ifndef __LAYER2_MAC_DEFS_H__
#define __LAYER2_MAC_DEFS_H__



#ifdef USER_MODE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif

//#include "COMMON/openair_defs.h"

#include "COMMON/platform_constants.h"
#include "COMMON/mac_rrc_primitives.h"
#include "PHY/defs.h"
#include "RadioResourceConfigCommon.h"
#include "RadioResourceConfigDedicated.h"
#include "MeasGapConfig.h"
#include "TDD-Config.h"
#include "RACH-ConfigCommon.h"
#include "MeasObjectToAddModList.h"
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#include "MobilityControlInfo.h"
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#ifdef Rel10
#include "MBSFN-AreaInfoList-r9.h"
#include "MBSFN-SubframeConfigList.h"
#include "PMCH-InfoList-r9.h"
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#include "SCellToAddMod-r10.h"
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#endif

//#ifdef PHY_EMUL
//#include "SIMULATION/PHY_EMULATION/impl_defs.h"
//#endif

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/** @defgroup _mac  MAC
 * @ingroup _oai2
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 * @{
 */

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#define BCCH_PAYLOAD_SIZE_MAX 128
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#define CCCH_PAYLOAD_SIZE_MAX 128
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#define PCCH_PAYLOAD_SIZE_MAX 128
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#define SCH_PAYLOAD_SIZE_MAX 4096
/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB)

#ifdef Rel10

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// Mask for identifying subframe for MBMS
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#define MBSFN_TDD_SF3 0x80// for TDD
#define MBSFN_TDD_SF4 0x40
#define MBSFN_TDD_SF7 0x20
#define MBSFN_TDD_SF8 0x10
#define MBSFN_TDD_SF9 0x08
#define MBSFN_FDD_SF1 0x80// for FDD
#define MBSFN_FDD_SF2 0x40
#define MBSFN_FDD_SF3 0x20
#define MBSFN_FDD_SF6 0x10
#define MBSFN_FDD_SF7 0x08
#define MBSFN_FDD_SF8 0x04

#define MAX_MBSFN_AREA 8
#define MAX_PMCH_perMBSFN 15
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/*!\brief MAX MCCH payload size  */
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#define MCCH_PAYLOAD_SIZE_MAX 128
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//#define MCH_PAYLOAD_SIZE_MAX 16384// this value is using in case mcs and TBS index are high
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#endif

#ifdef USER_MODE
#define printk printf
#endif //USER_MODE

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/*!\brief Maximum number of logical channl group IDs */
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#define MAX_NUM_LCGID 4
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/*!\brief logical channl group ID 0 */
#define LCGID0 0
/*!\brief logical channl group ID 1 */
#define LCGID1 1
/*!\brief logical channl group ID 2 */
#define LCGID2 2
/*!\brief logical channl group ID 3 */
#define LCGID3 3
/*!\brief Maximum number of logical chanels */
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#define MAX_NUM_LCID 11
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/*!\brief Maximum number od control elemenets */
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#define MAX_NUM_CE 5
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/*!\brief Maximum number of random access process */
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#define NB_RA_PROC_MAX 4
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/*!\brief size of buffer status report table */
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#define BSR_TABLE_SIZE 64
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/*!\brief The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1 */
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#define PHR_MAPPING_OFFSET 23  // if ( x>= -23 ) val = floor (x + 23) 
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/*!\brief maximum number of resource block groups */
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#define N_RBG_MAX 25 // for 20MHz channel BW
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/*!\brief minimum value for channel quality indicator */
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#define MIN_CQI_VALUE  0
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/*!\brief maximum value for channel quality indicator */
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#define MAX_CQI_VALUE  15

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#define LCID_EMPTY 0
#define LCID_NOT_EMPTY 1

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/* 
 * eNB part 
 */ 
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/* 
 * UE/ENB common part 
 */ 
/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */
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typedef struct {
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  uint8_t RAPID:6;
  uint8_t T:1;
  uint8_t E:1;
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} __attribute__((__packed__))RA_HEADER_RAPID;

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/*!\brief  MAC header of Random Access Response for backoff indicator (BI)*/
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typedef struct {
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  uint8_t BI:4;
  uint8_t R:2;
  uint8_t T:1;
  uint8_t E:1;
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} __attribute__((__packed__))RA_HEADER_BI;
/*
typedef struct {
  uint64_t padding:16;
  uint64_t t_crnti:16;
  uint64_t hopping_flag:1;
  uint64_t rb_alloc:10;
  uint64_t mcs:4;
  uint64_t TPC:3;
  uint64_t UL_delay:1;
  uint64_t cqi_req:1;
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t R:1;                        // octet MSB
  } __attribute__((__packed__))RAR_PDU;

typedef struct {
  uint64_t padding:16;
  uint64_t R:1;                        // octet MSB
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t cqi_req:1;
  uint64_t UL_delay:1;
  uint64_t TPC:3;
  uint64_t mcs:4;
  uint64_t rb_alloc:10;
  uint64_t hopping_flag:1;
  uint64_t t_crnti:16;
  } __attribute__((__packed__))RAR_PDU;

#define sizeof_RAR_PDU 6
*/
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/*!\brief  MAC subheader short with 7bit Length field */
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typedef struct {
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  uint8_t LCID:5;  // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;     // octet 1 MSB
  uint8_t L:7;     // octet 2 LSB
  uint8_t F:1;     // octet 2 MSB
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} __attribute__((__packed__))SCH_SUBHEADER_SHORT;
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/*!\brief  MAC subheader long  with 15bit Length field */
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typedef struct {
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  uint8_t LCID:5;   // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;      // octet 1 MSB
  uint8_t L_MSB:7;
  uint8_t F:1;      // octet 2 MSB
  uint8_t L_LSB:8;
  uint8_t padding;
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} __attribute__((__packed__))SCH_SUBHEADER_LONG;
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/*!\brief MAC subheader short without length field */
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typedef struct {
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  uint8_t LCID:5;
  uint8_t E:1;
  uint8_t R:2;
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} __attribute__((__packed__))SCH_SUBHEADER_FIXED;

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/*!\brief  mac control element: short buffer status report for a specific logical channel group ID*/
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typedef struct {
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  uint8_t Buffer_size:6;  // octet 1 LSB
  uint8_t LCGID:2;        // octet 1 MSB
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} __attribute__((__packed__))BSR_SHORT;

typedef BSR_SHORT BSR_TRUNCATED;
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/*!\brief  mac control element: long buffer status report for all logical channel group ID*/
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typedef struct {
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  uint32_t Buffer_size3:6;
  uint32_t Buffer_size2:6;
  uint32_t Buffer_size1:6;
  uint32_t Buffer_size0:6;
  uint32_t padding:8;
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} __attribute__((__packed__))BSR_LONG;

#define BSR_LONG_SIZE  (sizeof(BSR_LONG))
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/*!\brief  mac control element: timing advance  */
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typedef struct {
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  uint8_t TA:6;
  uint8_t R:2;
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} __attribute__((__packed__))TIMING_ADVANCE_CMD;
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/*!\brief  mac control element: power headroom report  */
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typedef struct {
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  uint8_t PH:6;
  uint8_t R:2;
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} __attribute__((__packed__))POWER_HEADROOM_CMD;

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/*!\brief  DCI PDU filled by MAC for the PHY  */
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typedef struct {
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  uint8_t Num_ue_spec_dci ;
  uint8_t Num_common_dci  ;
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  //  uint32_t nCCE;
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  uint32_t num_pdcch_symbols;
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  DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ;
} DCI_PDU;
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/*! \brief CCCH payload */
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typedef struct {
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  uint8_t payload[CCCH_PAYLOAD_SIZE_MAX] ;
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} __attribute__((__packed__))CCCH_PDU;
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/*! \brief BCCH payload */
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typedef struct {
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  uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ;
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} __attribute__((__packed__))BCCH_PDU;
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/*! \brief BCCH payload */
typedef struct {
  uint8_t payload[PCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))PCCH_PDU;
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#ifdef Rel10
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/*! \brief MCCH payload */
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typedef struct {
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  uint8_t payload[MCCH_PAYLOAD_SIZE_MAX] ;
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} __attribute__((__packed__))MCCH_PDU;
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/*!< \brief MAC control element for activation and deactivation of component carriers */
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typedef struct {
  uint8_t C7:1;/*!< \brief Component carrier 7 */
  uint8_t C6:1;/*!< \brief Component carrier 6 */
  uint8_t C5:1;/*!< \brief Component carrier 5 */
  uint8_t C4:1;/*!< \brief Component carrier 4 */
  uint8_t C3:1;/*!< \brief Component carrier 3 */
  uint8_t C2:1;/*!< \brief Component carrier 2 */
  uint8_t C1:1;/*!< \brief Component carrier 1 */
  uint8_t R:1;/*!< \brief Reserved  */
} __attribute__((__packed__))CC_ELEMENT;
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/*! \brief MAC control element: MCH Scheduling Information */
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typedef struct {
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  uint8_t stop_sf_MSB:3; // octet 1 LSB
  uint8_t lcid:5;        // octet 2 MSB
  uint8_t stop_sf_LSB:8;
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} __attribute__((__packed__))MSI_ELEMENT;
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#endif
/*! \brief Values of CCCH LCID for DLSCH */ 
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#define CCCH_LCHANID 0
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/*!\brief Values of BCCH logical channel */
#define BCCH 3  // SI 
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/*!\brief Values of PCCH logical channel */
#define PCCH 4  // Paging 
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/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0  // srb0
/*!\brief DCCH / SRB1 logical channel */
#define DCCH 1  // srb1
/*!\brief DCCH1 / SRB2  logical channel */
#define DCCH1 2 // srb2
/*!\brief DTCH DRB1  logical channel */
#define DTCH 3 // LCID
/*!\brief MCCH logical channel */
#define MCCH 4 
/*!\brief MTCH logical channel */
#define MTCH 1 
// DLSCH LCHAN ID
/*!\brief LCID of UE contention resolution identity for DLSCH*/
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#define UE_CONT_RES 28
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/*!\brief LCID of timing advance for DLSCH */
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#define TIMING_ADV_CMD 29
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/*!\brief LCID of discontinous reception mode for DLSCH */
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#define DRX_CMD 30
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/*!\brief LCID of padding LCID for DLSCH */
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#define SHORT_PADDING 31

#ifdef Rel10
// MCH LCHAN IDs (table6.2.1-4 TS36.321)
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/*!\brief LCID of MCCH for DL */
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#define MCCH_LCHANID 0
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/*!\brief LCID of MCH scheduling info for DL */
#define MCH_SCHDL_INFO 3
/*!\brief LCID of Carrier component activation/deactivation */
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#define CC_ACT_DEACT 27
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#endif

// ULSCH LCHAN IDs
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/*!\brief LCID of extended power headroom for ULSCH */
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#define EXTENDED_POWER_HEADROOM 25
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/*!\brief LCID of power headroom for ULSCH */
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#define POWER_HEADROOM 26
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/*!\brief LCID of CRNTI for ULSCH */
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#define CRNTI 27
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/*!\brief LCID of truncated BSR for ULSCH */
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#define TRUNCATED_BSR 28
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/*!\brief LCID of short BSR for ULSCH */
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#define SHORT_BSR 29
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/*!\brief LCID of long BSR for ULSCH */
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#define LONG_BSR 30

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/*! \brief Downlink SCH PDU Structure */
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typedef struct {
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  int8_t payload[8][SCH_PAYLOAD_SIZE_MAX];
  uint16_t Pdu_size[8];
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} __attribute__ ((__packed__)) DLSCH_PDU;

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/*! \brief MCH PDU Structure */
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typedef struct {
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  int8_t payload[SCH_PAYLOAD_SIZE_MAX];
  uint16_t Pdu_size;
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  uint8_t mcs;
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  uint8_t sync_area;
  uint8_t msi_active;
  uint8_t mcch_active;
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  uint8_t mtch_active;
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} __attribute__ ((__packed__)) MCH_PDU;

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/*! \brief Uplink SCH PDU Structure */
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typedef struct {
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  int8_t payload[SCH_PAYLOAD_SIZE_MAX];         /*!< \brief SACH payload */
  uint16_t Pdu_size;
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} __attribute__ ((__packed__)) ULSCH_PDU;

#include "PHY/impl_defs_top.h"

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/*!\brief  UE ULSCH scheduling states*/
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typedef enum {
  S_UL_NONE =0,
  S_UL_WAITING,
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  S_UL_SCHEDULED,
  S_UL_BUFFERED,
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  S_UL_NUM_STATUS
} UE_ULSCH_STATUS;

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/*!\brief  UE DLSCH scheduling states*/
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typedef enum {
  S_DL_NONE =0,
  S_DL_WAITING,
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  S_DL_SCHEDULED,
  S_DL_BUFFERED,
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  S_DL_NUM_STATUS
} UE_DLSCH_STATUS;

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/*!\brief  scheduling policy for the contention-based access */
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typedef enum {
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  CBA_ES=0, /// equal share of RB among groups w
  CBA_ES_S,  /// equal share of RB among groups with small allocation
  CBA_PF, /// proportional fair (kind of)
  CBA_PF_S,  /// proportional fair (kind of) with small RB allocation
  CBA_RS /// random allocation
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} CBA_POLICY;


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/*! \brief temporary struct for ULSCH sched */
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typedef struct {
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  rnti_t rnti;
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  uint16_t subframe;
  uint16_t serving_num;
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  UE_ULSCH_STATUS status;
} eNB_ULSCH_INFO;
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/*! \brief temp struct for DLSCH sched */
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typedef struct {
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  rnti_t rnti;
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  uint16_t weight;
  uint16_t subframe;
  uint16_t serving_num;
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  UE_DLSCH_STATUS status;
} eNB_DLSCH_INFO;
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/*! \brief eNB overall statistics */
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typedef struct {
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  /// num BCCH PDU per CC 
  uint32_t total_num_bcch_pdu;
  /// BCCH buffer size  
  uint32_t bcch_buffer;
  /// total BCCH buffer size  
  uint32_t total_bcch_buffer;
  /// BCCH MCS
  uint32_t bcch_mcs;

  /// num CCCH PDU per CC 
  uint32_t total_num_ccch_pdu;
  /// BCCH buffer size  
  uint32_t ccch_buffer;
  /// total BCCH buffer size  
  uint32_t total_ccch_buffer;
  /// BCCH MCS
  uint32_t ccch_mcs;

/// num active users
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  uint16_t num_dlactive_UEs;
  ///  available number of PRBs for a give SF
  uint16_t available_prbs;
  /// total number of PRB available for the user plane
  uint32_t total_available_prbs;
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  /// aggregation
  /// total avilable nccc : num control channel element
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  uint16_t available_ncces;
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  // only for a new transmission, should be extended for retransmission
  // current dlsch  bit rate for all transport channels
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  uint32_t dlsch_bitrate;
  //
  uint32_t dlsch_bytes_tx;
  //
  uint32_t dlsch_pdus_tx;
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  //
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  uint32_t total_dlsch_bitrate;
  //
  uint32_t total_dlsch_bytes_tx;
  //
  uint32_t total_dlsch_pdus_tx;
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  // here for RX
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  //
  uint32_t ulsch_bitrate;
  //
  uint32_t ulsch_bytes_rx;
  //
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  uint64_t ulsch_pdus_rx; 

  uint32_t total_ulsch_bitrate;
  //
  uint32_t total_ulsch_bytes_rx;
  //
  uint32_t total_ulsch_pdus_rx;
  
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} eNB_STATS;
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/*! \brief eNB statistics for the connected UEs*/
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typedef struct {
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  /// CRNTI of UE
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  rnti_t crnti; ///user id (rnti) of connected UEs
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  // rrc status
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  uint8_t rrc_status;
  /// harq pid
  uint8_t harq_pid;
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  /// harq rounf
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  uint8_t harq_round;
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  /// DL Wideband CQI index (2 TBs)
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  uint8_t dl_cqi;
  /// total available number of PRBs for a new transmission
  uint16_t rbs_used;
  /// total available number of PRBs for a retransmission
  uint16_t rbs_used_retx;
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  /// total nccc used for a new transmission: num control channel element
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  uint16_t ncce_used;
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  /// total avilable nccc for a retransmission: num control channel element
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  uint16_t ncce_used_retx;
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  // mcs1 before the rate adaptaion
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  uint8_t dlsch_mcs1;
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  /// Target mcs2 after rate-adaptation
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  uint8_t dlsch_mcs2;
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  //  current TBS with mcs2
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  uint32_t TBS;
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  //  total TBS with mcs2
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  //  uint32_t total_TBS;
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  //  total rb used for a new transmission
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  uint32_t total_rbs_used;
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  //  total rb used for retransmission
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  uint32_t total_rbs_used_retx;
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   /// TX
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  /// Num pkt
  uint32_t num_pdu_tx[NB_RB_MAX];
  /// num bytes
  uint32_t num_bytes_tx[NB_RB_MAX];
  /// num retransmission / harq
  uint32_t num_retransmission;
  /// instantaneous tx throughput for each TTI
  //  uint32_t tti_throughput[NB_RB_MAX];
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  /// overall
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  //
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  uint32_t  dlsch_bitrate;
  //total
  uint32_t  total_dlsch_bitrate;
  /// headers+ CE +  padding bytes for a MAC PDU
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  uint64_t overhead_bytes;
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  /// headers+ CE +  padding bytes for a MAC PDU
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  uint64_t total_overhead_bytes;
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  /// headers+ CE +  padding bytes for a MAC PDU
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  uint64_t avg_overhead_bytes;
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  // MAC multiplexed payload
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  uint64_t total_sdu_bytes;
  // total MAC pdu bytes
  uint64_t total_pdu_bytes;
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  // total num pdu
  uint32_t total_num_pdus;
  //
  //  uint32_t avg_pdu_size;
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  /// RX
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  /// preassigned mcs after rate adaptation
  uint8_t ulsch_mcs1;
  /// adjusted mcs
  uint8_t ulsch_mcs2;

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  /// estimated average pdu inter-departure time
  uint32_t avg_pdu_idt;
  /// estimated average pdu size
  uint32_t avg_pdu_ps;
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  ///
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  uint32_t aggregated_pdu_size;
  uint32_t aggregated_pdu_arrival;
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  ///  uplink transport block size
  uint32_t ulsch_TBS;

  ///  total rb used for a new uplink transmission
  uint32_t num_retransmission_rx;
  ///  total rb used for a new uplink transmission
  uint32_t rbs_used_rx;
   ///  total rb used for a new uplink retransmission
  uint32_t rbs_used_retx_rx;
  ///  total rb used for a new uplink transmission
  uint32_t total_rbs_used_rx;
  /// normalized rx power 
  int32_t      normalized_rx_power;
   /// target rx power 
  int32_t    target_rx_power;

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  /// num rx pdu
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  uint32_t num_pdu_rx[NB_RB_MAX];
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  /// num bytes rx
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  uint32_t num_bytes_rx[NB_RB_MAX];
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  /// instantaneous rx throughput for each TTI
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  //  uint32_t tti_goodput[NB_RB_MAX];
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  /// errors
  uint32_t num_errors_rx;
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  uint64_t overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t total_overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t avg_overhead_bytes_rx;
 //
  uint32_t  ulsch_bitrate;
  //total
  uint32_t  total_ulsch_bitrate;
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  /// overall
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  ///  MAC pdu bytes
  uint64_t pdu_bytes_rx;
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  /// total MAC pdu bytes
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  uint64_t total_pdu_bytes_rx;
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  /// total num pdu
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  uint32_t total_num_pdus_rx;
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  /// num of error pdus
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  uint32_t total_num_errors_rx;
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} eNB_UE_STATS;
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/*! \brief eNB template for UE context information  */
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typedef struct {
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  /// C-RNTI of UE
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  rnti_t rnti;
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  /// NDI from last scheduling
  uint8_t oldNDI[8];
  /// NDI from last UL scheduling
  uint8_t oldNDI_UL[8];
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  /// Flag to indicate UL has been scheduled at least once
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  boolean_t ul_active;
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  /// Flag to indicate UE has been configured (ACK from RRCConnectionSetup received)
  boolean_t configured;
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  // PHY interface info

  /// DCI format for DLSCH
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  uint16_t DLSCH_dci_fmt;
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  /// Current Aggregation Level for DCI
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  uint8_t DCI_aggregation_min;
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  /// size of DLSCH size in bit 
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  uint8_t DLSCH_dci_size_bits;
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  /// DCI buffer for DLSCH
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  /* rounded to 32 bits unit (actual value should be 8 due to the logic
   * of the function generate_dci0) */
  uint8_t DLSCH_DCI[8][(((MAX_DCI_SIZE_BITS)+31)>>5)*4];
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  /// Number of Allocated RBs for DL after scheduling (prior to frequency allocation)
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  uint16_t nb_rb[8]; // num_max_harq
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  /// Number of Allocated RBs for UL after scheduling (prior to frequency allocation)
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  uint16_t nb_rb_ul[8]; // num_max_harq
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  /// Number of Allocated RBs by the ulsch preprocessor
  uint8_t pre_allocated_nb_rb_ul;
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  /// index of Allocated RBs by the ulsch preprocessor
  int8_t pre_allocated_rb_table_index_ul;
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  /// total allocated RBs
  int8_t total_allocated_rbs;
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  /// pre-assigned MCS by the ulsch preprocessor
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  uint8_t pre_assigned_mcs_ul;
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  /// assigned MCS by the ulsch scheduler
  uint8_t assigned_mcs_ul;

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  /// DCI buffer for ULSCH
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  /* rounded to 32 bits unit (actual value should be 8 due to the logic
   * of the function generate_dci0) */
  uint8_t ULSCH_DCI[8][(((MAX_DCI_SIZE_BITS)+31)>>5)*4];
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  /// DL DAI
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  uint8_t DAI;
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  /// UL DAI
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  uint8_t DAI_ul[10];
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  /// UL Scheduling Request Received
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  uint8_t ul_SR;
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  ///Resource Block indication for each sub-band in MU-MIMO
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  uint8_t rballoc_subband[8][50];
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  // Logical channel info for link with RLC

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  /// Last received UE BSR info for each logical channel group id
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  uint8_t bsr_info[MAX_NUM_LCGID];
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  /// LCGID mapping
  long lcgidmap[11];

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  /// phr information
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  int8_t phr_info;
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  /// phr information
  int8_t phr_info_configured;

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  ///dl buffer info
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  uint32_t dl_buffer_info[MAX_NUM_LCID];
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  /// total downlink buffer info
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  uint32_t dl_buffer_total;
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  /// total downlink pdus
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  uint32_t dl_pdus_total;
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  /// downlink pdus for each LCID
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  uint32_t dl_pdus_in_buffer[MAX_NUM_LCID];
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  /// creation time of the downlink buffer head for each LCID
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  uint32_t dl_buffer_head_sdu_creation_time[MAX_NUM_LCID];
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  /// maximum creation time of the downlink buffer head across all LCID
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  uint32_t  dl_buffer_head_sdu_creation_time_max;
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  /// a flag indicating that the downlink head SDU is segmented  
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  uint8_t    dl_buffer_head_sdu_is_segmented[MAX_NUM_LCID];
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  /// size of remaining size to send for the downlink head SDU
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  uint32_t dl_buffer_head_sdu_remaining_size_to_send[MAX_NUM_LCID];
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  /// total uplink buffer size 
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  uint32_t ul_total_buffer;
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  /// uplink buffer creation time for each LCID
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  uint32_t ul_buffer_creation_time[MAX_NUM_LCGID];
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  /// maximum uplink buffer creation time across all the LCIDs
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  uint32_t ul_buffer_creation_time_max;
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  /// uplink buffer size per LCID
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  uint32_t ul_buffer_info[MAX_NUM_LCGID];

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  /// UE tx power
  int32_t ue_tx_power;

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  /// stores the frame where the last TPC was transmitted
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  uint32_t pusch_tpc_tx_frame;
  uint32_t pusch_tpc_tx_subframe;
  uint32_t pucch_tpc_tx_frame;
  uint32_t pucch_tpc_tx_subframe;
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#ifdef LOCALIZATION
  eNB_UE_estimated_distances distance;
#endif
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} UE_TEMPLATE;

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/*! \brief scheduling control information set through an API (not used)*/
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typedef struct {
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  ///UL transmission bandwidth in RBs
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  uint8_t ul_bandwidth[MAX_NUM_LCID];
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  ///DL transmission bandwidth in RBs
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  uint8_t dl_bandwidth[MAX_NUM_LCID];
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  //To do GBR bearer
  uint8_t min_ul_bandwidth[MAX_NUM_LCID];
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  uint8_t min_dl_bandwidth[MAX_NUM_LCID];
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  ///aggregated bit rate of non-gbr bearer per UE
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  uint64_t  ue_AggregatedMaximumBitrateDL;
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  ///aggregated bit rate of non-gbr bearer per UE
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  uint64_t  ue_AggregatedMaximumBitrateUL;
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  ///CQI scheduling interval in subframes.
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  uint16_t cqiSchedInterval;
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  ///Contention resolution timer used during random access
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  uint8_t mac_ContentionResolutionTimer;
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  uint16_t max_allowed_rbs[MAX_NUM_LCID];
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  uint8_t max_mcs[MAX_NUM_LCID];
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  uint16_t priority[MAX_NUM_LCID];
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  // resource scheduling information
  uint8_t       harq_pid[MAX_NUM_CCs];
  uint8_t       round[MAX_NUM_CCs];
  uint8_t       dl_pow_off[MAX_NUM_CCs];
  uint16_t      pre_nb_available_rbs[MAX_NUM_CCs];
  unsigned char rballoc_sub_UE[MAX_NUM_CCs][N_RBG_MAX];
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  uint16_t      ta_timer;
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  int16_t       ta_update;
  int32_t       context_active_timer;
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  int32_t       cqi_req_timer;
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  int32_t       ul_inactivity_timer;
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  int32_t       ul_failure_timer;
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  int32_t       ul_scheduled;
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  int32_t       ra_pdcch_order_sent;
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  int32_t       ul_out_of_sync;
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  int32_t       phr_received;
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} UE_sched_ctrl;
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/*! \brief eNB template for the Random access information */
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typedef struct {
  /// Flag to indicate this process is active
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  boolean_t RA_active;
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  /// Size of DCI for RA-Response (bytes)
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  uint8_t RA_dci_size_bytes1;
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  /// Size of DCI for RA-Response (bits)
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  uint8_t RA_dci_size_bits1;
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  /// Actual DCI to transmit for RA-Response
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  uint8_t RA_alloc_pdu1[(MAX_DCI_SIZE_BITS>>3)+1];
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  /// DCI format for RA-Response (should be 1A)
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  uint8_t RA_dci_fmt1;
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  /// Size of DCI for Msg4/ContRes (bytes)
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  uint8_t RA_dci_size_bytes2;
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  /// Size of DCI for Msg4/ContRes (bits)
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  uint8_t RA_dci_size_bits2;
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  /// Actual DCI to transmit for Msg4/ContRes
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  uint8_t RA_alloc_pdu2[(MAX_DCI_SIZE_BITS>>3)+1];
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  /// DCI format for Msg4/ContRes (should be 1A)
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  uint8_t RA_dci_fmt2;
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  /// Flag to indicate the eNB should generate RAR.  This is triggered by detection of PRACH
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  uint8_t generate_rar;
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  /// Subframe where preamble was received
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  uint8_t preamble_subframe;
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  /// Subframe where Msg3 is to be sent
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  uint8_t Msg3_subframe;
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  /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC.  This is triggered by first ULSCH reception at eNB for new user.
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  uint8_t generate_Msg4;
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  /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3.
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  uint8_t wait_ack_Msg4;
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  /// UE RNTI allocated during RAR
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  rnti_t rnti;
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  /// RA RNTI allocated from received PRACH
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  uint16_t RA_rnti;
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  /// Received preamble_index
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  uint8_t preamble_index;
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  /// Received UE Contention Resolution Identifier
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  uint8_t cont_res_id[6];
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  /// Timing offset indicated by PHY
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  int16_t timing_offset;
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  /// Timeout for RRC connection
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  int16_t RRC_timer;
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} RA_TEMPLATE;


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/*! \brief subband bitmap confguration (for ALU icic algo purpose), in test phase */
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typedef struct {
  uint8_t sbmap[NUMBER_OF_SUBBANDS_MAX]; //13 = number of SB MAX for 100 PRB
  uint8_t periodicity;
  uint8_t first_subframe;
  uint8_t sb_size;
  uint8_t nb_active_sb;
} SBMAP_CONF;
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/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ 
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typedef struct {
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  /// DLSCH pdu 
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  DLSCH_PDU DLSCH_pdu[MAX_NUM_CCs][2][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection parameters for UEs
  UE_TEMPLATE UE_template[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection for RA processes
  int pCC_id[NUMBER_OF_UE_MAX];
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  /// sorted downlink component carrier for the scheduler 
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  int ordered_CCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
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  /// number of downlink active component carrier 
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  int numactiveCCs[NUMBER_OF_UE_MAX];
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  /// sorted uplink component carrier for the scheduler 
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  int ordered_ULCCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
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  /// number of uplink active component carrier 
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  int numactiveULCCs[NUMBER_OF_UE_MAX];
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  /// number of downlink active component carrier 
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  uint8_t dl_CC_bitmap[NUMBER_OF_UE_MAX];
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  /// eNB to UE statistics
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  eNB_UE_STATS eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
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  /// scheduling control info
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  UE_sched_ctrl UE_sched_ctrl[NUMBER_OF_UE_MAX];

  int next[NUMBER_OF_UE_MAX];
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  int head;
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  int next_ul[NUMBER_OF_UE_MAX];
  int head_ul;
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  int avail;
  int num_UEs;
  boolean_t active[NUMBER_OF_UE_MAX];
} UE_list_t;
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/*! \brief eNB common channels */ 
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typedef struct {
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  /// Outgoing DCI for PHY generated by eNB scheduler
  DCI_PDU DCI_pdu;
  /// Outgoing BCCH pdu for PHY
  BCCH_PDU BCCH_pdu;
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  /// Outgoing BCCH DCI allocation
  uint32_t BCCH_alloc_pdu;
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  /// Outgoing CCCH pdu for PHY
  CCCH_PDU CCCH_pdu;
  RA_TEMPLATE RA_template[NB_RA_PROC_MAX];
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  /// VRB map for common channels
  uint8_t vrb_map[100];
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  /// MBSFN SubframeConfig
  struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8];
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  /// number of subframe allocation pattern available for MBSFN sync area
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  uint8_t num_sf_allocation_pattern;
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#ifdef Rel10
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  /// MBMS Flag
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  uint8_t MBMS_flag;
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  /// Outgoing MCCH pdu for PHY
  MCCH_PDU MCCH_pdu;
  /// MCCH active flag
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  uint8_t msi_active;
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  /// MCCH active flag
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  uint8_t mcch_active;
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  /// MTCH active flag
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  uint8_t mtch_active;
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  /// number of active MBSFN area
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  uint8_t num_active_mbsfn_area;
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  /// MBSFN Area Info
  struct  MBSFN_AreaInfo_r9 *mbsfn_AreaInfo[MAX_MBSFN_AREA];
  /// PMCH Config
  struct PMCH_Config_r9 *pmch_Config[MAX_PMCH_perMBSFN];
  /// MBMS session info list
  struct MBMS_SessionInfoList_r9 *mbms_SessionList[MAX_PMCH_perMBSFN];
  /// Outgoing MCH pdu for PHY
  MCH_PDU MCH_pdu;
#endif
#ifdef CBA
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  /// number of CBA groups 
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  uint8_t num_active_cba_groups;
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  /// RNTI for each CBA group 
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  uint16_t cba_rnti[NUM_MAX_CBA_GROUP];
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  /// MCS for each CBA group 
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  uint8_t group_mcs[NUM_MAX_CBA_GROUP];
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#endif
} COMMON_channels_t;
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/*! \brief top level eNB MAC structure */ 
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typedef struct {
  ///
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  uint16_t Node_id;
  /// frame counter
  frame_t frame;
  /// subframe counter
  sub_frame_t subframe;
  /// Common cell resources
  COMMON_channels_t common_channels[MAX_NUM_CCs];
  UE_list_t UE_list;
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  ///subband bitmap configuration
  SBMAP_CONF sbmap_conf;
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  /// CCE table used to build DCI scheduling information
  int CCE_table[MAX_NUM_CCs][800];
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  ///  active flag for Other lcid
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  uint8_t lcid_active[NB_RB_MAX];
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  /// eNB stats
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  eNB_STATS eNB_stats[MAX_NUM_CCs];
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  // MAC function execution peformance profiler
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  /// processing time of eNB scheduler 
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  time_stats_t eNB_scheduler;
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  /// processing time of eNB scheduler for SI 
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  time_stats_t schedule_si;
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  /// processing time of eNB scheduler for Random access
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  time_stats_t schedule_ra;
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  /// processing time of eNB ULSCH scheduler 
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  time_stats_t schedule_ulsch;
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  /// processing time of eNB DCI generation
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  time_stats_t fill_DLSCH_dci;
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  /// processing time of eNB MAC preprocessor
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  time_stats_t schedule_dlsch_preprocessor;
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  /// processing time of eNB DLSCH scheduler 
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  time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
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  /// processing time of eNB MCH scheduler 
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  time_stats_t schedule_mch;
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  /// processing time of eNB ULSCH reception
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  time_stats_t rx_ulsch_sdu; // include rlc_data_ind
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} eNB_MAC_INST;
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