pre_processor.c 54 KB
Newer Older
1
2
3
4
5
/*
 * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.
 * The OpenAirInterface Software Alliance licenses this file to You under
Cedric Roux's avatar
Cedric Roux committed
6
 * the OAI Public License, Version 1.1  (the "License"); you may not use this file
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 * except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.openairinterface.org/?page_id=698
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *-------------------------------------------------------------------------------
 * For more information about the OpenAirInterface (OAI) Software Alliance:
 *      contact@openairinterface.org
 */
21
22

/*! \file pre_processor.c
23
 * \brief eNB scheduler preprocessing fuction prior to scheduling
24
 * \author Navid Nikaein and Ankit Bhamri
nikaeinn's avatar
nikaeinn committed
25
 * \date 2013 - 2014
26
 * \email navid.nikaein@eurecom.fr
nikaeinn's avatar
nikaeinn committed
27
 * \version 1.0
28
29
30
31
 * @ingroup _mac

 */

32
33
34
#define _GNU_SOURCE
#include <stdlib.h>

35
#include "assertions.h"
36
37
38
39
40
41
42
#include "PHY/defs.h"
#include "PHY/extern.h"

#include "SCHED/defs.h"
#include "SCHED/extern.h"

#include "LAYER2/MAC/defs.h"
43
#include "LAYER2/MAC/proto.h"
44
45
#include "LAYER2/MAC/extern.h"
#include "UTIL/LOG/log.h"
46
#include "UTIL/LOG/vcd_signal_dumper.h"
47
48
49
50
51
#include "UTIL/OPT/opt.h"
#include "OCG.h"
#include "OCG_extern.h"
#include "RRC/LITE/extern.h"
#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h"
52
#include "rlc.h"
53
54


gauthier's avatar
gauthier committed
55

56
57
58
59
60
61
#define DEBUG_eNB_SCHEDULER 1
#define DEBUG_HEADER_PARSING 1
//#define DEBUG_PACKET_TRACE 1

//#define ICIC 0

62
/* this function checks that get_eNB_UE_stats returns
Cedric Roux's avatar
Cedric Roux committed
63
 * a non-NULL pointer for all the active CCs of an UE
64
 */
65
/*
66
int phy_stats_exist(module_id_t Mod_id, int rnti)
67
68
{
  int CC_id;
Cedric Roux's avatar
Cedric Roux committed
69
70
  int i;
  int UE_id          = find_UE_id(Mod_id, rnti);
71
  UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
Cedric Roux's avatar
Cedric Roux committed
72
73
74
75
76
77
78
79
80
81
82
83
  if (UE_id == -1) {
    LOG_W(MAC, "[eNB %d] UE %x not found, should be there (in phy_stats_exist)\n",
	  Mod_id, rnti);
    return 0;
  }
  if (UE_list->numactiveCCs[UE_id] == 0) {
    LOG_W(MAC, "[eNB %d] UE %x has no active CC (in phy_stats_exist)\n",
	  Mod_id, rnti);
    return 0;
  }
  for (i = 0; i < UE_list->numactiveCCs[UE_id]; i++) {
    CC_id = UE_list->ordered_CCids[i][UE_id];
84
85
    if (mac_xface->get_eNB_UE_stats(Mod_id, CC_id, rnti) == NULL)
      return 0;
86
  }
87
88
  return 1;
}
89
*/
90

91
// This function stores the downlink buffer for all the logical channels
92
93
94
void
store_dlsch_buffer(module_id_t Mod_id, frame_t frameP,
		   sub_frame_t subframeP)
95
{
Cedric Roux's avatar
Cedric Roux committed
96

97
98
99
100
101
    int UE_id, i;
    rnti_t rnti;
    mac_rlc_status_resp_t rlc_status;
    UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
    UE_TEMPLATE *UE_template;
knopp's avatar
   
knopp committed
102

103
104
105
    for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
	if (UE_list->active[UE_id] != TRUE)
	    continue;
106

107
108
	UE_template =
	    &UE_list->UE_template[UE_PCCID(Mod_id, UE_id)][UE_id];
109

110
111
112
	// clear logical channel interface variables
	UE_template->dl_buffer_total = 0;
	UE_template->dl_pdus_total = 0;
113

114
115
	rnti = UE_RNTI(Mod_id, UE_id);

116
    for (i = 0; i < MAX_NUM_LCID; i++) {    // loop over all the logical channels
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134

	    rlc_status =
		mac_rlc_status_ind(Mod_id, rnti, Mod_id, frameP, subframeP,
				   ENB_FLAG_YES, MBMS_FLAG_NO, i, 0);
	    UE_template->dl_buffer_info[i] = rlc_status.bytes_in_buffer;	//storing the dlsch buffer for each logical channel
	    UE_template->dl_pdus_in_buffer[i] = rlc_status.pdus_in_buffer;
	    UE_template->dl_buffer_head_sdu_creation_time[i] =
		rlc_status.head_sdu_creation_time;
	    UE_template->dl_buffer_head_sdu_creation_time_max =
		cmax(UE_template->dl_buffer_head_sdu_creation_time_max,
		     rlc_status.head_sdu_creation_time);
	    UE_template->dl_buffer_head_sdu_remaining_size_to_send[i] =
		rlc_status.head_sdu_remaining_size_to_send;
	    UE_template->dl_buffer_head_sdu_is_segmented[i] =
		rlc_status.head_sdu_is_segmented;
	    UE_template->dl_buffer_total += UE_template->dl_buffer_info[i];	//storing the total dlsch buffer
	    UE_template->dl_pdus_total +=
		UE_template->dl_pdus_in_buffer[i];
135

Cedric Roux's avatar
Cedric Roux committed
136
#ifdef DEBUG_eNB_SCHEDULER
137

138
139
140
141
142
143
144
145
146
147
148
149
150
	    /* note for dl_buffer_head_sdu_remaining_size_to_send[i] :
	     * 0 if head SDU has not been segmented (yet), else remaining size not already segmented and sent
	     */
	    if (UE_template->dl_buffer_info[i] > 0)
		LOG_D(MAC,
		      "[eNB %d] Frame %d Subframe %d : RLC status for UE %d in LCID%d: total of %d pdus and size %d, head sdu queuing time %d, remaining size %d, is segmeneted %d \n",
		      Mod_id, frameP, subframeP, UE_id,
		      i, UE_template->dl_pdus_in_buffer[i],
		      UE_template->dl_buffer_info[i],
		      UE_template->dl_buffer_head_sdu_creation_time[i],
		      UE_template->
		      dl_buffer_head_sdu_remaining_size_to_send[i],
		      UE_template->dl_buffer_head_sdu_is_segmented[i]);
151

Cedric Roux's avatar
Cedric Roux committed
152
#endif
153

154
	}
155

156
157
158
159
160
161
162
	//#ifdef DEBUG_eNB_SCHEDULER
	if (UE_template->dl_buffer_total > 0)
	    LOG_D(MAC,
		  "[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n",
		  Mod_id, frameP, subframeP, UE_id,
		  UE_template->dl_buffer_total,
		  UE_template->dl_pdus_total);
163

164
165
	//#endif
    }
166
167
}

168

169
// This function returns the estimated number of RBs required by each UE for downlink scheduling
170
171
172
173
174
175
176
void
assign_rbs_required(module_id_t Mod_id,
		    frame_t frameP,
		    sub_frame_t subframe,
		    uint16_t
		    nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
		    int min_rb_unit[MAX_NUM_CCs])
177
{
178

179
    uint16_t TBS = 0;
180

181
182
183
184
    int UE_id, n, i, j, CC_id, pCCid, tmp;
    UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
    eNB_UE_STATS *eNB_UE_stats, *eNB_UE_stats_i, *eNB_UE_stats_j;
    int N_RB_DL;
185

186
187
188
189
    // clear rb allocations across all CC_id
    for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
	if (UE_list->active[UE_id] != TRUE)
	    continue;
190

191
	pCCid = UE_PCCID(Mod_id, UE_id);
192

193
194
	//update CQI information across component carriers
	for (n = 0; n < UE_list->numactiveCCs[UE_id]; n++) {
195

196
197
	    CC_id = UE_list->ordered_CCids[n][UE_id];
	    eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];
knopp's avatar
knopp committed
198

199
200
	    eNB_UE_stats->dlsch_mcs1 =
		cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]];
201

202
	}
203

204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
	// provide the list of CCs sorted according to MCS
	for (i = 0; i < UE_list->numactiveCCs[UE_id]; i++) {
	    eNB_UE_stats_i =
		&UE_list->eNB_UE_stats[UE_list->
				       ordered_CCids[i][UE_id]][UE_id];
	    for (j = i + 1; j < UE_list->numactiveCCs[UE_id]; j++) {
		DevAssert(j < MAX_NUM_CCs);
		eNB_UE_stats_j =
		    &UE_list->
		    eNB_UE_stats[UE_list->ordered_CCids[j][UE_id]][UE_id];
		if (eNB_UE_stats_j->dlsch_mcs1 >
		    eNB_UE_stats_i->dlsch_mcs1) {
		    tmp = UE_list->ordered_CCids[i][UE_id];
		    UE_list->ordered_CCids[i][UE_id] =
			UE_list->ordered_CCids[j][UE_id];
		    UE_list->ordered_CCids[j][UE_id] = tmp;
		}
	    }
	}
223

224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
	if (UE_list->UE_template[pCCid][UE_id].dl_buffer_total > 0) {
	    LOG_D(MAC, "[preprocessor] assign RB for UE %d\n", UE_id);

	    for (i = 0; i < UE_list->numactiveCCs[UE_id]; i++) {
		CC_id = UE_list->ordered_CCids[i][UE_id];
		eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];

		if (eNB_UE_stats->dlsch_mcs1 == 0) {
		    nb_rbs_required[CC_id][UE_id] = 4;	// don't let the TBS get too small
		} else {
		    nb_rbs_required[CC_id][UE_id] = min_rb_unit[CC_id];
		}

		TBS =
		    get_TBS_DL(eNB_UE_stats->dlsch_mcs1,
			       nb_rbs_required[CC_id][UE_id]);

		LOG_D(MAC,
		      "[preprocessor] start RB assignement for UE %d CC_id %d dl buffer %d (RB unit %d, MCS %d, TBS %d) \n",
		      UE_id, CC_id,
		      UE_list->UE_template[pCCid][UE_id].dl_buffer_total,
		      nb_rbs_required[CC_id][UE_id],
		      eNB_UE_stats->dlsch_mcs1, TBS);

		N_RB_DL =
		    to_prb(RC.mac[Mod_id]->common_channels[CC_id].
			   mib->message.dl_Bandwidth);

		/* calculating required number of RBs for each UE */
		while (TBS <
		       UE_list->UE_template[pCCid][UE_id].
		       dl_buffer_total) {
		    nb_rbs_required[CC_id][UE_id] += min_rb_unit[CC_id];

		    if (nb_rbs_required[CC_id][UE_id] > N_RB_DL) {
			TBS =
			    get_TBS_DL(eNB_UE_stats->dlsch_mcs1, N_RB_DL);
			nb_rbs_required[CC_id][UE_id] = N_RB_DL;
			break;
		    }

		    TBS =
			get_TBS_DL(eNB_UE_stats->dlsch_mcs1,
				   nb_rbs_required[CC_id][UE_id]);
		}		// end of while

		LOG_D(MAC,
		      "[eNB %d] Frame %d: UE %d on CC %d: RB unit %d,  nb_required RB %d (TBS %d, mcs %d)\n",
		      Mod_id, frameP, UE_id, CC_id, min_rb_unit[CC_id],
		      nb_rbs_required[CC_id][UE_id], TBS,
		      eNB_UE_stats->dlsch_mcs1);
	    }
	}
knopp's avatar
   
knopp committed
277
278
    }
}
gauthier's avatar
gauthier committed
279
280


knopp's avatar
   
knopp committed
281
// This function scans all CC_ids for a particular UE to find the maximum round index of its HARQ processes
gauthier's avatar
gauthier committed
282

283
284
285
int
maxround(module_id_t Mod_id, uint16_t rnti, int frame,
	 sub_frame_t subframe, uint8_t ul_flag)
286
{
gauthier's avatar
gauthier committed
287

288
289
290
291
    uint8_t round, round_max = 0, UE_id;
    int CC_id, harq_pid;
    UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
    COMMON_channels_t *cc;
gauthier's avatar
gauthier committed
292

293
    for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
294

295
	cc = &RC.mac[Mod_id]->common_channels[CC_id];
296

297
	UE_id = find_UE_id(Mod_id, rnti);
298
299

	harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frame ,subframe);
300

301
302
303
304
	round = UE_list->UE_sched_ctrl[UE_id].round[CC_id][harq_pid];
	if (round > round_max) {
	    round_max = round;
	}
305
    }
306

307
    return round_max;
knopp's avatar
   
knopp committed
308
}
gauthier's avatar
gauthier committed
309

knopp's avatar
   
knopp committed
310
// This function scans all CC_ids for a particular UE to find the maximum DL CQI
Cedric Roux's avatar
Cedric Roux committed
311
// it returns -1 if the UE is not found in PHY layer (get_eNB_UE_stats gives NULL)
312
int maxcqi(module_id_t Mod_id, int32_t UE_id)
313
{
314
315
316
    UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
    int CC_id, n;
    int CQI = 0;
gauthier's avatar
gauthier committed
317

318
319
    for (n = 0; n < UE_list->numactiveCCs[UE_id]; n++) {
	CC_id = UE_list->ordered_CCids[n][UE_id];
320

321
322
323
	if (UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id] > CQI) {
	    CQI = UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
	}
324
    }
gauthier's avatar
gauthier committed
325

326
    return CQI;
knopp's avatar
   
knopp committed
327
}
gauthier's avatar
gauthier committed
328

329
struct sort_ue_dl_params {
330
331
332
    int Mod_idP;
    int frameP;
    int subframeP;
333
};
gauthier's avatar
gauthier committed
334

335
336
static int ue_dl_compare(const void *_a, const void *_b, void *_params)
{
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
    struct sort_ue_dl_params *params = _params;
    UE_list_t *UE_list = &RC.mac[params->Mod_idP]->UE_list;

    int UE_id1 = *(const int *) _a;
    int UE_id2 = *(const int *) _b;

    int rnti1 = UE_RNTI(params->Mod_idP, UE_id1);
    int pCC_id1 = UE_PCCID(params->Mod_idP, UE_id1);
    int round1 =
	maxround(params->Mod_idP, rnti1, params->frameP, params->subframeP,
		 1);

    int rnti2 = UE_RNTI(params->Mod_idP, UE_id2);
    int pCC_id2 = UE_PCCID(params->Mod_idP, UE_id2);
    int round2 =
	maxround(params->Mod_idP, rnti2, params->frameP, params->subframeP,
		 1);

    int cqi1 = maxcqi(params->Mod_idP, UE_id1);
    int cqi2 = maxcqi(params->Mod_idP, UE_id2);

    if (round1 > round2)
	return -1;
    if (round1 < round2)
	return 1;

    if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] +
	UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2] >
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] +
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2])
	return -1;
    if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] +
	UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2] <
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] +
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2])
	return 1;

    if (UE_list->
	UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max >
	UE_list->
	UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max)
	return -1;
    if (UE_list->
	UE_template[pCC_id1][UE_id1].dl_buffer_head_sdu_creation_time_max <
	UE_list->
	UE_template[pCC_id2][UE_id2].dl_buffer_head_sdu_creation_time_max)
	return 1;

    if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total >
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total)
	return -1;
    if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total <
	UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total)
	return 1;

    if (cqi1 > cqi2)
	return -1;
    if (cqi1 < cqi2)
	return 1;

    return 0;
398
#if 0
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
    /* The above order derives from the following.  */
    if (round2 > round1) {	// Check first if one of the UEs has an active HARQ process which needs service and swap order
	swap_UEs(UE_list, UE_id1, UE_id2, 0);
    } else if (round2 == round1) {
	// RK->NN : I guess this is for fairness in the scheduling. This doesn't make sense unless all UEs have the same configuration of logical channels.  This should be done on the sum of all information that has to be sent.  And still it wouldn't ensure fairness.  It should be based on throughput seen by each UE or maybe using the head_sdu_creation_time, i.e. swap UEs if one is waiting longer for service.
	//  for(j=0;j<MAX_NUM_LCID;j++){
	//    if (eNB_mac_inst[Mod_id][pCC_id1].UE_template[UE_id1].dl_buffer_info[j] <
	//      eNB_mac_inst[Mod_id][pCC_id2].UE_template[UE_id2].dl_buffer_info[j]){

	// first check the buffer status for SRB1 and SRB2

	if ((UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[1] +
	     UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_info[2]) <
	    (UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[1] +
	     UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_info[2])) {
	    swap_UEs(UE_list, UE_id1, UE_id2, 0);
	} else if (UE_list->UE_template[pCC_id1]
		   [UE_id1].dl_buffer_head_sdu_creation_time_max <
		   UE_list->UE_template[pCC_id2]
		   [UE_id2].dl_buffer_head_sdu_creation_time_max) {
	    swap_UEs(UE_list, UE_id1, UE_id2, 0);
	} else if (UE_list->UE_template[pCC_id1][UE_id1].dl_buffer_total <
		   UE_list->UE_template[pCC_id2][UE_id2].dl_buffer_total) {
	    swap_UEs(UE_list, UE_id1, UE_id2, 0);
	} else if (cqi1 < cqi2) {
	    swap_UEs(UE_list, UE_id1, UE_id2, 0);
	}
    }
427
428
#endif
}
gauthier's avatar
gauthier committed
429

knopp's avatar
   
knopp committed
430
// This fuction sorts the UE in order their dlsch buffer and CQI
431
void sort_UEs(module_id_t Mod_idP, int frameP, sub_frame_t subframeP)
432
{
433
434
435
436
437
    int i;
    int list[NUMBER_OF_UE_MAX];
    int list_size = 0;
    int rnti;
    struct sort_ue_dl_params params = { Mod_idP, frameP, subframeP };
438

439
    UE_list_t *UE_list = &RC.mac[Mod_idP]->UE_list;
440

441
    for (i = 0; i < NUMBER_OF_UE_MAX; i++) {
442

443
444
445
446
	if (UE_list->active[i] == FALSE)
	    continue;
	if ((rnti = UE_RNTI(Mod_idP, i)) == NOT_A_RNTI)
	    continue;
447
#if 0
448
449
	if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
	    continue;
450
#endif
451
452
453
	list[list_size] = i;
	list_size++;
    }
454

455
    qsort_r(list, list_size, sizeof(int), ue_dl_compare, &params);
456

457
458
459
460
461
462
463
464
    if (list_size) {
	for (i = 0; i < list_size - 1; i++)
	    UE_list->next[list[i]] = list[i + 1];
	UE_list->next[list[list_size - 1]] = -1;
	UE_list->head = list[0];
    } else {
	UE_list->head = -1;
    }
465
466

#if 0
gauthier's avatar
gauthier committed
467
468


469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
    int UE_id1, UE_id2;
    int pCC_id1, pCC_id2;
    int cqi1, cqi2, round1, round2;
    int i = 0, ii = 0;		//,j=0;
    rnti_t rnti1, rnti2;

    UE_list_t *UE_list = &RC.mac[Mod_idP]->UE_list;

    for (i = UE_list->head; i >= 0; i = UE_list->next[i]) {

	for (ii = UE_list->next[i]; ii >= 0; ii = UE_list->next[ii]) {

	    UE_id1 = i;
	    rnti1 = UE_RNTI(Mod_idP, UE_id1);
	    if (rnti1 == NOT_A_RNTI)
		continue;
	    if (UE_list->UE_sched_ctrl[UE_id1].ul_out_of_sync == 1)
		continue;
	    pCC_id1 = UE_PCCID(Mod_idP, UE_id1);
	    cqi1 = maxcqi(Mod_idP, UE_id1);	//
	    round1 = maxround(Mod_idP, rnti1, frameP, subframeP, 0);

	    UE_id2 = ii;
	    rnti2 = UE_RNTI(Mod_idP, UE_id2);
	    if (rnti2 == NOT_A_RNTI)
		continue;
	    if (UE_list->UE_sched_ctrl[UE_id2].ul_out_of_sync == 1)
		continue;
	    cqi2 = maxcqi(Mod_idP, UE_id2);
	    round2 = maxround(Mod_idP, rnti2, frameP, subframeP, 0);	//mac_xface->get_ue_active_harq_pid(Mod_id,rnti2,subframe,&harq_pid2,&round2,0);
	    pCC_id2 = UE_PCCID(Mod_idP, UE_id2);

	    if (round2 > round1) {	// Check first if one of the UEs has an active HARQ process which needs service and swap order
		swap_UEs(UE_list, UE_id1, UE_id2, 0);
	    } else if (round2 == round1) {
		// RK->NN : I guess this is for fairness in the scheduling. This doesn't make sense unless all UEs have the same configuration of logical channels.  This should be done on the sum of all information that has to be sent.  And still it wouldn't ensure fairness.  It should be based on throughput seen by each UE or maybe using the head_sdu_creation_time, i.e. swap UEs if one is waiting longer for service.
		//  for(j=0;j<MAX_NUM_LCID;j++){
		//    if (eNB_mac_inst[Mod_id][pCC_id1].UE_template[UE_id1].dl_buffer_info[j] <
		//      eNB_mac_inst[Mod_id][pCC_id2].UE_template[UE_id2].dl_buffer_info[j]){

		// first check the buffer status for SRB1 and SRB2

		if ((UE_list->UE_template[pCC_id1][UE_id1].
		     dl_buffer_info[1] +
		     UE_list->UE_template[pCC_id1][UE_id1].
		     dl_buffer_info[2]) <
		    (UE_list->UE_template[pCC_id2][UE_id2].
		     dl_buffer_info[1] +
		     UE_list->UE_template[pCC_id2][UE_id2].
		     dl_buffer_info[2])) {
		    swap_UEs(UE_list, UE_id1, UE_id2, 0);
		} else if (UE_list->UE_template[pCC_id1]
			   [UE_id1].dl_buffer_head_sdu_creation_time_max <
			   UE_list->UE_template[pCC_id2]
			   [UE_id2].dl_buffer_head_sdu_creation_time_max) {
		    swap_UEs(UE_list, UE_id1, UE_id2, 0);
		} else if (UE_list->UE_template[pCC_id1][UE_id1].
			   dl_buffer_total <
			   UE_list->UE_template[pCC_id2][UE_id2].
			   dl_buffer_total) {
		    swap_UEs(UE_list, UE_id1, UE_id2, 0);
		} else if (cqi1 < cqi2) {
		    swap_UEs(UE_list, UE_id1, UE_id2, 0);
		}
	    }
	}
knopp's avatar
   
knopp committed
535
    }
536
#endif
537
538
}

knopp's avatar
   
knopp committed
539
540


541
// This function assigns pre-available RBS to each UE in specified sub-bands before scheduling is done
knopp's avatar
   
knopp committed
542
void dlsch_scheduler_pre_processor (module_id_t   Mod_id,
543
544
545
                                    frame_t       frameP,
                                    sub_frame_t   subframeP,
                                    int           N_RBG[MAX_NUM_CCs],
Xu Bo's avatar
Xu Bo committed
546
                                    int           *mbsfn_flag)
547
{
knopp's avatar
   
knopp committed
548

549
  unsigned char rballoc_sub[MAX_NUM_CCs][N_RBG_MAX],harq_pid=0,round=0,total_ue_count;
Xu Bo's avatar
Xu Bo committed
550
551
552
553
  uint16_t ii;
  uint16_t                nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
  uint16_t r1=0;
//  int rrc_status           = RRC_IDLE;
knopp's avatar
   
knopp committed
554
  unsigned char MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX];
555
  int                     UE_id, i; 
Xu Bo's avatar
Xu Bo committed
556
  uint16_t                j;
knopp's avatar
   
knopp committed
557
558
  uint16_t                nb_rbs_required[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
  uint16_t                nb_rbs_required_remaining[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
Xu Bo's avatar
Xu Bo committed
559
//  uint16_t                nb_rbs_required_remaining_1[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
560
  uint16_t                average_rbs_per_user[MAX_NUM_CCs] = {0};
561
  rnti_t             rnti;
knopp's avatar
   
knopp committed
562
  int                min_rb_unit[MAX_NUM_CCs];
Xu Bo's avatar
Xu Bo committed
563
//  uint16_t r1=0;
564
  uint8_t CC_id;
565
  UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
566

knopp's avatar
knopp committed
567
  int N_RB_DL;
568
  int transmission_mode = 0;
569
570
  UE_sched_ctrl *ue_sched_ctl;
  //  int rrc_status           = RRC_IDLE;
571
  COMMON_channels_t *cc;
572
573

#ifdef TM5
574
575
576
577
578
579
580
581
    int harq_pid1 = 0;
    int round1 = 0, round2 = 0;
    int UE_id2;
    uint16_t i1, i2, i3;
    rnti_t rnti1, rnti2;
    LTE_eNB_UE_stats *eNB_UE_stats1 = NULL;
    LTE_eNB_UE_stats *eNB_UE_stats2 = NULL;
    UE_sched_ctrl *ue_sched_ctl1, *ue_sched_ctl2;
582
#endif
583
584

  for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
knopp's avatar
   
knopp committed
585

586
587
	if (mbsfn_flag[CC_id] > 0)	// If this CC is allocated for MBSFN skip it here
	    continue;
588
589


knopp's avatar
   
knopp committed
590

591
	min_rb_unit[CC_id] = get_min_rb_unit(Mod_id, CC_id);
592

593
594
595
	for (i = 0; i < NUMBER_OF_UE_MAX; i++) {
	    if (UE_list->active[i] != TRUE)
		continue;
596

597
598
	    UE_id = i;
	    // Initialize scheduling information for all active UEs
599

600
601


602
603
604
605
606
607
608
609
610
611
	    dlsch_scheduler_pre_processor_reset(Mod_id,
						UE_id,
						CC_id,
						frameP,
						subframeP,
						N_RBG[CC_id],
						nb_rbs_required,
						nb_rbs_required_remaining,
						rballoc_sub,
						MIMO_mode_indicator);
knopp's avatar
   
knopp committed
612

613
614
	}
    }
knopp's avatar
   
knopp committed
615

616
617
    // Store the DLSCH buffer for each logical channel
    store_dlsch_buffer(Mod_id, frameP, subframeP);
knopp's avatar
   
knopp committed
618
619


620

621
622
623
    // Calculate the number of RBs required by each UE on the basis of logical channel's buffer
    assign_rbs_required(Mod_id, frameP, subframeP, nb_rbs_required,
			min_rb_unit);
knopp's avatar
   
knopp committed
624

625
  // Sorts the user on the basis of dlsch logical channel buffer and CQI
knopp's avatar
   
knopp committed
626
627
  sort_UEs (Mod_id,frameP,subframeP);

628
  total_ue_count =0;
Xu Bo's avatar
Xu Bo committed
629
630
631

 //total_ue_count =0;

632
633
634
    // loop over all active UEs
    for (i = UE_list->head; i >= 0; i = UE_list->next[i]) {
	rnti = UE_RNTI(Mod_id, i);
635

636
637
	if (rnti == NOT_A_RNTI)
	    continue;
638
#if 0
639
640
	if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
	    continue;
641
#endif
642
	UE_id = i;
643

644
645
646
647
	for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) {
	    CC_id = UE_list->ordered_CCids[ii][UE_id];
	    ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
	    cc = &RC.mac[Mod_id]->common_channels[ii];
648
	    harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config,frameP ,subframeP);
649
	    round = ue_sched_ctl->round[CC_id][harq_pid];
650

651
	    average_rbs_per_user[CC_id] = 0;
652

653

654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
	    if (round != 8) {
		nb_rbs_required[CC_id][UE_id] =
		    UE_list->UE_template[CC_id][UE_id].nb_rb[harq_pid];
	    }
	    //nb_rbs_required_remaining[UE_id] = nb_rbs_required[UE_id];
	    if (nb_rbs_required[CC_id][UE_id] > 0) {
		total_ue_count = total_ue_count + 1;
	    }
	    // hypothetical assignment
	    /*
	     * If schedule is enabled and if the priority of the UEs is modified
	     * The average rbs per logical channel per user will depend on the level of
	     * priority. Concerning the hypothetical assignement, we should assign more
	     * rbs to prioritized users. Maybe, we can do a mapping between the
	     * average rbs per user and the level of priority or multiply the average rbs
	     * per user by a coefficient which represents the degree of priority.
	     */

	    N_RB_DL =
		to_prb(RC.mac[Mod_id]->common_channels[CC_id].mib->
		       message.dl_Bandwidth);

	    if (total_ue_count == 0) {
		average_rbs_per_user[CC_id] = 0;
	    } else if ((min_rb_unit[CC_id] * total_ue_count) <= (N_RB_DL)) {
		average_rbs_per_user[CC_id] =
		    (uint16_t) floor(N_RB_DL / total_ue_count);
	    } else {
		average_rbs_per_user[CC_id] = min_rb_unit[CC_id];	// consider the total number of use that can be scheduled UE
	    }
	}
knopp's avatar
   
knopp committed
685
    }
686

687
688
689
690
    // note: nb_rbs_required is assigned according to total_buffer_dl
    // extend nb_rbs_required to capture per LCID RB required
    for (i = UE_list->head; i >= 0; i = UE_list->next[i]) {
	rnti = UE_RNTI(Mod_id, i);
691

692
693
	if (rnti == NOT_A_RNTI)
	    continue;
694
#if 0
695
696
	if (UE_list->UE_sched_ctrl[i].ul_out_of_sync == 1)
	    continue;
697
#endif
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
	for (ii = 0; ii < UE_num_active_CC(UE_list, i); ii++) {
	    CC_id = UE_list->ordered_CCids[ii][i];
	    ue_sched_ctl = &UE_list->UE_sched_ctrl[i];
	    round = ue_sched_ctl->round[CC_id][harq_pid];

	    // control channel or retransmission
	    /* TODO: do we have to check for retransmission? */
	    if (mac_eNB_get_rrc_status(Mod_id, rnti) < RRC_RECONFIGURED
		|| round > 0) {
		nb_rbs_required_remaining_1[CC_id][i] =
		    nb_rbs_required[CC_id][i];
	    } else {
		nb_rbs_required_remaining_1[CC_id][i] =
		    cmin(average_rbs_per_user[CC_id],
			 nb_rbs_required[CC_id][i]);
713

714
715
	    }
	}
knopp's avatar
   
knopp committed
716
    }
717

718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
    //Allocation to UEs is done in 2 rounds,
    // 1st stage: average number of RBs allocated to each UE
    // 2nd stage: remaining RBs are allocated to high priority UEs
    for (r1 = 0; r1 < 2; r1++) {

	for (i = UE_list->head; i >= 0; i = UE_list->next[i]) {
	    for (ii = 0; ii < UE_num_active_CC(UE_list, i); ii++) {
		CC_id = UE_list->ordered_CCids[ii][i];

		if (r1 == 0) {
		    nb_rbs_required_remaining[CC_id][i] =
			nb_rbs_required_remaining_1[CC_id][i];
		} else {	// rb required based only on the buffer - rb allloctaed in the 1st round + extra reaming rb form the 1st round
		    nb_rbs_required_remaining[CC_id][i] =
			nb_rbs_required[CC_id][i] -
			nb_rbs_required_remaining_1[CC_id][i] +
			nb_rbs_required_remaining[CC_id][i];
		    if (nb_rbs_required_remaining[CC_id][i] < 0)
			abort();
		}

		if (nb_rbs_required[CC_id][i] > 0)
		    LOG_D(MAC,
			  "round %d : nb_rbs_required_remaining[%d][%d]= %d (remaining_1 %d, required %d,  pre_nb_available_rbs %d, N_RBG %d, rb_unit %d)\n",
			  r1, CC_id, i,
			  nb_rbs_required_remaining[CC_id][i],
			  nb_rbs_required_remaining_1[CC_id][i],
			  nb_rbs_required[CC_id][i],
			  UE_list->UE_sched_ctrl[i].
			  pre_nb_available_rbs[CC_id], N_RBG[CC_id],
			  min_rb_unit[CC_id]);
749

750
751
	    }
	}
752

753
754
755
756
757
758
759
760
761
762
763
764
765
766
	if (total_ue_count > 0) {
	    for (i = UE_list->head; i >= 0; i = UE_list->next[i]) {
		UE_id = i;

		for (ii = 0; ii < UE_num_active_CC(UE_list, UE_id); ii++) {
		    CC_id = UE_list->ordered_CCids[ii][UE_id];
		    ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
		    round = ue_sched_ctl->round[CC_id][harq_pid];

		    rnti = UE_RNTI(Mod_id, UE_id);

		    // LOG_D(MAC,"UE %d rnti 0x\n", UE_id, rnti );
		    if (rnti == NOT_A_RNTI)
			continue;
767
#if 0
768
769
		    if (UE_list->UE_sched_ctrl[UE_id].ul_out_of_sync == 1)
			continue;
770
#endif
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
		    transmission_mode = get_tmode(Mod_id, CC_id, UE_id);
		    //          mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti,frameP,subframeP,&harq_pid,&round,0);
		    //rrc_status = mac_eNB_get_rrc_status(Mod_id,rnti);
		    /* 1st allocate for the retx */

		    // retransmission in data channels
		    // control channel in the 1st transmission
		    // data channel for all TM
		    LOG_T(MAC,
			  "calling dlsch_scheduler_pre_processor_allocate .. \n ");
		    dlsch_scheduler_pre_processor_allocate(Mod_id, UE_id,
							   CC_id,
							   N_RBG[CC_id],
							   transmission_mode,
							   min_rb_unit
							   [CC_id],
							   to_prb(RC.mac
								  [Mod_id]->common_channels
								  [CC_id].mib->message.dl_Bandwidth),
							   nb_rbs_required,
							   nb_rbs_required_remaining,
							   rballoc_sub,
							   MIMO_mode_indicator);
794

795
#ifdef TM5
796

797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
		    // data chanel TM5: to be revisted
		    if ((round == 0) &&
			(transmission_mode == 5) &&
			(ue_sched_ctl->dl_pow_off[CC_id] != 1)) {

			for (j = 0; j < N_RBG[CC_id]; j += 2) {

			    if ((((j == (N_RBG[CC_id] - 1))
				  && (rballoc_sub[CC_id][j] == 0)
				  && (ue_sched_ctl->
				      rballoc_sub_UE[CC_id][j] == 0))
				 || ((j < (N_RBG[CC_id] - 1))
				     && (rballoc_sub[CC_id][j + 1] == 0)
				     &&
				     (ue_sched_ctl->rballoc_sub_UE
				      [CC_id][j + 1] == 0)))
				&& (nb_rbs_required_remaining[CC_id][UE_id]
				    > 0)) {

				for (ii = UE_list->next[i + 1]; ii >= 0;
				     ii = UE_list->next[ii]) {

				    UE_id2 = ii;
				    rnti2 = UE_RNTI(Mod_id, UE_id2);
				    ue_sched_ctl2 =
					&UE_list->UE_sched_ctrl[UE_id2];
				    round2 = ue_sched_ctl2->round[CC_id];
				    if (rnti2 == NOT_A_RNTI)
					continue;
826
#if 0				    if (UE_list->
827
828
829
					UE_sched_ctrl
					[UE_id2].ul_out_of_sync == 1)
					continue;
830
#endif
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
				    eNB_UE_stats2 =
					UE_list->
					eNB_UE_stats[CC_id][UE_id2];
				    //mac_xface->get_ue_active_harq_pid(Mod_id,CC_id,rnti2,frameP,subframeP,&harq_pid2,&round2,0);

				    if ((mac_eNB_get_rrc_status
					 (Mod_id,
					  rnti2) >= RRC_RECONFIGURED)
					&& (round2 == 0)
					&&
					(get_tmode(Mod_id, CC_id, UE_id2)
					 == 5)
					&& (ue_sched_ctl->
					    dl_pow_off[CC_id] != 1)) {

					if ((((j == (N_RBG[CC_id] - 1))
					      &&
					      (ue_sched_ctl->rballoc_sub_UE
					       [CC_id][j] == 0))
					     || ((j < (N_RBG[CC_id] - 1))
						 &&
						 (ue_sched_ctl->
						  rballoc_sub_UE[CC_id][j +
									1]
						  == 0)))
					    &&
					    (nb_rbs_required_remaining
					     [CC_id]
					     [UE_id2] > 0)) {

					    if ((((eNB_UE_stats2->
						   DL_pmi_single ^
						   eNB_UE_stats1->
						   DL_pmi_single)
						  << (14 - j)) & 0xc000) == 0x4000) {	//MU-MIMO only for 25 RBs configuration

						rballoc_sub[CC_id][j] = 1;
						ue_sched_ctl->
						    rballoc_sub_UE[CC_id]
						    [j] = 1;
						ue_sched_ctl2->
						    rballoc_sub_UE[CC_id]
						    [j] = 1;
						MIMO_mode_indicator[CC_id]
						    [j] = 0;

						if (j < N_RBG[CC_id] - 1) {
						    rballoc_sub[CC_id][j +
								       1] =
							1;
						    ue_sched_ctl->
							rballoc_sub_UE
							[CC_id][j + 1] = 1;
						    ue_sched_ctl2->rballoc_sub_UE
							[CC_id][j + 1] = 1;
						    MIMO_mode_indicator
							[CC_id][j + 1]
							= 0;
						}

						ue_sched_ctl->
						    dl_pow_off[CC_id]
						    = 0;
						ue_sched_ctl2->
						    dl_pow_off[CC_id]
						    = 0;


						if ((j == N_RBG[CC_id] - 1)
						    && ((N_RB_DL == 25)
							|| (N_RB_DL ==
							    50))) {

						    nb_rbs_required_remaining
							[CC_id][UE_id] =
							nb_rbs_required_remaining
							[CC_id][UE_id] -
							min_rb_unit[CC_id]
							+ 1;
						    ue_sched_ctl->pre_nb_available_rbs
							[CC_id] =
							ue_sched_ctl->pre_nb_available_rbs
							[CC_id] +
							min_rb_unit[CC_id]
							- 1;
						    nb_rbs_required_remaining
							[CC_id][UE_id2] =
							nb_rbs_required_remaining
							[CC_id][UE_id2] -
							min_rb_unit[CC_id]
							+ 1;
						    ue_sched_ctl2->pre_nb_available_rbs
							[CC_id] =
							ue_sched_ctl2->pre_nb_available_rbs
							[CC_id] +
							min_rb_unit[CC_id]
							- 1;
						} else {

						    nb_rbs_required_remaining
							[CC_id][UE_id] =
							nb_rbs_required_remaining
							[CC_id][UE_id] - 4;
						    ue_sched_ctl->pre_nb_available_rbs
							[CC_id] =
							ue_sched_ctl->pre_nb_available_rbs
							[CC_id] + 4;
						    nb_rbs_required_remaining
							[CC_id][UE_id2] =
							nb_rbs_required_remaining
							[CC_id][UE_id2] -
							4;
						    ue_sched_ctl2->pre_nb_available_rbs
							[CC_id] =
							ue_sched_ctl2->pre_nb_available_rbs
							[CC_id] + 4;
						}

						break;
					    }
					}
				    }
				}
			    }
			}
		    }
957
#endif
958
959
960
961
		}
	    }
	}			// total_ue_count
    }				// end of for for r1 and r2
962
963
#ifdef TM5

964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
    // This has to be revisited!!!!
    for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
	i1 = 0;
	i2 = 0;
	i3 = 0;

	for (j = 0; j < N_RBG[CC_id]; j++) {
	    if (MIMO_mode_indicator[CC_id][j] == 2) {
		i1 = i1 + 1;
	    } else if (MIMO_mode_indicator[CC_id][j] == 1) {
		i2 = i2 + 1;
	    } else if (MIMO_mode_indicator[CC_id][j] == 0) {
		i3 = i3 + 1;
	    }
	}
979

980
981
982
983
984
	if ((i1 < N_RBG[CC_id]) && (i2 > 0) && (i3 == 0)) {
	    PHY_vars_eNB_g[Mod_id][CC_id]->check_for_SUMIMO_transmissions =
		PHY_vars_eNB_g[Mod_id][CC_id]->
		check_for_SUMIMO_transmissions + 1;
	}
985

986
987
988
989
990
	if (i3 == N_RBG[CC_id] && i1 == 0 && i2 == 0) {
	    PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions =
		PHY_vars_eNB_g[Mod_id][CC_id]->FULL_MUMIMO_transmissions +
		1;
	}
991

Xu Bo's avatar
Xu Bo committed
992
        if((i1 < N_RBG[CC_id]) && (i3 > 0)) {
993
994
995
		PHY_vars_eNB_g[Mod_id][CC_id]->
		check_for_MUMIMO_transmissions + 1;
	}
996

997
998
999
	PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions =
	    PHY_vars_eNB_g[Mod_id][CC_id]->check_for_total_transmissions +
	    1;
1000

knopp's avatar
   
knopp committed
1001
    }
1002

1003
1004
1005
#endif

  for(i=UE_list->head; i>=0; i=UE_list->next[i]) {
1006
    UE_id = i;
1007
    ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
1008
1009

    for (ii=0; ii<UE_num_active_CC(UE_list,UE_id); ii++) {
knopp's avatar
   
knopp committed
1010
      CC_id = UE_list->ordered_CCids[ii][UE_id];
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
	    //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].dl_pow_off = dl_pow_off[UE_id];

	    if (ue_sched_ctl->pre_nb_available_rbs[CC_id] > 0) {
		LOG_D(MAC,
		      "******************DL Scheduling Information for UE%d ************************\n",
		      UE_id);
		LOG_D(MAC, "dl power offset UE%d = %d \n", UE_id,
		      ue_sched_ctl->dl_pow_off[CC_id]);
		LOG_D(MAC,
		      "***********RB Alloc for every subband for UE%d ***********\n",
		      UE_id);

		for (j = 0; j < N_RBG[CC_id]; j++) {
		    //PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].rballoc_sub[i] = rballoc_sub_UE[CC_id][UE_id][i];
		    LOG_D(MAC, "RB Alloc for UE%d and Subband%d = %d\n",
			  UE_id, j,
			  ue_sched_ctl->rballoc_sub_UE[CC_id][j]);
		}

		//PHY_vars_eNB_g[Mod_id]->mu_mimo_mode[UE_id].pre_nb_available_rbs = pre_nb_available_rbs[CC_id][UE_id];
		LOG_D(MAC, "Total RBs allocated for UE%d = %d\n", UE_id,
		      ue_sched_ctl->pre_nb_available_rbs[CC_id]);
	    }
	}
knopp's avatar
   
knopp committed
1035
    }
1036
1037
}

Cedric Roux's avatar
Cedric Roux committed
1038
#define SF0_LIMIT 1
1039

1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
void
dlsch_scheduler_pre_processor_reset(int module_idP,
				    int UE_id,
				    uint8_t CC_id,
				    int frameP,
				    int subframeP,
				    int N_RBG,
				    uint16_t nb_rbs_required[MAX_NUM_CCs]
				    [NUMBER_OF_UE_MAX],
				    uint16_t
				    nb_rbs_required_remaining
				    [MAX_NUM_CCs][NUMBER_OF_UE_MAX],
				    unsigned char
				    rballoc_sub[MAX_NUM_CCs]
				    [N_RBG_MAX], unsigned char
				    MIMO_mode_indicator[MAX_NUM_CCs]
				    [N_RBG_MAX])
1057
{
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
    int i, j;
    UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
    UE_sched_ctrl *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
    rnti_t rnti = UE_RNTI(module_idP, UE_id);

    uint8_t *vrb_map = RC.mac[module_idP]->common_channels[CC_id].vrb_map;
    int N_RB_DL =
	to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->
	       message.dl_Bandwidth);
    int RBGsize = N_RB_DL / N_RBG, RBGsize_last;
Cedric Roux's avatar
Cedric Roux committed
1068
#ifdef SF0_LIMIT
1069
    int sf0_upper = -1, sf0_lower = -1;
1070
#endif
1071

Xu Bo's avatar
Xu Bo committed
1072
    LOG_D(MAC,"Running preprocessor for UE %d (%x)\n",UE_id,rnti);
1073
    // initialize harq_pid and round
1074

1075
1076
    if (ue_sched_ctl->ta_timer)
	ue_sched_ctl->ta_timer--;
1077

1078
1079
    /*
       eNB_UE_stats *eNB_UE_stats;
1080

1081
1082
       if (eNB_UE_stats == NULL)
       return;
1083
1084


1085
1086
1087
1088
1089
       mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,
       frameP,subframeP,
       &ue_sched_ctl->harq_pid[CC_id],
       &ue_sched_ctl->round[CC_id],
       openair_harq_DL);
1090

1091

1092
       if (ue_sched_ctl->ta_timer == 0) {
1093

1094
       // WE SHOULD PROTECT the eNB_UE_stats with a mutex here ...
1095

1096
1097
1098
1099
1100
       ue_sched_ctl->ta_timer = 20;  // wait 20 subframes before taking TA measurement from PHY
       switch (N_RB_DL) {
       case 6:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update;
       break;
1101

1102
1103
1104
       case 15:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/2;
       break;
Cedric Roux's avatar
Cedric Roux committed
1105

1106
1107
1108
       case 25:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/4;
       break;
1109

1110
1111
1112
       case 50:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/8;
       break;
1113

1114
1115
1116
       case 75:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/12;
       break;
1117

1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
       case 100:
       ue_sched_ctl->ta_update = eNB_UE_stats->timing_advance_update/16;
       break;
       }
       // clear the update in case PHY does not have a new measurement after timer expiry
       eNB_UE_stats->timing_advance_update =  0;
       }
       else {
       ue_sched_ctl->ta_timer--;
       ue_sched_ctl->ta_update =0; // don't trigger a timing advance command
       }
1129

1130

1131
1132
1133
1134
       if (UE_id==0) {
       VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME(VCD_SIGNAL_DUMPER_VARIABLES_UE0_TIMING_ADVANCE,ue_sched_ctl->ta_update);
       }
     */
1135

1136
1137
1138
1139
    nb_rbs_required[CC_id][UE_id] = 0;
    ue_sched_ctl->pre_nb_available_rbs[CC_id] = 0;
    ue_sched_ctl->dl_pow_off[CC_id] = 2;
    nb_rbs_required_remaining[CC_id][UE_id] = 0;
1140

knopp's avatar
knopp committed
1141
    switch (N_RB_DL) {
1142
    case 6:
1143
1144
1145
	RBGsize = 1;
	RBGsize_last = 1;
	break;
1146
    case 15:
1147
1148
1149
	RBGsize = 2;
	RBGsize_last = 1;
	break;
1150
    case 25:
1151
1152
1153
	RBGsize = 2;
	RBGsize_last = 1;
	break;
1154
    case 50:
1155
1156
1157
	RBGsize = 3;
	RBGsize_last = 2;
	break;
1158
    case 75:
1159
1160
1161
	RBGsize = 4;
	RBGsize_last = 3;
	break;
1162
    case 100:
1163
1164
1165
1166
1167
	RBGsize = 4;
	RBGsize_last = 4;
	break;
    default:
	AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL);
1168
    }
1169

Cedric Roux's avatar
Cedric Roux committed
1170
#ifdef SF0_LIMIT
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
    switch (N_RBG) {
    case 6:
	sf0_lower = 0;
	sf0_upper = 5;
	break;
    case 8:
	sf0_lower = 2;
	sf0_upper = 5;
	break;
    case 13:
	sf0_lower = 4;
	sf0_upper = 7;
	break;
    case 17:
	sf0_lower = 7;
	sf0_upper = 9;
	break;
    case 25:
	sf0_lower = 11;
	sf0_upper = 13;
	break;
    default:
	AssertFatal(1 == 0, "unsupported RBs (%d)\n", N_RB_DL);
    }
1195
#endif
1196
1197
1198
    // Initialize Subbands according to VRB map
    for (i = 0; i < N_RBG; i++) {
	int rb_size = i == N_RBG - 1 ? RBGsize_last : RBGsize;
Cedric Roux's avatar
Cedric Roux committed
1199

1200
1201
	ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
	rballoc_sub[CC_id][i] = 0;
Cedric Roux's avatar
Cedric Roux committed
1202
#ifdef SF0_LIMIT
1203
1204
1205
1206
1207
1208
1209
	// for avoiding 6+ PRBs around DC in subframe 0 (avoid excessive errors)
	/* TODO: make it proper - allocate those RBs, do not "protect" them, but
	 * compute number of available REs and limit MCS according to the
	 * TBS table 36.213 7.1.7.2.1-1 (can be done after pre-processor)
	 */
	if (subframeP == 0 && i >= sf0_lower && i <= sf0_upper)
	    rballoc_sub[CC_id][i] = 1;
1210
#endif
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
	// for SI-RNTI,RA-RNTI and P-RNTI allocations
	for (j = 0; j < rb_size; j++) {
	    if (vrb_map[j + (i * RBGsize)] != 0) {
		rballoc_sub[CC_id][i] = 1;
		LOG_D(MAC, "Frame %d, subframe %d : vrb %d allocated\n",
		      frameP, subframeP, j + (i * RBGsize));
		break;
	    }
	}
	LOG_D(MAC, "Frame %d Subframe %d CC_id %d RBG %i : rb_alloc %d\n",
	      frameP, subframeP, CC_id, i, rballoc_sub[CC_id][i]);
	MIMO_mode_indicator[CC_id][i] = 2;
1223
    }
1224
1225
1226
}


1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
void
dlsch_scheduler_pre_processor_allocate(module_id_t Mod_id,
				       int UE_id,
				       uint8_t CC_id,
				       int N_RBG,
				       int transmission_mode,
				       int min_rb_unit,
				       uint8_t N_RB_DL,
				       uint16_t
				       nb_rbs_required[MAX_NUM_CCs]
				       [NUMBER_OF_UE_MAX],
				       uint16_t
				       nb_rbs_required_remaining
				       [MAX_NUM_CCs]
				       [NUMBER_OF_UE_MAX], unsigned char
				       rballoc_sub[MAX_NUM_CCs]
				       [N_RBG_MAX], unsigned char
				       MIMO_mode_indicator
				       [MAX_NUM_CCs][N_RBG_MAX])
1246
1247
{

1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
    int i;
    UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
    UE_sched_ctrl *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];

    for (i = 0; i < N_RBG; i++) {

	if ((rballoc_sub[CC_id][i] == 0) &&
	    (ue_sched_ctl->rballoc_sub_UE[CC_id][i] == 0) &&
	    (nb_rbs_required_remaining[CC_id][UE_id] > 0) &&
	    (ue_sched_ctl->pre_nb_available_rbs[CC_id] <
	     nb_rbs_required[CC_id][UE_id])) {

	    // if this UE is not scheduled for TM5
	    if (ue_sched_ctl->dl_pow_off[CC_id] != 0) {

		if ((i == N_RBG - 1)
		    && ((N_RB_DL == 25) || (N_RB_DL == 50))) {
		    if (nb_rbs_required_remaining[CC_id][UE_id] >=
			min_rb_unit - 1) {
			rballoc_sub[CC_id][i] = 1;
			ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1;
			MIMO_mode_indicator[CC_id][i] = 1;
			if (transmission_mode == 5) {
			    ue_sched_ctl->dl_pow_off[CC_id] = 1;
			}
			nb_rbs_required_remaining[CC_id][UE_id] =
			    nb_rbs_required_remaining[CC_id][UE_id] -
			    min_rb_unit + 1;
			ue_sched_ctl->pre_nb_available_rbs[CC_id] =
			    ue_sched_ctl->pre_nb_available_rbs[CC_id] +
			    min_rb_unit - 1;
		    }
		} else {
		    if (nb_rbs_required_remaining[CC_id][UE_id] >=
			min_rb_unit) {
			rballoc_sub[CC_id][i] = 1;
			ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 1;
			MIMO_mode_indicator[CC_id][i] = 1;
			if (transmission_mode == 5) {
			    ue_sched_ctl->dl_pow_off[CC_id] = 1;
			}
			nb_rbs_required_remaining[CC_id][UE_id] =
			    nb_rbs_required_remaining[CC_id][UE_id] -
			    min_rb_unit;
			ue_sched_ctl->pre_nb_available_rbs[CC_id] =
			    ue_sched_ctl->pre_nb_available_rbs[CC_id] +
			    min_rb_unit;
		    }
		}
	    }			// dl_pow_off[CC_id][UE_id] ! = 0
1298
	}
1299
1300
1301
1302
    }
}


1303
/// ULSCH PRE_PROCESSOR
1304

1305
void ulsch_scheduler_pre_processor(module_id_t module_idP,
1306
1307
                                   int frameP,
                                   sub_frame_t subframeP,
jftt_wangshanshan's avatar
jftt_wangshanshan committed
1308
                                   unsigned char sched_subframeP,
1309
                                   uint16_t *first_rb)
1310
{
1311

1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
    int16_t i;
    uint16_t UE_id, n, r;
    uint8_t CC_id, harq_pid;
    uint16_t nb_allocated_rbs[MAX_NUM_CCs][NUMBER_OF_UE_MAX],
	total_allocated_rbs[MAX_NUM_CCs],
	average_rbs_per_user[MAX_NUM_CCs];
    int16_t total_remaining_rbs[MAX_NUM_CCs];
    uint16_t max_num_ue_to_be_scheduled = 0;
    uint16_t total_ue_count = 0;
    rnti_t rnti = -1;
    UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
    UE_TEMPLATE *UE_template = 0;
    int N_RB_DL;
    int N_RB_UL;
    LOG_D(MAC, "In ulsch_preprocessor: assign max mcs min rb\n");
    // maximize MCS and then allocate required RB according to the buffer occupancy with the limit of max available UL RB
    assign_max_mcs_min_rb(module_idP, frameP, subframeP, first_rb);

    LOG_D(MAC, "In ulsch_preprocessor: sort ue \n");
    // sort ues
    sort_ue_ul(module_idP, frameP, subframeP);


    // we need to distribute RBs among UEs
    // step1:  reset the vars
    for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
	N_RB_DL =
	    to_prb(RC.mac[module_idP]->common_channels[CC_id].mib->
		   message.dl_Bandwidth);
	N_RB_UL =
	    to_prb(RC.mac[module_idP]->common_channels[CC_id].
		   ul_Bandwidth);
	total_allocated_rbs[CC_id] = 0;
	total_remaining_rbs[CC_id] = 0;
	average_rbs_per_user[CC_id] = 0;

	for (i = UE_list->head_ul; i >= 0; i = UE_list->next_ul[i]) {
	    nb_allocated_rbs[CC_id][i] = 0;
	}
1351
1352
    }

1353
1354
1355
1356
    LOG_D(MAC, "In ulsch_preprocessor: step2 \n");
    // step 2: calculate the average rb per UE
    total_ue_count = 0;
    max_num_ue_to_be_scheduled = 0;
1357

1358
    for (i = UE_list->head_ul; i >= 0; i = UE_list->next_ul[i]) {
1359

1360
	rnti = UE_RNTI(module_idP, i);
1361