dci_tools.c 260 KB
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/*******************************************************************************
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    OpenAirInterface 
    Copyright(c) 1999 - 2014 Eurecom
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    OpenAirInterface is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
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    OpenAirInterface is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
    along with OpenAirInterface.The full GNU General Public License is 
   included in this distribution in the file called "COPYING". If not, 
   see <http://www.gnu.org/licenses/>.
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  Contact Information
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  OpenAirInterface Admin: openair_admin@eurecom.fr
  OpenAirInterface Tech : openair_tech@eurecom.fr
  OpenAirInterface Dev  : openair4g-devel@eurecom.fr
  
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  Address      : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE
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 *******************************************************************************/
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/*! \file PHY/LTE_TRANSPORT/dci_tools.c
 * \brief PHY Support routines (eNB/UE) for filling PDSCH/PUSCH/DLSCH/ULSCH data structures based on DCI PDUs generated by eNB MAC scheduler. 
 * \author R. Knopp
 * \date 2011
 * \version 0.1
 * \company Eurecom
 * \email: knopp@eurecom.fr
 * \note
 * \warning
 */
#include "PHY/defs.h"
#include "PHY/extern.h"
#include "SCHED/defs.h"
#include "MAC_INTERFACE/defs.h"
#include "MAC_INTERFACE/extern.h"
#ifdef DEBUG_DCI_TOOLS
#include "PHY/vars.h"
#endif
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#include "assertions.h"
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//#define DEBUG_DCI

uint32_t  localRIV2alloc_LUT6[32];
uint32_t  distRIV2alloc_LUT6[32];
uint16_t RIV2nb_rb_LUT6[32];
uint16_t RIV2first_rb_LUT6[32];
uint16_t RIV_max6=0;

uint32_t  localRIV2alloc_LUT25[512];
uint32_t  distRIV2alloc_LUT25[512];
uint16_t RIV2nb_rb_LUT25[512];
uint16_t RIV2first_rb_LUT25[512];
uint16_t RIV_max25=0;


uint32_t  localRIV2alloc_LUT50_0[1600];
uint32_t  distRIV2alloc_LUT50_0[1600];
uint32_t  localRIV2alloc_LUT50_1[1600];
uint32_t  distRIV2alloc_LUT50_1[1600];
uint16_t RIV2nb_rb_LUT50[1600];
uint16_t RIV2first_rb_LUT50[1600];
uint16_t RIV_max50=0;

uint32_t  localRIV2alloc_LUT100_0[6000];
uint32_t  distRIV2alloc_LUT100_0[6000];
uint32_t  localRIV2alloc_LUT100_1[6000];
uint32_t  distRIV2alloc_LUT100_1[6000];
uint32_t  localRIV2alloc_LUT100_2[6000];
uint32_t  distRIV2alloc_LUT100_2[6000];
uint32_t  localRIV2alloc_LUT100_3[6000];
uint32_t  distRIV2alloc_LUT100_3[6000];
uint16_t RIV2nb_rb_LUT100[6000];
uint16_t RIV2first_rb_LUT100[6000];
uint16_t RIV_max100=0;


extern uint32_t current_dlsch_cqi;

// Table 8.6.3-3 36.213
uint16_t beta_cqi[16] = {0,   //reserved
			 0,   //reserved
			 9,   //1.125
			 10,  //1.250
			 11,  //1.375
			 13,  //1.625
			 14,  //1.750
			 16,  //2.000
			 18,  //2.250
			 20,  //2.500
			 23,  //2.875
			 25,  //3.125
			 28,  //3.500
			 32,  //4.000
			 40,  //5.000
			 50}; //6.250

// Table 8.6.3-2 36.213
uint16_t beta_ri[16] = {10,   //1.250
			13,   //1.625
			16,   //2.000
			20,   //2.500
			25,   //3.125
			32,   //4.000
			40,   //5.000
			50,   //6.250
			64,   //8.000
			80,   //10.000
			101,  //12.625
			127,  //15.875
			160,  //20.000
			0,    //reserved 
			0,    //reserved
			0};   //reserved

// Table 8.6.3-2 36.213
uint16_t beta_ack[16] = {16,  //2.000
			 20,  //2.500
			 25,  //3.125
			 32,  //4.000
			 40,  //5.000
			 50,  //6.250
			 64,  //8.000
			 80,  //10.000
			 101, //12.625
			 127, //15.875
			 160, //20.000
			 248, //31.000
			 400, //50.000
			 640, //80.000
			 808};//126.00

int8_t delta_PUSCH_abs[4] = {-4,-1,1,4};
int8_t delta_PUSCH_acc[4] = {-1,0,1,3};

int8_t *delta_PUCCH_lut = delta_PUSCH_acc;
		    
void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t *rb_alloc2) {

  uint32_t i,shift,subset;
  rb_alloc2[0] = 0; rb_alloc2[1] = 0; rb_alloc2[2] = 0; rb_alloc2[3] = 0;

  //  printf("N_RB_DL %d, ra_header %d, rb_alloc %x\n",N_RB_DL,ra_header,rb_alloc);

  switch (N_RB_DL) {

  case 6:
    rb_alloc2[0] = rb_alloc&0x3f;
    break;

  case 25:
    if (ra_header == 0) {// Type 0 Allocation
      
      for (i=12;i>0;i--) {
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	if ((rb_alloc&(1<<i)) != 0)
	  rb_alloc2[0] |= (3<<((2*(12-i))));
	//      printf("rb_alloc2 (type 0) %x\n",rb_alloc2);
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      }
      if ((rb_alloc&1) != 0)
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	rb_alloc2[0] |= (1<<24);
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    }
    else {
      subset = rb_alloc&1;
      shift  = (rb_alloc>>1)&1;
      for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  rb_alloc2[0] |= (1<<(2*i));
	//printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
      }
      if ((shift == 0) && (subset == 1))
	rb_alloc2[0]<<=1;
      else if ((shift == 1) && (subset == 0))
	rb_alloc2[0]<<=4;
      else if ((shift == 1) && (subset == 1))
	rb_alloc2[0]<<=3;
    }
    break;
  case 50:
    if (ra_header == 0) {// Type 0 Allocation

      for (i=16; i>0; i--) {
        if ((rb_alloc&(1<<i)) != 0)
          rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32));
      }
      /*
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	for (i=1;i<=16;i++) {
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        if ((rb_alloc&(1<<(16-i))) != 0) 
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	rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
	}
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      */
      // bit mask across 
      if ((rb_alloc2[0]>>31)==1)
        rb_alloc2[1] |= 1;
      if ((rb_alloc&1) != 0)
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	rb_alloc2[1] |= (3<<16);
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      /*      
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	      for (i=0;i<16;i++) {
	      if (((rb_alloc>>(16-i))&1) != 0)
	      rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
	      if ((i==10)&&((rb_alloc&(1<<6))!=0))
	      rb_alloc2[1] = 1;
	      //	printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);
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	      }
	      // fill in 2 from last bit instead of 3
	      if ((rb_alloc&1) != 0)
	      rb_alloc2[1] |= (3<<i);
	      //    printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);
	      */
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      //      printf("rb_alloc[1]=%x,rb_alloc[0]=%x\n",rb_alloc2[1],rb_alloc2[0]);
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    }
    else {
      LOG_E(PHY,"resource type 1 not supported for  N_RB_DL=100\n");
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      mac_xface->macphy_exit("resource type 1 not supported for  N_RB_DL=100\n");
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      /*
	subset = rb_alloc&1;
	shift  = (rb_alloc>>1)&1;
	for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	rb_alloc2 |= (1<<(2*i));
	//      printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
	}
	if ((shift == 0) && (subset == 1))
	rb_alloc2<<=1;
	else if ((shift == 1) && (subset == 0))
	rb_alloc2<<=4;
	else if ((shift == 1) && (subset == 1))
	rb_alloc2<<=3;
      */
    }
    break;

  case 100:
    if (ra_header == 0) {// Type 0 Allocation
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(24-i))) != 0)
	  rb_alloc2[(4*i)>>5] |= (0xf<<((4*i)%32));
	//	printf("rb_alloc2[%d] (type 0) %x (%d)\n",(4*i)>>5,rb_alloc2[(4*i)>>5],rb_alloc&(1<<i));
      }
    }
    else {
      LOG_E(PHY,"resource type 1 not supported for  N_RB_DL=100\n");
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      mac_xface->macphy_exit("resource type 1 not supported for  N_RB_DL=100\n");
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      /*
	subset = rb_alloc&1;
	shift  = (rb_alloc>>1)&1;
	for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	rb_alloc2 |= (1<<(2*i));
	//      printf("rb_alloc2 (type 1) %x\n",rb_alloc2);
	}
	if ((shift == 0) && (subset == 1))
	rb_alloc2<<=1;
	else if ((shift == 1) && (subset == 0))
	rb_alloc2<<=4;
	else if ((shift == 1) && (subset == 1))
	rb_alloc2<<=3;
      */
    }
    break;

  default:
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    LOG_E(PHY,"Invalid N_RB_DL %d\n", N_RB_DL);
    DevParam (N_RB_DL, 0, 0);
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    break;
  }

}



uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) {

  uint32_t nprb=0,i;

  switch (N_RB_DL) {
  case 6:
    for (i=0;i<6;i++) {
      if ((rb_alloc&(1<<i)) != 0)
	nprb += 1;
    }
    break;
  case 25:
    if (ra_header == 0) {// Type 0 Allocation
      
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      for (i=12;i>0;i--) {
	if ((rb_alloc&(1<<i)) != 0)
	  nprb += 2;
      }
      if ((rb_alloc&1) != 0)
	nprb += 1;
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    }
    else {
      for (i=0;i<11;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
  case 50:
    if (ra_header == 0) {// Type 0 Allocation
            
      for (i=0;i<16;i++) {
	if ((rb_alloc&(1<<(16-i))) != 0)
	  nprb += 3;
      }
      if ((rb_alloc&1) != 0)
	nprb += 2;

    }
    else {
      for (i=0;i<17;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
  case 100:
    if (ra_header == 0) {// Type 0 Allocation
      
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(24-i))) != 0)
	  nprb += 4;
      }
    }
    else {
      for (i=0;i<25;i++) {
	if ((rb_alloc&(1<<(i+2))) != 0)
	  nprb += 1;
      }
    }
    break;
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  default:
    LOG_E(PHY,"Invalide N_RB_DL %d\n", N_RB_DL);
    DevParam (N_RB_DL, 0, 0);
    break;
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  }

  return(nprb);
}

uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs) {

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  uint16_t RIV;
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  if (Lcrbs<=(1+(N_RB_DL>>1)))
    RIV = (N_RB_DL*(Lcrbs-1)) + RBstart;
  else
    RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart);
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  return(RIV);
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}

int dist6[6]={0,2,3,5,1,4};
int dist50[50]={};
int dist100[100]={};

void generate_RIV_tables() {

  // 6RBs localized RIV
  uint8_t Lcrbs,RBstart;
  uint8_t distpos;
  uint16_t RIV;
  uint32_t alloc0,alloc_dist0;
  uint32_t alloc1,alloc_dist1;
  uint32_t alloc2,alloc_dist2;
  uint32_t alloc3,alloc_dist3;

  for (RBstart=0;RBstart<6;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    for (Lcrbs=1;Lcrbs<=(6-RBstart);Lcrbs++) {
      //printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
      alloc0 |= (1<<(RBstart+Lcrbs-1));
      // This is the RB<->VRB relationship for N_RB_DL=25
      alloc_dist0 |= (1<<dist6[RBstart+Lcrbs-1]);

      RIV=computeRIV(6,RBstart,Lcrbs);
      if (RIV>RIV_max6)
	RIV_max6 = RIV;

      //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
      localRIV2alloc_LUT6[RIV] = alloc0;
      distRIV2alloc_LUT6[RIV]  = alloc_dist0;
      RIV2nb_rb_LUT6[RIV]      = Lcrbs;
      RIV2first_rb_LUT6[RIV]   = RBstart;
    }
  }


  for (RBstart=0;RBstart<25;RBstart++) {
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    alloc0 = 0;
    alloc_dist0 = 0;
    for (Lcrbs=1;Lcrbs<=(25-RBstart);Lcrbs++) {
      //      printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
      alloc0 |= (1<<(RBstart+Lcrbs-1));
      // This is the RB<->VRB relationship for N_RB_DL=25
      distpos = ((RBstart+Lcrbs-1)*6)%23;
      if (distpos == 0)
	distpos = 23;
      alloc_dist0 |= (1<<distpos);
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      RIV=computeRIV(25,RBstart,Lcrbs);
      if (RIV>RIV_max25)
	RIV_max25 = RIV;
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      //      printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
      localRIV2alloc_LUT25[RIV] = alloc0;
      distRIV2alloc_LUT25[RIV]  = alloc_dist0;
      RIV2nb_rb_LUT25[RIV]      = Lcrbs;
      RIV2first_rb_LUT25[RIV]   = RBstart;
    }
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  }


  for (RBstart=0;RBstart<50;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    alloc1 = 0;
    alloc_dist1 = 0;
    for (Lcrbs=1;Lcrbs<=(50-RBstart);Lcrbs++) {
      //      printf("RBstart %d, len %d --> ",RBstart,Lcrbs);

      if ((RBstart+Lcrbs-1)<32)
	alloc0 |= (1<<(RBstart+Lcrbs-1));
      else
	alloc1 |= (1<<(RBstart+Lcrbs-33));

      if (dist50[RBstart+Lcrbs-1]<32)
	alloc_dist0 |= (1<<dist50[RBstart+Lcrbs-1]);
      else
	alloc_dist1 |= (1<<dist50[RBstart+Lcrbs-33]);

      RIV=computeRIV(50,RBstart,Lcrbs);
      if (RIV>RIV_max50)
	RIV_max50 = RIV;

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
      localRIV2alloc_LUT50_0[RIV] = alloc0;
      localRIV2alloc_LUT50_1[RIV] = alloc1;
      distRIV2alloc_LUT50_0[RIV]  = alloc_dist0;
      distRIV2alloc_LUT50_1[RIV]  = alloc_dist1;
      RIV2nb_rb_LUT50[RIV]        = Lcrbs;
      RIV2first_rb_LUT50[RIV]     = RBstart;
    }
  }


  for (RBstart=0;RBstart<100;RBstart++) {
    alloc0 = 0;
    alloc_dist0 = 0;
    alloc1 = 0;
    alloc_dist1 = 0;
    alloc2 = 0;
    alloc_dist2 = 0;
    alloc3 = 0;
    alloc_dist3 = 0;

    for (Lcrbs=1;Lcrbs<=(100-RBstart);Lcrbs++) {

      if ((RBstart+Lcrbs-1)<32)
	alloc0 |= (1<<(RBstart+Lcrbs-1));
      else if ((RBstart+Lcrbs-1)<64)
	alloc1 |= (1<<(RBstart+Lcrbs-33));
      else if ((RBstart+Lcrbs-1)<96)
	alloc2 |= (1<<(RBstart+Lcrbs-65));
      else
	alloc3 |= (1<<(RBstart+Lcrbs-97));

      if (dist100[RBstart+Lcrbs-1]<32)
	alloc_dist0 |= (1<<dist100[RBstart+Lcrbs-1]);
      else if (dist100[RBstart+Lcrbs-1]<64)
	alloc_dist1 |= (1<<dist100[RBstart+Lcrbs-33]);
      else if (dist100[RBstart+Lcrbs-1]<64)
	alloc_dist2 |= (1<<dist100[RBstart+Lcrbs-65]);
      else
	alloc_dist3 |= (1<<dist100[RBstart+Lcrbs-97]);

      RIV=computeRIV(100,RBstart,Lcrbs);
      if (RIV>RIV_max100)
	RIV_max100 = RIV;

      //      printf("RIV %d : first_rb %d NBRB %d\n",RIV,RBstart,Lcrbs);
      localRIV2alloc_LUT100_0[RIV] = alloc0;
      distRIV2alloc_LUT100_0[RIV]  = alloc_dist0;
      localRIV2alloc_LUT100_1[RIV] = alloc1;
      distRIV2alloc_LUT100_1[RIV]  = alloc_dist1;
      localRIV2alloc_LUT100_2[RIV] = alloc2;
      distRIV2alloc_LUT100_2[RIV]  = alloc_dist2;
      localRIV2alloc_LUT100_3[RIV] = alloc3;
      distRIV2alloc_LUT100_3[RIV]  = alloc_dist3;
      RIV2nb_rb_LUT100[RIV]      = Lcrbs;
      RIV2first_rb_LUT100[RIV]   = RBstart;
    }
  }
}

// Ngap = 3, N_VRB_DL=6, P=1, N_row=2, N_null=4*2-6=2
// permutation for even slots :
//    n_PRB'(0,2,4) = (0,1,2), n_PRB'(1,3,5) = (4,5,6)
//    n_PRB''(0,1,2,3) = (0,2,4,6)
//    => n_tilde_PRB(5) = (4)
//       n_tilde_PRB(4) = (1)
//       n_tilde_PRB(2,3) = (3,5)
//       n_tilde_PRB(0,1) = (0,2)


 
uint32_t get_rballoc(uint8_t vrb_type,uint16_t rb_alloc_dci) {

  if (vrb_type == 0)
    return(localRIV2alloc_LUT25[rb_alloc_dci]);
  else
    return(distRIV2alloc_LUT25[rb_alloc_dci]);

}

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uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti) {
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  unsigned char UE_id;

  // find the UE_index corresponding to rnti
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  UE_id = find_ue(rnti,PHY_vars_eNB_g[Mod_id][CC_id]);
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  DevAssert( UE_id != (unsigned char)-1 );
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  return(PHY_vars_eNB_g[Mod_id][CC_id]->transmission_mode[UE_id]);
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}

int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
				       void *dci_pdu,
				       uint16_t rnti,
				       DCI_format_t dci_format,
				       LTE_eNB_DLSCH_t **dlsch,
				       LTE_DL_FRAME_PARMS *frame_parms,
				       PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
				       uint16_t si_rnti,
				       uint16_t ra_rnti,
				       uint16_t p_rnti,
				       uint16_t DL_pmi_single) {

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  uint8_t harq_pid = UINT8_MAX;
  uint32_t rballoc = UINT32_MAX;
  uint32_t RIV_max = 0;
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  uint8_t NPRB,tbswap,tpmi=0;
  LTE_eNB_DLSCH_t *dlsch0=NULL,*dlsch1;
  uint8_t frame_type=frame_parms->frame_type;
  uint8_t vrb_type=0;
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  uint8_t mcs=0,mcs1=0,mcs2=0;
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  uint8_t I_mcs = 0;
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  uint8_t rv=0,rv1=0,rv2=0;
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  uint8_t rah=0;
  uint8_t TPC=0;
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  LTE_DL_eNB_HARQ_t *dlsch0_harq,*dlsch1_harq;
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  //   printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);

  switch (dci_format) {

  case format0:
    return(-1);
    break;
  case format1A:  // This is DLSCH allocation for control traffic

 

    dlsch[0]->subframe_tx[subframe] = 1;

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    switch (frame_parms->N_RB_DL) {
    case 6:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

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	//	      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
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      }
      else {
	vrb_type = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;

	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
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      dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
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      if (vrb_type == 0)
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	dlsch0_harq->rb_alloc[0]                       = localRIV2alloc_LUT6[rballoc];
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      else
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	dlsch0_harq->rb_alloc[0]                       = distRIV2alloc_LUT6[rballoc];
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      dlsch0_harq->nb_rb                               = RIV2nb_rb_LUT6[rballoc];//NPRB;
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      RIV_max = RIV_max6;

      
      break;
    case 25:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_5MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;

	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

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      dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
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      if (vrb_type == 0)
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	dlsch0_harq->rb_alloc[0]                       = localRIV2alloc_LUT25[rballoc];
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      else
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	dlsch0_harq->rb_alloc[0]                       = distRIV2alloc_LUT25[rballoc];
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      dlsch0_harq->nb_rb                               = RIV2nb_rb_LUT25[rballoc];//NPRB;
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      RIV_max = RIV_max25;      
      break;
    case 50:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;

	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

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      dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
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      if (vrb_type == 0) {
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	dlsch0_harq->rb_alloc[0]                       = localRIV2alloc_LUT50_0[rballoc];
	dlsch0_harq->rb_alloc[1]                       = localRIV2alloc_LUT50_1[rballoc];
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      }
      else {
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	dlsch0_harq->rb_alloc[0]                       = distRIV2alloc_LUT50_0[rballoc];
	dlsch0_harq->rb_alloc[1]                       = distRIV2alloc_LUT50_1[rballoc];
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      }
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      dlsch0_harq->nb_rb                               = RIV2nb_rb_LUT50[rballoc];//NPRB;
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      RIV_max = RIV_max50;
      break;
    case 100:
      if (frame_type == TDD) {
	vrb_type = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
	//      printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }
      else {
	vrb_type = ((DCI1A_20MHz_FDD_t *)dci_pdu)->vrb_type;
	mcs      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
	rballoc  = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
	TPC      = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC; 
	harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
	//      printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
      }

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      dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
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      if (vrb_type == 0) {
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	dlsch0_harq->rb_alloc[0]                       = localRIV2alloc_LUT100_0[rballoc];
	dlsch0_harq->rb_alloc[1]                       = localRIV2alloc_LUT100_1[rballoc];
	dlsch0_harq->rb_alloc[2]                       = localRIV2alloc_LUT100_2[rballoc];
	dlsch0_harq->rb_alloc[3]                       = localRIV2alloc_LUT100_3[rballoc];
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      }
      else {
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	dlsch0_harq->rb_alloc[0]                       = distRIV2alloc_LUT100_0[rballoc];
	dlsch0_harq->rb_alloc[1]                       = distRIV2alloc_LUT100_1[rballoc];
	dlsch0_harq->rb_alloc[2]                       = distRIV2alloc_LUT100_2[rballoc];
	dlsch0_harq->rb_alloc[3]                       = distRIV2alloc_LUT100_3[rballoc];
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      }
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      dlsch0_harq->nb_rb                               = RIV2nb_rb_LUT100[rballoc];//NPRB;
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      RIV_max = RIV_max100;
      break;
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      default:
        LOG_E(PHY,"Invalid N_RB_D %dL\n", frame_parms->N_RB_DL);
        DevParam (frame_parms->N_RB_DL, 0, 0);
        break;
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    }

    // harq_pid field is reserved
    if ((rnti==si_rnti) || (rnti==ra_rnti) || (rnti==p_rnti)){  //
      harq_pid=0;
      // see 36-212 V8.6.0 p. 45
      NPRB      = (TPC&1)+2;
      // 36-213 sec.7.1.7.2 p.26
      I_mcs     = mcs;
    }
    else {
      if (harq_pid>1) {
	LOG_E(PHY,"ERROR: Format 1A: harq_pid > 1\n");
	return(-1);
      }
      if (rballoc>RIV_max) {
	LOG_E(PHY,"ERROR: Format 1A: rb_alloc (%x) > RIV_max (%x)\n",rballoc,RIV_max);
	return(-1);
      }
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      NPRB      = dlsch0_harq->nb_rb;
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      I_mcs     = get_I_TBS(mcs);
    }

    if (NPRB==0)
      return(-1);

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    //  printf("NPRB %d, nb_rb %d, ndi %d\n",NPRB,dlsch0_harq->nb_rb,ndi);
    dlsch0_harq->rvidx     = rv; 
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    dlsch0_harq->Nl          = 1;
    //dlsch0_harq->layer_index = 0;
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    dlsch0_harq->mimo_mode   = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
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    /*   
	 if ((rnti!=si_rnti)&&(rnti!=ra_rnti)&&(rnti!=p_rnti)) {  //handle toggling for C-RNTI
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	 if (dlsch0_harq->first_tx == 1) {
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	 LOG_D(PHY,"First TX for TC-RNTI %x, clearing first_tx flag\n",rnti);
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	 dlsch0_harq->first_tx=0;
	 dlsch0_harq->Ndi = 1;
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	 } 
	 else {
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	 if (ndi == dlsch0_harq->DCINdi)
	 dlsch0_harq->Ndi         = 0;
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	 else
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	 dlsch0_harq->Ndi         = 1;
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	 }
    
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	 dlsch0_harq->DCINdi=ndi;
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	 }
	 else {
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	 dlsch0_harq->Ndi         = 1;
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	 }
    */
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    dlsch0_harq->dl_power_off = 1;
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    dlsch0_harq->mcs           = mcs;
    dlsch0_harq->TBS           = TBStable[I_mcs][NPRB-1];
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    dlsch[0]->current_harq_pid   = harq_pid;
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    dlsch[0]->harq_ids[subframe] = harq_pid;

    dlsch[0]->active = 1;
    dlsch0 = dlsch[0];

    dlsch[0]->rnti = rnti;

    dlsch[0]->harq_ids[subframe] = harq_pid;
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    if (dlsch0_harq->round == 0)
      dlsch0_harq->status = ACTIVE;
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    break;
  case format1:

    switch (frame_parms->N_RB_DL) {

    case 6:
      if (frame_type == TDD) {
	mcs       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
	harq_pid  = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
	harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 25:
      
      if (frame_type == TDD) {
	mcs       = ((DCI1_5MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
	harq_pid  = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
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	LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_TDD_t *)dci_pdu)->ndi,harq_pid);
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      }
      else {
	mcs      = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
	harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
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	LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_FDD_t *)dci_pdu)->ndi,harq_pid);

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      }
      break;
    case 50:
      if (frame_type == TDD) {
	mcs       = ((DCI1_10MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
	harq_pid  = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_10MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
	harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;

    case 100:
      if (frame_type == TDD) {
	mcs       = ((DCI1_20MHz_TDD_t *)dci_pdu)->mcs;
	rballoc   = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
	rv        = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
	harq_pid  = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs      = ((DCI1_20MHz_FDD_t *)dci_pdu)->mcs;
	rah      = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
	rballoc  = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
	rv       = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
	harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;

    }

    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 1: harq_pid >= 8\n");
      return(-1);
    }

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    dlsch0_harq = dlsch[0]->harq_processes[harq_pid];

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    // msg("DCI: Setting subframe_tx for subframe %d\n",subframe);
    dlsch[0]->subframe_tx[subframe] = 1;

    conv_rballoc(rah,
		 rballoc,frame_parms->N_RB_DL,
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		 dlsch0_harq->rb_alloc);
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    dlsch0_harq->nb_rb = conv_nprb(rah,
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				rballoc,
				frame_parms->N_RB_DL);

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    NPRB      = dlsch0_harq->nb_rb;
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    if (NPRB==0)
      return(-1);


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    dlsch0_harq->rvidx       = rv;
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    dlsch0_harq->Nl          = 1;
    //    dlsch[0]->layer_index = 0;
    dlsch0_harq->mimo_mode   = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
    dlsch0_harq->dl_power_off = 1;
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    /*
      if (dlsch[0]->harq_processes[harq_pid]->first_tx == 1) {
      LOG_D(PHY,"First TX for C-RNTI %x, clearing first_tx flag, shouldn't happen!\n",rnti);
      dlsch[0]->harq_processes[harq_pid]->first_tx=0;
      dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
      } 
      else {
      LOG_D(PHY,"Checking for Toggled Ndi for C-RNTI %x, old value %d, DCINdi %d\n",rnti,dlsch[0]->harq_processes[harq_pid]->DCINdi,ndi);
      if (ndi == dlsch[0]->harq_processes[harq_pid]->DCINdi)
      dlsch[0]->harq_processes[harq_pid]->Ndi         = 0;
      else
      dlsch[0]->harq_processes[harq_pid]->Ndi         = 1;
      }
      dlsch[0]->harq_processes[harq_pid]->DCINdi=ndi;
    */
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    dlsch[0]->active = 1;

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    if (dlsch0_harq->round == 0) {
      dlsch0_harq->status = ACTIVE;
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      //            printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
      // MCS and TBS don't change across HARQ rounds
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      dlsch0_harq->mcs         = mcs;
      dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][NPRB-1];
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    }


    dlsch[0]->current_harq_pid = harq_pid;
    dlsch[0]->harq_ids[subframe] = harq_pid;



    dlsch0 = dlsch[0];

    dlsch[0]->rnti = rnti;


    break;

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  case format2:

    switch (frame_parms->N_RB_DL) {

    case 6:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_1_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_1_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;
    case 25:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }      
      break;
    case 50:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_10MHz_2A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_10MHz_2A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;

    case 100:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_20MHz_2A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_20MHz_2A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2 DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;
    }

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    if (harq_pid>=8) {
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      LOG_E(PHY,"ERROR: Format 2_2A: harq_pid >= 8\n");
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      return(-1);
    }


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    // Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
    // note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
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    if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
    }
    else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
    }

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    dlsch0_harq = dlsch0->harq_processes[harq_pid];
    dlsch1_harq = dlsch1->harq_processes[harq_pid];

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    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->current_harq_pid = harq_pid;
    dlsch1->current_harq_pid = harq_pid;
    dlsch0->harq_ids[subframe] = harq_pid;
    dlsch1->harq_ids[subframe] = harq_pid;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);


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    conv_rballoc(rah,
		 rballoc,
		 frame_parms->N_RB_DL,
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		 dlsch0_harq->rb_alloc);
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    dlsch1_harq->rb_alloc[0]                         = dlsch0_harq->rb_alloc[0];
    dlsch0_harq->nb_rb                               = conv_nprb(rah,
								 rballoc,
								 frame_parms->N_RB_DL);
    dlsch1_harq->nb_rb                               = dlsch0_harq->nb_rb;
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    if (dlsch0_harq->nb_rb == 0)
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      return(-1);

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    dlsch0_harq->mcs       = mcs1;
    dlsch1_harq->mcs       = mcs2;
    dlsch0_harq->rvidx     = rv1;
    dlsch1_harq->rvidx     = rv2;
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    // assume both TBs are active
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    dlsch0_harq->Nl        = 1;
    dlsch1_harq->Nl        = 1;
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    dlsch0->active = 1;
    dlsch1->active = 1;


    // check if either TB is disabled (see 36-213 V11.3 Section )
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    if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
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      dlsch0->active = 0;
    }
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    if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
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      dlsch1->active = 0;
    }

    if (frame_parms->nb_antennas_tx == 2) {
      if (dlsch1->active == 1) { // both TBs are active
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	dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
	dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
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	switch (tpmi) {
	case 0:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING11;
	  dlsch1_harq->mimo_mode   = UNIFORM_PRECODING1m1;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,0);
	  dlsch1_harq->pmi_alloc                             = pmi_extend(frame_parms,1);
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	  break;
	case 1:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1j;
	  dlsch1_harq->mimo_mode   = UNIFORM_PRECODING1mj;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,2);
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,3);
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	  break;
	case 2: // PUSCH precoding
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	  dlsch0_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
	  dlsch0_harq->pmi_alloc                             = DL_pmi_single;
	  dlsch1_harq->mimo_mode   = DUALSTREAM_PUSCH_PRECODING;
	  dlsch1_harq->pmi_alloc                             = DL_pmi_single;
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	  break;
	default:
	  break;
	}
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	dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
	dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
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      }
      else { // only one is active
	switch (tpmi) {
	case 0 :
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	  dlsch0_harq->mimo_mode   = ALAMOUTI;
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	  break;
	case 1:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING11;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,0);
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	  break;
	case 2:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1m1;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,1);
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	  break;
	case 3:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1j;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,2);
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	  break;
	case 4:
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	  dlsch0_harq->mimo_mode   = UNIFORM_PRECODING1mj;
	  dlsch0_harq->pmi_alloc                             = pmi_extend(frame_parms,3);
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	  break;
	case 5:
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	  dlsch0_harq->mimo_mode   = PUSCH_PRECODING0;
	  dlsch0_harq->pmi_alloc                             = DL_pmi_single;
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	  break;
	case 6:
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	  dlsch0_harq->mimo_mode   = PUSCH_PRECODING1;
	  dlsch0_harq->pmi_alloc                             = DL_pmi_single;
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	  break;
	}
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	dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
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      }
    }
    else if (frame_parms->nb_antennas_tx == 4) {
      // fill in later
    }
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    // reset HARQ process if this is the first transmission
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    if (dlsch0_harq->round == 0) {
      dlsch0_harq->status = ACTIVE;
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    }
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    if (dlsch1_harq->round == 0) {
      dlsch1_harq->status = ACTIVE;
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    }

    dlsch0->rnti = rnti;
    dlsch1->rnti = rnti;

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    dlsch0_harq->dl_power_off = 0;
    dlsch1_harq->dl_power_off = 0;

    break;

  case format2A:

    switch (frame_parms->N_RB_DL) {

    case 6:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_1_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	}
	else {
	  mcs1      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_1_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_1_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rv1       = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_1_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;
    case 25:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	}
	else {
	  mcs1      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_5MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_5MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }      
      break;
    case 50:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_10MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	}
	else {
	  mcs1      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_10MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_10MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_10MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;

    case 100:
      if (frame_parms->nb_antennas_tx == 2) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_20MHz_2A_TDD_t *)dci_pdu)->tb_swap;
	}
	else {
	  mcs1      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_20MHz_2A_FDD_t *)dci_pdu)->tb_swap;
	}
      }
      else if (frame_parms->nb_antennas_tx == 4) {
	if (frame_type == TDD) {
	  mcs1      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tb_swap;
	  tpmi      = ((DCI2A_20MHz_4A_TDD_t *)dci_pdu)->tpmi;
	}
	else {
	  mcs1      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs1;
	  mcs2      = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->mcs2;
	  rballoc   = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rballoc;
	  rah       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rah;
	  rv1       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv1;
	  rv2       = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->rv2;
	  harq_pid  = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->harq_pid;
	  tbswap    = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tb_swap;
	  tpmi    = ((DCI2A_20MHz_4A_FDD_t *)dci_pdu)->tpmi;
	}
      }
      else {
	LOG_E(PHY,"eNB: subframe %d UE %x, Format2A DCI: unsupported number of TX antennas %d\n",frame_parms->nb_antennas_tx);
      }
      break;
    }


    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 2_2A: harq_pid >= 8\n");
      return(-1);
    }


    // Flip the TB to codeword mapping as described in 5.3.3.1.5 of 36-212 V11.3.0
    // note that we must set tbswap=0 in eNB scheduler if one TB is deactivated
    if (tbswap == 0) {
      dlsch0 = dlsch[0];
      dlsch1 = dlsch[1];
    }
    else{
      dlsch0 = dlsch[1];
      dlsch1 = dlsch[0];
    }

    dlsch0_harq = dlsch0->harq_processes[harq_pid];
    dlsch1_harq = dlsch1->harq_processes[harq_pid];

    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->current_harq_pid = harq_pid;
    dlsch1->current_harq_pid = harq_pid;
    dlsch0->harq_ids[subframe] = harq_pid;
    dlsch1->harq_ids[subframe] = harq_pid;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);


    conv_rballoc(rah,
		 rballoc,
		 frame_parms->N_RB_DL,
		 dlsch0_harq->rb_alloc);

    dlsch1_harq->rb_alloc[0]                         = dlsch0_harq->rb_alloc[0];
    dlsch0_harq->nb_rb                               = conv_nprb(rah,
								 rballoc,
								 frame_parms->N_RB_DL);
    dlsch1_harq->nb_rb                               = dlsch0_harq->nb_rb;

    if (dlsch0_harq->nb_rb == 0)
      return(-1);

    dlsch0_harq->mcs       = mcs1;
    dlsch1_harq->mcs       = mcs2;
    dlsch0_harq->rvidx     = rv1;
    dlsch1_harq->rvidx     = rv2;

    // assume both TBs are active
    dlsch0_harq->Nl        = 1;
    dlsch1_harq->Nl        = 1;
    dlsch0->active = 1;
    dlsch1->active = 1;


    // check if either TB is disabled (see 36-213 V11.3 Section )
    if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
      dlsch0->active = 0;
    }
    if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
      dlsch1->active = 0;
    }

    dlsch0_harq->dl_power_off = 0;
    dlsch1_harq->dl_power_off = 0;


    if (frame_parms->nb_antennas_tx == 2) {
      dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
      dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
      if ((dlsch0->active==1) && (dlsch1->active==1)) {
	dlsch0_harq->mimo_mode = LARGE_CDD;
	dlsch1_harq->mimo_mode = LARGE_CDD;
	dlsch0_harq->dl_power_off = 1;
	dlsch1_harq->dl_power_off = 1;
      }
      else {
	dlsch0_harq->mimo_mode   = ALAMOUTI;
	dlsch1_harq->mimo_mode   = ALAMOUTI;
      }
    }
    else if (frame_parms->nb_antennas_tx == 4) { // 4 antenna case
      if ((dlsch0->active==1) && (dlsch1->active==1)) {
	switch (tpmi) {
	case 0: // one layer per transport block
	  dlsch0_harq->mimo_mode   = LARGE_CDD;
	  dlsch1_harq->mimo_mode   = LARGE_CDD;
	  dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
	  dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
	  dlsch0_harq->dl_power_off = 1;
	  dlsch1_harq->dl_power_off = 1;
	  break;
	case 1: // one-layers on TB 0, two on TB 1
	  dlsch0_harq->mimo_mode   = LARGE_CDD;
	  dlsch1_harq->mimo_mode   = LARGE_CDD;
	  dlsch1_harq->Nl          = 2;
	  dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
	  dlsch0_harq->dl_power_off = 1;
	  dlsch1_harq->dl_power_off = 1;
	  break;
	case 2: // two-layers on TB 0, two on TB 1
	  dlsch0_harq->mimo_mode   = LARGE_CDD;
	  dlsch1_harq->mimo_mode   = LARGE_CDD;
	  dlsch0_harq->Nl          = 2;
	  dlsch0_harq->dl_power_off = 1;
	  dlsch1_harq->dl_power_off = 1;
	  if (frame_parms->N_RB_DL <= 56) {
	    dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
	    dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
	  }
	  else {
	    LOG_E(PHY,"Add implementation of Table 7.1.7.2.2-1 for two-layer TBS conversion with N_RB_DL > 56\n");
	  }
	  break;
	case 3: //
	  LOG_E(PHY,"Illegal value (3) for TPMI in Format 2A DCI\n"); 
	  break;
	}
      }
      else if (dlsch0->active == 1) {
	switch (tpmi) {
	case 0: // one layer per transport block
	  dlsch0_harq->mimo_mode   = ALAMOUTI;
	  dlsch1_harq->mimo_mode   = ALAMOUTI;
	  dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
	  break;
	case 1: // two-layers on TB 0
	  dlsch0_harq->mimo_mode   = LARGE_CDD;
	  dlsch0_harq->Nl          = 2;
	  dlsch0_harq->dl_power_off = 1;
	  dlsch0_harq->TBS         = TBStable[get_I_TBS(dlsch0_harq->mcs)][(dlsch0_harq->nb_rb<<1)-1];
	  break;
	case 2: // two-layers on TB 0, two on TB 1
	case 3: //
	  LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi); 
	  break;
	}
      }
      else if (dlsch1->active == 1) {
	switch (tpmi) {
	case 0: // one layer per transport block
	  dlsch0_harq->mimo_mode   = ALAMOUTI;
	  dlsch1_harq->mimo_mode   = ALAMOUTI;
	  dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
	  break;
	case 1: // two-layers on TB 0
	  dlsch1_harq->mimo_mode   = LARGE_CDD;
	  dlsch1_harq->Nl          = 2;
	  dlsch1_harq->dl_power_off = 1;
	  dlsch1_harq->TBS         = TBStable[get_I_TBS(dlsch1_harq->mcs)][(dlsch1_harq->nb_rb<<1)-1];
	  break;
	case 2: // two-layers on TB 0, two on TB 1
	case 3: //
	  LOG_E(PHY,"Illegal value %d for TPMI in Format 2A DCI with one transport block enabled\n",tpmi); 
	  break;
	}
      }
    }
    else {
      LOG_E(PHY,"Illegal number of antennas for eNB %d\n",frame_parms->nb_antennas_tx);
    }
  
    // reset HARQ process if this is the first transmission
    if ((dlsch0->active==1) && (dlsch0_harq->round == 0)) {
      dlsch0_harq->status = ACTIVE;
    }
    if ((dlsch1->active==1) && (dlsch1_harq->round == 0)) {
      dlsch1_harq->status = ACTIVE;
    }

    dlsch0->rnti = rnti;
    dlsch1->rnti = rnti;


    //    printf("eNB: Format 2A TBS0 %d, TBS1 %d\n",dlsch0_harq->TBS,dlsch1_harq->TBS);
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    break;

  case format2B:

    switch (frame_parms->N_RB_DL) {

    case 6:
      if (frame_type == TDD) {
	mcs1      = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rballoc;
	rv1       = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs1      = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rballoc;
	rv1       = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 25:
      if (frame_type == TDD) {
	mcs1      = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_5MHz_TDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_5MHz_TDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_5MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs1      = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_5MHz_FDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_5MHz_FDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_5MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    case 50:
      if (frame_type == TDD) {
	mcs1      = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_10MHz_TDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_10MHz_TDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_10MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs1      = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_10MHz_FDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_10MHz_FDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_10MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;

    case 100:
      if (frame_type == TDD) {
	mcs1      = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_20MHz_TDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_20MHz_TDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_20MHz_TDD_t *)dci_pdu)->harq_pid;
      }
      else {
	mcs1      = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs1;
	mcs2      = ((DCI2B_20MHz_FDD_t *)dci_pdu)->mcs2;
	rballoc   = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rballoc;
	rah       = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rah;
	rv1       = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv1;
	rv2       = ((DCI2B_20MHz_FDD_t *)dci_pdu)->rv2;
	harq_pid  = ((DCI2B_20MHz_FDD_t *)dci_pdu)->harq_pid;
      }
      break;
    }


    if (harq_pid>=8) {
      LOG_E(PHY,"ERROR: Format 2_2A: harq_pid >= 8\n");
      return(-1);
    }



    dlsch0 = dlsch[0];
    dlsch1 = dlsch[1];

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    dlsch0->subframe_tx[subframe] = 1;

    dlsch0->current_harq_pid = harq_pid;
    dlsch1->current_harq_pid = harq_pid;
    dlsch0->harq_ids[subframe] = harq_pid;
    dlsch1->harq_ids[subframe] = harq_pid;
    //    printf("Setting DLSCH harq id %d to subframe %d\n",harq_pid,subframe);