phy_procedures_lte_ue.c 141 KB
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/*******************************************************************************
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    OpenAirInterface 
    Copyright(c) 1999 - 2014 Eurecom
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    OpenAirInterface is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
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    OpenAirInterface is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
    along with OpenAirInterface.The full GNU General Public License is 
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    included in this distribution in the file called "COPYING". If not, 
    see <http://www.gnu.org/licenses/>.
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  Contact Information
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  OpenAirInterface Admin: openair_admin@eurecom.fr
  OpenAirInterface Tech : openair_tech@eurecom.fr
  OpenAirInterface Dev  : openair4g-devel@eurecom.fr
  
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  Address      : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE
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 *******************************************************************************/
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/*! \file phy_procedures_lte_ue.c
 * \brief Implementation of UE procedures from 36.213 LTE specifications
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 * \author R. Knopp, F. Kaltenberger, N. Nikaein
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 * \date 2011
 * \version 0.1
 * \company Eurecom
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 * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr, navid.nikaein@eurecom.fr
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 * \note
 * \warning
 */

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#include "assertions.h"
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#include "defs.h"
#include "PHY/defs.h"
#include "PHY/extern.h"
#include "MAC_INTERFACE/defs.h"
#include "MAC_INTERFACE/extern.h"
#include "SCHED/defs.h"
#include "SCHED/extern.h"

#ifdef EMOS
#include "SCHED/phy_procedures_emos.h"
#endif

#ifdef EXMIMO
#ifdef DRIVER2013
#include "openair0_lib.h"
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#include "gain_control.h"
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extern int card;
#else
#include "ARCH/CBMIMO1/DEVICE_DRIVER/extern.h"
#include "ARCH/CBMIMO1/DEVICE_DRIVER/defs.h"
#include "ARCH/CBMIMO1/DEVICE_DRIVER/from_grlib_softregs.h"
#endif
#endif

#define DEBUG_PHY_PROC
#define UE_TX_POWER (-10)

//#ifdef OPENAIR2
#ifndef PUCCH
#define PUCCH
#endif
//#endif

//#ifdef OPENAIR2
#include "LAYER2/MAC/extern.h"
#include "LAYER2/MAC/defs.h"
#include "UTIL/LOG/log.h"
//#endif

#ifdef EMOS
fifo_dump_emos_UE emos_dump_UE;
#endif

#include "UTIL/LOG/vcd_signal_dumper.h"

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#if defined(ENABLE_ITTI)
# include "intertask_interface.h"
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#   if defined(ENABLE_RAL)
#     include "timer.h"
#   endif
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#endif

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#ifndef OPENAIR2
//#define DIAG_PHY
#endif

#define DLSCH_RB_ALLOC 0x1fbf  // skip DC RB (total 23/25 RBs)
#define DLSCH_RB_ALLOC_12 0x0aaa  // skip DC RB (total 23/25 RBs)

#define NS_PER_SLOT 500000

extern inline unsigned int taus(void);
extern int oai_exit;

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uint8_t ulsch_input_buffer[2700] __attribute__ ((aligned(16)));
uint8_t access_mode;
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#ifdef DLSCH_THREAD
extern int dlsch_instance_cnt[8];
extern int dlsch_subframe[8];
extern pthread_mutex_t dlsch_mutex[8];
/// Condition variable for dlsch thread
extern pthread_cond_t dlsch_cond[8];
extern int rx_pdsch_instance_cnt;
extern int rx_pdsch_slot;
extern pthread_mutex_t rx_pdsch_mutex;
/// Condition variable for rx_pdsch thread
extern pthread_cond_t rx_pdsch_cond;
#endif

DCI_ALLOC_t dci_alloc_rx[8];

#ifdef DIAG_PHY
extern int rx_sig_fifo;
#endif

/*
#if defined(CBMIMO) || defined(EXMIMO)
#include <rtai_lxrt.h>
extern struct timing_info_t {
  unsigned int frame, hw_slot, last_slot, next_slot;
  RTIME time0, time1, time2;
  unsigned int mbox0, mbox1, mbox2, mbox_target;
} timing_info[2];
#endif
*/

#ifdef EXMIMO
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extern uint32_t downlink_frequency[MAX_NUM_CCs][4];
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#endif

#ifdef USER_MODE

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void dump_dlsch(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe,uint8_t harq_pid) {
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  unsigned int coded_bits_per_codeword;
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  uint8_t nsymb = (phy_vars_ue->lte_frame_parms.Ncp == 0) ? 14 : 12;
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  coded_bits_per_codeword = get_G(&phy_vars_ue->lte_frame_parms,
                                  phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->nb_rb,
                                  phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->rb_alloc,
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                                  get_Qm(phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->mcs),
				  phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->Nl,    
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                                  phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
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                                  phy_vars_ue->frame_rx,subframe);
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  write_output("rxsigF0.m","rxsF0", phy_vars_ue->lte_ue_common_vars.rxdataF[0],2*nsymb*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,2,1);
  write_output("rxsigF0_ext.m","rxsF0_ext", phy_vars_ue->lte_ue_pdsch_vars[0]->rxdataF_ext[0],2*nsymb*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,1,1);
  write_output("dlsch00_ch0_ext.m","dl00_ch0_ext", phy_vars_ue->lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[0],300*nsymb,1,1);
  /*
    write_output("dlsch01_ch0_ext.m","dl01_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[1],300*12,1,1);
    write_output("dlsch10_ch0_ext.m","dl10_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[2],300*12,1,1);
    write_output("dlsch11_ch0_ext.m","dl11_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[3],300*12,1,1);
    write_output("dlsch_rho.m","dl_rho",lte_ue_pdsch_vars[0]->rho[0],300*12,1,1);
  */
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  write_output("dlsch_rxF_comp0.m","dlsch0_rxF_comp0", phy_vars_ue->lte_ue_pdsch_vars[0]->rxdataF_comp0[0],300*12,1,1);
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  write_output("dlsch_rxF_llr.m","dlsch_llr", phy_vars_ue->lte_ue_pdsch_vars[0]->llr[0],coded_bits_per_codeword,1,0);
  
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  write_output("dlsch_mag1.m","dlschmag1",phy_vars_ue->lte_ue_pdsch_vars[0]->dl_ch_mag0,300*12,1,1);
  write_output("dlsch_mag2.m","dlschmag2",phy_vars_ue->lte_ue_pdsch_vars[0]->dl_ch_magb0,300*12,1,1);
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}

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void dump_dlsch_SI(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe) {
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  unsigned int coded_bits_per_codeword;
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  uint8_t nsymb = ((phy_vars_ue->lte_frame_parms.Ncp == 0) ? 14 : 12);
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  coded_bits_per_codeword = get_G(&phy_vars_ue->lte_frame_parms,
                                  phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->nb_rb,
                                  phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->rb_alloc,
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                                  get_Qm(phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->mcs),
				  1,
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                                  phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
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                                  phy_vars_ue->frame_rx,subframe);
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  LOG_D(PHY,"[UE %d] Dumping dlsch_SI : nb_rb %d, mcs %d, nb_rb %d, num_pdcch_symbols %d,G %d\n",
      phy_vars_ue->Mod_id,
      phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->nb_rb,
      phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->mcs,  
      phy_vars_ue->dlsch_ue_SI[eNB_id]->harq_processes[0]->nb_rb,  
      phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
      coded_bits_per_codeword);

  write_output("rxsigF0.m","rxsF0", phy_vars_ue->lte_ue_common_vars.rxdataF[0],2*nsymb*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,2,1);
  write_output("rxsigF0_ext.m","rxsF0_ext", phy_vars_ue->lte_ue_pdsch_vars_SI[0]->rxdataF_ext[0],2*nsymb*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,1,1);
  write_output("dlsch00_ch0_ext.m","dl00_ch0_ext", phy_vars_ue->lte_ue_pdsch_vars_SI[0]->dl_ch_estimates_ext[0],300*nsymb,1,1);
  /*
    write_output("dlsch01_ch0_ext.m","dl01_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[1],300*12,1,1);
    write_output("dlsch10_ch0_ext.m","dl10_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[2],300*12,1,1);
    write_output("dlsch11_ch0_ext.m","dl11_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[3],300*12,1,1);
    write_output("dlsch_rho.m","dl_rho",lte_ue_pdsch_vars[0]->rho[0],300*12,1,1);
  */
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  write_output("dlsch_rxF_comp0.m","dlsch0_rxF_comp0", phy_vars_ue->lte_ue_pdsch_vars_SI[0]->rxdataF_comp0[0],300*nsymb,1,1);
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  write_output("dlsch_rxF_llr.m","dlsch_llr", phy_vars_ue->lte_ue_pdsch_vars_SI[0]->llr[0],coded_bits_per_codeword,1,0);
  
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  write_output("dlsch_mag1.m","dlschmag1",phy_vars_ue->lte_ue_pdsch_vars_SI[0]->dl_ch_mag0,300*nsymb,1,1);
  write_output("dlsch_mag2.m","dlschmag2",phy_vars_ue->lte_ue_pdsch_vars_SI[0]->dl_ch_magb0,300*nsymb,1,1);
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  exit(-1);
}

#ifdef EXMIMO
unsigned int prach_gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162};

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unsigned int get_tx_amp(int power_dBm, int power_max_dBm) {
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  int gain_dB = power_dBm - power_max_dBm;
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  if (gain_dB < -30) {
    return(AMP/32);
  }
  else if (gain_dB>0)
    return(AMP);
  else
    return(100*AMP/prach_gain_table[-gain_dB]);
}
#endif

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void dump_dlsch_ra(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe) {
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  unsigned int coded_bits_per_codeword;
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  uint8_t nsymb = ((phy_vars_ue->lte_frame_parms.Ncp == 0) ? 14 : 12);
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  coded_bits_per_codeword = get_G(&phy_vars_ue->lte_frame_parms,
                                  phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->nb_rb,
                                  phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->rb_alloc,
                                  get_Qm(phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->mcs),  
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				  1,
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                                  phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
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                                  phy_vars_ue->frame_rx,subframe);
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  LOG_D(PHY,"[UE %d] Dumping dlsch_ra : nb_rb %d, mcs %d, nb_rb %d, num_pdcch_symbols %d,G %d\n",
      phy_vars_ue->Mod_id,
      phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->nb_rb,
      phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->mcs,  
      phy_vars_ue->dlsch_ue_ra[eNB_id]->harq_processes[0]->nb_rb,  
      phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
      coded_bits_per_codeword);

  write_output("rxsigF0.m","rxsF0", phy_vars_ue->lte_ue_common_vars.rxdataF[0],2*12*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,2,1);
  write_output("rxsigF0_ext.m","rxsF0_ext", phy_vars_ue->lte_ue_pdsch_vars_ra[0]->rxdataF_ext[0],2*12*phy_vars_ue->lte_frame_parms.ofdm_symbol_size,1,1);
  write_output("dlsch00_ch0_ext.m","dl00_ch0_ext", phy_vars_ue->lte_ue_pdsch_vars_ra[0]->dl_ch_estimates_ext[0],300*nsymb,1,1);
  /*
    write_output("dlsch01_ch0_ext.m","dl01_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[1],300*12,1,1);
    write_output("dlsch10_ch0_ext.m","dl10_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[2],300*12,1,1);
    write_output("dlsch11_ch0_ext.m","dl11_ch0_ext",lte_ue_pdsch_vars[0]->dl_ch_estimates_ext[3],300*12,1,1);
    write_output("dlsch_rho.m","dl_rho",lte_ue_pdsch_vars[0]->rho[0],300*12,1,1);
  */
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  write_output("dlsch_rxF_comp0.m","dlsch0_rxF_comp0", phy_vars_ue->lte_ue_pdsch_vars_ra[0]->rxdataF_comp0[0],300*nsymb,1,1);
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  write_output("dlsch_rxF_llr.m","dlsch_llr", phy_vars_ue->lte_ue_pdsch_vars_ra[0]->llr[0],coded_bits_per_codeword,1,0);
  
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  write_output("dlsch_mag1.m","dlschmag1",phy_vars_ue->lte_ue_pdsch_vars_ra[0]->dl_ch_mag0,300*nsymb,1,1);
  write_output("dlsch_mag2.m","dlschmag2",phy_vars_ue->lte_ue_pdsch_vars_ra[0]->dl_ch_magb0,300*nsymb,1,1);
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}
#endif

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void phy_reset_ue(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) {
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  // This flushes ALL DLSCH and ULSCH harq buffers of ALL connected eNBs...add the eNB_index later
  // for more flexibility
  
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  uint8_t i,j,k;
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  PHY_VARS_UE *phy_vars_ue = PHY_vars_UE_g[Mod_id][CC_id];
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  //[NUMBER_OF_CONNECTED_eNB_MAX][2];
  for(i=0;i<NUMBER_OF_CONNECTED_eNB_MAX;i++) {
    for(j=0;j<2;j++) {
      //DL HARQ
      if(phy_vars_ue->dlsch_ue[i][j]) {
	for(k=0;k<NUMBER_OF_HARQ_PID_MAX && phy_vars_ue->dlsch_ue[i][j]->harq_processes[k];k++) {
	  phy_vars_ue->dlsch_ue[i][j]->harq_processes[k]->status = SCH_IDLE;
	}
      }
    }
    //UL HARQ
    if(phy_vars_ue->ulsch_ue[i]) {
      for(k=0;k<NUMBER_OF_HARQ_PID_MAX && phy_vars_ue->ulsch_ue[i]->harq_processes[k];k++) {
	phy_vars_ue->ulsch_ue[i]->harq_processes[k]->status = SCH_IDLE;
	//Set NDIs for all UL HARQs to 0
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	//	phy_vars_ue->ulsch_ue[i]->harq_processes[k]->Ndi = 0;
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      }
    }
    
    // flush Msg3 buffer
    phy_vars_ue->ulsch_ue_Msg3_active[i] = 0;
    
  }
}

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void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) {
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  // if contention resolution fails, go back to PRACH
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  PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PRACH;
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  LOG_E(PHY,"[UE %d] Frame %d Random-access procedure fails, going back to PRACH, setting SIStatus = 0 and State RRC_IDLE\n",Mod_id,PHY_vars_UE_g[Mod_id][CC_id]->frame_rx);
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  //mac_xface->macphy_exit("");
  //  exit(-1);
}

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void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) {
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  int i;

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  LOG_I(PHY,"[UE %d][RAPROC] Frame %d Random-access procedure succeeded\n",Mod_id,PHY_vars_UE_g[Mod_id][CC_id]->frame_rx);
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  PHY_vars_UE_g[Mod_id][CC_id]->ulsch_ue_Msg3_active[eNB_index] = 0;
  PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PUSCH;
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  for (i=0;i<8;i++) { 
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    if (PHY_vars_UE_g[Mod_id][CC_id]->ulsch_ue[eNB_index]->harq_processes[i]) {
      PHY_vars_UE_g[Mod_id][CC_id]->ulsch_ue[eNB_index]->harq_processes[i]->status=IDLE;
      PHY_vars_UE_g[Mod_id][CC_id]->dlsch_ue[eNB_index][0]->harq_processes[i]->round=0;
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    }
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  }


}

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UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index) {
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  return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index]);
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}
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void process_timing_advance_rar(PHY_VARS_UE *phy_vars_ue,uint16_t timing_advance) {
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  /*
  if ((timing_advance>>10) & 1) //it is negative
    timing_advance = timing_advance - (1<<11);
  */

  if (openair_daq_vars.manual_timing_advance == 0) {
    phy_vars_ue->timing_advance = timing_advance*4;    

  }

#ifdef DEBUG_PHY_PROC  
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  LOG_I(PHY,"[UE %d] Frame %d, received (rar) timing_advance %d, HW timing advance %d\n",phy_vars_ue->Mod_id,phy_vars_ue->frame_rx, phy_vars_ue->timing_advance,openair_daq_vars.timing_advance);
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#endif

}

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void process_timing_advance(uint8_t Mod_id,uint8_t CC_id,int16_t timing_advance) {
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  //  uint32_t frame = PHY_vars_UE_g[Mod_id]->frame;
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  if ((timing_advance>>5) & 1) //it is negative
    timing_advance = timing_advance - (1<<6);
  
  if (openair_daq_vars.manual_timing_advance == 0) {
    //if ( (frame % 100) == 0) {
    //if ((timing_advance > 3) || (timing_advance < -3) )
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    PHY_vars_UE_g[Mod_id][CC_id]->timing_advance = cmax(0,(int)PHY_vars_UE_g[Mod_id][CC_id]->timing_advance+timing_advance*4);
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    //}
  }

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  LOG_I(PHY,"[UE %d] Got timing advance %d from MAC, new value %d\n",Mod_id, timing_advance, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance);
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}

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uint8_t is_SR_TXOp(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe) {
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  LOG_D(PHY,"[UE %d][SR %x] Frame %d subframe %d Checking for SR TXOp (sr_ConfigIndex %d)\n",
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	phy_vars_ue->Mod_id,phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->crnti,phy_vars_ue->frame_tx,subframe,
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      phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex);
  
  if (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex <= 4) {        // 5 ms SR period
    if ((subframe%5) == phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex)
      return(1);
  }
  else if (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex <= 14) {  // 10 ms SR period
    if (subframe==(phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex-5))
      return(1);
  }
  else if (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex <= 34) { // 20 ms SR period
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    if ((10*(phy_vars_ue->frame_tx&1)+subframe) == (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex-15))
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      return(1);
  }
  else if (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex <= 74) { // 40 ms SR period
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    if ((10*(phy_vars_ue->frame_tx&3)+subframe) == (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex-35))
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      return(1);
  }
  else if (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex <= 154) { // 80 ms SR period
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    if ((10*(phy_vars_ue->frame_tx&7)+subframe) == (phy_vars_ue->scheduling_request_config[eNB_id].sr_ConfigIndex-75))
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      return(1);
  }

  return(0);
}

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uint16_t get_n1_pucch(PHY_VARS_UE *phy_vars_ue,
		 uint8_t eNB_id,
		 uint8_t subframe,
		 uint8_t *b,
		 uint8_t SR) {
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  LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_ue->lte_frame_parms;
403
  uint8_t nCCE0,nCCE1,harq_ack1,harq_ack0;
404
  ANFBmode_t bundling_flag;
405
  uint16_t n1_pucch0=0,n1_pucch1=0;
406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425
  int subframe_offset;
  int sf;
  int M;
  // clear this, important for case where n1_pucch selection is not used

  phy_vars_ue->pucch_sel[subframe] = 0;

  if (frame_parms->frame_type == FDD ) { // FDD
    sf = (subframe<4)? subframe+6 : subframe-4;
    printf("n1_pucch_UE: subframe %d, nCCE %d\n",sf,phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->nCCE[sf]);
    if (SR == 0) 
      return(frame_parms->pucch_config_common.n1PUCCH_AN + phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->nCCE[sf]);
    else
      return(phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
  }
  else {

    bundling_flag = phy_vars_ue->pucch_config_dedicated[eNB_id].tdd_AckNackFeedbackMode;
#ifdef DEBUG_PHY_PROC
    if (bundling_flag==bundling){
426
      LOG_D(PHY,"[UE%d] Frame %d subframe %d : get_n1_pucch, bundling, SR %d/%d\n",phy_vars_ue->Mod_id,phy_vars_ue->frame_tx,subframe,SR,
427 428 429
	    phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
    }
    else {
430
      LOG_D(PHY,"[UE%d] Frame %d subframe %d : get_n1_pucch, multiplexing, SR %d/%d\n",phy_vars_ue->Mod_id,phy_vars_ue->frame_tx,subframe,SR,
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	    phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
    }
#endif
    switch (frame_parms->tdd_config) {
    case 1:  // DL:S:UL:UL:DL:DL:S:UL:UL:DL

      harq_ack0 = 2; // DTX
      M=1;
      // This is the offset for a particular subframe (2,3,4) => (0,2,4)
      if (subframe == 2) {  // ACK subframes 5 (forget 6)
	subframe_offset = 5;
	M=2;
      }
      else if (subframe == 3) {   // ACK subframe 9
	subframe_offset = 9;	
      }
      else if (subframe == 7) {  // ACK subframes 0 (forget 1)
	subframe_offset = 0;
	M=2;
      }
      else if (subframe == 8) {   // ACK subframes 4
	subframe_offset = 4;
      }
      else {
	LOG_E(PHY,"[UE%d] : Frame %d phy_procedures_lte.c: get_n1pucch, illegal subframe %d for tdd_config %d\n",
456
	    phy_vars_ue->Mod_id,phy_vars_ue->frame_tx,subframe,frame_parms->tdd_config);
457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563
	return(0);
      }


      // i=0
      nCCE0 = phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->nCCE[subframe_offset];
      n1_pucch0 = get_Np(frame_parms->N_RB_DL,nCCE0,0) + nCCE0+ frame_parms->pucch_config_common.n1PUCCH_AN; 

      // set ACK/NAK to values if not DTX
      if (phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[subframe_offset].send_harq_status>0)  // n-6 // subframe 5 is to be ACK/NAKed
	harq_ack0 = phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[subframe_offset].ack; 
      

      if (harq_ack0!=2) {  // DTX
	if (SR == 0) {  // last paragraph pg 68 from 36.213 (v8.6), m=0
	  b[0]=(M==2) ? 1-harq_ack0 : harq_ack0;
	  b[1]=harq_ack0;   // in case we use pucch format 1b (subframes 2,7)
	  phy_vars_ue->pucch_sel[subframe] = 0;
	  return(n1_pucch0);
	}
	else { // SR and only 0 or 1 ACKs (first 2 entries in Table 7.3-1 of 36.213)
	  b[0]=harq_ack0;
	  return(phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
	}
      }


      break;
    case 3:  // DL:S:UL:UL:UL:DL:DL:DL:DL:DL
      // in this configuration we have M=2 from pg 68 of 36.213 (v8.6)
      // Note: this doesn't allow using subframe 1 for PDSCH transmission!!! (i.e. SF 1 cannot be acked in SF 2)
      // set ACK/NAKs to DTX
      harq_ack1 = 2; // DTX
      harq_ack0 = 2; // DTX
      // This is the offset for a particular subframe (2,3,4) => (0,2,4)
      subframe_offset = (subframe-2)<<1;
      // i=0
      nCCE0 = phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->nCCE[5+subframe_offset];
      n1_pucch0 = get_Np(frame_parms->N_RB_DL,nCCE0,0) + nCCE0+ frame_parms->pucch_config_common.n1PUCCH_AN; 
      // i=1
      nCCE1 = phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->nCCE[(6+subframe_offset)%10];
      n1_pucch1 = get_Np(frame_parms->N_RB_DL,nCCE1,1) + nCCE1 + frame_parms->pucch_config_common.n1PUCCH_AN; 

      // set ACK/NAK to values if not DTX
      if (phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[(6+subframe_offset)%10].send_harq_status>0)  // n-6 // subframe 6 is to be ACK/NAKed
	harq_ack1 = phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[(6+subframe_offset)%10].ack;
      if (phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[5+subframe_offset].send_harq_status>0)  // n-6 // subframe 5 is to be ACK/NAKed
	harq_ack0 = phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack[5+subframe_offset].ack; 
      

      if (harq_ack1!=2) { // n-6 // subframe 6,8,0 and maybe 5,7,9 is to be ACK/NAKed
	  
	if ((bundling_flag==bundling)&&(SR == 0)) {  // This is for bundling without SR, 
	                                             // n1_pucch index takes value of smallest element in set {0,1} 
	                                             // i.e. 0 if harq_ack0 is not DTX, otherwise 1
	  b[0] = harq_ack1;
	  if (harq_ack0!=2)
	    b[0]=b[0]&harq_ack0;
	  phy_vars_ue->pucch_sel[subframe] = 1;
	  return(n1_pucch1);
	  
	}
	else if ((bundling_flag==multiplexing)&&(SR==0)) {  // Table 10.1
	  if (harq_ack0 == 2)
	    harq_ack0 = 0;
	  b[1] = harq_ack0;
	  b[0] = (harq_ack0!=harq_ack1)?0:1;
	  if ((harq_ack0 == 1) && (harq_ack1 == 0)) {
	    phy_vars_ue->pucch_sel[subframe] = 0;
	    return(n1_pucch0);
	  }
	  else {
	    phy_vars_ue->pucch_sel[subframe] = 1;
	    return(n1_pucch1);
	  }
	}
	else if (SR==1) { // SR and 0,1,or 2 ACKS, (first 3 entries in Table 7.3-1 of 36.213)
	  // this should be number of ACKs (including
	  if (harq_ack0 == 2)
	    harq_ack0 = 0;
	  b[0]= harq_ack1 | harq_ack0;
	  b[1]= harq_ack1 ^ harq_ack0;
	  return(phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
	}
      }
      else if (harq_ack0!=2) {// n-7  // subframe 5,7,9 only is to be ACK/NAKed
	if ((bundling_flag==bundling)&&(SR == 0)) {  // last paragraph pg 68 from 36.213 (v8.6), m=0
	  b[0]=harq_ack0;
	  phy_vars_ue->pucch_sel[subframe] = 0;
	  return(n1_pucch0);
	}
	else if ((bundling_flag==multiplexing)&&(SR==0)) {  // Table 10.1 with i=1 set to DTX
	  b[0] = harq_ack0;
	  b[1] = 1-b[0];
	  phy_vars_ue->pucch_sel[subframe] = 0;
	  return(n1_pucch0);
	}
	else if (SR==1) { // SR and only 0 or 1 ACKs (first 2 entries in Table 7.3-1 of 36.213)
	  b[0]=harq_ack0;
	  b[1]=b[0];
	  return(phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex);
	}
      }
      break;

    }  // switch tdd_config     
  }
564
  LOG_E(PHY,"[UE%d] : Frame %d phy_procedures_lte.c: get_n1pucch, exit without proper return\n",phy_vars_ue->frame_tx);
565 566 567 568 569 570
  return(-1);
}


#ifdef EMOS
/*
571 572
void phy_procedures_emos_UE_TX(uint8_t next_slot,uint8_t eNB_id) {
  uint8_t harq_pid;
573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605
  

  if (next_slot%2==0) {      
    // get harq_pid from subframe relationship
    harq_pid = subframe2harq_pid(&phy_vars_ue->lte_frame_parms,phy_vars_ue->frame,(next_slot>>1));    
    if (harq_pid==255) {
      LOG_E(PHY,"[UE%d] Frame %d : FATAL ERROR: illegal harq_pid, returning\n",
	  0,phy_vars_ue->frame);
      return;
    }

    if (ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag == 1) {
      emos_dump_UE.uci_cnt[next_slot>>1] = 1;
      memcpy(emos_dump_UE.UCI_data[0][next_slot>>1].o,ulsch_ue[eNB_id]->o,MAX_CQI_BITS*sizeof(char));
      emos_dump_UE.UCI_data[0][next_slot>>1].O = ulsch_ue[eNB_id]->O;
      memcpy(emos_dump_UE.UCI_data[0][next_slot>>1].o_RI,ulsch_ue[eNB_id]->o_RI,2*sizeof(char));
      emos_dump_UE.UCI_data[0][next_slot>>1].O_RI = ulsch_ue[eNB_id]->O_RI;
      memcpy(emos_dump_UE.UCI_data[0][next_slot>>1].o_ACK,ulsch_ue[eNB_id]->o_ACK,4*sizeof(char));
      emos_dump_UE.UCI_data[0][next_slot>>1].O_ACK = ulsch_ue[eNB_id]->harq_processes[harq_pid]->O_ACK;
    }
    else {
      emos_dump_UE.uci_cnt[next_slot>>1] = 0;
    }
  }
}
*/
#endif

int dummy_tx_buffer[3840*4] __attribute__((aligned(16)));
#ifndef OPENAIR2
  PRACH_RESOURCES_t prach_resources_local;
#endif

606
void phy_procedures_UE_TX(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode,relaying_type_t r_type) {
607 608
  
  //  int i_d;
609 610
  uint16_t first_rb, nb_rb;
  uint8_t harq_pid;
611
  unsigned int input_buffer_length;
612
  unsigned int aa;
613 614 615
  uint8_t Msg3_flag=0;
  uint8_t pucch_ack_payload[2];
  uint8_t n1_pucch;
616 617
  ANFBmode_t bundling_flag;
  PUCCH_FMT_t format;
618 619
  uint8_t SR_payload;
  int32_t prach_power;
620
  uint8_t nsymb;
621
  LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_ue->lte_frame_parms;
622 623 624 625
  uint8_t generate_ul_signal = 0;
  uint8_t ack_status=0;
  int8_t Po_PUCCH;
  int32_t ulsch_start=0;
626
#ifdef EXMIMO
627
  int overflow=0;
628 629
  int k,l;
#endif
630 631 632 633 634
  int slot_tx = phy_vars_ue->slot_tx;
  int subframe_tx = phy_vars_ue->slot_tx>>1;
  int frame_tx = phy_vars_ue->frame_tx;
  int Mod_id = phy_vars_ue->Mod_id;
  int CC_id = phy_vars_ue->CC_id;
635 636 637
#ifndef OPENAIR2
  int i;
#endif
638 639

  vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN);
640

641
  start_meas(&phy_vars_ue->phy_proc_tx);
642 643 644 645 646

#ifdef EMOS
  //phy_procedures_emos_UE_TX(next_slot);
#endif

647
  if ((slot_tx%2)==0) {
648 649 650 651
    phy_vars_ue->tx_power_dBm=-127;

    if ((abstraction_flag==0)) {      
      for (aa=0;aa<frame_parms->nb_antennas_tx;aa++){
652
	memset(&phy_vars_ue->lte_ue_common_vars.txdataF[aa][subframe_tx*frame_parms->ofdm_symbol_size*frame_parms->symbols_per_tti],
653 654
	       0,
	       frame_parms->ofdm_symbol_size*frame_parms->symbols_per_tti*sizeof(int32_t));
655 656 657 658 659 660
      }
    }

    if (phy_vars_ue->UE_mode[eNB_id] != PRACH) {
    /*
#ifdef DEBUG_PHY_PROC
661
      LOG_D(PHY,"[UE  %d] Frame %d, slot %d: Generating SRS\n",Mod_id,phy_vars_ue->frame,slot_tx);
662 663 664
#endif
      if (abstraction_flag == 0) {
#ifdef OFDMA_ULSCH
665
	generate_srs_tx(phy_vars_ue,eNB_id,AMP,subframe_tx);
666
#else
667
	generate_srs_tx(phy_vars_ue,eNB_id,AMP,subframe_tx);
668 669 670 671 672
#endif
      }
      
#ifdef PHY_ABSTRACTION
      else {
673
	generate_srs_tx_emul(phy_vars_ue,subframe_tx);
674 675 676 677 678
      }
#endif
    */
      // get harq_pid from subframe relationship
      harq_pid = subframe2harq_pid(&phy_vars_ue->lte_frame_parms,
679 680
				   frame_tx,
				   subframe_tx);
681 682 683 684
      

#ifdef OPENAIR2
      if ((phy_vars_ue->ulsch_ue_Msg3_active[eNB_id] == 1) && 
685 686
	  (phy_vars_ue->ulsch_ue_Msg3_frame[eNB_id] == frame_tx) && 
	  (phy_vars_ue->ulsch_ue_Msg3_subframe[eNB_id] == subframe_tx)) { // Initial Transmission of Msg3
687 688 689 690 691 692 693 694
	
	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
	if (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->round==0)
	  generate_ue_ulsch_params_from_rar(phy_vars_ue,
					    eNB_id);

	phy_vars_ue->ulsch_ue[eNB_id]->power_offset = 14;
	LOG_I(PHY,"[UE  %d][RAPROC] Frame %d: Setting Msg3_flag in subframe %d, for harq_pid %d\n",
695 696 697
	    Mod_id,
	    frame_tx,
	    subframe_tx,
698 699 700 701 702 703 704
	    harq_pid);
	Msg3_flag = 1;
      }
      else {
	
	if (harq_pid==255) {
	  LOG_E(PHY,"[UE%d] Frame %d ulsch_decoding.c: FATAL ERROR: illegal harq_pid, returning\n",
705
	      Mod_id,frame_tx);
706 707
	  mac_xface->macphy_exit("");
          vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT);
708
	  stop_meas(&phy_vars_ue->phy_proc_tx);
709 710 711 712 713 714 715 716 717
	  return;
	}
	Msg3_flag=0;
      }
#endif
      
      if (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag == 1) {
	
	generate_ul_signal = 1;
718 719
	// FK 20140908: the power control cannot be done here, since we do not have the spectral efficiency yet. this is only done in ulsch_encoding
	/*
720
#ifdef OPENAIR2
721
	pusch_power_cntl(phy_vars_ue,subframe_tx,eNB_id,1, abstraction_flag);
722 723 724 725
	phy_vars_ue->tx_power_dBm = phy_vars_ue->ulsch_ue[eNB_id]->Po_PUSCH;
#else
	phy_vars_ue->tx_power_dBm = UE_TX_POWER;
#endif
726 727
	phy_vars_ue->tx_total_RE = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->nb_rb*12;

728
	LOG_D(PHY,"[UE  %d][PUSCH %d] Frame %d subframe %d harq pid %d, Po_PUSCH : %d dBm\n",
729
	      Mod_id,harq_pid,frame_tx,subframe_tx,harq_pid, phy_vars_ue->tx_power_dBm);	
730
	*/
731 732 733 734 735 736

	// deactivate service request
	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
	
	ack_status = get_ack(&phy_vars_ue->lte_frame_parms,
			     phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack,
737
			     subframe_tx,
738 739 740 741 742 743 744 745 746 747 748 749 750
			     phy_vars_ue->ulsch_ue[eNB_id]->o_ACK);
	
	first_rb = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->first_rb;
	nb_rb = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->nb_rb;
	
	
	//frame_parms->pusch_config_c ommon.ul_ReferenceSignalsPUSCH.cyclicShift = 0;
	
	//frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.nPRS[20] = 0;
	
	
	
#ifdef DEBUG_PHY_PROC
751
	LOG_I(PHY,"[UE  %d][PUSCH %d] Frame %d subframe %d Generating PUSCH : first_rb %d, nb_rb %d, round %d, mcs %d, rv %d, cyclic_shift %d (cyclic_shift_common %d,n_DMRS2 %d,n_PRS %d), ACK (%d,%d), O_ACK %d\n",
752
	      Mod_id,harq_pid,frame_tx,subframe_tx,
753 754 755 756 757 758
	      first_rb,nb_rb,
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->round,
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->mcs,
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->rvidx,
	      (frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift+
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->n_DMRS2+
759
	      frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.nPRS[slot_tx])%12,
760 761
	      frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift,
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->n_DMRS2,
762
	      frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.nPRS[slot_tx],
763 764 765 766
	      phy_vars_ue->ulsch_ue[eNB_id]->o_ACK[0],phy_vars_ue->ulsch_ue[eNB_id]->o_ACK[1],
	      phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->O_ACK);
	if (ack_status > 0) {
	  LOG_I(PHY,"[UE  %d][PDSCH %x] Frame %d subframe %d Generating ACK (%d,%d) for %d bits on PUSCH\n",
767
		Mod_id,
768
		phy_vars_ue->ulsch_ue[eNB_id]->rnti,
769
		frame_tx,subframe_tx,
770 771 772 773 774 775 776
		phy_vars_ue->ulsch_ue[eNB_id]->o_ACK[0],phy_vars_ue->ulsch_ue[eNB_id]->o_ACK[1],
		phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->O_ACK);
	}
#endif
	

	//#ifdef DEBUG_PHY_PROC      
777
	//	debug_LOG_D(PHY,"[UE  %d] Frame %d, Subframe %d ulsch harq_pid %d : O %d, O_ACK %d, O_RI %d, TBS %d\n",Mod_id,phy_vars_ue->frame,subframe_tx,harq_pid,phy_vars_ue->ulsch_ue[eNB_id]->O,phy_vars_ue->ulsch_ue[eNB_id]->O_ACK,phy_vars_ue->ulsch_ue[eNB_id]->O_RI,phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TBS);
778 779
	//#endif
	if (Msg3_flag == 1) {
780
	  LOG_I(PHY,"[UE  %d][RAPROC] Frame %d, Subframe %d next slot %d Generating (RRCConnectionRequest) Msg3 (nb_rb %d, first_rb %d, round %d, rvidx %d) Msg3: %x.%x.%x|%x.%x.%x.%x.%x.%x\n",Mod_id,frame_tx,subframe_tx, slot_tx, 
781 782
		phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->nb_rb,
		phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->first_rb,
783
		phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->round,
784 785 786 787 788 789 790 791 792 793 794
		phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->rvidx,
		phy_vars_ue->prach_resources[eNB_id]->Msg3[0],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[1],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[2],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[3],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[4],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[5],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[6],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[7],
		phy_vars_ue->prach_resources[eNB_id]->Msg3[8]);

795
	  start_meas(&phy_vars_ue->ulsch_encoding_stats);	      
796 797 798 799 800 801 802 803 804
	  if (abstraction_flag==0) {
	    if (ulsch_encoding(phy_vars_ue->prach_resources[eNB_id]->Msg3,
			       phy_vars_ue,
			       harq_pid,
			       eNB_id,
			       phy_vars_ue->transmission_mode[eNB_id],0,0)!=0) {
	      LOG_E(PHY,"ulsch_coding.c: FATAL ERROR: returning\n");
	      mac_xface->macphy_exit("");
              vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT);
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	      stop_meas(&phy_vars_ue->phy_proc_tx);
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	      return;
	    }
	  }
#ifdef PHY_ABSTRACTION
	  else {
	    ulsch_encoding_emul(phy_vars_ue->prach_resources[eNB_id]->Msg3,phy_vars_ue,eNB_id,harq_pid,0);
	  }
#endif
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	  stop_meas(&phy_vars_ue->ulsch_encoding_stats);	      

816 817 818

#ifdef OPENAIR2
	  // signal MAC that Msg3 was sent
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	  mac_xface->Msg3_transmitted(Mod_id,
				      CC_id,
				      frame_tx,
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				      eNB_id);
#endif
	}      
	else {
	  input_buffer_length = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TBS/8;
	 
#ifdef OPENAIR2
829
	  //  LOG_D(PHY,"[UE  %d] ULSCH : Searching for MAC SDUs\n",Mod_id);
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	  if (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->round==0) { 
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	    //if (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->calibration_flag == 0) {
	    access_mode=SCHEDULED_ACCESS;
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	    mac_xface->ue_get_sdu(Mod_id,
				  CC_id,
				  frame_tx,
				  subframe_tx,
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				  eNB_id,
				  ulsch_input_buffer,
				  input_buffer_length,
				  &access_mode);
	    
	    //}
	    /*
	    else {
	      // Get calibration information from TDD procedures
	      LOG_D(PHY,"[UE %d] Frame %d, subframe %d : ULSCH: Getting TDD Auto-Calibration information\n",
847
		    Mod_id,phy_vars_ue->frame,subframe_tx);
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	      for (i=0;i<input_buffer_length;i++)
		ulsch_input_buffer[i]= i;
	      
	    }
	    */
	  }
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#ifdef DEBUG_PHY_PROC
#ifdef DEBUG_ULSCH
856
	  LOG_I(PHY,"[UE] Frame %d, subframe %d : ULSCH SDU (TX harq_pid %d)  (%d bytes) : \n",frame_tx,subframe_tx,harq_pid, phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TBS>>3);
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	  for (i=0;i<phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TBS>>3;i++) 
	    LOG_T(PHY,"%x.",ulsch_input_buffer[i]);
	  LOG_T(PHY,"\n");
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#endif
#endif
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#else //OPENAIR2
      // the following lines were necessary for the calibration in CROWN
      /*
      if (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->calibration_flag == 0) {
          for (i=0;i<input_buffer_length;i++) 
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              ulsch_input_buffer[i]= (uint8_t)(taus()&0xff);
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	  }
	  else {
          // Get calibration information from TDD procedures
      }
      */

	  for (i=0;i<input_buffer_length;i++) 
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	    ulsch_input_buffer[i]= (uint8_t)(taus()&0xff);
876 877 878
	  
      // the following lines were necessary for the collaborative UL in PUCCO
	  /*
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	  memset(phy_vars_ue->ulsch_ue[eNB_id]->o    ,0,MAX_CQI_BYTES*sizeof(uint8_t));
	  memset(phy_vars_ue->ulsch_ue[eNB_id]->o_RI ,0,2*sizeof(uint8_t));
	  memset(phy_vars_ue->ulsch_ue[eNB_id]->o_ACK,0,4*sizeof(uint8_t));
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	  for (i=0;i<input_buffer_length;i++)
	    ulsch_input_buffer[i]= i;
	  */

#endif //OPENAIR2
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	  start_meas(&phy_vars_ue->ulsch_encoding_stats);	      
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	  if (abstraction_flag==0) {
	    /*
	    if (phy_vars_ue->frame%100==0) {
	      LOG_I(PHY,"Encoding ulsch\n");
	    }
	    */
	    if (ulsch_encoding(ulsch_input_buffer,
			       phy_vars_ue,
			       harq_pid,
			       eNB_id,
			       phy_vars_ue->transmission_mode[eNB_id],0,
			       0)!=0) {  //  Nbundled, to be updated!!!!
	      LOG_E(PHY,"ulsch_coding.c: FATAL ERROR: returning\n");
              vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT);
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	      stop_meas(&phy_vars_ue->phy_proc_tx);
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	      return;
	    }
	  }
#ifdef PHY_ABSTRACTION
	  else {
	    ulsch_encoding_emul(ulsch_input_buffer,phy_vars_ue,eNB_id,harq_pid,0);
	  }
#endif
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	  stop_meas(&phy_vars_ue->ulsch_encoding_stats);	      
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	}
	if (abstraction_flag == 0) {
#ifdef OPENAIR2
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	  pusch_power_cntl(phy_vars_ue,subframe_tx,eNB_id,1, abstraction_flag);
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	  phy_vars_ue->tx_power_dBm = phy_vars_ue->ulsch_ue[eNB_id]->Po_PUSCH;
#else
	  phy_vars_ue->tx_power_dBm = UE_TX_POWER;
#endif
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	  phy_vars_ue->tx_total_RE = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->nb_rb*12;

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	  LOG_I(PHY,"[UE  %d][PUSCH %d] Frame %d subframe %d, generating PUSCH, Po_PUSCH: %d dBm, amp %d\n",
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		Mod_id,harq_pid,frame_tx,subframe_tx,phy_vars_ue->tx_power_dBm,
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#ifdef EXMIMO
		get_tx_amp(phy_vars_ue->tx_power_dBm,phy_vars_ue->tx_power_max_dBm)
#else
		AMP
#endif
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		);    
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	  start_meas(&phy_vars_ue->ulsch_modulation_stats);	      	      	  
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	  ulsch_modulation(phy_vars_ue->lte_ue_common_vars.txdataF,
#ifdef EXMIMO                       
                       get_tx_amp(phy_vars_ue->tx_power_dBm,phy_vars_ue->tx_power_max_dBm),
#else
                       AMP,
#endif
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                       frame_tx,
                       subframe_tx,
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                       &phy_vars_ue->lte_frame_parms,
                       phy_vars_ue->ulsch_ue[eNB_id]);

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#ifdef EXMIMO
	  for (aa=0; aa<1/*frame_parms->nb_antennas_tx*/; aa++)
	    generate_drs_pusch(phy_vars_ue,eNB_id,get_tx_amp(phy_vars_ue->tx_power_dBm,phy_vars_ue->tx_power_max_dBm),subframe_tx,first_rb,nb_rb,aa);
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#else
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	  for (aa=0; aa<1/*frame_parms->nb_antennas_tx*/; aa++)
	    generate_drs_pusch(phy_vars_ue,eNB_id,AMP,subframe_tx,first_rb,nb_rb,aa);
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#endif
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	  stop_meas(&phy_vars_ue->ulsch_modulation_stats);	      	      	  
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	}
952

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	if (abstraction_flag==1) {
	  // clear SR
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	  phy_vars_ue->sr[subframe_tx]=0;
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	}
      } // ULSCH is active
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#ifdef PUCCH
      else if (phy_vars_ue->UE_mode[eNB_id] == PUSCH){  // check if we need to use PUCCH 1a/1b
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	//      debug_LOG_D(PHY,"[UE%d] Frame %d, subframe %d: Checking for PUCCH 1a/1b\n",Mod_id,frame_tx,subframe_tx);
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	bundling_flag = phy_vars_ue->pucch_config_dedicated[eNB_id].tdd_AckNackFeedbackMode;
	
	if ((frame_parms->frame_type==FDD) || 
	    (bundling_flag==bundling)    || 
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	    ((frame_parms->frame_type==TDD)&&(frame_parms->tdd_config==1)&&((slot_tx!=4)||(slot_tx!=14)))) {
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	  format = pucch_format1a;
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	  LOG_D(PHY,"[UE] PUCCH 1a\n");
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	}
	else {
	  format = pucch_format1b;
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	  LOG_D(PHY,"[UE] PUCCH 1b\n");
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	}
	
	// Check for SR and do ACK/NACK accordingly
976
	if (is_SR_TXOp(phy_vars_ue,eNB_id,subframe_tx)==1) {
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	  LOG_D(PHY,"[UE %d][SR %x] Frame %d subframe %d: got SR_TXOp, Checking for SR for PUSCH from MAC\n",
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	 	Mod_id,phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->crnti,frame_tx,subframe_tx);
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#ifdef OPENAIR2
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	  SR_payload = mac_xface->ue_get_SR(Mod_id,
					    CC_id,
					    frame_tx,
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					    eNB_id,
					    phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->crnti,
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					    subframe_tx); // subframe used for meas gap
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#else
	  SR_payload = 1;
#endif
	 
	  if (SR_payload>0) {
	    generate_ul_signal = 1;
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992
	    LOG_D(PHY,"[UE %d][SR %x] Frame %d subframe %d got the SR for PUSCH is %d\n",
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		  Mod_id,phy_vars_ue->lte_ue_pdcch_vars[eNB_id]->crnti,frame_tx,subframe_tx,SR_payload);
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	  }
	  else {
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	    phy_vars_ue->sr[subframe_tx]=0;
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	  }
	}
	else
	  SR_payload=0;
	
	if (get_ack(&phy_vars_ue->lte_frame_parms,
		    phy_vars_ue->dlsch_ue[eNB_id][0]->harq_ack,
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		    subframe_tx,pucch_ack_payload) > 0) {
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	  // we need to transmit ACK/NAK in this subframe
	  
	  generate_ul_signal = 1;
	  
	  n1_pucch = get_n1_pucch(phy_vars_ue,
				  eNB_id,
1011
				  subframe_tx,
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				  pucch_ack_payload,
				  SR_payload); 

#ifdef OPENAIR2
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	    Po_PUCCH = pucch_power_cntl(phy_vars_ue,subframe_tx,eNB_id,format);
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	    phy_vars_ue->tx_power_dBm = Po_PUCCH;
#else
	    phy_vars_ue->tx_power_dBm = UE_TX_POWER;
#endif
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	    phy_vars_ue->tx_total_RE = 12;
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	    if (SR_payload>0) {
	      LOG_I(PHY,"[UE  %d][SR %x] Frame %d subframe %d Generating PUCCH 1a/1b (with SR for PUSCH), n1_pucch %d, Po_PUCCH, amp %d\n",
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		    Mod_id, 
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		    phy_vars_ue->dlsch_ue[eNB_id][0]->rnti,
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		    frame_tx, subframe_tx,
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		    phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex,
		    Po_PUCCH,
#ifdef EXMIMO
		    get_tx_amp(Po_PUCCH,phy_vars_ue->tx_power_max_dBm)
#else
			AMP
#endif
);
	    }
	    else {
	      LOG_I(PHY,"[UE  %d][PDSCH %x] Frame %d subframe %d Generating PUCCH 1a/1b, n1_pucch %d, b[0]=%d,b[1]=%d (SR_Payload %d), Po_PUCCH %d, amp %d\n",
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		    Mod_id, 
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		    phy_vars_ue->dlsch_ue[eNB_id][0]->rnti,
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		    frame_tx, subframe_tx,
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		    n1_pucch,pucch_ack_payload[0],pucch_ack_payload[1],SR_payload,
		    Po_PUCCH,
#ifdef EXMIMO
		    get_tx_amp(Po_PUCCH,phy_vars_ue->tx_power_max_dBm)
#else
			AMP
#endif
			);
	    }

	  if (abstraction_flag == 0) {

	    generate_pucch(phy_vars_ue->lte_ue_common_vars.txdataF,
			   &phy_vars_ue->lte_frame_parms,
			   phy_vars_ue->ncs_cell,
			   format,
			   &phy_vars_ue->pucch_config_dedicated[eNB_id],
			   n1_pucch,
			   0,  // n2_pucch
			   1,  // shortened format
			   pucch_ack_payload,
#ifdef EXMIMO
			   get_tx_amp(Po_PUCCH,phy_vars_ue->tx_power_max_dBm),
#else
			   AMP,
#endif
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			   subframe_tx);
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	  }
	  else {
#ifdef PHY_ABSTRACTION
	    LOG_D(PHY,"Calling generate_pucch_emul ... (ACK %d %d, SR %d)\n",pucch_ack_payload[0],pucch_ack_payload[1],SR_payload);
	    generate_pucch_emul(phy_vars_ue,
				format,
				phy_vars_ue->lte_frame_parms.pucch_config_common.nCS_AN,
				pucch_ack_payload,
				SR_payload,
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				subframe_tx);
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#endif
	  }
	}
	else if (SR_payload==1) { // no ACK/NAK but SR is triggered by MAC

#ifdef OPENAIR2
1086
	  Po_PUCCH = pucch_power_cntl(phy_vars_ue,subframe_tx,eNB_id,pucch_format1);
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	  phy_vars_ue->tx_power_dBm = Po_PUCCH;
#else
	  phy_vars_ue->tx_power_dBm = UE_TX_POWER;
#endif
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	  phy_vars_ue->tx_total_RE = 12;
1092 1093

	  LOG_I(PHY,"[UE  %d][SR %x] Frame %d subframe %d Generating PUCCH 1 (SR for PUSCH), n1_pucch %d, Po_PUCCH %d\n",
1094
		Mod_id, 
1095
		phy_vars_ue->dlsch_ue[eNB_id][0]->rnti,
1096
		frame_tx, subframe_tx,
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		phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex,
		Po_PUCCH);
	  
	  if (abstraction_flag == 0) {

	    generate_pucch(phy_vars_ue->lte_ue_common_vars.txdataF,
			   &phy_vars_ue->lte_frame_parms,
			   phy_vars_ue->ncs_cell,
			   pucch_format1,
			   &phy_vars_ue->pucch_config_dedicated[eNB_id],
			   phy_vars_ue->scheduling_request_config[eNB_id].sr_PUCCH_ResourceIndex,
			   0,  // n2_pucch
			   1,  // shortened format
			   pucch_ack_payload,  // this is ignored anyway, we just need a pointer
#ifdef EXMIMO
			   get_tx_amp(Po_PUCCH,phy_vars_ue->tx_power_max_dBm),
#else
			   AMP,
#endif
1116
			   subframe_tx);	 
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	  }
	  else {
	    LOG_D(PHY,"Calling generate_pucch_emul ...\n");
	    generate_pucch_emul(phy_vars_ue,
				pucch_format1,
				phy_vars_ue->lte_frame_parms.pucch_config_common.nCS_AN,
				pucch_ack_payload,
				SR_payload,
1125
				subframe_tx);
1126 1127 1128 1129 1130
	  }
	}
      }
#endif  // PUCCH

1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182
#ifdef CBA
      if ((phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_cba_scheduling_flag >= 1) && 
	  (phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->status == CBA_ACTIVE)) {
	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->subframe_scheduling_flag=0; //-=1
	//	phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->status= IDLE; 
	first_rb = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->first_rb;
	nb_rb = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->nb_rb;
	//cba_mcs=phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->mcs;
	input_buffer_length = phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->TBS/8;
	access_mode=CBA_ACCESS;
	
	LOG_I(PHY,"[UE %d] Frame %d, subframe %d: CBA num dci %d\n", 
	      Mod_id,frame_tx,subframe_tx,
	      phy_vars_ue->ulsch_ue[eNB_id]->num_cba_dci[subframe_tx]);
	
	mac_xface->ue_get_sdu(Mod_id,
			      CC_id,
			      frame_tx,
			      subframe_tx,
			      eNB_id,
			      ulsch_input_buffer,
			      input_buffer_length,
			      &access_mode);
	
	phy_vars_ue->ulsch_ue[eNB_id]->num_cba_dci[subframe_tx]=0;
	
	if (access_mode > UNKNOWN_ACCESS){

	  if (abstraction_flag==0) {
	    if (ulsch_encoding(ulsch_input_buffer,
			       phy_vars_ue,
			       harq_pid,
			       eNB_id,
			       phy_vars_ue->transmission_mode[eNB_id],0,
			       0)!=0) {  //  Nbundled, to be updated!!!!
	      LOG_E(PHY,"ulsch_coding.c: FATAL ERROR: returning\n");
	      return;
	    }
	  }
#ifdef PHY_ABSTRACTION
	  else {
	    ulsch_encoding_emul(ulsch_input_buffer,phy_vars_ue,eNB_id,harq_pid,0);
	  }
#endif
	} else {
	  phy_vars_ue->ulsch_ue[eNB_id]->harq_processes[harq_pid]->status= IDLE; 
	  //reset_cba_uci(phy_vars_ue->ulsch_ue[eNB_id]->o);
	  LOG_N(PHY,"[UE %d] Frame %d, subframe %d: CBA transmission cancelled or postponed\n",
		Mod_id, frame_tx,subframe_tx);
	}
      }
#endif // end CBA
1183 1184

      if (abstraction_flag == 0) {
1185 1186
	nsymb = (frame_parms->Ncp == 0) ? 14 : 12;
	
1187
#ifdef EXMIMO //this is the EXPRESS MIMO case
1188
	ulsch_start = (phy_vars_ue->rx_offset+subframe_tx*frame_parms->samples_per_tti-openair_daq_vars.timing_advance-phy_vars_ue->timing_advance-phy_vars_ue->N_TA_offset+5)%(LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*frame_parms->samples_per_tti);
1189
#else //this is the normal case
1190
	ulsch_start = (frame_parms->samples_per_tti*subframe_tx)-phy_vars_ue->N_TA_offset;
1191
#endif //else EXMIMO
1192 1193
	if (generate_ul_signal == 1 ) {
	  
1194

1195 1196 1197
	  
	  start_meas(&phy_vars_ue->ofdm_mod_stats);	      	      	  
	  for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
1198
	    if (frame_parms->Ncp == 1) 
1199
	      PHY_ofdm_mod(&phy_vars_ue->lte_ue_common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
#ifdef EXMIMO
			   dummy_tx_buffer, 
#else
			   &phy_vars_ue->lte_ue_common_vars.txdata[aa][ulsch_start],
#endif
			   frame_parms->log2_symbol_size,
			   nsymb,
			   frame_parms->nb_prefix_samples,
			   frame_parms->twiddle_ifft,
			   frame_parms->rev,
			   CYCLIC_PREFIX);
	    else
1212
	      normal_prefix_mod(&phy_vars_ue->lte_ue_common_vars.txdataF[aa][subframe_tx*nsymb*frame_parms->ofdm_symbol_size],
1213 1214 1215 1216 1217 1218 1219
#ifdef EXMIMO
				dummy_tx_buffer, 
#else
				&phy_vars_ue->lte_ue_common_vars.txdata[aa][ulsch_start],
#endif
				nsymb,
				&phy_vars_ue->lte_frame_parms);
1220
	    
1221
	    /*
1222
	      if (subframe_tx == 8) {
1223
	      printf("Symbol 0 %p (offset %d) base %p\n", 
1224 1225 1226
	      &phy_vars_ue->lte_ue_common_vars.txdataF[0][nsymb*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*subframe],
	      nsymb*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*subframe,
	      phy_vars_ue->lte_ue_common_vars.txdataF[0]);
1227
	      write_output("txsigF8.m","txsF8", &phy_vars_ue->lte_ue_common_vars.txdataF[0][nsymb*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*subframe],
1228
	      phy_vars_ue->lte_frame_parms.ofdm_symbol_size*nsymb,1,1);	      
1229
	      write_output("txsig8.m","txs8", &phy_vars_ue->lte_ue_common_vars.txdata[0][phy_vars_ue->lte_frame_parms.samples_per_tti*subframe],
1230 1231
	      phy_vars_ue->lte_frame_parms.samples_per_tti,1,1);	      
	      }
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	    */
#ifndef OFDMA_ULSCH
#ifdef EXMIMO
	    apply_7_5_kHz(phy_vars_ue,dummy_tx_buffer,0);
	    apply_7_5_kHz(phy_vars_ue,dummy_tx_buffer,1);
#else
	    apply_7_5_kHz(phy_vars_ue,&phy_vars_ue->lte_ue_common_vars.txdata[aa][ulsch_start],0);
	    apply_7_5_kHz(phy_vars_ue,&phy_vars_ue->lte_ue_common_vars.txdata[aa][ulsch_start],1);
#endif
	    /*
1242
	      if (subframe_tx == 8) {
1243
	      write_output("txsig8_mod.m","txs8_mod", &phy_vars_ue->lte_ue_common_vars.txdata[0][phy_vars_ue->lte_frame_parms.samples_per_tti*subframe],
1244 1245
	      phy_vars_ue->lte_frame_parms.samples_per_tti,1,1);	      
	      }
1246 1247
	    */
#endif
1248
	    
1249 1250
#ifdef EXMIMO
	    overflow = ulsch_start - 9*frame_parms->samples_per_tti;
1251
	    //if ((slot_tx==4) && (aa==0)) printf("ulsch_start %d, overflow %d\n",ulsch_start,overflow);
1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262
	    for (k=ulsch_start,l=0; k<cmin(frame_parms->samples_per_tti*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,ulsch_start+frame_parms->samples_per_tti); k++,l++)
	      {
		((short*)phy_vars_ue->lte_ue_common_vars.txdata[aa])[2*k] = ((short*)dummy_tx_buffer)[2*l]<<4;
		((short*)phy_vars_ue->lte_ue_common_vars.txdata[aa])[2*k+1] = ((short*)dummy_tx_buffer)[2*l+1]<<4;
	      }
	    for (k=0;k<overflow;k++,l++)
	      {
		((short*)phy_vars_ue->lte_ue_common_vars.txdata[aa])[2*k] = ((short*)dummy_tx_buffer)[2*l]<<4;
		((short*)phy_vars_ue->lte_ue_common_vars.txdata[aa])[2*k+1] = ((short*)dummy_tx_buffer)[2*l+1]<<4;
	      }
#endif
1263
	    
1264
	  } //nb_antennas_tx
1265
	  stop_meas(&phy_vars_ue->ofdm_mod_stats);	      	      	  
1266
	} // generate_ul_signal == 1
1267 1268 1269 1270 1271
	else {  // no uplink so clear signal buffer instead
	  for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
	    memset(&phy_vars_ue->lte_ue_common_vars.txdata[aa][ulsch_start],0,frame_parms->samples_per_tti<<2);
	  }
	}
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      } 
    } // mode != PRACH
1274 1275
    //  }// slot_tx is even
    //  else {  // slot_tx is odd, do the PRACH here
1276 1277 1278 1279 1280 1281 1282
 
#ifdef OPENAIR2 
    if ((phy_vars_ue->UE_mode[eNB_id] == PRACH) && (phy_vars_ue->lte_frame_parms.prach_config_common.prach_Config_enabled==1)) {
#else
    if (1) {
#endif
      // check if we have PRACH opportunity
1283 1284
      if (is_prach_subframe(&phy_vars_ue->lte_frame_parms,frame_tx,subframe_tx)) {
	LOG_D(PHY,"UE %d: Frame %d, SF %d Clearing generate_prach\n",Mod_id,frame_tx,subframe_tx);
1285 1286 1287 1288
	phy_vars_ue->generate_prach=0;
#ifdef OPENAIR2
	// ask L2 for RACH transport
	if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ){
1289 1290 1291
	  phy_vars_ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(Mod_id,
									CC_id,
									frame_tx,
1292
									eNB_id,
1293 1294
									subframe_tx);
	  LOG_D(PHY,"Got prach_resources for eNB %d address %d, RRCCommon %d\n",eNB_id,phy_vars_ue->prach_resources[eNB_id],UE_mac_inst[Mod_id].radioResourceConfigCommon);
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	}
#endif
	if (phy_vars_ue->prach_resources[eNB_id]!=NULL) {
	  
	  phy_vars_ue->generate_prach=1;
	  phy_vars_ue->prach_cnt=0;
#ifdef SMBV
      phy_vars_ue->prach_resources[eNB_id]->ra_PreambleIndex = 19;
#endif
#ifdef OAI_EMU
	  phy_vars_ue->prach_PreambleIndex=phy_vars_ue->prach_resources[eNB_id]->ra_PreambleIndex; 
#endif
	  if (abstraction_flag == 0) {
	    LOG_D(PHY,"[UE  %d][RAPROC] Frame %d, Subframe %d : Generating PRACH, preamble %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n",
1309 1310 1311
		  Mod_id,
		  frame_tx,
		  subframe_tx,
1312 1313 1314 1315 1316 1317
		  phy_vars_ue->prach_resources[eNB_id]->ra_PreambleIndex,
		  phy_vars_ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER,
		  phy_vars_ue->prach_resources[eNB_id]->ra_TDD_map_index,
		  phy_vars_ue->prach_resources[eNB_id]->ra_RNTI);

#ifdef OPENAIR2
1318
	    phy_vars_ue->tx_power_dBm = phy_vars_ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_PL(Mod_id,CC_id,eNB_id);
1319 1320 1321 1322
#else
	    phy_vars_ue->tx_power_dBm = UE_TX_POWER;
#endif

1323 1324
	    phy_vars_ue->tx_total_RE = 96;

1325 1326 1327 1328 1329
#ifdef EXMIMO
	    phy_vars_ue->lte_ue_prach_vars[eNB_id]->amp = get_tx_amp(phy_vars_ue->tx_power_dBm,phy_vars_ue->tx_power_max_dBm);
#else
	    phy_vars_ue->lte_ue_prach_vars[eNB_id]->amp = AMP;
#endif
1330 1331
	    //	    start_meas(&phy_vars_ue->tx_prach);
	    vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN);
1332
	    prach_power = generate_prach(phy_vars_ue,eNB_id,subframe_tx,frame_tx);
1333 1334
	    vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT);
	    //	    stop_meas(&phy_vars_ue->tx_prach);
1335
	    LOG_D(PHY,"[UE  %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n",
1336 1337
		  Mod_id,
		  get_PL(Mod_id,CC_id,eNB_id),
1338 1339 1340 1341 1342
		  phy_vars_ue->tx_power_dBm,
		  dB_fixed(prach_power),
		  phy_vars_ue->lte_ue_prach_vars[eNB_id]->amp);
	  }
	  else {
1343 1344
	    UE_transport_info[Mod_id][CC_id].cntl.prach_flag=1;
	    UE_transport_info[Mod_id][CC_id].cntl.prach_id=phy_vars_ue->prach_resources[eNB_id]->ra_PreambleIndex;
1345
#ifdef OPENAIR2
1346 1347 1348
	    mac_xface->Msg1_transmitted(Mod_id,
					CC_id,
					frame_tx,
1349
					eNB_id);
1350
#endif
1351 1352
	  }
	  LOG_D(PHY,"[UE  %d][RAPROC] Frame %d, subframe %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n",
1353
		Mod_id,frame_tx,subframe_tx,eNB_id,
1354
		phy_vars_ue->prach_resources[eNB_id]->ra_PreambleIndex,
1355 1356
		phy_vars_ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_PL(Mod_id,CC_id,eNB_id),
		get_PL(Mod_id,CC_id,eNB_id));
1357 1358 1359

	}
      }
1360
      LOG_D(PHY,"[UE %d] frame %d subframe %d : generate_prach %d, prach_cnt %d\n",
1361
	    Mod_id,frame_tx,subframe_tx,phy_vars_ue->generate_prach,phy_vars_ue->prach_cnt);
1362 1363 1364 1365 1366 1367 1368 1369

      phy_vars_ue->prach_cnt++;
      if (phy_vars_ue->prach_cnt==3)
	phy_vars_ue->generate_prach=0;
    } // mode is PRACH
    else {
      phy_vars_ue->generate_prach=0; 
    }
1370
  } // slot_tx is even
1371
  vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT);
1372
  stop_meas(&phy_vars_ue->phy_proc_tx);
1373 1374
}

1375
void phy_procedures_UE_S_TX(PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t abstraction_flag,relaying_type_t r_type) {
1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
  int aa;//i,aa;
  LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_ue->lte_frame_parms;

  if (abstraction_flag==0) {
    /*
    if (phy_vars_ue->frame%100==1) {
      LOG_I(PHY,"frame %d, next_slot %d, setting switch to rx\n",phy_vars_ue->frame, next_slot);
    }
    */
    
    
    for (aa=0;aa<frame_parms->nb_antennas_tx;aa++){
#ifdef EXMIMO //this is the EXPRESS MIMO case
      int i;
      // set the whole tx buffer to RX
      for (i=0;i<LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*frame_parms->samples_per_tti;i++)
	phy_vars_ue->lte_ue_common_vars.txdata[aa][i] = 0x00010001;
#else //this is the normal case
      memset(&phy_vars_ue->lte_ue_common_vars.txdata[aa][0],0,
1395
	     (LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*frame_parms->samples_per_tti)*sizeof(int32_t));
1396 1397 1398 1399 1400 1401
#endif //else EXMIMO

    }
  }
}

1402
void lte_ue_measurement_procedures(uint16_t l, PHY_VARS_UE *phy_vars_ue,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) {
1403 1404 1405 1406
  
  LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_ue->lte_frame_parms;
  //  int aa;
#if defined(EXMIMO) && defined(DRIVER2013)
1407 1408
  //  exmimo_config_t *p_exmimo_config = openair0_exmimo_pci[0].exmimo_config_ptr;
  //  int aa;
1409
#endif
1410 1411 1412
  int Mod_id=phy_vars_ue->Mod_id;
  int slot_rx = phy_vars_ue->slot_rx;
  int subframe_rx = slot_rx>>1;
1413 1414 1415 1416 1417

  vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_MEASUREMENT_PROCEDURES, VCD_FUNCTION_IN);

#ifdef EMOS
  /*
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