Commit 0234a5c2 authored by Francesco Mani's avatar Francesco Mani

conflicts resolved after merging with nr-polar-encoder-optimizations

parents 7405eec0 f2d5cfae
...@@ -963,7 +963,7 @@ set(UTIL_SRC ...@@ -963,7 +963,7 @@ set(UTIL_SRC
${OPENAIR_DIR}/common/utils/LOG/log.c ${OPENAIR_DIR}/common/utils/LOG/log.c
# ${OPENAIR2_DIR}/UTIL/LOG/vcd_signal_dumper.c # ${OPENAIR2_DIR}/UTIL/LOG/vcd_signal_dumper.c
${OPENAIR2_DIR}/UTIL/MATH/oml.c ${OPENAIR2_DIR}/UTIL/MATH/oml.c
${OPENAIR2_DIR}/UTIL/MEM/mem_block.c # ${OPENAIR2_DIR}/UTIL/MEM/mem_block.c
# ${OPENAIR2_DIR}/UTIL/OCG/OCG.c # ${OPENAIR2_DIR}/UTIL/OCG/OCG.c
# ${OPENAIR2_DIR}/UTIL/OCG/OCG_create_dir.c # ${OPENAIR2_DIR}/UTIL/OCG/OCG_create_dir.c
# ${OPENAIR2_DIR}/UTIL/OCG/OCG_detect_file.c # ${OPENAIR2_DIR}/UTIL/OCG/OCG_detect_file.c
...@@ -1652,8 +1652,9 @@ set ( NR_LTE_UE_REUSE_SRC ...@@ -1652,8 +1652,9 @@ set ( NR_LTE_UE_REUSE_SRC
${OPENAIR1_DIR}/PHY/CODING/viterbi.c ${OPENAIR1_DIR}/PHY/CODING/viterbi.c
#${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/phich_common.c #${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/phich_common.c
${OPENAIR1_DIR}/PHY/LTE_UE_TRANSPORT/dlsch_llr_computation.c ${OPENAIR1_DIR}/PHY/LTE_UE_TRANSPORT/dlsch_llr_computation.c
${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c
#${OPENAIR1_DIR}/PHY/CODING/lte_rate_matching.c # ${OPENAIR1_DIR}/PHY/LTE_TRANSPORT/dci_tools_common.c
# ${OPENAIR1_DIR}/PHY/CODING/lte_rate_matching.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c ${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c
${OPENAIR1_DIR}/PHY/LTE_REFSIG/lte_gold.c ${OPENAIR1_DIR}/PHY/LTE_REFSIG/lte_gold.c
...@@ -2561,13 +2562,13 @@ add_executable(ldpctest ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c) ...@@ -2561,13 +2562,13 @@ add_executable(ldpctest ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c)
target_link_libraries(ldpctest SIMU PHY PHY_NR m ${ATLAS_LIBRARIES}) target_link_libraries(ldpctest SIMU PHY PHY_NR m ${ATLAS_LIBRARIES})
add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c ${T_SOURCE}) add_executable(nr_dlschsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c ${T_SOURCE})
target_link_libraries(nr_dlschsim -Wl,--start-group UTIL SIMU PHY PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl) target_link_libraries(nr_dlschsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl)
add_executable(nr_pbchsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/pbchsim.c ${T_SOURCE}) add_executable(nr_pbchsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/pbchsim.c ${T_SOURCE})
target_link_libraries(nr_pbchsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl) target_link_libraries(nr_pbchsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl)
add_executable(nr_dlsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlsim.c ${T_SOURCE}) add_executable(nr_dlsim ${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlsim.c ${T_SOURCE})
target_link_libraries(nr_dlsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl) target_link_libraries(nr_dlsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} dl)
foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim prachsim syncsim) foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim prachsim syncsim)
......
...@@ -1035,14 +1035,16 @@ ...@@ -1035,14 +1035,16 @@
<testCase id="015103"> <testCase id="015103">
<class>execution</class> <class>execution</class>
<desc>polartest Test cases. (Test1: PBCH polar test)</desc> <desc>polartest Test cases. (Test1: PBCH polar test),
(Test2: DCI polar test)</desc>
<pre_compile_prog></pre_compile_prog> <pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog> <compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args> <compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec> <pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args> <pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/polartest.Rel15</main_exec> <main_exec> $OPENAIR_DIR/targets/bin/polartest.Rel15</main_exec>
<main_exec_args>-q -s-10 -f0</main_exec_args> <main_exec_args>-q -s-10 -f0
-q -s-10 -f0 -m1</main_exec_args>
<tags>polartest.test1</tags> <tags>polartest.test1</tags>
<search_expr_true>BLER= 0.000000</search_expr_true> <search_expr_true>BLER= 0.000000</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false> <search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
...@@ -1051,16 +1053,24 @@ ...@@ -1051,16 +1053,24 @@
<testCase id="015104"> <testCase id="015104">
<class>execution</class> <class>execution</class>
<desc>nr_pbchsim Test cases. (Test1: PBCH-only), <desc>nr_pbchsim Test cases. (Test1: PBCH-only, 106 PRB),
(Test2: PBCH and synchronization)</desc> (Test2: PBCH and synchronization, 106PBR),
(Test3: PBCH-only, 217 PRB),
(Test4: PBCH and synchronization, 217 RPB),
(Test5: PBCH-only, 217 PRB),
(Test6: PBCH and synchronization, 217 PRB)</desc>
<pre_compile_prog></pre_compile_prog> <pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog> <compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args> <compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec> <pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args> <pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_pbchsim.Rel15</main_exec> <main_exec> $OPENAIR_DIR/targets/bin/nr_pbchsim.Rel15</main_exec>
<main_exec_args>-s-11 -S-10 -n1000 <main_exec_args>-s-11 -S-10 -n1000 -R106
-s-11 -S-10 -n10 -I</main_exec_args> -s-11 -S-10 -n10 -I -R106
-s-11 -S-10 -n1000 -R217 -N10
-s-11 -S-10 -n10 -I -R217 -N10
-s-11 -S-10 -n1000 -R273 -N20
-s-11 -S-10 -n10 -I -R273 -N20</main_exec_args>
<tags>nr_pbchsim.test1 nr_pbchsim.test2</tags> <tags>nr_pbchsim.test1 nr_pbchsim.test2</tags>
<search_expr_true>PBCH test OK</search_expr_true> <search_expr_true>PBCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false> <search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
......
...@@ -3,11 +3,11 @@ set(PACKAGE_NAME "unitary_tests_simulators") ...@@ -3,11 +3,11 @@ set(PACKAGE_NAME "unitary_tests_simulators")
set(PHYSIM True) set(PHYSIM True)
set(RF_BOARD None) set(RF_BOARD None)
set(XFORMS True) set(XFORMS True)
set(ENABLE_ITTI False) set(ENABLE_ITTI True)
set(DEBUG_PHY False) set(DEBUG_PHY False)
set(MU_RECIEVER False) set(MU_RECIEVER False)
set(NAS_UE False) set(NAS_UE False)
set(MESSAGE_CHART_GENERATOR False) set(MESSAGE_CHART_GENERATOR False)
set(RRC_ASN1_VERSION "Rel14") set(RRC_ASN1_VERSION "Rel15")
set(T_TRACER True) set(T_TRACER True)
include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt) include(${CMAKE_CURRENT_SOURCE_DIR}/../CMakeLists.txt)
...@@ -74,10 +74,10 @@ const char* eurecomVariablesNames[] = { ...@@ -74,10 +74,10 @@ const char* eurecomVariablesNames[] = {
"frame_number_TX1_RU", "frame_number_TX1_RU",
"frame_number_RX0_RU", "frame_number_RX0_RU",
"frame_number_RX1_RU", "frame_number_RX1_RU",
"subframe_number_TX0_RU", "tti_number_TX0_RU",
"subframe_number_TX1_RU", "tti_number_TX1_RU",
"subframe_number_RX0_RU", "tti_number_RX0_RU",
"subframe_number_RX1_RU", "tti_number_RX1_RU",
"runtime_TX_eNB", "runtime_TX_eNB",
"runtime_RX_eNB", "runtime_RX_eNB",
"frame_number_TX0_UE", "frame_number_TX0_UE",
...@@ -196,10 +196,10 @@ const char* eurecomVariablesNames[] = { ...@@ -196,10 +196,10 @@ const char* eurecomVariablesNames[] = {
"frame_number_TX1_gNB", "frame_number_TX1_gNB",
"frame_number_RX0_gNB", "frame_number_RX0_gNB",
"frame_number_RX1_gNB", "frame_number_RX1_gNB",
"subframe_number_TX0_gNB", "slot_number_TX0_gNB",
"subframe_number_TX1_gNB", "slot_number_TX1_gNB",
"subframe_number_RX0_gNB", "slot_number_RX0_gNB",
"subframe_number_RX1_gNB" "slot_number_RX1_gNB"
}; };
const char* eurecomFunctionsNames[] = { const char* eurecomFunctionsNames[] = {
......
...@@ -51,10 +51,10 @@ typedef enum { ...@@ -51,10 +51,10 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_RU, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_RU,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_RU, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_RU,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_RU, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_RU,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX0_RU, VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX1_RU, VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX1_RU,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX0_RU, VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_RX0_RU,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX1_RU, VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_RX1_RU,
VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_TX_ENB, VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_TX_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_RX_ENB, VCD_SIGNAL_DUMPER_VARIABLES_RUNTIME_RX_ENB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_UE,
...@@ -173,10 +173,10 @@ typedef enum { ...@@ -173,10 +173,10 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_GNB, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_GNB, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX0_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_GNB, VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_RX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX0_GNB, VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_TX0_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_TX1_GNB, VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_TX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX0_GNB, VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX0_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SUBFRAME_NUMBER_RX1_GNB, VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_END VCD_SIGNAL_DUMPER_VARIABLES_END
} vcd_signal_dump_variables; } vcd_signal_dump_variables;
......
...@@ -1099,26 +1099,26 @@ ID = VCD_VARIABLE_FRAME_NUMBER_RX1_RU ...@@ -1099,26 +1099,26 @@ ID = VCD_VARIABLE_FRAME_NUMBER_RX1_RU
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = frame_number_RX1_RU VCD_NAME = frame_number_RX1_RU
ID = VCD_VARIABLE_SUBFRAME_NUMBER_TX0_RU ID = VCD_VARIABLE_TTI_NUMBER_TX0_RU
DESC = VCD variable SUBFRAME_NUMBER_TX0_RU DESC = VCD variable TTI_NUMBER_TX0_RU
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_TX0_RU VCD_NAME = tti_number_TX0_RU
ID = VCD_VARIABLE_SUBFRAME_NUMBER_TX1_RU ID = VCD_VARIABLE_TTI_NUMBER_TX1_RU
DESC = VCD variable SUBFRAME_NUMBER_TX1_RU DESC = VCD variable TTI_NUMBER_TX1_RU
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_TX1_RU VCD_NAME = tti_number_TX1_RU
ID = VCD_VARIABLE_SUBFRAME_NUMBER_RX0_RU ID = VCD_VARIABLE_TTI_NUMBER_RX0_RU
DESC = VCD variable SUBFRAME_NUMBER_RX0_RU DESC = VCD variable TTI_NUMBER_RX0_RU
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_RX0_RU VCD_NAME = tti_number_RX0_RU
ID = VCD_VARIABLE_SUBFRAME_NUMBER_RX1_RU ID = VCD_VARIABLE_TTI_NUMBER_RX1_RU
DESC = VCD variable SUBFRAME_NUMBER_RX1_RU DESC = VCD variable TTI_NUMBER_RX1_RU
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_RX1_RU VCD_NAME = tti_number_RX1_RU
ID = VCD_VARIABLE_RUNTIME_TX_ENB ID = VCD_VARIABLE_RUNTIME_TX_ENB
DESC = VCD variable RUNTIME_TX_ENB DESC = VCD variable RUNTIME_TX_ENB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
...@@ -1701,26 +1701,26 @@ ID = VCD_VARIABLE_FRAME_NUMBER_RX1_GNB ...@@ -1701,26 +1701,26 @@ ID = VCD_VARIABLE_FRAME_NUMBER_RX1_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = frame_number_RX1_gNB VCD_NAME = frame_number_RX1_gNB
ID = VCD_VARIABLE_SUBFRAME_NUMBER_TX0_GNB ID = VCD_VARIABLE_SLOT_NUMBER_TX0_GNB
DESC = VCD variable SUBFRAME_NUMBER_TX0_GNB DESC = VCD variable SLOT_NUMBER_TX0_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_TX0_gNB VCD_NAME = slot_number_TX0_gNB
ID = VCD_VARIABLE_SUBFRAME_NUMBER_TX1_GNB ID = VCD_VARIABLE_SLOT_NUMBER_TX1_GNB
DESC = VCD variable SUBFRAME_NUMBER_TX1_GNB DESC = VCD variable SLOT_NUMBER_TX1_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_TX1_gNB VCD_NAME = slot_number_TX1_gNB
ID = VCD_VARIABLE_SUBFRAME_NUMBER_RX0_GNB ID = VCD_VARIABLE_SLOT_NUMBER_RX0_GNB
DESC = VCD variable SUBFRAME_NUMBER_RX0_GNB DESC = VCD variable SLOT_NUMBER_RX0_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_RX0_gNB VCD_NAME = slot_number_RX0_gNB
ID = VCD_VARIABLE_SUBFRAME_NUMBER_RX1_GNB ID = VCD_VARIABLE_SLOT_NUMBER_RX1_GNB
DESC = VCD variable SUBFRAME_NUMBER_RX1_GNB DESC = VCD variable SLOT_NUMBER_RX1_GNB
GROUP = ALL:VCD:ENB:VCD_VARIABLE GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value FORMAT = ulong,value
VCD_NAME = subframe_number_RX1_gNB VCD_NAME = slot_number_RX1_gNB
#functions #functions
......
...@@ -24,119 +24,119 @@ ...@@ -24,119 +24,119 @@
#include "PHY/impl_defs_nr.h" #include "PHY/impl_defs_nr.h"
/* /*
typedef unsigned int uint32_t; typedef unsigned int uint32_t;
typedef unsigned short uint16_t; typedef unsigned short uint16_t;
typedef unsigned char uint8_t; typedef unsigned char uint8_t;
typedef signed int int32_t; typedef signed int int32_t;
typedef signed short int16_t; typedef signed short int16_t;
typedef signed char int8_t; typedef signed char int8_t;
*/ */
typedef struct { typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS: uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213] uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1: uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213] uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3 uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND: uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND: uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND: uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES: uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space // (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding // and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space // is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0 // the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0 // is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits, uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList // where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0 uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214] uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER: uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0 uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS: uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI: uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV: uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS: uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI: uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV: uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS: uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI: uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV: uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER: uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI // 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise // 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING: uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH: uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH: uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND: uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND: uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS: uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS: uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST: uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD: uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST: uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS: uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND: uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise // is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding // and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space // is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0 // zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0 // until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0: uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX: uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0: uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} fapi_nr_dci_pdu_rel15_t; } fapi_nr_dci_pdu_rel15_t;
typedef struct { typedef struct {
uint8_t uci_format; uint8_t uci_format;
uint8_t uci_channel; uint8_t uci_channel;
uint8_t harq_ack_bits; uint8_t harq_ack_bits;
uint32_t harq_ack; uint32_t harq_ack;
uint8_t csi_bits; uint8_t csi_bits;
uint32_t csi; uint32_t csi;
uint8_t sr_bits; uint8_t sr_bits;
uint32_t sr; uint32_t sr;
} fapi_nr_uci_pdu_rel15_t; } fapi_nr_uci_pdu_rel15_t;
typedef struct { typedef struct {
/// frequency_domain_resource; /// frequency_domain_resource;
//uint32_t rb_start; //uint32_t rb_start;
//uint32_t rb_end; //uint32_t rb_end;
uint64_t frequency_domain_resource; uint64_t frequency_domain_resource;
uint16_t rb_offset; uint16_t rb_offset;
uint8_t duration; uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
uint8_t precoder_granularity; uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id; uint16_t pdcch_dmrs_scrambling_id;
uint8_t tci_state_pdcch; uint8_t tci_state_pdcch;
uint8_t tci_present_in_dci; uint8_t tci_present_in_dci;
} fapi_nr_coreset_t; } fapi_nr_coreset_t;
// //
// Top level FAPI messages // Top level FAPI messages
...@@ -148,79 +148,79 @@ typedef struct { ...@@ -148,79 +148,79 @@ typedef struct {
// P7 // P7
// //
typedef struct { typedef struct {
uint16_t rnti; uint16_t rnti;
uint8_t dci_format; uint8_t dci_format;
// n_CCE index of first CCE for PDCCH reception // n_CCE index of first CCE for PDCCH reception
int n_CCE; int n_CCE;
// N_CCE is L, or number of CCEs for DCI // N_CCE is L, or number of CCEs for DCI
int N_CCE; int N_CCE;
fapi_nr_dci_pdu_rel15_t dci; fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t; } fapi_nr_dci_indication_pdu_t;
/// ///
typedef struct { typedef struct {
uint32_t sfn_slot; uint32_t sfn_slot;
uint16_t number_of_dcis; uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10]; fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t; } fapi_nr_dci_indication_t;
typedef struct { typedef struct {
uint32_t pdu_length; uint32_t pdu_length;
uint8_t* pdu; uint8_t* pdu;
} fapi_nr_pdsch_pdu_t; } fapi_nr_pdsch_pdu_t;
typedef struct { typedef struct {
uint8_t* pdu; // 3bytes uint8_t* pdu; // 3bytes
uint8_t additional_bits; uint8_t additional_bits;
uint8_t ssb_index; uint8_t ssb_index;
uint8_t ssb_length; uint8_t ssb_length;
uint16_t cell_id; uint16_t cell_id;
} fapi_nr_mib_pdu_t; } fapi_nr_mib_pdu_t;
typedef struct { typedef struct {
uint32_t pdu_length; uint32_t pdu_length;
uint8_t* pdu; uint8_t* pdu;
uint32_t sibs_mask; uint32_t sibs_mask;
} fapi_nr_sib_pdu_t; } fapi_nr_sib_pdu_t;
typedef struct { typedef struct {
uint8_t pdu_type; uint8_t pdu_type;
union { union {
fapi_nr_pdsch_pdu_t pdsch_pdu; fapi_nr_pdsch_pdu_t pdsch_pdu;
fapi_nr_mib_pdu_t mib_pdu; fapi_nr_mib_pdu_t mib_pdu;
fapi_nr_sib_pdu_t sib_pdu; fapi_nr_sib_pdu_t sib_pdu;
}; };
} fapi_nr_rx_indication_body_t; } fapi_nr_rx_indication_body_t;
/// ///
typedef struct { typedef struct {
uint32_t sfn_slot; uint32_t sfn_slot;
uint16_t number_pdus; uint16_t number_pdus;
fapi_nr_rx_indication_body_t *rx_indication_body; fapi_nr_rx_indication_body_t *rx_indication_body;
} fapi_nr_rx_indication_t; } fapi_nr_rx_indication_t;
typedef struct { typedef struct {
uint8_t ul_cqi; uint8_t ul_cqi;
uint16_t timing_advance; uint16_t timing_advance;
uint16_t rnti; uint16_t rnti;
} fapi_nr_tx_config_t; } fapi_nr_tx_config_t;
typedef struct { typedef struct {
uint16_t pdu_length; uint16_t pdu_length;
uint16_t pdu_index; uint16_t pdu_index;
uint8_t* pdu; uint8_t* pdu;
} fapi_nr_tx_request_body_t; } fapi_nr_tx_request_body_t;
/// ///
typedef struct { typedef struct {
uint32_t sfn_slot; uint32_t sfn_slot;
fapi_nr_tx_config_t tx_config; fapi_nr_tx_config_t tx_config;
uint16_t number_of_pdus;