diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c index 3497e8aef3689dfda0dfb0af0bdcf4fe418c2378..d27c13565a852dbc68a61bb235eea9b1bda40973 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c @@ -629,7 +629,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = rnti; fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu_1_0 = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15; - NR_PDSCH_Config_t *pdsch_config= (mac->DLbwp[dl_bwp_id -1]) ? mac->DLbwp[dl_bwp_id -1]->bwp_Dedicated->pdsch_Config->choice.setup : NULL; + NR_PDSCH_Config_t *pdsch_config= (mac->DLbwp[dl_bwp_id-1]) ? mac->DLbwp[dl_bwp_id-1]->bwp_Dedicated->pdsch_Config->choice.setup : NULL; uint16_t BWPSize = n_RB_DLBWP; if(rnti == SI_RNTI) { @@ -1537,7 +1537,7 @@ uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac, break; case NR_UL_DCI_FORMAT_0_0: - if (mac->ULbwp[ul_bwp_id-1]) N_RB_UL=NRRIV2BW(mac->ULbwp[ul_bwp_id -1]->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); + if (mac->ULbwp[ul_bwp_id-1]) N_RB_UL=NRRIV2BW(mac->ULbwp[ul_bwp_id-1]->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); else N_RB_UL=NRRIV2BW(mac->scc_SIB->uplinkConfigCommon->initialUplinkBWP.genericParameters.locationAndBandwidth, MAX_BWP_SIZE); switch(rnti_type) diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c index cf83136a72bba50999e453462462d7b25d22589c..5e8774d118e373a59b84168c244ea6910e2fa382 100644 --- a/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c +++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c @@ -666,7 +666,10 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac, } else if (*dci_format == NR_UL_DCI_FORMAT_0_1) { /* BANDWIDTH_PART_IND */ - + // if (dci->bwp_indicator.val != 1) { + // LOG_W(NR_MAC, "bwp_indicator != 1! Possibly due to false DCI. Ignoring DCI!\n"); + // return -1; + // } config_bwp_ue(mac, &dci->bwp_indicator.val, dci_format); target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific; ul_layers_config(mac, pusch_config_pdu, dci); @@ -783,9 +786,9 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac, /* DMRS */ l_prime_mask = get_l_prime(pusch_config_pdu->nr_of_symbols, mappingtype, add_pos, dmrslength, pusch_config_pdu->start_symbol_index, mac->scc ? mac->scc->dmrs_TypeA_Position : mac->mib->dmrs_TypeA_Position); - if ((mac->ULbwp[ul_bwp_id -1] && pusch_config_pdu->transform_precoding == transform_precoder_disabled)) + if ((mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == transform_precoder_disabled)) pusch_config_pdu->num_dmrs_cdm_grps_no_data = 1; - else if (*dci_format == NR_UL_DCI_FORMAT_0_0 || (mac->ULbwp[ul_bwp_id -1] && pusch_config_pdu->transform_precoding == transform_precoder_enabled)) + else if (*dci_format == NR_UL_DCI_FORMAT_0_0 || (mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == transform_precoder_enabled)) pusch_config_pdu->num_dmrs_cdm_grps_no_data = 2; // Num PRB Overhead from PUSCH-ServingCellConfig diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c index fc2daeac059e4a8f46f1fd0fab94b68186a9193b..52b4c5c1739119fd99983c84a35fa494f1b373fc 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c @@ -353,8 +353,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, } memset(RC.nrmac[module_idP]->cce_list[0][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0 - for (int i_bwp=1 ; i_bwp < MAX_NUM_BWP; i_bwp++) - memset(RC.nrmac[module_idP]->cce_list[i_bwp][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1-4 + for(int i_bwp = 1; i_bwp < MAX_NUM_BWP; i_bwp++) + memset(RC.nrmac[module_idP]->cce_list[i_bwp][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid i + NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info; for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) for (int i=0; i<MAX_NUM_CORESET; i++)