diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c index 78d25b1bd15e8120f3bcd1ea10cc3686ccc801f1..1e1751fe24adabdeaf9ff76fa21a31f2b7f6daff 100644 --- a/openair1/PHY/MODULATION/slot_fep_nr.c +++ b/openair1/PHY/MODULATION/slot_fep_nr.c @@ -56,11 +56,17 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue, unsigned int rx_offset; NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns]][0]; uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB; - uint16_t nb_rb_coreset = 24; + uint16_t nb_rb_coreset = 0; uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516; uint16_t nb_rb_pdsch = 50; uint8_t p=0; - uint8_t l0 = 2; + uint8_t l0 = pdcch_vars->coreset[0].duration; + uint64_t coreset_freq_dom = pdcch_vars->coreset[0].frequencyDomainResources; + for (int i = 0; i < 45; i++) { + if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> i) & 0x1) nb_rb_coreset++; + } + nb_rb_coreset = 6 * nb_rb_coreset; + //printf("corset duration %d nb_rb_coreset %d\n", l0, nb_rb_coreset); void (*dft)(int16_t *,int16_t *, int); int tmp_dft_in[8192] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c index 0aeab29f97101d1cf1dd17104f6853b0c8426665..ca30ab1cec789a8f2fe05d2e3f39f9a82b13b72f 100644 --- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c +++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c @@ -48,11 +48,13 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ /// component carrier id uint8_t cc_id = scheduled_response->CC_id; uint32_t i; + int slot = scheduled_response->slot; + uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot]; if(scheduled_response != NULL){ // Note: we have to handle the thread IDs for this. To be revisited completely. - NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[0][0]; - NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[0][0][0]; + NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0]; + NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0]; NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[0]; NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms; PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0]; diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c index 3b7d86f16bd8fd5a47c2d6fe0b58f8caf966dbe7..3eb0c319aaf9edfc137b569c6fb4fde871af41ca 100644 --- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c +++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c @@ -4969,10 +4969,9 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eN int frame_rx = proc->frame_rx; int nr_tti_rx = proc->nr_tti_rx; + NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0]; uint16_t nb_symb_sch = 8; // to be updated by higher layer - uint8_t nb_symb_pdcch =2; - //proc->decoder_switch = 0; - //int counter_decoder = 0; + uint8_t nb_symb_pdcch = pdcch_vars->coreset[0].duration; LOG_D(PHY," ****** start RX-Chain for AbsSubframe %d.%d ****** \n", frame_rx%1024, nr_tti_rx); diff --git a/targets/RT/USER/nr-ue.c b/targets/RT/USER/nr-ue.c index 7d3c7539908d1cca0c0ef28075835246374fc6ec..f06ae0864df42a334391e04a2dc9e9b8854896fa 100644 --- a/targets/RT/USER/nr-ue.c +++ b/targets/RT/USER/nr-ue.c @@ -693,6 +693,7 @@ static void *UE_thread_rxn_txnp4(void *arg) { NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0); UE_mac->scheduled_response.dl_config = &UE->dcireq.dl_config_req; + UE_mac->scheduled_response.slot = proc->nr_tti_rx; nr_ue_scheduled_response(&UE_mac->scheduled_response); #ifdef UE_SLOT_PARALLELISATION @@ -920,7 +921,7 @@ void *UE_thread(void *arg) { if(thread_idx>=RX_NB_TH) thread_idx = 0; - printf("slot_nr %d nb slot frame %d\n",slot_nr, nb_slot_frame); + //printf("slot_nr %d nb slot frame %d\n",slot_nr, nb_slot_frame); slot_nr++; slot_nr %= nb_slot_frame; @@ -1110,6 +1111,7 @@ void *UE_thread(void *arg) { NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0); UE_mac->scheduled_response.dl_config = &UE->dcireq.dl_config_req; + UE_mac->scheduled_response.slot = proc->nr_tti_rx; nr_ue_scheduled_response(&UE_mac->scheduled_response); //write_output("uerxdata_frame.m", "uerxdata_frame", UE->common_vars.rxdata[0], UE->frame_parms.samples_per_frame, 1, 1);