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Commit 36cd05bc authored by Louis Adrien Dufrene's avatar Louis Adrien Dufrene

Bug fix: dci0_ongoing timer ok, now impossible to set ul_SR when dci0 is ongoing.

parent d7cddc28
......@@ -4954,7 +4954,7 @@ SR_indication(module_id_t mod_idP,
UE_scheduling_ctrl = &(UE_list->UE_sched_ctrl[UE_id]);
if ((UE_scheduling_ctrl->cdrx_configured == TRUE) &&
(UE_scheduling_ctrl->dci0_ongoing_timer > 4) &&
(UE_scheduling_ctrl->dci0_ongoing_timer > 0) &&
(UE_scheduling_ctrl->dci0_ongoing_timer < 8)) {
LOG_D(MAC, "[eNB %d][SR %x] Frame %d subframeP %d Signaling SR for UE %d on CC_id %d. \
The SR is not set do to ongoing DCI0 with CDRX activated\n",
......@@ -241,9 +241,6 @@ rx_sdu(const module_id_t enb_mod_idP,
* Note: in case of asynchronous UL HARQ process restart here relevant RTT timer.
* Start corresponding CDRX ULRetransmission timer.
unsigned long active_time_condition = 10;
first_rb = UE_template_ptr->first_rb_ul[harq_pid];
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