diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c
index 8148f09fc05363c025ed8e390ff9819b09f949f4..b0a6266d349ce3328cbf6161cd6aab136861eb36 100644
--- a/common/utils/nr/nr_common.c
+++ b/common/utils/nr/nr_common.c
@@ -500,6 +500,12 @@ int get_subband_size(int NPRB,int size) {
}
+
+// from start symbol index and nb or symbols to symbol occupation bitmap in a slot
+uint16_t SL_to_bitmap(int startSymbolIndex, int nrOfSymbols) {
+ return ((1<<nrOfSymbols)-1)<<startSymbolIndex;
+}
+
int get_SLIV(uint8_t S, uint8_t L) {
return ( (uint16_t)(((L-1)<=7)? (14*(L-1)+S) : (14*(15-L)+(13-S))) );
}
diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h
index e7414c9f83c01b8e9da34170611969f08020cd5e..6dd0965e10a8f539e47cb26e3ec614f5cdfa3ba3 100644
--- a/common/utils/nr/nr_common.h
+++ b/common/utils/nr/nr_common.h
@@ -78,6 +78,7 @@ uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
int get_subband_size(int NPRB,int size);
void SLIV2SL(int SLIV,int *S,int *L);
int get_dmrs_port(int nl, uint16_t dmrs_ports);
+uint16_t SL_to_bitmap(int startSymbolIndex, int nrOfSymbols);
int get_nb_periods_per_frame(uint8_t tdd_period);
#define CEILIDIV(a,b) ((a+b-1)/b)
diff --git a/nfapi/oai_integration/nfapi_pnf.c b/nfapi/oai_integration/nfapi_pnf.c
index 2c317687cf6cc3e925ed1b57f07426816e8d169d..205f8799645a35583e25ab2d0c6c9f514547fa7a 100644
--- a/nfapi/oai_integration/nfapi_pnf.c
+++ b/nfapi/oai_integration/nfapi_pnf.c
@@ -1122,11 +1122,11 @@ int pnf_phy_ul_dci_req(gNB_L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7,
proc = &gNB->proc.L1_proc;
if (req->numPdus > 0) {
- if (req->ul_dci_pdu_list[req->numPdus-1].PDUType == 0) { // copy only the last PDU (PHY can have only one UL PDCCH pdu)
- msgTx->ul_pdcch_pdu = req->ul_dci_pdu_list[req->numPdus-1]; // copy the last pdu
- }
- else {
- LOG_E(PHY,"[PNF] UL_DCI_REQ sfn_slot:%d PDU[%d] - unknown pdu type:%d\n", NFAPI_SFNSLOT2DEC(req->SFN, req->Slot), req->numPdus-1, req->ul_dci_pdu_list[req->numPdus-1].PDUType);
+ for (int i=0; i<req->numPdus; i++) {
+ if (req->ul_dci_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE) // only possible value 0: PDCCH PDU
+ msgTx->ul_pdcch_pdu[i] = req->ul_dci_pdu_list[i];
+ else
+ LOG_E(PHY,"[PNF] UL_DCI_REQ sfn_slot:%d PDU[%d] - unknown pdu type:%d\n", NFAPI_SFNSLOT2DEC(req->SFN, req->Slot), req->numPdus-1, req->ul_dci_pdu_list[req->numPdus-1].PDUType);
}
}
@@ -1207,8 +1207,7 @@ int pnf_phy_dl_tti_req(gNB_L1_rxtx_proc_t *proc, nfapi_pnf_p7_config_t *pnf_p7,
processingData_L1tx_t *msgTx = (processingData_L1tx_t *)NotifiedFifoData(res);
if (dl_tti_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE) {
- // we trust the scheduler sends only one PDCCH PDU per slot
- msgTx->pdcch_pdu = dl_tti_pdu_list[i].pdcch_pdu; // fills the last received PDCCH PDU
+ msgTx->pdcch_pdu[i] = dl_tti_pdu_list[i].pdcch_pdu; // copies all the received PDCCH PDUs
}
else if (dl_tti_pdu_list[i].PDUType == NFAPI_NR_DL_TTI_SSB_PDU_TYPE) {
//NFAPI_TRACE(NFAPI_TRACE_INFO, "%s() PDU:%d BCH: pdu_index:%u pdu_length:%d sdu_length:%d BCH_SDU:%x,%x,%x\n", __FUNCTION__, i, pdu_index, bch_pdu->bch_pdu_rel8.length, tx_request_pdu[sfn][sf][pdu_index]->segments[0].segment_length, sdu[0], sdu[1], sdu[2]);
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
index c124ad9fb9dde6b58a258eebc4620c124441ae0a..9681c1d19bb9828f7660e3757f9a6a48f44983b6 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
@@ -1402,9 +1402,6 @@ typedef struct
} nfapi_nr_ul_dci_request_t;
*/
- // normally one PDU per coreset per BWP
-#define NFAPI_NR_MAX_UL_DCI_PDUS 4
-
typedef struct {
/// only possible value 0: PDCCH PDU
uint16_t PDUType;
@@ -1418,7 +1415,7 @@ typedef struct {
uint16_t SFN;
uint16_t Slot;
uint8_t numPdus;
- nfapi_nr_ul_dci_request_pdus_t ul_dci_pdu_list[NFAPI_NR_MAX_UL_DCI_PDUS];
+ nfapi_nr_ul_dci_request_pdus_t ul_dci_pdu_list[NFAPI_NR_MAX_NB_CORESETS];
} nfapi_nr_ul_dci_request_t;
//3.4.5 slot_errors
diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c
index c193733aef4c8fbe1d903d52d45c72578fa4589a..5a9e1376c25f8c22539779d4c274561b29278220 100644
--- a/openair1/PHY/INIT/nr_init_ue.c
+++ b/openair1/PHY/INIT/nr_init_ue.c
@@ -41,7 +41,7 @@
#include "PHY/NR_REFSIG/ul_ref_seq_nr.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
-#include <openair1/PHY/MODULATION/nr_modulation.h>
+#include "PHY/MODULATION/nr_modulation.h"
#if 0
void phy_config_harq_ue(module_id_t Mod_id,
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c
index 4c9f6a7734aefa6b55ef4c2eed023a28ba519e22..0998003e0601c4481a8cd0970c9368784e75d964 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c
@@ -254,20 +254,16 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
}
void nr_generate_dci_top(PHY_VARS_gNB *gNB,
- nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
- nfapi_nr_dl_tti_pdcch_pdu *ul_dci_pdu,
- uint32_t **gold_pdcch_dmrs,
- int32_t *txdataF,
- int16_t amp,
- NR_DL_FRAME_PARMS *frame_parms) {
+ processingData_L1tx_t *msgTx,
+ uint32_t **gold_pdcch_dmrs,
+ int32_t *txdataF,
+ int16_t amp,
+ NR_DL_FRAME_PARMS *frame_parms) {
- AssertFatal(pdcch_pdu!=NULL || ul_dci_pdu!=NULL,"At least one pointer has to be !NULL\n");
+ for (int i=0; i<msgTx->num_ul_pdcch; i++)
+ nr_generate_dci(gNB,&msgTx->ul_pdcch_pdu[i].pdcch_pdu.pdcch_pdu_rel15,gold_pdcch_dmrs,txdataF,amp,frame_parms);
+ for (int i=0; i<msgTx->num_dl_pdcch; i++)
+ nr_generate_dci(gNB,&msgTx->pdcch_pdu[i].pdcch_pdu_rel15,gold_pdcch_dmrs,txdataF,amp,frame_parms);
- if (pdcch_pdu) {
- nr_generate_dci(gNB,&pdcch_pdu->pdcch_pdu_rel15,gold_pdcch_dmrs,txdataF,amp,frame_parms);
- }
- if (ul_dci_pdu) {
- nr_generate_dci(gNB,&ul_dci_pdu->pdcch_pdu_rel15,gold_pdcch_dmrs,txdataF,amp,frame_parms);
- }
}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.h b/openair1/PHY/NR_TRANSPORT/nr_dci.h
index 07baaf2728f8b02d163623fa664694d2a36d6c51..0077bd2f38c9ad51a39214a131e6b75459c7478d 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci.h
@@ -30,12 +30,11 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format,
uint16_t N_RB);
void nr_generate_dci_top(PHY_VARS_gNB *gNB,
- nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
- nfapi_nr_dl_tti_pdcch_pdu *ul_pdcch_pdu,
- uint32_t **gold_pdcch_dmrs,
- int32_t *txdataF,
- int16_t amp,
- NR_DL_FRAME_PARMS *frame_parms);
+ processingData_L1tx_t *msgTx,
+ uint32_t **gold_pdcch_dmrs,
+ int32_t *txdataF,
+ int16_t amp,
+ NR_DL_FRAME_PARMS *frame_parms);
void nr_pdcch_scrambling(uint32_t *in,
uint32_t size,
diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h
index edcac7a91dedcf13ea9c62912c68c9fc1f80da4c..6f308615842c65819decb397b8254115d930660f 100644
--- a/openair1/PHY/defs_gNB.h
+++ b/openair1/PHY/defs_gNB.h
@@ -954,12 +954,14 @@ typedef struct processingData_L1tx {
int slot;
openair0_timestamp timestamp_tx;
PHY_VARS_gNB *gNB;
- nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu;
- nfapi_nr_ul_dci_request_pdus_t ul_pdcch_pdu;
+ nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu[NFAPI_NR_MAX_NB_CORESETS];
+ nfapi_nr_ul_dci_request_pdus_t ul_pdcch_pdu[NFAPI_NR_MAX_NB_CORESETS];
NR_gNB_CSIRS_t csirs_pdu[NUMBER_OF_NR_CSIRS_MAX];
NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2];
NR_gNB_SSB_t ssb[64];
uint16_t num_pdsch_slot;
+ int num_dl_pdcch;
+ int num_ul_pdcch;
time_stats_t phy_proc_tx;
} processingData_L1tx_t;
diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c
index 70e2948402993639ebabe98425f040d860900c9a..8f83e52820053ca0a9737777164850858a8c52ca 100644
--- a/openair1/SCHED_NR/fapi_nr_l1.c
+++ b/openair1/SCHED_NR/fapi_nr_l1.c
@@ -164,10 +164,9 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
res = pullTpool(gNB->L1_tx_free, gNB->threadPool);
processingData_L1tx_t *msgTx = (processingData_L1tx_t *)NotifiedFifoData(res);
- int pdcch_received=0;
msgTx->num_pdsch_slot=0;
- msgTx->pdcch_pdu.pdcch_pdu_rel15.numDlDci = 0;
- msgTx->ul_pdcch_pdu.pdcch_pdu.pdcch_pdu_rel15.numDlDci = 0;
+ msgTx->num_dl_pdcch=0;
+ msgTx->num_ul_pdcch=number_ul_dci_pdu;
msgTx->slot = slot;
msgTx->frame = frame;
@@ -181,16 +180,14 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
break;
case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE:
- AssertFatal(pdcch_received == 0, "pdcch_received is not 0, we can only handle one PDCCH PDU per slot\n");
- msgTx->pdcch_pdu = dl_tti_pdu->pdcch_pdu;
-
- pdcch_received = 1;
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot);
+ msgTx->pdcch_pdu[msgTx->num_dl_pdcch] = dl_tti_pdu->pdcch_pdu;
+ msgTx->num_dl_pdcch++;
break;
case NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot);
- handle_nfapi_nr_csirs_pdu(msgTx,frame,slot,
- &dl_tti_pdu->csi_rs_pdu);
+ handle_nfapi_nr_csirs_pdu(msgTx,frame,slot,&dl_tti_pdu->csi_rs_pdu);
break;
case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE:
@@ -201,13 +198,13 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
pduIndex,TX_req->pdu_list[pduIndex].num_TLV);
uint8_t *sdu = (uint8_t *)TX_req->pdu_list[pduIndex].TLVs[0].value.direct;
AssertFatal(msgTx->num_pdsch_slot < gNB->number_of_nr_dlsch_max,"Number of PDSCH PDUs %d exceeded the limit %d\n",
- msgTx->num_pdsch_slot,gNB->number_of_nr_dlsch_max);
+ msgTx->num_pdsch_slot,gNB->number_of_nr_dlsch_max);
handle_nr_nfapi_pdsch_pdu(msgTx,&dl_tti_pdu->pdsch_pdu, sdu);
}
}
- if (number_ul_dci_pdu > 0)
- msgTx->ul_pdcch_pdu = UL_dci_req->ul_dci_pdu_list[number_ul_dci_pdu-1]; // copy the last pdu
+ for (int i=0; i<number_ul_dci_pdu; i++)
+ msgTx->ul_pdcch_pdu[i] = UL_dci_req->ul_dci_pdu_list[i];
pushNotifiedFIFO(gNB->L1_tx_filled,res);
}
diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
index 100c2238928659c5615011d31cf34695149aa08e..591cc3a9d08f026ea8fec2373164c49d0bd6d48e 100644
--- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c
+++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
@@ -159,18 +159,16 @@ void phy_procedures_gNB_TX(processingData_L1tx_t *msgTx,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,0);
- int num_dl_dci = msgTx->pdcch_pdu.pdcch_pdu_rel15.numDlDci;
- int num_ul_dci = msgTx->ul_pdcch_pdu.pdcch_pdu.pdcch_pdu_rel15.numDlDci;
+ int num_pdcch_pdus = msgTx->num_ul_pdcch + msgTx->num_dl_pdcch;
- if (num_dl_dci > 0 || num_ul_dci > 0) {
- LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL DCI %d/%d)\n",
- gNB->Mod_id, frame, slot, num_ul_dci, num_dl_dci);
+ if (num_pdcch_pdus > 0) {
+ LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci_top (number of UL/DL PDCCH PDUs %d/%d)\n",
+ gNB->Mod_id, frame, slot, msgTx->num_ul_pdcch, msgTx->num_dl_pdcch);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,1);
nr_generate_dci_top(gNB,
- num_dl_dci > 0 ? &msgTx->pdcch_pdu : NULL,
- num_ul_dci > 0 ? &msgTx->ul_pdcch_pdu.pdcch_pdu : NULL,
+ msgTx,
gNB->nr_gold_pdcch_dmrs[slot],
&gNB->common_vars.txdataF[0][txdataF_offset],
AMP, fp);
diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c
index 4efd98d905a5f8d773898ed90b990718889fc8cc..9121d4ba91b804d5d1ea074c8797922ce6f182dc 100644
--- a/openair1/SIMULATION/NR_PHY/dlsim.c
+++ b/openair1/SIMULATION/NR_PHY/dlsim.c
@@ -1049,8 +1049,6 @@ int main(int argc, char **argv)
while ((round<num_rounds) && (UE_harq_process->ack==0)) {
- memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
- memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int));
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1);
@@ -1058,7 +1056,7 @@ int main(int argc, char **argv)
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].round = round;
for (int i=0; i<MAX_NUM_CORESET; i++)
- gNB_mac->UE_info.num_pdcch_cand[0][i] = 0;
+ gNB_mac->pdcch_cand[i] = 0;
if (css_flag == 0) {
nr_schedule_ue_spec(0, frame, slot);
diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c
index f940f36c6c4a38527437e3d4f95df3ce282c41a0..bbec4817bdad0ed274f8f93876743a06ffd3501e 100644
--- a/openair2/LAYER2/NR_MAC_gNB/config.c
+++ b/openair2/LAYER2/NR_MAC_gNB/config.c
@@ -536,7 +536,6 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (CellGroup) {
const NR_ServingCellConfig_t *servingCellConfig = CellGroup->spCellConfig->spCellConfigDedicated;
-
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
if(bwpList) {
AssertFatal(bwpList->list.count > 0, "downlinkBWP_ToAddModList has no BWPs!\n");
@@ -607,6 +606,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
ra->msg3_dcch_dtch = false;
LOG_I(NR_MAC,"Added new RA process for UE RNTI %04x with initial CellGroup\n", rnti);
} else { // CellGroup has been updated
+ NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels[0].ServingCellConfigCommon;
const int UE_id = find_nr_UE_id(Mod_idP,rnti);
int target_ss;
UE_info->CellGroup[UE_id] = CellGroup;
@@ -627,19 +627,30 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
}
// update coreset/searchspace
void *bwpd = NULL;
+ NR_BWP_t *genericParameters = NULL;
target_ss = NR_SearchSpace__searchSpaceType_PR_common;
if ((sched_ctrl->active_bwp)) {
target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
bwpd = (void*)sched_ctrl->active_bwp->bwp_Dedicated;
+ genericParameters = &sched_ctrl->active_bwp->bwp_Common->genericParameters;
}
else if (CellGroup->spCellConfig &&
CellGroup->spCellConfig->spCellConfigDedicated &&
(CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP)) {
target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
bwpd = (void*)CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP;
+ genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
}
+ else
+ AssertFatal(1==0,"Either initial BWP or active BWP should always be present\n");
sched_ctrl->search_space = get_searchspace(scc, bwpd, target_ss);
sched_ctrl->coreset = get_coreset(Mod_idP, scc, bwpd, sched_ctrl->search_space, target_ss);
+ sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP],
+ sched_ctrl->search_space,
+ sched_ctrl->coreset,
+ scc,
+ genericParameters,
+ NULL);
sched_ctrl->maxL = 2;
if (CellGroup->spCellConfig &&
CellGroup->spCellConfig->spCellConfigDedicated &&
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
index 87c1dee1e50c91f56c52dc234b218742e93af410..0a7a3e3399d9fbae8a78b416389e64c39c27aa2e 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
@@ -67,7 +67,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
nfapi_nr_dl_tti_request_t *DL_req = &gNB->DL_req[0];
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t ***pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t ***)gNB->pdcch_pdu_idx[CC_idP];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t **pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t **)gNB->pdcch_pdu_idx[CC_idP];
nfapi_nr_ul_tti_request_t *future_ul_tti_req =
&gNB->UL_tti_req_ahead[CC_idP][(slotP + num_slots - 1) % num_slots];
nfapi_nr_ul_dci_request_t *UL_dci_req = &gNB->UL_dci_req[0];
@@ -80,7 +80,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
DL_req[CC_idP].dl_tti_request_body.nPDUs = 0;
DL_req[CC_idP].dl_tti_request_body.nGroup = 0;
//DL_req[CC_idP].dl_tti_request_body.transmission_power_pcfich = 6000;
- memset(pdcch, 0, sizeof(**pdcch) * MAX_NUM_BWP * MAX_NUM_CORESET);
+ memset(pdcch, 0, sizeof(*pdcch) * MAX_NUM_CORESET);
UL_dci_req[CC_idP].SFN = frameP;
UL_dci_req[CC_idP].Slot = slotP;
@@ -277,7 +277,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
protocol_ctxt_t ctxt={0};
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame, slot,module_idP);
- const int bwp_id = 1;
char stats_output[16384];
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
@@ -308,13 +307,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_rrc_trigger(&ctxt, 0 /*CC_id*/, frame, slot >> *scc->ssbSubcarrierSpacing);
}
- memset(RC.nrmac[module_idP]->cce_list[0][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
- memset(RC.nrmac[module_idP]->cce_list[0][1],0,MAX_NUM_CCE*sizeof(int)); // coreset1 on initialBWP
- memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
- NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
- for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id])
- for (int i=0; i<MAX_NUM_CORESET; i++)
- UE_info->num_pdcch_cand[UE_id][i] = 0;
+ for (int i=0; i<MAX_NUM_CORESET; i++)
+ RC.nrmac[module_idP]->pdcch_cand[i] = 0;
for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
//mbsfn_status[CC_id] = 0;
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
index d7acf6a614fa21b789ce1f54de1ed6327e9539f6..0c935eea09dd04302dafd1e6907ec05bdaedb8c1 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
@@ -587,12 +587,15 @@ void nr_initiate_ra_proc(module_id_t module_idP,
NR_SearchSpaceId_t ra_SearchSpace = 0;
struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = NULL;
+ NR_BWP_t *genericParameters = NULL;
if(bwp) {
commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
ra_SearchSpace = *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
+ genericParameters = &bwp->bwp_Common->genericParameters;
} else {
commonSearchSpaceList = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
ra_SearchSpace = *scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->ra_SearchSpace;
+ genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
}
AssertFatal(commonSearchSpaceList->list.count > 0, "common SearchSpace list has 0 elements\n");
@@ -605,6 +608,14 @@ void nr_initiate_ra_proc(module_id_t module_idP,
AssertFatal(ra->ra_ss!=NULL,"SearchSpace cannot be null for RA\n");
+ ra->coreset = get_coreset(module_idP, scc, bwp, ra->ra_ss, NR_SearchSpace__searchSpaceType_PR_common);
+ ra->sched_pdcch = set_pdcch_structure(nr_mac,
+ ra->ra_ss,
+ ra->coreset,
+ scc,
+ genericParameters,
+ NULL);
+
// retrieving ra pdcch monitoring period and offset
find_monitoring_periodicity_offset_common(ra->ra_ss, &monitoring_slot_period, &monitoring_offset);
@@ -781,13 +792,13 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
// generation of DCI 0_0 to schedule msg3 retransmission
NR_SearchSpace_t *ss = ra->ra_ss;
- NR_ControlResourceSet_t *coreset = get_coreset(module_idP, scc, NULL, ss, NR_SearchSpace__searchSpaceType_PR_common);
+ NR_ControlResourceSet_t *coreset = ra->coreset;
AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg3 retransmission\n");
nfapi_nr_ul_dci_request_t *ul_dci_req = &nr_mac->UL_dci_req[CC_id];
const int coresetid = coreset->controlResourceSetId;
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
@@ -795,8 +806,8 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
pdcch_pdu_rel15 = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
ul_dci_req->numPdus += 1;
- nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
- nr_mac->pdcch_pdu_idx[CC_id][ra->bwp_id][coresetid] = pdcch_pdu_rel15;
+ nr_configure_pdcch(pdcch_pdu_rel15, coreset, genericParameters, &ra->sched_pdcch);
+ nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
}
uint8_t aggregation_level;
@@ -807,7 +818,13 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
if(nr_of_candidates>0) break;
}
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
- int CCEIndex = allocate_nr_CCEs(nr_mac, NULL, coreset, aggregation_level, 0, 0, nr_of_candidates);
+ int CCEIndex = find_pdcch_candidate(nr_mac,
+ CC_id,
+ aggregation_level,
+ nr_of_candidates,
+ &ra->sched_pdcch,
+ coreset,
+ 0);
if (CCEIndex < 0) {
LOG_E(NR_MAC, "%s(): cannot find free CCE for RA RNTI 0x%04x!\n", __func__, ra->rnti);
return;
@@ -848,6 +865,13 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
ra->bwp_id);
// Mark the corresponding RBs as used
+
+ fill_pdcch_vrb_map(nr_mac,
+ CC_id,
+ &ra->sched_pdcch,
+ CCEIndex,
+ aggregation_level);
+
for (int rb = 0; rb < ra->msg3_nb_rb; rb++) {
vrb_map_UL[rbStart + BWPStart + rb] = 1;
}
@@ -1165,13 +1189,19 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
BWPSize = type0_PDCCH_CSS_config->num_rbs;
}
- coreset = get_coreset(module_idP, scc, bwp, ss, NR_SearchSpace__searchSpaceType_PR_common);
+ // Calculate number of symbols
+ int startSymbolIndex, nrOfSymbols;
+ const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
+ SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
+ AssertFatal(startSymbolIndex >= 0, "StartSymbolIndex is negative\n");
+
+ coreset = ra->coreset;
AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg2\n");
uint16_t *vrb_map = cc[CC_id].vrb_map;
for (int i = 0; (i < rbSize) && (rbStart <= (BWPSize - rbSize)); i++) {
- if (vrb_map[BWPStart + rbStart + i]) {
+ if (vrb_map[BWPStart + rbStart + i]&SL_to_bitmap(startSymbolIndex, nrOfSymbols)) {
rbStart += i;
i = 0;
}
@@ -1197,18 +1227,20 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if(nr_of_candidates>0) break;
}
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
- int CCEIndex = allocate_nr_CCEs(nr_mac, bwp, coreset, aggregation_level,0,0,nr_of_candidates);
+
+ int CCEIndex = find_pdcch_candidate(nr_mac,
+ CC_id,
+ aggregation_level,
+ nr_of_candidates,
+ &ra->sched_pdcch,
+ coreset,
+ 0);
+
if (CCEIndex < 0) {
LOG_E(NR_MAC, "%s(): cannot find free CCE for RA RNTI 0x%04x!\n", __func__, ra->rnti);
return;
}
- // Calculate number of symbols
- int startSymbolIndex, nrOfSymbols;
- const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
- SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
- AssertFatal(startSymbolIndex >= 0, "StartSymbolIndex is negative\n");
-
LOG_D(NR_MAC,"Msg2 startSymbolIndex.nrOfSymbols %d.%d\n",startSymbolIndex,nrOfSymbols);
int mappingtype = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType;
@@ -1217,7 +1249,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const int bwpid = bwp ? bwp->bwp_Id : 0;
const int coresetid = coreset->controlResourceSetId;
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
@@ -1225,8 +1257,8 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
- nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
- nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
+ nr_configure_pdcch(pdcch_pdu_rel15, coreset, genericParameters, &ra->sched_pdcch);
+ nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
@@ -1385,9 +1417,14 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP;
- // Mark the corresponding RBs as used
+ // Mark the corresponding symbols RBs as used
+ fill_pdcch_vrb_map(nr_mac,
+ CC_id,
+ &ra->sched_pdcch,
+ CCEIndex,
+ aggregation_level);
for (int rb = 0; rb < rbSize; rb++) {
- vrb_map[BWPStart + rb + rbStart] = 1;
+ vrb_map[BWPStart + rb + rbStart] |= SL_to_bitmap(startSymbolIndex, nrOfSymbols);
}
ra->state = WAIT_Msg3;
@@ -1424,7 +1461,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_TimeDomainAllocationList = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
}
- coreset = get_coreset(module_idP, scc, bwp, ss, NR_SearchSpace__searchSpaceType_PR_common);
+ coreset = ra->coreset;
AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg4\n");
@@ -1481,7 +1518,15 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if(nr_of_candidates>0) break;
}
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
- int CCEIndex = allocate_nr_CCEs(nr_mac, bwp, coreset, aggregation_level,0,0,nr_of_candidates);
+
+ int CCEIndex = find_pdcch_candidate(nr_mac,
+ CC_id,
+ aggregation_level,
+ nr_of_candidates,
+ &ra->sched_pdcch,
+ coreset,
+ 0);
+
if (CCEIndex < 0) {
LOG_E(NR_MAC, "%s(): cannot find free CCE for RA RNTI 0x%04x!\n", __func__, ra->rnti);
return;
@@ -1596,7 +1641,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
AssertFatal(mcsIndex<10,"Cannot fit Msg4 in %d PRBs with QPSK\n",(int)BWPSize);
int i = 0;
while ((i < rbSize) && (rbStart + rbSize <= BWPSize)) {
- if (vrb_map[BWPStart + rbStart + i]) {
+ if (vrb_map[BWPStart + rbStart + i]&SL_to_bitmap(startSymbolIndex, nrOfSymbols)) {
rbStart += i+1;
i = 0;
} else {
@@ -1621,7 +1666,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const int bwpid = bwp ? bwp->bwp_Id : 0;
const int coresetid = coreset->controlResourceSetId;
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
if (!pdcch_pdu_rel15) {
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset(dl_tti_pdcch_pdu, 0, sizeof(nfapi_nr_dl_tti_request_pdu_t));
@@ -1629,8 +1674,8 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
- nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
- nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
+ nr_configure_pdcch(pdcch_pdu_rel15, coreset, genericParameters, &ra->sched_pdcch);
+ nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu_rel15;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
@@ -1770,9 +1815,14 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].Slot = slotP;
- // Mark the corresponding RBs as used
+ // Mark the corresponding symbols and RBs as used
+ fill_pdcch_vrb_map(nr_mac,
+ CC_id,
+ &ra->sched_pdcch,
+ CCEIndex,
+ aggregation_level);
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) {
- vrb_map[BWPStart + rb + pdsch_pdu_rel15->rbStart] = 1;
+ vrb_map[BWPStart + rb + pdsch_pdu_rel15->rbStart] |= SL_to_bitmap(startSymbolIndex, nrOfSymbols);
}
LOG_D(NR_MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
index 2171d3a974ae22b2f5cc6a30d83376a8828e596e..4d864ebe9c6037697030e3da900b20648e3e4813 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
@@ -314,7 +314,7 @@ void fill_ssb_vrb_map (NR_COMMON_channels_t *cc, int rbStart, uint16_t symStart
uint16_t *vrb_map = cc[CC_id].vrb_map;
for (int rb = 0; rb < 20; rb++)
- vrb_map[rbStart + rb] = 15<<symStart;
+ vrb_map[rbStart + rb] = SL_to_bitmap(symStart, 4);
}
@@ -329,7 +329,9 @@ uint32_t schedule_control_sib1(module_id_t module_id,
int num_total_bytes) {
gNB_MAC_INST *gNB_mac = RC.nrmac[module_id];
- uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
+ NR_COMMON_channels_t *cc = &gNB_mac->common_channels[CC_id];
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ uint16_t *vrb_map = cc->vrb_map;
if (gNB_mac->sched_ctrlCommon == NULL){
LOG_D(NR_MAC,"schedule_control_common: Filling nr_mac->sched_ctrlCommon\n");
@@ -340,6 +342,12 @@ uint32_t schedule_control_sib1(module_id_t module_id,
fill_coresetZero(gNB_mac->sched_ctrlCommon->coreset,type0_PDCCH_CSS_config);
gNB_mac->cset0_bwp_start = type0_PDCCH_CSS_config->cset_start_rb;
gNB_mac->cset0_bwp_size = type0_PDCCH_CSS_config->num_rbs;
+ gNB_mac->sched_ctrlCommon->sched_pdcch = set_pdcch_structure(NULL,
+ gNB_mac->sched_ctrlCommon->search_space,
+ gNB_mac->sched_ctrlCommon->coreset,
+ scc,
+ NULL,
+ type0_PDCCH_CSS_config);
}
gNB_mac->sched_ctrlCommon->pdsch_semi_static.time_domain_allocation = time_domain_allocation;
@@ -354,13 +362,13 @@ uint32_t schedule_control_sib1(module_id_t module_id,
if (nr_of_candidates>0) break; // choosing the lower value of aggregation level available
}
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
- gNB_mac->sched_ctrlCommon->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
- NULL,
- gNB_mac->sched_ctrlCommon->coreset,
- gNB_mac->sched_ctrlCommon->aggregation_level,
- 0,
- candidate_idx,
- nr_of_candidates);
+ gNB_mac->sched_ctrlCommon->cce_index = find_pdcch_candidate(gNB_mac,
+ CC_id,
+ gNB_mac->sched_ctrlCommon->aggregation_level,
+ nr_of_candidates,
+ &gNB_mac->sched_ctrlCommon->sched_pdcch,
+ gNB_mac->sched_ctrlCommon->coreset,
+ 0);
AssertFatal(gNB_mac->sched_ctrlCommon->cce_index >= 0, "Could not find CCE for coreset0\n");
@@ -383,7 +391,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
int rbSize = 0;
uint32_t TBS = 0;
do {
- if(rbSize < bwpSize && !vrb_map[rbStart + rbSize])
+ if(rbSize < bwpSize && !(vrb_map[rbStart + rbSize]&SL_to_bitmap(startSymbolIndex, nrOfSymbols)))
rbSize++;
else{
if (gNB_mac->sched_ctrlCommon->sched_pdsch.mcs<10)
@@ -410,16 +418,21 @@ uint32_t schedule_control_sib1(module_id_t module_id,
LOG_D(NR_MAC,"dmrs_length %d\n",dmrs_length);
LOG_D(NR_MAC,"N_PRB_DMRS = %d\n",N_PRB_DMRS);
LOG_D(NR_MAC,"mappingtype = %d\n", mappingtype);
-
// Mark the corresponding RBs as used
+ fill_pdcch_vrb_map(gNB_mac,
+ CC_id,
+ &gNB_mac->sched_ctrlCommon->sched_pdcch,
+ gNB_mac->sched_ctrlCommon->cce_index,
+ gNB_mac->sched_ctrlCommon->aggregation_level);
for (int rb = 0; rb < gNB_mac->sched_ctrlCommon->sched_pdsch.rbSize; rb++) {
- vrb_map[rb + rbStart] = 1;
+ vrb_map[rb + rbStart] = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
}
return TBS;
}
void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
nfapi_nr_dl_tti_request_body_t *dl_req,
+ int pdu_index,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config,
uint32_t TBS,
int StartSymbolIndex,
@@ -436,13 +449,10 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
- nr_configure_pdcch(NULL,
- pdcch_pdu_rel15,
- gNB_mac->sched_ctrlCommon->search_space,
+ nr_configure_pdcch(pdcch_pdu_rel15,
gNB_mac->sched_ctrlCommon->coreset,
- scc,
NULL,
- type0_PDCCH_CSS_config);
+ &gNB_mac->sched_ctrlCommon->sched_pdcch);
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
@@ -455,7 +465,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
pdsch_pdu_rel15->pduBitmap = 0;
pdsch_pdu_rel15->rnti = SI_RNTI;
- pdsch_pdu_rel15->pduIndex = gNB_mac->pdu_index[0]++;
+ pdsch_pdu_rel15->pduIndex = pdu_index;
pdsch_pdu_rel15->BWPSize = type0_PDCCH_CSS_config->num_rbs;
pdsch_pdu_rel15->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
@@ -623,7 +633,8 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
candidate_idx, sib1_sdu_length);
nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body;
- nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
+ int pdu_index = gNB_mac->pdu_index[0]++;
+ nr_fill_nfapi_dl_sib1_pdu(module_idP, dl_req, pdu_index, type0_PDCCH_CSS_config, TBS, startSymbolIndex, nrOfSymbols, dlDmrsSymbPos);
const int ntx_req = gNB_mac->TX_req[CC_id].Number_of_PDUs;
nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[ntx_req];
@@ -633,7 +644,7 @@ void schedule_nr_sib1(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
memcpy(tx_req->TLVs[0].value.direct, sib1_payload, sib1_sdu_length);
tx_req->PDU_length = TBS;
- tx_req->PDU_index = gNB_mac->pdu_index[0]++;
+ tx_req->PDU_index = pdu_index;
tx_req->num_TLV = 1;
tx_req->TLVs[0].length = TBS + 2;
gNB_mac->TX_req[CC_id].Number_of_PDUs++;
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
index 45dbdba288b660ca86c0d46549f4795662544c31..91187a88f8fbe53883248ddf9dbf0cd4f1a49628 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
@@ -531,7 +531,7 @@ void nr_store_dlsch_buffer(module_id_t module_id,
bool allocate_dl_retransmission(module_id_t module_id,
frame_t frame,
sub_frame_t slot,
- uint8_t *rballoc_mask,
+ uint16_t *rballoc_mask,
int *n_rb_sched,
int UE_id,
int current_harq_pid) {
@@ -561,13 +561,16 @@ bool allocate_dl_retransmission(module_id_t module_id,
while (rbSize < retInfo->rbSize) {
rbStart += rbSize; /* last iteration rbSize was not enough, skip it */
rbSize = 0;
- while (rbStart < bwpSize && !rballoc_mask[rbStart])
+ while (rbStart < bwpSize &&
+ !(rballoc_mask[rbStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
rbStart++;
if (rbStart >= bwpSize) {
LOG_D(NR_MAC, "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n", UE_id, UE_info->rnti[UE_id]);
return false;
}
- while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart + rbSize] && rbSize < retInfo->rbSize)
+ while (rbStart + rbSize < bwpSize &&
+ (rballoc_mask[rbStart + rbSize]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)) &&
+ rbSize < retInfo->rbSize)
rbSize++;
}
/* check whether we need to switch the TDA allocation since the last
@@ -577,9 +580,11 @@ bool allocate_dl_retransmission(module_id_t module_id,
} else {
/* the retransmission will use a different time domain allocation, check
* that we have enough resources */
- while (rbStart < bwpSize && !rballoc_mask[rbStart])
+ while (rbStart < bwpSize &&
+ !(rballoc_mask[rbStart]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
rbStart++;
- while (rbStart + rbSize < bwpSize && rballoc_mask[rbStart + rbSize])
+ while (rbStart + rbSize < bwpSize &&
+ (rballoc_mask[rbStart + rbSize]&SL_to_bitmap(temp_ps.startSymbolIndex, temp_ps.nrOfSymbols)))
rbSize++;
NR_pdsch_semi_static_t temp_ps = *ps;
nr_set_pdsch_semi_static(scc, cg, sched_ctrl->active_bwp, bwpd,tda, ps->nrOfLayers, sched_ctrl, &temp_ps);
@@ -607,8 +612,27 @@ bool allocate_dl_retransmission(module_id_t module_id,
}
/* Find a free CCE */
- bool freeCCE = find_free_CCE(module_id, slot, UE_id);
- if (!freeCCE) {
+ const int cid = sched_ctrl->coreset->controlResourceSetId;
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+ uint8_t nr_of_candidates;
+ for (int i=0; i<5; i++) {
+ // for now taking the lowest value among the available aggregation levels
+ find_aggregation_candidates(&sched_ctrl->aggregation_level,
+ &nr_of_candidates,
+ sched_ctrl->search_space,
+ 1<<i);
+ if(nr_of_candidates>0) break;
+ }
+
+ int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
+ /* CC_id = */ 0,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
+ if (CCEIndex<0) {
LOG_D(MAC, "%4d.%2d could not find CCE for DL DCI retransmission UE %d/RNTI %04x\n",
frame, slot, UE_id, UE_info->rnti[UE_id]);
return false;
@@ -625,14 +649,18 @@ bool allocate_dl_retransmission(module_id_t module_id,
UE_info->rnti[UE_id],
frame,
slot);
- int cid = sched_ctrl->coreset->controlResourceSetId;
- UE_info->num_pdcch_cand[UE_id][cid]--;
- int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp?sched_ctrl->active_bwp->bwp_Id:0][cid];
- for (int i = 0; i < sched_ctrl->aggregation_level; i++)
- cce_list[sched_ctrl->cce_index + i] = 0;
+ RC.nrmac[module_id]->pdcch_cand[cid]--;
return false;
}
+ sched_ctrl->cce_index = CCEIndex;
+
+ fill_pdcch_vrb_map(RC.nrmac[module_id],
+ /* CC_id = */ 0,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
/* just reuse from previous scheduling opportunity, set new start RB */
sched_ctrl->sched_pdsch = *retInfo;
sched_ctrl->sched_pdsch.rbStart = rbStart;
@@ -642,7 +670,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
/* retransmissions: directly allocate */
*n_rb_sched -= sched_ctrl->sched_pdsch.rbSize;
for (int rb = 0; rb < sched_ctrl->sched_pdsch.rbSize; rb++)
- rballoc_mask[rb + sched_ctrl->sched_pdsch.rbStart] = 0;
+ rballoc_mask[rb + sched_ctrl->sched_pdsch.rbStart] -= SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
return true;
}
@@ -655,7 +683,7 @@ void pf_dl(module_id_t module_id,
NR_list_t *UE_list,
int max_num_ue,
int n_rb_sched,
- uint8_t *rballoc_mask) {
+ uint16_t *rballoc_mask) {
gNB_MAC_INST *mac = RC.nrmac[module_id];
NR_UE_info_t *UE_info = &mac->UE_info;
@@ -745,7 +773,6 @@ void pf_dl(module_id_t module_id,
NR_BWP_DownlinkDedicated_t *bwpd= cg ? cg->spCellConfig->spCellConfigDedicated->initialDownlinkBWP:NULL;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
- int bwp_Id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
const uint16_t rnti = UE_info->rnti[UE_id];
NR_BWP_t *genericParameters = sched_ctrl->active_bwp ?
&sched_ctrl->active_bwp->bwp_Common->genericParameters:
@@ -760,8 +787,27 @@ void pf_dl(module_id_t module_id,
}
/* Find a free CCE */
- bool freeCCE = find_free_CCE(module_id, slot, UE_id);
- if (!freeCCE) {
+ const int cid = sched_ctrl->coreset->controlResourceSetId;
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+ uint8_t nr_of_candidates;
+ for (int i=0; i<5; i++) {
+ // for now taking the lowest value among the available aggregation levels
+ find_aggregation_candidates(&sched_ctrl->aggregation_level,
+ &nr_of_candidates,
+ sched_ctrl->search_space,
+ 1<<i);
+ if(nr_of_candidates>0) break;
+ }
+
+ int CCEIndex = find_pdcch_candidate(mac,
+ /* CC_id = */ 0,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
+ if (CCEIndex<0) {
LOG_D(NR_MAC, "%4d.%2d could not find CCE for DL DCI UE %d/RNTI %04x\n", frame, slot, UE_id, rnti);
continue;
}
@@ -780,20 +826,17 @@ void pf_dl(module_id_t module_id,
rnti,
frame,
slot);
- int cid = sched_ctrl->coreset->controlResourceSetId;
- UE_info->num_pdcch_cand[UE_id][cid]--;
- int *cce_list = mac->cce_list[bwp_Id][cid];
- for (int i = 0; i < sched_ctrl->aggregation_level; i++)
- cce_list[sched_ctrl->cce_index + i] = 0;
+ mac->pdcch_cand[cid]--;
return;
}
- // Freq-demain allocation
- while (rbStart < bwpSize && !rballoc_mask[rbStart]) rbStart++;
+ sched_ctrl->cce_index = CCEIndex;
- uint16_t max_rbSize = 1;
- while (rbStart + max_rbSize < bwpSize && rballoc_mask[rbStart + max_rbSize])
- max_rbSize++;
+ fill_pdcch_vrb_map(mac,
+ /* CC_id = */ 0,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
/* MCS has been set above */
@@ -804,6 +847,18 @@ void pf_dl(module_id_t module_id,
if (ps->nrOfLayers != layers[UE_id] ||
ps->time_domain_allocation != tda)
nr_set_pdsch_semi_static(scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, bwpd, tda, layers[UE_id], sched_ctrl, ps);
+
+ const uint16_t slbitmap = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
+ // Freq-demain allocation
+ while (rbStart < bwpSize &&
+ !(rballoc_mask[rbStart]&slbitmap))
+ rbStart++;
+
+ uint16_t max_rbSize = 1;
+ while (rbStart + max_rbSize < bwpSize &&
+ (rballoc_mask[rbStart + max_rbSize]&slbitmap))
+ max_rbSize++;
+
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->pucch_allocation = alloc;
@@ -826,7 +881,7 @@ void pf_dl(module_id_t module_id,
/* transmissions: directly allocate */
n_rb_sched -= sched_pdsch->rbSize;
for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
- rballoc_mask[rb + sched_pdsch->rbStart] = 0;
+ rballoc_mask[rb + sched_pdsch->rbStart] -= slbitmap;
}
}
@@ -839,9 +894,18 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
const int CC_id = 0;
- /* Get bwpSize from the first UE */
+ /* Get bwpSize and TDAfrom the first UE */
+ /* This is temporary and it assumes all UEs have the same BWP and TDA*/
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
+ int startSymbolIndex, nrOfSymbols;
+ const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = sched_ctrl->active_bwp ?
+ sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList :
+ scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
+ AssertFatal(tda < tdaList->list.count, "time_domain_allocation %d>=%d\n", tda, tdaList->list.count);
+ const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
+ SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp ?
sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth:
@@ -852,14 +916,18 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,
MAX_BWP_SIZE);
+ const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
- uint8_t rballoc_mask[bwpSize];
+ uint16_t rballoc_mask[bwpSize];
int n_rb_sched = 0;
for (int i = 0; i < bwpSize; i++) {
// calculate mask: init with "NOT" vrb_map:
// if any RB in vrb_map is blocked (1), the current RBG will be 0
- rballoc_mask[i] = !vrb_map[i+BWPStart];
- n_rb_sched += rballoc_mask[i];
+ rballoc_mask[i] = (~vrb_map[i+BWPStart])&0x3fff; //bitwise not and 14 symbols
+ // if all the pdsch symbols are free
+ if((rballoc_mask[i]&slbitmap) ==
+ slbitmap)
+ n_rb_sched++;
}
/* Retrieve amount of data to send for this UE */
@@ -1014,7 +1082,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
const int bwpid = bwp ? bwp->bwp_Id : 0;
const int coresetid = (bwp||bwpd) ? sched_ctrl->coreset->controlResourceSetId : gNB_mac->sched_ctrlCommon->coreset->controlResourceSetId;
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = gNB_mac->pdcch_pdu_idx[CC_id][coresetid];
if (!pdcch_pdu) {
LOG_D(NR_MAC, "creating pdcch pdu, pdcch_pdu = NULL. \n");
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
@@ -1024,10 +1092,9 @@ void nr_schedule_ue_spec(module_id_t module_id,
dl_req->nPDUs += 1;
pdcch_pdu = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
LOG_D(NR_MAC,"Trying to configure DL pdcch for UE %d, bwp %d, cs %d\n",UE_id,bwpid,coresetid);
- NR_SearchSpace_t *ss = (bwp||bwpd) ? sched_ctrl->search_space:gNB_mac->sched_ctrlCommon->search_space;
NR_ControlResourceSet_t *coreset = (bwp||bwpd)? sched_ctrl->coreset:gNB_mac->sched_ctrlCommon->coreset;
- nr_configure_pdcch(gNB_mac, pdcch_pdu, ss, coreset, scc, genericParameters, NULL);
- gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu;
+ nr_configure_pdcch(pdcch_pdu, coreset, genericParameters, &sched_ctrl->sched_pdcch);
+ gNB_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
}
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
index d17e20fb1fe3eb053f6765e4b4c92626308566df..633ff0e54cec4897391bbf67ea0d6db158ef5aae 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
@@ -278,6 +278,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
__func__,
UE_id);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
+ const long f = sched_ctrl->active_bwp ? sched_ctrl->search_space->searchSpaceType->choice.ue_Specific->dci_Formats : 0;
+ NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
+ ps->nrOfLayers = target_dl_Nl;
+ if (ps->time_domain_allocation != tda)
+ nr_set_pdsch_semi_static(
+ scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, NULL, tda, f, ps);
+
/* find largest unallocated chunk */
const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
const int BWPStart = NRRIV2PRBOFFSET(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
@@ -289,11 +297,14 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* loop ensures that we allocate exactly target_dl_bw, or return */
while (true) {
/* advance to first free RB */
- while (rbStart < bwpSize && vrb_map[rbStart + BWPStart])
+ while (rbStart < bwpSize &&
+ (vrb_map[rbStart + BWPStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)))
rbStart++;
rbSize = 1;
/* iterate until we are at target_dl_bw or no available RBs */
- while (rbStart + rbSize < bwpSize && !vrb_map[rbStart + rbSize + BWPStart] && rbSize < target_dl_bw)
+ while (rbStart + rbSize < bwpSize &&
+ !(vrb_map[rbStart + rbSize + BWPStart]&SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols)) &&
+ rbSize < target_dl_bw)
rbSize++;
/* found target_dl_bw? */
if (rbSize == target_dl_bw)
@@ -334,16 +345,17 @@ void nr_preprocessor_phytest(module_id_t module_id,
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
- const uint16_t Y = UE_info->Y[UE_id][cid][slot];
- const int m = UE_info->num_pdcch_cand[UE_id][cid];
- sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
- sched_ctrl->active_bwp,
- sched_ctrl->coreset,
- sched_ctrl->aggregation_level,
- Y,
- m,
- nr_of_candidates);
- AssertFatal(sched_ctrl->cce_index >= 0,
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+
+ int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
+ CC_id,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
+ AssertFatal(CCEIndex >= 0,
"%s(): could not find CCE for UE %d\n",
__func__,
UE_id);
@@ -357,19 +369,23 @@ void nr_preprocessor_phytest(module_id_t module_id,
rnti,
frame,
slot);
- UE_info->num_pdcch_cand[UE_id][cid]--;
- int *cce_list = RC.nrmac[module_id]->cce_list[sched_ctrl->active_bwp->bwp_Id][cid];
- for (int i = 0; i < sched_ctrl->aggregation_level; i++)
- cce_list[sched_ctrl->cce_index + i] = 0;
+ RC.nrmac[module_id]->pdcch_cand[cid]--;
return;
}
+ sched_ctrl->cce_index = CCEIndex;
+
+ fill_pdcch_vrb_map(RC.nrmac[module_id],
+ CC_id,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
//AssertFatal(alloc,
// "could not find uplink slot for PUCCH (RNTI %04x@%d.%d)!\n",
// rnti, frame, slot);
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
- NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
sched_pdsch->pucch_allocation = alloc;
sched_pdsch->rbStart = rbStart;
sched_pdsch->rbSize = rbSize;
@@ -396,7 +412,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
- vrb_map[rb + sched_pdsch->rbStart + BWPStart] = 1;
+ vrb_map[rb + sched_pdsch->rbStart + BWPStart] = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols);
if ((frame&127) == 0) LOG_D(MAC,"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d\n", frame, slot, sched_pdsch->mcs, rbStart,rbSize);
}
@@ -499,20 +515,21 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
- const uint16_t Y = UE_info->Y[UE_id][cid][slot];
- const int m = UE_info->num_pdcch_cand[UE_id][cid];
- sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
- sched_ctrl->active_bwp,
- sched_ctrl->coreset,
- sched_ctrl->aggregation_level,
- Y,
- m,
- nr_of_candidates);
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+
+ int CCEIndex = find_pdcch_candidate(nr_mac,
+ CC_id,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
if (sched_ctrl->cce_index < 0) {
LOG_E(MAC, "%s(): CCE list not empty, couldn't schedule PUSCH\n", __func__);
+ nr_mac->pdcch_cand[cid]--;
return false;
}
- UE_info->num_pdcch_cand[UE_id][cid]++;
const int mcs = target_ul_mcs;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
@@ -541,6 +558,12 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
>> 3;
/* mark the corresponding RBs as used */
+ fill_pdcch_vrb_map(nr_mac,
+ CC_id,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
for (int rb = rbStart; rb < rbStart + rbSize; rb++)
vrb_map_UL[rb+BWPStart] = 1;
return true;
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
index 386a2032f9e95697de7614b70b9f8dba3bfdd8f2..21e8419884cd0388183d9a2fe00c7e7f1edc5cbe 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
@@ -232,6 +232,7 @@ NR_ControlResourceSet_t *get_coreset(module_id_t module_idP,
NR_SearchSpace_t *ss,
NR_SearchSpace__searchSpaceType_PR ss_type) {
NR_ControlResourceSetId_t coreset_id = *ss->controlResourceSetId;
+
if (ss_type == NR_SearchSpace__searchSpaceType_PR_common) { // common search space
NR_ControlResourceSet_t *coreset;
if(coreset_id == 0) {
@@ -281,53 +282,181 @@ NR_SearchSpace_t *get_searchspace(NR_ServingCellConfigCommon_t *scc,
AssertFatal(0, "Couldn't find an adequate searchspace bwp_Dedicated %p\n",bwp_Dedicated);
}
-int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
- NR_BWP_Downlink_t *bwp,
- NR_ControlResourceSet_t *coreset,
- int aggregation,
- uint16_t Y,
- int m,
- int nr_of_candidates) {
+NR_sched_pdcch_t set_pdcch_structure(gNB_MAC_INST *gNB_mac,
+ NR_SearchSpace_t *ss,
+ NR_ControlResourceSet_t *coreset,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_t *bwp,
+ NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config) {
- int coreset_id = coreset->controlResourceSetId;
+ int sps;
+ NR_sched_pdcch_t pdcch;
- int *cce_list;
- if(bwp == NULL) {
- cce_list = nr_mac->cce_list[0][coreset_id];
- } else {
- cce_list = nr_mac->cce_list[bwp->bwp_Id][coreset_id];
+ AssertFatal(*ss->controlResourceSetId == coreset->controlResourceSetId,
+ "coreset id in SS %ld does not correspond to the one in coreset %ld",
+ *ss->controlResourceSetId, coreset->controlResourceSetId);
+
+ if (bwp) { // This is not for SIB1
+ if(coreset->controlResourceSetId == 0){
+ pdcch.BWPSize = gNB_mac->cset0_bwp_size;
+ pdcch.BWPStart = gNB_mac->cset0_bwp_start;
+ }
+ else {
+ pdcch.BWPSize = NRRIV2BW(bwp->locationAndBandwidth, MAX_BWP_SIZE);
+ pdcch.BWPStart = NRRIV2PRBOFFSET(bwp->locationAndBandwidth, MAX_BWP_SIZE);
+ }
+ pdcch.SubcarrierSpacing = bwp->subcarrierSpacing;
+ pdcch.CyclicPrefix = (bwp->cyclicPrefix==NULL) ? 0 : *bwp->cyclicPrefix;
+
+ //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
+ sps = bwp->cyclicPrefix == NULL ? 14 : 12;
+ }
+ else {
+ AssertFatal(type0_PDCCH_CSS_config!=NULL,"type0_PDCCH_CSS_config is null,bwp %p\n",bwp);
+ pdcch.BWPSize = type0_PDCCH_CSS_config->num_rbs;
+ pdcch.BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
+ pdcch.SubcarrierSpacing = type0_PDCCH_CSS_config->scs_pdcch;
+ pdcch.CyclicPrefix = 0;
+ sps = 14;
}
- int n_rb=0;
- for (int i=0;i<6;i++)
- for (int j=0;j<8;j++) {
- n_rb+=((coreset->frequencyDomainResources.buf[i]>>j)&1);
+ AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
+ AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
+
+ // for SPS=14 8 MSBs in positions 13 downto 6
+ uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
+ (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
+
+ for (int i=0; i<sps; i++) {
+ if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
+ pdcch.StartSymbolIndex=i;
+ break;
}
- n_rb*=6;
+ }
- uint16_t N_reg = n_rb * coreset->duration;
- uint16_t n_CI = 0;
+ pdcch.DurationSymbols = coreset->duration;
- const uint16_t N_cce = N_reg / NR_NB_REG_PER_CCE;
- const uint16_t M_s_max = nr_of_candidates;
+ //cce-REG-MappingType
+ pdcch.CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
+ NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
- LOG_D(PHY,"allocate_NR_CCes : bwp_id %d, coreset_id %d : N_cce %d, m %d, nr_of_candidates %d, Y %d\n",
- (int)(bwp ? bwp->bwp_Id : 0),coreset_id,N_cce,m,nr_of_candidates, Y);
- //PDCCH candidate index m in CORESET exceeds the maximum number of PDCCH candidates
- if(m >= nr_of_candidates)
- return -1;
+ if (pdcch.CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
+ pdcch.RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize ==
+ NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
+ pdcch.InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize ==
+ NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize);
+ AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n");
+ pdcch.ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
+ }
+ else {
+ pdcch.RegBundleSize = 6;
+ pdcch.InterleaverSize = 0;
+ pdcch.ShiftIndex = 0;
+ }
- int first_cce = aggregation * (( Y + CEILIDIV((m*N_cce),(aggregation*M_s_max)) + n_CI ) % CEILIDIV(N_cce,aggregation));
+ int N_rb = 0; // nb of rbs of coreset per symbol
+ for (int i=0;i<6;i++) {
+ for (int t=0;t<8;t++) {
+ N_rb+=((coreset->frequencyDomainResources.buf[i]>>t)&1);
+ }
+ }
+ pdcch.n_rb = N_rb*=6; // each bit of frequencyDomainResources represents 6 PRBs
- for (int i=0;i<aggregation;i++)
- if (cce_list[first_cce+i] != 0) return(-1);
-
- for (int i=0;i<aggregation;i++) cce_list[first_cce+i] = 1;
+ return pdcch;
+}
+
+
+int cce_to_reg_interleaving(const int R, int k, int n_shift, const int C, int L, const int N_regs) {
+
+ int f; // interleaving function
+ if(R==0)
+ f = k;
+ else {
+ int c = k/R;
+ int r = k%R;
+ f = (r*C + c + n_shift)%(N_regs/L);
+ }
+ return f;
+}
+
+uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
+ int cc_id,
+ int aggregation,
+ int nr_of_candidates,
+ NR_sched_pdcch_t *pdcch,
+ NR_ControlResourceSet_t *coreset,
+ uint16_t Y){
- return(first_cce);
+ uint16_t *vrb_map = mac->common_channels[cc_id].vrb_map;
+ const int next_cand = mac->pdcch_cand[coreset->controlResourceSetId];
+ const int N_ci = 0;
+
+ if(next_cand>=nr_of_candidates) {
+ LOG_D(NR_MAC,"No more available candidates for this coreset\n");
+ return -1;
+ }
+
+ const int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
+ const int N_symb = coreset->duration; // nb of coreset symbols
+ const int N_regs = N_rb*N_symb; // nb of REGs per coreset
+ const int N_cces = N_regs / NR_NB_REG_PER_CCE; // nb of cces in coreset
+ const int R = pdcch->InterleaverSize;
+ const int L = pdcch->RegBundleSize;
+ const int C = R>0 ? N_regs/(L*R) : 0;
+ const int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
+
+ int first_cce;
+ bool taken = false; // flag if the resource for a given candidate are taken
+ // loop over all the available candidates
+ // this implements TS 38.211 Sec. 7.3.2.2
+ for(int m=next_cand; m<nr_of_candidates; m++) { // loop over candidates
+ first_cce = aggregation * (( Y + CEILIDIV((m*N_cces),(aggregation*nr_of_candidates)) + N_ci ) % CEILIDIV(N_cces,aggregation));
+ for (int j=first_cce; (j<first_cce+aggregation) && !taken; j++) { // loop over CCEs
+ for (int k=6*j/L; (k<(6*j/L+6/L)) && !taken; k++) { // loop over REG bundles
+ int f = cce_to_reg_interleaving(R, k, pdcch->ShiftIndex, C, L, N_regs);
+ for(int rb=0; rb<B_rb; rb++) { // loop over the RBs of the bundle
+ if(vrb_map[pdcch->BWPStart + f*B_rb + rb]&SL_to_bitmap(pdcch->StartSymbolIndex,N_symb)) {
+ taken = true;
+ break;
+ }
+ }
+ }
+ }
+ if(!taken){
+ mac->pdcch_cand[coreset->controlResourceSetId] = m++; // using candidate m, next available is m+1
+ return first_cce;
+ }
+ }
+ return -1;
+}
+void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
+ int CC_id,
+ NR_sched_pdcch_t *pdcch,
+ int first_cce,
+ int aggregation){
+
+ uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map;
+
+ int N_rb = pdcch->n_rb; // nb of rbs of coreset per symbol
+ int L = pdcch->RegBundleSize;
+ int R = pdcch->InterleaverSize;
+ int n_shift = pdcch->ShiftIndex;
+ int N_symb = pdcch->DurationSymbols;
+ int N_regs = N_rb*N_symb; // nb of REGs per coreset
+ int B_rb = L/N_symb; // nb of RBs occupied by each REG bundle
+ int C = R>0 ? N_regs/(L*R) : 0;
+
+ for (int j=first_cce; j<first_cce+aggregation; j++) { // loop over CCEs
+ for (int k=6*j/L; k<(6*j/L+6/L); k++) { // loop over REG bundles
+ int f = cce_to_reg_interleaving(R, k, n_shift, C, L, N_regs);
+ for(int rb=0; rb<B_rb; rb++) // loop over the RBs of the bundle
+ vrb_map[pdcch->BWPStart + f*B_rb + rb] |= SL_to_bitmap(pdcch->StartSymbolIndex, N_symb);
+ }
+ }
}
+
bool nr_find_nb_rb(uint16_t Qm,
uint16_t R,
uint8_t nrOfLayers,
@@ -836,81 +965,32 @@ int nr_get_default_pucch_res(int pucch_ResourceCommon) {
return(default_pucch_csset[pucch_ResourceCommon]);
}
-void nr_configure_pdcch(gNB_MAC_INST *gNB_mac,
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
- NR_SearchSpace_t *ss,
- NR_ControlResourceSet_t *coreset,
- NR_ServingCellConfigCommon_t *scc,
- NR_BWP_t *bwp,
- NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config) {
-
- int sps;
- AssertFatal(*ss->controlResourceSetId == coreset->controlResourceSetId,
- "coreset id in SS %ld does not correspond to the one in coreset %ld",
- *ss->controlResourceSetId, coreset->controlResourceSetId);
- if (bwp) { // This is not for SIB1
- if(coreset->controlResourceSetId == 0){
- pdcch_pdu->BWPSize = gNB_mac->cset0_bwp_size;
- pdcch_pdu->BWPStart = gNB_mac->cset0_bwp_start;
- }
- else {
- pdcch_pdu->BWPSize = NRRIV2BW(bwp->locationAndBandwidth, MAX_BWP_SIZE);
- pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->locationAndBandwidth, MAX_BWP_SIZE);
- }
- pdcch_pdu->SubcarrierSpacing = bwp->subcarrierSpacing;
- pdcch_pdu->CyclicPrefix = (bwp->cyclicPrefix==NULL) ? 0 : *bwp->cyclicPrefix;
- //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
- sps = bwp->cyclicPrefix == NULL ? 14 : 12;
- }
- else {
- AssertFatal(type0_PDCCH_CSS_config!=NULL,"type0_PDCCH_CSS_config is null,bwp %p\n",bwp);
- pdcch_pdu->BWPSize = type0_PDCCH_CSS_config->num_rbs;
- pdcch_pdu->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
- pdcch_pdu->SubcarrierSpacing = type0_PDCCH_CSS_config->scs_pdcch;
- pdcch_pdu->CyclicPrefix = 0;
- sps = 14;
- }
+void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
+ NR_ControlResourceSet_t *coreset,
+ NR_BWP_t *bwp,
+ NR_sched_pdcch_t *pdcch) {
- AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
- AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
-
- // for SPS=14 8 MSBs in positions 13 downto 6
- uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
- (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
- for (int i=0; i<sps; i++) {
- if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
- pdcch_pdu->StartSymbolIndex=i;
- break;
- }
- }
+ pdcch_pdu->BWPSize = pdcch->BWPSize;
+ pdcch_pdu->BWPStart = pdcch->BWPStart;
+ pdcch_pdu->SubcarrierSpacing = pdcch->SubcarrierSpacing;
+ pdcch_pdu->CyclicPrefix = pdcch->CyclicPrefix;
+ pdcch_pdu->StartSymbolIndex = pdcch->StartSymbolIndex;
pdcch_pdu->DurationSymbols = coreset->duration;
for (int i=0;i<6;i++)
pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i];
- LOG_D(MAC,"Coreset : BWPstart %d, BWPsize %d, SCS %d, freq %x, , duration %d, \n",pdcch_pdu->BWPStart,pdcch_pdu->BWPSize,(int)pdcch_pdu->SubcarrierSpacing,(int)coreset->frequencyDomainResources.buf[0],(int)coreset->duration);
-
- //cce-REG-MappingType
- pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
- NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
+ LOG_D(MAC,"Coreset : BWPstart %d, BWPsize %d, SCS %d, freq %x, , duration %d, \n",
+ pdcch_pdu->BWPStart,pdcch_pdu->BWPSize,(int)pdcch_pdu->SubcarrierSpacing,(int)coreset->frequencyDomainResources.buf[0],(int)coreset->duration);
- if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
- pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize ==
- NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
- pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize ==
- NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize);
- AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n");
- pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
- }
- else {
- pdcch_pdu->RegBundleSize = 0;
- pdcch_pdu->InterleaverSize = 0;
- pdcch_pdu->ShiftIndex = 0;
- }
+ pdcch_pdu->CceRegMappingType = pdcch->CceRegMappingType;
+ pdcch_pdu->RegBundleSize = pdcch->RegBundleSize;
+ pdcch_pdu->InterleaverSize = pdcch->InterleaverSize;
+ pdcch_pdu->ShiftIndex = pdcch->ShiftIndex;
if(coreset->controlResourceSetId == 0) {
if(bwp == NULL)
@@ -1962,19 +2042,18 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP)
return -1;
}
-void set_Y(int Y[3][160], rnti_t rnti) {
+uint16_t get_Y(int cid, int slot, rnti_t rnti) {
+
const int A[3] = {39827, 39829, 39839};
const int D = 65537;
+ int Y;
- Y[0][0] = (A[0] * rnti) % D;
- Y[1][0] = (A[1] * rnti) % D;
- Y[2][0] = (A[2] * rnti) % D;
+ Y = (A[cid] * rnti) % D;
- for (int s = 1; s < 160; s++) {
- Y[0][s] = (A[0] * Y[0][s - 1]) % D;
- Y[1][s] = (A[1] * Y[1][s - 1]) % D;
- Y[2][s] = (A[2] * Y[2][s - 1]) % D;
- }
+ for (int s = 0; s < slot; s++)
+ Y = (A[cid] * Y) % D;
+
+ return Y;
}
int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP) {
@@ -2090,8 +2169,12 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellG
if (bwpList) AssertFatal(bwpList->list.count == 1,
"downlinkBWP_ToAddModList has %d BWP!\n",
bwpList->list.count);
+
const int bwp_id = servingCellConfig ? *servingCellConfig->firstActiveDownlinkBWP_Id : 0;
sched_ctrl->active_bwp = bwpList && bwp_id > 0 ? bwpList->list.array[bwp_id - 1] : NULL;
+ NR_BWP_t *genericParameters = sched_ctrl->active_bwp ?
+ &sched_ctrl->active_bwp->bwp_Common->genericParameters:
+ &scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
const int target_ss = sched_ctrl->active_bwp ? NR_SearchSpace__searchSpaceType_PR_ue_Specific : NR_SearchSpace__searchSpaceType_PR_common;
sched_ctrl->search_space = get_searchspace(scc,
sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Dedicated : NULL,
@@ -2099,6 +2182,12 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellG
sched_ctrl->coreset = get_coreset(mod_idP, scc,
sched_ctrl->active_bwp ? (void*)sched_ctrl->active_bwp->bwp_Dedicated : NULL,
sched_ctrl->search_space, target_ss);
+ sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[mod_idP],
+ sched_ctrl->search_space,
+ sched_ctrl->coreset,
+ scc,
+ genericParameters,
+ NULL);
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig ? servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList : NULL;
if (ubwpList) AssertFatal(ubwpList->list.count == 1,
"uplinkBWP_ToAddModList has %d BWP!\n",
@@ -2400,20 +2489,20 @@ void nr_csirs_scheduling(int Mod_idP,
csirs_pdu_rel15->row = 1;
csirs_pdu_rel15->freq_domain = ((resourceMapping.frequencyDomainAllocation.choice.row1.buf[0])>>4)&0x0f;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
break;
case NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row2:
csirs_pdu_rel15->row = 2;
csirs_pdu_rel15->freq_domain = (((resourceMapping.frequencyDomainAllocation.choice.row2.buf[1]>>4)&0x0f) |
((resourceMapping.frequencyDomainAllocation.choice.row2.buf[0]<<8)&0xff0));
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
break;
case NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row4:
csirs_pdu_rel15->row = 4;
csirs_pdu_rel15->freq_domain = ((resourceMapping.frequencyDomainAllocation.choice.row4.buf[0])>>5)&0x07;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
break;
case NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other:
csirs_pdu_rel15->freq_domain = ((resourceMapping.frequencyDomainAllocation.choice.other.buf[0])>>2)&0x3f;
@@ -2424,18 +2513,18 @@ void nr_csirs_scheduling(int Mod_idP,
case NR_CSI_RS_ResourceMapping__nrofPorts_p2:
csirs_pdu_rel15->row = 3;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
break;
case NR_CSI_RS_ResourceMapping__nrofPorts_p4:
csirs_pdu_rel15->row = 5;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((1 << csirs_pdu_rel15->symb_l0) | (2 << csirs_pdu_rel15->symb_l0));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2);
break;
case NR_CSI_RS_ResourceMapping__nrofPorts_p8:
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2) {
csirs_pdu_rel15->row = 8;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((1 << csirs_pdu_rel15->symb_l0) | (2 << csirs_pdu_rel15->symb_l0));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2);
}
else{
int num_k = 0;
@@ -2444,12 +2533,12 @@ void nr_csirs_scheduling(int Mod_idP,
if(num_k==4) {
csirs_pdu_rel15->row = 6;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
}
else {
csirs_pdu_rel15->row = 7;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((1 << csirs_pdu_rel15->symb_l0) | (2 << csirs_pdu_rel15->symb_l0));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2);
}
}
break;
@@ -2457,12 +2546,12 @@ void nr_csirs_scheduling(int Mod_idP,
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2) {
csirs_pdu_rel15->row = 10;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((1 << csirs_pdu_rel15->symb_l0) | (2 << csirs_pdu_rel15->symb_l0));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2);
}
else {
csirs_pdu_rel15->row = 9;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (1 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 1);
}
break;
case NR_CSI_RS_ResourceMapping__nrofPorts_p16:
@@ -2471,24 +2560,24 @@ void nr_csirs_scheduling(int Mod_idP,
else
csirs_pdu_rel15->row = 11;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((1 << csirs_pdu_rel15->symb_l0) | (2 << csirs_pdu_rel15->symb_l0));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2);
break;
case NR_CSI_RS_ResourceMapping__nrofPorts_p24:
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2) {
csirs_pdu_rel15->row = 14;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((3 << csirs_pdu_rel15->symb_l0) | (3 << csirs_pdu_rel15->symb_l1));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2) | SL_to_bitmap(csirs_pdu_rel15->symb_l1, 2));
}
else{
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4) {
csirs_pdu_rel15->row = 15;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (7 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 3);
}
else {
csirs_pdu_rel15->row = 13;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((3 << csirs_pdu_rel15->symb_l0) | (3 << csirs_pdu_rel15->symb_l1));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2) | SL_to_bitmap(csirs_pdu_rel15->symb_l1, 2));
}
}
break;
@@ -2496,18 +2585,18 @@ void nr_csirs_scheduling(int Mod_idP,
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2) {
csirs_pdu_rel15->row = 17;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((3 << csirs_pdu_rel15->symb_l0) | (3 << csirs_pdu_rel15->symb_l1));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2) | SL_to_bitmap(csirs_pdu_rel15->symb_l1, 2));
}
else{
if (resourceMapping.cdm_Type == NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4) {
csirs_pdu_rel15->row = 18;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (7 << csirs_pdu_rel15->symb_l0);
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= SL_to_bitmap(csirs_pdu_rel15->symb_l0, 3);
}
else {
csirs_pdu_rel15->row = 16;
for (int rb = csirs_pdu_rel15->start_rb; rb < (csirs_pdu_rel15->start_rb + csirs_pdu_rel15->nr_of_rbs); rb++)
- vrb_map[rb+csirs_pdu_rel15->bwp_start] |= ((3 << csirs_pdu_rel15->symb_l0) | (3 << csirs_pdu_rel15->symb_l1));
+ vrb_map[rb+csirs_pdu_rel15->bwp_start] |= (SL_to_bitmap(csirs_pdu_rel15->symb_l0, 2) | SL_to_bitmap(csirs_pdu_rel15->symb_l1, 2));
}
}
break;
@@ -2525,38 +2614,6 @@ void nr_csirs_scheduling(int Mod_idP,
}
}
-bool find_free_CCE(module_id_t module_id,
- sub_frame_t slot,
- int UE_id){
- NR_UE_sched_ctrl_t *sched_ctrl = &RC.nrmac[module_id]->UE_info.UE_sched_ctrl[UE_id];
- uint8_t nr_of_candidates;
- for (int i=0; i<5; i++) {
- // for now taking the lowest value among the available aggregation levels
- find_aggregation_candidates(&sched_ctrl->aggregation_level,
- &nr_of_candidates,
- sched_ctrl->search_space,
- 1<<i);
- if(nr_of_candidates>0) break;
- }
- AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
- const int cid = sched_ctrl->coreset->controlResourceSetId;
- const uint16_t Y = RC.nrmac[module_id]->UE_info.Y[UE_id][cid][slot];
- const int m = RC.nrmac[module_id]->UE_info.num_pdcch_cand[UE_id][cid];
- if (UE_id >= 0) LOG_D(NR_MAC,"calling allocate_nr_CCEs with L %d, nr_of_candidates %d, Y %x\n",sched_ctrl->aggregation_level,nr_of_candidates,Y);
- sched_ctrl->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
- sched_ctrl->active_bwp,
- sched_ctrl->coreset,
- sched_ctrl->aggregation_level,
- Y,
- m,
- nr_of_candidates);
- if (sched_ctrl->cce_index < 0)
- return false;
-
- RC.nrmac[module_id]->UE_info.num_pdcch_cand[UE_id][cid]++;
- return true;
-}
-
/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg,
nfapi_nr_coreset_t *coreset,
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
index 106df26b5528402de9207fabf3aa96b16cdb45cb..970e828c9c2f681371fb156bb3739e887540546e 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
@@ -1014,13 +1014,38 @@ bool allocate_ul_retransmission(module_id_t module_id,
sched_ctrl->sched_pusch = *retInfo;
}
- /* Find free CCE */
- bool freeCCE = find_free_CCE(module_id, slot, UE_id);
- if (!freeCCE) {
+ /* Find a free CCE */
+ const int cid = sched_ctrl->coreset->controlResourceSetId;
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+ uint8_t nr_of_candidates;
+ for (int i=0; i<5; i++) {
+ // for now taking the lowest value among the available aggregation levels
+ find_aggregation_candidates(&sched_ctrl->aggregation_level,
+ &nr_of_candidates,
+ sched_ctrl->search_space,
+ 1<<i);
+ if(nr_of_candidates>0) break;
+ }
+ int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
+ CC_id,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
+ if (CCEIndex<0) {
LOG_D(NR_MAC, "%4d.%2d no free CCE for retransmission UL DCI UE %04x\n", frame, slot, UE_info->rnti[UE_id]);
return false;
}
+ sched_ctrl->cce_index = CCEIndex;
+ fill_pdcch_vrb_map(RC.nrmac[module_id],
+ CC_id,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
/* frame/slot in sched_pusch has been set previously. In the following, we
* overwrite the information in the retransmission information before storing
* as the new scheduling instruction */
@@ -1135,8 +1160,27 @@ void pf_ul(module_id_t module_id,
* based on data to transmit) */
if (B == 0 && do_sched) {
/* if no data, pre-allocate 5RB */
- bool freeCCE = find_free_CCE(module_id, slot, UE_id);
- if (!freeCCE) {
+ /* Find a free CCE */
+ const int cid = sched_ctrl->coreset->controlResourceSetId;
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+ uint8_t nr_of_candidates;
+ for (int i=0; i<5; i++) {
+ // for now taking the lowest value among the available aggregation levels
+ find_aggregation_candidates(&sched_ctrl->aggregation_level,
+ &nr_of_candidates,
+ sched_ctrl->search_space,
+ 1<<i);
+ if(nr_of_candidates>0) break;
+ }
+ int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
+ CC_id,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+
+ if (CCEIndex<0) {
LOG_D(NR_MAC, "%4d.%2d no free CCE for UL DCI UE %04x (BSR 0)\n", frame, slot, UE_info->rnti[UE_id]);
continue;
}
@@ -1153,6 +1197,13 @@ void pf_ul(module_id_t module_id,
return;
}
+ sched_ctrl->cce_index = CCEIndex;
+ fill_pdcch_vrb_map(RC.nrmac[module_id],
+ CC_id,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
/* Save PUSCH field */
/* we want to avoid a lengthy deduction of DMRS and other parameters in
* every TTI if we can save it, so check whether dci_format, TDA, or
@@ -1218,8 +1269,27 @@ void pf_ul(module_id_t module_id,
*max = UE_sched.next[*max];
*p = -1;
- bool freeCCE = find_free_CCE(module_id, slot, UE_id);
- if (!freeCCE) {
+ NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+
+ const int cid = sched_ctrl->coreset->controlResourceSetId;
+ const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
+ uint8_t nr_of_candidates;
+ for (int i=0; i<5; i++) {
+ // for now taking the lowest value among the available aggregation levels
+ find_aggregation_candidates(&sched_ctrl->aggregation_level,
+ &nr_of_candidates,
+ sched_ctrl->search_space,
+ 1<<i);
+ if(nr_of_candidates>0) break;
+ }
+ int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
+ CC_id,
+ sched_ctrl->aggregation_level,
+ nr_of_candidates,
+ &sched_ctrl->sched_pdcch,
+ sched_ctrl->coreset,
+ Y);
+ if (CCEIndex<0) {
LOG_D(NR_MAC, "%4d.%2d no free CCE for UL DCI UE %04x\n", frame, slot, UE_info->rnti[UE_id]);
continue;
}
@@ -1230,7 +1300,6 @@ void pf_ul(module_id_t module_id,
if (max_num_ue < 0)
return;
- NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
NR_BWP_UplinkDedicated_t *ubwpd= cg ? cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP:NULL;
NR_BWP_t *genericParameters = sched_ctrl->active_ubwp ? &sched_ctrl->active_ubwp->bwp_Common->genericParameters : &scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
@@ -1285,6 +1354,14 @@ void pf_ul(module_id_t module_id,
rbSize, max_rbSize,sched_pusch->tb_size, sched_ctrl->estimated_ul_buffer, sched_ctrl->sched_ul_bytes, B,sched_ctrl->cce_index,ps->num_dmrs_symb,ps->N_PRB_DMRS);
/* Mark the corresponding RBs as used */
+
+ sched_ctrl->cce_index = CCEIndex;
+ fill_pdcch_vrb_map(RC.nrmac[module_id],
+ CC_id,
+ &sched_ctrl->sched_pdcch,
+ CCEIndex,
+ sched_ctrl->aggregation_level);
+
n_rb_sched -= sched_pusch->rbSize;
for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++)
rballoc_mask[rb + sched_ctrl->sched_pusch.rbStart] = 0;
@@ -1441,10 +1518,6 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[CC_id];
ul_dci_req->SFN = frame;
ul_dci_req->Slot = slot;
- /* a PDCCH PDU groups DCIs per BWP and CORESET. Save a pointer to each
- * allocated PDCCH so we can easily allocate UE's DCIs independent of any
- * CORESET order */
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_bwp_coreset[MAX_NUM_BWP][MAX_NUM_CORESET] = {{0}};
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
@@ -1683,7 +1756,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
NR_SearchSpace_t *ss = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->search_space: RC.nrmac[module_id]->sched_ctrlCommon->search_space;
NR_ControlResourceSet_t *coreset = (sched_ctrl->active_bwp || ubwpd) ? sched_ctrl->coreset: RC.nrmac[module_id]->sched_ctrlCommon->coreset;
const int coresetid = coreset->controlResourceSetId;
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = pdcch_pdu_bwp_coreset[bwpid][coresetid];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu = nr_mac->pdcch_pdu_idx[CC_id][coresetid];
if (!pdcch_pdu) {
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu = &ul_dci_req->ul_dci_pdu_list[ul_dci_req->numPdus];
memset(ul_dci_request_pdu, 0, sizeof(nfapi_nr_ul_dci_request_pdus_t));
@@ -1691,8 +1764,8 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
ul_dci_req->numPdus += 1;
- nr_configure_pdcch(nr_mac, pdcch_pdu, ss, coreset, scc, genericParameters, NULL);
- pdcch_pdu_bwp_coreset[bwpid][coresetid] = pdcch_pdu;
+ nr_configure_pdcch(pdcch_pdu, coreset, genericParameters, &sched_ctrl->sched_pdcch);
+ nr_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
}
LOG_D(NR_MAC,"Configuring ULDCI/PDCCH in %d.%d at CCE %d, rnti %x\n", frame,slot,sched_ctrl->cce_index,rnti);
diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
index 5b0dbe584e2dba6254004697a54f6b4a5996917c..4c4028e806e40a69b2c9a9d8fa6562e86a10594d 100644
--- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
@@ -248,13 +248,31 @@ void find_search_space(int ss_type,
NR_BWP_Downlink_t *bwp,
NR_SearchSpace_t *ss);
-void nr_configure_pdcch(gNB_MAC_INST *gNB_mac,
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
- NR_SearchSpace_t *ss,
+void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
NR_ControlResourceSet_t *coreset,
- NR_ServingCellConfigCommon_t *scc,
NR_BWP_t *bwp,
- NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config);
+ NR_sched_pdcch_t *pdcch);
+
+NR_sched_pdcch_t set_pdcch_structure(gNB_MAC_INST *gNB_mac,
+ NR_SearchSpace_t *ss,
+ NR_ControlResourceSet_t *coreset,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_t *bwp,
+ NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config);
+
+uint8_t find_pdcch_candidate(gNB_MAC_INST *mac,
+ int cc_id,
+ int aggregation,
+ int nr_of_candidates,
+ NR_sched_pdcch_t *pdcch,
+ NR_ControlResourceSet_t *coreset,
+ uint16_t Y);
+
+void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
+ int CC_id,
+ NR_sched_pdcch_t *pdcch,
+ int first_cce,
+ int aggregation);
void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *CellGroup,
@@ -301,6 +319,8 @@ void nr_set_pusch_semi_static(const NR_ServingCellConfigCommon_t *scc,
uint8_t num_dmrs_cdm_grps_no_data,
NR_pusch_semi_static_t *ps);
+uint16_t get_Y(int cid, int slot, rnti_t rnti);
+
uint8_t nr_get_tpc(int target, uint8_t cqi, int incr);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
index 3fd51710251064ed7f330d88a872973200a3e233..9cf59569926057015377f4256567f4074789c217 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
@@ -73,7 +73,7 @@
/* Defs */
#define MAX_NUM_BWP 2
-#define MAX_NUM_CORESET 2
+#define MAX_NUM_CORESET 12
#define MAX_NUM_CCE 90
#define MAX_HARQ_ROUNDS 4
/*!\brief Maximum number of random access process */
@@ -103,6 +103,20 @@ typedef struct NR_preamble_ue {
uint8_t *preamble_list;
} NR_preamble_ue_t;
+typedef struct NR_sched_pdcch {
+ uint16_t BWPSize;
+ uint16_t BWPStart;
+ uint8_t CyclicPrefix;
+ uint8_t SubcarrierSpacing;
+ uint8_t StartSymbolIndex;
+ uint8_t CceRegMappingType;
+ uint8_t RegBundleSize;
+ uint8_t InterleaverSize;
+ uint16_t ShiftIndex;
+ uint8_t DurationSymbols;
+ int n_rb;
+} NR_sched_pdcch_t;
+
/*! \brief gNB template for the Random access information */
typedef struct {
/// Flag to indicate this process is active
@@ -165,6 +179,9 @@ typedef struct {
int mac_pdu_length;
/// RA search space
NR_SearchSpace_t *ra_ss;
+ /// RA Coreset
+ NR_ControlResourceSet_t *coreset;
+ NR_sched_pdcch_t sched_pdcch;
// Beam index
uint8_t beam_id;
/// CellGroup for UE that is to come (NSA is non-null, null for SA)
@@ -300,7 +317,6 @@ typedef struct UE_info {
pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact;
} NR_UE_mac_ce_ctrl_t;
-
typedef struct NR_sched_pucch {
int frame;
int ul_slot;
@@ -535,6 +551,7 @@ typedef struct {
/// CCE index and aggregation, should be coherent with cce_list
NR_SearchSpace_t *search_space;
NR_ControlResourceSet_t *coreset;
+ NR_sched_pdcch_t sched_pdcch;
/// CCE index and Aggr. Level are shared for PUSCH/PDSCH allocation decisions
/// corresponding to the sched_pusch/sched_pdsch structures below
@@ -651,12 +668,11 @@ typedef struct {
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *CellGroup[MAX_MOBILES_PER_GNB];
/// CCE indexing
- int Y[MAX_MOBILES_PER_GNB][3][160];
int m[MAX_MOBILES_PER_GNB];
- int num_pdcch_cand[MAX_MOBILES_PER_GNB][MAX_NUM_CORESET];
// UE selected beam index
uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
bool Msg4_ACKed[MAX_MOBILES_PER_GNB];
+
} NR_UE_info_t;
typedef void (*nr_pp_impl_dl)(module_id_t mod_id,
@@ -704,7 +720,7 @@ typedef struct gNB_MAC_INST_s {
/// a PDCCH PDU groups DCIs per BWP and CORESET. The following structure
/// keeps pointers to PDCCH PDUs within DL_req so that we can easily track
/// PDCCH PDUs per CC/BWP/CORESET
- nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_idx[NFAPI_CC_MAX][MAX_NUM_BWP][MAX_NUM_CORESET];
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_idx[NFAPI_CC_MAX][MAX_NUM_CORESET];
/// NFAPI UL TTI Request Structure, simple pointer into structure
/// UL_tti_req_ahead for current frame/slot
nfapi_nr_ul_tti_request_t *UL_tti_req[NFAPI_CC_MAX];
@@ -715,7 +731,7 @@ typedef struct gNB_MAC_INST_s {
nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX];
/// NFAPI DL PDU structure
nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX];
-
+ int pdcch_cand[MAX_NUM_CORESET];
NR_UE_info_t UE_info;
/// UL handle
@@ -743,8 +759,6 @@ typedef struct gNB_MAC_INST_s {
time_stats_t rx_ulsch_sdu; // include rlc_data_ind
/// processing time of eNB PCH scheduler
time_stats_t schedule_pch;
- /// CCE lists
- int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
/// list of allocated beams per period
int16_t *tdd_beam_association;