Commit 64116b90 authored by Elena Lukashova's avatar Elena Lukashova
Browse files

Adding HARQ support for TM4. No fallback to Alamouti yet.

Counting for the number of 2CWs or 1CW retransmissions.
Adding corresponding changes to the phy_scope.
parent e202953c
...@@ -984,8 +984,8 @@ void phy_init_lte_ue__PDSCH( LTE_UE_PDSCH* const pdsch, const LTE_DL_FRAME_PARMS ...@@ -984,8 +984,8 @@ void phy_init_lte_ue__PDSCH( LTE_UE_PDSCH* const pdsch, const LTE_DL_FRAME_PARMS
pdsch->dl_ch_estimates_ext = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); pdsch->dl_ch_estimates_ext = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
pdsch->dl_ch_mag0 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); pdsch->dl_ch_mag0 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
pdsch->dl_ch_magb0 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); pdsch->dl_ch_magb0 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
pdsch->dl_ch_mag1 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); //pdsch->dl_ch_mag1 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
pdsch->dl_ch_magb1 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); //pdsch->dl_ch_magb1 = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
// the allocated memory size is fixed: // the allocated memory size is fixed:
AssertFatal( frame_parms->nb_antennas_rx <= 2, "nb_antennas_rx > 2" ); AssertFatal( frame_parms->nb_antennas_rx <= 2, "nb_antennas_rx > 2" );
...@@ -999,8 +999,8 @@ void phy_init_lte_ue__PDSCH( LTE_UE_PDSCH* const pdsch, const LTE_DL_FRAME_PARMS ...@@ -999,8 +999,8 @@ void phy_init_lte_ue__PDSCH( LTE_UE_PDSCH* const pdsch, const LTE_DL_FRAME_PARMS
pdsch->dl_ch_estimates_ext[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); pdsch->dl_ch_estimates_ext[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
pdsch->dl_ch_mag0[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); pdsch->dl_ch_mag0[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
pdsch->dl_ch_magb0[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); pdsch->dl_ch_magb0[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
pdsch->dl_ch_mag1[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); //pdsch->dl_ch_mag1[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
pdsch->dl_ch_magb1[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); //pdsch->dl_ch_magb1[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
} }
} }
} }
...@@ -1172,29 +1172,34 @@ int phy_init_lte_ue(PHY_VARS_UE *phy_vars_ue, ...@@ -1172,29 +1172,34 @@ int phy_init_lte_ue(PHY_VARS_UE *phy_vars_ue,
ue_pdsch_vars[eNB_id]->rho = (int32_t**)malloc16_clear( frame_parms->nb_antennas_rx*sizeof(int32_t*) ); ue_pdsch_vars[eNB_id]->rho = (int32_t**)malloc16_clear( frame_parms->nb_antennas_rx*sizeof(int32_t*) );
for (int i=0; i<frame_parms->nb_antennas_rx; i++) for (int i=0; i<frame_parms->nb_antennas_rx; i++)
ue_pdsch_vars[eNB_id]->rho[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*(frame_parms->N_RB_DL*12*7*2) ); ue_pdsch_vars[eNB_id]->rho[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*(frame_parms->N_RB_DL*12*7*2) );
ue_pdsch_vars[eNB_id]->dl_ch_rho2_ext = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); ue_pdsch_vars[eNB_id]->dl_ch_rho2_ext = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
for (i=0; i<frame_parms->nb_antennas_rx; i++) for (i=0; i<frame_parms->nb_antennas_rx; i++)
for (j=0; j<4; j++) { for (j=0; j<4; j++) {
const int idx = (j<<1)+i; const int idx = (j<<1)+i;
const size_t num = 7*2*frame_parms->N_RB_DL*12+4; const size_t num = 7*2*frame_parms->N_RB_DL*12+4;
ue_pdsch_vars[eNB_id]->dl_ch_rho2_ext[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); ue_pdsch_vars[eNB_id]->dl_ch_rho2_ext[idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
} }
const size_t num = 7*2*frame_parms->N_RB_DL*12+4; const size_t num = 7*2*frame_parms->N_RB_DL*12+4;
for (k=0;k<8;k++) { //harq_pid for (k=0;k<8;k++) { //harq_pid
for (l=0;l<8;l++) { //round for (l=0;l<8;l++) { //round
ue_pdsch_vars[eNB_id]->rxdataF_comp1[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); ue_pdsch_vars[eNB_id]->rxdataF_comp1[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
ue_pdsch_vars[eNB_id]->dl_ch_rho_ext[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) ); ue_pdsch_vars[eNB_id]->dl_ch_rho_ext[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
// ue_pdsch_vars[eNB_id]->clean_x1[k][l] = (int16_t*)malloc16_clear( sizeof(int32_t) * num); ue_pdsch_vars[eNB_id]->dl_ch_mag1[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
ue_pdsch_vars[eNB_id]->dl_ch_magb1[k][l] = (int32_t**)malloc16_clear( 8*sizeof(int32_t*) );
for (int i=0; i<frame_parms->nb_antennas_rx; i++)
for (int j=0; j<4; j++) { //frame_parms->nb_antennas_tx; j++) // ue_pdsch_vars[eNB_id]->clean_x1[k][l] = (int16_t*)malloc16_clear( sizeof(int32_t) * num);
const int idx = (j<<1)+i;
ue_pdsch_vars[eNB_id]->dl_ch_rho_ext[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); for (int i=0; i<frame_parms->nb_antennas_rx; i++)
ue_pdsch_vars[eNB_id]->rxdataF_comp1[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num ); for (int j=0; j<4; j++) { //frame_parms->nb_antennas_tx; j++)
} const int idx = (j<<1)+i;
ue_pdsch_vars[eNB_id]->dl_ch_rho_ext[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
ue_pdsch_vars[eNB_id]->rxdataF_comp1[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
ue_pdsch_vars[eNB_id]->dl_ch_mag1[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
ue_pdsch_vars[eNB_id]->dl_ch_magb1[k][l][idx] = (int32_t*)malloc16_clear( sizeof(int32_t) * num );
}
} }
} }
......
...@@ -860,7 +860,7 @@ uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti) ...@@ -860,7 +860,7 @@ uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti)
} }
int generate_eNB_dlsch_params_from_dci(int frame, int generate_eNB_dlsch_params_from_dci(int frame,
uint8_t subframe, uint8_t subframe,
void *dci_pdu, void *dci_pdu,
uint16_t rnti, uint16_t rnti,
DCI_format_t dci_format, DCI_format_t dci_format,
...@@ -871,7 +871,7 @@ int generate_eNB_dlsch_params_from_dci(int frame, ...@@ -871,7 +871,7 @@ int generate_eNB_dlsch_params_from_dci(int frame,
uint16_t ra_rnti, uint16_t ra_rnti,
uint16_t p_rnti, uint16_t p_rnti,
uint16_t DL_pmi_single uint16_t DL_pmi_single
) )
{ {
uint8_t harq_pid = UINT8_MAX; uint8_t harq_pid = UINT8_MAX;
...@@ -1551,68 +1551,101 @@ int generate_eNB_dlsch_params_from_dci(int frame, ...@@ -1551,68 +1551,101 @@ int generate_eNB_dlsch_params_from_dci(int frame,
} }
if (frame_parms->nb_antennas_tx == 2) { if (frame_parms->nb_antennas_tx == 2) {
if (dlsch1->active == 1) { // both TBs are active if (dlsch0->active == 1 && dlsch1->active == 1) { // both TBs are active
dlsch0_harq->dl_power_off = 1; dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1; dlsch1_harq->dl_power_off = 1;
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1]; dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1]; dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
switch (tpmi) { switch (tpmi) {
case 0: case 0:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1; dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1; dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,1); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,1);
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0,1); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0,1);
break; break;
case 1: case 1:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj; dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj; dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1);
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1);
break; break;
case 2: // PUSCH precoding case 2: // PUSCH precoding
dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING; dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch0_harq->pmi_alloc = DL_pmi_single; dlsch0_harq->pmi_alloc = DL_pmi_single;
dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING; dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch1_harq->pmi_alloc = DL_pmi_single; dlsch1_harq->pmi_alloc = DL_pmi_single;
break; break;
default: default:
break; break;
} }
} }
else { // only one is active else if (dlsch1->active == 0) { // only one is active
dlsch0_harq->dl_power_off = 1; dlsch0_harq->dl_power_off = 1;
dlsch0_harq->TBS= TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1]; dlsch0_harq->TBS= TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
switch (tpmi) { switch (tpmi) {
case 0 : case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI; dlsch0_harq->mimo_mode = ALAMOUTI;
break; break;
case 1: case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11; dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,0); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0,0);
break; break;
case 2: case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1; dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,0); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,0);
break; break;
case 3: case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j; dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2,0); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2,0);
break; break;
case 4: case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj; dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3,0); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3,0);
break; break;
case 5: case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0; dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
dlsch0_harq->pmi_alloc = DL_pmi_single; dlsch0_harq->pmi_alloc = DL_pmi_single;
break; break;
case 6: case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1; dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
dlsch0_harq->pmi_alloc = DL_pmi_single; dlsch0_harq->pmi_alloc = DL_pmi_single;
break; break;
} }
}
else if (dlsch0->active == 0) { // only one is active
dlsch1_harq->dl_power_off = 1;
dlsch1_harq->TBS= TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
switch (tpmi) {
case 0 :
dlsch1_harq->mimo_mode = ALAMOUTI;
break;
case 1:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0,0);
break;
case 2:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,1,0);
break;
case 3:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,2,0);
break;
case 4:
dlsch1_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,3,0);
break;
case 5:
dlsch1_harq->mimo_mode = PUSCH_PRECODING0;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
case 6:
dlsch1_harq->mimo_mode = PUSCH_PRECODING1;
dlsch1_harq->pmi_alloc = DL_pmi_single;
break;
}
} }
} else if (frame_parms->nb_antennas_tx == 4) { } else if (frame_parms->nb_antennas_tx == 4) {
// fill in later // fill in later
...@@ -2670,6 +2703,20 @@ int generate_eNB_dlsch_params_from_dci(int frame, ...@@ -2670,6 +2703,20 @@ int generate_eNB_dlsch_params_from_dci(int frame,
printf("dlsch0 eNB: mimo_mode %d\n",dlsch0_harq->mimo_mode); printf("dlsch0 eNB: mimo_mode %d\n",dlsch0_harq->mimo_mode);
} }
if (dlsch1) {
printf("dlsch1 eNB: dlsch1 %p\n",dlsch1);
printf("dlsch1 eNB: rnti %x\n",dlsch1->rnti);
printf("dlsch1 eNB: NBRB %d\n",dlsch1_harq->nb_rb);
printf("dlsch1 eNB: rballoc %x\n",dlsch1_harq->rb_alloc[0]);
printf("dlsch1 eNB: harq_pid %d\n",harq_pid);
printf("dlsch1 eNB: round %d\n",dlsch1_harq->round);
printf("dlsch1 eNB: rvidx %d\n",dlsch1_harq->rvidx);
printf("dlsch1 eNB: TBS %d (NPRB %d)\n",dlsch1_harq->TBS,NPRB);
printf("dlsch1 eNB: mcs %d\n",dlsch1_harq->mcs);
printf("dlsch1 eNB: tpmi %d\n",tpmi);
printf("dlsch1 eNB: mimo_mode %d\n",dlsch1_harq->mimo_mode);
}
#endif #endif
// compute DL power control parameters // compute DL power control parameters
...@@ -3794,7 +3841,7 @@ int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci) ...@@ -3794,7 +3841,7 @@ int dump_dci(LTE_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci)
int generate_ue_dlsch_params_from_dci(int frame, int generate_ue_dlsch_params_from_dci(int frame,
uint8_t subframe, uint8_t subframe,
void *dci_pdu, void *dci_pdu,
uint16_t rnti, uint16_t rnti,
DCI_format_t dci_format, DCI_format_t dci_format,
...@@ -4730,10 +4777,11 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4730,10 +4777,11 @@ int generate_ue_dlsch_params_from_dci(int frame,
return(-1); return(-1);
} }
if (frame_type == TDD) /*if (frame_type == TDD)
tbswap = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap; tbswap = ((DCI2_5MHz_2A_TDD_t *)dci_pdu)->tb_swap;
else else
tbswap = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap; tbswap = ((DCI2_5MHz_2A_FDD_t *)dci_pdu)->tb_swap;*/
if (tbswap == 0) { if (tbswap == 0) {
dlsch0 = dlsch[0]; dlsch0 = dlsch[0];
...@@ -4769,16 +4817,16 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4769,16 +4817,16 @@ int generate_ue_dlsch_params_from_dci(int frame,
dlsch1_harq->rb_alloc_odd[2] = dlsch0_harq->rb_alloc_odd[2]; dlsch1_harq->rb_alloc_odd[2] = dlsch0_harq->rb_alloc_odd[2];
dlsch1_harq->rb_alloc_odd[3] = dlsch0_harq->rb_alloc_odd[3]; dlsch1_harq->rb_alloc_odd[3] = dlsch0_harq->rb_alloc_odd[3];
dlsch0_harq->nb_rb = conv_nprb(rah, dlsch0_harq->nb_rb = conv_nprb(rah,
rballoc, rballoc,
frame_parms->N_RB_DL); frame_parms->N_RB_DL);
dlsch1_harq->nb_rb = dlsch0_harq->nb_rb; dlsch1_harq->nb_rb = dlsch0_harq->nb_rb;
dlsch0_harq->mcs = mcs1; dlsch0_harq->mcs = mcs1;
dlsch1_harq->mcs = mcs2; dlsch1_harq->mcs = mcs2;
dlsch0_harq->delta_PUCCH = delta_PUCCH_lut[TPC&3]; dlsch0_harq->delta_PUCCH = delta_PUCCH_lut[TPC&3];
dlsch1_harq->delta_PUCCH = delta_PUCCH_lut[TPC&3]; dlsch1_harq->delta_PUCCH = delta_PUCCH_lut[TPC&3];
dlsch[0]->g_pucch += delta_PUCCH_lut[TPC&3]; dlsch[0]->g_pucch += delta_PUCCH_lut[TPC&3];
dlsch[1]->g_pucch += delta_PUCCH_lut[TPC&3]; dlsch[1]->g_pucch += delta_PUCCH_lut[TPC&3];
/* /*
...@@ -4789,8 +4837,8 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4789,8 +4837,8 @@ int generate_ue_dlsch_params_from_dci(int frame,
*/ */
dlsch0_harq->rvidx = rv1; dlsch0_harq->rvidx = rv1;
dlsch1_harq->rvidx = rv2; dlsch1_harq->rvidx = rv2;
// assume both TBs are active // assume both TBs are active
dlsch0_harq->Nl = 1; dlsch0_harq->Nl = 1;
...@@ -4802,11 +4850,14 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4802,11 +4850,14 @@ int generate_ue_dlsch_params_from_dci(int frame,
// check if either TB is disabled (see 36-213 V8.6 p. 26) // check if either TB is disabled (see 36-213 V8.6 p. 26)
if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) { if ((dlsch0_harq->rvidx == 1) && (dlsch0_harq->mcs == 0)) {
dlsch0_harq->status = DISABLED; dlsch0_harq->status = DISABLED;
dlsch0->active = 0;
} }
if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) { if ((dlsch1_harq->rvidx == 1) && (dlsch1_harq->mcs == 0)) {
dlsch1_harq->status = DISABLED; dlsch1_harq->status = DISABLED;
dlsch1->active = 0;
} }
dlsch0_harq->Nl = 1; dlsch0_harq->Nl = 1;
...@@ -4815,65 +4866,98 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4815,65 +4866,98 @@ int generate_ue_dlsch_params_from_dci(int frame,
// dlsch0->layer_index = tbswap; // dlsch0->layer_index = tbswap;
// dlsch1->layer_index = 1-tbswap; // dlsch1->layer_index = 1-tbswap;
if (dlsch1->active==1) { //two codewords if (dlsch0->active==1 && dlsch1->active==1) { //two TB
dlsch0_harq->dl_power_off = 1; dlsch0_harq->dl_power_off = 1;
dlsch1_harq->dl_power_off = 1; dlsch1_harq->dl_power_off = 1;
switch (tpmi) { switch (tpmi) {
case 0: case 0:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1; dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1; dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODING1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0, 1); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0, 1);
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0, 1); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0, 1);
break; break;
case 1: case 1:
dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj; dlsch0_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj; dlsch1_harq->mimo_mode = DUALSTREAM_UNIFORM_PRECODINGj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1); dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1,1);
dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,1, 1); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,1, 1);
break; break;
case 2: // PUSCH precoding case 2: // PUSCH precoding
dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING; dlsch0_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch0_harq->pmi_alloc = dlsch0->pmi_alloc; dlsch0_harq->pmi_alloc = dlsch0->pmi_alloc;
dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING; dlsch1_harq->mimo_mode = DUALSTREAM_PUSCH_PRECODING;
dlsch1_harq->pmi_alloc = dlsch0->pmi_alloc^0x1555; dlsch1_harq->pmi_alloc = dlsch0->pmi_alloc^0x1555;
break; break;
default: default:
break; break;
} }
} } else if (dlsch1_harq->status == DISABLED) {
else {
dlsch0_harq->dl_power_off = 1; dlsch0_harq->dl_power_off = 1;
switch (tpmi) { switch (tpmi) {
case 0 : case 0 :
dlsch0_harq->mimo_mode = ALAMOUTI; dlsch0_harq->mimo_mode = ALAMOUTI;
break; break;
case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0, 0);
break;
case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1, 0);
break;
case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2, 0);
break;
case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3, 0);
break;
case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0;
// pmi stored from ulsch allocation routine
dlsch0_harq->pmi_alloc = dlsch0->pmi_alloc;
//LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc));
break;
case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1;
LOG_E(PHY,"Unsupported TPMI\n");
return(-1);
break;
}
} else if (dlsch0_harq->status == DISABLED) {
dlsch1_harq->dl_power_off = 1;
switch (tpmi) {
case 0 :
dlsch1_harq->mimo_mode = ALAMOUTI;
break;
case 1: case 1:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING11; dlsch1_harq->mimo_mode = UNIFORM_PRECODING11;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,0, 0); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,0, 0);
break; break;
case 2: case 2:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1m1; dlsch1_harq->mimo_mode = UNIFORM_PRECODING1m1;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,1, 0); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,1, 0);
break; break;
case 3: case 3:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1j; dlsch1_harq->mimo_mode = UNIFORM_PRECODING1j;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,2, 0); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,2, 0);
break; break;
case 4: case 4:
dlsch0_harq->mimo_mode = UNIFORM_PRECODING1mj; dlsch1_harq->mimo_mode = UNIFORM_PRECODING1mj;
dlsch0_harq->pmi_alloc = pmi_extend(frame_parms,3, 0); dlsch1_harq->pmi_alloc = pmi_extend(frame_parms,3, 0);
break; break;
case 5: case 5:
dlsch0_harq->mimo_mode = PUSCH_PRECODING0; dlsch1_harq->mimo_mode = PUSCH_PRECODING0;
// pmi stored from ulsch allocation routine // pmi stored from ulsch allocation routine
dlsch0_harq->pmi_alloc = dlsch0->pmi_alloc; dlsch1_harq->pmi_alloc = dlsch0->pmi_alloc;
//LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc)); //LOG_I(PHY,"XXX using PMI %x\n",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc));
break; break;
case 6: case 6:
dlsch0_harq->mimo_mode = PUSCH_PRECODING1; dlsch1_harq->mimo_mode = PUSCH_PRECODING1;
LOG_E(PHY,"Unsupported TPMI\n"); LOG_E(PHY,"Unsupported TPMI\n");
return(-1); return(-1);
break; break;
} }
} }
...@@ -4882,61 +4966,59 @@ int generate_ue_dlsch_params_from_dci(int frame, ...@@ -4882,61 +4966,59 @@ int generate_ue_dlsch_params_from_dci(int frame,
if (dlsch0->active == 1) { if (dlsch0->active == 1) {
if ((ndi1!=dlsch0_harq->DCINdi) || if ((ndi1!=dlsch0_harq->DCINdi) || (dlsch0_harq->first_tx==1)) {
(dlsch0_harq->first_tx==1)) { dlsch0_harq->round = 0;
dlsch0_harq->round = 0; dlsch0_harq->status = ACTIVE;
dlsch0_harq->status = ACTIVE; dlsch0_harq->DCINdi = ndi1;
dlsch0_harq->DCINdi = ndi1;
if (dlsch0_harq->first_tx==1) { if (dlsch0_harq->first_tx==1) {
LOG_D(PHY,"Format 2 DCI First TX0: Clearing flag\n"); LOG_D(PHY,"Format 2 DCI First TX0: Clearing flag\n");
dlsch0_harq->first_tx = 0; dlsch0_harq->first_tx = 0;
} }
} }
else if (dlsch0_harq->status == SCH_IDLE) { // we got an Ndi = 0 for a previously decoded process, else if (dlsch0_harq->status == SCH_IDLE) { // we got an Ndi = 0 for a previously decoded process,
// this happens if either another harq process in the same // this happens if either another harq process in the same
// is NAK or an ACK was not received // is NAK or an ACK was not received
dlsch0->harq_ack[subframe].ack = 1; dlsch0->harq_ack[subframe].ack = 1;