Commit 9efd5d6f authored by Niccolò Iardella's avatar Niccolò Iardella Committed by Robert Schmidt
Browse files

Inter/intra-slice sharing are now optional

parent 8d9a8ab5
......@@ -114,6 +114,11 @@ typedef enum {
CR_NUM = 6
} sorting_criterion_t;
typedef enum {
POL_FAIR = 0,
POL_GREEDY = 1,
POL_NUM = 2
} accounting_policy_t;
//-----------------------------------------------------------------------------
// PHY TYPES
//-----------------------------------------------------------------------------
......
......@@ -435,6 +435,34 @@ schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, in
slice_percentage_total += slice_percentage[i];
}
// Check for *intra*slice share activation
if (intraslice_share_active_current != intraslice_share_active) {
if (intraslice_share_active != 1 && intraslice_share_active != 0) {
LOG_W(MAC,
"[eNB %d][DL] frame %d subframe %d: invalid intraslice sharing status (%d), revert to its previous value (%d)\n",
module_idP, i, frameP, subframeP, intraslice_share_active, intraslice_share_active_current);
intraslice_share_active = intraslice_share_active_current;
} else {
LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: intraslice sharing status has changed (%x-->%x)\n",
module_idP, i, frameP, subframeP, intraslice_share_active_current, intraslice_share_active);
intraslice_share_active_current = intraslice_share_active;
}
}
// Check for *inter*slice share activation
if (interslice_share_active_current != interslice_share_active) {
if (interslice_share_active != 1 && interslice_share_active != 0) {
LOG_W(MAC,
"[eNB %d][DL] frame %d subframe %d: invalid interslice sharing status (%d), revert to its previous value (%d)\n",
module_idP, i, frameP, subframeP, interslice_share_active, interslice_share_active_current);
interslice_share_active = interslice_share_active_current;
} else {
LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: interslice sharing status has changed (%x-->%x)\n",
module_idP, i, frameP, subframeP, interslice_share_active_current, interslice_share_active);
interslice_share_active_current = interslice_share_active;
}
}
for (i = 0; i < n_active_slices; i++) {
// Load any updated functions
......@@ -712,7 +740,9 @@ schedule_ue_spec(module_id_t module_idP, slice_id_t slice_idP,
return;
}
dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP);
if (interslice_share_active) {
dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP);
}
for (CC_id = 0; CC_id < NFAPI_CC_MAX; CC_id++) {
LOG_D(MAC, "doing schedule_ue_spec for CC_id %d\n", CC_id);
......@@ -1732,7 +1762,7 @@ void dlsch_scheduler_qos_multiplexing(module_id_t Mod_id, int frameP, sub_frame_
UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
UE_sched_ctrl *ue_sched_ctl;
for (CC_id = 0; CC_id < MAX_NUM_CCs; ++CC_id) {
for (CC_id = 0; CC_id < NFAPI_CC_MAX; ++CC_id) {
for (i = 0; i < n_active_slices; ++i) {
// Sort UE again
......
......@@ -42,6 +42,11 @@ int n_active_slices = 1;
int n_active_slices_current = 1;
int slice_counter = 0;
int intraslice_share_active = 1;
int intraslice_share_active_current = 1;
int interslice_share_active = 1;
int interslice_share_active_current = 1;
// RB share for each slice for past and current time
float slice_percentage[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0};
float slice_percentage_current[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0};
......
......@@ -1582,6 +1582,10 @@ typedef struct {
uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX];
uint8_t slice_allocated_rbgs[NFAPI_CC_MAX][N_RBG_MAX];
uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX];
uint32_t bytes_lcid[MAX_MOBILES_PER_ENB][MAX_NUM_LCID];
uint32_t wb_pmi[MAX_NUM_CCs][MAX_MOBILES_PER_ENB];
uint8_t mcs[MAX_NUM_CCs][MAX_MOBILES_PER_ENB];
} pre_processor_results_t;
#include "mac_proto.h"
......
......@@ -63,6 +63,8 @@ extern int slice_maxmcs[MAX_NUM_SLICES];
extern int slice_maxmcs_uplink[MAX_NUM_SLICES];
extern pre_processor_results_t pre_processor_results[MAX_NUM_SLICES];
extern int intraslice_share_active;
//#define ICIC 0
/* this function checks that get_eNB_UE_stats returns
......@@ -164,6 +166,7 @@ store_dlsch_buffer(module_id_t Mod_id,
#endif
}
if (UE_template->dl_buffer_total > 0)
......@@ -204,7 +207,8 @@ assign_rbs_required(module_id_t Mod_id,
CC_id = UE_list->ordered_CCids[n][UE_id];
eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];
eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]);
// eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]);
eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]), slice_maxmcs[slice_id]);
}
......@@ -266,6 +270,8 @@ assign_rbs_required(module_id_t Mod_id,
Mod_id, frameP, UE_id, CC_id, min_rb_unit[CC_id],
nb_rbs_required[CC_id][UE_id], TBS,
eNB_UE_stats->dlsch_mcs1);
pre_processor_results[slice_id].mcs[CC_id][UE_id] = eNB_UE_stats->dlsch_mcs1;
}
}
}
......@@ -646,7 +652,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
CC_id = UE_list->ordered_CCids[i][UE_id];
ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
cc = &RC.mac[Mod_id]->common_channels[CC_id];
// TODO Can we use subframe2harqpid() here?
// FIXME: Can we use subframe2harqpid() here?
if (cc->tdd_Config)
harq_pid = ((frameP * 10) + subframeP) % 10;
else
......@@ -675,7 +681,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
switch (slice_accounting[slice_id]) {
// If greedy scheduling, try to account all the required RBs
case 1:
case POL_GREEDY:
for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
rnti = UE_RNTI(Mod_id, UE_id);
if (rnti == NOT_A_RNTI) continue;
......@@ -691,6 +697,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
// Use the old, fair algorithm
// Loop over all active UEs and account the avg number of RBs to each UE, based on all non-retx UEs.
// case POL_FAIR:
default:
// FIXME: This is not ideal, why loop on UEs to find average_rbs_per_user[], that is per-CC?
// TODO: Look how to loop on active CCs only without using the UE_num_active_CC() function.
......@@ -1252,12 +1259,14 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
#endif
// Initialize scheduling information for all active UEs
memset(&pre_processor_results[slice_id], 0, sizeof(pre_processor_results));
// FIXME: After the memset above, some of the resets in reset() are redundant
dlsch_scheduler_pre_processor_reset(Mod_id, slice_id, frameP, subframeP,
min_rb_unit,
nb_rbs_required,
rballoc_sub,
MIMO_mode_indicator,
mbsfn_flag); // TODO Not sure if useful
mbsfn_flag); // FIXME: Not sure if useful
// STATUS
// Store the DLSCH buffer for each logical channel
......@@ -1289,13 +1298,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
// SHARING
// If there are available RBs left in the slice, allocate them to the highest priority UEs
dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id,
min_rb_unit,
nb_rbs_required,
nb_rbs_accounted,
nb_rbs_remaining,
rballoc_sub,
MIMO_mode_indicator);
if (intraslice_share_active) {
dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id,
min_rb_unit,
nb_rbs_required,
nb_rbs_accounted,
nb_rbs_remaining,
rballoc_sub,
MIMO_mode_indicator);
}
#ifdef TM5
// This has to be revisited!!!!
......@@ -2075,3 +2086,7 @@ void sort_ue_ul(module_id_t module_idP, int frameP, sub_frame_t subframeP)
UE_list->head_ul = -1;
}
}
int cqi2mcs(int cqi) {
return cqi_to_mcs[cqi];
}
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