Commit bb398adb authored by Guy De Souza's avatar Guy De Souza

DCI payload fixes

parent 4c5d5ea4
...@@ -33,8 +33,8 @@ ...@@ -33,8 +33,8 @@
#include "nr_dci.h" #include "nr_dci.h"
//#define DEBUG_PDCCH_DMRS //#define DEBUG_PDCCH_DMRS
#define DEBUG_DCI //#define DEBUG_DCI
#define DEBUG_CHANNEL_CODING //#define DEBUG_CHANNEL_CODING
extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT]; extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
......
...@@ -36,7 +36,6 @@ ...@@ -36,7 +36,6 @@
#include "nr_dlsch.h" #include "nr_dlsch.h"
void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) { void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) {
nr_cce_t* cce; nr_cce_t* cce;
...@@ -48,6 +47,8 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -48,6 +47,8 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
uint8_t R = pdcch_params->interleaver_size; uint8_t R = pdcch_params->interleaver_size;
uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb; uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb;
uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C; uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C;
uint16_t n_RNTI = (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params->rnti:0;
uint32_t A[3]={39827,39829,39839};
if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1) if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
...@@ -59,6 +60,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -59,6 +60,7 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON) if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON)
Y = 0; Y = 0;
else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
Y = (A[0]*n_RNTI)%65537; // Candidate 0, antenna port 0
} }
if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
...@@ -111,6 +113,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m ...@@ -111,6 +113,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
} }
} }
/*static inline uint64_t dci_field(uint64_t field, uint8_t size) {
uint64_t ret = 0;
for (int i=0; i<size; i++)
ret |= ((field>>i)&1)<<(size-i-1);
return ret;
}*/
void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
int frame, int frame,
int subframe, int subframe,
...@@ -156,38 +165,38 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -156,38 +165,38 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
case NFAPI_NR_DL_DCI_FORMAT_1_0: case NFAPI_NR_DL_DCI_FORMAT_1_0:
switch(params_rel15->rnti_type) { switch(params_rel15->rnti_type) {
case NFAPI_NR_RNTI_RA: case NFAPI_NR_RNTI_RA:
// printf("dci_pdu %llx\n",(unsigned long long int)*dci_pdu);
// Freq domain assignment // Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize; pos=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("frequency-domain assignment %d (%d bits)=> %d (%llx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("frequency-domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// Time domain assignment // Time domain assignment
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("time-domain assignment %d (3 bits)=> %d (%llx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("time-domain assignment %d (3 bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// VRB to PRB mapping // VRB to PRB mapping
pos++; pos++;
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("vrb to prb mapping %d (1 bits)=> %d (%llx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// MCS // MCS
pos+=5; pos+=5;
*dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("mcs %d (5 bits)=> %d (%llx)\n",pdu_rel15->mcs,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("mcs %d (5 bits)=> %d (0x%lx)\n",pdu_rel15->mcs,dci_alloc->size-pos,*dci_pdu);
#endif #endif
// TB scaling // TB scaling
pos+=2; pos+=2;
*dci_pdu |= (pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->tb_scaling&0x3)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI #ifdef DEBUG_FILL_DCI
printf("tb_scaling %d (2 bits)=> %d (%llx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,(unsigned long long int)*dci_pdu); printf("tb_scaling %d (2 bits)=> %d (0x%lx)\n",pdu_rel15->tb_scaling,dci_alloc->size-pos,*dci_pdu);
#endif #endif
break; break;
...@@ -195,14 +204,27 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -195,14 +204,27 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("Format indicator %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->format_indicator,1,dci_alloc->size-pos,*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16) // Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize; pos+=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos)); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->frequency_domain_assignment,fsize,dci_alloc->size-pos,*dci_pdu);
#endif
if (((pdu_rel15->frequency_domain_assignment+1)&1) ==0) //fsize are all 1 38.212 p86 uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
if (!((pdu_rel15->frequency_domain_assignment>>i)&1)) {
is_ra = 0;
break;
}
if (is_ra) //fsize are all 1 38.212 p86
{ {
// ra_preamble_index 6 bits // ra_preamble_index 6 bits
pos+=6; pos+=6;
...@@ -228,42 +250,72 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -228,42 +250,72 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("Time domain assignment %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->time_domain_assignment,4,dci_alloc->size-pos,*dci_pdu);
#endif
// VRB to PRB mapping 1bit // VRB to PRB mapping 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("VRB to PRB %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->vrb_to_prb_mapping,1,dci_alloc->size-pos,*dci_pdu);
#endif
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
pos+=5; pos+=5;
*dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->mcs&0x1f)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("MCS %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->mcs,5,dci_alloc->size-pos,*dci_pdu);
#endif
// New data indicator 1bit // New data indicator 1bit
pos++; pos++;
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("NDI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->ndi,1,dci_alloc->size-pos,*dci_pdu);
#endif
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; pos+=2;
*dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos); *dci_pdu |= (pdu_rel15->rv&0x3)<<(dci_alloc->size-pos);
#ifdef DEBUG_FILL_DCI
printf("RV %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->rv,2,dci_alloc->size-pos,*dci_pdu);
#endif
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; pos+=4;
*dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("HARQ_PID %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->harq_pid,4,dci_alloc->size-pos,*dci_pdu);
#endif
// Downlink assignment index 2bit // Downlink assignment index 2bit
pos+=2; pos+=2;
*dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->dai&3)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("DAI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->dai,2,dci_alloc->size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; pos+=2;
*dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("TPC %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->tpc,2,dci_alloc->size-pos,*dci_pdu);
#endif
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("PUCCH RI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pucch_resource_indicator,3,dci_alloc->size-pos,*dci_pdu);
#endif
// PDSCH-to-HARQ_feedback timing indicator 3bit // PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos)); *dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos));
#ifdef DEBUG_FILL_DCI
printf("PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_alloc->size-pos,*dci_pdu);
#endif
} //end else } //end else
break; break;
...@@ -272,26 +324,26 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -272,26 +324,26 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// Short Messages Indicator – 2 bits // Short Messages Indicator – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_alloc->size-pos++);
// Short Messages – 8 bits // Short Messages – 8 bits
for (int i=0; i<8; i++) for (int i=0; i<8; i++)
*dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->short_messages>>(7-i))&1)<<(dci_alloc->size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// TB scaling 2 bit // TB scaling 2 bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_alloc->size-pos++);
break; break;
...@@ -303,49 +355,49 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -303,49 +355,49 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
break; break;
case NFAPI_NR_RNTI_TC: case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->vrb_to_prb_mapping&1)<<(dci_alloc->size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// Downlink assignment index – 2 bits // Downlink assignment index – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->dai>>(1-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUCCH – 2 bits // TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// LOG_I(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", // LOG_I(PHY, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n",
...@@ -354,49 +406,50 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -354,49 +406,50 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// PDSCH-to-HARQ_feedback timing indicator – 3 bits // PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++) for (int i=0; i<3; i++)
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_alloc->size-pos++);
break; break;
} }
break;
case NFAPI_NR_UL_DCI_FORMAT_0_0: case NFAPI_NR_UL_DCI_FORMAT_0_0:
switch(params_rel15->rnti_type) switch(params_rel15->rnti_type)
{ {
case NFAPI_NR_RNTI_C: case NFAPI_NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ul_sul_indicator&1)<<(dci_alloc->size-pos++);
break; break;
...@@ -410,39 +463,39 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB, ...@@ -410,39 +463,39 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_alloc->size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_alloc->size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->frequency_hopping_flag&1)<<(dci_alloc->size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->mcs>>(4-i))&1)<<(dci_alloc->size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->ndi&1)<<(dci_alloc->size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->rv>>(1-i))&1)<<(dci_alloc->size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->harq_pid>>(3-i))&1)<<(dci_alloc->size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++); *dci_pdu |= (((uint64_t)pdu_rel15->tpc>>(1-i))&1)<<(dci_alloc->size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<(dci_alloc->size-pos++); *dci_pdu |= ((uint64_t)pdu_rel15->padding&1)<<(dci_alloc->size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)