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oai
openairinterface5G
Commits
bfa8a28c
Commit
bfa8a28c
authored
Feb 14, 2017
by
Bilel
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[OAI-UE] fix pucch format2 regression
parent
4ecdfa05
Changes
1
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1 changed file
with
44 additions
and
45 deletions
+44
-45
openair1/PHY/LTE_TRANSPORT/pucch.c
openair1/PHY/LTE_TRANSPORT/pucch.c
+44
-45
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openair1/PHY/LTE_TRANSPORT/pucch.c
View file @
bfa8a28c
...
...
@@ -523,8 +523,29 @@ void generate_pucch2x(int32_t **txdataF,
pucch2x_modulation
(
btilde
,
d
,
amp
);
// add extra symbol for 2a/2b
d
[
20
]
=
0
;
d
[
21
]
=
0
;
if
(
fmt
==
pucch_format2a
)
d
[
20
]
=
(
B2
==
0
)
?
amp
:
-
amp
;
else
if
(
fmt
==
pucch_format2b
)
{
switch
(
B2
)
{
case
0
:
d
[
20
]
=
amp
;
break
;
case
1
:
d
[
21
]
=
-
amp
;
break
;
case
2
:
d
[
21
]
=
amp
;
break
;
case
3
:
d
[
20
]
=
-
amp
;
break
;
default:
AssertFatal
(
1
==
0
,
"Illegal modulation symbol %d for PUCCH %s
\n
"
,
B2
,
pucch_format_string
[
fmt
]);
break
;
}
}
#ifdef DEBUG_PUCCH_TX
...
...
@@ -552,7 +573,8 @@ void generate_pucch2x(int32_t **txdataF,
n_cs
=
(
ncs_cell
[
ns
][
l
]
+
nprime
)
%
12
;
alpha_ind
=
0
;
for
(
n
=
0
;
n
<
12
;
n
++
)
{
for
(
n
=
0
;
n
<
12
;
n
++
)
{
// this is r_uv^alpha(n)
ref_re
=
(
int16_t
)(((
int32_t
)
alpha_re
[
alpha_ind
]
*
ul_ref_sigs
[
u
][
v
][
0
][
n
<<
1
]
-
(
int32_t
)
alpha_im
[
alpha_ind
]
*
ul_ref_sigs
[
u
][
v
][
0
][
1
+
(
n
<<
1
)])
>>
15
);
ref_im
=
(
int16_t
)(((
int32_t
)
alpha_re
[
alpha_ind
]
*
ul_ref_sigs
[
u
][
v
][
0
][
1
+
(
n
<<
1
)]
+
(
int32_t
)
alpha_im
[
alpha_ind
]
*
ul_ref_sigs
[
u
][
v
][
0
][
n
<<
1
])
>>
15
);
...
...
@@ -563,48 +585,25 @@ void generate_pucch2x(int32_t **txdataF,
//LOG_I(PHY,"slot %d ofdm# %d ==> d[%d,%d] \n",ns,l,data_ind,n);
}
else
{
if
(
l
==
1
){
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
amp
*
ref_im
>>
15
);
}
else
if
(
fmt
==
pucch_format2a
)
{
d
[
20
]
=
amp
;
d
[
21
]
=
amp
;
if
(
B2
==
0
)
{
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
amp
*
ref_im
>>
15
);
}
else
{
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
-
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
-
((
int32_t
)
amp
*
ref_im
>>
15
);
}
//LOG_I(PHY,"slot %d ofdm# %d ==> dmrs[%d] \n",ns,l,n);
}
else
if
(
fmt
==
pucch_format2b
)
{
switch
(
B2
)
{
case
0
:
// 1
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
amp
*
ref_im
>>
15
);
break
;
case
1
:
// -j
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
-
((
int32_t
)
amp
*
ref_im
>>
15
);
break
;
case
2
:
// -1
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
-
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
-
((
int32_t
)
amp
*
ref_im
>>
15
);
break
;
case
3
:
// j
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
-
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
amp
*
ref_im
>>
15
);
break
;
default:
AssertFatal
(
1
==
0
,
"Illegal modulation symbol %d for PUCCH %s
\n
"
,
B2
,
pucch_format_string
[
fmt
]);
break
;
}
}
// fmt==pucch_format2b
}
// l==1 || l==5
alpha_ind
=
(
alpha_ind
+
n_cs
)
%
12
;
if
((
l
==
1
)
||
(
(
l
==
5
)
&&
(
fmt
==
pucch_format2
)
))
{
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
amp
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
amp
*
ref_im
>>
15
);
}
// l == 5 && pucch format 2a
else
if
(
fmt
==
pucch_format2a
)
{
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
d
[
20
]
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
d
[
21
]
*
ref_im
>>
15
);
}
// l == 5 && pucch format 2b
else
if
(
fmt
==
pucch_format2b
)
{
((
int16_t
*
)
&
zptr
[
n
])[
0
]
=
((
int32_t
)
d
[
20
]
*
ref_re
>>
15
);
((
int16_t
*
)
&
zptr
[
n
])[
1
]
=
((
int32_t
)
d
[
21
]
*
ref_im
>>
15
);
}
}
// l==1 || l==5
alpha_ind
=
(
alpha_ind
+
n_cs
)
%
12
;
}
// n
zptr
+=
12
;
...
...
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