Commit c4b7d4c1 authored by knopp's avatar knopp
Browse files

updates to UL (DFTs for 10/20 MHz), Ndi toggling, DCI structures

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4600 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 21635af2
...@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) { ...@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) {
k++;k2++;k2++; k++;k2++;k2++;
} }
} }
if (ND>0)
d[2] = LTE_NULL;//d[(3*D)+2]; // if (ND>0)
// d[2] = LTE_NULL;//d[(3*D)+2];
} }
...@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC, ...@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC,
k=0; k=0;
for (;(ind<Ncb)&&(k<E);ind++) { for (;(ind<Ncb)&&(k<E);ind++) {
e2[k]=w[ind]; // e2[k]=w[ind];
#ifdef RM_DEBUG_TX #ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]); printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif #endif
if (w[ind] != LTE_NULL) k++; if (w[ind] != LTE_NULL) e2[k++]=w[ind];
} }
while(k<E) { while(k<E) {
for (ind=0;(ind<Ncb)&&(k<E);ind++) { for (ind=0;(ind<Ncb)&&(k<E);ind++) {
e2[k] = w[ind]; // e2[k] = w[ind];
#ifdef RM_DEBUG_TX #ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]); printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif #endif
if (w[ind] != LTE_NULL) k++; if (w[ind] != LTE_NULL) e2[k++]=w[ind];
} }
} }
/* /*
......
...@@ -1963,7 +1963,7 @@ u8 get_num_pdcch_symbols(u8 num_dci, ...@@ -1963,7 +1963,7 @@ u8 get_num_pdcch_symbols(u8 num_dci,
// compute numCCE // compute numCCE
for (i=0;i<num_dci;i++) { for (i=0;i<num_dci;i++) {
// printf("dci %d => %d\n",i,dci_alloc[i].L); // printf("dci %d => %d\n",i,dci_alloc[i].L);
numCCE += (1<<(dci_alloc[i].L)); numCCE += (1<<(dci_alloc[i].L));
} }
...@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mod_sym_t *y[2]; mod_sym_t *y[2];
mod_sym_t *wbar[2]; mod_sym_t *wbar[2];
#ifdef IFFT_FPGA
u8 qpsk_table_offset = 0;
u8 qpsk_table_offset2 = 0;
#endif
int nushiftmod3 = frame_parms->nushift%3; int nushiftmod3 = frame_parms->nushift%3;
int Msymb2; int Msymb2;
...@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr = e; e_ptr = e;
if (frame_parms->mode1_flag) { //SISO if (frame_parms->mode1_flag) { //SISO
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i++) { for (i=0;i<Msymb2;i++) {
//((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; //((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
//((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; //((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
...@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr++; e_ptr++;
} }
#else
for (i=0;i<Msymb2;i++) {
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET;
if (*e_ptr == 1)
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1)
qpsk_table_offset+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset;
y[1][i] = (mod_sym_t) qpsk_table_offset;
}
#endif
} }
else { //ALAMOUTI else { //ALAMOUTI
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i+=2) { for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING #ifdef DEBUG_DCI_ENCODING
...@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1]; ((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1];
} }
#else
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
LOG_I(PHY," PDCCH Modulation: Symbol %d : REG %d/%d\n",i,i>>2,Msymb2>>2);
#endif
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //x0
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x0*
if (*e_ptr == 1) { //real
qpsk_table_offset+=2;
qpsk_table_offset2+=2;
}
e_ptr++;
if (*e_ptr == 1) //imag
qpsk_table_offset+=1;
else
qpsk_table_offset2+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset; // x0
y[1][i+1] = (mod_sym_t) qpsk_table_offset2; // x0*
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //-x1*
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x1
if (*e_ptr == 1) // flipping bit for real part of symbol means taking -x1*
qpsk_table_offset2+=2;
else
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1) {
qpsk_table_offset+=1;
qpsk_table_offset2+=1;
}
e_ptr++;
y[1][i] = (mod_sym_t) qpsk_table_offset; // -x1*
y[0][i+1] = (mod_sym_t) qpsk_table_offset2; // x1
}
#endif
} }
...@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mprime=0; mprime=0;
nsymb = (frame_parms->Ncp==0) ? 14:12; nsymb = (frame_parms->Ncp==0) ? 14:12;
#ifdef IFFT_FPGA
re_offset = frame_parms->N_RB_DL*12/2;
#else
re_offset = frame_parms->first_carrier_offset; re_offset = frame_parms->first_carrier_offset;
#endif
// This is the REG allocation algorithm from 36-211, second part of Section 6.8.5 // This is the REG allocation algorithm from 36-211, second part of Section 6.8.5
// printf("DCI : txdataF %p (0 %p)\n",&txdataF[0][512*14*subframe],&txdataF[0][0]); // printf("DCI (SF %d) : txdataF %p (0 %p)\n",subframe,&txdataF[0][512*14*subframe],&txdataF[0][0]);
for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) { for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) {
for (lprime=0;lprime<num_pdcch_symbols;lprime++) { for (lprime=0;lprime<num_pdcch_symbols;lprime++) {
#ifdef IFFT_FPGA
symbol_offset = (u32)frame_parms->N_RB_DL*12*(lprime+(subframe*nsymb));
#else
symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb)); symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb));
#endif
...@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
} //lprime loop } //lprime loop
re_offset++; re_offset++;
#ifdef IFFT_FPGA
if (re_offset == (frame_parms->N_RB_DL*12))
re_offset = 0;
#else
if (re_offset == (frame_parms->ofdm_symbol_size)) if (re_offset == (frame_parms->ofdm_symbol_size))
re_offset = 1; re_offset = 1;
#endif
} // kprime loop } // kprime loop
return(num_pdcch_symbols); return(num_pdcch_symbols);
} }
......
...@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t; ...@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t;
/// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits) /// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits)
struct DCI1A_1_5MHz_TDD_1_6 { struct DCI1A_1_5MHz_TDD_1_6 {
/// padding /// padding
uint32_t padding:8; uint32_t padding:9;
/// SRS request bit
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t; ...@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t;
/// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits) /// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits)
struct DCI1A_10MHz_TDD_1_6 { struct DCI1A_10MHz_TDD_1_6 {
/// padding /// padding
uint32_t padding:2; uint32_t padding:3;
/// SRS request bit
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t; ...@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t;
struct DCI0_20MHz_TDD_1_6 { struct DCI0_20MHz_TDD_1_6 {
/// Padding /// Padding
uint32_t padding:2; uint32_t padding:2;
/// CQI Request /// CQI request
uint32_t cqi_req:1; uint32_t cqi_req:1;
/// DAI /// DAI
uint32_t dai:2; uint32_t dai:2;
...@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t; ...@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t;
/// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits) /// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits)
struct DCI1A_20MHz_TDD_1_6 { struct DCI1A_20MHz_TDD_1_6 {
/// SRS request bit uint32_t padding:1;
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t; ...@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t;
struct DCI1A_1_5MHz_FDD { struct DCI1A_1_5MHz_FDD {
/// padding /// padding
uint32_t padding:11; uint32_t padding:12;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t; ...@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t;
struct DCI1A_5MHz_FDD { struct DCI1A_5MHz_FDD {
/// padding /// padding
uint32_t padding:7; uint32_t padding:8;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t; ...@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t;
struct DCI1A_10MHz_FDD { struct DCI1A_10MHz_FDD {
/// padding /// padding
uint32_t padding:5; uint32_t padding:6;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t; ...@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t;
struct DCI1A_20MHz_FDD { struct DCI1A_20MHz_FDD {
/// padding /// padding
uint32_t padding:3; uint32_t padding:4;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
......
...@@ -161,12 +161,12 @@ void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t ...@@ -161,12 +161,12 @@ void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t
if (ra_header == 0) {// Type 0 Allocation if (ra_header == 0) {// Type 0 Allocation
for (i=12;i>0;i--) { for (i=12;i>0;i--) {
if ((rb_alloc&(1<<i)) != 0) if ((rb_alloc&(1<<i)) != 0)
rb_alloc2[0] |= (3<<((2*(12-i)))); rb_alloc2[0] |= (3<<((2*(12-i))));
// printf("rb_alloc2 (type 0) %x\n",rb_alloc2); // printf("rb_alloc2 (type 0) %x\n",rb_alloc2);
} }
if ((rb_alloc&1) != 0) if ((rb_alloc&1) != 0)
rb_alloc2[0] |= (1<<24); rb_alloc2[0] |= (1<<24);
} }
else { else {
subset = rb_alloc&1; subset = rb_alloc&1;
...@@ -192,30 +192,30 @@ void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t ...@@ -192,30 +192,30 @@ void conv_rballoc(uint8_t ra_header,uint32_t rb_alloc,uint32_t N_RB_DL,uint32_t
rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32)); rb_alloc2[(3*(16-i))>>5] |= (7<<((3*(16-i))%32));
} }
/* /*
for (i=1;i<=16;i++) { for (i=1;i<=16;i++) {
if ((rb_alloc&(1<<(16-i))) != 0) if ((rb_alloc&(1<<(16-i))) != 0)
rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32)); rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
} }
*/ */
// bit mask across // bit mask across
if ((rb_alloc2[0]>>31)==1) if ((rb_alloc2[0]>>31)==1)
rb_alloc2[1] |= 1; rb_alloc2[1] |= 1;
if ((rb_alloc&1) != 0) if ((rb_alloc&1) != 0)
rb_alloc2[1] |= (3<<16); rb_alloc2[1] |= (3<<16);
/* /*
for (i=0;i<16;i++) { for (i=0;i<16;i++) {
if (((rb_alloc>>(16-i))&1) != 0) if (((rb_alloc>>(16-i))&1) != 0)
rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32)); rb_alloc2[(3*i)>>5] |= (7<<((3*i)%32));
if ((i==10)&&((rb_alloc&(1<<6))!=0)) if ((i==10)&&((rb_alloc&(1<<6))!=0))
rb_alloc2[1] = 1; rb_alloc2[1] = 1;
// printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1); // printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);
} }
// fill in 2 from last bit instead of 3 // fill in 2 from last bit instead of 3
if ((rb_alloc&1) != 0) if ((rb_alloc&1) != 0)
rb_alloc2[1] |= (3<<i); rb_alloc2[1] |= (3<<i);
// printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1); // printf("rb_alloc2[%d] (type 0) %x ((%x>>%d)&1=%d)\n",(3*i)>>5,rb_alloc2[(3*i)>>5],rb_alloc,i,(rb_alloc>>i)&1);
*/ */
// printf("rb_alloc[1]=%x,rb_alloc[0]=%x\n",rb_alloc2[1],rb_alloc2[0]); // printf("rb_alloc[1]=%x,rb_alloc[0]=%x\n",rb_alloc2[1],rb_alloc2[0]);
} }
else { else {
...@@ -292,12 +292,12 @@ uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) { ...@@ -292,12 +292,12 @@ uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) {
case 25: case 25:
if (ra_header == 0) {// Type 0 Allocation if (ra_header == 0) {// Type 0 Allocation
for (i=12;i>0;i--) { for (i=12;i>0;i--) {
if ((rb_alloc&(1<<i)) != 0) if ((rb_alloc&(1<<i)) != 0)
nprb += 2; nprb += 2;
} }
if ((rb_alloc&1) != 0) if ((rb_alloc&1) != 0)
nprb += 1; nprb += 1;
} }
else { else {
for (i=0;i<11;i++) { for (i=0;i<11;i++) {
...@@ -351,14 +351,14 @@ uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) { ...@@ -351,14 +351,14 @@ uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL) {
uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs) { uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs) {
uint16_t RIV; uint16_t RIV;
if (Lcrbs<=(1+(N_RB_DL>>1))) if (Lcrbs<=(1+(N_RB_DL>>1)))
RIV = (N_RB_DL*(Lcrbs-1)) + RBstart; RIV = (N_RB_DL*(Lcrbs-1)) + RBstart;
else else
RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart); RIV = (N_RB_DL*(N_RB_DL+1-Lcrbs)) + (N_RB_DL-1-RBstart);
return(RIV); return(RIV);
} }
int dist6[6]={0,2,3,5,1,4}; int dist6[6]={0,2,3,5,1,4};
...@@ -399,27 +399,27 @@ void generate_RIV_tables() { ...@@ -399,27 +399,27 @@ void generate_RIV_tables() {
for (RBstart=0;RBstart<25;RBstart++) { for (RBstart=0;RBstart<25;RBstart++) {
alloc0 = 0; alloc0 = 0;
alloc_dist0 = 0; alloc_dist0 = 0;
for (Lcrbs=1;Lcrbs<=(25-RBstart);Lcrbs++) { for (Lcrbs=1;Lcrbs<=(25-RBstart);Lcrbs++) {
// printf("RBstart %d, len %d --> ",RBstart,Lcrbs); // printf("RBstart %d, len %d --> ",RBstart,Lcrbs);
alloc0 |= (1<<(RBstart+Lcrbs-1)); alloc0 |= (1<<(RBstart+Lcrbs-1));
// This is the RB<->VRB relationship for N_RB_DL=25 // This is the RB<->VRB relationship for N_RB_DL=25
distpos = ((RBstart+Lcrbs-1)*6)%23; distpos = ((RBstart+Lcrbs-1)*6)%23;
if (distpos == 0) if (distpos == 0)
distpos = 23; distpos = 23;
alloc_dist0 |= (1<<distpos); alloc_dist0 |= (1<<distpos);
RIV=computeRIV(25,RBstart,Lcrbs); RIV=computeRIV(25,RBstart,Lcrbs);
if (RIV>RIV_max25) if (RIV>RIV_max25)
RIV_max25 = RIV; RIV_max25 = RIV;
// printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs); // printf("RIV %d (%d) : first_rb %d NBRB %d\n",RIV,localRIV2alloc_LUT25[RIV],RBstart,Lcrbs);
localRIV2alloc_LUT25[RIV] = alloc0; localRIV2alloc_LUT25[RIV] = alloc0;
distRIV2alloc_LUT25[RIV] = alloc_dist0; distRIV2alloc_LUT25[RIV] = alloc_dist0;
RIV2nb_rb_LUT25[RIV] = Lcrbs; RIV2nb_rb_LUT25[RIV] = Lcrbs;
RIV2first_rb_LUT25[RIV] = RBstart; RIV2first_rb_LUT25[RIV] = RBstart;
} }
} }
...@@ -556,7 +556,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -556,7 +556,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
uint8_t mcs=0; uint8_t mcs=0;
uint8_t I_mcs = 0; uint8_t I_mcs = 0;
uint8_t rv=0; uint8_t rv=0;
uint8_t ndi=0;
uint8_t rah=0; uint8_t rah=0;
uint8_t TPC=0; uint8_t TPC=0;
// printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu); // printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);
...@@ -579,7 +578,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -579,7 +578,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs; mcs = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc; rballoc = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv; rv = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC; TPC = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid; harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
...@@ -590,7 +588,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -590,7 +588,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs; mcs = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc; rballoc = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv; rv = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC; TPC = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid; harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
...@@ -613,7 +610,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -613,7 +610,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs; mcs = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc; rballoc = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv; rv = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC; TPC = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid; harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
...@@ -624,7 +620,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -624,7 +620,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs; mcs = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc; rballoc = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv; rv = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC; TPC = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid; harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
...@@ -645,7 +640,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe, ...@@ -645,7 +640,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs; mcs = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc; rballoc = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv; rv = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC; TPC = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid; harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;