Commit c4b7d4c1 authored by knopp's avatar knopp
Browse files

updates to UL (DFTs for 10/20 MHz), Ndi toggling, DCI structures

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4600 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 21635af2
......@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) {
k++;k2++;k2++;
}
}
if (ND>0)
d[2] = LTE_NULL;//d[(3*D)+2];
// if (ND>0)
// d[2] = LTE_NULL;//d[(3*D)+2];
}
......@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC,
k=0;
for (;(ind<Ncb)&&(k<E);ind++) {
e2[k]=w[ind];
// e2[k]=w[ind];
#ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif
if (w[ind] != LTE_NULL) k++;
if (w[ind] != LTE_NULL) e2[k++]=w[ind];
}
while(k<E) {
for (ind=0;(ind<Ncb)&&(k<E);ind++) {
e2[k] = w[ind];
// e2[k] = w[ind];
#ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif
if (w[ind] != LTE_NULL) k++;
if (w[ind] != LTE_NULL) e2[k++]=w[ind];
}
}
/*
......
......@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mod_sym_t *y[2];
mod_sym_t *wbar[2];
#ifdef IFFT_FPGA
u8 qpsk_table_offset = 0;
u8 qpsk_table_offset2 = 0;
#endif
int nushiftmod3 = frame_parms->nushift%3;
int Msymb2;
......@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr = e;
if (frame_parms->mode1_flag) { //SISO
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i++) {
//((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
//((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
......@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr++;
}
#else
for (i=0;i<Msymb2;i++) {
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET;
if (*e_ptr == 1)
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1)
qpsk_table_offset+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset;
y[1][i] = (mod_sym_t) qpsk_table_offset;
}
#endif
}
else { //ALAMOUTI
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
......@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1];
}
#else
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
LOG_I(PHY," PDCCH Modulation: Symbol %d : REG %d/%d\n",i,i>>2,Msymb2>>2);
#endif
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //x0
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x0*
if (*e_ptr == 1) { //real
qpsk_table_offset+=2;
qpsk_table_offset2+=2;
}
e_ptr++;
if (*e_ptr == 1) //imag
qpsk_table_offset+=1;
else
qpsk_table_offset2+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset; // x0
y[1][i+1] = (mod_sym_t) qpsk_table_offset2; // x0*
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //-x1*
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x1
if (*e_ptr == 1) // flipping bit for real part of symbol means taking -x1*
qpsk_table_offset2+=2;
else
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1) {
qpsk_table_offset+=1;
qpsk_table_offset2+=1;
}
e_ptr++;
y[1][i] = (mod_sym_t) qpsk_table_offset; // -x1*
y[0][i+1] = (mod_sym_t) qpsk_table_offset2; // x1
}
#endif
}
......@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mprime=0;
nsymb = (frame_parms->Ncp==0) ? 14:12;
#ifdef IFFT_FPGA
re_offset = frame_parms->N_RB_DL*12/2;
#else
re_offset = frame_parms->first_carrier_offset;
#endif
// This is the REG allocation algorithm from 36-211, second part of Section 6.8.5
// printf("DCI : txdataF %p (0 %p)\n",&txdataF[0][512*14*subframe],&txdataF[0][0]);
// printf("DCI (SF %d) : txdataF %p (0 %p)\n",subframe,&txdataF[0][512*14*subframe],&txdataF[0][0]);
for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) {
for (lprime=0;lprime<num_pdcch_symbols;lprime++) {
#ifdef IFFT_FPGA
symbol_offset = (u32)frame_parms->N_RB_DL*12*(lprime+(subframe*nsymb));
#else
symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb));
#endif
......@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
} //lprime loop
re_offset++;
#ifdef IFFT_FPGA
if (re_offset == (frame_parms->N_RB_DL*12))
re_offset = 0;
#else
if (re_offset == (frame_parms->ofdm_symbol_size))
re_offset = 1;
#endif
} // kprime loop
return(num_pdcch_symbols);
}
......
......@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t;
/// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits)
struct DCI1A_1_5MHz_TDD_1_6 {
/// padding
uint32_t padding:8;
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:9;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t;
/// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits)
struct DCI1A_10MHz_TDD_1_6 {
/// padding
uint32_t padding:2;
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:3;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t;
struct DCI0_20MHz_TDD_1_6 {
/// Padding
uint32_t padding:2;
/// CQI Request
/// CQI request
uint32_t cqi_req:1;
/// DAI
uint32_t dai:2;
......@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t;
/// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits)
struct DCI1A_20MHz_TDD_1_6 {
/// SRS request bit
uint32_t srs_req:1;
uint32_t padding:1;
/// Downlink Assignment Index
uint32_t dai:2;
/// Power Control
......@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t;
struct DCI1A_1_5MHz_FDD {
/// padding
uint32_t padding:11;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:12;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t;
struct DCI1A_5MHz_FDD {
/// padding
uint32_t padding:7;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:8;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t;
struct DCI1A_10MHz_FDD {
/// padding
uint32_t padding:5;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:6;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t;
struct DCI1A_20MHz_FDD {
/// padding
uint32_t padding:3;
/// Downlink Assignment Index
uint32_t srs_req:1;
uint32_t padding:4;
/// Power Control
uint32_t TPC:2;
/// Redundancy version
......
......@@ -556,7 +556,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
uint8_t mcs=0;
uint8_t I_mcs = 0;
uint8_t rv=0;
uint8_t ndi=0;
uint8_t rah=0;
uint8_t TPC=0;
// printf("Generate eNB DCI, format %d, rnti %x (pdu %p)\n",dci_format,rnti,dci_pdu);
......@@ -579,7 +578,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
......@@ -590,7 +588,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
......@@ -613,7 +610,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
......@@ -624,7 +620,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_5MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_5MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid;
......@@ -645,7 +640,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
......@@ -656,7 +650,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_10MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_10MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
......@@ -679,7 +672,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->rv;
ndi = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->ndi;
TPC = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
......@@ -689,7 +681,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
mcs = ((DCI1A_20MHz_FDD_t *)dci_pdu)->mcs;
rballoc = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1A_20MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1A_20MHz_FDD_t *)dci_pdu)->ndi;
TPC = ((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC;
harq_pid = ((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
......@@ -722,7 +713,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
harq_pid=0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1)+2;
ndi = 1;
// 36-213 sec.7.1.7.2 p.26
I_mcs = mcs;
}
......@@ -748,13 +738,28 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
dlsch[0]->harq_processes[harq_pid]->Nl = 1;
dlsch[0]->layer_index = 0;
dlsch[0]->harq_processes[harq_pid]->mimo_mode = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
dlsch[0]->harq_processes[harq_pid]->Ndi = ndi;
dlsch[0]->dl_power_off = 1;
if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
/*
if ((rnti!=si_rnti)&&(rnti!=ra_rnti)&&(rnti!=p_rnti)) { //handle toggling for C-RNTI
if (dlsch[0]->harq_processes[harq_pid]->first_tx == 1) {
LOG_D(PHY,"First TX for TC-RNTI %x, clearing first_tx flag\n",rnti);
dlsch[0]->harq_processes[harq_pid]->first_tx=0;
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
else {
if (ndi == dlsch[0]->harq_processes[harq_pid]->DCINdi)
dlsch[0]->harq_processes[harq_pid]->Ndi = 0;
else
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
dlsch[0]->harq_processes[harq_pid]->DCINdi=ndi;
}
else {
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
*/
dlsch[0]->dl_power_off = 1;
......@@ -770,7 +775,7 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
dlsch[0]->rnti = rnti;
dlsch[0]->harq_ids[subframe] = harq_pid;
if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1)
if (dlsch[0]->harq_processes[harq_pid]->round == 0)
dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
break;
......@@ -784,7 +789,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rballoc = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->rv;
ndi = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_1_5MHz_TDD_t *)dci_pdu)->harq_pid;
}
else {
......@@ -792,7 +796,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rah = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_1_5MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
......@@ -803,16 +806,17 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rballoc = ((DCI1_5MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_5MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_5MHz_TDD_t *)dci_pdu)->rv;
ndi = ((DCI1_5MHz_TDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_5MHz_TDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_TDD_t *)dci_pdu)->ndi,harq_pid);
}
else {
mcs = ((DCI1_5MHz_FDD_t *)dci_pdu)->mcs;
rah = ((DCI1_5MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_5MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_5MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1_5MHz_FDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_5MHz_FDD_t *)dci_pdu)->harq_pid;
LOG_D(PHY,"eNB: subframe %d UE %x, Format1 DCI: ndi %d, harq_pid %d\n",subframe,rnti,((DCI1_5MHz_FDD_t *)dci_pdu)->ndi,harq_pid);
}
break;
case 50:
......@@ -821,7 +825,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rballoc = ((DCI1_10MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_10MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_10MHz_TDD_t *)dci_pdu)->rv;
ndi = ((DCI1_10MHz_TDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_10MHz_TDD_t *)dci_pdu)->harq_pid;
}
else {
......@@ -829,7 +832,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rah = ((DCI1_10MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_10MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_10MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1_10MHz_FDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_10MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
......@@ -840,7 +842,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rballoc = ((DCI1_20MHz_TDD_t *)dci_pdu)->rballoc;
rah = ((DCI1_20MHz_TDD_t *)dci_pdu)->rah;
rv = ((DCI1_20MHz_TDD_t *)dci_pdu)->rv;
ndi = ((DCI1_20MHz_TDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_20MHz_TDD_t *)dci_pdu)->harq_pid;
}
else {
......@@ -848,7 +849,6 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
rah = ((DCI1_20MHz_FDD_t *)dci_pdu)->rah;
rballoc = ((DCI1_20MHz_FDD_t *)dci_pdu)->rballoc;
rv = ((DCI1_20MHz_FDD_t *)dci_pdu)->rv;
ndi = ((DCI1_20MHz_FDD_t *)dci_pdu)->ndi;
harq_pid = ((DCI1_20MHz_FDD_t *)dci_pdu)->harq_pid;
}
break;
......@@ -884,11 +884,27 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
dlsch[0]->layer_index = 0;
dlsch[0]->harq_processes[harq_pid]->mimo_mode = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
dlsch[0]->dl_power_off = 1;
dlsch[0]->harq_processes[harq_pid]->Ndi = ndi;
/*
if (dlsch[0]->harq_processes[harq_pid]->first_tx == 1) {
LOG_D(PHY,"First TX for C-RNTI %x, clearing first_tx flag, shouldn't happen!\n",rnti);
dlsch[0]->harq_processes[harq_pid]->first_tx=0;
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
else {
LOG_D(PHY,"Checking for Toggled Ndi for C-RNTI %x, old value %d, DCINdi %d\n",rnti,dlsch[0]->harq_processes[harq_pid]->DCINdi,ndi);
if (ndi == dlsch[0]->harq_processes[harq_pid]->DCINdi)
dlsch[0]->harq_processes[harq_pid]->Ndi = 0;
else
dlsch[0]->harq_processes[harq_pid]->Ndi = 1;
}
dlsch[0]->harq_processes[harq_pid]->DCINdi=ndi;
*/
dlsch[0]->active = 1;
if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
if (dlsch[0]->harq_processes[harq_pid]->round == 0) {
dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
// MCS and TBS don't change across HARQ rounds
......@@ -1009,8 +1025,8 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
if (frame_parms->mode1_flag == 1)
dlsch0->harq_processes[harq_pid]->mimo_mode = SISO;
dlsch0->harq_processes[harq_pid]->Ndi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
if (dlsch0->harq_processes[harq_pid]->Ndi == 1) {
// dlsch0->harq_processes[harq_pid]->Ndi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
if (dlsch0->harq_processes[harq_pid]->round == 0) {
dlsch0->harq_processes[harq_pid]->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
......@@ -1133,8 +1149,8 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
if (frame_parms->mode1_flag == 1)
dlsch0->harq_processes[harq_pid]->mimo_mode = SISO;
dlsch0->harq_processes[harq_pid]->Ndi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
if (dlsch0->harq_processes[harq_pid]->Ndi == 1) {
// dlsch0->harq_processes[harq_pid]->Ndi = ((DCI1E_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi;
if (dlsch0->harq_processes[harq_pid]->round == 0) {
dlsch0->harq_processes[harq_pid]->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
}
......@@ -1174,7 +1190,7 @@ int generate_eNB_dlsch_params_from_dci(uint8_t subframe,
msg("dlsch0 eNB: NBRB %d\n",dlsch0->nb_rb);
msg("dlsch0 eNB: rballoc %x\n",dlsch0->rb_alloc[0]);
msg("dlsch0 eNB: harq_pid %d\n",harq_pid);
msg("dlsch0 eNB: Ndi %d\n",dlsch0->harq_processes[harq_pid]->Ndi);
msg("dlsch0 eNB: round %d\n",dlsch0->harq_processes[harq_pid]->round);
msg("dlsch0 eNB: rvidx %d\n",dlsch0->harq_processes[harq_pid]->rvidx);
msg("dlsch0 eNB: TBS %d (NPRB %d)\n",dlsch0->harq_processes[harq_pid]->TBS,NPRB);
msg("dlsch0 eNB: mcs %d\n",dlsch0->harq_processes[harq_pid]->mcs);
......@@ -1652,7 +1668,6 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
harq_pid = 0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1) + 2;
ndi = 1;
}
else {
......@@ -1701,7 +1716,6 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
harq_pid = 0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1) + 2;
ndi = 1; // bit is reserved
}
else {
......@@ -1749,7 +1763,6 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
harq_pid = 0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1) + 2;
ndi = 1;
}
else {
......@@ -1799,7 +1812,7 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
harq_pid = 0;
// see 36-212 V8.6.0 p. 45
NPRB = (TPC&1) + 2;
ndi = 1;
// toggle the ndi
}
else {
......@@ -1844,6 +1857,11 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
return(-1);
}
if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)){ //
// toggle the ndi, always toggled for si,p and ra
ndi = 1-dlsch[0]->harq_processes[harq_pid]->DCINdi;
}
dlsch[0]->current_harq_pid = harq_pid;
// msg("Format 1A: harq_pid %d\n",harq_pid);
dlsch[0]->harq_processes[harq_pid]->rvidx = rv;
......@@ -1851,7 +1869,16 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch[0]->layer_index = 0;
dlsch[0]->harq_processes[harq_pid]->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI;
dlsch[0]->harq_processes[harq_pid]->dl_power_off = 1; //no power offset
dlsch[0]->harq_processes[harq_pid]->Ndi = ndi;
if ((ndi!=dlsch[0]->harq_processes[harq_pid]->DCINdi)|| // DCI has been toggled or this is the first transmission
(dlsch[0]->harq_processes[harq_pid]->first_tx==1)) {
dlsch[0]->harq_processes[harq_pid]->round = 0;
if (dlsch[0]->harq_processes[harq_pid]->first_tx==1)
LOG_D(PHY,"[PDSCH %x/%d] Format 1A DCI First TX: Clearing flag\n");
dlsch[0]->harq_processes[harq_pid]->first_tx = 0;
}
dlsch[0]->harq_processes[harq_pid]->DCINdi = ndi;
dlsch[0]->harq_processes[harq_pid]->mcs = mcs;
dlsch[0]->harq_processes[harq_pid]->TBS = TBStable[get_I_TBS(mcs)][NPRB-1];
dlsch[0]->rnti = rnti;
......@@ -1965,11 +1992,19 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch[0]->layer_index = 0;
dlsch[0]->harq_processes[harq_pid]->mimo_mode = (frame_parms->mode1_flag == 1) ? SISO : ALAMOUTI;
dlsch[0]->harq_processes[harq_pid]->dl_power_off = 1; //no power offset
dlsch[0]->harq_processes[harq_pid]->Ndi = ndi;
if (dlsch[0]->harq_processes[harq_pid]->Ndi == 1) {
LOG_D(PHY,"Format1 DCI: ndi %d, old_ndi %d (first tx %d)\n",ndi,dlsch[0]->harq_processes[harq_pid]->DCINdi,
dlsch[0]->harq_processes[harq_pid]->first_tx);
if ((ndi!=dlsch[0]->harq_processes[harq_pid]->DCINdi)||
(dlsch[0]->harq_processes[harq_pid]->first_tx==1)) {
dlsch[0]->harq_processes[harq_pid]->round=0;
dlsch[0]->harq_processes[harq_pid]->status = ACTIVE;
// printf("Setting DLSCH process %d to ACTIVE\n",harq_pid);
dlsch[0]->harq_processes[harq_pid]->DCINdi = ndi;
if (dlsch[0]->harq_processes[harq_pid]->first_tx==1)
LOG_D(PHY,"[PDSCH %x/%d] Format 1 DCI First TX: Clearing flag\n");
dlsch[0]->harq_processes[harq_pid]->first_tx = 0;
}
else if (dlsch[0]->harq_processes[harq_pid]->status == SCH_IDLE) { // we got an Ndi = 0 for a previously decoded process,
// this happens if either another harq process in the same
......@@ -2097,10 +2132,11 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
if (frame_parms->mode1_flag == 1)
dlsch0->harq_processes[harq_pid]->mimo_mode = SISO;
dlsch0->harq_processes[harq_pid]->Ndi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
if (dlsch0->harq_processes[harq_pid]->Ndi == 1)
if (((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1!=dlsch0->harq_processes[harq_pid]->DCINdi) {
dlsch0->harq_processes[harq_pid]->round = 0;
dlsch0->harq_processes[harq_pid]->status = ACTIVE;
dlsch0->harq_processes[harq_pid]->DCINdi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi1;
}
else if (dlsch0->harq_processes[harq_pid]->status == SCH_IDLE) { // we got an Ndi = 0 for a previously decoded process,
// this happens if either another harq process in the same
// is NAK or an ACK was not received
......@@ -2126,9 +2162,12 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
if (dlsch0->harq_processes[harq_pid]->mcs > 18)
printf("mcs %d, TBS %d\n",dlsch0->harq_processes[harq_pid]->mcs,dlsch0->harq_processes[harq_pid]->TBS);
*/
dlsch1->harq_processes[harq_pid]->Ndi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi2;
if (dlsch1->harq_processes[harq_pid]->Ndi == 1)
if (dlsch1->harq_processes[harq_pid]->DCINdi != ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi2) {
dlsch1->harq_processes[harq_pid]->round=0;
dlsch1->harq_processes[harq_pid]->status = ACTIVE;
}
dlsch1->harq_processes[harq_pid]->DCINdi = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->ndi2;
dlsch1->harq_processes[harq_pid]->mcs = ((DCI2_5MHz_2A_M10PRB_TDD_t *)dci_pdu)->mcs2;