Commit c4b7d4c1 authored by knopp's avatar knopp
Browse files

updates to UL (DFTs for 10/20 MHz), Ndi toggling, DCI structures

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4600 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 21635af2
...@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) { ...@@ -185,8 +185,9 @@ void sub_block_deinterleaving_turbo(uint32_t D,int16_t *d,int16_t *w) {
k++;k2++;k2++; k++;k2++;k2++;
} }
} }
if (ND>0)
d[2] = LTE_NULL;//d[(3*D)+2]; // if (ND>0)
// d[2] = LTE_NULL;//d[(3*D)+2];
} }
...@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC, ...@@ -476,19 +477,19 @@ uint32_t lte_rate_matching_turbo(uint32_t RTC,
k=0; k=0;
for (;(ind<Ncb)&&(k<E);ind++) { for (;(ind<Ncb)&&(k<E);ind++) {
e2[k]=w[ind]; // e2[k]=w[ind];
#ifdef RM_DEBUG_TX #ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]); printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif #endif
if (w[ind] != LTE_NULL) k++; if (w[ind] != LTE_NULL) e2[k++]=w[ind];
} }
while(k<E) { while(k<E) {
for (ind=0;(ind<Ncb)&&(k<E);ind++) { for (ind=0;(ind<Ncb)&&(k<E);ind++) {
e2[k] = w[ind]; // e2[k] = w[ind];
#ifdef RM_DEBUG_TX #ifdef RM_DEBUG_TX
printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]); printf("RM_TX k%d Ind: %d (%d)\n",k,ind,w[ind]);
#endif #endif
if (w[ind] != LTE_NULL) k++; if (w[ind] != LTE_NULL) e2[k++]=w[ind];
} }
} }
/* /*
......
...@@ -1963,7 +1963,7 @@ u8 get_num_pdcch_symbols(u8 num_dci, ...@@ -1963,7 +1963,7 @@ u8 get_num_pdcch_symbols(u8 num_dci,
// compute numCCE // compute numCCE
for (i=0;i<num_dci;i++) { for (i=0;i<num_dci;i++) {
// printf("dci %d => %d\n",i,dci_alloc[i].L); // printf("dci %d => %d\n",i,dci_alloc[i].L);
numCCE += (1<<(dci_alloc[i].L)); numCCE += (1<<(dci_alloc[i].L));
} }
...@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2017,11 +2017,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mod_sym_t *y[2]; mod_sym_t *y[2];
mod_sym_t *wbar[2]; mod_sym_t *wbar[2];
#ifdef IFFT_FPGA
u8 qpsk_table_offset = 0;
u8 qpsk_table_offset2 = 0;
#endif
int nushiftmod3 = frame_parms->nushift%3; int nushiftmod3 = frame_parms->nushift%3;
int Msymb2; int Msymb2;
...@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2129,7 +2124,7 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr = e; e_ptr = e;
if (frame_parms->mode1_flag) { //SISO if (frame_parms->mode1_flag) { //SISO
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i++) { for (i=0;i<Msymb2;i++) {
//((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; //((s16*)(&(y[0][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
//((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK; //((s16*)(&(y[1][i])))[0] = (*e_ptr == 1) ? -gain_lin_QPSK : gain_lin_QPSK;
...@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2144,25 +2139,10 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
e_ptr++; e_ptr++;
} }
#else
for (i=0;i<Msymb2;i++) {
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET;
if (*e_ptr == 1)
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1)
qpsk_table_offset+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset;
y[1][i] = (mod_sym_t) qpsk_table_offset;
}
#endif
} }
else { //ALAMOUTI else { //ALAMOUTI
#ifndef IFFT_FPGA
for (i=0;i<Msymb2;i+=2) { for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING #ifdef DEBUG_DCI_ENCODING
...@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2187,49 +2167,6 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1]; ((s16*)&y[1][i+1])[1] = -((s16*)&y[0][i])[1];
} }
#else
for (i=0;i<Msymb2;i+=2) {
#ifdef DEBUG_DCI_ENCODING
LOG_I(PHY," PDCCH Modulation: Symbol %d : REG %d/%d\n",i,i>>2,Msymb2>>2);
#endif
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //x0
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x0*
if (*e_ptr == 1) { //real
qpsk_table_offset+=2;
qpsk_table_offset2+=2;
}
e_ptr++;
if (*e_ptr == 1) //imag
qpsk_table_offset+=1;
else
qpsk_table_offset2+=1;
e_ptr++;
y[0][i] = (mod_sym_t) qpsk_table_offset; // x0
y[1][i+1] = (mod_sym_t) qpsk_table_offset2; // x0*
qpsk_table_offset = MOD_TABLE_QPSK_OFFSET; //-x1*
qpsk_table_offset2 = MOD_TABLE_QPSK_OFFSET; //x1
if (*e_ptr == 1) // flipping bit for real part of symbol means taking -x1*
qpsk_table_offset2+=2;
else
qpsk_table_offset+=2;
e_ptr++;
if (*e_ptr == 1) {
qpsk_table_offset+=1;
qpsk_table_offset2+=1;
}
e_ptr++;
y[1][i] = (mod_sym_t) qpsk_table_offset; // -x1*
y[0][i+1] = (mod_sym_t) qpsk_table_offset2; // x1
}
#endif
} }
...@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2243,23 +2180,14 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
mprime=0; mprime=0;
nsymb = (frame_parms->Ncp==0) ? 14:12; nsymb = (frame_parms->Ncp==0) ? 14:12;
#ifdef IFFT_FPGA
re_offset = frame_parms->N_RB_DL*12/2;
#else
re_offset = frame_parms->first_carrier_offset; re_offset = frame_parms->first_carrier_offset;
#endif
// This is the REG allocation algorithm from 36-211, second part of Section 6.8.5 // This is the REG allocation algorithm from 36-211, second part of Section 6.8.5
// printf("DCI : txdataF %p (0 %p)\n",&txdataF[0][512*14*subframe],&txdataF[0][0]); // printf("DCI (SF %d) : txdataF %p (0 %p)\n",subframe,&txdataF[0][512*14*subframe],&txdataF[0][0]);
for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) { for (kprime=0;kprime<frame_parms->N_RB_DL*12;kprime++) {
for (lprime=0;lprime<num_pdcch_symbols;lprime++) { for (lprime=0;lprime<num_pdcch_symbols;lprime++) {
#ifdef IFFT_FPGA
symbol_offset = (u32)frame_parms->N_RB_DL*12*(lprime+(subframe*nsymb));
#else
symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb)); symbol_offset = (u32)frame_parms->ofdm_symbol_size*(lprime+(subframe*nsymb));
#endif
...@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci, ...@@ -2353,14 +2281,8 @@ u8 generate_dci_top(u8 num_ue_spec_dci,
} //lprime loop } //lprime loop
re_offset++; re_offset++;
#ifdef IFFT_FPGA
if (re_offset == (frame_parms->N_RB_DL*12))
re_offset = 0;
#else
if (re_offset == (frame_parms->ofdm_symbol_size)) if (re_offset == (frame_parms->ofdm_symbol_size))
re_offset = 1; re_offset = 1;
#endif
} // kprime loop } // kprime loop
return(num_pdcch_symbols); return(num_pdcch_symbols);
} }
......
...@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t; ...@@ -100,9 +100,7 @@ typedef struct DCI0_1_5MHz_TDD_1_6 DCI0_1_5MHz_TDD_1_6_t;
/// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits) /// DCI Format Type 1A (1.5 MHz, TDD, frame 1-6, 24 bits)
struct DCI1A_1_5MHz_TDD_1_6 { struct DCI1A_1_5MHz_TDD_1_6 {
/// padding /// padding
uint32_t padding:8; uint32_t padding:9;
/// SRS request bit
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t; ...@@ -212,9 +210,7 @@ typedef struct DCI0_10MHz_TDD_1_6 DCI0_10MHz_TDD_1_6_t;
/// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits) /// DCI Format Type 1A (10 MHz, TDD, frame 1-6, 30 bits)
struct DCI1A_10MHz_TDD_1_6 { struct DCI1A_10MHz_TDD_1_6 {
/// padding /// padding
uint32_t padding:2; uint32_t padding:3;
/// SRS request bit
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t; ...@@ -243,7 +239,7 @@ typedef struct DCI1A_10MHz_TDD_1_6 DCI1A_10MHz_TDD_1_6_t;
struct DCI0_20MHz_TDD_1_6 { struct DCI0_20MHz_TDD_1_6 {
/// Padding /// Padding
uint32_t padding:2; uint32_t padding:2;
/// CQI Request /// CQI request
uint32_t cqi_req:1; uint32_t cqi_req:1;
/// DAI /// DAI
uint32_t dai:2; uint32_t dai:2;
...@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t; ...@@ -268,8 +264,7 @@ typedef struct DCI0_20MHz_TDD_1_6 DCI0_20MHz_TDD_1_6_t;
/// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits) /// DCI Format Type 1A (20 MHz, TDD, frame 1-6, 27 bits)
struct DCI1A_20MHz_TDD_1_6 { struct DCI1A_20MHz_TDD_1_6 {
/// SRS request bit uint32_t padding:1;
uint32_t srs_req:1;
/// Downlink Assignment Index /// Downlink Assignment Index
uint32_t dai:2; uint32_t dai:2;
/// Power Control /// Power Control
...@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t; ...@@ -321,9 +316,7 @@ typedef struct DCI0_1_5MHz_FDD DCI0_1_5MHz_FDD_t;
struct DCI1A_1_5MHz_FDD { struct DCI1A_1_5MHz_FDD {
/// padding /// padding
uint32_t padding:11; uint32_t padding:12;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t; ...@@ -374,9 +367,7 @@ typedef struct DCI0_5MHz_FDD DCI0_5MHz_FDD_t;
struct DCI1A_5MHz_FDD { struct DCI1A_5MHz_FDD {
/// padding /// padding
uint32_t padding:7; uint32_t padding:8;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t; ...@@ -428,9 +419,7 @@ typedef struct DCI0_10MHz_FDD DCI0_10MHz_FDD_t;
struct DCI1A_10MHz_FDD { struct DCI1A_10MHz_FDD {
/// padding /// padding
uint32_t padding:5; uint32_t padding:6;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
...@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t; ...@@ -480,9 +469,7 @@ typedef struct DCI0_20MHz_FDD DCI0_20MHz_FDD_t;
struct DCI1A_20MHz_FDD { struct DCI1A_20MHz_FDD {
/// padding /// padding
uint32_t padding:3; uint32_t padding:4;
/// Downlink Assignment Index
uint32_t srs_req:1;
/// Power Control /// Power Control
uint32_t TPC:2; uint32_t TPC:2;
/// Redundancy version /// Redundancy version
......
This diff is collapsed.
...@@ -88,8 +88,6 @@ typedef enum { ...@@ -88,8 +88,6 @@ typedef enum {
typedef struct { typedef struct {
/// Flag indicating that this DLSCH is active (i.e. not the first round)
uint8_t Ndi;
/// Status Flag indicating for this DLSCH (idle,active,disabled) /// Status Flag indicating for this DLSCH (idle,active,disabled)
SCH_status_t status; SCH_status_t status;
/// Transport block size /// Transport block size
...@@ -131,8 +129,12 @@ typedef struct { ...@@ -131,8 +129,12 @@ typedef struct {
} LTE_DL_eNB_HARQ_t; } LTE_DL_eNB_HARQ_t;
typedef struct { typedef struct {
/// Indicator of first transmission
uint8_t first_tx;
/// Last Ndi received for this process on DCI (used for C-RNTI only)
uint8_t DCINdi;
/// Flag indicating that this ULSCH has a new packet (start of new round) /// Flag indicating that this ULSCH has a new packet (start of new round)
uint8_t Ndi; // uint8_t Ndi;
/// Status Flag indicating for this ULSCH (idle,active,disabled) /// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status; SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator) /// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
...@@ -325,8 +327,6 @@ typedef struct { ...@@ -325,8 +327,6 @@ typedef struct {
uint8_t dci_alloc; uint8_t dci_alloc;
/// Flag indicating that this ULSCH has been allocated by a RAR (otherwise it is a retransmission based on PHICH NAK or DCI) /// Flag indicating that this ULSCH has been allocated by a RAR (otherwise it is a retransmission based on PHICH NAK or DCI)
uint8_t rar_alloc; uint8_t rar_alloc;
/// Flag indicating that this ULSCH has new data
uint8_t Ndi;
/// Status Flag indicating for this ULSCH (idle,active,disabled) /// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status; SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator) /// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
...@@ -463,8 +463,10 @@ typedef struct { ...@@ -463,8 +463,10 @@ typedef struct {
} LTE_eNB_ULSCH_t; } LTE_eNB_ULSCH_t;
typedef struct { typedef struct {
/// Flag indicating that this DLSCH has a new transport block /// Indicator of first transmission
uint8_t Ndi; uint8_t first_tx;
/// Last Ndi received for this process on DCI (used for C-RNTI only)
uint8_t DCINdi;
/// DLSCH status flag indicating /// DLSCH status flag indicating
SCH_status_t status; SCH_status_t status;
/// Transport block size /// Transport block size
......
...@@ -141,6 +141,7 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,unsigne ...@@ -141,6 +141,7 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,unsigne
MAX_DLSCH_PAYLOAD_BYTES/bw_scaling,bw_scaling, i,dlsch->harq_processes[i]); MAX_DLSCH_PAYLOAD_BYTES/bw_scaling,bw_scaling, i,dlsch->harq_processes[i]);
if (dlsch->harq_processes[i]) { if (dlsch->harq_processes[i]) {
bzero(dlsch->harq_processes[i],sizeof(LTE_DL_eNB_HARQ_t)); bzero(dlsch->harq_processes[i],sizeof(LTE_DL_eNB_HARQ_t));
// dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (unsigned char*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); dlsch->harq_processes[i]->b = (unsigned char*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b) { if (dlsch->harq_processes[i]->b) {
bzero(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); bzero(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
...@@ -202,7 +203,7 @@ void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch, u8 abstraction_flag) { ...@@ -202,7 +203,7 @@ void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch, u8 abstraction_flag) {
for (i=0;i<Mdlharq;i++) { for (i=0;i<Mdlharq;i++) {
if (dlsch->harq_processes[i]) { if (dlsch->harq_processes[i]) {
dlsch->harq_processes[i]->Ndi = 0; // dlsch->harq_processes[i]->Ndi = 0;
dlsch->harq_processes[i]->status = 0; dlsch->harq_processes[i]->status = 0;
dlsch->harq_processes[i]->round = 0; dlsch->harq_processes[i]->round = 0;
if (abstraction_flag==0) { if (abstraction_flag==0) {
...@@ -245,7 +246,8 @@ int dlsch_encoding(unsigned char *a, ...@@ -245,7 +246,8 @@ int dlsch_encoding(unsigned char *a,
G = get_G(frame_parms,nb_rb,dlsch->rb_alloc,mod_order,num_pdcch_symbols,frame,subframe); G = get_G(frame_parms,nb_rb,dlsch->rb_alloc,mod_order,num_pdcch_symbols,frame,subframe);
if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet // if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet
if (dlsch->harq_processes[harq_pid]->round == 0) { // this is a new packet
/* /*
int i; int i;
...@@ -382,7 +384,8 @@ void dlsch_encoding_emul(PHY_VARS_eNB *phy_vars_eNB, ...@@ -382,7 +384,8 @@ void dlsch_encoding_emul(PHY_VARS_eNB *phy_vars_eNB,
unsigned char harq_pid = dlsch->current_harq_pid; unsigned char harq_pid = dlsch->current_harq_pid;
unsigned short i; unsigned short i;
if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // if (dlsch->harq_processes[harq_pid]->Ndi == 1) {
if (dlsch->harq_processes[harq_pid]->round == 0) {
memcpy(dlsch->harq_processes[harq_pid]->b, memcpy(dlsch->harq_processes[harq_pid]->b,
DLSCH_pdu, DLSCH_pdu,
dlsch->harq_processes[harq_pid]->TBS>>3); dlsch->harq_processes[harq_pid]->TBS>>3);
......
...@@ -111,6 +111,7 @@ LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_ite ...@@ -111,6 +111,7 @@ LTE_UE_DLSCH_t *new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint8_t max_turbo_ite
dlsch->harq_processes[i] = (LTE_DL_UE_HARQ_t *)malloc16(sizeof(LTE_DL_UE_HARQ_t)); dlsch->harq_processes[i] = (LTE_DL_UE_HARQ_t *)malloc16(sizeof(LTE_DL_UE_HARQ_t));
if (dlsch->harq_processes[i]) { if (dlsch->harq_processes[i]) {
memset(dlsch->harq_processes[i],0,sizeof(LTE_DL_UE_HARQ_t)); memset(dlsch->harq_processes[i],0,sizeof(LTE_DL_UE_HARQ_t));
dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b) if (dlsch->harq_processes[i]->b)
memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling); memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
...@@ -235,7 +236,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue, ...@@ -235,7 +236,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
// msg("DLSCH Decoding, harq_pid %d Ndi %d\n",harq_pid,harq_process->Ndi); // msg("DLSCH Decoding, harq_pid %d Ndi %d\n",harq_pid,harq_process->Ndi);
if (harq_process->Ndi == 1) { if (harq_process->round == 0) {
// This is a new packet, so compute quantities regarding segmentation // This is a new packet, so compute quantities regarding segmentation
harq_process->B = A+24; harq_process->B = A+24;
lte_segmentation(NULL, lte_segmentation(NULL,
...@@ -309,7 +310,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue, ...@@ -309,7 +310,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
dlsch->Mdlharq, dlsch->Mdlharq,
dlsch->Kmimo, dlsch->Kmimo,
harq_process->rvidx, harq_process->rvidx,
harq_process->Ndi, (harq_process->round==0)?1:0,
get_Qm(harq_process->mcs), get_Qm(harq_process->mcs),
harq_process->Nl, harq_process->Nl,
r, r,
...@@ -718,7 +719,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue, ...@@ -718,7 +719,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue,
dlsch_ue->harq_ack[subframe].ack = 1; dlsch_ue->harq_ack[subframe].ack = 1;
dlsch_ue->harq_ack[subframe].harq_id = harq_pid; dlsch_ue->harq_ack[subframe].harq_id = harq_pid;
dlsch_ue->harq_ack[subframe].send_harq_status = 1; dlsch_ue->harq_ack[subframe].send_harq_status = 1;
if (dlsch_ue->harq_processes[harq_pid]->Ndi == 1) if (dlsch_ue->harq_processes[harq_pid]->round == 0)
memcpy(dlsch_ue->harq_processes[harq_pid]->b, memcpy(dlsch_ue->harq_processes[harq_pid]->b,
dlsch_eNB->harq_processes[harq_pid]->b, dlsch_eNB->harq_processes[harq_pid]->b,
dlsch_ue->harq_processes[harq_pid]->TBS>>3); dlsch_ue->harq_processes[harq_pid]->TBS>>3);
...@@ -746,7 +747,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue, ...@@ -746,7 +747,7 @@ uint32_t dlsch_decoding_emul(PHY_VARS_UE *phy_vars_ue,
dlsch_ue->harq_ack[subframe].ack = 1; dlsch_ue->harq_ack[subframe].ack = 1;
dlsch_ue->harq_ack[subframe].harq_id = harq_pid; dlsch_ue->harq_ack[subframe].harq_id = harq_pid;
dlsch_ue->harq_ack[subframe].send_harq_status = 1; dlsch_ue->harq_ack[subframe].send_harq_status = 1;
if (dlsch_ue->harq_processes[harq_pid]->Ndi == 1) if (dlsch_ue->harq_processes[harq_pid]->round == 0)
memcpy(dlsch_eNB->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->TBS>>3); memcpy(dlsch_eNB->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->b,dlsch_ue->harq_processes[harq_pid]->TBS>>3);
break; break;
default: default:
......
...@@ -1258,7 +1258,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue, ...@@ -1258,7 +1258,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue,
&phy_vars_ue->ulsch_ue_Msg3_frame[eNB_id], &phy_vars_ue->ulsch_ue_Msg3_frame[eNB_id],
&phy_vars_ue->ulsch_ue_Msg3_subframe[eNB_id]); &phy_vars_ue->ulsch_ue_Msg3_subframe[eNB_id]);
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1; ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch->harq_processes[harq_pid]->Ndi = 0; // ulsch->harq_processes[harq_pid]->Ndi = 0;
ulsch->harq_processes[harq_pid]->round++; ulsch->harq_processes[harq_pid]->round++;
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3]; ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
if (ulsch->harq_processes[harq_pid]->round>=phy_vars_ue->lte_frame_parms.maxHARQ_Msg3Tx) { if (ulsch->harq_processes[harq_pid]->round>=phy_vars_ue->lte_frame_parms.maxHARQ_Msg3Tx) {
...@@ -1279,7 +1279,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue, ...@@ -1279,7 +1279,7 @@ void rx_phich(PHY_VARS_UE *phy_vars_ue,
ngroup_PHICH); ngroup_PHICH);
//#endif //#endif
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1; ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch->harq_processes[harq_pid]->Ndi = 0; // ulsch->harq_processes[harq_pid]->Ndi = 0;
ulsch->harq_processes[harq_pid]->round++; ulsch->harq_processes[harq_pid]->round++;
ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3]; ulsch->harq_processes[harq_pid]->rvidx = rv_table[ulsch->harq_processes[harq_pid]->round&3];
} }
...@@ -1400,7 +1400,7 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB, ...@@ -1400,7 +1400,7 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB,
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH ACK / (no format0 DCI) Setting subframe_scheduling_flag\n", LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH ACK / (no format0 DCI) Setting subframe_scheduling_flag\n",
phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->frame,subframe); phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->frame,subframe);
ulsch_eNB[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1; ulsch_eNB[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch_eNB[UE_id]->harq_processes[harq_pid]->Ndi = 0; // ulsch_eNB[UE_id]->harq_processes[harq_pid]->Ndi = 0;
// ulsch_eNB[UE_id]->harq_processes[harq_pid]->round++; //this is already done in phy_procedures // ulsch_eNB[UE_id]->harq_processes[harq_pid]->round++; //this is already done in phy_procedures
ulsch_eNB[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch_eNB[UE_id]->harq_processes[harq_pid]->round&3]; ulsch_eNB[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch_eNB[UE_id]->harq_processes[harq_pid]->round&3];
} }
......
...@@ -62,13 +62,8 @@ void generate_pilots(PHY_VARS_eNB *phy_vars_eNB, ...@@ -62,13 +62,8 @@ void generate_pilots(PHY_VARS_eNB *phy_vars_eNB,
#ifdef IFFT_FPGA
tti_offset = tti*frame_parms->N_RB_DL*12*Nsymb;
samples_per_symbol = frame_parms->N_RB_DL*12;
#else
tti_offset = tti*frame_parms->ofdm_symbol_size*Nsymb; tti_offset = tti*frame_parms->ofdm_symbol_size*Nsymb;