diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index 61e44bdd55c41b796f0a3fe162f6ac2923b1395d..7a8634f468aa5fe1a1b459638805e0e5b4d1c6f7 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -2,13 +2,12 @@
We want to make contributing to this project as easy and transparent as possible.
-Please refer to the steps described on our website: [How to contribute to OAI](https://www.openairinterface.org/?page_id=112)
-
1. Sign and return a Contributor License Agreement to OAI team.
-2. Create an account on [Eurecom GitLab Server](https://gitlab.eurecom.fr).
-3. Provide the identifiant of this account to the OAI team (mailto:contact@openairinterface.org) so you have developer rights on this repository.
+2. We recommend that you provide us with a professional or student email address
+2. Register on [Eurecom GitLab Server](https://gitlab.eurecom.fr/users/sign_in)
+3. Provide the OAI team with the **username** of this account to (mailto:contact@openairinterface.org) ; we will give you the developer rights on this repository.
4. The policies are described in these wiki pages: [OAI Policies](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/oai-policies-home)
- - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers.
+ - PLEASE DO NOT FORK the OAI repository on your own Eurecom GitLab account. It just eats up space on our servers.
- You can fork onto another hosting system. But we will NOT accept a merge request from a forked repository.
* This decision was made for the license reasons.
* The Continuous Integration will reject your merge request.
diff --git a/ci-scripts/.gitignore b/ci-scripts/.gitignore
index dc5e7c747645122e82e4e54a31492151d629680b..34d19403a7c3f1169391296970ea44e99e4740a9 100644
--- a/ci-scripts/.gitignore
+++ b/ci-scripts/.gitignore
@@ -1,3 +1,4 @@
+r*.raw
enb_*.log
ue_*.log
ping_*.*
diff --git a/ci-scripts/Jenkinsfile-gitlab b/ci-scripts/Jenkinsfile-gitlab
index 8dfa5c4ec4c93895262d81b6909fe54918d2cac1..c3b997a4e89e015722df42a63979073cae3f3351 100644
--- a/ci-scripts/Jenkinsfile-gitlab
+++ b/ci-scripts/Jenkinsfile-gitlab
@@ -66,7 +66,8 @@ pipeline {
"Test-IF4p5-TDD-Band38-Multi-RRU",
"Test-eNB-OAI-UE-FDD-Band7",
"Test-Mono-FDD-Band13-X2-HO",
- "Test-TDD-Band78-gNB-NR-UE"
+ "Test-TDD-Band78-gNB-NR-UE",
+ "Test-OCP-FDD-Band7"
])
ansiColor('xterm')
}
@@ -683,6 +684,25 @@ pipeline {
}
}
}
+ stage ("Test OAI OCP-eNB - FDD - Band 7 - B210") {
+ steps {
+ script {
+ triggerSlaveJob ('OCPeNB-FDD-Band7-B210', 'Test-OCP-FDD-Band7')
+ }
+ }
+ post {
+ always {
+ script {
+ finalizeSlaveJob('OCPeNB-FDD-Band7-B210')
+ }
+ }
+ failure {
+ script {
+ currentBuild.result = 'FAILURE'
+ }
+ }
+ }
+ }
}
post {
always {
diff --git a/ci-scripts/Jenkinsfile-inria-r2lab b/ci-scripts/Jenkinsfile-inria-r2lab
index ca6893dc4ff36d7711c37b2b02739ed848ee029f..ada52277f4ea702b21edecdc1f18ec9b541560e3 100644
--- a/ci-scripts/Jenkinsfile-inria-r2lab
+++ b/ci-scripts/Jenkinsfile-inria-r2lab
@@ -62,6 +62,7 @@ def r2labUE0IpAddr = r2labBaseIpAddr + r2labUE0Idx
def r2labENB1Idx = '16'
def r2labENB1 = 'fit' + r2labENB1Idx
def r2labENB1IpAddr = r2labBaseIpAddr + r2labENB1Idx
+def r2labDoAllOff = true
pipeline {
agent {
@@ -136,22 +137,28 @@ pipeline {
sh "python3 /home/eurecom/inria-scripts/booking-lease.py --book-lease --from ${BOOK_TIMESTAMP}T${r2labStartTime} --duration ${r2labDuration} --slice inria_oaici ${r2labuser} ${r2labpassword}"
sh "python3 /home/eurecom/inria-scripts/booking-lease.py --get-leases ${r2labuser} ${r2labpassword} | grep -v nightly"
}
+
+ // Adding a tempo after booking leases
+ sh "sleep 10"
+ LEASE_STATUS = sh returnStdout: true, script: "ssh -t inria_oaici@faraday.inria.fr 'rleases --check'"
+ LEASE_STATUS = LEASE_STATUS.trim()
+ if (LEASE_STATUS ==~ /.*Access currently denied to inria_oaici.*/) {
+ r2labDoAllOff = false
+ currentBuild.result = 'ABORTED'
+ error('Stopping early because R2LAB not available')
+ }
}
}
}
stage ("Load Images") {
steps {
script {
- // Adding a tempo after booking leases
- sh "sleep 10"
- sh "ssh -t inria_oaici@faraday.inria.fr 'rleases --check'"
sh "ssh -t inria_oaici@faraday.inria.fr 'all-off'"
sh "sleep 10"
echo '\u2705 \u001B[32mLoad Image for Python Executor\u001B[0m'
try {
- //sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labPythonExeIdx} > /dev/null 2>&1'"
- sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labPythonExeIdx}'"
+ sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labPythonExeIdx} > /dev/null 2>&1'"
} catch (Exception e) {
echo "Why is it wrong?"
}
@@ -164,14 +171,12 @@ pipeline {
echo '\u2705 \u001B[32mLoad Image for two (2) eNBs\u001B[0m'
try {
- //sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labENB0Idx},${r2labENB1Idx} > /dev/null 2>&1'"
- sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labENB0Idx},${r2labENB1Idx}"
+ sh "ssh -t inria_oaici@faraday.inria.fr 'rload -i oai-ci-cd-u18-lowlatency-enb-ue ${r2labENB0Idx},${r2labENB1Idx} > /dev/null 2>&1'"
} catch (Exception e) {
echo "Why is it wrong?"
}
try {
- //sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labENB0Idx},${r2labENB1Idx}'"
- sh "ssh -t inria_oaici@faraday.inria.fr 'rwait ${r2labENB0Idx},${r2labENB1Idx}'"
+ sh "ssh -t inria_oaici@faraday.inria.fr 'rwait --silent ${r2labENB0Idx},${r2labENB1Idx}'"
} catch (Exception e) {
echo "Why is it wrong?"
}
@@ -441,9 +446,11 @@ pipeline {
post {
always {
script {
- echo '\u2705 \u001B[32mShutdown every node\u001B[0m'
- sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"'
- sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"'
+ if (r2labDoAllOff) {
+ echo '\u2705 \u001B[32mShutdown every node\u001B[0m'
+ sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"'
+ sh 'ssh -t inria_oaici@faraday.inria.fr "all-off"'
+ }
}
}
}
diff --git a/ci-scripts/args_parse.py b/ci-scripts/args_parse.py
new file mode 100644
index 0000000000000000000000000000000000000000..1249f521728c1e846f7dfb8871185d966292aa40
--- /dev/null
+++ b/ci-scripts/args_parse.py
@@ -0,0 +1,229 @@
+
+# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+# * contributor license agreements. See the NOTICE file distributed with
+# * this work for additional information regarding copyright ownership.
+# * The OpenAirInterface Software Alliance licenses this file to You under
+# * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+# * except in compliance with the License.
+# * You may obtain a copy of the License at
+# *
+# * http://www.openairinterface.org/?page_id=698
+# *
+# * Unless required by applicable law or agreed to in writing, software
+# * distributed under the License is distributed on an "AS IS" BASIS,
+# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# * See the License for the specific language governing permissions and
+# * limitations under the License.
+# *-------------------------------------------------------------------------------
+# * For more information about the OpenAirInterface (OAI) Software Alliance:
+# * contact@openairinterface.org
+# */
+#---------------------------------------------------------------------
+# Python for CI of OAI-eNB + COTS-UE
+#
+# Required Python Version
+# Python 3.x
+#
+# Required Python Package
+# pexpect
+#---------------------------------------------------------------------
+
+#-----------------------------------------------------------
+# Import Libs
+#-----------------------------------------------------------
+import sys # arg
+import re # reg
+import yaml
+
+
+#-----------------------------------------------------------
+# Parsing Command Line Arguements
+#-----------------------------------------------------------
+
+
+def ArgsParse(argvs,CiTestObj,RAN,HTML,EPC,ldpc,HELP):
+
+
+ py_param_file_present = False
+ py_params={}
+
+ while len(argvs) > 1:
+ myArgv = argvs.pop(1) # 0th is this file's name
+
+ #--help
+ if re.match('^\-\-help$', myArgv, re.IGNORECASE):
+ HELP.GenericHelp(CONST.Version)
+ sys.exit(0)
+
+ #--apply=<filename> as parameters file, to replace inline parameters
+ elif re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-Apply=(.+)$', myArgv, re.IGNORECASE)
+ py_params_file = matchReg.group(1)
+ with open(py_params_file,'r') as file:
+ # The FullLoader parameter handles the conversion from YAML
+ # scalar values to Python dictionary format
+ py_params = yaml.load(file,Loader=yaml.FullLoader)
+ py_param_file_present = True #to be removed once validated
+ #AssignParams(py_params) #to be uncommented once validated
+
+ #consider inline parameters
+ elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE)
+ mode = matchReg.group(1)
+ elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE)
+ else:
+ matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.ranRepository = matchReg.group(1)
+ RAN.ranRepository=matchReg.group(1)
+ HTML.ranRepository=matchReg.group(1)
+ ldpc.ranRepository=matchReg.group(1)
+ elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE)
+ else:
+ matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE)
+ doMerge = matchReg.group(1)
+ ldpc.ranAllowMerge=matchReg.group(1)
+ if ((doMerge == 'true') or (doMerge == 'True')):
+ CiTestObj.ranAllowMerge = True
+ RAN.ranAllowMerge=True
+ HTML.ranAllowMerge=True
+ elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE)
+ else:
+ matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.ranBranch = matchReg.group(1)
+ RAN.ranBranch=matchReg.group(1)
+ HTML.ranBranch=matchReg.group(1)
+ ldpc.ranBranch=matchReg.group(1)
+ elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE)
+ else:
+ matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE)
+ CiTestObj.ranCommitID = matchReg.group(1)
+ RAN.ranCommitID=matchReg.group(1)
+ HTML.ranCommitID=matchReg.group(1)
+ ldpc.ranCommitID=matchReg.group(1)
+ elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE)
+ else:
+ matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE)
+ CiTestObj.ranTargetBranch = matchReg.group(1)
+ RAN.ranTargetBranch=matchReg.group(1)
+ HTML.ranTargetBranch=matchReg.group(1)
+ ldpc.ranTargetBranch=matchReg.group(1)
+ elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNBIPAddress=matchReg.group(1)
+ ldpc.eNBIpAddr=matchReg.group(1)
+ elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB1IPAddress=matchReg.group(1)
+ elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB2IPAddress=matchReg.group(1)
+ elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNBUserName=matchReg.group(1)
+ ldpc.eNBUserName=matchReg.group(1)
+ elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB1UserName=matchReg.group(1)
+ elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB2UserName=matchReg.group(1)
+ elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNBPassword=matchReg.group(1)
+ ldpc.eNBPassWord=matchReg.group(1)
+ elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB1Password=matchReg.group(1)
+ elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB2Password=matchReg.group(1)
+ elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNBSourceCodePath=matchReg.group(1)
+ ldpc.eNBSourceCodePath=matchReg.group(1)
+ elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB1SourceCodePath=matchReg.group(1)
+ elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE)
+ RAN.eNB2SourceCodePath=matchReg.group(1)
+ elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE)
+ EPC.IPAddress=matchReg.group(1)
+ elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE)
+ EPC.UserName=matchReg.group(1)
+ elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE)
+ EPC.Password=matchReg.group(1)
+ elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE)
+ EPC.SourceCodePath=matchReg.group(1)
+ elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE)
+ if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-Docker', matchReg.group(1), re.IGNORECASE):
+ EPC.Type=matchReg.group(1)
+ else:
+ sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS or OAI-Rel14-Docker)')
+ elif re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-EPCContainerPrefix=(.+)$', myArgv, re.IGNORECASE)
+ EPC.ContainerPrefix=matchReg.group(1)
+ elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.ADBIPAddress = matchReg.group(1)
+ elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.ADBUserName = matchReg.group(1)
+ elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE)
+ if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE):
+ if re.match('distributed', matchReg.group(1), re.IGNORECASE):
+ CiTestObj.ADBCentralized = False
+ else:
+ CiTestObj.ADBCentralized = True
+ else:
+ sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)')
+ elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.ADBPassword = matchReg.group(1)
+ elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.testXMLfiles.append(matchReg.group(1))
+ HTML.testXMLfiles.append(matchReg.group(1))
+ HTML.nbTestXMLfiles=HTML.nbTestXMLfiles+1
+ elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.UEIPAddress = matchReg.group(1)
+ elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.UEUserName = matchReg.group(1)
+ elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.UEPassword = matchReg.group(1)
+ elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE)
+ CiTestObj.UESourceCodePath = matchReg.group(1)
+ elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE):
+ matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE)
+ finalStatus = matchReg.group(1)
+ if ((finalStatus == 'true') or (finalStatus == 'True')):
+ CiTestObj.finalStatus = True
+ else:
+ HELP.GenericHelp(CONST.Version)
+ sys.exit('Invalid Parameter: ' + myArgv)
+
+ return py_param_file_present, py_params, mode
diff --git a/ci-scripts/checkAddedWarnings.sh b/ci-scripts/checkAddedWarnings.sh
index d366059a853cf39ea2deaa771dee93de2c5b2e8e..bda8287a784862ddc7a050e2216385231f6d3e76 100755
--- a/ci-scripts/checkAddedWarnings.sh
+++ b/ci-scripts/checkAddedWarnings.sh
@@ -110,7 +110,7 @@ MODIFIED_FILES=`git log $TARGET_INIT_COMMIT..$MERGE_COMMMIT --oneline --name-sta
NB_WARNINGS_FILES=0
# Retrieve list of warnings
-LIST_WARNING_FILES=`egrep "error:|warning:" archives/*/*.Rel15.txt archives/*/basic_simulator_*txt | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | sed -e "s#^.*/home/ubuntu/tmp/##" -e "s#^.*/tmp/CI-eNB/##" -e "s#common/utils/.*/itti#common/utils/itti#" | awk -F ":" '{print $1}' | sort | uniq`
+LIST_WARNING_FILES=`egrep "error:|warning:" archives/*/*.Rel15.txt | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | sed -e "s#^.*/home/ubuntu/tmp/##" -e "s#^.*/tmp/CI-eNB/##" -e "s#common/utils/.*/itti#common/utils/itti#" | awk -F ":" '{print $1}' | sort | uniq`
echo ""
echo "List of files that have been modified by the Merge Request AND"
diff --git a/ci-scripts/checkCodingFormattingRules.sh b/ci-scripts/checkCodingFormattingRules.sh
index 6ac43ca19fefd240bcaf64e13c2aeac48889a4eb..fb159d4da07db4662a48f297c5646c807ee05084 100755
--- a/ci-scripts/checkCodingFormattingRules.sh
+++ b/ci-scripts/checkCodingFormattingRules.sh
@@ -62,6 +62,30 @@ then
NB_FILES_TO_FORMAT=`astyle --dry-run --options=ci-scripts/astyle-options.txt --recursive *.c *.h | grep -c Formatted `
echo "Nb Files that do NOT follow OAI rules: $NB_FILES_TO_FORMAT"
echo $NB_FILES_TO_FORMAT > ./oai_rules_result.txt
+
+ # Testing Circular Dependencies protection
+ awk '/#[ \t]*ifndef/ { gsub("^.*ifndef *",""); if (names[$1]!="") print "files with same {define ", FILENAME, names[$1]; names[$1]=FILENAME } /#[ \t]*define/ { gsub("^.*define *",""); if(names[$1]!=FILENAME) print "error in declaration", FILENAME, $1, names[$1]; nextfile }' `find openair* common targets executables -name *.h |grep -v LFDS` > header-files-w-incorrect-define.txt
+
+ # Testing if explicit GNU GPL license banner
+ egrep -irl --exclude-dir=.git --include=*.cpp --include=*.c --include=*.h "General Public License" . > files-w-gnu-gpl-license-banner.txt
+
+ # Looking at exotic/suspect banner
+ LIST_OF_FILES_W_BANNER=`egrep -irl --exclude-dir=.git --include=*.cpp --include=*.c --include=*.h "Copyright|copyleft" .`
+ if [ -f ./files-w-suspect-banner.txt ]; then rm -f ./files-w-suspect-banner.txt; fi
+ for FILE in $LIST_OF_FILES_W_BANNER
+ do
+ IS_NFAPI=`echo $FILE | egrep -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext"`
+ IS_OAI_LICENCE_PRESENT=`egrep -c "OAI Public License" $FILE`
+ IS_BSD_LICENCE_PRESENT=`egrep -c "the terms of the BSD Licence" $FILE`
+ IS_EXCEPTION=`echo $FILE | egrep -c "common/utils/collection/tree.h|common/utils/collection/queue.h|common/utils/itti_analyzer/common/queue.h|openair3/UTILS/tree.h|openair3/UTILS/queue.h"`
+ if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ]
+ then
+ if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ]
+ then
+ echo $FILE >> ./files-w-suspect-banner.txt
+ fi
+ fi
+ done
exit 0
fi
@@ -131,8 +155,25 @@ if [ -f oai_rules_result_list.txt ]
then
rm -f oai_rules_result_list.txt
fi
+if [ -f header-files-w-incorrect-define.txt ]
+then
+ rm -f header-files-w-incorrect-define.txt
+fi
+if [ -f files-w-gnu-gpl-license-banner.txt ]
+then
+ rm -f files-w-gnu-gpl-license-banner.txt
+fi
+if [ -f files-w-suspect-banner.txt ]
+then
+ rm -f files-w-suspect-banner.txt
+fi
+awk '/#[ \t]*ifndef/ { gsub("^.*ifndef *",""); if (names[$1]!="") print "files with same {define ", FILENAME, names[$1]; names[$1]=FILENAME } /#[ \t]*define/ { gsub("^.*define *",""); if(names[$1]!=FILENAME) print "error in declaration", FILENAME, $1, names[$1]; nextfile }' `find openair* common targets executables -name *.h |grep -v LFDS` > header-files-w-incorrect-define-tmp.txt
+
for FULLFILE in $MODIFIED_FILES
do
+ # sometimes, we remove files
+ if [ ! -f $FULLFILE ]; then continue; fi
+
filename=$(basename -- "$FULLFILE")
EXT="${filename##*.}"
if [ $EXT = "c" ] || [ $EXT = "h" ] || [ $EXT = "cpp" ] || [ $EXT = "hpp" ]
@@ -144,8 +185,32 @@ do
echo $FULLFILE
echo $FULLFILE >> ./oai_rules_result_list.txt
fi
+ # Testing if explicit GNU GPL license banner
+ egrep -i "General Public License" $FULLFILE >> files-w-gnu-gpl-license-banner.txt
+ # Looking at exotic/suspect banner
+ IS_BANNER=`egrep -i -c "Copyright|copyleft" $FULLFILE`
+ if [ $IS_BANNER -ne 0 ]
+ then
+ IS_NFAPI=`echo $FULLFILE | egrep -c "nfapi/open-nFAPI|nfapi/oai_integration/vendor_ext"`
+ IS_OAI_LICENCE_PRESENT=`egrep -c "OAI Public License" $FULLFILE`
+ IS_BSD_LICENCE_PRESENT=`egrep -c "the terms of the BSD Licence" $FULLFILE`
+ IS_EXCEPTION=`echo $FILE | egrep -c "common/utils/collection/tree.h|common/utils/collection/queue.h|common/utils/itti_analyzer/common/queue.h|openair3/UTILS/tree.h|openair3/UTILS/queue.h"`
+ if [ $IS_OAI_LICENCE_PRESENT -eq 0 ] && [ $IS_BSD_LICENCE_PRESENT -eq 0 ]
+ then
+ if [ $IS_NFAPI -eq 0 ] && [ $IS_EXCEPTION -eq 0 ]
+ then
+ echo $FILE >> ./files-w-suspect-banner.txt
+ fi
+ fi
+ fi
+ fi
+ # Testing Circular Dependencies protection
+ if [ $EXT = "h" ] || [ $EXT = "hpp" ]
+ then
+ grep $FULLFILE header-files-w-incorrect-define-tmp.txt >> header-files-w-incorrect-define.txt
fi
done
+rm -f header-files-w-incorrect-define-tmp.txt
echo ""
echo " ----------------------------------------------------------"
echo "Nb Files that do NOT follow OAI rules: $NB_TO_FORMAT"
diff --git a/ci-scripts/cls_cots_ue.py b/ci-scripts/cls_cots_ue.py
new file mode 100644
index 0000000000000000000000000000000000000000..6954aa392742f1ca77ee64d46e97b468a2614cff
--- /dev/null
+++ b/ci-scripts/cls_cots_ue.py
@@ -0,0 +1,88 @@
+# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+# * contributor license agreements. See the NOTICE file distributed with
+# * this work for additional information regarding copyright ownership.
+# * The OpenAirInterface Software Alliance licenses this file to You under
+# * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+# * except in compliance with the License.
+# * You may obtain a copy of the License at
+# *
+# * http://www.openairinterface.org/?page_id=698
+# *
+# * Unless required by applicable law or agreed to in writing, software
+# * distributed under the License is distributed on an "AS IS" BASIS,
+# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# * See the License for the specific language governing permissions and
+# * limitations under the License.
+# *-------------------------------------------------------------------------------
+# * For more information about the OpenAirInterface (OAI) Software Alliance:
+# * contact@openairinterface.org
+# */
+#---------------------------------------------------------------------
+# Python for CI of OAI-eNB + COTS-UE
+#
+# Required Python Version
+# Python 3.x
+#
+# Required Python Package
+# pexpect
+#---------------------------------------------------------------------
+
+#to use logging.info()
+import logging
+#to create a SSH object locally in the methods
+import sshconnection
+#time.sleep
+import time
+
+class CotsUe:
+ def __init__(self,model,UEIPAddr,UEUserName,UEPassWord):
+ self.model = model
+ self.UEIPAddr = UEIPAddr
+ self.UEUserName = UEUserName
+ self.UEPassWord = UEPassWord
+ self.runargs = '' #on of off to toggle airplane mode on/off
+ self.__SetAirplaneRetry = 3
+
+#-----------------$
+#PUBLIC Methods$
+#-----------------$
+
+ def Check_Airplane(self):
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord)
+ status=mySSH.cde_check_value('sudo adb shell settings get global airplane_mode_on ', ['0','1'],5)
+ mySSH.close()
+ return status
+
+
+ def Set_Airplane(self,target_state_str):
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.UEIPAddr, self.UEUserName, self.UEPassWord)
+ mySSH.command('sudo adb start-server','$',5)
+ logging.info("Toggling COTS UE Airplane mode to : "+target_state_str)
+ current_state = self.Check_Airplane()
+ if target_state_str.lower()=="on":
+ target_state=1
+ else:
+ target_state=0
+ if current_state != target_state:
+ #toggle state
+ retry = 0
+ while (current_state!=target_state) and (retry < self.__SetAirplaneRetry):
+ mySSH.command('sudo adb shell am start -a android.settings.AIRPLANE_MODE_SETTINGS', '\$', 5)
+ mySSH.command('sudo adb shell input keyevent 20', '\$', 5)
+ mySSH.command('sudo adb shell input tap 968 324', '\$', 5)
+ time.sleep(1)
+ current_state = self.Check_Airplane()
+ retry+=1
+ if current_state != target_state:
+ logging.error("ATTENTION : Could not toggle to : "+target_state_str)
+ logging.error("Current state is : "+ str(current_state))
+ else:
+ print("Airplane mode is already "+ target_state_str)
+ mySSH.command('sudo adb kill-server','$',5)
+ mySSH.close()
+
+
+
+
diff --git a/ci-scripts/cls_physim.py b/ci-scripts/cls_physim.py
new file mode 100644
index 0000000000000000000000000000000000000000..4ca36b8cf0f6c485b31cb025349e3a693531d1ca
--- /dev/null
+++ b/ci-scripts/cls_physim.py
@@ -0,0 +1,191 @@
+# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+# * contributor license agreements. See the NOTICE file distributed with
+# * this work for additional information regarding copyright ownership.
+# * The OpenAirInterface Software Alliance licenses this file to You under
+# * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+# * except in compliance with the License.
+# * You may obtain a copy of the License at
+# *
+# * http://www.openairinterface.org/?page_id=698
+# *
+# * Unless required by applicable law or agreed to in writing, software
+# * distributed under the License is distributed on an "AS IS" BASIS,
+# * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# * See the License for the specific language governing permissions and
+# * limitations under the License.
+# *-------------------------------------------------------------------------------
+# * For more information about the OpenAirInterface (OAI) Software Alliance:
+# * contact@openairinterface.org
+# */
+#---------------------------------------------------------------------
+# Python for CI of OAI-eNB + COTS-UE
+#
+# Required Python Version
+# Python 3.x
+#
+# Required Python Package
+# pexpect
+#---------------------------------------------------------------------
+
+#to use logging.info()
+import logging
+#to create a SSH object locally in the methods
+import sshconnection
+#to update the HTML object
+import html
+from multiprocessing import SimpleQueue
+#for log folder maintenance
+import os
+
+class PhySim:
+ def __init__(self):
+ self.buildargs = ""
+ self.runargs = ""
+ self.eNBIpAddr = ""
+ self.eNBUserName = ""
+ self.eNBPassWord = ""
+ self.eNBSourceCodePath = ""
+ self.ranRepository = ""
+ self.ranBranch = ""
+ self.ranCommitID= ""
+ self.ranAllowMerge= ""
+ self.ranTargetBranch= ""
+ self.exitStatus=0
+ self.forced_workspace_cleanup=False
+ #private attributes
+ self.__workSpacePath=''
+ self.__buildLogFile='compile_phy_sim.log'
+ self.__runLogFile=''
+ self.__runResults=[]
+ self.__runLogPath='phy_sim_logs'
+
+
+#-----------------
+#PRIVATE Methods
+#-----------------
+
+ def __CheckResults_PhySim(self,HTML,CONST,testcase_id):
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord)
+ #retrieve run log file and store it locally$
+ mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__runLogFile, '.')
+ mySSH.close()
+ #parse results looking for Encoding and Decoding mean values
+ self.__runResults=[]
+ with open(self.__runLogFile) as f:
+ for line in f:
+ if 'mean' in line:
+ self.__runResults.append(line)
+ #the values are appended for each mean value (2), so we take these 2 values from the list
+ info=self.__runResults[0]+self.__runResults[1]
+
+ #once parsed move the local logfile to its folder for tidiness
+ os.system('mv '+self.__runLogFile+' '+ self.__runLogPath+'/.')
+
+ #updating the HTML with results
+ html_cell = '<pre style="background-color:white">' + info + '</pre>'
+ html_queue=SimpleQueue()
+ html_queue.put(html_cell)
+ HTML.CreateHtmlTestRowQueue(self.runargs, 'OK', 1, html_queue)
+ return HTML
+
+
+ def __CheckBuild_PhySim(self, HTML, CONST):
+ self.__workSpacePath=self.eNBSourceCodePath+'/cmake_targets/'
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord)
+ #retrieve compile log file and store it locally
+ mySSH.copyin(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord, self.__workSpacePath+self.__buildLogFile, '.')
+ #delete older run log file
+ mySSH.command('rm ' + self.__workSpacePath+self.__runLogFile, '\$', 5)
+ mySSH.close()
+ #check build result from local compile log file
+ buildStatus=False
+ with open(self.__buildLogFile) as f:
+ #nr_prachsim is the last compile step
+ if 'nr_prachsim compiled' in f.read():
+ buildStatus=True
+ #update HTML based on build status
+ if buildStatus:
+ HTML.CreateHtmlTestRow(self.buildargs, 'OK', CONST.ALL_PROCESSES_OK, 'LDPC')
+ self.exitStatus=0
+ else:
+ logging.error('\u001B[1m Building Physical Simulators Failed\u001B[0m')
+ HTML.CreateHtmlTestRow(self.buildargs, 'KO', CONST.ALL_PROCESSES_OK, 'LDPC')
+ HTML.CreateHtmlTabFooter(False)
+ #exitStatus=1 will do a sys.exit in main
+ self.exitStatus=1
+ return HTML
+
+
+#-----------------$
+#PUBLIC Methods$
+#-----------------$
+
+ def Build_PhySim(self,htmlObj,constObj):
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord)
+
+ #create working dir
+ mySSH.command('mkdir -p ' + self.eNBSourceCodePath, '\$', 5)
+ mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5)
+
+ if not self.ranRepository.lower().endswith('.git'):
+ self.ranRepository+='.git'
+
+ #git clone
+ mySSH.command('if [ ! -e .git ]; then stdbuf -o0 git clone ' + self.ranRepository + ' .; else stdbuf -o0 git fetch --prune; fi', '\$', 600)
+ #git config
+ mySSH.command('git config user.email "jenkins@openairinterface.org"', '\$', 5)
+ mySSH.command('git config user.name "OAI Jenkins"', '\$', 5)
+
+ #git clean depending on self.forced_workspace_cleanup captured in xml
+ if self.forced_workspace_cleanup==True:
+ logging.info('Cleaning workspace ...')
+ mySSH.command('echo ' + self.eNBPassWord + ' | sudo -S git clean -x -d -ff', '\$', 30)
+ else:
+ logging.info('Workspace cleaning was disabled')
+
+ # if the commit ID is provided, use it to point to it
+ if self.ranCommitID != '':
+ mySSH.command('git checkout -f ' + self.ranCommitID, '\$', 5)
+ # if the branch is not develop, then it is a merge request and we need to do
+ # the potential merge. Note that merge conflicts should have already been checked earlier
+ if (self.ranAllowMerge):
+ if self.ranTargetBranch == '':
+ if (self.ranBranch != 'develop') and (self.ranBranch != 'origin/develop'):
+ mySSH.command('git merge --ff origin/develop -m "Temporary merge for CI"', '\$', 5)
+ else:
+ logging.info('Merging with the target branch: ' + self.ranTargetBranch)
+ mySSH.command('git merge --ff origin/' + self.ranTargetBranch + ' -m "Temporary merge for CI"', '\$', 5)
+
+ #build
+ mySSH.command('source oaienv', '\$', 5)
+ mySSH.command('cd cmake_targets', '\$', 5)
+ mySSH.command('mkdir -p log', '\$', 5)
+ mySSH.command('chmod 777 log', '\$', 5)
+ mySSH.command('stdbuf -o0 ./build_oai ' + self.buildargs + ' 2>&1 | stdbuf -o0 tee ' + self.__buildLogFile, 'Bypassing the Tests|build have failed', 1500)
+
+ mySSH.close()
+ #check build status and update HTML object
+ lHTML = html.HTMLManagement()
+ lHTML=self.__CheckBuild_PhySim(htmlObj,constObj)
+ return lHTML
+
+
+ def Run_PhySim(self,htmlObj,constObj,testcase_id):
+ #create run logs folder locally
+ os.system('mkdir -p ./'+self.__runLogPath)
+ #log file is tc_<testcase_id>.log remotely
+ self.__runLogFile='physim_'+str(testcase_id)+'.log'
+ #open a session for test run
+ mySSH = sshconnection.SSHConnection()
+ mySSH.open(self.eNBIpAddr, self.eNBUserName, self.eNBPassWord)
+ mySSH.command('cd '+self.__workSpacePath,'\$',5)
+ #run and redirect the results to a log file
+ mySSH.command(self.__workSpacePath+'phy_simulators/build/ldpctest ' + self.runargs + ' >> '+self.__runLogFile, '\$', 30)
+ mySSH.close()
+ #return updated HTML to main
+ lHTML = html.HTMLManagement()
+ lHTML=self.__CheckResults_PhySim(htmlObj,constObj,testcase_id)
+ return lHTML
diff --git a/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf
index db1c5eae2a1e81ddef717b5c997069b32b68f7f3..d834b23e30a1eb8daeee95b114a1e7e7be0865e0 100644
--- a/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf
+++ b/ci-scripts/conf_files/enb.band17.tm1.25PRB.usrpb210.conf
@@ -105,6 +105,7 @@ eNBs =
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
+ mbms_dedicated_serving_cell = "DISABLE"
//Parameters for SIB18
rxPool_sc_CP_Len = "normal";
diff --git a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf
index de58950df4eed9883c9d63229d92620fbebb618c..a9ccb9f78398951fcd6c78a5bd6965d506600174 100644
--- a/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf
+++ b/ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf
@@ -105,6 +105,8 @@ eNBs =
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
+ mbms_dedicated_serving_cell = "DISABLE"
+
//Parameters for SIB18
rxPool_sc_CP_Len = "normal";
@@ -247,7 +249,6 @@ MCEs = (
);
-
NETWORK_INTERFACES :
{
MCE_INTERFACE_NAME_FOR_M2_ENB = "lo";
@@ -271,12 +272,12 @@ MCEs = (
mcch_update_time = 10;
mbms_area_config_list = (
{
- common_sf_allocation_period = 2; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6)
+ common_sf_allocation_period = 1; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6)
mbms_area_id = 0;
pmch_config_list = (
{
- allocated_sf_end=64;
- data_mcs=10;
+ allocated_sf_end=40;
+ data_mcs=20;
mch_scheduling_period = 0; #rf8(0)
mbms_session_list = (
{
@@ -288,7 +289,7 @@ MCEs = (
mnc_length = 2;
}
service_id=0;
- lcid=5; #this must be properly defined lcid:8+service:0 -> rab_id:5
+ lcid=5; #this must be properly defined lcid:8+service:0 -> rab_id:5 //with new RLC set lcid either 4 or 5
}
);
}
@@ -296,10 +297,10 @@ MCEs = (
mbms_sf_config_list = (
{
- radioframe_allocation_period=1; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5)
+ radioframe_allocation_period=0; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5)
radioframe_alloocation_offset=0;
num_frame="oneFrame";
- subframe_allocation=57; #xx100000
+ subframe_allocation=59; #xx111011 #57; #xx111001
//num_frame="fourFrame";
//subframe_allocation=14548987; #
}
diff --git a/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf
new file mode 100755
index 0000000000000000000000000000000000000000..5b2c90a714d773e456215098095edfd569a428fd
--- /dev/null
+++ b/ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf
@@ -0,0 +1,284 @@
+Active_eNBs = ( "eNB-Eurecom-LTEBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+eNBs =
+(
+ {
+ # real_time choice in {hard, rt-preempt, no}
+ real_time = "no";
+ ////////// Identification parameters:
+ eNB_ID = 0xe01;
+ cell_type = "CELL_MACRO_ENB";
+ eNB_name = "eNB-Eurecom-LTEBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+ plmn_list = (
+ { mcc = 222; mnc = 01; mnc_length = 2; }
+ );
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ component_carriers = (
+ {
+ node_function = "eNodeB_3GPP";
+ node_timing = "synch_to_ext_device";
+ node_synch_ref = 0;
+ nb_antenna_ports = 1;
+ ue_TransmissionMode = 1;
+ frame_type = "FDD";
+ tdd_config = 3;
+ tdd_config_s = 0;
+ prefix_type = "NORMAL";
+ eutra_band = 7;
+ downlink_frequency = 2680000000L;
+ uplink_frequency_offset = -120000000;
+
+ Nid_cell = 0;
+ N_RB_DL = 25;
+ Nid_cell_mbsfn = 0;
+ nb_antennas_tx = 1;
+ nb_antennas_rx = 1;
+ prach_root = 0;
+ tx_gain = 90;
+ rx_gain = 115;
+ pbch_repetition = "FALSE";
+
+ prach_config_index = 0;
+ prach_high_speed = "DISABLE";
+ prach_zero_correlation = 1;
+ prach_freq_offset = 2;
+
+ pucch_delta_shift = 1;
+ pucch_nRB_CQI = 0;
+ pucch_nCS_AN = 0;
+ pucch_n1_AN = 0;
+ pdsch_referenceSignalPower = -29;
+ pdsch_p_b = 0;
+ pusch_n_SB = 1;
+ pusch_enable64QAM = "DISABLE";
+ pusch_hoppingMode = "interSubFrame";
+ pusch_hoppingOffset = 0;
+ pusch_groupHoppingEnabled = "ENABLE";
+ pusch_groupAssignment = 0;
+ pusch_sequenceHoppingEnabled = "DISABLE";
+ pusch_nDMRS1 = 1;
+ phich_duration = "NORMAL";
+ phich_resource = "ONESIXTH";
+ srs_enable = "DISABLE";
+/*
+ srs_BandwidthConfig =;
+ srs_SubframeConfig =;
+ srs_ackNackST =;
+ srs_MaxUpPts =;
+*/
+
+ pusch_p0_Nominal = -96;
+ pusch_alpha = "AL1";
+ pucch_p0_Nominal = -96;
+ msg3_delta_Preamble = 6;
+ pucch_deltaF_Format1 = "deltaF2";
+ pucch_deltaF_Format1b = "deltaF3";
+ pucch_deltaF_Format2 = "deltaF0";
+ pucch_deltaF_Format2a = "deltaF0";
+ pucch_deltaF_Format2b = "deltaF0";
+
+ rach_numberOfRA_Preambles = 64;
+ rach_preamblesGroupAConfig = "DISABLE";
+/*
+ rach_sizeOfRA_PreamblesGroupA = ;
+ rach_messageSizeGroupA = ;
+ rach_messagePowerOffsetGroupB = ;
+*/
+ rach_powerRampingStep = 4;
+ rach_preambleInitialReceivedTargetPower = -108;
+ rach_preambleTransMax = 10;
+ rach_raResponseWindowSize = 10;
+ rach_macContentionResolutionTimer = 48;
+ rach_maxHARQ_Msg3Tx = 4;
+
+ pcch_default_PagingCycle = 128;
+ pcch_nB = "oneT";
+ bcch_modificationPeriodCoeff = 2;
+ ue_TimersAndConstants_t300 = 1000;
+ ue_TimersAndConstants_t301 = 1000;
+ ue_TimersAndConstants_t310 = 1000;
+ ue_TimersAndConstants_t311 = 10000;
+ ue_TimersAndConstants_n310 = 20;
+ ue_TimersAndConstants_n311 = 1;
+
+ //Parameters for SIB18
+ rxPool_sc_CP_Len = "normal";
+ rxPool_sc_Period = "sf40";
+ rxPool_data_CP_Len = "normal";
+ rxPool_ResourceConfig_prb_Num = 20;
+ rxPool_ResourceConfig_prb_Start = 5;
+ rxPool_ResourceConfig_prb_End = 44;
+ rxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ rxPool_ResourceConfig_offsetIndicator_choice = 0;
+ rxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+/*
+ rxPool_dataHoppingConfig_hoppingParameter = 0;
+ rxPool_dataHoppingConfig_numSubbands = "ns1";
+ rxPool_dataHoppingConfig_rbOffset = 0;
+ rxPool_commTxResourceUC-ReqAllowed = "TRUE";
+*/
+ // Parameters for SIB19
+ discRxPool_cp_Len = "normal"
+ discRxPool_discPeriod = "rf32"
+ discRxPool_numRetx = 1;
+ discRxPool_numRepetition = 2;
+ discRxPool_ResourceConfig_prb_Num = 5;
+ discRxPool_ResourceConfig_prb_Start = 3;
+ discRxPool_ResourceConfig_prb_End = 21;
+ discRxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ discRxPool_ResourceConfig_offsetIndicator_choice = 0;
+ discRxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+
+ }
+ );
+
+ srb1_parameters :
+ {
+ # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
+ timer_poll_retransmit = 80;
+
+ # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
+ timer_reordering = 35;
+
+ # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
+ timer_status_prohibit = 0;
+
+ # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
+ poll_pdu = 4;
+
+ # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
+ poll_byte = 99999;
+
+ # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
+ max_retx_threshold = 4;
+ }
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+ enable_measurement_reports = "yes";
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+
+ NETWORK_INTERFACES :
+ {
+ ENB_INTERFACE_NAME_FOR_S1_MME = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR";
+
+ ENB_INTERFACE_NAME_FOR_S1U = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR";
+ ENB_PORT_FOR_S1U = 2152; # Spec 2152
+
+ ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR";
+ ENB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="debug";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ phy_test_mode = 0;
+ puSch10xSnr = 160;
+ puCch10xSnr = 160;
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
+ worker_config = "ENABLE";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 118;
+ eNB_instances = [0];
+ clock_src = "external";
+ }
+);
+
+log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
diff --git a/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf
new file mode 100755
index 0000000000000000000000000000000000000000..92af74c300248c020bc8ebedca4b5fc9e62c1f5e
--- /dev/null
+++ b/ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf
@@ -0,0 +1,291 @@
+Active_gNBs = ( "gNB-Eurecom-5GNRBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+gNBs =
+(
+ {
+ ////////// Identification parameters:
+ gNB_ID = 0xe00;
+
+ cell_type = "CELL_MACRO_GNB";
+ gNB_name = "gNB-Eurecom-5GNRBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+ plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;});
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ ssb_SubcarrierOffset = 31; //0;
+ pdsch_AntennaPorts = 1;
+
+ servingCellConfigCommon = (
+ {
+ #spCellConfigCommon
+
+ physCellId = 0;
+
+# downlinkConfigCommon
+ #frequencyInfoDL
+ # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP)
+ absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell
+ dl_frequencyBand = 78;
+ # this is 3600 MHz
+ dl_absoluteFrequencyPointA = 640000;
+ #scs-SpecificCarrierList
+ dl_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ dl_subcarrierSpacing = 1;
+ dl_carrierBandwidth = 106;
+ #initialDownlinkBWP
+ #genericParameters
+ # this is RBstart=84,L=13 (275*(L-1))+RBstart
+ initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialDLBWPsubcarrierSpacing = 1;
+ #pdcch-ConfigCommon
+ initialDLBWPcontrolResourceSetZero = 0;
+ initialDLBWPsearchSpaceZero = 0;
+ #pdsch-ConfigCommon
+ #pdschTimeDomainAllocationList (up to 16 entries)
+ initialDLBWPk0_0 = 0;
+ #initialULBWPmappingType
+ #0=typeA,1=typeB
+ initialDLBWPmappingType_0 = 0;
+ #this is SS=1,L=13
+ initialDLBWPstartSymbolAndLength_0 = 40;
+
+ initialDLBWPk0_1 = 0;
+ initialDLBWPmappingType_1 = 0;
+ #this is SS=2,L=12
+ initialDLBWPstartSymbolAndLength_1 = 53;
+
+ initialDLBWPk0_2 = 0;
+ initialDLBWPmappingType_2 = 0;
+ #this is SS=1,L=12
+ initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
+ initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
+ #uplinkConfigCommon
+ #frequencyInfoUL
+ ul_frequencyBand = 78;
+ #scs-SpecificCarrierList
+ ul_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ ul_subcarrierSpacing = 1;
+ ul_carrierBandwidth = 106;
+ pMax = 20;
+ #initialUplinkBWP
+ #genericParameters
+ initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialULBWPsubcarrierSpacing = 1;
+ #rach-ConfigCommon
+ #rach-ConfigGeneric
+ prach_ConfigurationIndex = 98;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+ prach_msg1_FDM = 0;
+ prach_msg1_FrequencyStart = 0;
+ zeroCorrelationZoneConfig = 13;
+ preambleReceivedTargetPower = -100;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+ preambleTransMax = 6;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+ powerRampingStep = 1;
+#ra_ReponseWindow
+#1,2,4,8,10,20,40,80
+ ra_ResponseWindow = 5;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
+#oneHalf (0..15) 4,8,12,16,...60,64
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+ ra_ContentionResolutionTimer = 7;
+ rsrp_ThresholdSSB = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
+ prach_RootSequenceIndex = 1;
+ # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+ #
+ msg1_SubcarrierSpacing = 1,
+
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+ restrictedSetConfig = 0,
+ # pusch-ConfigCommon (up to 16 elements)
+ initialULBWPk2_0 = 2;
+ initialULBWPmappingType_0 = 1
+ # this is SS=0 L=11
+ initialULBWPstartSymbolAndLength_0 = 55;
+
+ initialULBWPk2_1 = 2;
+ initialULBWPmappingType_1 = 1;
+ # this is SS=0 L=12
+ initialULBWPstartSymbolAndLength_1 = 69;
+
+ initialULBWPk2_2 = 7;
+ initialULBWPmappingType_2 = 1;
+ # this is SS=10 L=4
+ initialULBWPstartSymbolAndLength_2 = 52;
+
+ msg3_DeltaPreamble = 1;
+ p0_NominalWithGrant =-90;
+
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+ pucchGroupHopping = 0;
+ hoppingId = 40;
+ p0_nominal = -90;
+# ssb_PositionsInBurs_BitmapPR
+# 1=short, 2=medium, 3=long
+ ssb_PositionsInBurst_PR = 2;
+ ssb_PositionsInBurst_Bitmap = 1; #0x80;
+
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+ ssb_periodicityServingCell = 2;
+
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+ dmrs_TypeA_Position = 0;
+
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ subcarrierSpacing = 1;
+
+
+ #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ referenceSubcarrierSpacing = 1;
+ # pattern1
+ # dl_UL_TransmissionPeriodicity
+ # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+ dl_UL_TransmissionPeriodicity = 6;
+ nrofDownlinkSlots = 7; //8; //7;
+ nrofDownlinkSymbols = 6; //0; //6;
+ nrofUplinkSlots = 2;
+ nrofUplinkSymbols = 4; //0; //4;
+
+ ssPBCH_BlockPower = -25;
+ }
+
+ );
+
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+ target_enb_x2_ip_address = (
+ { ipv4 = "CI_FR1_CTL_ENB_IP_ADDR";
+ ipv6 = "192:168:30::17";
+ preference = "ipv4";
+ }
+ );
+
+ NETWORK_INTERFACES :
+ {
+
+ GNB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1_MME = "CI_GNB_IP_ADDR";
+ GNB_INTERFACE_NAME_FOR_S1U = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1U = "CI_GNB_IP_ADDR";
+ GNB_PORT_FOR_S1U = 2152; # Spec 2152
+ GNB_IPV4_ADDRESS_FOR_X2C = "CI_GNB_IP_ADDR";
+ GNB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 114;
+ eNB_instances = [0];
+ clock_src = "external";
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
+ parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
+ //parallel_config = "PARALLEL_SINGLE_THREAD";
+ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
+ worker_config = "WORKER_ENABLE";
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="medium";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="medium";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="medium";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
diff --git a/ci-scripts/conf_files/lte-fdd-fembms-basic-sim.conf b/ci-scripts/conf_files/lte-fdd-fembms-basic-sim.conf
new file mode 100644
index 0000000000000000000000000000000000000000..e3adedbf4a86a6fef55814ec838c8967c94c7472
--- /dev/null
+++ b/ci-scripts/conf_files/lte-fdd-fembms-basic-sim.conf
@@ -0,0 +1,426 @@
+Active_eNBs = ( "eNB-Eurecom-LTEBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+eNBs =
+(
+ {
+ ////////// Identification parameters:
+ eNB_ID = 0xe00;
+
+ cell_type = "CELL_MACRO_ENB";
+
+ eNB_name = "eNB-Eurecom-LTEBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+ plmn_list = ( { mcc = 208; mnc = 93; mnc_length = 2; } );
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ component_carriers = (
+ {
+ node_function = "3GPP_eNODEB";
+ node_timing = "synch_to_ext_device";
+ node_synch_ref = 0;
+ frame_type = "FDD";
+ tdd_config = 3;
+ tdd_config_s = 0;
+ prefix_type = "NORMAL";
+ eutra_band = 7;
+ downlink_frequency = 2680000000L;
+ uplink_frequency_offset = -120000000;
+ Nid_cell = 0;
+ N_RB_DL = 25;
+ Nid_cell_mbsfn = 0;
+ nb_antenna_ports = 1;
+ nb_antennas_tx = 1;
+ nb_antennas_rx = 1;
+ tx_gain = 90;
+ rx_gain = 125;
+ pbch_repetition = "FALSE";
+ prach_root = 0;
+ prach_config_index = 0;
+ prach_high_speed = "DISABLE";
+ prach_zero_correlation = 1;
+ prach_freq_offset = 2;
+ pucch_delta_shift = 1;
+ pucch_nRB_CQI = 0;
+ pucch_nCS_AN = 0;
+ pucch_n1_AN = 0;
+ pdsch_referenceSignalPower = -27;
+ pdsch_p_b = 0;
+ pusch_n_SB = 1;
+ pusch_enable64QAM = "DISABLE";
+ pusch_hoppingMode = "interSubFrame";
+ pusch_hoppingOffset = 0;
+ pusch_groupHoppingEnabled = "ENABLE";
+ pusch_groupAssignment = 0;
+ pusch_sequenceHoppingEnabled = "DISABLE";
+ pusch_nDMRS1 = 1;
+ phich_duration = "NORMAL";
+ phich_resource = "ONESIXTH";
+ srs_enable = "DISABLE";
+ /* srs_BandwidthConfig =;
+ srs_SubframeConfig =;
+ srs_ackNackST =;
+ srs_MaxUpPts =;*/
+
+ pusch_p0_Nominal = -96;
+ pusch_alpha = "AL1";
+ pucch_p0_Nominal = -104;
+ msg3_delta_Preamble = 6;
+ pucch_deltaF_Format1 = "deltaF2";
+ pucch_deltaF_Format1b = "deltaF3";
+ pucch_deltaF_Format2 = "deltaF0";
+ pucch_deltaF_Format2a = "deltaF0";
+ pucch_deltaF_Format2b = "deltaF0";
+
+ rach_numberOfRA_Preambles = 64;
+ rach_preamblesGroupAConfig = "DISABLE";
+ /*
+ rach_sizeOfRA_PreamblesGroupA = ;
+ rach_messageSizeGroupA = ;
+ rach_messagePowerOffsetGroupB = ;
+ */
+ rach_powerRampingStep = 4;
+ rach_preambleInitialReceivedTargetPower = -108;
+ rach_preambleTransMax = 10;
+ rach_raResponseWindowSize = 10;
+ rach_macContentionResolutionTimer = 48;
+ rach_maxHARQ_Msg3Tx = 4;
+
+ pcch_default_PagingCycle = 128;
+ pcch_nB = "oneT";
+ bcch_modificationPeriodCoeff = 2;
+ ue_TimersAndConstants_t300 = 1000;
+ ue_TimersAndConstants_t301 = 1000;
+ ue_TimersAndConstants_t310 = 1000;
+ ue_TimersAndConstants_t311 = 10000;
+ ue_TimersAndConstants_n310 = 20;
+ ue_TimersAndConstants_n311 = 1;
+ ue_TransmissionMode = 1;
+ mbms_dedicated_serving_cell = "ENABLE"
+
+ //Parameters for SIB18
+ rxPool_sc_CP_Len = "normal";
+ rxPool_sc_Period = "sf40";
+ rxPool_data_CP_Len = "normal";
+ rxPool_ResourceConfig_prb_Num = 20;
+ rxPool_ResourceConfig_prb_Start = 5;
+ rxPool_ResourceConfig_prb_End = 44;
+ rxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ rxPool_ResourceConfig_offsetIndicator_choice = 0;
+ rxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+/* rxPool_dataHoppingConfig_hoppingParameter = 0;
+ rxPool_dataHoppingConfig_numSubbands = "ns1";
+ rxPool_dataHoppingConfig_rbOffset = 0;
+ rxPool_commTxResourceUC-ReqAllowed = "TRUE";
+*/
+ // Parameters for SIB19
+ discRxPool_cp_Len = "normal"
+ discRxPool_discPeriod = "rf32"
+ discRxPool_numRetx = 1;
+ discRxPool_numRepetition = 2;
+ discRxPool_ResourceConfig_prb_Num = 5;
+ discRxPool_ResourceConfig_prb_Start = 3;
+ discRxPool_ResourceConfig_prb_End = 21;
+ discRxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ discRxPool_ResourceConfig_offsetIndicator_choice = 0;
+ discRxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+
+ }
+ );
+
+
+ srb1_parameters :
+ {
+ # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
+ timer_poll_retransmit = 80;
+
+ # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
+ timer_reordering = 35;
+
+ # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
+ timer_status_prohibit = 0;
+
+ # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
+ poll_pdu = 4;
+
+ # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
+ poll_byte = 99999;
+
+ # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
+ max_retx_threshold = 4;
+ }
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "CI_MME_IP_ADDR";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ enable_measurement_reports = "no";
+
+ ///X2
+ enable_x2 = "no";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+
+ ////////// MCE parameters:
+ target_mce_m2_ip_address = ( { ipv4 = "127.0.0.7";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///M2
+ enable_enb_m2 = "yes";
+
+
+ mbms_configuration_data_list = (
+ {
+ mbsfn_sync_area = 0x0001;
+ mbms_service_area_list=(
+ {
+ mbms_service_area=0x0001;
+ }
+ );
+ }
+
+ );
+
+
+
+ NETWORK_INTERFACES :
+ {
+
+ ENB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ ENB_IPV4_ADDRESS_FOR_S1_MME = "CI_ENB_IP_ADDR";
+ ENB_INTERFACE_NAME_FOR_S1U = "eth0";
+ ENB_IPV4_ADDRESS_FOR_S1U = "CI_ENB_IP_ADDR";
+ ENB_PORT_FOR_S1U = 2152; # Spec 2152
+ ENB_IPV4_ADDRESS_FOR_X2C = "CI_ENB_IP_ADDR";
+ ENB_PORT_FOR_X2C = 36422; # Spec 36422
+
+ ENB_IPV4_ADDRESS_FOR_M2C = "127.0.0.2/24";
+ ENB_PORT_FOR_M2C = 36443; # Spec 36443
+ };
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ phy_test_mode = 0;
+ puSch10xSnr = 200;
+ puCch10xSnr = 200;
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+MCEs = (
+ {
+ MCE_ID = 0xe00;
+
+ MCE_name = "MCE-Vicomtech-LTEBox";
+
+ //M2
+ enable_mce_m2 = "yes";
+
+ //M3
+ enable_mce_m3 = "yes";
+
+ target_mme_m3_ip_address = ( { ipv4 = "127.0.0.18";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+
+
+ NETWORK_INTERFACES :
+ {
+ MCE_INTERFACE_NAME_FOR_M2_ENB = "lo";
+ MCE_IPV4_ADDRESS_FOR_M2C = "127.0.0.7/24";
+ MCE_PORT_FOR_M2C = 36443; # Spec 36443
+
+ MCE_INTERFACE_NAME_FOR_M3_MME = "lo";
+ MCE_IPV4_ADDRESS_FOR_M3C = "127.0.0.3/24";
+ MCE_PORT_FOR_M3C = 36444; # Spec 36444
+ };
+
+ plnm:
+ {
+ mcc = 208;
+ mnc = 93;
+ mnc_length = 2;
+ };
+
+ mbms_sched_info :
+ {
+ mcch_update_time = 10;
+ mbms_area_config_list = (
+ {
+ common_sf_allocation_period = 1; #rf4(0) rf8(1) rf16(2) rf32(3) rf64(4) rf128(5) rf256(6)
+ mbms_area_id = 0;
+ pmch_config_list = (
+ {
+ allocated_sf_end=512;
+ data_mcs=15;
+ mch_scheduling_period = 0; #rf8(0) rf16(1) rf32(2) rf64(3) rf128(4) rf256(5) rf512(6) rf1024(7)
+ mbms_session_list = (
+ {
+ #plnm + service_id ->tmgi
+ plnm:
+ {
+ mcc = 208;
+ mnc = 93;
+ mnc_length = 2;
+ }
+ service_id=0; #keep this allways as 0 (workaround for TUN if)
+ lcid=5; #this must be properly defined lcid:6+service:0 -> rab_id:5 //with new RLC set lcid either 4 or 5
+ }
+ );
+ }
+ );
+
+ mbms_sf_config_list = (
+ {
+ radioframe_allocation_period=0; #n1(0) n2(1) n4(2) n8(3) n16(4) n32(5)
+ radioframe_alloocation_offset=0;
+ num_frame="oneFrame";
+ subframe_allocation=57; #xx111001
+ //num_frame="fourFrame";
+ //subframe_allocation=14548987; #
+ }
+ );
+
+ }
+ );
+ };
+
+
+ mcch_config_per_mbsfn_area = (
+ {
+ mbsfn_area = 0;
+ pdcch_length = 1; #s1(0), s2(1)
+ repetition_period = 0; #rf32(0), rf64(1), rf128(2), rf256(3)
+ offset = 0;
+ modification_period = 0; #rf512(0; rf1024(1)
+ subframe_allocation_info = 32; #BITSTRING (6bits -> one frame) xx100000
+ mcs = 0; #n2(0), n7(1), n13(2), n19(3)
+ }
+ );
+
+ #); #end mbms_scheduling_info
+
+ }
+);
+
+MMEs = (
+ {
+ MME_ID = 0xe00;
+
+ MME_name = "MME-MBMS-Vicomtech-LTEBox";
+
+ //M3
+ enable_mme_m3 = "yes";
+ NETWORK_INTERFACES :
+ {
+ MME_INTERFACE_NAME_FOR_M3_MCE = "lo";
+ MME_IPV4_ADDRESS_FOR_M3C = "127.0.0.18/24";
+ MME_PORT_FOR_M3C = 36444; # Spec 36444
+
+ };
+ }
+);
+
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 125;
+ eNB_instances = [0];
+
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
+ parallel_config = "PARALLEL_SINGLE_THREAD";
+ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
+ worker_config = "WORKER_ENABLE";
+ }
+);
+
+NETWORK_CONTROLLER :
+{
+ FLEXRAN_ENABLED = "no";
+ FLEXRAN_INTERFACE_NAME = "ens3";
+ FLEXRAN_IPV4_ADDRESS = "CI_FLEXRAN_CTL_IP_ADDR";
+ FLEXRAN_PORT = 2210;
+ FLEXRAN_CACHE = "/mnt/oai_agent_cache";
+ FLEXRAN_AWAIT_RECONF = "no";
+};
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="medium";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="medium";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="medium";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
+//rfsimulator :
+//{
+ //options = ("chanmod");
+ //modelname = "AWGN";
+//};
+
diff --git a/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf b/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf
index 53261ec32de1b7b5bed2316fd7bdc08445257f4e..3d5a859156310b023c611a26e04a76de2a349ad8 100644
--- a/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf
+++ b/ci-scripts/conf_files/lte-fdd-mbms-basic-sim.conf
@@ -102,6 +102,7 @@ eNBs =
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
+ mbms_dedicated_serving_cell = "DISABLE"
//Parameters for SIB18
rxPool_sc_CP_Len = "normal";
@@ -295,8 +296,8 @@ MCEs = (
pmch_config_list = (
{
allocated_sf_end=32;
- data_mcs=14;
- mch_scheduling_period = 0; #rf8(0)
+ data_mcs=15;
+ mch_scheduling_period = 0; #rf8(0) rf16(1) rf32(2) rf64(3) rf128(4) rf256(5) rf512(6) rf1024(7)
mbms_session_list = (
{
#plnm + service_id ->tmgi
@@ -337,7 +338,7 @@ MCEs = (
offset = 0;
modification_period = 0; #rf512(0; rf1024(1)
subframe_allocation_info = 32; #BITSTRING (6bits -> one frame) xx100000
- mcs = 1; #n2(0), n7(1), n13(2), n19(3)
+ mcs = 0; #n2(0), n7(1), n13(2), n19(3)
}
);
@@ -416,3 +417,10 @@ NETWORK_CONTROLLER :
rrc_log_level ="info";
rrc_log_verbosity ="medium";
};
+
+//rfsimulator :
+//{
+ //options = ("chanmod");
+ //modelname = "AWGN";
+//};
+
diff --git a/ci-scripts/constants.py b/ci-scripts/constants.py
index 1e7e84fb32af9a694992f8b54f3f9bbb43278c66..c5698c5a3ef38dee1ad100933b3a63bbef1b7478 100644
--- a/ci-scripts/constants.py
+++ b/ci-scripts/constants.py
@@ -57,6 +57,7 @@ OAI_UE_PROCESS_ASSERTION = -22
OAI_UE_PROCESS_FAILED = -23
OAI_UE_PROCESS_NO_TUNNEL_INTERFACE = -24
OAI_UE_PROCESS_SEG_FAULT = -25
+OAI_UE_PROCESS_NO_MBMS_MSGS = -26
OAI_UE_PROCESS_OK = +6
UE_STATUS_DETACHED = 0
diff --git a/ci-scripts/cppcheck_suppressions.list b/ci-scripts/cppcheck_suppressions.list
index cad2aab88b4374811490153c509e941b2a2e4e57..727fd22e745ceb031a0c65938827efc49cab13dc 100644
--- a/ci-scripts/cppcheck_suppressions.list
+++ b/ci-scripts/cppcheck_suppressions.list
@@ -37,6 +37,7 @@ memleak:openair2/UTIL/OMG/omg_hashtable.c
// _emm_as_encode function creates the encoded buffer
//
memleak:openair3/NAS/UE/EMM/SAP/emm_as.c
+memleak:openair1/PHY/INIT/nr_init_ue.c
//-----------------------------------------------------------------------------
//*****************************************************************************
// section for files not used in oai exec's included in CI.
diff --git a/ci-scripts/doc/vm_based_simulator_env.md b/ci-scripts/doc/vm_based_simulator_env.md
index 5dbcfbd93118db7f224691741cbd96592936dbd6..95b9d920d592e66c4a6b8f17b74e0b2b206029e6 100644
--- a/ci-scripts/doc/vm_based_simulator_env.md
+++ b/ci-scripts/doc/vm_based_simulator_env.md
@@ -38,7 +38,6 @@ Last point, this documentation is valid for all CI-supported branches:
* `master`
* `develop`
-* `develop-nr`
But the feature set may not be aligned. **The principles still apply.**
diff --git a/ci-scripts/epc.py b/ci-scripts/epc.py
index 4926f2d6e880a4dd82cee104afcdc0e107ad2527..25bbbba091b3ad6b65ed8e5b0a976e883de06a4b 100644
--- a/ci-scripts/epc.py
+++ b/ci-scripts/epc.py
@@ -62,33 +62,10 @@ class EPCManagement():
self.Type = ''
self.PcapFileName = ''
self.htmlObj = None
+ self.testCase_id = ''
+ self.MmeIPAddress = ''
+ self.containerPrefix = 'prod'
-#-----------------------------------------------------------
-# Setter and Getters on Public Members
-#-----------------------------------------------------------
-
- def SetIPAddress(self, ipaddress):
- self.IPAddress = ipaddress
- def GetIPAddress(self):
- return self.IPAddress
- def SetUserName(self, username):
- self.UserName = username
- def GetUserName(self):
- return self.UserName
- def SetPassword(self, password):
- self.Password = password
- def GetPassword(self):
- return self.Password
- def SetSourceCodePath(self, sourcecodepath):
- self.SourceCodePath = sourcecodepath
- def GetSourceCodePath(self):
- return self.SourceCodePath
- def SetType(self, kind):
- self.Type = kind
- def GetType(self):
- return self.Type
- def SetHtmlObj(self, obj):
- self.htmlObj = obj
#-----------------------------------------------------------
# EPC management functions
@@ -101,7 +78,14 @@ class EPCManagement():
sys.exit('Insufficient EPC Parameters')
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ logging.debug('Using the OAI EPC Release 14 Cassandra-based HSS in Docker')
+ mySSH.command('if [ -d ' + self.SourceCodePath + '/scripts ]; then echo ' + self.Password + ' | sudo -S rm -Rf ' + self.SourceCodePath + '/scripts ; fi', '\$', 5)
+ mySSH.command('mkdir -p ' + self.SourceCodePath + '/scripts', '\$', 5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-hss /bin/bash -c "nohup tshark -i eth0 -i eth1 -w /tmp/hss_check_run.pcap 2>&1 > /dev/null"', '\$', 5)
+ time.sleep(5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-hss /bin/bash -c "nohup ./bin/oai_hss -j ./etc/hss_rel14.json --reloadkey true > hss_check_run.log 2>&1"', '\$', 5)
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
logging.debug('Using the OAI EPC Release 14 Cassandra-based HSS')
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
logging.debug('\u001B[1m Launching tshark on all interfaces \u001B[0m')
@@ -139,7 +123,12 @@ class EPCManagement():
sys.exit('Insufficient EPC Parameters')
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ logging.debug('Using the OAI EPC Release 14 MME in Docker')
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-mme /bin/bash -c "nohup tshark -i eth0 -i lo:s10 -w /tmp/mme_check_run.pcap 2>&1 > /dev/null"', '\$', 5)
+ time.sleep(5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-mme /bin/bash -c "nohup ./bin/oai_mme -c ./etc/mme.conf > mme_check_run.log 2>&1"', '\$', 5)
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
logging.debug('Using the OAI EPC Release 14 MME')
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
mySSH.command('echo ' + self.Password + ' | sudo -S rm -f mme_' + self.testCase_id + '.log', '\$', 5)
@@ -166,6 +155,25 @@ class EPCManagement():
if self.htmlObj is not None:
self.htmlObj.CreateHtmlTestRow(self.Type, 'OK', CONST.ALL_PROCESSES_OK)
+ def SetMmeIPAddress(self):
+ # Not an error if we don't need an EPC
+ if self.IPAddress == '' or self.UserName == '' or self.Password == '' or self.SourceCodePath == '' or self.Type == '':
+ return
+ if self.IPAddress == 'none':
+ return
+ # Only in case of Docker containers, MME IP address is not the EPC HOST IP address
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH = SSH.SSHConnection()
+ mySSH.open(self.IPAddress, self.UserName, self.Password)
+ mySSH.command('docker inspect --format="MME_IP_ADDR = {{range .NetworkSettings.Networks}}{{.IPAddress}}{{end}}" ' + self.containerPrefix + '-oai-mme', '\$', 5)
+ result = re.search('MME_IP_ADDR = (?P<mme_ip_addr>[0-9\.]+)', mySSH.getBefore())
+ if result is not None:
+ self.MmeIPAddress = result.group('mme_ip_addr')
+ logging.debug('MME IP Address is ' + self.MmeIPAddress)
+ mySSH.close()
+ else:
+ self.MmeIPAddress = self.IPAddress
+
def InitializeSPGW(self):
if self.IPAddress == '' or self.UserName == '' or self.Password == '' or self.SourceCodePath == '' or self.Type == '':
HELP.GenericHelp(CONST.Version)
@@ -173,7 +181,15 @@ class EPCManagement():
sys.exit('Insufficient EPC Parameters')
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ logging.debug('Using the OAI EPC Release 14 SPGW-CUPS in Docker')
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "nohup tshark -i eth0 -i lo:p5c -i lo:s5c -w /tmp/spgwc_check_run.pcap 2>&1 > /dev/null"', '\$', 5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "nohup tshark -i eth0 -w /tmp/spgwu_check_run.pcap 2>&1 > /dev/null"', '\$', 5)
+ time.sleep(5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "nohup ./bin/oai_spgwc -o -c ./etc/spgw_c.conf > spgwc_check_run.log 2>&1"', '\$', 5)
+ time.sleep(5)
+ mySSH.command('docker exec -d ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "nohup ./bin/oai_spgwu -o -c ./etc/spgw_u.conf > spgwu_check_run.log 2>&1"', '\$', 5)
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
logging.debug('Using the OAI EPC Release 14 SPGW-CUPS')
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
mySSH.command('echo ' + self.Password + ' | sudo -S rm -f spgwc_' + self.testCase_id + '.log spgwu_' + self.testCase_id + '.log', '\$', 5)
@@ -202,8 +218,11 @@ class EPCManagement():
try:
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- mySSH.command('stdbuf -o0 ps -aux | grep --color=never hss | grep -v grep', '\$', 5)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-hss /bin/bash -c "ps aux | grep oai_hss"', '\$', 5)
+ else:
+ mySSH.command('stdbuf -o0 ps -aux | grep --color=never hss | grep -v grep', '\$', 5)
+ if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
result = re.search('oai_hss -j', mySSH.getBefore())
elif re.match('OAI', self.Type, re.IGNORECASE):
result = re.search('\/bin\/bash .\/run_', mySSH.getBefore())
@@ -224,8 +243,13 @@ class EPCManagement():
try:
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- mySSH.command('stdbuf -o0 ps -aux | grep --color=never mme | grep -v grep', '\$', 5)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-mme /bin/bash -c "ps aux | grep oai_mme"', '\$', 5)
+ else:
+ mySSH.command('stdbuf -o0 ps -aux | grep --color=never mme | grep -v grep', '\$', 5)
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ result = re.search('oai_mme -c ', mySSH.getBefore())
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
result = re.search('mme -c', mySSH.getBefore())
elif re.match('OAI', self.Type, re.IGNORECASE):
result = re.search('\/bin\/bash .\/run_', mySSH.getBefore())
@@ -246,7 +270,13 @@ class EPCManagement():
try:
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "ps aux | grep oai_spgwc"', '\$', 5)
+ result = re.search('oai_spgwc -o -c ', mySSH.getBefore())
+ if result is not None:
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "ps aux | grep oai_spgwu"', '\$', 5)
+ result = re.search('oai_spgwu -o -c ', mySSH.getBefore())
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('stdbuf -o0 ps -aux | grep --color=never spgw | grep -v grep', '\$', 5)
result = re.search('spgwu -c ', mySSH.getBefore())
elif re.match('OAI', self.Type, re.IGNORECASE):
@@ -269,7 +299,14 @@ class EPCManagement():
def TerminateHSS(self):
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-hss /bin/bash -c "killall --signal SIGINT oai_hss tshark"', '\$', 5)
+ time.sleep(2)
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-hss /bin/bash -c "ps aux | grep oai_hss"', '\$', 5)
+ result = re.search('oai_hss -j ', mySSH.getBefore())
+ if result is not None:
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-hss /bin/bash -c "killall --signal SIGKILL oai_hss"', '\$', 5)
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('echo ' + self.Password + ' | sudo -S killall --signal SIGINT oai_hss || true', '\$', 5)
time.sleep(2)
mySSH.command('stdbuf -o0 ps -aux | grep hss | grep -v grep', '\$', 5)
@@ -298,7 +335,14 @@ class EPCManagement():
def TerminateMME(self):
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-mme /bin/bash -c "killall --signal SIGINT oai_mme tshark"', '\$', 5)
+ time.sleep(2)
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-mme /bin/bash -c "ps aux | grep oai_mme"', '\$', 5)
+ result = re.search('oai_mme -c ', mySSH.getBefore())
+ if result is not None:
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-mme /bin/bash -c "killall --signal SIGKILL oai_mme"', '\$', 5)
+ elif re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('echo ' + self.Password + ' | sudo -S killall --signal SIGINT run_mme mme || true', '\$', 5)
time.sleep(2)
mySSH.command('stdbuf -o0 ps -aux | grep mme | grep -v grep', '\$', 5)
@@ -318,7 +362,19 @@ class EPCManagement():
def TerminateSPGW(self):
mySSH = SSH.SSHConnection()
mySSH.open(self.IPAddress, self.UserName, self.Password)
- if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "killall --signal SIGINT oai_spgwc tshark"', '\$', 5)
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "killall --signal SIGINT oai_spgwu tshark"', '\$', 5)
+ time.sleep(2)
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "ps aux | grep oai_spgwc"', '\$', 5)
+ result = re.search('oai_spgwc -o -c ', mySSH.getBefore())
+ if result is not None:
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwc /bin/bash -c "killall --signal SIGKILL oai_spgwc"', '\$', 5)
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "ps aux | grep oai_spgwu"', '\$', 5)
+ result = re.search('oai_spgwu -o -c ', mySSH.getBefore())
+ if result is not None:
+ mySSH.command('docker exec -it ' + self.containerPrefix + '-oai-spgwu-tiny /bin/bash -c "killall --signal SIGKILL oai_spgwu"', '\$', 5)
+ elif re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('echo ' + self.Password + ' | sudo -S killall --signal SIGINT spgwc spgwu || true', '\$', 5)
time.sleep(2)
mySSH.command('stdbuf -o0 ps -aux | grep spgw | grep -v grep', '\$', 5)
@@ -352,7 +408,11 @@ class EPCManagement():
mySSH.open(self.IPAddress, self.UserName, self.Password)
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
mySSH.command('rm -f hss.log.zip', '\$', 5)
- if re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-hss:/openair-hss/hss_check_run.log .', '\$', 60)
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-hss:/tmp/hss_check_run.pcap .', '\$', 60)
+ mySSH.command('zip hss.log.zip hss_check_run.*', '\$', 60)
+ elif re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('zip hss.log.zip hss*.log', '\$', 60)
mySSH.command('echo ' + self.Password + ' | sudo -S rm hss*.log', '\$', 5)
if re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
@@ -370,7 +430,11 @@ class EPCManagement():
mySSH.open(self.IPAddress, self.UserName, self.Password)
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
mySSH.command('rm -f mme.log.zip', '\$', 5)
- if re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-mme:/openair-mme/mme_check_run.log .', '\$', 60)
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-mme:/tmp/mme_check_run.pcap .', '\$', 60)
+ mySSH.command('zip mme.log.zip mme_check_run.*', '\$', 60)
+ elif re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('zip mme.log.zip mme*.log', '\$', 60)
mySSH.command('echo ' + self.Password + ' | sudo -S rm mme*.log', '\$', 5)
elif re.match('ltebox', self.Type, re.IGNORECASE):
@@ -385,7 +449,13 @@ class EPCManagement():
mySSH.open(self.IPAddress, self.UserName, self.Password)
mySSH.command('cd ' + self.SourceCodePath + '/scripts', '\$', 5)
mySSH.command('rm -f spgw.log.zip', '\$', 5)
- if re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
+ if re.match('OAI-Rel14-Docker', self.Type, re.IGNORECASE):
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-spgwc:/openair-spgwc/spgwc_check_run.log .', '\$', 60)
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-spgwu-tiny:/openair-spgwu-tiny/spgwu_check_run.log .', '\$', 60)
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-spgwc:/tmp/spgwc_check_run.pcap .', '\$', 60)
+ mySSH.command('docker cp ' + self.containerPrefix + '-oai-spgwu-tiny:/tmp/spgwu_check_run.pcap .', '\$', 60)
+ mySSH.command('zip spgw.log.zip spgw*_check_run.*', '\$', 60)
+ elif re.match('OAI', self.Type, re.IGNORECASE) or re.match('OAI-Rel14-CUPS', self.Type, re.IGNORECASE):
mySSH.command('zip spgw.log.zip spgw*.log', '\$', 60)
mySSH.command('echo ' + self.Password + ' | sudo -S rm spgw*.log', '\$', 5)
elif re.match('ltebox', self.Type, re.IGNORECASE):
diff --git a/ci-scripts/html.py b/ci-scripts/html.py
index 3d0c8f3897d56693e6e31037c6a37d9701ecd2c0..8f2d38cced95600c4ae587ba65aab2f871d3edc5 100644
--- a/ci-scripts/html.py
+++ b/ci-scripts/html.py
@@ -82,70 +82,14 @@ class HTMLManagement():
#-----------------------------------------------------------
# Setters and Getters
#-----------------------------------------------------------
- def SethtmlUEFailureMsg(self,huefa):
- self.htmlUEFailureMsg = huefa
- def GethtmlUEFailureMsg(self):
- return self.htmlUEFailureMsg
- def SetHmleNBFailureMsg(self, msg):
- self.htmleNBFailureMsg = msg
-
- def Setdesc(self, dsc):
- self.desc = dsc
-
- def SetstartTime(self, sttime):
- self.startTime = sttime
-
- def SettestCase_id(self, tcid):
- self.testCase_id = tcid
- def GettestCase_id(self):
- return self.testCase_id
-
- def SetranRepository(self, repository):
- self.ranRepository = repository
- def SetranAllowMerge(self, merge):
- self.ranAllowMerge = merge
- def SetranBranch(self, branch):
- self.ranBranch = branch
- def SetranCommitID(self, commitid):
- self.ranCommitID = commitid
- def SetranTargetBranch(self, tbranch):
- self.ranTargetBranch = tbranch
-
+
def SethtmlUEConnected(self, nbUEs):
- self.htmlUEConnected = nbUEs
- def SethtmlNb_Smartphones(self, nbUEs):
- self.htmlNb_Smartphones = nbUEs
- def SethtmlNb_CATM_Modules(self, nbUEs):
- self.htmlNb_CATM_Modules = nbUEs
-
- def SetnbTestXMLfiles(self, nb):
- self.nbTestXMLfiles = nb
- def GetnbTestXMLfiles(self):
- return self.nbTestXMLfiles
-
- def SettestXMLfiles(self, xmlFile):
- self.testXMLfiles.append(xmlFile)
- def SethtmlTabRefs(self, tabRef):
- self.htmlTabRefs.append(tabRef)
- def SethtmlTabNames(self, tabName):
- self.htmlTabNames.append(tabName)
- def SethtmlTabIcons(self, tabIcon):
- self.htmlTabIcons.append(tabIcon)
+ if nbUEs > 0:
+ self.htmlUEConnected = nbUEs
+ else:
+ self.htmlUEConnected = 1
+
- def SetOsVersion(self, version, idx):
- self.OsVersion[idx] = version
- def SetKernelVersion(self, version, idx):
- self.KernelVersion[idx] = version
- def SetUhdVersion(self, version, idx):
- self.UhdVersion[idx] = version
- def SetUsrpBoard(self, version, idx):
- self.UsrpBoard[idx] = version
- def SetCpuNb(self, nb, idx):
- self.CpuNb[idx] = nb
- def SetCpuModel(self, model, idx):
- self.CpuModel[idx] = model
- def SetCpuMHz(self, freq, idx):
- self.CpuMHz[idx] = freq
#-----------------------------------------------------------
# HTML structure creation functions
@@ -323,7 +267,7 @@ class HTMLManagement():
continue
self.htmlFile.write(' <tr>\n')
- self.htmlFile.write(' <th colspan=8>' + str('eNB') + ' Server Characteristics</th>\n')
+ self.htmlFile.write(' <th colspan=8>' + str(machine) + ' Server Characteristics</th>\n')
self.htmlFile.write(' </tr>\n')
self.htmlFile.write(' <tr>\n')
self.htmlFile.write(' <td>OS Version</td>\n')
diff --git a/ci-scripts/main.py b/ci-scripts/main.py
index 1e149c40504f055ae6080fef01467f5be3d44aa5..d37f205f4e6a11cb72ebacb3455613b52b21d2f9 100644
--- a/ci-scripts/main.py
+++ b/ci-scripts/main.py
@@ -1,4 +1,4 @@
-
+#/*
# * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
# * contributor license agreements. See the NOTICE file distributed with
# * this work for additional information regarding copyright ownership.
@@ -28,14 +28,30 @@
# pexpect
#---------------------------------------------------------------------
+
+
+#-----------------------------------------------------------
+# Import Components
+#-----------------------------------------------------------
+
+import helpreadme as HELP
import constants as CONST
+import cls_physim #class PhySim for physical simulators build and test
+import cls_cots_ue #class CotsUe for Airplane mode control
+
+import sshconnection
+import epc
+import ran
+import html
+
+
#-----------------------------------------------------------
-# Import
+# Import Libs
#-----------------------------------------------------------
import sys # arg
import re # reg
-import pexpect # pexpect
+import pexpect # pexpect
import time # sleep
import os
import subprocess
@@ -50,8 +66,9 @@ logging.basicConfig(
)
+
#-----------------------------------------------------------
-# Class Declaration
+# OaiCiTest Class Definition
#-----------------------------------------------------------
class OaiCiTest():
@@ -86,7 +103,6 @@ class OaiCiTest():
self.UEDevicesRebootCmd = []
self.CatMDevices = []
self.UEIPAddresses = []
- self.htmlUEConnected = -1
self.idle_sleep_time = 0
self.x2_ho_options = 'network'
self.x2NbENBs = 0
@@ -97,12 +113,13 @@ class OaiCiTest():
self.UEIPAddress = ''
self.UEUserName = ''
self.UEPassword = ''
- self.UE_instance = ''
+ self.UE_instance = 0
self.UESourceCodePath = ''
self.UELogFile = ''
self.Build_OAI_UE_args = ''
self.Initialize_OAI_UE_args = ''
self.clean_repository = True
+ self.air_interface=''
self.expectedNbOfConnectedUEs = 0
def BuildOAIUE(self):
@@ -112,10 +129,10 @@ class OaiCiTest():
SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword)
result = re.search('--nrUE', self.Build_OAI_UE_args)
if result is not None:
- RAN.Setair_interface('nr')
+ self.air_interface='nr-uesoftmodem'
ue_prefix = 'NR '
else:
- RAN.Setair_interface('lte')
+ self.air_interface='lte-uesoftmodem'
ue_prefix = ''
result = re.search('([a-zA-Z0-9\:\-\.\/])+\.git', self.ranRepository)
if result is not None:
@@ -155,7 +172,7 @@ class OaiCiTest():
mismatch = True
if not mismatch:
SSH.close()
- HTML.CreateHtmlTestRow(RAN.GetBuild_eNB_args(), 'OK', CONST.ALL_PROCESSES_OK)
+ HTML.CreateHtmlTestRow(self.Build_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK)
return
SSH.command('echo ' + self.UEPassword + ' | sudo -S git clean -x -d -ff', '\$', 30)
@@ -177,11 +194,11 @@ class OaiCiTest():
SSH.command('mkdir -p log', '\$', 5)
SSH.command('chmod 777 log', '\$', 5)
# no need to remove in log (git clean did the trick)
- SSH.command('stdbuf -o0 ./build_oai ' + self.Build_OAI_UE_args + ' 2>&1 | stdbuf -o0 tee compile_oai_ue.log', 'Bypassing the Tests|build have failed', 600)
+ SSH.command('stdbuf -o0 ./build_oai ' + self.Build_OAI_UE_args + ' 2>&1 | stdbuf -o0 tee compile_oai_ue.log', 'Bypassing the Tests|build have failed', 900)
SSH.command('ls ran_build/build', '\$', 3)
SSH.command('ls ran_build/build', '\$', 3)
buildStatus = True
- result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore())
+ result = re.search(self.air_interface, SSH.getBefore())
if result is None:
buildStatus = False
SSH.command('mkdir -p build_log_' + self.testCase_id, '\$', 5)
@@ -209,33 +226,33 @@ class OaiCiTest():
sys.exit(1)
def CheckFlexranCtrlInstallation(self):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '':
return
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
SSH.command('ls -ls /opt/flexran_rtc/*/rt_controller', '\$', 5)
result = re.search('/opt/flexran_rtc/build/rt_controller', SSH.getBefore())
if result is not None:
- RAN.SetflexranCtrlInstalled(True)
+ RAN.flexranCtrlInstalled=True
logging.debug('Flexran Controller is installed')
SSH.close()
def InitializeFlexranCtrl(self):
- if RAN.GetflexranCtrlInstalled() == False:
+ if RAN.flexranCtrlInstalled == False:
return
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
SSH.command('cd /opt/flexran_rtc', '\$', 5)
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S rm -f log/*.log', '\$', 5)
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5)
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5)
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S rm -f log/*.log', '\$', 5)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S echo "build/rt_controller -c log_config/basic_log" > ./my-flexran-ctl.sh', '\$', 5)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S chmod 755 ./my-flexran-ctl.sh', '\$', 5)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S daemon --unsafe --name=flexran_rtc_daemon --chdir=/opt/flexran_rtc -o /opt/flexran_rtc/log/flexranctl_' + self.testCase_id + '.log ././my-flexran-ctl.sh', '\$', 5)
SSH.command('ps -aux | grep --color=never rt_controller', '\$', 5)
result = re.search('rt_controller -c ', SSH.getBefore())
if result is not None:
logging.debug('\u001B[1m Initialize FlexRan Controller Completed\u001B[0m')
- RAN.SetflexranCtrlStarted(True)
+ RAN.flexranCtrlStarted=True
SSH.close()
HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK)
@@ -306,14 +323,14 @@ class OaiCiTest():
if self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '' or self.UESourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
- if RAN.Getair_interface() == 'lte':
+ if self.air_interface == 'lte-uesoftmodem':
result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args))
if result is None:
check_eNB = True
check_OAI_UE = False
pStatus = self.CheckProcessExist(check_eNB, check_OAI_UE)
if (pStatus < 0):
- HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', pStatus)
+ HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', pStatus)
HTML.CreateHtmlTabFooter(False)
sys.exit(1)
UE_prefix = ''
@@ -333,15 +350,9 @@ class OaiCiTest():
logging.debug('Found a N3xx device --> resetting it')
SSH.command('cd ' + self.UESourceCodePath, '\$', 5)
# Initialize_OAI_UE_args usually start with -C and followed by the location in repository
- # in case of NR-UE, we may have rrc_config_path (Temporary?)
- modifiedUeOptions = str(self.Initialize_OAI_UE_args)
- if RAN.Getair_interface() == 'nr':
- result = re.search('--rrc_config_path ', modifiedUeOptions)
- if result is not None:
- modifiedUeOptions = modifiedUeOptions.replace('rrc_config_path ', 'rrc_config_path ' + self.UESourceCodePath + '/')
SSH.command('source oaienv', '\$', 5)
SSH.command('cd cmake_targets/ran_build/build', '\$', 5)
- if RAN.Getair_interface() == 'lte':
+ if self.air_interface == 'lte-uesoftmodem':
result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args))
# We may have to regenerate the .u* files
if result is None:
@@ -353,7 +364,17 @@ class OaiCiTest():
SSH.command('sed -e "s#93#92#" -e "s#8baf473f2f8fd09487cccbd7097c6862#fec86ba6eb707ed08905757b1bb44b8f#" -e "s#e734f8734007d6c5ce7a0508809e7e9c#C42449363BBAD02B66D16BC975D77CC1#" ../../../openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf > ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf', '\$', 5)
SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf .u*', '\$', 5)
SSH.command('echo ' + self.UEPassword + ' | sudo -S ../../../targets/bin/conf2uedata -c ../../../openair3/NAS/TOOLS/ci-ue_eurecom_test_sfr.conf -o .', '\$', 5)
- SSH.command('echo "ulimit -c unlimited && ./'+ RAN.Getair_interface() +'-uesoftmodem ' + modifiedUeOptions + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5)
+ else:
+ SSH.command('if [ -e rbconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm rbconfig.raw; fi', '\$', 5)
+ SSH.command('if [ -e reconfig.raw ]; then echo ' + self.UEPassword + ' | sudo -S rm reconfig.raw; fi', '\$', 5)
+ # Copy the RAW files from gNB running directory (maybe on another machine)
+ copyin_res = SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/rbconfig.raw', '.')
+ if (copyin_res == 0):
+ SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './rbconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build')
+ copyin_res = SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/reconfig.raw', '.')
+ if (copyin_res == 0):
+ SSH.copyout(self.UEIPAddress, self.UEUserName, self.UEPassword, './reconfig.raw', self.UESourceCodePath + '/cmake_targets/ran_build/build')
+ SSH.command('echo "ulimit -c unlimited && ./'+ self.air_interface +' ' + self.Initialize_OAI_UE_args + '" > ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5)
SSH.command('chmod 775 ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5)
SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5)
self.UELogFile = 'ue_' + self.testCase_id + '.log'
@@ -366,9 +387,7 @@ class OaiCiTest():
while (doOutterLoop):
SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/ran_build/build', '\$', 5)
SSH.command('echo ' + self.UEPassword + ' | sudo -S rm -Rf ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log', '\$', 5)
- #use nohup instead of daemon
- #SSH.command('echo ' + self.UEPassword + ' | sudo -S -E daemon --inherit --unsafe --name=ue' + str(self.UE_instance) + '_daemon --chdir=' + self.UESourceCodePath + '/cmake_targets/ran_build/build -o ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh', '\$', 5)
- SSH.command('echo $USER; nohup sudo ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5)
+ SSH.command('echo $USER; nohup sudo -E ./my-lte-uesoftmodem-run' + str(self.UE_instance) + '.sh' + ' > ' + self.UESourceCodePath + '/cmake_targets/ue_' + self.testCase_id + '.log ' + ' 2>&1 &', self.UEUserName, 5)
time.sleep(6)
SSH.command('cd ../..', '\$', 5)
doLoop = True
@@ -384,7 +403,7 @@ class OaiCiTest():
doLoop = False
continue
SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4)
- if RAN.Getair_interface() == 'nr':
+ if self.air_interface == 'nr-uesoftmodem':
result = re.search('Starting sync detection', SSH.getBefore())
else:
result = re.search('got sync', SSH.getBefore())
@@ -404,23 +423,50 @@ class OaiCiTest():
if (outterLoopCounter == 0):
doOutterLoop = False
continue
- if RAN.Getair_interface() == 'nr':
- fullSyncStatus = True
- doOutterLoop = False
+ # We are now checking if sync w/ eNB DOES NOT OCCUR
+ # Usually during the cell synchronization stage, the UE returns with No cell synchronization message
+ # That is the case for LTE
+ # In NR case, it's a positive message that will show if synchronization occurs
+ doLoop = True
+ if self.air_interface == 'nr-uesoftmodem':
+ loopCounter = 10
else:
# We are now checking if sync w/ eNB DOES NOT OCCUR
# Usually during the cell synchronization stage, the UE returns with No cell synchronization message
- doLoop = True
loopCounter = 10
- while (doLoop):
- loopCounter = loopCounter - 1
- if (loopCounter == 0):
+ while (doLoop):
+ loopCounter = loopCounter - 1
+ if (loopCounter == 0):
+ if self.air_interface == 'nr-uesoftmodem':
+ # Here we do have great chances that UE did NOT cell-sync w/ gNB
+ doLoop = False
+ fullSyncStatus = False
+ logging.debug('Never seen the NR-Sync message (Measured Carrier Frequency) --> try again')
+ time.sleep(6)
+ # Stopping the NR-UE
+ SSH.command('ps -aux | grep --text --color=never softmodem | grep -v grep', '\$', 4)
+ result = re.search('nr-uesoftmodem', SSH.getBefore())
+ if result is not None:
+ SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT nr-uesoftmodem', '\$', 4)
+ time.sleep(6)
+ else:
# Here we do have a great chance that the UE did cell-sync w/ eNB
doLoop = False
doOutterLoop = False
fullSyncStatus = True
continue
- SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync"', '\$', 4)
+ SSH.command('stdbuf -o0 cat ue_' + self.testCase_id + '.log | egrep --text --color=never -i "wait|sync|Frequency"', '\$', 4)
+ if self.air_interface == 'nr-uesoftmodem':
+ # Positive messaging -->
+ result = re.search('Measured Carrier Frequency', SSH.getBefore())
+ if result is not None:
+ doLoop = False
+ doOutterLoop = False
+ fullSyncStatus = True
+ else:
+ time.sleep(6)
+ else:
+ # Negative messaging -->
result = re.search('No cell synchronization found', SSH.getBefore())
if result is None:
time.sleep(6)
@@ -433,13 +479,22 @@ class OaiCiTest():
result = re.search('lte-uesoftmodem', SSH.getBefore())
if result is not None:
SSH.command('echo ' + self.UEPassword + ' | sudo -S killall --signal=SIGINT lte-uesoftmodem', '\$', 4)
- outterLoopCounter = outterLoopCounter - 1
- if (outterLoopCounter == 0):
- doOutterLoop = False
+ outterLoopCounter = outterLoopCounter - 1
+ if (outterLoopCounter == 0):
+ doOutterLoop = False
- if fullSyncStatus and gotSyncStatus and RAN.Getair_interface() == 'lte':
- result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args))
- if result is None:
+ if fullSyncStatus and gotSyncStatus:
+ doInterfaceCheck = False
+ if self.air_interface == 'lte-uesoftmodem':
+ result = re.search('--no-L2-connect', str(self.Initialize_OAI_UE_args))
+ if result is None:
+ doInterfaceCheck = True
+ # For the moment, only in explicit noS1 without kernel module (ie w/ tunnel interface)
+ if self.air_interface == 'nr-uesoftmodem':
+ result = re.search('--noS1 --nokrnmod 1', str(self.Initialize_OAI_UE_args))
+ if result is not None:
+ doInterfaceCheck = True
+ if doInterfaceCheck:
SSH.command('ifconfig oaitun_ue1', '\$', 4)
SSH.command('ifconfig oaitun_ue1', '\$', 4)
# ifconfig output is different between ubuntu 16 and ubuntu 18
@@ -451,7 +506,7 @@ class OaiCiTest():
logging.debug(SSH.getBefore())
logging.error('\u001B[1m oaitun_ue1 interface is either NOT mounted or NOT configured\u001B[0m')
tunnelInterfaceStatus = False
- if RAN.GeteNBmbmsEnable(0):
+ if RAN.eNBmbmsEnables[0]:
SSH.command('ifconfig oaitun_uem1', '\$', 4)
result = re.search('inet addr', SSH.getBefore())
if result is not None:
@@ -467,7 +522,7 @@ class OaiCiTest():
SSH.close()
if fullSyncStatus and gotSyncStatus and tunnelInterfaceStatus:
- HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE')
+ HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'OK', CONST.ALL_PROCESSES_OK, 'OAI UE')
logging.debug('\u001B[1m Initialize OAI UE Completed\u001B[0m')
if (self.ADBIPAddress != 'none'):
self.UEDevices = []
@@ -475,15 +530,15 @@ class OaiCiTest():
self.UEDevicesStatus = []
self.UEDevicesStatus.append(CONST.UE_STATUS_DETACHED)
else:
- if RAN.Getair_interface() == 'lte':
- if RAN.GeteNBmbmsEnable(0):
- HTML.SethtmlUEFailureMsg('oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured')
+ if self.air_interface == 'lte-uesoftmodem':
+ if RAN.eNBmbmsEnables[0]:
+ HTML.htmlUEFailureMsg='oaitun_ue1/oaitun_uem1 interfaces are either NOT mounted or NOT configured'
else:
- HTML.SethtmlUEFailureMsg('oaitun_ue1 interface is either NOT mounted or NOT configured')
- HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE')
+ HTML.htmlUEFailureMsg='oaitun_ue1 interface is either NOT mounted or NOT configured'
+ HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_NO_TUNNEL_INTERFACE, 'OAI UE')
else:
- HTML.SethtmlUEFailureMsg('nr-uesoftmodem did NOT synced')
- HTML.CreateHtmlTestRow(self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE')
+ HTML.htmlUEFailureMsg='nr-uesoftmodem did NOT synced'
+ HTML.CreateHtmlTestRow(self.air_interface + ' ' + self.Initialize_OAI_UE_args, 'KO', CONST.OAI_UE_PROCESS_COULD_NOT_SYNC, 'OAI UE')
logging.error('\033[91mInitialize OAI UE Failed! \033[0m')
self.AutoTerminateUEandeNB()
@@ -635,7 +690,7 @@ class OaiCiTest():
self.AutoTerminateUEandeNB()
def PingCatM(self):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
check_eNB = True
@@ -648,10 +703,10 @@ class OaiCiTest():
try:
statusQueue = SimpleQueue()
lock = Lock()
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath, '\$', 5)
SSH.command('cd scripts', '\$', 5)
- if re.match('OAI', EPC.GetType(), re.IGNORECASE):
+ if re.match('OAI', EPC.Type, re.IGNORECASE):
logging.debug('Using the OAI EPC HSS: not implemented yet')
HTML.CreateHtmlTestRow(self.ping_args, 'KO', pStatus)
HTML.CreateHtmlTabFooter(False)
@@ -851,7 +906,7 @@ class OaiCiTest():
self.UEDevicesStatus[cnt] = CONST.UE_STATUS_ATTACHED
cnt += 1
HTML.CreateHtmlTestRowQueue('N/A', 'OK', len(self.UEDevices), html_queue)
- result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args()))
+ result = re.search('T_stdout', str(RAN.Initialize_eNB_args))
if result is not None:
logging.debug('Waiting 5 seconds to fill up record file')
time.sleep(5)
@@ -897,7 +952,7 @@ class OaiCiTest():
for job in multi_jobs:
job.join()
HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK)
- result = re.search('T_stdout', str(RAN.GetInitialize_eNB_args()))
+ result = re.search('T_stdout', str(RAN.Initialize_eNB_args))
if result is not None:
logging.debug('Waiting 5 seconds to fill up record file')
time.sleep(5)
@@ -1031,7 +1086,6 @@ class OaiCiTest():
SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword)
if self.ADBCentralized:
SSH.command('adb devices', '\$', 15)
- #self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore())
self.UEDevices = re.findall("\\\\r\\\\n([A-Za-z0-9]+)\\\\tdevice",SSH.getBefore())
SSH.close()
else:
@@ -1163,8 +1217,8 @@ class OaiCiTest():
i += 1
for job in multi_jobs:
job.join()
- if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted():
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
+ if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted:
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
SSH.command('cd /opt/flexran_rtc', '\$', 5)
SSH.command('curl http://localhost:9999/stats | jq \'.\' > log/check_status_' + self.testCase_id + '.log 2>&1', '\$', 5)
SSH.command('cat log/check_status_' + self.testCase_id + '.log | jq \'.eNB_config[0].UE\' | grep -c rnti | sed -e "s#^#Nb Connected UE = #"', '\$', 5)
@@ -1276,13 +1330,13 @@ class OaiCiTest():
# Launch ping on the EPC side (true for ltebox and old open-air-cn)
# But for OAI-Rel14-CUPS, we launch from python executor
launchFromEpc = True
- if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE):
+ if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE):
launchFromEpc = False
ping_time = re.findall("-c (\d+)",str(self.ping_args))
if launchFromEpc:
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath, '\$', 5)
SSH.command('cd scripts', '\$', 5)
ping_status = SSH.command('stdbuf -o0 ping ' + self.ping_args + ' ' + UE_IPAddress + ' 2>&1 | stdbuf -o0 tee ping_' + self.testCase_id + '_' + device_id + '.log', '\$', int(ping_time[0])*1.5)
else:
@@ -1291,9 +1345,9 @@ class OaiCiTest():
logging.debug(cmd)
ret = subprocess.run(cmd, shell=True)
ping_status = ret.returncode
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'ping_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cat ' + EPC.SourceCodePath + '/scripts/ping_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
# TIMEOUT CASE
if ping_status < 0:
message = 'Ping with UE (' + str(UE_IPAddress) + ') crashed due to TIMEOUT!'
@@ -1373,7 +1427,7 @@ class OaiCiTest():
return
ping_from_eNB = re.search('oaitun_enb1', str(self.ping_args))
if ping_from_eNB is not None:
- if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '':
+ if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
else:
@@ -1382,8 +1436,8 @@ class OaiCiTest():
sys.exit('Insufficient Parameter')
try:
if ping_from_eNB is not None:
- SSH.open(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword())
- SSH.command('cd ' + RAN.GeteNBSourceCodePath() + '/cmake_targets/', '\$', 5)
+ SSH.open(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword)
+ SSH.command('cd ' + RAN.eNBSourceCodePath + '/cmake_targets/', '\$', 5)
else:
SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword)
SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets/', '\$', 5)
@@ -1447,20 +1501,20 @@ class OaiCiTest():
# copying on the EPC server for logCollection
if ping_from_eNB is not None:
- copyin_res = SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/ping_' + self.testCase_id + '.log', '.')
+ copyin_res = SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.')
else:
copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/ping_' + self.testCase_id + '.log', '.')
if (copyin_res == 0):
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'ping_' + self.testCase_id + '.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'ping_' + self.testCase_id + '.log', EPC.SourceCodePath + '/scripts')
except:
os.kill(os.getppid(),signal.SIGUSR1)
def Ping(self):
- result = re.search('noS1', str(RAN.GetInitialize_eNB_args()))
+ result = re.search('noS1', str(RAN.Initialize_eNB_args))
if result is not None:
self.PingNoS1()
return
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
check_eNB = True
@@ -1546,7 +1600,7 @@ class OaiCiTest():
return result
def Iperf_analyzeV2TCPOutput(self, lock, UE_IPAddress, device_id, statusQueue, iperf_real_options):
- SSH.command('awk -f /tmp/tcp_iperf_stats.awk /tmp/CI-eNB/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
+ SSH.command('awk -f /tmp/tcp_iperf_stats.awk ' + EPC.SourceCodePath + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
result = re.search('Avg Bitrate : (?P<average>[0-9\.]+ Mbits\/sec) Max Bitrate : (?P<maximum>[0-9\.]+ Mbits\/sec) Min Bitrate : (?P<minimum>[0-9\.]+ Mbits\/sec)', SSH.getBefore())
if result is not None:
avgbitrate = result.group('average')
@@ -1804,7 +1858,7 @@ class OaiCiTest():
# Launch iperf server on EPC side (true for ltebox and old open-air-cn0
# But for OAI-Rel14-CUPS, we launch from python executor and we are using its IP address as iperf client address
launchFromEpc = True
- if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE):
+ if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE):
launchFromEpc = False
cmd = 'hostname -I'
ret = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, encoding='utf-8')
@@ -1812,13 +1866,13 @@ class OaiCiTest():
EPC_Iperf_UE_IPAddress = ret.stdout.strip()
port = 5001 + idx
if launchFromEpc:
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5)
SSH.command('rm -f iperf_server_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
if udpIperf:
- SSH.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5)
+ SSH.command('echo $USER; nohup iperf -u -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.UserName, 5)
else:
- SSH.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.GetUserName(), 5)
+ SSH.command('echo $USER; nohup iperf -s -i 1 -p ' + str(port) + ' > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', EPC.UserName, 5)
SSH.close()
else:
if self.ueIperfVersion == self.dummyIperfVersion:
@@ -1841,7 +1895,7 @@ class OaiCiTest():
SSH.command('cd ' + self.UESourceCodePath + '/cmake_targets', '\$', 5)
else:
SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword)
- SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5)
+ SSH.command('cd ' + EPC.SourceCodePath+ '/scripts', '\$', 5)
iperf_time = self.Iperf_ComputeTime()
time.sleep(0.5)
@@ -1875,27 +1929,27 @@ class OaiCiTest():
# Kill iperf server on EPC side
if launchFromEpc:
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('killall --signal SIGKILL iperf', EPC.GetUserName(), 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('killall --signal SIGKILL iperf', EPC.UserName, 5)
SSH.close()
else:
cmd = 'killall --signal SIGKILL iperf'
logging.debug(cmd)
subprocess.run(cmd, shell=True)
time.sleep(1)
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
# in case of failure, retrieve server log
if (clientStatus == -1) or (clientStatus == -2):
if launchFromEpc:
time.sleep(1)
if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')):
os.remove('iperf_server_' + self.testCase_id + '_' + device_id + '.log')
- SSH.copyin(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
+ SSH.copyin(EPC.IPAddress, EPC.UserName, EPC.Password, EPC.SourceCodePath+ '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
self.Iperf_analyzeV2Server(lock, UE_IPAddress, device_id, statusQueue, modified_options)
# in case of OAI-UE
if (device_id == 'OAI-UE'):
SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_' + self.testCase_id + '_' + device_id + '.log', '.')
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
def Iperf_common(self, lock, UE_IPAddress, device_id, idx, ue_num, statusQueue):
try:
@@ -1909,8 +1963,8 @@ class OaiCiTest():
if (device_id != 'OAI-UE'):
SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword)
# if by chance ADB server and EPC are on the same remote host, at least log collection will take care of it
- SSH.command('if [ ! -d ' + EPC.GetSourceCodePath() + '/scripts ]; then mkdir -p ' + EPC.GetSourceCodePath() + '/scripts ; fi', '\$', 5)
- SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5)
+ SSH.command('if [ ! -d ' + EPC.SourceCodePath + '/scripts ]; then mkdir -p ' + EPC.SourceCodePath + '/scripts ; fi', '\$', 5)
+ SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5)
# Checking if iperf / iperf3 are installed
if self.ADBCentralized:
SSH.command('adb -s ' + device_id + ' shell "ls /data/local/tmp"', '\$', 5)
@@ -1969,7 +2023,7 @@ class OaiCiTest():
SSH.command('echo $USER; nohup iperf -B ' + UE_IPAddress + ' -u -s -i 1 > iperf_server_' + self.testCase_id + '_' + device_id + '.log &', self.UEUserName, 5)
else:
SSH.open(self.ADBIPAddress, self.ADBUserName, self.ADBPassword)
- SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5)
+ SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5)
if self.ADBCentralized:
if (useIperf3):
SSH.command('stdbuf -o0 adb -s ' + device_id + ' shell /data/local/tmp/iperf3 -s &', '\$', 5)
@@ -1991,11 +2045,11 @@ class OaiCiTest():
# Launch the IPERF client on the EPC side for DL (true for ltebox and old open-air-cn
# But for OAI-Rel14-CUPS, we launch from python executor
launchFromEpc = True
- if re.match('OAI-Rel14-CUPS', EPC.GetType(), re.IGNORECASE):
+ if re.match('OAI-Rel14-CUPS', EPC.Type, re.IGNORECASE):
launchFromEpc = False
if launchFromEpc:
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath() + '/scripts', '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath + '/scripts', '\$', 5)
iperf_time = self.Iperf_ComputeTime()
time.sleep(0.5)
@@ -2030,9 +2084,9 @@ class OaiCiTest():
logging.debug(cmd)
ret = subprocess.run(cmd, shell=True)
iperf_status = ret.returncode
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cat ' + EPC.GetSourceCodePath() + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cat ' + EPC.SourceCodePath + '/scripts/iperf_' + self.testCase_id + '_' + device_id + '.log', '\$', 5)
if iperf_status < 0:
if launchFromEpc:
SSH.close()
@@ -2069,7 +2123,7 @@ class OaiCiTest():
if (device_id == 'OAI-UE'):
SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
else:
- SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, EPC.GetSourceCodePath() + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
+ SSH.copyin(self.ADBIPAddress, self.ADBUserName, self.ADBPassword, EPC.SourceCodePath + '/scripts/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
# fromdos has to be called on the python executor not on ADB server
cmd = 'fromdos -o iperf_server_' + self.testCase_id + '_' + device_id + '.log'
subprocess.run(cmd, shell=True)
@@ -2079,15 +2133,15 @@ class OaiCiTest():
if (device_id == 'OAI-UE'):
if (os.path.isfile('iperf_server_' + self.testCase_id + '_' + device_id + '.log')):
if not launchFromEpc:
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
else:
SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/iperf_server_' + self.testCase_id + '_' + device_id + '.log', '.')
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_' + device_id + '.log', EPC.SourceCodePath + '/scripts')
except:
os.kill(os.getppid(),signal.SIGUSR1)
def IperfNoS1(self):
- if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '':
+ if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or self.UEIPAddress == '' or self.UEUserName == '' or self.UEPassword == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
check_eNB = True
@@ -2099,9 +2153,9 @@ class OaiCiTest():
return
server_on_enb = re.search('-R', str(self.iperf_args))
if server_on_enb is not None:
- iServerIPAddr = RAN.GeteNBIPAddress()
- iServerUser = RAN.GeteNBUserName()
- iServerPasswd = RAN.GeteNBPassword()
+ iServerIPAddr = RAN.eNBIPAddress
+ iServerUser = RAN.eNBUserName
+ iServerPasswd = RAN.eNBPassword
iClientIPAddr = self.UEIPAddress
iClientUser = self.UEUserName
iClientPasswd = self.UEPassword
@@ -2109,9 +2163,9 @@ class OaiCiTest():
iServerIPAddr = self.UEIPAddress
iServerUser = self.UEUserName
iServerPasswd = self.UEPassword
- iClientIPAddr = RAN.GeteNBIPAddress()
- iClientUser = RAN.GeteNBUserName()
- iClientPasswd = RAN.GeteNBPassword()
+ iClientIPAddr = RAN.eNBIPAddress
+ iClientUser = RAN.eNBUserName
+ iClientPasswd = RAN.eNBPassword
if self.iperf_options != 'sink':
# Starting the iperf server
SSH.open(iServerIPAddr, iServerUser, iServerPasswd)
@@ -2166,10 +2220,10 @@ class OaiCiTest():
if (clientStatus == -1):
copyin_res = SSH.copyin(iServerIPAddr, iServerUser, iServerPasswd, '/tmp/tmp_iperf_server_' + self.testCase_id + '.log', 'iperf_server_' + self.testCase_id + '_OAI-UE.log')
if (copyin_res == 0):
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_server_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_server_' + self.testCase_id + '_OAI-UE.log', EPC.SourceCodePath + '/scripts')
copyin_res = SSH.copyin(iClientIPAddr, iClientUser, iClientPasswd, '/tmp/tmp_iperf_' + self.testCase_id + '.log', 'iperf_' + self.testCase_id + '_OAI-UE.log')
if (copyin_res == 0):
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), 'iperf_' + self.testCase_id + '_OAI-UE.log', EPC.GetSourceCodePath() + '/scripts')
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, 'iperf_' + self.testCase_id + '_OAI-UE.log', EPC.SourceCodePath + '/scripts')
iperf_noperf = False
if status_queue.empty():
iperf_status = False
@@ -2196,11 +2250,11 @@ class OaiCiTest():
self.AutoTerminateUEandeNB()
def Iperf(self):
- result = re.search('noS1', str(RAN.GetInitialize_eNB_args()))
+ result = re.search('noS1', str(RAN.Initialize_eNB_args))
if result is not None:
self.IperfNoS1()
return
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '' or self.ADBIPAddress == '' or self.ADBUserName == '' or self.ADBPassword == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
check_eNB = True
@@ -2277,7 +2331,7 @@ class OaiCiTest():
status_queue = SimpleQueue()
# in noS1 config, no need to check status from EPC
# in gNB also currently no need to check
- result = re.search('noS1|band78', str(RAN.GetInitialize_eNB_args()))
+ result = re.search('noS1|band78', str(RAN.Initialize_eNB_args))
if result is None:
p = Process(target = EPC.CheckHSSProcess, args = (status_queue,))
p.daemon = True
@@ -2316,14 +2370,14 @@ class OaiCiTest():
if (status < 0):
result = status
if result == CONST.ENB_PROCESS_FAILED:
- fileCheck = re.search('enb_', str(RAN.GeteNBLogFile(0)))
+ fileCheck = re.search('enb_', str(RAN.eNBLogFiles[0]))
if fileCheck is not None:
- SSH.copyin(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath() + '/cmake_targets/' + RAN.GeteNBLogFile(0), '.')
- logStatus = RAN.AnalyzeLogFile_eNB(RAN.GeteNBLogFile[0])
+ SSH.copyin(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath + '/cmake_targets/' + RAN.eNBLogFiles[0], '.')
+ logStatus = RAN.AnalyzeLogFile_eNB(RAN.eNBLogFiles[0])
if logStatus < 0:
result = logStatus
- RAN.SeteNBLogFile('', 0)
- if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted():
+ RAN.eNBLogFiles[0]=''
+ if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted:
self.TerminateFlexranCtrl()
return result
@@ -2358,8 +2412,8 @@ class OaiCiTest():
def CheckOAIUEProcess(self, status_queue):
try:
SSH.open(self.UEIPAddress, self.UEUserName, self.UEPassword)
- SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + RAN.Getair_interface() + '-uesoftmodem | grep -v grep', '\$', 5)
- result = re.search(RAN.Getair_interface() + '-uesoftmodem', SSH.getBefore())
+ SSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + ' | grep -v grep', '\$', 5)
+ result = re.search(self.air_interface, SSH.getBefore())
if result is None:
logging.debug('\u001B[1;37;41m OAI UE Process Not Found! \u001B[0m')
status_queue.put(CONST.OAI_UE_PROCESS_FAILED)
@@ -2396,7 +2450,8 @@ class OaiCiTest():
nrFoundDCI = 0
nrCRCOK = 0
mbms_messages = 0
- HTML.SethtmlUEFailureMsg('')
+ HTML.htmlUEFailureMsg=''
+ global_status = CONST.ALL_PROCESSES_OK
for line in ue_log_file.readlines():
result = re.search('nr_synchro_time', str(line))
if result is not None:
@@ -2457,7 +2512,7 @@ class OaiCiTest():
result = re.search('No cell synchronization found, abandoning', str(line))
if result is not None:
no_cell_sync_found = True
- if RAN.GeteNBmbmsEnable(0):
+ if RAN.eNBmbmsEnables[0]:
result = re.search('TRIED TO PUSH MBMS DATA', str(line))
if result is not None:
mbms_messages += 1
@@ -2465,22 +2520,22 @@ class OaiCiTest():
if result is not None and (not mib_found):
try:
mibMsg = "MIB Information: " + result.group(1) + ', ' + result.group(2)
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
mibMsg = " nidcell = " + result.group('nidcell')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg)
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg
logging.debug('\033[94m' + mibMsg + '\033[0m')
mibMsg = " n_rb_dl = " + result.group('n_rb_dl')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
mibMsg = " phich_duration = " + result.group('phich_duration')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg)
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg
logging.debug('\033[94m' + mibMsg + '\033[0m')
mibMsg = " phich_resource = " + result.group('phich_resource')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
mibMsg = " tx_ant = " + result.group('tx_ant')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
mib_found = True
except Exception as e:
@@ -2489,7 +2544,7 @@ class OaiCiTest():
if result is not None and (not frequency_found):
try:
mibMsg = "Measured Carrier Frequency = " + result.group('measured_carrier_frequency') + ' Hz'
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
frequency_found = True
except Exception as e:
@@ -2498,7 +2553,7 @@ class OaiCiTest():
if result is not None and (not plmn_found):
try:
mibMsg = 'PLMN MCC = ' + result.group('mcc') + ' MNC = ' + result.group('mnc')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
plmn_found = True
except Exception as e:
@@ -2507,7 +2562,7 @@ class OaiCiTest():
if result is not None:
try:
mibMsg = "The operator is: " + result.group('operator')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + '\n'
logging.debug('\033[94m' + mibMsg + '\033[0m')
except Exception as e:
logging.error('\033[91m' + "Operator name not found" + '\033[0m')
@@ -2515,25 +2570,25 @@ class OaiCiTest():
if result is not None:
try:
mibMsg = "SIB5 InterFreqCarrierFreq element " + result.group(1) + '/' + result.group(2)
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + mibMsg + ' -> ')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + mibMsg + ' -> '
logging.debug('\033[94m' + mibMsg + '\033[0m')
except Exception as e:
logging.error('\033[91m' + "SIB5 InterFreqCarrierFreq element not found" + '\033[0m')
- result = re.search("DL Carrier Frequency/ARFCN : (?P<carrier_frequency>\d{1,15}/\d{1,4})", str(line))
+ result = re.search("DL Carrier Frequency/ARFCN : \-*(?P<carrier_frequency>\d{1,15}/\d{1,4})", str(line))
if result is not None:
try:
freq = result.group('carrier_frequency')
new_freq = re.sub('/[0-9]+','',freq)
float_freq = float(new_freq) / 1000000
- HTMLSethtmlUEFailureMsg(HTMLGethtmlUEFailureMsg() + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz')
- logging.debug('\033[94m' + " DL Carrier Frequency is: " + freq + '\033[0m')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'DL Freq: ' + ('%.1f' % float_freq) + ' MHz'
+ logging.debug('\033[94m' + " DL Carrier Frequency is: " + str(freq) + '\033[0m')
except Exception as e:
logging.error('\033[91m' + " DL Carrier Frequency not found" + '\033[0m')
result = re.search("AllowedMeasBandwidth : (?P<allowed_bandwidth>\d{1,7})", str(line))
if result is not None:
try:
prb = result.group('allowed_bandwidth')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + ' -- PRB: ' + prb + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + ' -- PRB: ' + prb + '\n'
logging.debug('\033[94m' + " AllowedMeasBandwidth: " + prb + '\033[0m')
except Exception as e:
logging.error('\033[91m' + " AllowedMeasBandwidth not found" + '\033[0m')
@@ -2541,100 +2596,100 @@ class OaiCiTest():
if rrcConnectionRecfgComplete > 0:
statMsg = 'UE connected to eNB (' + str(rrcConnectionRecfgComplete) + ' RRCConnectionReconfigurationComplete message(s) generated)'
logging.debug('\033[94m' + statMsg + '\033[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if nrUEFlag:
if nrDecodeMib > 0:
statMsg = 'UE showed ' + str(nrDecodeMib) + ' MIB decode message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if nrFoundDCI > 0:
statMsg = 'UE showed ' + str(nrFoundDCI) + ' DCI found message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if nrCRCOK > 0:
statMsg = 'UE showed ' + str(nrCRCOK) + ' PDSCH decoding message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if not frequency_found:
statMsg = 'NR-UE could NOT synch!'
logging.error('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if uciStatMsgCount > 0:
statMsg = 'UE showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if pdcpDataReqFailedCount > 0:
statMsg = 'UE showed ' + str(pdcpDataReqFailedCount) + ' "PDCP data request failed" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if badDciCount > 0:
statMsg = 'UE showed ' + str(badDciCount) + ' "bad DCI 1(A)" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if f1aRetransmissionCount > 0:
statMsg = 'UE showed ' + str(f1aRetransmissionCount) + ' "Format1A Retransmission but TBS are different" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if fatalErrorCount > 0:
statMsg = 'UE showed ' + str(fatalErrorCount) + ' "FATAL ERROR:" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if macBsrTimerExpiredCount > 0:
statMsg = 'UE showed ' + str(fatalErrorCount) + ' "MAC BSR Triggered ReTxBSR Timer expiry" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
- if RAN.GeteNBmbmsEnable(0):
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
+ if RAN.eNBmbmsEnables[0]:
if mbms_messages > 0:
statMsg = 'UE showed ' + str(mbms_messages) + ' "TRIED TO PUSH MBMS DATA" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
else:
statMsg = 'UE did NOT SHOW "TRIED TO PUSH MBMS DATA" message(s)'
logging.debug('\u001B[1;30;41m ' + statMsg + ' \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + statMsg + '\n')
+ global_status = CONST.OAI_UE_PROCESS_NO_MBMS_MSGS
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + statMsg + '\n'
if foundSegFault:
logging.debug('\u001B[1;37;41m UE ended with a Segmentation Fault! \u001B[0m')
if not nrUEFlag:
- return CONST.OAI_UE_PROCESS_SEG_FAULT
+ global_status = CONST.OAI_UE_PROCESS_SEG_FAULT
else:
if not frequency_found:
- return CONST.OAI_UE_PROCESS_SEG_FAULT
+ global_status = CONST.OAI_UE_PROCESS_SEG_FAULT
if foundAssertion:
logging.debug('\u001B[1;30;43m UE showed an assertion! \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE showed an assertion!\n')
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE showed an assertion!\n'
if not nrUEFlag:
if not mib_found or not frequency_found:
- return CONST.OAI_UE_PROCESS_ASSERTION
+ global_status = CONST.OAI_UE_PROCESS_ASSERTION
else:
if not frequency_found:
- return CONST.OAI_UE_PROCESS_ASSERTION
+ global_status = CONST.OAI_UE_PROCESS_ASSERTION
if foundRealTimeIssue:
logging.debug('\u001B[1;37;41m UE faced real time issues! \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE faced real time issues!\n')
- #return CONST.ENB_PROCESS_REALTIME_ISSUE
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE faced real time issues!\n'
if nrUEFlag:
if not frequency_found:
- return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC
+ global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC
else:
if no_cell_sync_found and not mib_found:
logging.debug('\u001B[1;37;41m UE could not synchronize ! \u001B[0m')
- HTML.SethtmlUEFailureMsg(HTML.GethtmlUEFailureMsg() + 'UE could not synchronize!\n')
- return CONST.OAI_UE_PROCESS_COULD_NOT_SYNC
- return 0
+ HTML.htmlUEFailureMsg=HTML.htmlUEFailureMsg + 'UE could not synchronize!\n'
+ global_status = CONST.OAI_UE_PROCESS_COULD_NOT_SYNC
+ return global_status
def TerminateFlexranCtrl(self):
- if RAN.GetflexranCtrlInstalled() == False or RAN.GetflexranCtrlStarted() == False:
+ if RAN.flexranCtrlInstalled == False or RAN.flexranCtrlStarted == False:
return
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S daemon --name=flexran_rtc_daemon --stop', '\$', 5)
time.sleep(1)
- SSH.command('echo ' + EPC.GetPassword() + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5)
+ SSH.command('echo ' + EPC.Password + ' | sudo -S killall --signal SIGKILL rt_controller', '\$', 5)
time.sleep(1)
SSH.close()
- RAN.SetflexranCtrlStarted(False)
+ RAN.flexranCtrlStarted=False
HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK)
def TerminateUE_common(self, device_id, idx):
@@ -2700,7 +2755,7 @@ class OaiCiTest():
copyin_res = SSH.copyin(self.UEIPAddress, self.UEUserName, self.UEPassword, self.UESourceCodePath + '/cmake_targets/' + self.UELogFile, '.')
if (copyin_res == -1):
logging.debug('\u001B[1;37;41m Could not copy UE logfile to analyze it! \u001B[0m')
- HTML.SethtmlUEFailureMsg('Could not copy UE logfile to analyze it!')
+ HTML.htmlUEFailureMsg='Could not copy UE logfile to analyze it!'
HTML.CreateHtmlTestRow('N/A', 'KO', CONST.OAI_UE_PROCESS_NOLOGFILE_TO_ANALYZE, 'UE')
self.UELogFile = ''
return
@@ -2713,9 +2768,9 @@ class OaiCiTest():
ueAction = 'Connection'
if (logStatus < 0):
logging.debug('\u001B[1m' + ueAction + ' Failed \u001B[0m')
- HTML.SethtmlUEFailureMsg('<b>' + ueAction + ' Failed</b>\n' + HTML.GethtmlUEFailureMsg())
+ HTML.htmlUEFailureMsg='<b>' + ueAction + ' Failed</b>\n' + HTML.htmlUEFailureMsg
HTML.CreateHtmlTestRow('N/A', 'KO', logStatus, 'UE')
- if RAN.Getair_interface() == 'lte':
+ if self.air_interface == 'lte-uesoftmodem':
# In case of sniffing on commercial eNBs we have random results
# Not an error then
if (logStatus != CONST.OAI_UE_PROCESS_COULD_NOT_SYNC) or (ueAction != 'Sniffing'):
@@ -2727,7 +2782,7 @@ class OaiCiTest():
self.AutoTerminateUEandeNB()
else:
logging.debug('\u001B[1m' + ueAction + ' Completed \u001B[0m')
- HTML.SethtmlUEFailureMsg('<b>' + ueAction + ' Completed</b>\n' + HTML.GethtmlUEFailureMsg())
+ HTML.htmlUEFailureMsg='<b>' + ueAction + ' Completed</b>\n' + HTML.htmlUEFailureMsg
HTML.CreateHtmlTestRow('N/A', 'OK', CONST.ALL_PROCESSES_OK)
self.UELogFile = ''
else:
@@ -2736,41 +2791,41 @@ class OaiCiTest():
def AutoTerminateUEandeNB(self):
if (self.ADBIPAddress != 'none'):
self.testCase_id = 'AUTO-KILL-UE'
- HTML.SettestCase_id(self.testCase_id)
+ HTML.testCase_id=self.testCase_id
self.desc = 'Automatic Termination of UE'
- HTML.Setdesc('Automatic Termination of UE')
+ HTML.desc='Automatic Termination of UE'
self.ShowTestID()
self.TerminateUE()
if (self.Initialize_OAI_UE_args != ''):
self.testCase_id = 'AUTO-KILL-OAI-UE'
- HTML.SettestCase_id(self.testCase_id)
+ HTML.testCase_id=self.testCase_id
self.desc = 'Automatic Termination of OAI-UE'
- HTML.Setdesc('Automatic Termination of OAI-UE')
+ HTML.desc='Automatic Termination of OAI-UE'
self.ShowTestID()
self.TerminateOAIUE()
- if (RAN.GetInitialize_eNB_args() != ''):
+ if (RAN.Initialize_eNB_args != ''):
self.testCase_id = 'AUTO-KILL-eNB'
- HTML.SettestCase_id(self.testCase_id)
+ HTML.testCase_id=self.testCase_id
self.desc = 'Automatic Termination of eNB'
- HTML.Setdesc('Automatic Termination of eNB')
+ HTML.desc='Automatic Termination of eNB'
self.ShowTestID()
- RAN.SeteNB_instance('0')
+ RAN.eNB_instance=0
RAN.TerminateeNB()
- if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted():
+ if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted:
self.testCase_id = 'AUTO-KILL-flexran-ctl'
- HTML.SettestCase_id(self.testCase_id)
+ HTML.testCase_id=self.testCase_id
self.desc = 'Automatic Termination of FlexRan CTL'
- HTML.Setdesc('Automatic Termination of FlexRan CTL')
+ HTML.desc='Automatic Termination of FlexRan CTL'
self.ShowTestID()
self.TerminateFlexranCtrl()
- RAN.SetprematureExit(True)
+ RAN.prematureExit=True
def IdleSleep(self):
time.sleep(self.idle_sleep_time)
HTML.CreateHtmlTestRow(str(self.idle_sleep_time) + ' sec', 'OK', CONST.ALL_PROCESSES_OK)
def X2_Status(self, idx, fileName):
- cmd = "curl --silent http://" + EPC.GetIPAddress() + ":9999/stats | jq '.' > " + fileName
+ cmd = "curl --silent http://" + EPC.IPAddress + ":9999/stats | jq '.' > " + fileName
message = cmd + '\n'
logging.debug(cmd)
subprocess.run(cmd, shell=True)
@@ -2819,7 +2874,7 @@ class OaiCiTest():
logging.debug(msg)
fullMessage += msg + '\n'
if self.x2_ho_options == 'network':
- if RAN.GetflexranCtrlInstalled() and RAN.GetflexranCtrlStarted():
+ if RAN.flexranCtrlInstalled and RAN.flexranCtrlStarted:
self.x2ENBBsIds = []
self.x2ENBConnectedUEs = []
self.x2ENBBsIds.append([])
@@ -2834,7 +2889,7 @@ class OaiCiTest():
eNB_cnt = self.x2NbENBs
cnt = 0
while cnt < eNB_cnt:
- cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1"
+ cmd = "curl -XPOST http://" + EPC.IPAddress + ":9999/rrc/x2_ho_net_control/enb/" + str(self.x2ENBBsIds[0][cnt]) + "/1"
logging.debug(cmd)
fullMessage += cmd + '\n'
subprocess.run(cmd, shell=True)
@@ -2848,7 +2903,7 @@ class OaiCiTest():
while cnt < eNB_cnt:
ueIdx = 0
while ueIdx < len(self.x2ENBConnectedUEs[0][cnt]):
- cmd = "curl -XPOST http://" + EPC.GetIPAddress() + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1])
+ cmd = "curl -XPOST http://" + EPC.IPAddress() + ":9999/rrc/ho/senb/" + str(self.x2ENBBsIds[0][cnt]) + "/ue/" + str(self.x2ENBConnectedUEs[0][cnt][ueIdx]) + "/tenb/" + str(self.x2ENBBsIds[0][eNB_cnt - cnt - 1])
logging.debug(cmd)
fullMessage += cmd + '\n'
subprocess.run(cmd, shell=True)
@@ -2880,11 +2935,11 @@ class OaiCiTest():
HTML.CreateHtmlTestRow('Cannot perform requested X2 Handover', 'KO', CONST.ALL_PROCESSES_OK)
def LogCollectBuild(self):
- if (RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != ''):
- IPAddress = RAN.GeteNBIPAddress()
- UserName = RAN.GeteNBUserName()
- Password = RAN.GeteNBPassword()
- SourceCodePath = RAN.GeteNBSourceCodePath()
+ if (RAN.eNBIPAddress != '' and RAN.eNBUserName != '' and RAN.eNBPassword != ''):
+ IPAddress = RAN.eNBIPAddress
+ UserName = RAN.eNBUserName
+ Password = RAN.eNBPassword
+ SourceCodePath = RAN.eNBSourceCodePath
elif (self.UEIPAddress != '' and self.UEUserName != '' and self.UEPassword != ''):
IPAddress = self.UEIPAddress
UserName = self.UEUserName
@@ -2899,8 +2954,8 @@ class OaiCiTest():
SSH.command('zip build.log.zip build_log_*/*', '\$', 60)
SSH.close()
def LogCollectPing(self):
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath, '\$', 5)
SSH.command('cd scripts', '\$', 5)
SSH.command('rm -f ping.log.zip', '\$', 5)
SSH.command('zip ping.log.zip ping*.log', '\$', 60)
@@ -2908,8 +2963,8 @@ class OaiCiTest():
SSH.close()
def LogCollectIperf(self):
- SSH.open(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword())
- SSH.command('cd ' + EPC.GetSourceCodePath(), '\$', 5)
+ SSH.open(EPC.IPAddress, EPC.UserName, EPC.Password)
+ SSH.command('cd ' + EPC.SourceCodePath, '\$', 5)
SSH.command('cd scripts', '\$', 5)
SSH.command('rm -f iperf.log.zip', '\$', 5)
SSH.command('zip iperf.log.zip iperf*.log', '\$', 60)
@@ -2926,20 +2981,20 @@ class OaiCiTest():
SSH.close()
def RetrieveSystemVersion(self, machine):
- if RAN.GeteNBIPAddress() == 'none' or self.UEIPAddress == 'none':
- HTML.SetOsVersion('Ubuntu 16.04.5 LTS', 0)
- HTML.SetKernelVersion('4.15.0-45-generic', 0)
- HTML.SetUhdVersion('3.13.0.1-0', 0)
- HTML.SetUsrpBoard('B210', 0)
- HTML.SetCpuNb('4', 0)
- HTML.SetCpuModel('Intel(R) Core(TM) i5-6200U', 0)
- HTML.SetCpuMHz('2399.996 MHz', 0)
+ if RAN.eNBIPAddress == 'none' or self.UEIPAddress == 'none':
+ HTML.OsVersion[0]='Ubuntu 16.04.5 LTS'
+ HTML.KernelVersion[0]='4.15.0-45-generic'
+ HTML.UhdVersion[0]='3.13.0.1-0'
+ HTML.UsrpBoard[0]='B210'
+ HTML.CpuNb[0]='4'
+ HTML.CpuModel[0]='Intel(R) Core(TM) i5-6200U'
+ HTML.CpuMHz[0]='2399.996 MHz'
return 0
if machine == 'eNB':
- if RAN.GeteNBIPAddress() != '' and RAN.GeteNBUserName() != '' and RAN.GeteNBPassword() != '':
- IPAddress = RAN.GeteNBIPAddress()
- UserName = RAN.GeteNBUserName()
- Password = RAN.GeteNBPassword()
+ if RAN.eNBIPAddress != '' and RAN.eNBUserName != '' and RAN.eNBPassword != '':
+ IPAddress = RAN.eNBIPAddress
+ UserName = RAN.eNBUserName
+ Password = RAN.eNBPassword
idx = 0
else:
return -1
@@ -2958,7 +3013,7 @@ class OaiCiTest():
if result is not None:
OsVersion = result.group('os_type')
logging.debug('OS is: ' + OsVersion)
- HTML.SetOsVersion(OsVersion, idx)
+ HTML.OsVersion[idx]=OsVersion
else:
SSH.command('hostnamectl', '\$', 5)
result = re.search('Operating System: (?P<os_type>[a-zA-Z0-9\-\_\.\ ]+)', SSH.getBefore())
@@ -2970,26 +3025,26 @@ class OaiCiTest():
if result is not None:
OsVersion = OsVersion.replace('7 ', result.group('os_version'))
logging.debug('OS is: ' + OsVersion)
- HTML.SetOsVersion(OsVersion, idx)
+ HTML.OsVersion[idx]=OsVersion
SSH.command('uname -r', '\$', 5)
result = re.search('uname -r\\\\r\\\\n(?P<kernel_version>[a-zA-Z0-9\-\_\.]+)', SSH.getBefore())
if result is not None:
KernelVersion = result.group('kernel_version')
logging.debug('Kernel Version is: ' + KernelVersion)
- HTML.SetKernelVersion(KernelVersion, idx)
+ HTML.KernelVersion[idx]=KernelVersion
SSH.command('dpkg --list | egrep --color=never libuhd003', '\$', 5)
result = re.search('libuhd003:amd64 *(?P<uhd_version>[0-9\.]+)', SSH.getBefore())
if result is not None:
UhdVersion = result.group('uhd_version')
logging.debug('UHD Version is: ' + UhdVersion)
- HTML.SetUhdVersion(UhdVersion, idx)
+ HTML.UhdVersion[idx]=UhdVersion
else:
SSH.command('uhd_config_info --version', '\$', 5)
result = re.search('UHD (?P<uhd_version>[a-zA-Z0-9\.\-]+)', SSH.getBefore())
if result is not None:
UhdVersion = result.group('uhd_version')
logging.debug('UHD Version is: ' + UhdVersion)
- HTML.SetUhdVersion(UhdVersion, idx)
+ HTML.UhdVersion[idx]=UhdVersion
SSH.command('echo ' + Password + ' | sudo -S uhd_find_devices', '\$', 60)
usrp_boards = re.findall('product: ([0-9A-Za-z]+)\\\\r\\\\n', SSH.getBefore())
count = 0
@@ -3001,99 +3056,132 @@ class OaiCiTest():
count += 1
if count > 0:
logging.debug('USRP Board(s) : ' + UsrpBoard)
- HTML.SetUsrpBoard(UsrpBoard, idx)
+ HTML.UsrpBoard[idx]=UsrpBoard
SSH.command('lscpu', '\$', 5)
result = re.search('CPU\(s\): *(?P<nb_cpus>[0-9]+).*Model name: *(?P<model>[a-zA-Z0-9\-\_\.\ \(\)]+).*CPU MHz: *(?P<cpu_mhz>[0-9\.]+)', SSH.getBefore())
if result is not None:
CpuNb = result.group('nb_cpus')
logging.debug('nb_cpus: ' + CpuNb)
- HTML.SetCpuNb(CpuNb, idx)
+ HTML.CpuNb[idx]=CpuNb
CpuModel = result.group('model')
logging.debug('model: ' + CpuModel)
- HTML.SetCpuModel(CpuModel, idx)
+ HTML.CpuModel[idx]=CpuModel
CpuMHz = result.group('cpu_mhz') + ' MHz'
logging.debug('cpu_mhz: ' + CpuMHz)
- HTML.SetCpuMHz(CpuMHz, idx)
+ HTML.CpuMHz[idx]=CpuMHz
SSH.close()
-#-----------------------------------------------------------
-# ShowTestID()
-#-----------------------------------------------------------
def ShowTestID(self):
logging.debug('\u001B[1m----------------------------------------\u001B[0m')
logging.debug('\u001B[1mTest ID:' + self.testCase_id + '\u001B[0m')
logging.debug('\u001B[1m' + self.desc + '\u001B[0m')
logging.debug('\u001B[1m----------------------------------------\u001B[0m')
-def CheckClassValidity(action,id):
- if action != 'Build_eNB' and action != 'WaitEndBuild_eNB' and action != 'Initialize_eNB' and action != 'Terminate_eNB' and action != 'Initialize_UE' and action != 'Terminate_UE' and action != 'Attach_UE' and action != 'Detach_UE' and action != 'Build_OAI_UE' and action != 'Initialize_OAI_UE' and action != 'Terminate_OAI_UE' and action != 'DataDisable_UE' and action != 'DataEnable_UE' and action != 'CheckStatusUE' and action != 'Ping' and action != 'Iperf' and action != 'Reboot_UE' and action != 'Initialize_FlexranCtrl' and action != 'Terminate_FlexranCtrl' and action != 'Initialize_HSS' and action != 'Terminate_HSS' and action != 'Initialize_MME' and action != 'Terminate_MME' and action != 'Initialize_SPGW' and action != 'Terminate_SPGW' and action != 'Initialize_CatM_module' and action != 'Terminate_CatM_module' and action != 'Attach_CatM_module' and action != 'Detach_CatM_module' and action != 'Ping_CatM_module' and action != 'IdleSleep' and action != 'Perform_X2_Handover':
- logging.debug('ERROR: test-case ' + id + ' has wrong class ' + action)
- return False
- return True
+
+
+#-----------------------------------------------------------
+# General Functions
+#-----------------------------------------------------------
+
+
+
+def CheckClassValidity(xml_class_list,action,id):
+ if action not in xml_class_list:
+ logging.debug('ERROR: test-case ' + id + ' has unlisted class ' + action + ' ##CHECK xml_class_list.yml')
+ resp=False
+ else:
+ resp=True
+ return resp
+
+
+#assigning parameters to object instance attributes (even if the attributes do not exist !!)
+def AssignParams(params_dict):
+
+ for key,value in params_dict.items():
+ setattr(CiTestObj, key, value)
+ setattr(RAN, key, value)
+ setattr(HTML, key, value)
+ setattr(ldpc, key, value)
+
+
def GetParametersFromXML(action):
if action == 'Build_eNB':
- RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args'))
+ RAN.Build_eNB_args=test.findtext('Build_eNB_args')
forced_workspace_cleanup = test.findtext('forced_workspace_cleanup')
if (forced_workspace_cleanup is None):
- RAN.SetBuild_eNB_forced_workspace_cleanup(False)
+ RAN.Build_eNB_forced_workspace_cleanup=False
else:
if re.match('true', forced_workspace_cleanup, re.IGNORECASE):
- RAN.SetBuild_eNB_forced_workspace_cleanup(True)
+ RAN.Build_eNB_forced_workspace_cleanup=True
else:
- RAN.SetBuild_eNB_forced_workspace_cleanup(False)
- RAN.SeteNB_instance(test.findtext('eNB_instance'))
- if (RAN.GeteNB_instance() is None):
- RAN.SeteNB_instance('0')
- RAN.SeteNB_serverId(test.findtext('eNB_serverId'))
- if (RAN.GeteNB_serverId() is None):
- RAN.SeteNB_serverId('0')
+ RAN.Build_eNB_forced_workspace_cleanup=False
+ eNB_instance=test.findtext('eNB_instance')
+ if (eNB_instance is None):
+ RAN.eNB_instance=0
+ else:
+ RAN.eNB_instance=int(eNB_instance)
+ RAN.eNB_serverId=test.findtext('eNB_serverId')
+ if (RAN.eNB_serverId is None):
+ RAN.eNB_serverId='0'
xmlBgBuildField = test.findtext('backgroundBuild')
if (xmlBgBuildField is None):
- RAN.SetbackgroundBuild(False)
+ RAN.backgroundBuild=False
else:
if re.match('true', xmlBgBuildField, re.IGNORECASE):
- RAN.SetbackgroundBuild(True)
+ RAN.backgroundBuild=True
else:
- RAN.SetbackgroundBuild(False)
+ RAN.backgroundBuild=False
if action == 'WaitEndBuild_eNB':
- RAN.SetBuild_eNB_args(test.findtext('Build_eNB_args'))
- RAN.SeteNB_instance(test.findtext('eNB_instance'))
- if (RAN.GeteNB_instance() is None):
- RAN.SeteNB_instance('0')
- RAN.SeteNB_serverId(test.findtext('eNB_serverId'))
- if (RAN.GeteNB_serverId() is None):
- RAN.SeteNB_serverId('0')
+ RAN.Build_eNB_args=test.findtext('Build_eNB_args')
+ eNB_instance=test.findtext('eNB_instance')
+ if (eNB_instance is None):
+ RAN.eNB_instance=0
+ else:
+ RAN.eNB_instance=int(eNB_instance)
+ RAN.eNB_serverId=test.findtext('eNB_serverId')
+ if (RAN.eNB_serverId is None):
+ RAN.eNB_serverId='0'
if action == 'Initialize_eNB':
- RAN.SetInitialize_eNB_args(test.findtext('Initialize_eNB_args'))
- RAN.SeteNB_instance(test.findtext('eNB_instance'))
- if (RAN.GeteNB_instance() is None):
- RAN.SeteNB_instance('0')
- RAN.SeteNB_serverId(test.findtext('eNB_serverId'))
- if (RAN.GeteNB_serverId() is None):
- RAN.SeteNB_serverId('0')
- CiTestObj.air_interface = test.findtext('air_interface')
- if (CiTestObj.air_interface is None):
- CiTestObj.air_interface = 'lte'
+ RAN.Initialize_eNB_args=test.findtext('Initialize_eNB_args')
+ eNB_instance=test.findtext('eNB_instance')
+ if (eNB_instance is None):
+ RAN.eNB_instance=0
else:
- CiTestObj.air_interface = CiTestObj.air_interface.lower()
- RAN.Setair_interface(CiTestObj.air_interface)
+ RAN.eNB_instance=int(eNB_instance)
+ RAN.eNB_serverId=test.findtext('eNB_serverId')
+ if (RAN.eNB_serverId is None):
+ RAN.eNB_serverId='0'
+
+ #local variable air_interface
+ air_interface = test.findtext('air_interface')
+ if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']):
+ RAN.air_interface[RAN.eNB_instance] = 'lte-softmodem'
+ elif (air_interface.lower() in ['nr','lte']):
+ RAN.air_interface[RAN.eNB_instance] = air_interface.lower() +'-softmodem'
+ else :
+ RAN.air_interface[RAN.eNB_instance] = 'ocp-enb'
if action == 'Terminate_eNB':
- RAN.SeteNB_instance(test.findtext('eNB_instance'))
- if (RAN.GeteNB_instance() is None):
- RAN.SeteNB_instance('0')
- RAN.SeteNB_serverId(test.findtext('eNB_serverId'))
- if (RAN.GeteNB_serverId() is None):
- RAN.SeteNB_serverId('0')
- CiTestObj.air_interface = test.findtext('air_interface')
- if (CiTestObj.air_interface is None):
- CiTestObj.air_interface = 'lte'
+ eNB_instance=test.findtext('eNB_instance')
+ if (eNB_instance is None):
+ RAN.eNB_instance=0
else:
- CiTestObj.air_interface = CiTestObj.air_interface.lower()
- RAN.Setair_interface(CiTestObj.air_interface)
+ RAN.eNB_instance=int(eNB_instance)
+ RAN.eNB_serverId=test.findtext('eNB_serverId')
+ if (RAN.eNB_serverId is None):
+ RAN.eNB_serverId='0'
+
+ #local variable air_interface
+ air_interface = test.findtext('air_interface')
+ if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']):
+ RAN.air_interface[RAN.eNB_instance] = 'lte-softmodem'
+ elif (air_interface.lower() in ['nr','lte']):
+ RAN.air_interface[RAN.eNB_instance] = air_interface.lower() +'-softmodem'
+ else :
+ RAN.air_interface[RAN.eNB_instance] = 'ocp-enb'
if action == 'Attach_UE':
nbMaxUEtoAttach = test.findtext('nbMaxUEtoAttach')
@@ -3119,19 +3207,38 @@ def GetParametersFromXML(action):
if action == 'Initialize_OAI_UE':
CiTestObj.Initialize_OAI_UE_args = test.findtext('Initialize_OAI_UE_args')
- CiTestObj.UE_instance = test.findtext('UE_instance')
- if (CiTestObj.UE_instance is None):
- CiTestObj.UE_instance = '0'
- CiTestObj.air_interface = test.findtext('air_interface')
- if (CiTestObj.air_interface is None):
- CiTestObj.air_interface = 'lte'
+ UE_instance = test.findtext('UE_instance')
+ if (UE_instance is None):
+ CiTestObj.UE_instance = 0
else:
- CiTestObj.air_interface = CiTestObj.air_interface.lower()
+ CiTestObj.UE_instance = UE_instance
+
+ #local variable air_interface
+ air_interface = test.findtext('air_interface')
+ if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']):
+ CiTestObj.air_interface = 'lte-uesoftmodem'
+ elif (air_interface.lower() in ['nr','lte']):
+ CiTestObj.air_interface = air_interface.lower() +'-uesoftmodem'
+ else :
+ #CiTestObj.air_interface = 'ocp-enb'
+ logging.error('OCP UE -- NOT SUPPORTED')
if action == 'Terminate_OAI_UE':
- RAN.SeteNB_instance(test.findtext('UE_instance'))
- if (CiTestObj.UE_instance is None):
+ UE_instance=test.findtext('UE_instance')
+ if (UE_instance is None):
CiTestObj.UE_instance = '0'
+ else:
+ CiTestObj.UE_instance = int(UE_instance)
+
+ #local variable air_interface
+ air_interface = test.findtext('air_interface')
+ if (air_interface is None) or (air_interface.lower() not in ['nr','lte','ocp']):
+ CiTestObj.air_interface = 'lte-uesoftmodem'
+ elif (air_interface.lower() in ['nr','lte']):
+ CiTestObj.air_interface = air_interface.lower() +'-uesoftmodem'
+ else :
+ #CiTestObj.air_interface = 'ocp-enb'
+ logging.error('OCP UE -- NOT SUPPORTED')
if action == 'Ping' or action == 'Ping_CatM_module':
CiTestObj.ping_args = test.findtext('ping_args')
@@ -3173,6 +3280,22 @@ def GetParametersFromXML(action):
else:
CiTestObj.x2_ho_options = string_field
+ if action == 'Build_PhySim':
+ ldpc.buildargs = test.findtext('physim_build_args')
+ forced_workspace_cleanup = test.findtext('forced_workspace_cleanup')
+ if (forced_workspace_cleanup is None):
+ ldpc.forced_workspace_cleanup=False
+ else:
+ if re.match('true', forced_workspace_cleanup, re.IGNORECASE):
+ ldpc.forced_workspace_cleanup=True
+ else:
+ ldpc.forced_workspace_cleanup=False
+
+ if action == 'Run_PhySim':
+ ldpc.runargs = test.findtext('physim_run_args')
+
+ if action == 'COTS_UE_Airplane':
+ COTS_UE.runargs = test.findtext('cots_ue_airplane_args')
#check if given test is in list
#it is in list if one of the strings in 'list' is at the beginning of 'test'
@@ -3186,192 +3309,88 @@ def test_in_list(test, list):
def receive_signal(signum, frame):
sys.exit(1)
+
+
+
+
+
#-----------------------------------------------------------
-# Parameter Check
+# MAIN PART
#-----------------------------------------------------------
+
+#loading xml action list from yaml
+import yaml
+xml_class_list_file=''
+if (os.path.isfile('xml_class_list.yml')):
+ xml_class_list_file='xml_class_list.yml'
+if (os.path.isfile('ci-scripts/xml_class_list.yml')):
+ xml_class_list_file='ci-scripts/xml_class_list.yml'
+with open(xml_class_list_file,'r') as file:
+ # The FullLoader parameter handles the conversion from YAML
+ # scalar values to Python the dictionary format
+ xml_class_list = yaml.load(file,Loader=yaml.FullLoader)
+
mode = ''
-CiTestObj = OaiCiTest()
-import sshconnection
-import epc
-import helpreadme as HELP
-import ran
-import html
-import constants
+CiTestObj = OaiCiTest()
SSH = sshconnection.SSHConnection()
EPC = epc.EPCManagement()
RAN = ran.RANManagement()
HTML = html.HTMLManagement()
-EPC.SetHtmlObj(HTML)
-RAN.SetHtmlObj(HTML)
-RAN.SetEpcObj(EPC)
+EPC.htmlObj=HTML
+RAN.htmlObj=HTML
+RAN.epcObj=EPC
-argvs = sys.argv
-argc = len(argvs)
-cwd = os.getcwd()
-while len(argvs) > 1:
- myArgv = argvs.pop(1) # 0th is this file's name
+ldpc=cls_physim.PhySim() #create an instance for LDPC test using GPU or CPU build
- if re.match('^\-\-help$', myArgv, re.IGNORECASE):
- HELP.GenericHelp(CONST.Version)
- sys.exit(0)
- elif re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-mode=(.+)$', myArgv, re.IGNORECASE)
- mode = matchReg.group(1)
- elif re.match('^\-\-eNBRepository=(.+)$|^\-\-ranRepository(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBRepository=(.+)$', myArgv, re.IGNORECASE)
- else:
- matchReg = re.match('^\-\-ranRepository=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.ranRepository = matchReg.group(1)
- RAN.SetranRepository(matchReg.group(1))
- HTML.SetranRepository(matchReg.group(1))
- elif re.match('^\-\-eNB_AllowMerge=(.+)$|^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB_AllowMerge=(.+)$', myArgv, re.IGNORECASE)
- else:
- matchReg = re.match('^\-\-ranAllowMerge=(.+)$', myArgv, re.IGNORECASE)
- doMerge = matchReg.group(1)
- if ((doMerge == 'true') or (doMerge == 'True')):
- CiTestObj.ranAllowMerge = True
- RAN.SetranAllowMerge(True)
- HTML.SetranAllowMerge(True)
- elif re.match('^\-\-eNBBranch=(.+)$|^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBBranch=(.+)$', myArgv, re.IGNORECASE)
- else:
- matchReg = re.match('^\-\-ranBranch=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.ranBranch = matchReg.group(1)
- RAN.SetranBranch(matchReg.group(1))
- HTML.SetranBranch(matchReg.group(1))
- elif re.match('^\-\-eNBCommitID=(.*)$|^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBCommitID=(.*)$', myArgv, re.IGNORECASE)
- else:
- matchReg = re.match('^\-\-ranCommitID=(.*)$', myArgv, re.IGNORECASE)
- CiTestObj.ranCommitID = matchReg.group(1)
- RAN.SetranCommitID(matchReg.group(1))
- HTML.SetranCommitID(matchReg.group(1))
- elif re.match('^\-\-eNBTargetBranch=(.*)$|^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBTargetBranch=(.*)$', myArgv, re.IGNORECASE)
- else:
- matchReg = re.match('^\-\-ranTargetBranch=(.*)$', myArgv, re.IGNORECASE)
- CiTestObj.ranTargetBranch = matchReg.group(1)
- RAN.SetranTargetBranch(matchReg.group(1))
- HTML.SetranTargetBranch(matchReg.group(1))
- elif re.match('^\-\-eNBIPAddress=(.+)$|^\-\-eNB[1-2]IPAddress=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBIPAddress=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNBIPAddress(matchReg.group(1))
- elif re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB1IPAddress=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB1IPAddress(matchReg.group(1))
- elif re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB2IPAddress=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB2IPAddress(matchReg.group(1))
- elif re.match('^\-\-eNBUserName=(.+)$|^\-\-eNB[1-2]UserName=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBUserName=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNBUserName(matchReg.group(1))
- elif re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB1UserName=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB1UserName(matchReg.group(1))
- elif re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB2UserName=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB2UserName(matchReg.group(1))
- elif re.match('^\-\-eNBPassword=(.+)$|^\-\-eNB[1-2]Password=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBPassword=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNBPassword(matchReg.group(1))
- elif re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB1Password=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB1Password(matchReg.group(1))
- elif re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB2Password=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB2Password(matchReg.group(1))
- elif re.match('^\-\-eNBSourceCodePath=(.+)$|^\-\-eNB[1-2]SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- if re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNBSourceCodePath=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNBSourceCodePath(matchReg.group(1))
- elif re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB1SourceCodePath=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB1SourceCodePath(matchReg.group(1))
- elif re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-eNB2SourceCodePath=(.+)$', myArgv, re.IGNORECASE)
- RAN.SeteNB2SourceCodePath(matchReg.group(1))
- elif re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-EPCIPAddress=(.+)$', myArgv, re.IGNORECASE)
- EPC.SetIPAddress(matchReg.group(1))
- elif re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-EPCUserName=(.+)$', myArgv, re.IGNORECASE)
- EPC.SetUserName(matchReg.group(1))
- elif re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-EPCPassword=(.+)$', myArgv, re.IGNORECASE)
- EPC.SetPassword(matchReg.group(1))
- elif re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-EPCSourceCodePath=(.+)$', myArgv, re.IGNORECASE)
- EPC.SetSourceCodePath(matchReg.group(1))
- elif re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-EPCType=(.+)$', myArgv, re.IGNORECASE)
- if re.match('OAI', matchReg.group(1), re.IGNORECASE) or re.match('ltebox', matchReg.group(1), re.IGNORECASE) or re.match('OAI-Rel14-CUPS', matchReg.group(1), re.IGNORECASE):
- EPC.SetType(matchReg.group(1))
- else:
- sys.exit('Invalid EPC Type: ' + matchReg.group(1) + ' -- (should be OAI or ltebox or OAI-Rel14-CUPS)')
- elif re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-ADBIPAddress=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.ADBIPAddress = matchReg.group(1)
- elif re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-ADBUserName=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.ADBUserName = matchReg.group(1)
- elif re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-ADBType=(.+)$', myArgv, re.IGNORECASE)
- if re.match('centralized', matchReg.group(1), re.IGNORECASE) or re.match('distributed', matchReg.group(1), re.IGNORECASE):
- if re.match('distributed', matchReg.group(1), re.IGNORECASE):
- CiTestObj.ADBCentralized = False
- else:
- CiTestObj.ADBCentralized = True
- else:
- sys.exit('Invalid ADB Type: ' + matchReg.group(1) + ' -- (should be centralized or distributed)')
- elif re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-ADBPassword=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.ADBPassword = matchReg.group(1)
- elif re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-XMLTestFile=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.testXMLfiles.append(matchReg.group(1))
- HTML.SettestXMLfiles(matchReg.group(1))
- HTML.SetnbTestXMLfiles(HTML.GetnbTestXMLfiles()+1)
- elif re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-UEIPAddress=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.UEIPAddress = matchReg.group(1)
- elif re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-UEUserName=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.UEUserName = matchReg.group(1)
- elif re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-UEPassword=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.UEPassword = matchReg.group(1)
- elif re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-UESourceCodePath=(.+)$', myArgv, re.IGNORECASE)
- CiTestObj.UESourceCodePath = matchReg.group(1)
- elif re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE):
- matchReg = re.match('^\-\-finalStatus=(.+)$', myArgv, re.IGNORECASE)
- finalStatus = matchReg.group(1)
- if ((finalStatus == 'true') or (finalStatus == 'True')):
- CiTestObj.finalStatus = True
- else:
- HELP.GenericHelp(CONST.Version)
- sys.exit('Invalid Parameter: ' + myArgv)
+
+
+#-----------------------------------------------------------
+# Parsing Command Line Arguments
+#-----------------------------------------------------------
+
+import args_parse
+py_param_file_present, py_params, mode = args_parse.ArgsParse(sys.argv,CiTestObj,RAN,HTML,EPC,ldpc,HELP)
+
+
+
+#-----------------------------------------------------------
+# TEMPORARY params management
+#-----------------------------------------------------------
+#temporary solution for testing:
+if py_param_file_present == True:
+ AssignParams(py_params)
+
+#for debug
+#print(RAN.__dict__)
+#print(CiTestObj.__dict__)
+#print(HTML.__dict__)
+#print(ldpc.__dict__)
+#for debug
+
+
+#-----------------------------------------------------------
+# COTS UE instanciation
+#-----------------------------------------------------------
+#COTS_UE instanciation can only be done here for the moment, due to code architecture
+COTS_UE=cls_cots_ue.CotsUe('oppo', CiTestObj.UEIPAddress, CiTestObj.UEUserName,CiTestObj.UEPassword)
+
+
+#-----------------------------------------------------------
+# XML class (action) analysis
+#-----------------------------------------------------------
+cwd = os.getcwd()
if re.match('^TerminateeNB$', mode, re.IGNORECASE):
- if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '':
+ if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
- RAN.SeteNB_serverId('0')
- RAN.SeteNB_instance('0')
- RAN.SeteNBSourceCodePath('/tmp/')
+ RAN.eNB_serverId='0'
+ RAN.eNB_instance=0
+ RAN.eNBSourceCodePath='/tmp/'
RAN.TerminateeNB()
elif re.match('^TerminateUE$', mode, re.IGNORECASE):
if (CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == ''):
@@ -3386,52 +3405,52 @@ elif re.match('^TerminateOAIUE$', mode, re.IGNORECASE):
signal.signal(signal.SIGUSR1, receive_signal)
CiTestObj.TerminateOAIUE()
elif re.match('^TerminateHSS$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.TerminateHSS()
elif re.match('^TerminateMME$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.TerminateMME()
elif re.match('^TerminateSPGW$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath== '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.TerminateSPGW()
elif re.match('^LogCollectBuild$', mode, re.IGNORECASE):
- if (RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '') and (CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == ''):
+ if (RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '') and (CiTestObj.UEIPAddress == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == ''):
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
CiTestObj.LogCollectBuild()
elif re.match('^LogCollecteNB$', mode, re.IGNORECASE):
- if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '':
+ if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
RAN.LogCollecteNB()
elif re.match('^LogCollectHSS$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.LogCollectHSS()
elif re.match('^LogCollectMME$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.LogCollectMME()
elif re.match('^LogCollectSPGW$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
EPC.LogCollectSPGW()
elif re.match('^LogCollectPing$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
CiTestObj.LogCollectPing()
elif re.match('^LogCollectIperf$', mode, re.IGNORECASE):
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '':
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '':
HELP.GenericHelp(CONST.Version)
sys.exit('Insufficient Parameter')
CiTestObj.LogCollectIperf()
@@ -3446,7 +3465,7 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE):
sys.exit('Insufficient Parameter')
count = 0
foundCount = 0
- while (count < HTML.GetnbTestXMLfiles()):
+ while (count < HTML.nbTestXMLfiles):
#xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[count]
xml_test_file = sys.path[0] + "/" + CiTestObj.testXMLfiles[count]
if (os.path.isfile(xml_test_file)):
@@ -3455,21 +3474,21 @@ elif re.match('^InitiateHtml$', mode, re.IGNORECASE):
except:
print("Error while parsing file: " + xml_test_file)
xmlRoot = xmlTree.getroot()
- HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count)))
- HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='test-tab-' + str(count)))
- HTML.SethtmlTabIcons(xmlRoot.findtext('htmlTabIcon',default='info-sign'))
+ HTML.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-' + str(count)))
+ HTML.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='test-tab-' + str(count)))
+ HTML.htmlTabIcons.append(xmlRoot.findtext('htmlTabIcon',default='info-sign'))
foundCount += 1
count += 1
- if foundCount != HTML.GetnbTestXMLfiles():
- HTML.SetnbTestXMLfiles(foundcount)
+ if foundCount != HTML.nbTestXMLfiles:
+ HTML.nbTestXMLfiles=foundCount
if (CiTestObj.ADBIPAddress != 'none'):
terminate_ue_flag = False
CiTestObj.GetAllUEDevices(terminate_ue_flag)
CiTestObj.GetAllCatMDevices(terminate_ue_flag)
HTML.SethtmlUEConnected(len(CiTestObj.UEDevices) + len(CiTestObj.CatMDevices))
- HTML.SethtmlNb_Smartphones(len(CiTestObj.UEDevices))
- HTML.SethtmlNb_CATM_Modules(len(CiTestObj.CatMDevices))
+ HTML.htmlNb_Smartphones=len(CiTestObj.UEDevices)
+ HTML.htmlNb_CATM_Modules=len(CiTestObj.CatMDevices)
HTML.CreateHtmlHeader(CiTestObj.ADBIPAddress)
elif re.match('^FinalizeHtml$', mode, re.IGNORECASE):
logging.debug('\u001B[1m----------------------------------------\u001B[0m')
@@ -3481,19 +3500,19 @@ elif re.match('^FinalizeHtml$', mode, re.IGNORECASE):
HTML.CreateHtmlFooter(CiTestObj.finalStatus)
elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re.IGNORECASE):
if re.match('^TesteNB$', mode, re.IGNORECASE):
- if RAN.GeteNBIPAddress() == '' or RAN.GetranRepository() == '' or RAN.GetranBranch() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '' or EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetType() == '' or EPC.GetSourceCodePath() == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '':
+ if RAN.eNBIPAddress == '' or RAN.ranRepository == '' or RAN.ranBranch == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '' or EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.Type == '' or EPC.SourceCodePath == '' or CiTestObj.ADBIPAddress == '' or CiTestObj.ADBUserName == '' or CiTestObj.ADBPassword == '':
HELP.GenericHelp(CONST.Version)
- if EPC.GetIPAddress() == '' or EPC.GetUserName() == '' or EPC.GetPassword() == '' or EPC.GetSourceCodePath() == '' or EPC.GetType() == '':
- HELP.EPCSrvHelp(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), EPC.GetSourceCodePath(), EPC.GetType())
- if RAN.GetranRepository() == '':
- HELP.GitSrvHelp(RAN.GetranRepository(), RAN.GetranBranch(), RAN.GetranCommitID(), RAN.GetranAllowMerge(), RAN.GetranTargetBranch())
- if RAN.GeteNBIPAddress() == '' or RAN.GeteNBUserName() == '' or RAN.GeteNBPassword() == '' or RAN.GeteNBSourceCodePath() == '':
- HELP.eNBSrvHelp(RAN.GeteNBIPAddress(), RAN.GeteNBUserName(), RAN.GeteNBPassword(), RAN.GeteNBSourceCodePath())
+ if EPC.IPAddress == '' or EPC.UserName == '' or EPC.Password == '' or EPC.SourceCodePath == '' or EPC.Type == '':
+ HELP.EPCSrvHelp(EPC.IPAddress, EPC.UserName, EPC.Password, EPC.SourceCodePath, EPC.Type)
+ if RAN.ranRepository == '':
+ HELP.GitSrvHelp(RAN.ranRepository, RAN.ranBranch, RAN.ranCommitID, RAN.ranAllowMerge, RAN.ranTargetBranch)
+ if RAN.eNBIPAddress == '' or RAN.eNBUserName == '' or RAN.eNBPassword == '' or RAN.eNBSourceCodePath == '':
+ HELP.eNBSrvHelp(RAN.eNBIPAddress, RAN.eNBUserName, RAN.eNBPassword, RAN.eNBSourceCodePath)
sys.exit('Insufficient Parameter')
- if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'):
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/tcp_iperf_stats.awk", "/tmp")
- SSH.copyout(EPC.GetIPAddress(), EPC.GetUserName(), EPC.GetPassword(), cwd + "/active_net_interfaces.awk", "/tmp")
+ if (EPC.IPAddress!= '') and (EPC.IPAddress != 'none'):
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, cwd + "/tcp_iperf_stats.awk", "/tmp")
+ SSH.copyout(EPC.IPAddress, EPC.UserName, EPC.Password, cwd + "/active_net_interfaces.awk", "/tmp")
else:
if CiTestObj.UEIPAddress == '' or CiTestObj.ranRepository == '' or CiTestObj.ranBranch == '' or CiTestObj.UEUserName == '' or CiTestObj.UEPassword == '' or CiTestObj.UESourceCodePath == '':
HELP.GenericHelp(CONST.Version)
@@ -3501,7 +3520,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
#read test_case_list.xml file
# if no parameters for XML file, use default value
- if (HTML.GetnbTestXMLfiles() != 1):
+ if (HTML.nbTestXMLfiles != 1):
xml_test_file = cwd + "/test_case_list.xml"
else:
xml_test_file = cwd + "/" + CiTestObj.testXMLfiles[0]
@@ -3511,9 +3530,9 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
exclusion_tests=xmlRoot.findtext('TestCaseExclusionList',default='')
requested_tests=xmlRoot.findtext('TestCaseRequestedList',default='')
- if (HTML.GetnbTestXMLfiles() == 1):
- HTML.SethtmlTabRefs(xmlRoot.findtext('htmlTabRef',default='test-tab-0'))
- HTML.SethtmlTabNames(xmlRoot.findtext('htmlTabName',default='Test-0'))
+ if (HTML.nbTestXMLfiles == 1):
+ HTML.htmlTabRefs.append(xmlRoot.findtext('htmlTabRef',default='test-tab-0'))
+ HTML.htmlTabNames.append(xmlRoot.findtext('htmlTabName',default='Test-0'))
repeatCount = xmlRoot.findtext('repeatCount',default='1')
CiTestObj.repeatCounts.append(int(repeatCount))
all_tests=xmlRoot.findall('testCase')
@@ -3541,8 +3560,9 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
else:
logging.debug('ERROR: requested test is invalidly formatted: ' + test)
sys.exit(1)
- if (EPC.GetIPAddress() != '') and (EPC.GetIPAddress() != 'none'):
+ if (EPC.IPAddress != '') and (EPC.IPAddress != 'none'):
CiTestObj.CheckFlexranCtrlInstallation()
+ EPC.SetMmeIPAddress()
#get the list of tests to be done
todo_tests=[]
@@ -3565,28 +3585,29 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
HTML.CreateHtmlTabHeader()
CiTestObj.FailReportCnt = 0
- RAN.SetprematureExit(True)
- HTML.SetstartTime(int(round(time.time() * 1000)))
- while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.GetprematureExit():
- RAN.SetprematureExit(False)
+ RAN.prematureExit=True
+ HTML.startTime=int(round(time.time() * 1000))
+ while CiTestObj.FailReportCnt < CiTestObj.repeatCounts[0] and RAN.prematureExit:
+ RAN.prematureExit=False
# At every iteratin of the retry loop, a separator will be added
# pass CiTestObj.FailReportCnt as parameter of HTML.CreateHtmlRetrySeparator
HTML.CreateHtmlRetrySeparator(CiTestObj.FailReportCnt)
for test_case_id in todo_tests:
- if RAN.GetprematureExit():
+ if RAN.prematureExit:
break
for test in all_tests:
- if RAN.GetprematureExit():
+ if RAN.prematureExit:
break
id = test.get('id')
if test_case_id != id:
continue
CiTestObj.testCase_id = id
- HTML.SettestCase_id(CiTestObj.testCase_id)
+ HTML.testCase_id=CiTestObj.testCase_id
+ EPC.testCase_id=CiTestObj.testCase_id
CiTestObj.desc = test.findtext('desc')
- HTML.Setdesc(CiTestObj.desc)
+ HTML.desc=CiTestObj.desc
action = test.findtext('class')
- if (CheckClassValidity(action, id) == False):
+ if (CheckClassValidity(xml_class_list, action, id) == False):
continue
CiTestObj.ShowTestID()
GetParametersFromXML(action)
@@ -3601,7 +3622,7 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
elif action == 'Initialize_eNB':
check_eNB = False
check_OAI_UE = False
- RAN.SetpStatus(CiTestObj.CheckProcessExist(check_eNB, check_OAI_UE))
+ RAN.pStatus=CiTestObj.CheckProcessExist(check_eNB, check_OAI_UE)
RAN.InitializeeNB()
elif action == 'Terminate_eNB':
@@ -3662,16 +3683,25 @@ elif re.match('^TesteNB$', mode, re.IGNORECASE) or re.match('^TestUE$', mode, re
CiTestObj.IdleSleep()
elif action == 'Perform_X2_Handover':
CiTestObj.Perform_X2_Handover()
+ elif action == 'Build_PhySim':
+ HTML=ldpc.Build_PhySim(HTML,CONST)
+ if ldpc.exitStatus==1:sys.exit()
+ elif action == 'Run_PhySim':
+ HTML=ldpc.Run_PhySim(HTML,CONST,id)
+ elif action == 'COTS_UE_Airplane':
+ COTS_UE.Set_Airplane(COTS_UE.runargs)
else:
- sys.exit('Invalid action')
+ sys.exit('Invalid class (action) from xml')
CiTestObj.FailReportCnt += 1
- if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.GetprematureExit():
+ if CiTestObj.FailReportCnt == CiTestObj.repeatCounts[0] and RAN.prematureExit:
logging.debug('Testsuite failed ' + str(CiTestObj.FailReportCnt) + ' time(s)')
HTML.CreateHtmlTabFooter(False)
sys.exit('Failed Scenario')
else:
logging.info('Testsuite passed after ' + str(CiTestObj.FailReportCnt) + ' time(s)')
HTML.CreateHtmlTabFooter(True)
+elif re.match('^LoadParams$', mode, re.IGNORECASE):
+ pass
else:
HELP.GenericHelp(CONST.Version)
sys.exit('Invalid mode')
diff --git a/ci-scripts/oai-ci-vm-tool b/ci-scripts/oai-ci-vm-tool
index 9d6349077f00288301e1fc6d510f50d674abc695..9b9fe462f15d07200b316cedb3b8273451b91807 100755
--- a/ci-scripts/oai-ci-vm-tool
+++ b/ci-scripts/oai-ci-vm-tool
@@ -186,7 +186,7 @@ function variant__v3__phy_sim {
BUILD_OPTIONS="--phy_simulators"
VM_MEMORY=8192
VM_DISK=20
- RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111\" -q -np -b"
+ RUN_OPTIONS="./run_exec_autotests.bash -g \"01510* 015111 015112\" -q -np -b"
}
function variant__v4__cppcheck {
@@ -197,7 +197,7 @@ function variant__v4__cppcheck {
}
function variant__v5__gnb_usrp {
- VM_MEMORY=8192
+ VM_MEMORY=10240
VM_CPU=8
NB_PATTERN_FILES=9
BUILD_OPTIONS="--gNB -w USRP"
diff --git a/ci-scripts/py_params.yaml b/ci-scripts/py_params.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..303d5d100660b8d2608a67f58e4950690882ffb8
--- /dev/null
+++ b/ci-scripts/py_params.yaml
@@ -0,0 +1,53 @@
+eNBRepository : b
+ranRepository : c
+eNB_AllowMerge :
+ranAllowMerge :
+eNBBranch : f
+ranBranch : g
+eNBCommitID :
+ranCommitID : i
+eNBTargetBranch : j
+ranTargetBranch : k
+
+nodes :
+ - type : eNB
+ IPAddress : 001.1.1
+ UserName : toto
+ Password : qwe
+ SourceCodePath : l
+ - type : gNB
+ IPAddress : 002.2.2
+ UserName : tata
+ Password : asd
+ SourceCodePath : m
+ - type : eNB
+ IPAddress : 003.3.3
+ UserName : titi
+ Password : zxc
+ SourceCodePath : n
+ - type : gNB
+ IPAddress : 004.4.4
+ UserName : caca
+ Password : pepe
+ SourceCodePath : o
+
+EPCIPAddress : p
+EPCUserName : q
+EPCPassword : r
+EPCSourceCodePath : s
+EPCType : t
+EPCContainerPrefix : u
+
+ADBIPAddress : v
+ADBUserName : w
+ADBType : x
+ADBPassword : y
+
+XMLTestFile : z
+
+UEIPAddress : qqq
+UEUserName : www
+UEPassword : eee
+UESourceCodePath : yyy
+
+finalStatus : bbb
\ No newline at end of file
diff --git a/ci-scripts/py_params_template.yaml b/ci-scripts/py_params_template.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..aaf31c1576527dc08985a37dfe1dd2b97eca8d64
--- /dev/null
+++ b/ci-scripts/py_params_template.yaml
@@ -0,0 +1,97 @@
+eNBRepository : b
+ranRepository : c
+eNB_AllowMerge :
+ranAllowMerge :
+eNBBranch : f
+ranBranch : g
+eNBCommitID :
+ranCommitID : i
+eNBTargetBranch : j
+ranTargetBranch : k
+
+
+RAN:
+ RAN_inst_0:
+ name : RAN_1
+ nodes :
+ - type : eNB
+ IPAddress : 001.1.1
+ UserName : toto
+ Password : qwe
+ SourceCodePath : l
+ - type : gNB
+ IPAddress : 002.2.2
+ UserName : tata
+ Password : asd
+ SourceCodePath : m
+ - type : eNB
+ IPAddress : 003.3.3
+ UserName : titi
+ Password : zxc
+ SourceCodePath : n
+ - type : gNB
+ IPAddress : 004.4.4
+ UserName : caca
+ Password : pepe
+ SourceCodePath : o
+ RAN_inst_1:
+ name : RAN_2
+ nodes :
+ - type : eNB
+ IPAddress : 101.1.1
+ UserName : toto
+ Password : qwe
+ SourceCodePath : l
+ - type : gNB
+ IPAddress : 102.2.2
+ UserName : zaza
+ Password : asd
+ SourceCodePath : m
+ - type : eNB
+ IPAddress : 103.3.3
+ UserName : zizi
+ Password : zxc
+ SourceCodePath : n
+ - type : gNB
+ IPAddress : 104.4.4
+ UserName : aaaa
+ Password : pepe
+ SourceCodePath : o
+
+
+
+EPC:
+ EPC_inst_0:
+ EPCIPAddress : p
+ EPCUserName : q
+ EPCPassword : r
+ EPCSourceCodePath : s
+ EPCType : t
+ EPCContainerPrefix : u
+
+ADB:
+ ADBIPAddress : v
+ ADBUserName : w
+ ADBType : x
+ ADBPassword : y
+
+
+UE:
+ UE_inst_0:
+ name : UE_1
+ type :
+ UEIPAddress : qqq
+ UEUserName : www
+ UEPassword : eee
+ UESourceCodePath : yyy
+ UE_inst_1:
+ name : UE_2
+ type :
+ UEIPAddress : bloblob
+ UEUserName : gwou
+ UEPassword : zebu
+ UESourceCodePath : pop
+
+
+XMLTestFile : z
+finalStatus : bbb
\ No newline at end of file
diff --git a/ci-scripts/ran.py b/ci-scripts/ran.py
index 350098e66ee20e74a20915f3f72d084742f5acf5..96f28e21fe3f58e19d56510c3fcac22645a2df05 100644
--- a/ci-scripts/ran.py
+++ b/ci-scripts/ran.py
@@ -77,8 +77,8 @@ class RANManagement():
self.backgroundBuildTestId = ['', '', '']
self.Build_eNB_forced_workspace_cleanup = False
self.Initialize_eNB_args = ''
- self.air_interface = 'lte'
- self.eNB_instance = ''
+ self.air_interface = ['', '', ''] #changed from 'lte' to '' may lead to side effects in main
+ self.eNB_instance = 0
self.eNB_serverId = ''
self.eNBLogFiles = ['', '', '']
self.eNBOptions = ['', '', '']
@@ -91,140 +91,7 @@ class RANManagement():
self.htmlObj = None
self.epcObj = None
-#-----------------------------------------------------------
-# Setters and Getters on Public members
-#-----------------------------------------------------------
-
- def SetHtmlObj(self, obj):
- self.htmlObj = obj
- def SetEpcObj(self, obj):
- self.epcObj = obj
-
- def SetflexranCtrlInstalled(self,fxrctin):
- self.flexranCtrlInstalled = fxrctin
- def GetflexranCtrlInstalled(self):
- return self.flexranCtrlInstalled
- def SetflexranCtrlStarted(self,fxrctst):
- self.flexranCtrlStarted = fxrctst
- def GetflexranCtrlStarted(self):
- return self.flexranCtrlStarted
- def SetpStatus(self, pSt):
- self.pStatus = pSt
- def SetranRepository(self, repository):
- self.ranRepository = repository
- def GetranRepository(self):
- return self.ranRepository
- def SetranBranch(self, branch):
- self.ranBranch = branch
- def GetranBranch(self):
- return self.ranBranch
- def SetranCommitID(self, commitid):
- self.ranCommitID = commitid
- def GetranCommitID(self):
- return self.ranCommitID
- def SeteNB_serverId(self, enbsrvid):
- self.eNB_serverId = enbsrvid
- def GeteNB_serverId(self):
- return self.eNB_serverId
- def SeteNBIPAddress(self, enbip):
- self.eNBIPAddress = enbip
- def GeteNBIPAddress(self):
- return self.eNBIPAddress
- def SeteNBUserName(self, enbusr):
- self.eNBUserName = enbusr
- def GeteNBUserName(self):
- return self.eNBUserName
- def SeteNBPassword(self, enbpw):
- self.eNBPassword = enbpw
- def GeteNBPassword(self):
- return self.eNBPassword
- def SeteNBSourceCodePath(self, enbcodepath):
- self.eNBSourceCodePath = enbcodepath
- def GeteNBSourceCodePath(self):
- return self.eNBSourceCodePath
- def SetranAllowMerge(self, merge):
- self.ranAllowMerge = merge
- def GetranAllowMerge(self):
- return self.ranAllowMerge
- def SetranTargetBranch(self, tbranch):
- self.ranTargetBranch = tbranch
- def GetranTargetBranch(self):
- return self.ranTargetBranch
- def SetBuild_eNB_args(self, enbbuildarg):
- self.Build_eNB_args = enbbuildarg
- def GetBuild_eNB_args(self):
- return self.Build_eNB_args
- def SetInitialize_eNB_args(self, initenbarg):
- self.Initialize_eNB_args = initenbarg
- def GetInitialize_eNB_args(self):
- return self.Initialize_eNB_args
- def SetbackgroundBuild(self, bkbuild):
- self.backgroundBuild = bkbuild
- def GetbackgroundBuild(self):
- return self.backgroundBuild
- def SetbackgroundBuildTestId(self, bkbuildid):
- self.backgroundBuildTestId = bkbuildid
- def GetbackgroundBuildTestId(self):
- return self.backgroundBuildTestId
- def SetBuild_eNB_forced_workspace_cleanup(self, fcdwspclean):
- self.Build_eNB_forced_workspace_cleanup = fcdwspclean
- def GetBuild_eNB_forced_workspace_cleanup(self):
- return self.Build_eNB_forced_workspace_cleanup
- def Setair_interface(self, airif):
- self.air_interface = airif
- def Getair_interface(self):
- return self.air_interface
- def SeteNB_instance(self, enbinst):
- self.eNB_instance = enbinst
- def GeteNB_instance(self):
- return self.eNB_instance
-
- def SeteNBLogFile(self, enblog, idx):
- self.eNBLogFiles[idx] = enblog
- def GeteNBLogFile(self, idx):
- return self.eNBLogFiles[idx]
-
- def GeteNBmbmsEnable(self, idx):
- return self.eNBmbmsEnables[idx]
- def SeteNB1IPAddress(self,enb1ip):
- self.eNB1IPAddress = enb1ip
- def GeteNB1IPAddress(self):
- return self.eNB1IPAddress
- def SeteNB1UserName(self, enb1usr):
- self.eNB1UserName = enb1usr
- def GeteNB1UserName(self):
- return self.eNB1UserName
- def SeteNB1Password(self, enb1pw):
- self.eNB1Password = enb1pw
- def GeteNB1Password(self):
- return self.eNB1Password
- def SeteNB1SourceCodePath(self, enb1codepath):
- self.eNB1SourceCodePath = enb1codepath
- def GeteNB1SourceCodePath(self):
- return self.eNB1SourceCodePath
-
- def SeteNB2IPAddress(self, enb2ip):
- self.eNB2IPAddress = enb2ip
- def GeteNB2IPAddress(self):
- return self.eNB2IPAddress
- def SeteNB2UserName(self, enb2usr):
- self.eNB2UserName = enb2usr
- def GeteNB2UserName(self):
- return self.eNB2UserName
- def SeteNB2Password(self, enb2pw):
- self.eNB2Password = enb2pw
- def GeteNB2Password(self):
- return self.eNB2Password
- def SeteNB2SourceCodePath(self, enb2codepath):
- self.eNB2SourceCodePath = enb2codepath
- def GeteNB2SourceCodePath(self):
- return self.eNB2SourceCodePath
-
- def SetprematureExit(self, premex):
- self.prematureExit = premex
- def GetprematureExit(self):
- return self.prematureExit
#-----------------------------------------------------------
# RAN management functions
@@ -254,17 +121,23 @@ class RANManagement():
sys.exit('Insufficient Parameter')
mySSH = SSH.SSHConnection()
mySSH.open(lIpAddr, lUserName, lPassWord)
- # Check if we build an 5G-NR gNB or an LTE eNB
- result = re.search('--gNB', self.Build_eNB_args)
+
+ # Check if we build an 5G-NR gNB or an LTE eNB or an OCP eNB
+ result = re.search('--eNBocp', self.Build_eNB_args)
if result is not None:
- self.air_interface = 'nr'
- else:
- self.air_interface = 'lte'
+ self.air_interface[self.eNB_instance] = 'ocp-enb'
+ else:
+ result = re.search('--gNB', self.Build_eNB_args)
+ if result is not None:
+ self.air_interface[self.eNB_instance] = 'nr-softmodem'
+ else:
+ self.air_interface[self.eNB_instance] = 'lte-softmodem'
+
# Worakround for some servers, we need to erase completely the workspace
if self.Build_eNB_forced_workspace_cleanup:
mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf ' + lSourcePath, '\$', 15)
if self.htmlObj is not None:
- self.testCase_id = self.htmlObj.GettestCase_id()
+ self.testCase_id = self.htmlObj.testCase_id
else:
self.testCase_id = '000000'
# on RedHat/CentOS .git extension is mandatory
@@ -332,7 +205,8 @@ class RANManagement():
if self.backgroundBuild:
mySSH.command('echo "./build_oai ' + self.Build_eNB_args + '" > ./my-lte-softmodem-build.sh', '\$', 5)
mySSH.command('chmod 775 ./my-lte-softmodem-build.sh', '\$', 5)
- mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=build_enb_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ./my-lte-softmodem-build.sh', '\$', 5)
+ mySSH.command('echo ' + lPassWord + ' | sudo -S ls', '\$', 5)
+ mySSH.command('echo $USER; nohup sudo -E ./my-lte-softmodem-build.sh' + ' > ' + lSourcePath + '/cmake_targets/compile_oai_enb.log ' + ' 2>&1 &', lUserName, 5)
mySSH.close()
if self.htmlObj is not None:
self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK)
@@ -366,7 +240,7 @@ class RANManagement():
count = 40
buildOAIprocess = True
while (count > 0) and buildOAIprocess:
- mySSH.command('ps aux | grep --color=never build_ | grep -v grep', '\$', 3)
+ mySSH.command('ps aux | grep --color=never build_ | grep -v grep', '\$', 6)
result = re.search('build_oai', mySSH.getBefore())
if result is None:
buildOAIprocess = False
@@ -378,21 +252,21 @@ class RANManagement():
def checkBuildeNB(self, lIpAddr, lUserName, lPassWord, lSourcePath, testcaseId):
if self.htmlObj is not None:
- self.htmlObj.SettestCase_id(testcaseId)
+ self.htmlObj.testCase_id=testcaseId
+
mySSH = SSH.SSHConnection()
mySSH.open(lIpAddr, lUserName, lPassWord)
mySSH.command('cd ' + lSourcePath + '/cmake_targets', '\$', 3)
mySSH.command('ls ran_build/build', '\$', 3)
mySSH.command('ls ran_build/build', '\$', 3)
- if self.air_interface == 'nr':
- nodeB_prefix = 'g'
- else:
- nodeB_prefix = 'e'
- buildStatus = True
- result = re.search(self.air_interface + '-softmodem', mySSH.getBefore())
+
+ #check if we have the build corresponding to the air interface keywords (nr-softmode, lte-softmodem, ocp-enb)
+ logging.info('CHECK Build with IP='+lIpAddr+' SourcePath='+lSourcePath)
+ result = re.search(self.air_interface[self.eNB_instance], mySSH.getBefore())
if result is None:
- buildStatus = False
+ buildStatus = False #if not, build failed
else:
+ buildStatus = True
# Generating a BUILD INFO file
mySSH.command('echo "SRC_BRANCH: ' + self.ranBranch + '" > ../LAST_BUILD_INFO.txt', '\$', 2)
mySSH.command('echo "SRC_COMMIT: ' + self.ranCommitID + '" >> ../LAST_BUILD_INFO.txt', '\$', 2)
@@ -404,6 +278,8 @@ class RANManagement():
mySSH.command('echo "TGT_BRANCH: ' + self.ranTargetBranch + '" >> ../LAST_BUILD_INFO.txt', '\$', 2)
else:
mySSH.command('echo "MERGED_W_TGT_BRANCH: NO" >> ../LAST_BUILD_INFO.txt', '\$', 2)
+
+
mySSH.command('mkdir -p build_log_' + testcaseId, '\$', 5)
mySSH.command('mv log/* ' + 'build_log_' + testcaseId, '\$', 5)
mySSH.command('mv compile_oai_enb.log ' + 'build_log_' + testcaseId, '\$', 5)
@@ -420,18 +296,20 @@ class RANManagement():
os.remove('./tmp_build' + testcaseId + '.zip')
mySSH.open(self.eNBIPAddress, self.eNBUserName, self.eNBPassword)
mySSH.command('cd ' + self.eNBSourceCodePath + '/cmake_targets', '\$', 5)
- mySSH.command('unzip -qq -DD tmp_build' + testcaseId + '.zip', '\$', 5)
+ #-qq quiet / -u update orcreate files
+ mySSH.command('unzip -u -qq -DD tmp_build' + testcaseId + '.zip', '\$', 5)
mySSH.command('rm -f tmp_build' + testcaseId + '.zip', '\$', 5)
mySSH.close()
else:
mySSH.close()
+ #generate logging info depending on buildStatus and air interface
if buildStatus:
- logging.info('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Pass\u001B[0m')
+ logging.info('\u001B[1m Building OAI ' + self.air_interface[self.eNB_instance] + ' Pass\u001B[0m')
if self.htmlObj is not None:
- self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK)
+ self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'OK', CONST.ALL_PROCESSES_OK)
else:
- logging.error('\u001B[1m Building OAI ' + nodeB_prefix + 'NB Failed\u001B[0m')
+ logging.error('\u001B[1m Building OAI ' + self.air_interface[self.eNB_instance] + ' Failed\u001B[0m')
if self.htmlObj is not None:
self.htmlObj.CreateHtmlTestRow(self.Build_eNB_args, 'KO', CONST.ALL_PROCESSES_OK)
self.htmlObj.CreateHtmlTabFooter(False)
@@ -458,22 +336,22 @@ class RANManagement():
sys.exit('Insufficient Parameter')
if self.htmlObj is not None:
- self.testCase_id = self.htmlObj.GettestCase_id()
+ self.testCase_id = self.htmlObj.testCase_id
else:
self.testCase_id = '000000'
mySSH = SSH.SSHConnection()
if (self.pStatus < 0):
if self.htmlObj is not None:
- self.htmlObj.CreateHtmlTestRow(self.Initialize_eNB_args, 'KO', self.pStatus)
+ self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' ' + self.Initialize_eNB_args, 'KO', self.pStatus)
self.htmlObj.CreateHtmlTabFooter(False)
sys.exit(1)
# If tracer options is on, running tshark on EPC side and capture traffic b/ EPC and eNB
result = re.search('T_stdout', str(self.Initialize_eNB_args))
if (result is not None) and (self.epcObj is not None):
- localEpcIpAddr = self.epcObj.GetIPAddress()
- localEpcUserName = self.epcObj.GetUserName()
- localEpcPassword = self.epcObj.GetPassword()
+ localEpcIpAddr = self.epcObj.IPAddress
+ localEpcUserName = self.epcObj.UserName
+ localEpcPassword = self.epcObj.Password
mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword)
mySSH.command('ip addr show | awk -f /tmp/active_net_interfaces.awk | egrep -v "lo|tun"', '\$', 5)
result = re.search('interfaceToUse=(?P<eth_interface>[a-zA-Z0-9\-\_]+)done', mySSH.getBefore())
@@ -522,12 +400,14 @@ class RANManagement():
# Make a copy and adapt to EPC / eNB IP addresses
mySSH.command('cp ' + full_config_file + ' ' + ci_full_config_file, '\$', 5)
if self.epcObj is not None:
- localEpcIpAddr = self.epcObj.GetIPAddress()
- mySSH.command('sed -i -e \'s/CI_MME_IP_ADDR/' + localEpcIpAddr + '/\' ' + ci_full_config_file, '\$', 2);
+ localMmeIpAddr = self.epcObj.MmeIPAddress
+ mySSH.command('sed -i -e \'s/CI_MME_IP_ADDR/' + localMmeIpAddr + '/\' ' + ci_full_config_file, '\$', 2);
mySSH.command('sed -i -e \'s/CI_ENB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2);
+ mySSH.command('sed -i -e \'s/CI_GNB_IP_ADDR/' + lIpAddr + '/\' ' + ci_full_config_file, '\$', 2);
mySSH.command('sed -i -e \'s/CI_RCC_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2);
mySSH.command('sed -i -e \'s/CI_RRU1_IP_ADDR/' + self.eNB1IPAddress + '/\' ' + ci_full_config_file, '\$', 2);
mySSH.command('sed -i -e \'s/CI_RRU2_IP_ADDR/' + self.eNB2IPAddress + '/\' ' + ci_full_config_file, '\$', 2);
+ mySSH.command('sed -i -e \'s/CI_FR1_CTL_ENB_IP_ADDR/' + self.eNBIPAddress + '/\' ' + ci_full_config_file, '\$', 2);
if self.flexranCtrlInstalled and self.flexranCtrlStarted:
mySSH.command('sed -i -e \'s/FLEXRAN_ENABLED.*;/FLEXRAN_ENABLED = "yes";/\' ' + ci_full_config_file, '\$', 2);
else:
@@ -546,15 +426,14 @@ class RANManagement():
# Launch eNB with the modified config file
mySSH.command('source oaienv', '\$', 5)
mySSH.command('cd cmake_targets', '\$', 5)
- mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface + '-softmodem -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5)
+ if self.air_interface == 'nr':
+ mySSH.command('if [ -e rbconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm rbconfig.raw; fi', '\$', 5)
+ mySSH.command('if [ -e reconfig.raw ]; then echo ' + lPassWord + ' | sudo -S rm reconfig.raw; fi', '\$', 5)
+ # NOTE: WE SHALL do a check if the executable is present (in case build went wrong)
+ mySSH.command('echo "ulimit -c unlimited && ./ran_build/build/' + self.air_interface[self.eNB_instance] + ' -O ' + lSourcePath + '/' + ci_full_config_file + extra_options + '" > ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5)
mySSH.command('chmod 775 ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5)
mySSH.command('echo ' + lPassWord + ' | sudo -S rm -Rf enb_' + self.testCase_id + '.log', '\$', 5)
- mySSH.command('hostnamectl','\$', 5)
- result = re.search('CentOS Linux 7', mySSH.getBefore())
- if result is not None:
- mySSH.command('echo $USER; nohup sudo ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log 2>&1 &', lUserName, 10)
- else:
- mySSH.command('echo ' + lPassWord + ' | sudo -S -E daemon --inherit --unsafe --name=enb' + str(self.eNB_instance) + '_daemon --chdir=' + lSourcePath + '/cmake_targets -o ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5)
+ mySSH.command('echo $USER; nohup sudo -E ./my-lte-softmodem-run' + str(self.eNB_instance) + '.sh > ' + lSourcePath + '/cmake_targets/enb_' + self.testCase_id + '.log 2>&1 &', lUserName, 10)
self.eNBLogFiles[int(self.eNB_instance)] = 'enb_' + self.testCase_id + '.log'
if extra_options != '':
self.eNBOptions[int(self.eNB_instance)] = extra_options
@@ -571,15 +450,15 @@ class RANManagement():
mySSH.command('killall --signal SIGKILL record', '\$', 5)
mySSH.close()
doLoop = False
- logging.error('\u001B[1;37;41m eNB logging system did not show got sync! \u001B[0m')
+ logging.error('\u001B[1;37;41m eNB/gNB/ocp-eNB logging system did not show got sync! \u001B[0m')
if self.htmlObj is not None:
- self.htmlObj.CreateHtmlTestRow('-O ' + config_file + extra_options, 'KO', CONST.ALL_PROCESSES_OK)
+ self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' -O ' + config_file + extra_options, 'KO', CONST.ALL_PROCESSES_OK)
# In case of T tracer recording, we need to kill tshark on EPC side
result = re.search('T_stdout', str(self.Initialize_eNB_args))
if (result is not None) and (self.epcObj is not None):
- localEpcIpAddr = self.epcObj.GetIPAddress()
- localEpcUserName = self.epcObj.GetUserName()
- localEpcPassword = self.epcObj.GetPassword()
+ localEpcIpAddr = self.epcObj.IPAddress
+ localEpcUserName = self.epcObj.UserName
+ localEpcPassword = self.epcObj.Password
mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword)
logging.debug('\u001B[1m Stopping tshark \u001B[0m')
mySSH.command('echo ' + localEpcPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5)
@@ -607,7 +486,11 @@ class RANManagement():
enbDidSync = True
time.sleep(10)
- if enbDidSync and eNBinNoS1:
+ rruCheck = False
+ result = re.search('^rru|^du.band', str(config_file))
+ if result is not None:
+ rruCheck = True
+ if enbDidSync and eNBinNoS1 and not rruCheck:
mySSH.command('ifconfig oaitun_enb1', '\$', 4)
mySSH.command('ifconfig oaitun_enb1', '\$', 4)
result = re.search('inet addr:1|inet 1', mySSH.getBefore())
@@ -627,8 +510,8 @@ class RANManagement():
mySSH.close()
if self.htmlObj is not None:
- self.htmlObj.CreateHtmlTestRow('-O ' + config_file + extra_options, 'OK', CONST.ALL_PROCESSES_OK)
- logging.debug('\u001B[1m Initialize eNB Completed\u001B[0m')
+ self.htmlObj.CreateHtmlTestRow(self.air_interface[self.eNB_instance] + ' -O ' + config_file + extra_options, 'OK', CONST.ALL_PROCESSES_OK)
+ logging.debug('\u001B[1m Initialize eNB/gNB/ocp-eNB Completed\u001B[0m')
def CheckeNBProcess(self, status_queue):
try:
@@ -651,8 +534,8 @@ class RANManagement():
lPassWord = self.eNBPassword
mySSH = SSH.SSHConnection()
mySSH.open(lIpAddr, lUserName, lPassWord)
- mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface + '-softmodem | grep -v grep', '\$', 5)
- result = re.search(self.air_interface + '-softmodem', mySSH.getBefore())
+ mySSH.command('stdbuf -o0 ps -aux | grep --color=never ' + self.air_interface[self.eNB_instance] + ' | grep -v grep', '\$', 5)
+ result = re.search(self.air_interface[self.eNB_instance], mySSH.getBefore())
if result is None:
logging.debug('\u001B[1;37;41m eNB Process Not Found! \u001B[0m')
status_queue.put(CONST.ENB_PROCESS_FAILED)
@@ -684,29 +567,28 @@ class RANManagement():
mySSH = SSH.SSHConnection()
mySSH.open(lIpAddr, lUserName, lPassWord)
mySSH.command('cd ' + lSourcePath + '/cmake_targets', '\$', 5)
- if self.air_interface == 'lte':
+ if (self.air_interface[self.eNB_instance] == 'lte-softmodem') or (self.air_interface[self.eNB_instance] == 'ocp-enb'):
nodeB_prefix = 'e'
else:
nodeB_prefix = 'g'
- mySSH.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5)
- result = re.search('-softmodem', mySSH.getBefore())
+ mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5)
+ result = re.search('(-softmodem|ocp)', mySSH.getBefore())
if result is not None:
- mySSH.command('echo ' + lPassWord + ' | sudo -S daemon --name=enb' + str(self.eNB_instance) + '_daemon --stop', '\$', 5)
- mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem || true', '\$', 5)
+ mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGINT -r .*-softmodem ocp-enb || true', '\$', 5)
time.sleep(10)
- mySSH.command('stdbuf -o0 ps -aux | grep --color=never softmodem | grep -v grep', '\$', 5)
- result = re.search('-softmodem', mySSH.getBefore())
+ mySSH.command('stdbuf -o0 ps -aux | grep --color=never -e softmodem -e ocp-enb | grep -v grep', '\$', 5)
+ result = re.search('(-softmodem|ocp)', mySSH.getBefore())
if result is not None:
- mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem || true', '\$', 5)
+ mySSH.command('echo ' + lPassWord + ' | sudo -S killall --signal SIGKILL -r .*-softmodem ocp-enb || true', '\$', 5)
time.sleep(5)
mySSH.command('rm -f my-lte-softmodem-run' + str(self.eNB_instance) + '.sh', '\$', 5)
mySSH.close()
# If tracer options is on, stopping tshark on EPC side
result = re.search('T_stdout', str(self.Initialize_eNB_args))
if (result is not None) and (self.epcObj is not None):
- localEpcIpAddr = self.epcObj.GetIPAddress()
- localEpcUserName = self.epcObj.GetUserName()
- localEpcPassword = self.epcObj.GetPassword()
+ localEpcIpAddr = self.epcObj.IPAddress
+ localEpcUserName = self.epcObj.UserName
+ localEpcPassword = self.epcObj.Password
mySSH.open(localEpcIpAddr, localEpcUserName, localEpcPassword)
logging.debug('\u001B[1m Stopping tshark \u001B[0m')
mySSH.command('echo ' + localEpcPassword + ' | sudo -S killall --signal SIGKILL tshark', '\$', 5)
@@ -745,7 +627,7 @@ class RANManagement():
if (copyin_res == -1):
logging.debug('\u001B[1;37;41m Could not copy ' + nodeB_prefix + 'NB logfile to analyze it! \u001B[0m')
if self.htmlObj is not None:
- self.htmlObj.SetHmleNBFailureMsg('Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!')
+ self.htmlObj.htmleNBFailureMsg='Could not copy ' + nodeB_prefix + 'NB logfile to analyze it!'
self.htmlObj.CreateHtmlTestRow('N/A', 'KO', CONST.ENB_PROCESS_NOLOGFILE_TO_ANALYZE)
self.eNBmbmsEnables[int(self.eNB_instance)] = False
return
@@ -774,7 +656,7 @@ class RANManagement():
mySSH.command('cd ' + self.eNBSourceCodePath, '\$', 5)
mySSH.command('cd cmake_targets', '\$', 5)
mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm -f enb.log.zip', '\$', 5)
- mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 60)
+ mySSH.command('echo ' + self.eNBPassword + ' | sudo -S zip enb.log.zip enb*.log core* enb_*record.raw enb_*.pcap enb_*txt physim_*.log', '\$', 60)
mySSH.command('echo ' + self.eNBPassword + ' | sudo -S rm enb*.log core* enb_*record.raw enb_*.pcap enb_*txt', '\$', 5)
mySSH.close()
@@ -800,7 +682,11 @@ class RANManagement():
uciStatMsgCount = 0
pdcpFailure = 0
ulschFailure = 0
+ ulschAllocateCCEerror = 0
+ uplinkSegmentsAborted = 0
ulschReceiveOK = 0
+ gnbRxTxWakeUpFailure = 0
+ gnbTxWriteThreadEnabled = False
cdrxActivationMessageCount = 0
dropNotEnoughRBs = 0
mbmsRequestMsg = 0
@@ -811,7 +697,31 @@ class RANManagement():
X2HO_state = CONST.X2_HO_REQ_STATE__IDLE
X2HO_inNbProcedures = 0
X2HO_outNbProcedures = 0
+ global_status = CONST.ALL_PROCESSES_OK
+ # Runtime statistics
+ runTime = ''
+ userTime = ''
+ systemTime = ''
+ maxPhyMemUsage = ''
+ nbContextSwitches = ''
for line in enb_log_file.readlines():
+ # Runtime statistics
+ result = re.search('Run time:' ,str(line))
+ if result is not None:
+ runTime = str(line).strip()
+ if runTime != '':
+ result = re.search('Time executing user inst', str(line))
+ if result is not None:
+ userTime = 'to be decoded - 1'
+ result = re.search('Time executing system inst', str(line))
+ if result is not None:
+ systemTime = 'to be decoded - 2'
+ result = re.search('Max. Phy. memory usage:', str(line))
+ if result is not None:
+ maxPhyMemUsage = 'to be decoded - 3'
+ result = re.search('Number of context switch.*process origin', str(line))
+ if result is not None:
+ nbContextSwitches = 'to be decoded - 4'
if X2HO_state == CONST.X2_HO_REQ_STATE__IDLE:
result = re.search('target eNB Receives X2 HO Req X2AP_HANDOVER_REQ', str(line))
if result is not None:
@@ -884,8 +794,7 @@ class RANManagement():
if result is not None:
rrcSetupComplete += 1
result = re.search('Generate LTE_RRCConnectionRelease|Generate RRCConnectionRelease', str(line))
- if result is not None:
- rrcReleaseRequest += 1
+ if result is not None: rrcReleaseRequest += 1
result = re.search('Generate LTE_RRCConnectionReconfiguration', str(line))
if result is not None:
rrcReconfigRequest += 1
@@ -910,9 +819,21 @@ class RANManagement():
result = re.search('PDCP.*Out of Resources.*reason', str(line))
if result is not None:
pdcpFailure += 1
- result = re.search('ULSCH in error in round', str(line))
+ result = re.search('could not wakeup gNB rxtx process', str(line))
+ if result is not None:
+ gnbRxTxWakeUpFailure += 1
+ result = re.search('tx write thread ready', str(line))
+ if result is not None:
+ gnbTxWriteThreadEnabled = True
+ result = re.search('ULSCH in error in round|ULSCH 0 in error', str(line))
if result is not None:
ulschFailure += 1
+ result = re.search('ERROR ALLOCATING CCEs', str(line))
+ if result is not None:
+ ulschAllocateCCEerror += 1
+ result = re.search('uplink segment error.*aborted [1-9] segments', str(line))
+ if result is not None:
+ uplinkSegmentsAborted += 1
result = re.search('ULSCH received ok', str(line))
if result is not None:
ulschReceiveOK += 1
@@ -931,15 +852,23 @@ class RANManagement():
mbmsRequestMsg += 1
enb_log_file.close()
logging.debug(' File analysis completed')
- if self.air_interface == 'lte':
+ if (self.air_interface[self.eNB_instance] == 'lte-softmodem') or (self.air_interface[self.eNB_instance] == 'ocp-enb'):
nodeB_prefix = 'e'
else:
nodeB_prefix = 'g'
- if self.air_interface == 'nr':
+ if self.air_interface[self.eNB_instance] == 'nr-softmodem':
if ulschReceiveOK > 0:
statMsg = nodeB_prefix + 'NB showed ' + str(ulschReceiveOK) + ' "ULSCH received ok" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
htmleNBFailureMsg += statMsg + '\n'
+ if gnbRxTxWakeUpFailure > 0:
+ statMsg = nodeB_prefix + 'NB showed ' + str(gnbRxTxWakeUpFailure) + ' "could not wakeup gNB rxtx process" message(s)'
+ logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
+ htmleNBFailureMsg += statMsg + '\n'
+ if gnbTxWriteThreadEnabled:
+ statMsg = nodeB_prefix + 'NB ran with TX Write thread enabled'
+ logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
+ htmleNBFailureMsg += statMsg + '\n'
if uciStatMsgCount > 0:
statMsg = nodeB_prefix + 'NB showed ' + str(uciStatMsgCount) + ' "uci->stat" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
@@ -952,6 +881,14 @@ class RANManagement():
statMsg = nodeB_prefix + 'NB showed ' + str(ulschFailure) + ' "ULSCH in error in round" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
htmleNBFailureMsg += statMsg + '\n'
+ if ulschAllocateCCEerror > 0:
+ statMsg = nodeB_prefix + 'NB showed ' + str(ulschAllocateCCEerror) + ' "eNB_dlsch_ulsch_scheduler(); ERROR ALLOCATING CCEs" message(s)'
+ logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
+ htmleNBFailureMsg += statMsg + '\n'
+ if uplinkSegmentsAborted > 0:
+ statMsg = nodeB_prefix + 'NB showed ' + str(uplinkSegmentsAborted) + ' "uplink segment error 0/2, aborted * segments" message(s)'
+ logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
+ htmleNBFailureMsg += statMsg + '\n'
if dropNotEnoughRBs > 0:
statMsg = 'eNB showed ' + str(dropNotEnoughRBs) + ' "dropping, not enough RBs" message(s)'
logging.debug('\u001B[1;30;43m ' + statMsg + ' \u001B[0m')
@@ -1022,30 +959,30 @@ class RANManagement():
rruMsg = 'Slave RRU DID NOT receive the RRU_frame_resynch command from RAU'
logging.debug('\u001B[1;37;41m ' + rruMsg + ' \u001B[0m')
htmleNBFailureMsg += rruMsg + '\n'
- self.prematureExit(True)
- return CONST.ENB_PROCESS_SLAVE_RRU_NOT_SYNCED
+ self.prematureExit = True
+ global_status = CONST.ENB_PROCESS_SLAVE_RRU_NOT_SYNCED
if foundSegFault:
logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with a Segmentation Fault! \u001B[0m')
- if self.htmlObj is not None:
- self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg)
- return CONST.ENB_PROCESS_SEG_FAULT
+ global_status = CONST.ENB_PROCESS_SEG_FAULT
if foundAssertion:
logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB ended with an assertion! \u001B[0m')
htmleNBFailureMsg += msgAssertion
- if self.htmlObj is not None:
- self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg)
- return CONST.ENB_PROCESS_ASSERTION
+ global_status = CONST.ENB_PROCESS_ASSERTION
if foundRealTimeIssue:
logging.debug('\u001B[1;37;41m ' + nodeB_prefix + 'NB faced real time issues! \u001B[0m')
htmleNBFailureMsg += nodeB_prefix + 'NB faced real time issues!\n'
- #return CONST.ENB_PROCESS_REALTIME_ISSUE
if rlcDiscardBuffer > 0:
rlcMsg = nodeB_prefix + 'NB RLC discarded ' + str(rlcDiscardBuffer) + ' buffer(s)'
logging.debug('\u001B[1;37;41m ' + rlcMsg + ' \u001B[0m')
htmleNBFailureMsg += rlcMsg + '\n'
- if self.htmlObj is not None:
- self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg)
- return CONST.ENB_PROCESS_REALTIME_ISSUE
+ global_status = CONST.ENB_PROCESS_REALTIME_ISSUE
if self.htmlObj is not None:
- self.htmlObj.SetHmleNBFailureMsg(htmleNBFailureMsg)
- return 0
+ self.htmlObj.htmleNBFailureMsg=htmleNBFailureMsg
+ # Runtime statistics
+ if runTime != '':
+ logging.debug(runTime)
+ logging.debug('Time executing user inst : ' + userTime)
+ logging.debug('Time executing system inst : ' + systemTime)
+ logging.debug('Max Physical Memory Usage : ' + maxPhyMemUsage)
+ logging.debug('Nb Context Switches : ' + nbContextSwitches)
+ return global_status
diff --git a/ci-scripts/reportBuildLocally.sh b/ci-scripts/reportBuildLocally.sh
index 54372ac6ba7842ec376136ef541f464d8707facf..44d200c3b6419b1c0fe354fdb33db882c9bcb1f2 100755
--- a/ci-scripts/reportBuildLocally.sh
+++ b/ci-scripts/reportBuildLocally.sh
@@ -53,7 +53,7 @@ function details_table {
echo " <th>Message</th>" >> $3
echo " </tr>" >> $3
- LIST_MESSAGES=`egrep "error:|warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto"`
+ LIST_MESSAGES=`egrep "error:|warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto|disabling jobserver mode"`
COMPLETE_MESSAGE="start"
for MESSAGE in $LIST_MESSAGES
do
@@ -146,7 +146,7 @@ function summary_table_row {
else
echo " <td bgcolor = \"red\" >$NB_ERRORS</th>" >> ./build_results.html
fi
- NB_WARNINGS=`egrep "warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto" | egrep -c "warning:"`
+ NB_WARNINGS=`egrep "warning:" $2 | egrep -v "jobserver unavailable|Clock skew detected.|flexran.proto|disabling jobserver mode" | egrep -c "warning:"`
if [ $NB_WARNINGS -eq 0 ]
then
echo " <td bgcolor = \"green\" >$NB_WARNINGS</th>" >> ./build_results.html
@@ -492,6 +492,77 @@ function report_build {
awk '{print " <tr><td>"$1"</td></tr>"}' ./oai_rules_result_list.txt >> ./build_results.html
echo " </table>" >> ./build_results.html
echo " </div>" >> ./build_results.html
+ echo " <br>" >> ./build_results.html
+ fi
+ if [ -f ./header-files-w-incorrect-define.txt ]
+ then
+ NB_FILES_IN_ERROR=`wc -l ./header-files-w-incorrect-define.txt | sed -e "s@ .*@@"`
+ if [ $NB_FILES_IN_ERROR -eq 0 ]
+ then
+ echo " <div class=\"alert alert-success\">" >> ./build_results.html
+ if [ $MR_TRIG -eq 1 ]; then echo " <strong>No Issue for CIRCULAR DEPENDENCY PROTECTION in modified files</strong>" >> ./build_results.html; fi
+ if [ $PU_TRIG -eq 1 ]; then echo " <strong>No Issue for CIRCULAR DEPENDENCY PROTECTION in the whole repository</strong>" >> ./build_results.html; fi
+ echo " </div>" >> ./build_results.html
+ else
+ echo " <div class=\"alert alert-warning\">" >> ./build_results.html
+ if [ $MR_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} modified files MAY NOT HAVE CIRCULAR DEPENDENCY PROTECTION</strong>" >> ./build_results.html; fi
+ if [ $PU_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} files in repository MAY NOT HAVE CIRCULAR DEPENDENCY PROTECTION in the whole repository</strong>" >> ./build_results.html; fi
+ echo " </div>" >> ./build_results.html
+ echo " <button data-toggle=\"collapse\" data-target=\"#oai-circular-details\">More details on circular dependency protection check</button>" >> ./build_results.html
+ echo " <div id=\"oai-circular-details\" class=\"collapse\">" >> ./build_results.html
+ echo " <table border = 1>" >> ./build_results.html
+ echo " <tr>" >> ./build_results.html
+ echo " <th bgcolor = \"lightcyan\" >Potential Issue</th>" >> ./build_results.html
+ echo " <th bgcolor = \"lightcyan\" >Impacted File</th>" >> ./build_results.html
+ echo " <th bgcolor = \"lightcyan\" >Incorrect Macro</th>" >> ./build_results.html
+ echo " </tr>" >> ./build_results.html
+ awk '{if($0 ~/error in/){print " <tr><td>error in declaration</td><td>"$4"</td><td>"$5"</td></tr>"};if($0 ~/files with same/){print " <tr><td>files with same #define</td><td>"$5"</td><td>"$6"</td></tr>"}}' ./header-files-w-incorrect-define.txt >> ./build_results.html
+ echo " </table>" >> ./build_results.html
+ echo " </div>" >> ./build_results.html
+ echo " <br>" >> ./build_results.html
+ fi
+ fi
+ if [ -f ./files-w-gnu-gpl-license-banner.txt ]
+ then
+ NB_FILES_IN_ERROR=`wc -l ./files-w-gnu-gpl-license-banner.txt | sed -e "s@ .*@@"`
+ if [ $NB_FILES_IN_ERROR -ne 0 ]
+ then
+ echo " <div class=\"alert alert-danger\">" >> ./build_results.html
+ if [ $MR_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} modified files HAVE a GNU GPL license banner</strong>" >> ./build_results.html; fi
+ if [ $PU_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} files in repository HAVE a GNU GPL license banner</strong>" >> ./build_results.html; fi
+ echo " </div>" >> ./build_results.html
+ echo " <button data-toggle=\"collapse\" data-target=\"#oai-license-gpl\">More details on GNU GPL license banner issue</button>" >> ./build_results.html
+ echo " <div id=\"oai-license-gpl\" class=\"collapse\">" >> ./build_results.html
+ echo " <table border = 1>" >> ./build_results.html
+ echo " <tr>" >> ./build_results.html
+ echo " <th bgcolor = \"lightcyan\" >Filename</th>" >> ./build_results.html
+ echo " </tr>" >> ./build_results.html
+ awk '{print " <tr><td>"$1"</td></tr>"}' ./files-w-gnu-gpl-license-banner.txt >> ./build_results.html
+ echo " </table>" >> ./build_results.html
+ echo " </div>" >> ./build_results.html
+ echo " <br>" >> ./build_results.html
+ fi
+ fi
+ if [ -f ./files-w-suspect-banner.txt ]
+ then
+ NB_FILES_IN_ERROR=`wc -l ./files-w-suspect-banner.txt | sed -e "s@ .*@@"`
+ if [ $NB_FILES_IN_ERROR -ne 0 ]
+ then
+ echo " <div class=\"alert alert-warning\">" >> ./build_results.html
+ if [ $MR_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} modified files HAVE a suspect license banner</strong>" >> ./build_results.html; fi
+ if [ $PU_TRIG -eq 1 ]; then echo " <strong>${NB_FILES_IN_ERROR} files in repository HAVE a suspect license banner</strong>" >> ./build_results.html; fi
+ echo " </div>" >> ./build_results.html
+ echo " <button data-toggle=\"collapse\" data-target=\"#oai-license-suspect\">More details on suspect banner files</button>" >> ./build_results.html
+ echo " <div id=\"oai-license-suspect\" class=\"collapse\">" >> ./build_results.html
+ echo " <table border = 1>" >> ./build_results.html
+ echo " <tr>" >> ./build_results.html
+ echo " <th bgcolor = \"lightcyan\" >Filename</th>" >> ./build_results.html
+ echo " </tr>" >> ./build_results.html
+ awk '{print " <tr><td>"$1"</td></tr>"}' ././files-w-suspect-banner.txt >> ./build_results.html
+ echo " </table>" >> ./build_results.html
+ echo " </div>" >> ./build_results.html
+ echo " <br>" >> ./build_results.html
+ fi
fi
fi
diff --git a/ci-scripts/reportTestLocally.sh b/ci-scripts/reportTestLocally.sh
index b74fe93a1f6aa3dd9066050c39dd93ed4b5a8d7d..b05ccf39db43a1d8d19c44662b3acb3a3b528690 100755
--- a/ci-scripts/reportTestLocally.sh
+++ b/ci-scripts/reportTestLocally.sh
@@ -620,6 +620,101 @@ function report_test {
#IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_ul*client*txt | grep -v mbms 2> /dev/null`
#analyzeIperfFiles
done
+
+ # FeMBMS Case
+ CN_CONFIG="noS1"
+ TMODE="fdd"
+ BW_CASES=(05)
+ for BW in ${BW_CASES[@]}
+ do
+ echo " <tr bgcolor = \"#8FBC8F\" >" >> ./test_simulator_results.html
+ echo " <td align = \"center\" colspan = 4 >Test FeMBMS without EPC (aka noS1): ${TMODE} -- ${BW}MHz </td>" >> ./test_simulator_results.html
+ echo " </tr>" >> ./test_simulator_results.html
+ ENB_LOG=$ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_enb_fembms.log
+ UE_LOG=`echo $ENB_LOG | sed -e "s#enb#ue#"`
+ if [ -f $ENB_LOG ] && [ -f $UE_LOG ]
+ then
+ NAME_ENB=`echo $ENB_LOG | sed -e "s#$ARCHIVES_LOC/##"`
+ NAME_UE=`echo $UE_LOG | sed -e "s#$ARCHIVES_LOC/##"`
+ echo " <tr>" >> ./test_simulator_results.html
+ echo " <td>$NAME_ENB --- $NAME_UE</td>" >> ./test_simulator_results.html
+ echo " <td>N/A</td>" >> ./test_simulator_results.html
+ #NB_ENB_GOT_SYNC=`egrep -c "got sync" $ENB_LOG`
+ NB_ENB_TUNNEL_UP=`egrep -c "Interface oaitun_enb1 successfully configured" $ENB_LOG`
+ NB_ENB_MTUNNEL_UP=`egrep -c "Interface oaitun_enm1 successfully configured" $ENB_LOG`
+ #NB_UE_GOT_SYNC=`egrep -c "rfsimulator: Success" $UE_LOG`
+ #NB_ENB_SYNCED_WITH_UE=`egrep -c "Generating RRCConnectionReconfigurationComplete" $UE_LOG`
+ NB_UE_TUNNEL_UP=`egrep -c "Interface oaitun_ue1 successfully configured" $UE_LOG`
+ NB_UE_MTUNNEL_UP=`egrep -c "Interface oaitun_uem1 successfully configured" $UE_LOG`
+ NB_UE_MBMS_PUSH_MSG=`egrep -c "TRIED TO PUSH MBMS DATA TO" $UE_LOG`
+ #if [ $NB_ENB_GOT_SYNC -gt 0 ] && [ $NB_UE_GOT_SYNC -gt 0 ] && [ $NB_ENB_SYNCED_WITH_UE -gt 0 ] && [ $NB_UE_MBMS_PUSH_MSG -gt 0 ]
+ if [ $NB_UE_MBMS_PUSH_MSG -gt 0 ]
+ then
+ echo " <td bgcolor = \"green\" >OK</td>" >> ./test_simulator_results.html
+ else
+ echo " <td bgcolor = \"red\" >KO</td>" >> ./test_simulator_results.html
+ fi
+ echo " <td><pre>" >> ./test_simulator_results.html
+ #if [ $NB_ENB_GOT_SYNC -gt 0 ]
+ #then
+ # echo "<font color = \"blue\">- eNB --> got sync</font>" >> ./test_simulator_results.html
+ #else
+ # echo "<font color = \"red\"><b>- eNB NEVER got sync</b></font>" >> ./test_simulator_results.html
+ #fi
+ if [ $NB_ENB_TUNNEL_UP -gt 0 ]
+ then
+ echo "<font color = \"blue\">- eNB mounted oaitun_enb1 interface</font>" >> ./test_simulator_results.html
+ else
+ echo "<font color = \"red\"><b>- eNB NEVER mounted oaitun_enb1 interface</b></font>" >> ./test_simulator_results.html
+ fi
+ if [ $NB_ENB_MTUNNEL_UP -gt 0 ]
+ then
+ echo "<font color = \"blue\">- eNB mounted oaitun_enm1 interface</font>" >> ./test_simulator_results.html
+ else
+ echo "<font color = \"red\"><b>- eNB NEVER mounted oaitun_enm1 interface</b></font>" >> ./test_simulator_results.html
+ fi
+ #if [ $NB_UE_GOT_SYNC -gt 0 ]
+ #then
+ # echo "<font color = \"blue\">- LTE UE --> got sync</font>" >> ./test_simulator_results.html
+ #else
+ # echo "<font color = \"red\"><b>- LTE UE NEVER got sync</b></font>" >> ./test_simulator_results.html
+ #fi
+ #if [ $NB_ENB_SYNCED_WITH_UE -gt 0 ]
+ #then
+ # echo "<font color = \"blue\">- LTE UE attached to eNB</font>" >> ./test_simulator_results.html
+ #else
+ # echo "<font color = \"red\"><b>- LTE UE NEVER attached to eNB</b></font>" >> ./test_simulator_results.html
+ #fi
+ if [ $NB_UE_TUNNEL_UP -gt 0 ]
+ then
+ echo "<font color = \"blue\">- LTE UE mounted oaitun_ue1 interface</font>" >> ./test_simulator_results.html
+ else
+ echo "<font color = \"red\"><b>- LTE UE NEVER mounted oaitun_ue1 interface</b></font>" >> ./test_simulator_results.html
+ fi
+ if [ $NB_UE_MTUNNEL_UP -gt 0 ]
+ then
+ echo "<font color = \"blue\">- LTE UE mounted oaitun_uem1 interface</font>" >> ./test_simulator_results.html
+ else
+ echo "<font color = \"red\"><b>- LTE UE NEVER mounted oaitun_uem1 interface</b></font>" >> ./test_simulator_results.html
+ fi
+ if [ $NB_UE_MBMS_PUSH_MSG -gt 0 ]
+ then
+ echo "<font color = \"blue\">- LTE UE tried to push ${NB_UE_MBMS_PUSH_MSG} MBMS DATA</font>" >> ./test_simulator_results.html
+ else
+ echo "<font color = \"red\"><b>- LTE UE NEVER pushed MBMS DATA</b></font>" >> ./test_simulator_results.html
+ fi
+ echo " </pre></td>" >> ./test_simulator_results.html
+ echo " </tr>" >> ./test_simulator_results.html
+ fi
+ #PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_ping*.log 2> /dev/null`
+ #analyzePingFiles
+
+ #IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_dl*client*txt | grep -v mbms 2> /dev/null`
+ #analyzeIperfFiles
+
+ #IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_ul*client*txt | grep -v mbms 2> /dev/null`
+ #analyzeIperfFiles
+ done
echo " </table>" >> ./test_simulator_results.html
echo " </div>" >> ./test_simulator_results.html
@@ -724,8 +819,8 @@ function report_test {
echo " </pre></td>" >> ./test_simulator_results.html
echo " </tr>" >> ./test_simulator_results.html
fi
- #PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}MHz_${UES}users_${CN_CONFIG}_ping*.log 2> /dev/null`
- #analyzePingFiles
+ PING_LOGS=`ls $ARCHIVES_LOC/${TMODE}_${BW}prb_${CN_CONFIG}_ping*.log 2> /dev/null`
+ analyzePingFiles
IPERF_TESTS=`ls $ARCHIVES_LOC/${TMODE}_${BW}prb_${CN_CONFIG}_iperf_dl*client*txt 2> /dev/null`
analyzeIperfFiles
diff --git a/ci-scripts/rrc-files/rbconfig.raw b/ci-scripts/rrc-files/rbconfig.raw
deleted file mode 100644
index b03f18d1219201d789d1c70e1dced3e84a932990..0000000000000000000000000000000000000000
Binary files a/ci-scripts/rrc-files/rbconfig.raw and /dev/null differ
diff --git a/ci-scripts/rrc-files/reconfig.raw b/ci-scripts/rrc-files/reconfig.raw
deleted file mode 100644
index 97b41d9b6b0f0662487ca39848f85e9c1f7f8594..0000000000000000000000000000000000000000
Binary files a/ci-scripts/rrc-files/reconfig.raw and /dev/null differ
diff --git a/ci-scripts/runTestOnVM.sh b/ci-scripts/runTestOnVM.sh
index 64af11c8ba67b6f2fc40e43081a8c299253248b4..b9b9a2bafab5d722aa7dc33be32e1777dd5ec76c 100755
--- a/ci-scripts/runTestOnVM.sh
+++ b/ci-scripts/runTestOnVM.sh
@@ -89,6 +89,9 @@ function start_basic_sim_enb {
fi
done
ENB_SYNC=0
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_VM_IP_ADDR < $1
rm $1
if [ $i -lt 50 ]
then
@@ -151,6 +154,9 @@ function start_basic_sim_ue {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$2 < $1
rm $1
if [ $i -lt 50 ]
then
@@ -523,9 +529,9 @@ function install_epc_on_vm {
echo "############################################################"
echo "[ -f 01proxy ] && sudo cp 01proxy /etc/apt/apt.conf.d/" > $LOC_EPC_VM_CMDS
echo "touch /home/ubuntu/.hushlogin" >> $LOC_EPC_VM_CMDS
- echo "echo \"sudo apt-get --yes --quiet install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev daemon iperf\"" >> $LOC_EPC_VM_CMDS
+ echo "echo \"sudo apt-get --yes --quiet install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev iperf\"" >> $LOC_EPC_VM_CMDS
echo "sudo apt-get update > zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS
- echo "sudo apt-get --yes install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev daemon iperf >> zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS
+ echo "sudo apt-get --yes install zip openjdk-8-jre libconfuse-dev libreadline-dev liblog4c-dev libgcrypt-dev libsctp-dev python2.7 python2.7-dev iperf >> zip-install.txt 2>&1" >> $LOC_EPC_VM_CMDS
# Installing HSS
echo "echo \"cd /opt\"" >> $LOC_EPC_VM_CMDS
@@ -588,8 +594,6 @@ function start_epc {
echo "echo \"cd /opt/hss_sim0609\"" > $LOC_EPC_VM_CMDS
echo "cd /opt/hss_sim0609" >> $LOC_EPC_VM_CMDS
echo "sudo rm -f hss.log" >> $LOC_EPC_VM_CMDS
- #echo "echo \"sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real\"" >> $LOC_EPC_VM_CMDS
- #echo "sudo daemon --unsafe --name=simulated_hss --chdir=/opt/hss_sim0609 ./starthss_real" >> $LOC_EPC_VM_CMDS
echo "echo \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS
echo "sudo su -c \"screen -dm -S simulated_hss ./starthss_real\"" >> $LOC_EPC_VM_CMDS
@@ -656,8 +660,6 @@ function terminate_epc {
echo "cd /opt/ltebox/tools" >> $1
echo "echo \"sudo ./stop_ltebox\"" >> $1
echo "sudo ./stop_ltebox" >> $1
- echo "echo \"sudo daemon --name=simulated_hss --stop\"" >> $1
- echo "sudo daemon --name=simulated_hss --stop" >> $1
echo "echo \"sudo killall --signal SIGKILL hss_sim\"" >> $1
echo "sudo killall --signal SIGKILL hss_sim" >> $1
ssh -T -o StrictHostKeyChecking=no ubuntu@$2 < $1
@@ -764,6 +766,9 @@ function start_l2_sim_enb {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1
rm $1
ENB_SYNC=1
if [ $i -lt 50 ]
@@ -872,6 +877,9 @@ function start_l2_sim_ue {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1
rm $1
UE_SYNC=1
if [ $i -lt 50 ]
@@ -985,6 +993,9 @@ function start_rf_sim_enb {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_ENB_VM_IP_ADDR < $1
rm $1
if [ $i -lt 50 ]
then
@@ -1114,6 +1125,9 @@ function start_rf_sim_ue {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_UE_VM_IP_ADDR < $1
rm $1
if [ $i -lt 50 ]
then
@@ -1158,6 +1172,10 @@ function start_rf_sim_gnb {
local LOC_CONF_FILE=$5
# 1 is with S1 and 0 without S1 aka noS1
local LOC_S1_CONFIGURATION=$6
+
+ if [ -e rbconfig.raw ]; then rm -f rbconfig.raw; fi
+ if [ -e reconfig.raw ]; then rm -f reconfig.raw; fi
+
echo "cd /home/ubuntu/tmp" > $1
echo "echo \"sudo apt-get --yes --quiet install daemon \"" >> $1
echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1
@@ -1171,6 +1189,7 @@ function start_rf_sim_gnb {
echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1
echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
+ echo "sudo rm -f r*config.raw" >> $1
if [ $LOC_S1_CONFIGURATION -eq 0 ]
then
echo "echo \"RFSIMULATOR=server ./nr-softmodem -O /home/ubuntu/tmp/ci-scripts/conf_files/ci-$LOC_CONF_FILE --log_config.global_log_options level,nocolor --parallel-config PARALLEL_SINGLE_THREAD --noS1 --nokrnmod 1 --rfsim --phy-test\" > ./my-nr-softmodem-run.sh " >> $1
@@ -1231,6 +1250,13 @@ function start_rf_sim_gnb {
fi
fi
sleep 10
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR < $1
+ rm $1
+ # Copy the RAW files from the gNB run for the NR-UE
+ scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/rbconfig.raw .
+ scp -o StrictHostKeyChecking=no ubuntu@$LOC_GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/ran_build/build/reconfig.raw .
}
function start_rf_sim_nr_ue {
@@ -1241,14 +1267,21 @@ function start_rf_sim_nr_ue {
local LOC_FREQUENCY=$6
# 1 is with S1 and 0 without S1 aka noS1
local LOC_S1_CONFIGURATION=$7
+
+ # Copy the RAW files from the gNB run
+ scp -o StrictHostKeyChecking=no rbconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp
+ scp -o StrictHostKeyChecking=no reconfig.raw ubuntu@$LOC_NR_UE_VM_IP_ADDR:/home/ubuntu/tmp
+
echo "echo \"sudo apt-get --yes --quiet install daemon \"" > $1
echo "sudo apt-get --yes install daemon >> /home/ubuntu/tmp/cmake_targets/log/daemon-install.txt 2>&1" >> $1
echo "echo \"cd /home/ubuntu/tmp/cmake_targets/ran_build/build/\"" >> $1
echo "sudo chmod 777 /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
+ echo "sudo cp /home/ubuntu/tmp/r*config.raw /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
+ echo "sudo chmod 666 /home/ubuntu/tmp/cmake_targets/ran_build/build/r*config.raw" >> $1
echo "cd /home/ubuntu/tmp/cmake_targets/ran_build/build/" >> $1
if [ $LOC_S1_CONFIGURATION -eq 0 ]
then
- echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/ci-scripts/rrc-files --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1
+ echo "echo \"RFSIMULATOR=${LOC_GNB_VM_IP_ADDR} ./nr-uesoftmodem --nokrnmod 1 --rfsim --phy-test --rrc_config_path /home/ubuntu/tmp/cmake_targets/ran_build/build/ --log_config.global_log_options level,nocolor --noS1\" > ./my-nr-softmodem-run.sh " >> $1
fi
echo "chmod 775 ./my-nr-softmodem-run.sh" >> $1
echo "cat ./my-nr-softmodem-run.sh" >> $1
@@ -1295,6 +1328,9 @@ function start_rf_sim_nr_ue {
i=$[$i+1]
fi
done
+ echo "echo \"free -m\"" > $1
+ echo "free -m" >> $1
+ ssh -T -o StrictHostKeyChecking=no ubuntu@$LOC_NR_UE_VM_IP_ADDR < $1
rm $1
if [ $i -lt 50 ]
then
@@ -2014,6 +2050,95 @@ function run_test_on_vm {
echo "LTE RFSIM seems to FAIL"
echo "LTE: TEST_KO" > $ARCHIVES_LOC/test_final_status.log
fi
+
+ ####################
+ ## FeMBMS CASE noS1 ##
+ ####################
+ CONF_FILE=lte-fdd-fembms-basic-sim.conf
+ CN_CONFIG="noS1"
+ S1_NOS1_CFG=0
+ LTEBOX=0
+ TMODE="fdd"
+ FREQUENCY=2680
+ BW_CASES=(05)
+ FeMBMS_STATUS=0
+
+ for BW in ${BW_CASES[@]}
+ do
+ if [[ $BW =~ .*05.* ]]; then PRB=25; fi
+ if [[ $BW =~ .*10.* ]]; then PRB=50; fi
+ if [[ $BW =~ .*20.* ]]; then PRB=100; fi
+
+ echo "############################################################"
+ echo "${CN_CONFIG} : Starting the eNB with MSMS in ${TMODE}-${BW}MHz mode"
+ echo "############################################################"
+ CURRENT_ENB_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_enb_fembms.log
+ start_rf_sim_enb $ENB_VM_CMDS "$ENB_VM_IP_ADDR" "$EPC_VM_IP_ADDR" $CURRENT_ENB_LOG_FILE $PRB $CONF_FILE $S1_NOS1_CFG
+
+ echo "############################################################"
+ echo "${CN_CONFIG} : Starting the UE"
+ echo "############################################################"
+ CURRENT_UE_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_ue_fembms.log
+ start_rf_sim_ue $UE_VM_CMDS $UE_VM_IP_ADDR $ENB_VM_IP_ADDR $CURRENT_UE_LOG_FILE $PRB $FREQUENCY $S1_NOS1_CFG 1
+ if [ $UE_SYNC -eq 0 ]
+ then
+ echo "Problem w/ eNB and UE not syncing"
+ terminate_enb_ue_basic_sim $ENB_VM_CMDS $ENB_VM_IP_ADDR 1
+ terminate_enb_ue_basic_sim $UE_VM_CMDS $UE_VM_IP_ADDR 2
+ scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_ENB_LOG_FILE $ARCHIVES_LOC
+ scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_UE_LOG_FILE $ARCHIVES_LOC
+ STATUS=-1
+ break
+ fi
+
+ echo "############################################################"
+ echo "${CN_CONFIG} : iperf DL -- UE is server and eNB is client"
+ echo "############################################################"
+ get_enb_mbms_noS1_ip_addr $ENB_VM_CMDS $ENB_VM_IP_ADDR
+ IPERF_LOG_FILE=${TMODE}_${BW}MHz_${CN_CONFIG}_iperf_dl_fembms
+ get_ue_mbms_ip_addr $UE_VM_CMDS $UE_VM_IP_ADDR 1
+ THROUGHPUT=2
+ generic_iperf $UE_VM_CMDS $UE_VM_IP_ADDR $UE_IP_ADDR $ENB_VM_CMDS $ENB_VM_IP_ADDR $ENB_IP_ADDR $THROUGHPUT $IPERF_LOG_FILE 1 0
+ scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/${IPERF_LOG_FILE}_server.txt $ARCHIVES_LOC
+ scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/${IPERF_LOG_FILE}_client.txt $ARCHIVES_LOC
+ #check_iperf $ARCHIVES_LOC/$IPERF_LOG_FILE $THROUGHPUT
+
+ echo "############################################################"
+ echo "${CN_CONFIG} : Terminate enb/ue simulators"
+ echo "############################################################"
+ terminate_enb_ue_basic_sim $ENB_VM_CMDS $ENB_VM_IP_ADDR 1
+ terminate_enb_ue_basic_sim $UE_VM_CMDS $UE_VM_IP_ADDR 2
+ scp -o StrictHostKeyChecking=no ubuntu@$ENB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_ENB_LOG_FILE $ARCHIVES_LOC
+ scp -o StrictHostKeyChecking=no ubuntu@$UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_UE_LOG_FILE $ARCHIVES_LOC
+ NB_UE_FeMBMS_MESSAGES=`egrep -c "TRIED TO PUSH MBMS DATA TO" $ARCHIVES_LOC/$CURRENT_UE_LOG_FILE`
+ if [ $NB_UE_FeMBMS_MESSAGES -eq 0 ]; then FeMBMS_STATUS=-1; fi
+
+ done
+
+ full_l2_sim_destroy
+
+ echo "############################################################"
+ echo "Checking run status"
+ echo "############################################################"
+
+ if [ $PING_STATUS -ne 0 ]; then STATUS=-1; fi
+ if [ $IPERF_STATUS -ne 0 ]; then STATUS=-1; fi
+ if [ $FeMBMS_STATUS -eq 0 ]
+ then
+ echo "LTE FeMBMS RFSIM seems OK"
+ else
+ echo "LTE FeMBMS RFSIM seems to FAIL"
+ STATUS=-1
+ fi
+ if [ $STATUS -eq 0 ]
+ then
+ echo "LTE RFSIM seems OK"
+ echo "LTE: TEST_OK" > $ARCHIVES_LOC/test_final_status.log
+ else
+ echo "LTE RFSIM seems to FAIL"
+ echo "LTE: TEST_KO" > $ARCHIVES_LOC/test_final_status.log
+ fi
+
fi
if [[ "$RUN_OPTIONS" == "complex" ]] && [[ $VM_NAME =~ .*-rf-sim.* ]]
@@ -2028,7 +2153,7 @@ function run_test_on_vm {
NR_STATUS=0
######### start of loop
- while [ $try_cnt -lt 5 ]
+ while [ $try_cnt -lt 1 ]
do
SYNC_STATUS=0
PING_STATUS=0
@@ -2050,6 +2175,8 @@ function run_test_on_vm {
echo "Problem w/ gNB and NR-UE not syncing"
terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2
terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1
+ scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC
+ scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC
SYNC_STATUS=-1
try_cnt=$[$try_cnt+1]
continue
@@ -2089,6 +2216,8 @@ function run_test_on_vm {
echo "DL test not OK"
terminate_enb_ue_basic_sim $NR_UE_VM_CMDS $NR_UE_VM_IP_ADDR 2
terminate_enb_ue_basic_sim $GNB_VM_CMDS $GNB_VM_IP_ADDR 1
+ scp -o StrictHostKeyChecking=no ubuntu@$GNB_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_GNB_LOG_FILE $ARCHIVES_LOC
+ scp -o StrictHostKeyChecking=no ubuntu@$NR_UE_VM_IP_ADDR:/home/ubuntu/tmp/cmake_targets/log/$CURRENT_NR_UE_LOG_FILE $ARCHIVES_LOC
try_cnt=$[$try_cnt+1]
continue
fi
diff --git a/ci-scripts/sshconnection.py b/ci-scripts/sshconnection.py
index 68a1d7836c78cf8a6b306736ee0d9685ae48a450..ed0cf5379a18aa121e0a2cd373a9faf26518366e 100644
--- a/ci-scripts/sshconnection.py
+++ b/ci-scripts/sshconnection.py
@@ -52,15 +52,19 @@ class SSHConnection():
self.picocom_closure = True
def open(self, ipaddress, username, password):
+ extraSshOptions = ''
count = 0
connect_status = False
+ if ipaddress == '192.168.18.197':
+ extraSshOptions = ' -o UserKnownHostsFile=/dev/null -o StrictHostKeyChecking=no'
while count < 4:
- self.ssh = pexpect.spawn('ssh', [username + '@' + ipaddress], timeout = 5)
+ self.ssh = pexpect.spawn('ssh', [username + '@' + ipaddress + extraSshOptions], timeout = 5)
self.sshresponse = self.ssh.expect(['Are you sure you want to continue connecting (yes/no)?', 'password:', 'Last login', pexpect.EOF, pexpect.TIMEOUT])
if self.sshresponse == 0:
self.ssh.sendline('yes')
- self.ssh.expect('password:')
- self.ssh.sendline(password)
+ self.sshresponse = self.ssh.expect(['password:', username + '@'])
+ if self.sshresponse == 0:
+ self.ssh.sendline(password)
self.sshresponse = self.ssh.expect(['\$', 'Permission denied', 'password:', pexpect.EOF, pexpect.TIMEOUT])
if self.sshresponse == 0:
count = 10
@@ -97,6 +101,18 @@ class SSHConnection():
else:
sys.exit('SSH Connection Failed')
+
+
+
+ def cde_check_value(self, commandline, expected, timeout):
+ logging.debug(commandline)
+ self.ssh.timeout = timeout
+ self.ssh.sendline(commandline)
+ expected.append(pexpect.EOF)
+ expected.append(pexpect.TIMEOUT)
+ self.sshresponse = self.ssh.expect(expected)
+ return self.sshresponse
+
def command(self, commandline, expectedline, timeout):
logging.debug(commandline)
self.ssh.timeout = timeout
diff --git a/ci-scripts/xml_class_list.yml b/ci-scripts/xml_class_list.yml
new file mode 100755
index 0000000000000000000000000000000000000000..e80063a120ad9e163a7ef549f296da0f677241fc
--- /dev/null
+++ b/ci-scripts/xml_class_list.yml
@@ -0,0 +1,35 @@
+ - COTS_UE_Airplane
+ - Build_PhySim
+ - Run_PhySim
+ - Build_eNB
+ - WaitEndBuild_eNB
+ - Initialize_eNB
+ - Terminate_eNB
+ - Initialize_UE
+ - Terminate_UE
+ - Attach_UE
+ - Detach_UE
+ - Build_OAI_UE
+ - Initialize_OAI_UE
+ - Terminate_OAI_UE
+ - DataDisable_UE
+ - DataEnable_UE
+ - CheckStatusUE
+ - Ping
+ - Iperf
+ - Reboot_UE
+ - Initialize_FlexranCtrl
+ - Terminate_FlexranCtrl
+ - Initialize_HSS
+ - Terminate_HSS
+ - Initialize_MME
+ - Terminate_MME
+ - Initialize_SPGW
+ - Terminate_SPGW
+ - Initialize_CatM_module
+ - Terminate_CatM_module
+ - Attach_CatM_module
+ - Detach_CatM_module
+ - Ping_CatM_module
+ - IdleSleep
+ - Perform_X2_Handover
diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a4caa77075979939cdbe7530caa1f8a399129e57
--- /dev/null
+++ b/ci-scripts/xml_files/enb_ocp_usrp210_band7_test_05mhz_tm1.xml
@@ -0,0 +1,147 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>test-05-tm1</htmlTabRef>
+ <htmlTabName>Test-05MHz-TM1</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>4</repeatCount>
+ <TestCaseRequestedList>
+ 030201
+ 040101
+ 030101 040301 040501 040603 040604 040605 040606 040607 040641 040642 040643 040644 040401 040201 030201
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="030101">
+ <class>Initialize_eNB</class>
+ <desc>Initialize OCP-eNB (FDD/Band7/5MHz)</desc>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf</Initialize_eNB_args>
+ <air_interface>ocp</air_interface>
+ </testCase>
+
+ <testCase id="030201">
+ <class>Terminate_eNB</class>
+ <desc>Terminate OCP-eNB</desc>
+ <air_interface>ocp</air_interface>
+ </testCase>
+
+ <testCase id="040101">
+ <class>Initialize_UE</class>
+ <desc>Initialize UE</desc>
+ </testCase>
+
+ <testCase id="040201">
+ <class>Terminate_UE</class>
+ <desc>Terminate UE</desc>
+ </testCase>
+
+ <testCase id="040301">
+ <class>Attach_UE</class>
+ <desc>Attach UE</desc>
+ </testCase>
+
+ <testCase id="040401">
+ <class>Detach_UE</class>
+ <desc>Detach UE</desc>
+ </testCase>
+
+ <testCase id="040501">
+ <class>Ping</class>
+ <desc>ping (5MHz - 20 sec)</desc>
+ <ping_args>-c 20</ping_args>
+ <ping_packetloss_threshold>5</ping_packetloss_threshold>
+ </testCase>
+
+ <testCase id="040603">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/15Mbps/UDP)(30 sec)(balanced profile)</desc>
+ <iperf_args>-u -b 15M -t 30 -i 1</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>balanced</iperf_profile>
+ </testCase>
+
+ <testCase id="040604">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/15Mbps/UDP)(30 sec)(single-ue profile)</desc>
+ <iperf_args>-u -b 15M -t 30 -i 1</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>single-ue</iperf_profile>
+ </testCase>
+
+ <testCase id="040605">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/15Mbps/UDP)(30 sec)(unbalanced profile)</desc>
+ <iperf_args>-u -b 15M -t 30 -i 1</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>unbalanced</iperf_profile>
+ </testCase>
+
+ <testCase id="040606">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/TCP)(30 sec)(single-ue profile)</desc>
+ <iperf_args>-t 30 -i 1 -fm</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>single-ue</iperf_profile>
+ </testCase>
+
+ <testCase id="040607">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/TCP)(30 sec)(balanced profile)</desc>
+ <iperf_args>-t 30 -i 1 -fm</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>balanced</iperf_profile>
+ </testCase>
+
+ <testCase id="040641">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - UL/9Mbps/UDP)(30 sec)(balanced profile)</desc>
+ <iperf_args>-u -b 9M -t 30 -i 1 -R</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>balanced</iperf_profile>
+ </testCase>
+
+ <testCase id="040642">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - UL/9Mbps/UDP)(30 sec)(single-ue profile)</desc>
+ <iperf_args>-u -b 9M -t 30 -i 1 -R</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>single-ue</iperf_profile>
+ </testCase>
+
+ <testCase id="040643">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - UL/TCP)(30 sec)(single-ue profile)</desc>
+ <iperf_args>-t 30 -i 1 -fm -R</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>single-ue</iperf_profile>
+ </testCase>
+
+ <testCase id="040644">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - UL/TCP)(30 sec)(balanced profile)</desc>
+ <iperf_args>-t 30 -i 1 -fm -R</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_profile>balanced</iperf_profile>
+ </testCase>
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/enb_ocp_usrp210_build.xml b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml
new file mode 100644
index 0000000000000000000000000000000000000000..33a0fc205e0855de99602abc4f7394e89ad98963
--- /dev/null
+++ b/ci-scripts/xml_files/enb_ocp_usrp210_build.xml
@@ -0,0 +1,38 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>build-tab</htmlTabRef>
+ <htmlTabName>Build</htmlTabName>
+ <htmlTabIcon>wrench</htmlTabIcon>
+ <TestCaseRequestedList>
+ 010101
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="010101">
+ <class>Build_eNB</class>
+ <desc>Build eNB OCP (USRP)</desc>
+ <Build_eNB_args>-w USRP -c --eNBocp --ninja</Build_eNB_args>
+ </testCase>
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml
index 4dbfe008217fa7a8af5eb6e9d0c70bd754b22b33..aac71198f1826ce5440c28e84a6e2c2a4d7807c3 100644
--- a/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml
+++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_epc_start.xml
@@ -25,23 +25,10 @@
<htmlTabName>EPC-Start</htmlTabName>
<htmlTabIcon>log-in</htmlTabIcon>
<TestCaseRequestedList>
- 010101 090101
050101 060101 070101
</TestCaseRequestedList>
<TestCaseExclusionList></TestCaseExclusionList>
- <testCase id="010101">
- <class>Build_eNB</class>
- <desc>Build eNB (USRP)</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
- </testCase>
-
- <testCase id="090101">
- <class>Build_OAI_UE</class>
- <desc>Build OAI UE</desc>
- <Build_OAI_UE_args>-w USRP --UE</Build_OAI_UE_args>
- </testCase>
-
<testCase id="050101">
<class>Initialize_HSS</class>
<desc>Initialize HSS</desc>
diff --git a/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..775ef2e023257733c55b1cf5a822773caa3f808d
--- /dev/null
+++ b/ci-scripts/xml_files/enb_ue_usrp210_band7_test_05mhz_tm1_fembms_no_s1.xml
@@ -0,0 +1,82 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>test-05-tm1-fembms-nos1-tunnel</htmlTabRef>
+ <htmlTabName>Test-05MHz-FEMBMS-TM1-noS1-tunnel</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>2</repeatCount>
+ <TestCaseRequestedList>
+ 030201 090109
+ 030104 000001 090104 000002 040605 000001 090109 030201
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="000001">
+ <class>IdleSleep</class>
+ <desc>Sleep</desc>
+ <idle_sleep_time_in_sec>10</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="000002">
+ <class>IdleSleep</class>
+ <desc>Sleep</desc>
+ <idle_sleep_time_in_sec>15</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="000003">
+ <class>IdleSleep</class>
+ <desc>Sleep</desc>
+ <idle_sleep_time_in_sec>60</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="030104">
+ <class>Initialize_eNB</class>
+ <desc>Initialize eNB (FDD/Band7/5MHz/MBMS)</desc>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band17.tm1.mbms.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --nokrnmod 1 --eNBs.[0].component_carriers.[0].eutra_band 7 --eNBs.[0].component_carriers.[0].downlink_frequency 2680000000 --eNBs.[0].component_carriers.[0].uplink_frequency_offset -120000000 --eNBs.[0].component_carriers.[0].mbms_dedicated_serving_cell ENABLE --MCEs.[0].mbms_sched_info.mbms_area_config_list.[0].pmch_config_list.[0].allocated_sf_end 512</Initialize_eNB_args>
+ </testCase>
+
+ <testCase id="030201">
+ <class>Terminate_eNB</class>
+ <desc>Terminate eNB</desc>
+ </testCase>
+
+ <testCase id="090104">
+ <class>Initialize_OAI_UE</class>
+ <desc>Initialize OAI UE (FDD/Band7/5MHz/MBMS)</desc>
+ <Initialize_OAI_UE_args>-C 2680000000 -r 25 --ue-rxgain 120 --ue-txgain 0 --ue-max-power 0 --ue-scan-carrier --nokrnmod 1 --noS1</Initialize_OAI_UE_args>
+ </testCase>
+
+ <testCase id="090109">
+ <class>Terminate_OAI_UE</class>
+ <desc>Terminate OAI UE</desc>
+ </testCase>
+
+ <testCase id="040605">
+ <class>Iperf</class>
+ <desc>iperf (5MHz - DL/1.5Mbps/UDP/MBMS-sink)(20 sec)</desc>
+ <iperf_args>-c 10.0.2.2 -u -b 1.5M -t 20 -i 1 -fm -B 10.0.2.1</iperf_args>
+ <iperf_packetloss_threshold>50</iperf_packetloss_threshold>
+ <iperf_options>sink</iperf_options>
+ </testCase>
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml
index a28a81d970ccc90bf1ccca42508e2ea5533c0a5e..73d12161994923f717c3c330c2d725710b58200b 100644
--- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml
+++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_no_flexran.xml
@@ -24,6 +24,7 @@
<htmlTabRef>test-05-tm1-rrc-no-flex</htmlTabRef>
<htmlTabName>Test-05MHz-TM1-RRC-Inactivity</htmlTabName>
<htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>2</repeatCount>
<TestCaseRequestedList>
030201
040101
@@ -33,8 +34,8 @@
<testCase id="000001">
<class>IdleSleep</class>
- <desc>Waiting for 35 seconds</desc>
- <idle_sleep_time_in_sec>35</idle_sleep_time_in_sec>
+ <desc>Waiting for 55 seconds</desc>
+ <idle_sleep_time_in_sec>55</idle_sleep_time_in_sec>
</testCase>
<testCase id="000002">
diff --git a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml
index 07cd8fbb304a92e50564d56109089c534ffb35dc..6ee9247ef34c5ae8366693105c6bbd51c6801412 100644
--- a/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml
+++ b/ci-scripts/xml_files/enb_usrp210_band7_test_05mhz_tm1_rrc_inactivity_w_flexran.xml
@@ -36,8 +36,8 @@
<testCase id="000001">
<class>IdleSleep</class>
- <desc>Waiting for 45 seconds</desc>
- <idle_sleep_time_in_sec>45</idle_sleep_time_in_sec>
+ <desc>Waiting for 55 seconds</desc>
+ <idle_sleep_time_in_sec>55</idle_sleep_time_in_sec>
</testCase>
<testCase id="000002">
diff --git a/ci-scripts/xml_files/fr1_multi_node_build.xml b/ci-scripts/xml_files/fr1_multi_node_build.xml
new file mode 100644
index 0000000000000000000000000000000000000000..7b4eacef3a3d091e7397bfc89a7f8422c459998c
--- /dev/null
+++ b/ci-scripts/xml_files/fr1_multi_node_build.xml
@@ -0,0 +1,66 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>build-tab</htmlTabRef>
+ <htmlTabName>Build</htmlTabName>
+ <htmlTabIcon>wrench</htmlTabIcon>
+ <TestCaseRequestedList>
+ 000001 000002
+ 000003 000004
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="000001">
+ <class>Build_eNB</class>
+ <desc>Build eNB</desc>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
+ <eNB_instance>0</eNB_instance>
+ <eNB_serverId>0</eNB_serverId>
+ <backgroundBuild>True</backgroundBuild>
+ </testCase>
+
+ <testCase id="000004">
+ <class>WaitEndBuild_eNB</class>
+ <desc>Wait for end of Build eNB</desc>
+ <eNB_instance>0</eNB_instance>
+ <eNB_serverId>0</eNB_serverId>
+ </testCase>
+
+ <testCase id="000002">
+ <class>Build_eNB</class>
+ <desc>Build gNB</desc>
+ <Build_eNB_args>-w USRP -c --gNB --ninja</Build_eNB_args>
+ <eNB_instance>1</eNB_instance>
+ <eNB_serverId>1</eNB_serverId>
+ <backgroundBuild>True</backgroundBuild>
+ </testCase>
+
+ <testCase id="000003">
+ <class>WaitEndBuild_eNB</class>
+ <desc>Wait for end of Build gNB</desc>
+ <eNB_instance>1</eNB_instance>
+ <eNB_serverId>1</eNB_serverId>
+ </testCase>
+
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/fr1_multi_node_terminate.xml b/ci-scripts/xml_files/fr1_multi_node_terminate.xml
new file mode 100644
index 0000000000000000000000000000000000000000..cbaaf8ba9975a8e464424e0ff258e64a5b3aabac
--- /dev/null
+++ b/ci-scripts/xml_files/fr1_multi_node_terminate.xml
@@ -0,0 +1,50 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>test-fr1-tm1</htmlTabRef>
+ <htmlTabName>Test-FR1-TM1</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>1</repeatCount>
+ <TestCaseRequestedList>
+ 070001
+ 070000
+ </TestCaseRequestedList>
+ <TestCaseExclusionList>
+ </TestCaseExclusionList>
+
+ <testCase id="070000">
+ <class>Terminate_eNB</class>
+ <desc>Terminate eNB</desc>
+ <eNB_instance>0</eNB_instance>
+ <eNB_serverId>0</eNB_serverId>
+ </testCase>
+
+ <testCase id="070001">
+ <class>Terminate_eNB</class>
+ <desc>Terminate gNB</desc>
+ <eNB_instance>1</eNB_instance>
+ <eNB_serverId>1</eNB_serverId>
+ </testCase>
+
+</testCaseList>
+
diff --git a/ci-scripts/xml_files/fr1_multi_node_test.xml b/ci-scripts/xml_files/fr1_multi_node_test.xml
new file mode 100644
index 0000000000000000000000000000000000000000..8c56f0bcec9354394dc622d86675e30ff1281dff
--- /dev/null
+++ b/ci-scripts/xml_files/fr1_multi_node_test.xml
@@ -0,0 +1,77 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>test-fr1-tm1</htmlTabRef>
+ <htmlTabName>Test-FR1-TM1</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>1</repeatCount>
+ <TestCaseRequestedList>
+ 030000
+ 040000
+ 000001
+ 070001
+ 070000
+ </TestCaseRequestedList>
+ <TestCaseExclusionList>
+ </TestCaseExclusionList>
+
+ <testCase id="030000">
+ <class>Initialize_eNB</class>
+ <desc>Initialize eNB</desc>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf</Initialize_eNB_args>
+ <eNB_instance>0</eNB_instance>
+ <eNB_serverId>0</eNB_serverId>
+ <air_interface>lte</air_interface>
+ </testCase>
+
+ <testCase id="040000">
+ <class>Initialize_eNB</class>
+ <desc>Initialize gNB (3/4 sampling rate)</desc>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf -E</Initialize_eNB_args>
+ <eNB_instance>1</eNB_instance>
+ <eNB_serverId>1</eNB_serverId>
+ <air_interface>nr</air_interface>
+ </testCase>
+
+ <testCase id="000001">
+ <class>IdleSleep</class>
+ <desc>Sleep</desc>
+ <idle_sleep_time_in_sec>30</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="070000">
+ <class>Terminate_eNB</class>
+ <desc>Terminate eNB</desc>
+ <eNB_instance>0</eNB_instance>
+ <eNB_serverId>0</eNB_serverId>
+ </testCase>
+
+ <testCase id="070001">
+ <class>Terminate_eNB</class>
+ <desc>Terminate gNB</desc>
+ <eNB_instance>1</eNB_instance>
+ <eNB_serverId>1</eNB_serverId>
+ </testCase>
+
+</testCaseList>
+
diff --git a/ci-scripts/xml_files/fr1_toggle_cots_ue.xml b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b2267efc77dcc514bcf07eda0c2223be3ed5b46a
--- /dev/null
+++ b/ci-scripts/xml_files/fr1_toggle_cots_ue.xml
@@ -0,0 +1,39 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>test-airplane-mode</htmlTabRef>
+ <htmlTabName>AirplaneToggle</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <TestCaseRequestedList>
+ 010000
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="010000">
+ <class>COTS_UE_Airplane</class>
+ <desc>Toggle COTS Airplane mode ON</desc>
+ <cots_ue_airplane_args>ON</cots_ue_airplane_args>
+ </testCase>
+
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml
index f3e80c576acac4c76e4dd24b0e04e61e8dbe7fd3..c51093c1785b26267a71bd3a03a3d42580dd1560 100644
--- a/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml
+++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run.xml
@@ -52,7 +52,7 @@
<testCase id="090102">
<class>Initialize_OAI_UE</class>
<desc>Initialize NR UE USRP</desc>
- <Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path ci-scripts/rrc-files</Initialize_OAI_UE_args>
+ <Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path .</Initialize_OAI_UE_args>
<air_interface>NR</air_interface>
</testCase>
diff --git a/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b4290ae6a3da69eae76ad7e8359a3df1272483b7
--- /dev/null
+++ b/ci-scripts/xml_files/gnb_nr_ue_usrp_run_multi_thread.xml
@@ -0,0 +1,71 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+-->
+<testCaseList>
+ <htmlTabRef>run-oai-gnb-nr-ue-tx-write-thread</htmlTabRef>
+ <htmlTabName>Run-gNB-and-NR-UE-TX-Write-Thread</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>2</repeatCount>
+ <TestCaseRequestedList>
+090103 000001 090104 000002 090108 090109
+ </TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="090103">
+ <class>Initialize_eNB</class>
+ <desc>Initialize gNB USRP (Tx-Write-Threading enabled)</desc>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test --usrp-tx-thread-config 1</Initialize_eNB_args>
+ <air_interface>NR</air_interface>
+ </testCase>
+
+ <testCase id="000001">
+ <class>IdleSleep</class>
+ <desc>Sleep</desc>
+ <idle_sleep_time_in_sec>5</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="000002">
+ <class>IdleSleep</class>
+ <desc>Waiting for NR UE to synchronize w/ gNB</desc>
+ <idle_sleep_time_in_sec>180</idle_sleep_time_in_sec>
+ </testCase>
+
+ <testCase id="090104">
+ <class>Initialize_OAI_UE</class>
+ <desc>Initialize NR UE USRP</desc>
+ <Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --threadoffset 16 --rrc_config_path .</Initialize_OAI_UE_args>
+ <air_interface>NR</air_interface>
+ </testCase>
+
+ <testCase id="090108">
+ <class>Terminate_OAI_UE</class>
+ <desc>Terminate NR UE</desc>
+ <air_interface>NR</air_interface>
+ </testCase>
+
+ <testCase id="090109">
+ <class>Terminate_eNB</class>
+ <desc>Terminate gNB</desc>
+ <air_interface>NR</air_interface>
+ </testCase>
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/gnb_usrp_build.xml b/ci-scripts/xml_files/gnb_usrp_build.xml
index bba92930c51eed145afe6df831defea38d3ef5c5..e2662180c5b8fee0c2974e703328a30673eb5193 100644
--- a/ci-scripts/xml_files/gnb_usrp_build.xml
+++ b/ci-scripts/xml_files/gnb_usrp_build.xml
@@ -24,6 +24,7 @@
<htmlTabRef>gnb-build-tab</htmlTabRef>
<htmlTabName>Build-gNB</htmlTabName>
<htmlTabIcon>wrench</htmlTabIcon>
+ <repeatCount>4</repeatCount>
<TestCaseRequestedList>
010101
</TestCaseRequestedList>
@@ -33,7 +34,7 @@
<mode>TesteNB</mode>
<class>Build_eNB</class>
<desc>Build gNB (USRP)</desc>
- <Build_eNB_args>--gNB -w USRP</Build_eNB_args>
+ <Build_eNB_args>--gNB -w USRP --ninja</Build_eNB_args>
<forced_workspace_cleanup>True</forced_workspace_cleanup>
</testCase>
diff --git a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml
index e1644f393125ea4fd1ed2697a50593da3e7d8ae7..8276294e9af23a63adafd13786be22d81365b295 100644
--- a/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml
+++ b/ci-scripts/xml_files/if4p5_usrp210_band40_test_10mhz.xml
@@ -24,6 +24,7 @@
<htmlTabRef>test-10</htmlTabRef>
<htmlTabName>Test-10MHz</htmlTabName>
<htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>2</repeatCount>
<TestCaseRequestedList>
030201
040101
diff --git a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml
index 0196bf1ab6532d2a2e757abf93b25eb69a5306cc..ae348b6b259d94f44ac379d682079ccf8e355878 100644
--- a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml
+++ b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1.xml
@@ -46,7 +46,7 @@
<testCase id="030102">
<class>Initialize_eNB</class>
<desc>Initialize eNB (FDD/Band7/5MHz)</desc>
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT</Initialize_eNB_args>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95</Initialize_eNB_args>
</testCase>
<testCase id="030201">
diff --git a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml
index c2835d04615d93450eeaba6ef66d802665fa762a..b77c6273e6873a9f37cf3427b4a76bd998cdc49d 100644
--- a/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml
+++ b/ci-scripts/xml_files/inria/enb_ue_usrp210_band7_test_05mhz_tm1_nos1.xml
@@ -52,7 +52,7 @@
<testCase id="030101">
<class>Initialize_eNB</class>
<desc>Initialize eNB (FDD/Band7/5MHz)</desc>
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT</Initialize_eNB_args>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --noS1 --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95</Initialize_eNB_args>
</testCase>
<testCase id="030201">
diff --git a/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml
index 964550d872b46b7b2426902906495c8f310077d8..df41385f83899c751ba1e492a45fff139680c2e8 100644
--- a/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml
+++ b/ci-scripts/xml_files/inria/enb_usrp210_band7_test_05mhz_tm1.xml
@@ -93,7 +93,7 @@
<testCase id="030103">
<class>Initialize_eNB</class>
<desc>Initialize eNB (FDD/Band7/5MHz)</desc>
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT</Initialize_eNB_args>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95</Initialize_eNB_args>
</testCase>
<testCase id="030201">
diff --git a/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml b/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml
index 8116b9dcdf316a0f36cd5bfc48122b165416c4ab..852f48c370e2b2a7455857d6c07250cada0030af 100644
--- a/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml
+++ b/ci-scripts/xml_files/inria/enb_usrp210_band7_x2_ho_test_05Mhz_tm1.xml
@@ -64,7 +64,7 @@
<testCase id="030104">
<class>Initialize_eNB</class>
<desc>Initialize eNB #0 (FDD/Band7/5MHz)</desc>
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 123456</Initialize_eNB_args>
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 123456</Initialize_eNB_args>
<eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId>
</testCase>
@@ -72,11 +72,7 @@
<testCase id="030105">
<class>Initialize_eNB</class>
<desc>Initialize eNB #1 (FDD/Band7/5MHz)</desc>
-<<<<<<< HEAD
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].target_enb_x2_ip_address.[0].ipv4 CI_RCC_IP_ADDR --eNBs.[0].target_enb_x2_ip_address.[0].preference ipv4 --eNBs.[0].eNB_ID 0xe01 --eNBs.[0].component_carriers.[0].Nid_cell 1 --eNBs.[0].nr_cellid 98765</Initialize_eNB_args>
-=======
- <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.slave.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --THREAD_STRUCT.[0].parallel_config PARALLEL_RU_L1_TRX_SPLIT --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 98765</Initialize_eNB_args>
->>>>>>> origin/develop_inria_ci_deployment
+ <Initialize_eNB_args>-O ci-scripts/conf_files/enb.band7.tm1.25PRB.slave.usrpb210.conf --eNBs.[0].rrc_inactivity_threshold 0 --RUs.[0].max_rxgain 120 --eNBs.[0].component_carriers.[0].pusch_p0_Nominal -90 --eNBs.[0].component_carriers.[0].pucch_p0_Nominal -96 --eNBs.[0].tracking_area_code 600 --eNBs.[0].plmn_list.[0].mnc 95 --eNBs.[0].enable_measurement_reports yes --eNBs.[0].enable_x2 yes --eNBs.[0].nr_cellid 98765</Initialize_eNB_args>
<eNB_instance>1</eNB_instance>
<eNB_serverId>1</eNB_serverId>
</testCase>
diff --git a/ci-scripts/xml_files/ldpc_gpu_test.xml b/ci-scripts/xml_files/ldpc_gpu_test.xml
new file mode 100644
index 0000000000000000000000000000000000000000..a0191fbd7683d4ac339c55ba63aa1f2475c39970
--- /dev/null
+++ b/ci-scripts/xml_files/ldpc_gpu_test.xml
@@ -0,0 +1,161 @@
+<!--
+
+ Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ contributor license agreements. See the NOTICE file distributed with
+ this work for additional information regarding copyright ownership.
+ The OpenAirInterface Software Alliance licenses this file to You under
+ the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.openairinterface.org/?page_id=698
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ For more information about the OpenAirInterface (OAI) Software Alliance:
+ contact@openairinterface.org
+
+ 030105 040301 040502 040606 040601 040603 040608 040605 040646 040641 040643 040648 040645 040401 040201 030201
+-->
+<testCaseList>
+ <htmlTabRef>test-ldpc-gpu</htmlTabRef>
+ <htmlTabName>Test-ldpc-GPU</htmlTabName>
+ <htmlTabIcon>tasks</htmlTabIcon>
+ <repeatCount>1</repeatCount>
+ <TestCaseRequestedList>000001 000002 000003 000004 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 000020 000021</TestCaseRequestedList>
+ <TestCaseExclusionList></TestCaseExclusionList>
+
+ <testCase id="000001">
+ <class>Build_PhySim</class>
+ <desc>Build for physical simulator</desc>
+ <physim_build_args>--phy_simulators --ninja</physim_build_args>
+ <forced_workspace_cleanup>FALSE</forced_workspace_cleanup>
+ </testCase>
+
+ <testCase id="000002">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 3872 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000003">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 3872 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000004">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 4224 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000005">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 4224 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000006">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 4576 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000007">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 4576 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000008">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 4928 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000009">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 4928 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000010">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 5280 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000011">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 5280 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000012">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 5632 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000013">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 5632 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000014">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 6336 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000015">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 6336 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000016">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 7040 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000017">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 7040 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000018">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 7744 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000019">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 7744 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+ <testCase id="000020">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with CPU</desc>
+ <physim_run_args>-l 8448 -s10 -n100</physim_run_args>
+ </testCase>
+
+ <testCase id="000021">
+ <class>Run_PhySim</class>
+ <desc>Run LDPC Test with GPU</desc>
+ <physim_run_args>-l 8448 -s10 -n100 -G 1</physim_run_args>
+ </testCase>
+
+
+
+</testCaseList>
diff --git a/ci-scripts/xml_files/multi_rru_band38_build.xml b/ci-scripts/xml_files/multi_rru_band38_build.xml
index 614ef394f3307d89cee917d7f78c2fd9fc790835..ba45eab10a35e8db259457d7578f3a1e694761ad 100644
--- a/ci-scripts/xml_files/multi_rru_band38_build.xml
+++ b/ci-scripts/xml_files/multi_rru_band38_build.xml
@@ -33,7 +33,7 @@
<testCase id="010101">
<class>Build_eNB</class>
<desc>Build RCC</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId>
<backgroundBuild>True</backgroundBuild>
@@ -42,7 +42,7 @@
<testCase id="000101">
<class>WaitEndBuild_eNB</class>
<desc>Wait for end of Build RCC</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>0</eNB_instance>
<eNB_serverId>0</eNB_serverId>
</testCase>
@@ -50,7 +50,7 @@
<testCase id="010102">
<class>Build_eNB</class>
<desc>Build Master RRU</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>1</eNB_instance>
<eNB_serverId>1</eNB_serverId>
<backgroundBuild>True</backgroundBuild>
@@ -59,7 +59,7 @@
<testCase id="000102">
<class>WaitEndBuild_eNB</class>
<desc>Wait for end of Build Master RRU</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>1</eNB_instance>
<eNB_serverId>1</eNB_serverId>
</testCase>
@@ -67,7 +67,7 @@
<testCase id="010103">
<class>Build_eNB</class>
<desc>Build Slave RRU</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>2</eNB_instance>
<eNB_serverId>2</eNB_serverId>
<backgroundBuild>True</backgroundBuild>
@@ -76,7 +76,7 @@
<testCase id="000103">
<class>WaitEndBuild_eNB</class>
<desc>Wait for end of Build Slave RRU</desc>
- <Build_eNB_args>-w USRP -c --eNB</Build_eNB_args>
+ <Build_eNB_args>-w USRP -c --eNB --ninja</Build_eNB_args>
<eNB_instance>2</eNB_instance>
<eNB_serverId>2</eNB_serverId>
</testCase>
diff --git a/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml b/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml
index 7658f8a0e5069a975d3477184eaabd9ee6646210..cca14c0696253f1f87b5c3c88a8f6ffe4c3ff1b0 100644
--- a/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml
+++ b/ci-scripts/xml_files/multi_rru_band38_test_10mhz_tm1.xml
@@ -24,7 +24,7 @@
<htmlTabRef>test-multi-rru-10</htmlTabRef>
<htmlTabName>Test-Multi-RRU-10MHz</htmlTabName>
<htmlTabIcon>tasks</htmlTabIcon>
- <repeatCount>4</repeatCount>
+ <repeatCount>2</repeatCount>
<TestCaseRequestedList>
030211 030212 030213
030111 030112 030113
diff --git a/ci-scripts/xml_files/nr_ue_usrp_build.xml b/ci-scripts/xml_files/nr_ue_usrp_build.xml
index 7d8d97d2c5276e6b7b3feac3df842c627e1b03f6..bc04efdb4b8cd50ffd7905196f2f14b941db14ab 100644
--- a/ci-scripts/xml_files/nr_ue_usrp_build.xml
+++ b/ci-scripts/xml_files/nr_ue_usrp_build.xml
@@ -24,6 +24,7 @@
<htmlTabRef>nr-ue-build-tab</htmlTabRef>
<htmlTabName>Build-NR-UE</htmlTabName>
<htmlTabIcon>wrench</htmlTabIcon>
+ <repeatCount>2</repeatCount>
<TestCaseRequestedList>
010102
</TestCaseRequestedList>
@@ -33,7 +34,7 @@
<mode>TestUE</mode>
<class>Build_OAI_UE</class>
<desc>Build NR UE (USRP)</desc>
- <Build_OAI_UE_args>--nrUE -w USRP</Build_OAI_UE_args>
+ <Build_OAI_UE_args>--nrUE -w USRP --ninja</Build_OAI_UE_args>
<clean_repository>false</clean_repository>
</testCase>
diff --git a/cmake_targets/CMakeLists.txt b/cmake_targets/CMakeLists.txt
index 51ec0bc4d72bf57be729d89efb8a8a1d708a850b..29c1dc9ad54290c41c829b0b47750cdd5e4b6c25 100644
--- a/cmake_targets/CMakeLists.txt
+++ b/cmake_targets/CMakeLists.txt
@@ -27,6 +27,10 @@ cmake_minimum_required (VERSION 3.0)
# Base directories, compatible with legacy OAI building #
#########################################################
set (OPENAIR_DIR $ENV{OPENAIR_DIR})
+if("${OPENAIR_DIR}" STREQUAL "")
+ string(REGEX REPLACE "/cmake_targets.*$" "" OPENAIR_DIR ${CMAKE_CURRENT_BINARY_DIR})
+endif()
+
set (NFAPI_DIR ${OPENAIR_DIR}/nfapi/open-nFAPI)
set (NFAPI_USER_DIR ${OPENAIR_DIR}/nfapi/oai_integration)
set (OPENAIR1_DIR ${OPENAIR_DIR}/openair1)
@@ -39,6 +43,33 @@ set (OPENAIR_BIN_DIR ${CMAKE_CURRENT_BINARY_DIR}${CMAKE_FILES_DIRECTORY})
project (OpenAirInterface)
+
+
+##############################################
+# Base CUDA setting
+##############################################
+find_package(CUDA)
+if (CUDA_FOUND)
+ message ("cuda include ${CUDA_INCLUDE_DIRS}")
+ message ("cuda library ${CUDA_LIBRARY_DIRS}")
+
+ add_definitions("-L/usr/local/cuda/lib64")
+
+ SET(CUDA_NVCC_FLAGS
+ "${CUDA_NVCC_FLAGS};-arch=sm_60;")
+
+ # Disable warnings for CUDA
+ SET(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS};-lpthread;-w;-O3;--default-stream;per-thread;-I/usr/local/cuda/inc;-L/usr/local/cuda/lib -lcutil;-rdc=true;-lcudadevrt")
+ SET(CUDA_VERBOSE_BUILD ON)
+ SET(CUDA_HOST_COMPILER "/usr/bin/g++")
+
+ SET(CUDA_SEPARABLE_COMPILATION ON)
+
+else (CUDA_FOUND)
+ message ("No CUDA tool installed")
+endif ()
+
+
###########################################
# macros to define options as there is numerous options in oai
################################################
@@ -172,15 +203,32 @@ Message("C_FLAGS_PROCESSOR is ${C_FLAGS_PROCESSOR}")
#
set(CMAKE_C_FLAGS
- "${CMAKE_C_FLAGS} ${C_FLAGS_PROCESSOR} -std=gnu99 -Wall -fopenmp -Wstrict-prototypes -fno-strict-aliasing -rdynamic -funroll-loops -Wno-packed-bitfield-compat -fPIC")
+ "${CMAKE_C_FLAGS} ${C_FLAGS_PROCESSOR} -pipe -std=gnu99 -Wall -Wstrict-prototypes -fno-strict-aliasing -rdynamic -funroll-loops -Wno-packed-bitfield-compat -fPIC")
# add autotools definitions that were maybe used!
-set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'")
-set(CMAKE_C_FLAGS
- "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER}"
-)
-set(CMAKE_CXX_FLAGS
+if (CUDA_FOUND)
+ set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'")
+ set(CUDA_CMAKE_C_FLAGS
+ "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D CUDA_FLAG"
+ )
+ set(CUDA_CMAKE_CXX_FLAGS
+ "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D CUDA_FLAG"
+ )
+
+ set(CMAKE_C_FLAGS
+ "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER} -D CUDA_FLAG"
+ )
+ set(CMAKE_CXX_FLAGS
+ "${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D${MKVER} -D CUDA_FLAG"
+ )
+else (CUDA_FOUND)
+ set(MKVER "'MAKE_VERSION(a,b,c)=((a)*256+(b)*16+c)'")
+ set(CMAKE_C_FLAGS
+ "${CMAKE_C_FLAGS} -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_FCNTL_H=1 -DHAVE_ARPA_INET_H=1 -DHAVE_SYS_TIME_H=1 -DHAVE_SYS_SOCKET_H=1 -DHAVE_STRERROR=1 -DHAVE_SOCKET=1 -DHAVE_MEMSET=1 -DHAVE_GETTIMEOFDAY=1 -DHAVE_STDLIB_H=1 -DHAVE_MALLOC=1 -DHAVE_LIBSCTP -D${MKVER}"
+ )
+ set(CMAKE_CXX_FLAGS
"${CMAKE_CXX_FLAGS} ${C_FLAGS_PROCESSOR} -Wno-packed-bitfield-compat -fPIC -Wall -fno-strict-aliasing -rdynamic -std=c++11 -D${MKVER}"
-)
+ )
+endif ()
add_definitions("-DASN_DISABLE_OER_SUPPORT")
@@ -1213,7 +1261,7 @@ set(SCHED_SRC_NR_UE
${OPENAIR1_DIR}/SCHED_NR_UE/phy_procedures_nr_ue.c
${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_common.c
${OPENAIR1_DIR}/SCHED_NR_UE/fapi_nr_ue_l1.c
- ${OPENAIR1_DIR}/SCHED_NR/phy_frame_config_nr.c
+ ${OPENAIR1_DIR}/SCHED_NR_UE/phy_frame_config_nr_ue.c
${OPENAIR1_DIR}/SCHED_NR_UE/harq_nr.c
${OPENAIR1_DIR}/SCHED_NR_UE/pucch_uci_ue_nr.c
${OPENAIR1_DIR}/SCHED_NR_UE/pucch_power_control_ue_nr.c
@@ -1503,6 +1551,8 @@ set(PHY_SRC_UE
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold.c
+ ${OPENAIR1_DIR}/PHY/NR_REFSIG/scrambling_luts.c
+ ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gen_mod_table.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c
${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c
@@ -1524,6 +1574,7 @@ set(PHY_SRC_UE
${PHY_SMALLBLOCKSRC}
${PHY_NR_CODINGIF}
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/pucch_rx.c
+ ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_uci_tools_common.c
)
set(PHY_NR_UE_SRC
${OPENAIR1_DIR}/PHY/INIT/nr_parms.c
@@ -1547,12 +1598,14 @@ set(PHY_SRC_UE
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/dci_nr.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/pucch_nr.c
+ ${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_uci_tools_common.c
${OPENAIR1_DIR}/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/ul_ref_seq_nr.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_dmrs_rx.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/dmrs_nr.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/ptrs_nr.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold_ue.c
+ ${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gen_mod_table.c
${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/filt16a_32.c
${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
${OPENAIR1_DIR}/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c
@@ -1632,7 +1685,7 @@ add_library(PHY_MEX ${PHY_MEX_UE} ${CONFIG_LIB})
#Layer 2 library
#####################
set(MAC_DIR ${OPENAIR2_DIR}/LAYER2/MAC)
-set(NR_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB)
+set(NR_GNB_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB)
set(NR_UE_MAC_DIR ${OPENAIR2_DIR}/LAYER2/NR_MAC_UE)
set(PHY_INTERFACE_DIR ${OPENAIR2_DIR}/PHY_INTERFACE)
set(NR_PHY_INTERFACE_DIR ${OPENAIR2_DIR}/NR_PHY_INTERFACE)
@@ -1788,20 +1841,22 @@ set (MAC_SRC
${MAC_DIR}/eNB_scheduler_fairRR.c
${MAC_DIR}/eNB_scheduler_phytest.c
${MAC_DIR}/pre_processor.c
+ ${MAC_DIR}/slicing/slicing.c
${MAC_DIR}/config.c
${MAC_DIR}/config_ue.c
)
set (MAC_NR_SRC
${NR_PHY_INTERFACE_DIR}/NR_IF_Module.c
- ${NR_MAC_DIR}/main.c
- ${NR_MAC_DIR}/config.c
- ${NR_MAC_DIR}/gNB_scheduler.c
- ${NR_MAC_DIR}/gNB_scheduler_bch.c
- ${NR_MAC_DIR}/gNB_scheduler_dlsch.c
- ${NR_MAC_DIR}/gNB_scheduler_ulsch.c
- ${NR_MAC_DIR}/gNB_scheduler_primitives.c
- ${NR_MAC_DIR}/gNB_scheduler_phytest.c
+ ${NR_GNB_MAC_DIR}/main.c
+ ${NR_GNB_MAC_DIR}/config.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_bch.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_dlsch.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_ulsch.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_primitives.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_phytest.c
+ ${NR_GNB_MAC_DIR}/gNB_scheduler_RA.c
)
@@ -1813,7 +1868,6 @@ set (MAC_SRC_UE
${MAC_DIR}/l1_helpers.c
${MAC_DIR}/rar_tools_ue.c
${MAC_DIR}/config_ue.c
-
)
set (MAC_NR_SRC_UE
@@ -1823,6 +1877,9 @@ set (MAC_NR_SRC_UE
${NR_UE_MAC_DIR}/main_ue_nr.c
${NR_UE_MAC_DIR}/nr_ue_procedures.c
${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c
+ ${NR_UE_MAC_DIR}/nr_l1_helpers.c
+ ${NR_UE_MAC_DIR}/nr_ra_procedures.c
+ ${NR_UE_MAC_DIR}/rar_tools_nrUE.c
)
set (ENB_APP_SRC
@@ -1886,7 +1943,7 @@ add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} )
add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_COMMON/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c)
include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE")
-include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE")
+include_directories("${OPENAIR2_DIR}/LAYER2")
include_directories("${OPENAIR1_DIR}/SCHED_NR_UE")
#include_directories("${NFAPI_USER_DIR}"")
@@ -1914,6 +1971,19 @@ set (GTPV1U_SRC
add_library(GTPV1U ${GTPV1U_SRC})
add_dependencies(GTPV1U rrc_flag)
+#NR case
+set (NR_GTPV1U_SRC
+ ${NR_RRC_DIR}/rrc_gNB_GTPV1U.c
+ ${RRC_DIR}/rrc_eNB_GTPV1U.c
+ ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTunnelEndPoint.c
+ ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uTrxn.c
+ ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1uMsg.c
+ ${GTPV1U_DIR}/nw-gtpv1u/src/NwGtpv1u.c
+ ${GTPV1U_DIR}/gtpv1u_teid_pool.c
+)
+add_library(NR_GTPV1U ${NR_GTPV1U_SRC})
+add_dependencies(NR_GTPV1U rrc_flag)
+
set (MME_APP_SRC
${OPENAIR3_DIR}/MME_APP/mme_app.c
${OPENAIR3_DIR}/MME_APP/mme_config.c
@@ -2241,26 +2311,28 @@ add_library(LFDS7
${lfds7_queue} ${lfds7_ring} ${lfds7_qbss} ${lfds7_stack} ${lfds7_freelist} ${lfds7_btree} ${lfds7_hash} ${lfds7_ordered_list} ${lfds7_unordered_list} ${lfds7_misc}
)
+add_library(SIMU_COMMON
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/random_channel.c
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/rangen_double.c
+ )
+
# Simulation library
##########################
set (SIMUSRC
-${OPENAIR1_DIR}/SIMULATION/TOOLS/random_channel.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/rangen_double.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_channel.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_tv_channel.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/abstraction.c
-${OPENAIR1_DIR}/SIMULATION/TOOLS/channel_sim.c
-${OPENAIR1_DIR}/SIMULATION/RF/rf.c
-${OPENAIR1_DIR}/SIMULATION/RF/dac.c
-${OPENAIR1_DIR}/SIMULATION/RF/adc.c
-${OPENAIR_DIR}/targets/ARCH/rfsimulator/apply_channelmod.c
-#${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
-)
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_channel.c
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/multipath_tv_channel.c
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/abstraction.c
+ ${OPENAIR1_DIR}/SIMULATION/TOOLS/channel_sim.c
+ ${OPENAIR1_DIR}/SIMULATION/RF/rf.c
+ ${OPENAIR1_DIR}/SIMULATION/RF/dac.c
+ ${OPENAIR1_DIR}/SIMULATION/RF/adc.c
+ #${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
+ )
# Simulation library
##########################
-add_library( SIMU SHARED ${SIMUSRC} )
+add_library(SIMU SHARED ${SIMUSRC} )
add_library(SIMU_ETH
${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
@@ -2413,14 +2485,16 @@ add_library(uescope MODULE ${XFORMS_SOURCE} ${XFORMS_SOURCE_SOFTMODEM} ${XFORMS_
target_link_libraries(enbscope ${XFORMS_LIBRARIES})
target_link_libraries(uescope ${XFORMS_LIBRARIES})
-add_library(gnbscope MODULE ${XFORMS_SOURCE_NR})
-target_link_libraries(gnbscope ${XFORMS_LIBRARIES})
+add_library(nrscope MODULE ${XFORMS_SOURCE_NR})
+target_link_libraries(nrscope ${XFORMS_LIBRARIES})
add_library(rfsimulator MODULE
- ${OPENAIR_TARGETS}/ARCH/rfsimulator/simulator.c
+ ${OPENAIR_TARGETS}/ARCH/rfsimulator/simulator.c
+ ${OPENAIR_TARGETS}/ARCH/rfsimulator/apply_channelmod.c
+ ${OPENAIR_TARGETS}/ARCH/rfsimulator/new_channel_sim.c
)
-target_link_libraries(rfsimulator SIMU ${ATLAS_LIBRARIES})
+target_link_libraries(rfsimulator SIMU_COMMON ${ATLAS_LIBRARIES})
add_library(oai_iqplayer MODULE
${OPENAIR_TARGETS}/ARCH/iqplayer/iqplayer_lib.c
@@ -2442,9 +2516,9 @@ endif (${T_TRACER})
#This rule and the following deal with it.
add_custom_command (
OUTPUT ${OPENAIR_DIR}/common/utils/T/T_IDs.h
- COMMAND $(MAKE) clean
- COMMAND $(MAKE)
- COMMAND $(MAKE) check_vcd
+ COMMAND make clean
+ COMMAND make -j2
+ COMMAND make check_vcd
WORKING_DIRECTORY ${OPENAIR_DIR}/common/utils/T
DEPENDS ${OPENAIR_DIR}/common/utils/T/T_messages.txt
${OPENAIR_DIR}/common/utils/LOG/vcd_signal_dumper.c
@@ -2561,12 +2635,12 @@ add_executable(ocp-enb
${CONFIG_SOURCES}
${SHLIB_LOADER_SOURCES}
)
-add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer)
+add_dependencies(ocp-enb rrc_flag s1ap_flag x2_flag oai_iqplayer coding params_libconfig rfsimulator)
target_link_libraries (ocp-enb
-Wl,--start-group
RRC_LIB NR_RRC_LIB S1AP_LIB S1AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB X2AP_LIB X2AP_ENB M3AP_LIB M3AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_LIB SCHED_RU_LIB
- PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7
+ PHY_COMMON PHY PHY_RU LFDS L2 L2_LTE NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB LFDS7 SIMU_COMMON
${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} ${FSPT_MSG_LIB} ${PROTO_AGENT_LIB}
-Wl,--end-group z dl)
target_link_libraries (ocp-enb ${LIBXML2_LIBRARIES} pthread m ${CONFIG_LIBRARIES} rt crypt ${CRYPTO_LIBRARIES} ${OPENSSL_LIBRARIES} ${NETTLE_LIBRARIES} sctp ${PROTOBUF_LIB} ${CMAKE_DL_LIBS} ${LIBYAML_LIBRARIES} ${LIB_LMS_LIBRARIES} ${T_LIB})
@@ -2636,7 +2710,7 @@ target_link_libraries (lte-uesoftmodem
-Wl,--start-group
RRC_LIB S1AP_LIB S1AP_ENB X2AP_LIB X2AP_ENB M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB F1AP F1AP_LIB
GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT MME_APP UDP SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON
- PHY_UE PHY_RU LFDS L2_UE L2_LTE LFDS7 SIMU NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB
+ PHY_UE PHY_RU LFDS L2_UE L2_LTE LFDS7 SIMU_COMMON SIMU NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB
${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${ATLAS_LIBRARIES}
-Wl,--end-group z dl)
@@ -2662,12 +2736,13 @@ add_executable(nr-softmodem
${OPENAIR_TARGETS}/ARCH/COMMON/record_player.c
${OPENAIR2_DIR}/RRC/NAS/nas_config.c
${OPENAIR2_DIR}/RRC/NAS/rb_config.c
+ ${OPENAIR3_DIR}/GTPV1-U/gtpv1u_gNB.c
${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
${OPENAIR_DIR}/common/utils/utils.c
${OPENAIR_DIR}/common/utils/system.c
${OPENAIR_DIR}/common/utils/nr/nr_common.c
${GTPU_need_ITTI}
- ${XFORMS_SOURCE_NR}
+ ${XFORMSINTERFACE_SOURCE}
${T_SOURCE}
${CONFIG_SOURCES}
${SHLIB_LOADER_SOURCES}
@@ -2675,7 +2750,7 @@ add_executable(nr-softmodem
target_link_libraries (nr-softmodem
-Wl,--start-group
- UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS GTPV1U SECU_CN SECU_OSA
+ UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB SCHED_RU_LIB SCHED_NR_LIB PHY_NR PHY PHY_COMMON PHY_NR_COMMON PHY_RU LFDS NR_GTPV1U SECU_CN SECU_OSA
${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} LFDS7 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} RRC_LIB NR_RRC_LIB
S1AP_LIB S1AP_ENB L2 L2_NR MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_VNF_LIB NFAPI_PNF_LIB NFAPI_USER_LIB
X2AP_LIB X2AP_ENB F1AP_LIB F1AP M2AP_LIB M2AP_ENB M3AP_LIB M3AP_ENB ${PROTO_AGENT_LIB} ${FSPT_MSG_LIB}
@@ -2709,7 +2784,7 @@ add_executable(nr-uesoftmodem
${OPENAIR_DIR}/common/utils/utils.c
${OPENAIR_DIR}/common/utils/system.c
${OPENAIR_DIR}/common/utils/nr/nr_common.c
- ${XFORMS_SOURCE_NR}
+ ${XFORMSINTERFACE_SOURCE}
${T_SOURCE}
${UTIL_SRC}
${CONFIG_SOURCES}
@@ -2719,9 +2794,9 @@ add_executable(nr-uesoftmodem
target_link_libraries (nr-uesoftmodem
-Wl,--start-group
RRC_LIB NR_RRC_LIB SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT UDP SCHED_RU_LIB SCHED_UE_LIB SCHED_NR_UE_LIB
+ PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS NR_L2_UE L2_UE MAC_NR_COMMON NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB
+ NFAPI_USER_LIB S1AP_LIB S1AP_ENB
${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} LFDS7 ${ATLAS_LIBRARIES}
- PHY_COMMON PHY_NR_COMMON PHY_UE PHY_NR_UE PHY_RU LFDS L2_UE NR_L2_UE MAC_NR_COMMON S1AP_LIB S1AP_ENB
- NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_USER_LIB
-Wl,--end-group z dl)
target_link_libraries (nr-uesoftmodem ${LIBXML2_LIBRARIES})
@@ -2731,29 +2806,6 @@ target_link_libraries (nr-uesoftmodem ${T_LIB})
add_dependencies( nr-uesoftmodem ldpc_orig ldpc_optim ldpc_optim8seg ldpc )
-# USIM process
-#################
-#add_executable(usim
-# ${OPENAIR3_DIR}/NAS/TOOLS/usim_data.c
-# ${OPENAIR3_DIR}/NAS/USER/API/USIM/usim_api.c
-# ${OPENAIR3_DIR}/NAS/USER/API/USIM/aka_functions.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/memory.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/nas_log.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/OctetString.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/TLVEncoder.c
-# )
-#target_link_libraries (usim ${NAS_LIB} UTIL ${ITTI_LIB} LFDS pthread rt nettle crypto m)
-
-# ???
-#####################
-#add_executable(nvram
-# ${OPENAIR3_DIR}/NAS/TOOLS/ue_data.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/memory.c
-# ${OPENAIR3_DIR}/NAS/COMMON/UTIL/nas_log.c
-# )
-#target_link_libraries (nvram LIB_NAS_UE UTIL ${ITTI_LIB} LFDS pthread rt nettle crypto m)
-
-
###################################"
# Addexecutables for tests
####################################
@@ -2770,7 +2822,7 @@ add_executable(dlsim_tm4
${T_SOURCE}
)
target_link_libraries (dlsim_tm4
- -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB PHY LFDS ${ITTI_LIB} -Wl,--end-group
+ -Wl,--start-group SIMU_COMMON SIMU UTIL SCHED_LIB SCHED_RU_LIB PHY LFDS ${ITTI_LIB} -Wl,--end-group
pthread m rt ${CONFIG_LIB} ${ATLAS_LIBRARIES} ${T_LIB}
)
@@ -2783,7 +2835,7 @@ add_executable(polartest
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(polartest
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE CONFIG_LIB -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE CONFIG_LIB -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} dl
)
@@ -2798,44 +2850,88 @@ add_executable(smallblocktest
target_link_libraries(smallblocktest
- -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} dl
)
-add_executable(ldpctest
- ${PHY_NR_CODINGIF}
- ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c
- ${T_SOURCE}
- ${SHLIB_LOADER_SOURCES}
- )
+
+# temp_C_flag = CMAKE_C_FLAGS
+#set(CMAKE_C_FLAGS " ")
+set (TEMP_C_FLAG ${CMAKE_C_FLAGS})
+set (CMAKE_C_FLAGS ${CUDA_CMAKE_C_FLAGS})
+
+set (TEMP_CXX_FLAG ${CMAKE_CXX_FLAGS})
+set (CMAKE_CXX_FLAGS ${CUDA_CMAKE_CXX_FLAGS})
+if (CUDA_FOUND)
+###################################################
+# For CUDA library
+###################################################
+
+ CUDA_ADD_LIBRARY(LDPC_CU
+ ${OPENAIR1_DIR}/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu
+ )
+ CUDA_ADD_CUFFT_TO_TARGET(LDPC_CU)
+ cuda_add_executable(ldpctest
+ ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c
+ ${T_SOURCE}
+ ${SHLIB_LOADER_SOURCES}
+ )
+ target_link_libraries(ldpctest -ldl
+ -Wl,--start-group
+ LDPC_CU UTIL SIMU PHY_NR CONFIG_LIB
+ -Wl,--end-group
+ m pthread ${ATLAS_LIBRARIES} dl
+ )
+
+else (CUDA_FOUND)
+ add_executable(ldpctest
+ ${PHY_NR_CODINGIF}
+ ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c
+ ${T_SOURCE}
+ ${SHLIB_LOADER_SOURCES}
+ )
+
+endif ()
+set (CMAKE_C_FLAGS ${TEMP_C_FLAG})
+set (CMAKE_CXX_FLAGS ${TEMP_CXX_FLAG})
+
+
+# add_executable(ldpctest
+ # ${PHY_NR_CODINGIF}
+ # ${OPENAIR1_DIR}/PHY/CODING/TESTBENCH/ldpctest.c
+ # ${T_SOURCE}
+ # ${SHLIB_LOADER_SOURCES}
+ # )
add_dependencies( ldpctest ldpc_orig ldpc_optim ldpc_optim8seg ldpc )
target_link_libraries(ldpctest
- -Wl,--start-group UTIL SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_NR PHY_COMMON PHY_NR_COMMON CONFIG_LIB -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} dl
)
add_executable(nr_dlschsim
${OPENAIR1_DIR}/SIMULATION/NR_PHY/dlschsim.c
${OPENAIR_DIR}/common/utils/system.c
+ ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${UTIL_SRC}
${T_SOURCE}
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_dlschsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
add_executable(nr_pbchsim
${OPENAIR1_DIR}/SIMULATION/NR_PHY/pbchsim.c
${OPENAIR_DIR}/common/utils/system.c
+ ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${UTIL_SRC}
${T_SOURCE}
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_pbchsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
@@ -2850,7 +2946,7 @@ add_executable(nr_pucchsim
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_pucchsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
@@ -2864,7 +2960,7 @@ add_executable(nr_dlsim
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_dlsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
target_compile_definitions(nr_dlsim PUBLIC -DPHYSICAL_SIMULATOR)
@@ -2878,17 +2974,18 @@ add_executable(nr_prachsim
${T_SOURCE}
${SHLIB_LOADER_SOURCES})
target_link_libraries(nr_prachsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl)
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_RU PHY_NR_UE MAC_NR_COMMON SCHED_NR_LIB MAC_UE_NR SCHED_NR_UE_LIB RRC_LIB NR_RRC_LIB L2_NR CONFIG_LIB -Wl,--end-group m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl)
add_executable(nr_ulschsim
${OPENAIR1_DIR}/SIMULATION/NR_PHY/ulschsim.c
${OPENAIR_DIR}/common/utils/system.c
+ ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${UTIL_SRC}
${T_SOURCE}
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_ulschsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB MAC_NR_COMMON -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
@@ -2902,7 +2999,7 @@ add_executable(nr_ulsim
${SHLIB_LOADER_SOURCES}
)
target_link_libraries(nr_ulsim
- -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group
+ -Wl,--start-group UTIL SIMU_COMMON SIMU PHY_COMMON PHY_NR PHY_NR_COMMON PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR MAC_NR_COMMON RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group
m pthread ${ATLAS_LIBRARIES} ${T_LIB} ${ITTI_LIB} dl
)
target_compile_definitions(nr_ulsim PUBLIC -DPHYSICAL_SIMULATOR)
@@ -2921,7 +3018,7 @@ foreach(myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim pr
${NFAPI_USER_DIR}/nfapi.c
)
target_link_libraries (${myExe}
- -Wl,--start-group SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY_NR_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group
+ -Wl,--start-group SIMU_COMMON SIMU UTIL SCHED_LIB SCHED_RU_LIB SCHED_UE_LIB PHY_COMMON PHY_NR_COMMON PHY PHY_UE PHY_RU LFDS ${ITTI_LIB} LFDS7 -Wl,--end-group
pthread m rt ${CONFIG_LIB} ${ATLAS_LIBRARIES} ${XFORMS_LIBRARIES} ${T_LIB} dl
)
@@ -3001,8 +3098,8 @@ if (${T_TRACER})
NFAPI_COMMON_LIB NFAPI_LIB NFAPI_PNF_LIB NFAPI_VNF_LIB NFAPI_USER_LIB
PHY_COMMON PHY PHY_UE PHY_NR PHY_NR_COMMON PHY_NR_UE PHY_RU PHY_MEX
L2 L2_LTE L2_NR L2_UE NR_L2_UE MAC_NR_COMMON MAC_NR MAC_UE_NR
- CN_UTILS GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU SIMU_ETH OPENAIR0_LIB
- ldpc_orig ldpc_optim ldpc_optim8seg ldpc)
+ CN_UTILS GTPV1U NR_GTPV1U SCTP_CLIENT MME_APP UDP LIB_NAS_UE NB_IoT LFDS LFDS7 SIMU_COMMON SIMU SIMU_ETH OPENAIR0_LIB
+ ldpc_orig ldpc_optim ldpc_optim8seg ldpc PROTO_AGENT dfts)
if (TARGET ${i})
add_dependencies(${i} generate_T)
endif()
@@ -3045,7 +3142,7 @@ function(make_driver name dir)
endforeach()
CONFIGURE_FILE(${OPENAIR_CMAKE}/tools/Kbuild.cmake ${OPENAIR_BIN_DIR}/${name}/Kbuild)
add_custom_command(OUTPUT ${name}.ko
- COMMAND $(MAKE) -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name}
+ COMMAND make -j2 -C ${module_build_path} M=${OPENAIR_BIN_DIR}/${name}
WORKING_DIRECTORY ${OPENAIR_BIN_DIR}/${name}
COMMENT "building ${module}.ko"
VERBATIM
diff --git a/cmake_targets/autotests/README.txt b/cmake_targets/autotests/README.txt
index 10c14fd59a22370f816b07cd0552090597f01478..19a333c6265251537ae25d33a2c228b605697593 100644
--- a/cmake_targets/autotests/README.txt
+++ b/cmake_targets/autotests/README.txt
@@ -142,10 +142,14 @@ Obj.# Case# Test# Description
(Test 11: 10 MHz, R7.FDD (MCS 25), EVA5, 17.7dB (70%))
(TM2 Test 1 10 MHz, R.11 FDD (MCS 14), EVA5, 6.8 dB (70%)),
(TM2 Test 1b 20 MHz, R.11-2 FDD (MCS 13), EVA5, 5.9 dB (70%)),
-01 51 11 nr_ulsim Test cases. (Test1: MCS 9),
- (Test2: MCS 16),
- (Test3: MCS 28)
-
+01 51 11 nr_ulsim Test cases. (Test1: MCS 9 106 PRBs),
+ (Test2: MCS 16 50 PRBs),
+ (Test3: MCS 28 50 PRBs),
+ (Test4: MCS 9 217 PRBs),
+ (Test5: MCS 9 273 PRBs)
+01 51 12 nr_prachsim Test cases.(Test1: 106 PRBs),
+ (Test2: 217 PRBs),
+ (Test3: 273 PRBs)
diff --git a/cmake_targets/autotests/test_case_list.xml b/cmake_targets/autotests/test_case_list.xml
index 0e6435aaf3d2cb3dd05284d72bf8139d1bcfd2c0..786002e9823b6a0a866c11947b061489d5d85c89 100644
--- a/cmake_targets/autotests/test_case_list.xml
+++ b/cmake_targets/autotests/test_case_list.xml
@@ -1036,7 +1036,9 @@
<testCase id="015103">
<class>execution</class>
<desc>polartest Test cases. (Test1: PBCH polar test),
- (Test2: DCI polar test)</desc>
+ (Test2: DCI polar test),
+ (Test3: UCI polar test,6-bit CRC),
+ (Test4: UCI polar test,11-bit CRC)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
@@ -1044,8 +1046,10 @@
<pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/polartest.Rel15</main_exec>
<main_exec_args>-q -s-10 -f0
- -q -s-10 -f0 -m1</main_exec_args>
- <tags>polartest.test1 polartest.test2</tags>
+ -q -s-10 -f0 -m1
+ -q -s-2 -f2 -m2 -k12
+ -q -s-2 -f2 -m2 -k20</main_exec_args>
+ <tags>polartest.test1 polartest.test2 polartest.test3 polartest.test4</tags>
<search_expr_true>BLER= 0.000000</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
@@ -1067,9 +1071,9 @@
<main_exec> $OPENAIR_DIR/targets/bin/nr_pbchsim.Rel15</main_exec>
<main_exec_args>-s0 -S1 -n1000 -R106
-s0 -S1 -n10 -I -R106
- -s0 -S1 -n1000 -R217
+ -s0 -S1 -n1000 -R217
-s0 -S1 -n10 -I -R217
- -s0 -S1 -n1000 -R273
+ -s0 -S1 -n1000 -R273
-s0 -S1 -n10 -I -R273</main_exec_args>
<tags>nr_pbchsim.test1 nr_pbchsim.test2 nr_pbchsim.test3 nr_pbchsim.test4 nr_pbchsim.test5 nr_pbchsim.test6</tags>
<search_expr_true>PBCH test OK</search_expr_true>
@@ -1087,8 +1091,11 @@
(Test6: 217 PRB 100 PDSCH-PRBs),
(Test7: 217 PRB 80 PDSCH-Offset),
(Test8: 217 PRB 100 PDSCH-PRBs 110 PDSCH-Offset),
- (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27)
- (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16)</desc>
+ (Test9: 106 PRBs 50 PDSCH-PRBs MCS Index 27),
+ (Test10: 106 PRBs 50 PDSCH-PRBs MCS Index 16),
+ (Test11: HARQ test 25% TP (4 rounds),
+ (Test12: HARQ test 33% TP (3 rounds),
+ (Test13: HARQ test 50% TP (2 rounds)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
@@ -1104,8 +1111,11 @@
-n100 -R217 -a80 -s5
-n100 -R217 -a110 -s5 -b100
-n100 -e27 -s30
- -n100 -e16 -s10</main_exec_args>
- <tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10</tags>
+ -n100 -e16 -s10
+ -n100 -s1 -t25
+ -n100 -s1 -t33
+ -n100 -s1 -t50</main_exec_args>
+ <tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13</tags>
<search_expr_true>PDSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
@@ -1176,21 +1186,47 @@
<testCase id="015109">
<class>execution</class>
- <desc>nr_pucchsim Test cases. (Test1: Format 0 ACK miss 106 PRB),
- (Test2: Format 1 ACK miss 106 PRB),
- (Test3: Format 1 ACK miss 273 PRB),
- (Test4: Format 1 NACKtoACK 106 PRB)</desc>
+ <desc>nr_pucchsim Test cases. (Test1: Format 0 1-bit ACK miss 106 PRB),
+ (Test2: Format 0 2-bit ACK miss 106 PRB),
+ (Test3: Format 0 2-bit ACK miss, 1-bit SR 106 PRB),
+ (Test4: Format 2 3-bit 2/106 PRB),
+ (Test5: Format 2 4-bit 2/106 PRB),
+ (Test6: Format 2 5-bit 2/106 PRB),
+ (Test7: Format 2 6-bit 2/106 PRB),
+ (Test8: Format 2 7-bit 2/106 PRB),
+ (Test9: Format 2 8-bit 2/106 PRB),
+ (Test10: Format 2 9-bit 2/106 PRB),
+ (Test11: Format 2 10-bit 2/106 PRB),
+ (Test12: Format 2 11-bit 2/106 PRB),
+ (Test13: Format 2 12-bit 8/106 PRB),
+ (Test14: Format 2 19-bit 8/106 PRB),
+ (Test15: Format 2 32-bit 8/106 PRB),
+ (Test16: Format 2 32-bit 16/106 PRB),
+ (Test17: Format 2 64-bit 16/106 PRB)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_pucchsim.Rel15</main_exec>
- <main_exec_args>-R 106 -i 1 -P 0 -b 1 -s3 -n100
- -R 106 -i 14 -P 1 -b 1 -s-6 -n100
- -R 273 -i 14 -P 1 -b 1 -s-6 -n100
- -R 106 -i 14 -P 1 -b 1 -s-6 -T 0.001 -n1000</main_exec_args>
- <tags>nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4</tags>
+ <main_exec_args>-R 106 -i 1 -P 0 -b 1 -s-2 -n1000
+ -R 106 -i 1 -P 0 -b 2 -s-2 -n1000
+ -R 106 -i 1 -P 0 -b 2 -s-2 -c -n1000
+ -R 106 -i 1 -P 2 -b 3 -s0 -n1000
+ -R 106 -i 1 -P 2 -b 4 -s0 -n1000
+ -R 106 -i 1 -P 2 -b 5 -s1 -n1000
+ -R 106 -i 1 -P 2 -b 6 -s2 -n1000
+ -R 106 -i 1 -P 2 -b 7 -s3 -n1000
+ -R 106 -i 1 -P 2 -b 8 -s4 -n1000
+ -R 106 -i 1 -P 2 -b 9 -s5 -n1000
+ -R 106 -i 1 -P 2 -b 10 -s6 -n1000
+ -R 106 -i 1 -P 2 -b 11 -s6 -n1000
+ -R 106 -i 1 -P 2 -q8 -b 12 -s-3 -n1000
+ -R 106 -i 1 -P 2 -q8 -b 19 -s-3 -n1000
+ -R 106 -i 1 -P 2 -q8 -b 32 -s-3 -n1000
+ -R 106 -i 1 -P 2 -q16 -b 32 -s-3 -n1000
+ -R 106 -i 1 -P 2 -q16 -b 64 -s-3 -n1000</main_exec_args>
+ <tags>nr_pucchsim.test1 nr_pucchsim.test2 nr_pucchsim.test3 nr_pucchsim.test4 nr_pucchsim.test5 nr_pucchsim.test6 nr_pucchsim.test7 nr_pucchsim.test8 nr_pucchsim.test9 nr_pucchsim.test10 nr_pucchsim.test11 nr_pucchsim.test12 nr_pucchsim.test13 nr_pucchsim.test14 nr_pucchsim.test15 nr_pucchsim.test16 nr_pucchsim.test17</tags>
<search_expr_true>PUCCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
@@ -1258,6 +1294,28 @@
<nruns>3</nruns>
</testCase>
+ <testCase id="015112">
+ <class>execution</class>
+ <desc>nr_prachsim Test cases. (Test1: 106 PRBs - Prach format A2),
+ (Test2: 217 PRBs - Prach format A2),
+ (Test3: 273 PRBs - Prach format A2),
+ (Test4: 106 PRBs - Prach format 0)</desc>
+ <pre_compile_prog></pre_compile_prog>
+ <compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
+ <compile_prog_args> --phy_simulators -c </compile_prog_args>
+ <pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
+ <pre_exec_args></pre_exec_args>
+ <main_exec> $OPENAIR_DIR/targets/bin/nr_prachsim.Rel15</main_exec>
+ <main_exec_args>-a -s -30 -n 100 -p 63 -R 106
+ -a -s -30 -n 100 -p 63 -R 217
+ -a -s -30 -n 100 -p 63 -R 273
+ -a -s -30 -n 100 -p 63 -R 106 -c 4</main_exec_args>
+ <tags>nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 nr_prachsim.test4</tags>
+ <search_expr_true>PRACH test OK</search_expr_true>
+ <search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
+ <nruns>3</nruns>
+ </testCase>
+
<testCase id="015500" >
<class>lte-softmodem</class>
<desc></desc>
diff --git a/cmake_targets/build_oai b/cmake_targets/build_oai
index 8ab9fff880958e1a0b6e1445e19e02cf78494793..36af9eaee4cd3538d1a8914a55b0ebb34b3bfa27 100755
--- a/cmake_targets/build_oai
+++ b/cmake_targets/build_oai
@@ -67,7 +67,7 @@ UE_TIMING_TRACE="False"
USRP_REC_PLAY="False"
BUILD_ECLIPSE=0
NR="False"
-OPTIONAL_LIBRARIES="telnetsrv enbscope uescope msc"
+OPTIONAL_LIBRARIES="telnetsrv enbscope uescope nrscope msc"
trap handle_ctrl_c INT
function print_help() {
@@ -96,7 +96,9 @@ Options
enable cmake debugging messages
--eNB
Makes the LTE softmodem
---gNB
+--eNBocp
+ Makes the OCP LTE softmodem
+-gNB
Makes the NR softmodem
--nrUE
Makes the NR UE softmodem
@@ -237,7 +239,11 @@ function main() {
eNB=1
echo_info "Will compile eNB"
shift;;
- --gNB)
+ --eNBocp)
+ eNBocp=1
+ echo_info "Will compile OCP eNB"
+ shift;;
+ --gNB)
gNB=1
NR="True"
echo_info "Will compile gNB"
@@ -406,8 +412,12 @@ function main() {
shift 1;;
-k | --skip-shared-libraries)
SKIP_SHARED_LIB_FLAG="True"
- echo_info "Skipping build of shared libraries, rfsimulator, basicsimulator and transport protocol libraries"
+ echo_info "Skipping build of shared libraries, rfsimulator and transport protocol libraries"
shift;;
+ --ninja)
+ CMAKE_CMD="$CMAKE_CMD -GNinja"
+ MAKE_CMD=ninja
+ shift;;
-h | --help)
print_help
exit 1;;
@@ -439,7 +449,7 @@ function main() {
########################################################
# to be discussed
- if [ "$eNB" = "1" -o "$gNB" = "1" ] ; then
+ if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$gNB" = "1" ] ; then
if [ "$HW" = "None" -a "$TP" = "None" ] ; then
echo_info "No local radio head and no transport protocol selected"
fi
@@ -570,12 +580,13 @@ function main() {
config_libconfig_shlib=params_libconfig
# first generate the CMakefile in the right directory
- if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HW" = "EXMIMO" ] ; then
+ if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HW" = "EXMIMO" ] ; then
# softmodem compilation
cmake_file=$DIR/$build_dir/CMakeLists.txt
echo "cmake_minimum_required(VERSION 2.8)" > $cmake_file
+ echo "project (OpenAirInterface)" >> $cmake_file
echo "set ( CMAKE_BUILD_TYPE $CMAKE_BUILD_TYPE )" >> $cmake_file
echo "set ( CFLAGS_PROCESSOR_USER \"$CFLAGS_PROCESSOR_USER\" )" >> $cmake_file
echo "set ( UE_EXPANSION $UE_EXPANSION )" >> $cmake_file
@@ -602,6 +613,9 @@ function main() {
if [ "$eNB" = "1" ] ; then
execlist="$execlist lte-softmodem"
fi
+ if [ "$eNBocp" = "1" ] ; then
+ execlist="$execlist ocp-enb"
+ fi
if [ "$gNB" = "1" ] ; then
execlist="$execlist nr-softmodem"
fi
@@ -697,7 +711,8 @@ function main() {
if [ "$SIMUS_PHY" = "1" ] ; then
echo_info "Compiling physical unitary tests simulators"
# TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim
- simlist="ldpctest dlsim ulsim polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim"
+ simlist="dlsim ulsim ldpctest polartest smallblocktest nr_pbchsim nr_dlschsim nr_ulschsim nr_dlsim nr_ulsim nr_pucchsim nr_prachsim"
+ # simlist="ldpctest"
for f in $simlist ; do
compilations \
phy_simulators $f \
@@ -816,7 +831,7 @@ function main() {
####################################################
# Build RF device and transport protocol libraries #
####################################################
- if [ "$eNB" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HWLAT" = "1" ] ; then
+ if [ "$eNB" = "1" -o "$eNBocp" = "1" -o "$UE" = "1" -o "$gNB" = "1" -o "$nrUE" = "1" -o "$HWLAT" = "1" ] ; then
# build RF device libraries
if [ "$HW" != "None" ] ; then
@@ -892,7 +907,7 @@ function main() {
$build_dir rfsimulator \
librfsimulator.so $dbin/librfsimulator.so.$REL
- echo_info "Compiling basicsimulator"
+ echo_info "Compiling tcp_bridge_oai"
compilations \
$build_dir tcp_bridge_oai \
libtcp_bridge_oai.so $dbin/libtcp_bridge_oai.so.$REL
@@ -954,6 +969,7 @@ function main() {
wait
else
echo_info "10. Bypassing the Tests ..."
+ echo_success "BUILD SHOULD BE SUCCESSFUL"
fi
}
diff --git a/cmake_targets/tools/build_helper b/cmake_targets/tools/build_helper
index 8e4ae59a7faf90c5c10e70037ff2d52913b27491..b8f0125b103e83870c3d99784fcba3b2a0064eba 100755
--- a/cmake_targets/tools/build_helper
+++ b/cmake_targets/tools/build_helper
@@ -150,7 +150,9 @@ clean_all_files() {
set_openair_env
dir=$OPENAIR_DIR/cmake_targets
rm -rf $dir/log $OPENAIR_DIR/targets/bin/*
- rm -rf $dir/ran_build $dir/lte-simulators/build
+ rm -rf $dir/ran_build $dir/ran_build_noLOG
+ rm -rf $dir/lte-simulators/build
+ rm -rf $dir/phy_simulators/build $dir/nas_sim_tools/build
rm -rf $dir/oaisim_build_oai/build $dir/oaisim_build_oai/CMakeLists.txt
rm -rf $dir/autotests/bin $dir/autotests/log $dir/autotests/*/build
}
@@ -167,36 +169,59 @@ check_warnings() {
#we look for 'warning:' in the compilation log file
#this is how gcc starts a warning
#this is not perfect, we may get false positive
- warning_count=`grep "warning:" "$1"|wc -l`
+ warning_count=`grep "warning:" "$1" | egrep -v "jobserver unavailable|disabling jobserver mode" | wc -l`
if [ $warning_count -gt 0 ]; then
echo_error "WARNING: $warning_count warnings. See $1"
fi
}
+#check_errors:
+# print error message if the compilation had errors
+#argument:
+# $1: log file
+check_errors() {
+ #we look for 'warning:' in the compilation log file
+ error_count=`grep "error:" "$1" | wc -l`
+ if [ $error_count -gt 0 ]; then
+ echo_error "ERROR: $error_count error. See $1"
+ fi
+}
+
compilations() {
cd $OPENAIR_DIR/cmake_targets/$1/build
+ echo_info "Log file for compilation is being written to: $dlog/$2.$REL.txt"
set +e
{
- rm -f $3
if [ "$BUILD_COVERITY_SCAN" == "1" ]; then
COV_SCAN_PREFIX="cov-build --dir cov-int"
else
COV_SCAN_PREFIX=""
fi
+ if [ "$MAKE_CMD" != "" ]; then
+ $MAKE_CMD $2
+ else
if [ "$VERBOSE_COMPILE" == "1" ]; then
$COV_SCAN_PREFIX make -j`nproc` $2 VERBOSE=$VERBOSE_COMPILE
else
$COV_SCAN_PREFIX make -j`nproc` $2
fi
-
+ fi
+ ret=$?
} > $dlog/$2.$REL.txt 2>&1
set -e
- echo_info "Log file for compilation has been written to: $dlog/$2.$REL.txt"
+ if [[ $ret -ne 0 ]]; then
+ check_warnings "$dlog/$2.$REL.txt"
+ check_errors "$dlog/$2.$REL.txt"
+ echo_error "$2 compilation failed"
+ exit 1
+ fi
if [ -s $3 ] ; then
cp $3 $4
echo_success "$2 compiled"
check_warnings "$dlog/$2.$REL.txt"
else
+ check_warnings "$dlog/$2.$REL.txt"
+ check_errors "$dlog/$2.$REL.txt"
echo_error "$2 compilation failed"
exit 1
fi
@@ -619,6 +644,7 @@ check_install_oai_software() {
build-essential \
cmake \
cmake-curses-gui \
+ ninja-build \
doxygen \
doxygen-gui \
texlive-latex-base \
diff --git a/common/config/libconfig/config_libconfig.c b/common/config/libconfig/config_libconfig.c
index 2d861f2dc33df5684730d1cf1af9bfe57c0c73d2..2e9fd614c504e286f5eeb728a4b03ab198ec1cf0 100644
--- a/common/config/libconfig/config_libconfig.c
+++ b/common/config/libconfig/config_libconfig.c
@@ -179,8 +179,8 @@ int config_libconfig_get(paramdef_t *cfgoptions,int numoptions, char *prefix ) {
*(cfgoptions[i].u64ptr) = (uint64_t)llu;
printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].u64ptr)) );
} else {
- *(cfgoptions[i].iptr) = llu;
- printf_params("[LIBCONFIG] %s: %llu\n", cfgpath,(long long unsigned)(*(cfgoptions[i].i64ptr)) );
+ *(cfgoptions[i].i64ptr) = llu;
+ printf_params("[LIBCONFIG] %s: %lld\n", cfgpath,(long long)(*(cfgoptions[i].i64ptr)) );
}
} else {
defval=config_setdefault_int64(&(cfgoptions[i]),prefix);
diff --git a/common/utils/LOG/vcd_signal_dumper.c b/common/utils/LOG/vcd_signal_dumper.c
index 0043eb32380892cda7846c59f1b4f19a7eeff79f..90857d7cd941dcbf8b05020b8328ee99a9deed09 100644
--- a/common/utils/LOG/vcd_signal_dumper.c
+++ b/common/utils/LOG/vcd_signal_dumper.c
@@ -248,7 +248,8 @@ const char* eurecomVariablesNames[] = {
"slot_number_TX1_gNB",
"slot_number_RX0_gNB",
"slot_number_RX1_gNB",
- "ru_tx_ofdm_mask"
+ "ru_tx_ofdm_mask",
+ "usrp_send_return"
};
const char* eurecomFunctionsNames[] = {
@@ -282,6 +283,8 @@ const char* eurecomFunctionsNames[] = {
"lock_mutex_ru",
"lock_mutex_ru1",
"lock_mutex_ru2",
+ /* uhd signals */
+ "trx_write_thread",
/* simulation signals */
"do_DL_sig",
"do_UL_sig",
@@ -515,7 +518,29 @@ const char* eurecomFunctionsNames[] = {
"wakeup_txfh",
"gNB_thread_rxtx0",
"gNB_thread_rxtx1",
- "ru_thread_tx_wait"
+ "ru_thread_tx_wait",
+ "gNB_ulsch_decoding",
+ "gNB_pdsch_codeword_scrambling",
+ "gNB_dlsch_encoding",
+ "gNB_pdsch_modulation",
+ "gNB_pdcch_tx",
+ "phy_procedures_gNB_tx",
+ "phy_procedures_gNB_common_tx",
+ "phy_procedures_gNB_uespec_rx",
+ "nr_rx_pusch",
+ "nr_ulsch_procedures_rx",
+ "macxface_gNB_dlsch_ulsch_scheduler",
+
+ /*NR ue-softmodem signal*/
+ "nr_ue_ulsch_encoding",
+ "nr_segmentation",
+ "ldpc_encoder_optim",
+ "nr_rate_matching_ldpc",
+ "nr_interleaving_ldpc",
+ "pss_synchro_nr",
+ "pss_search_time_nr",
+ "nr_initial_ue_sync",
+ "beam_switching_gpio"
};
struct vcd_module_s vcd_modules[] = {
diff --git a/common/utils/LOG/vcd_signal_dumper.h b/common/utils/LOG/vcd_signal_dumper.h
index 20588bb8286f42ca8367c5ab5be486b79c3e87ee..601465c628dc725b0502235e7b7ac14ced6dab9c 100644
--- a/common/utils/LOG/vcd_signal_dumper.h
+++ b/common/utils/LOG/vcd_signal_dumper.h
@@ -226,6 +226,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX0_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_SLOT_NUMBER_RX1_GNB,
VCD_SIGNAL_DUMPER_VARIABLES_RU_TX_OFDM_MASK,
+ VCD_SIGNAL_DUMPER_VARIABLES_USRP_SEND_RETURN,
VCD_SIGNAL_DUMPER_VARIABLES_END
@@ -262,6 +263,8 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU,
VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU1,
VCD_SIGNAL_DUMPER_FUNCTIONS_LOCK_MUTEX_RU2,
+ /* uhd signals */
+ VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD,
/* SIMULATION signals */
VCD_SIGNAL_DUMPER_FUNCTIONS_SIM_DO_DL_SIGNAL,
VCD_SIGNAL_DUMPER_FUNCTIONS_SIM_DO_UL_SIGNAL,
@@ -508,6 +511,29 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX0,
VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PROC_RXTX1,
VCD_SIGNAL_DUMPER_FUNCTIONS_RU_TX_WAIT,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,
+
+/* NR ue-softmodem signal*/
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC,
+ VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,
+
VCD_SIGNAL_DUMPER_FUNCTIONS_END
} vcd_signal_dump_functions;
diff --git a/common/utils/T/T_defs.h b/common/utils/T/T_defs.h
index 4cb4bf2bbaf8814ffaa17468037258b343da2e33..7b5304b1cb144fdeb3ffdac617c27a45d398aba1 100644
--- a/common/utils/T/T_defs.h
+++ b/common/utils/T/T_defs.h
@@ -73,10 +73,10 @@ typedef struct {
} T_cache_t;
/* number of VCD functions (to be kept up to date! see in T_messages.txt) */
-#define VCD_NUM_FUNCTIONS (248)
+#define VCD_NUM_FUNCTIONS (269)
/* number of VCD variables (to be kept up to date! see in T_messages.txt) */
-#define VCD_NUM_VARIABLES (186)
+#define VCD_NUM_VARIABLES (187)
/* first VCD function (to be kept up to date! see in T_messages.txt) */
#define VCD_FIRST_FUNCTION ((uintptr_t)T_VCD_FUNCTION_RT_SLEEP)
diff --git a/common/utils/T/T_messages.txt b/common/utils/T/T_messages.txt
index f8b746669c835f26982eb3ca2caef96a13b6bd1d..d036b405606a78cb1b73d9564ec2b8ddc9383b29 100644
--- a/common/utils/T/T_messages.txt
+++ b/common/utils/T/T_messages.txt
@@ -2138,6 +2138,11 @@ ID = VCD_VARIABLE_RU_TX_OFDM_MASK
GROUP = ALL:VCD:ENB:VCD_VARIABLE
FORMAT = ulong,value
VCD_NAME = ru_tx_ofdm_mask
+ID = VCD_VARIABLE_USRP_SEND_RETURN
+ DESC = VCD variable USRP_SEND_RETURN
+ GROUP = ALL:VCD:ENB:VCD_VARIABLE
+ FORMAT = ulong,value
+ VCD_NAME = usrp_send_return
#functions
@@ -2286,6 +2291,11 @@ ID = VCD_FUNCTION_LOCK_MUTEX_RU2
GROUP = ALL:VCD:UE:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = lock_mutex_ru2
+ID = VCD_FUNCTION_TRX_WRITE_THREAD
+ DESC = VCD function TRX_WRITE_THREAD
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = trx_write_thread
ID = VCD_FUNCTION_SIM_DO_DL_SIGNAL
DESC = VCD function SIM_DO_DL_SIGNAL
GROUP = ALL:VCD:ENB:VCD_FUNCTION
@@ -3383,3 +3393,106 @@ ID = VCD_FUNCTION_RU_TX_WAIT
GROUP = ALL:VCD:ENB:VCD_FUNCTION
FORMAT = int,value
VCD_NAME = ru_thread_tx_wait
+ID = VCD_FUNCTION_PHY_gNB_ULSCH_DECODING
+ DESC = VCD function PHY_gNB_ULSCH_DECODING
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = gNB_ulsch_decoding
+ID = VCD_FUNCTION_gNB_PDSCH_CODEWORD_SCRAMBLING
+ DESC = VCD function gNB_PDSCH_CODEWORD_SCRAMBLING
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = gNB_pdsch_codeword_scrambling
+ID = VCD_FUNCTION_gNB_DLSCH_ENCODING
+ DESC = VCD function gNB_DLSCH_ENCODING
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = gNB_dlsch_encoding
+ID = VCD_FUNCTION_gNB_PDSCH_MODULATION
+ DESC = VCD function gNB_PDSCH_MODULATION
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = gNB_pdsch_modulation
+ID = VCD_FUNCTION_PHY_gNB_PDCCH_TX
+ DESC = VCD function PHY_gNB_PDCCH_TX
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = gNB_pdcch_tx
+ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_TX
+ DESC = VCD function PHY_PROCEDURES_gNB_TX
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = phy_procedures_gNB_tx
+ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_COMMON_TX
+ DESC = VCD function PHY_PROCEDURES_gNB_COMMON_TX
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = phy_procedures_gNB_common_tx
+ID = VCD_FUNCTION_PHY_PROCEDURES_gNB_UESPEC_RX
+ DESC = VCD function PHY_PROCEDURES_gNB_UESPEC_RX
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = phy_procedures_gNB_uespec_rx
+ID = VCD_FUNCTION_NR_RX_PUSCH
+ DESC = VCD function NR_RX_PUSCH
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_rx_pusch
+ID = VCD_FUNCTION_NR_ULSCH_PROCEDURES_RX
+ DESC = VCD function NR_ULSCH_PROCEDURES_RX
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_ulsch_procedures_rx
+ID = VCD_FUNCTION_gNB_DLSCH_ULSCH_SCHEDULER
+ DESC = VCD function gNB_DLSCH_ULSCH_SCHEDULER
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = macxface_gNB_dlsch_ulsch_scheduler
+
+ #function for nrUE
+ID = VCD_FUNCTION_NR_UE_ULSCH_ENCODING
+ DESC = VCD function NR_UE_ULSCH_ENCODING
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_ue_ulsch_encoding
+ID = VCD_FUNCTION_NR_SEGMENTATION
+ DESC = VCD function NR_SEGMENTATION
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_segmentation
+ID = VCD_FUNCTION_LDPC_ENCODER_OPTIM
+ DESC = VCD function LDPC_ENCODER_OPTIM
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = ldpc_encoder_optim
+ID = VCD_FUNCTION_NR_RATE_MATCHING_LDPC
+ DESC = VCD function NR_RATE_MATCHING_LDPC
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_rate_matching_ldpc
+ID = VCD_FUNCTION_NR_INTERLEAVING_LDPC
+ DESC = VCD function NR_INTERLEAVING_LDPC
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_interleaving_ldpc
+ID = VCD_FUNCTION_PSS_SYNCHRO_NR
+ DESC = VCD function PSS_SYNCHRO_NR
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = pss_synchro_nr
+ID = VCD_FUNCTION_PSS_SEARCH_TIME_NR
+ DESC = VCD function PSS_SEARCH_TIME_NR
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = pss_search_time_nr
+ID = VCD_FUNCTION_NR_INITIAL_UE_SYNC
+ DESC = VCD function NR_INITIAL_UE_SYNC
+ GROUP = ALL:VCD:UE:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = nr_initial_ue_sync
+ID = VCD_FUNCTION_BEAM_SWITCHING_GPIO
+ DESC = VCD function BEAM_SWITCHING_GPIO
+ GROUP = ALL:VCD:ENB:VCD_FUNCTION
+ FORMAT = int,value
+ VCD_NAME = beam_switching_gpio
+
diff --git a/common/utils/T/tracer/config.h b/common/utils/T/tracer/config.h
index 07290c71a35c5605596ff3770a34db40ce5dbc0a..765b1261334ecb75dcec10d72d76f89ee93eb799 100644
--- a/common/utils/T/tracer/config.h
+++ b/common/utils/T/tracer/config.h
@@ -1,5 +1,5 @@
-#ifndef _CONFIG_H_
-#define _CONFIG_H_
+#ifndef __COMMON_UTILS_T_TRACER_CONFIG__H__
+#define __COMMON_UTILS_T_TRACER_CONFIG__H__
void clear_remote_config(void);
void append_received_config_chunk(char *buf, int length);
@@ -7,4 +7,4 @@ void load_config_file(char *filename);
void verify_config(void);
void get_local_config(char **txt, int *len);
-#endif /* _CONFIG_H_ */
+#endif /* __COMMON_UTILS_T_TRACER_CONFIG__H__ */
diff --git a/common/utils/T/tracer/packet-mac-lte.h b/common/utils/T/tracer/packet-mac-lte.h
index 1bc6df632b7e07810ca1f2c3c87e98e2d97c7d91..54e6d1a09bbf13a90800fa4778cd3e54661a99f4 100644
--- a/common/utils/T/tracer/packet-mac-lte.h
+++ b/common/utils/T/tracer/packet-mac-lte.h
@@ -33,6 +33,9 @@
* SUCH DAMAGE
*/
+#ifndef __COMMON_UTILS_T_TRACER_PACKET_MAC_LTE__H__
+#define __COMMON_UTILS_T_TRACER_PACKET_MAC_LTE__H__
+
//#include "ws_symbol_export.h"
/* radioType */
@@ -139,3 +142,4 @@
continues until the end of the frame) */
#define MAC_LTE_PAYLOAD_TAG 0x01
+#endif
diff --git a/common/utils/assertions.h b/common/utils/assertions.h
index 97f186627488de5f14c5660a4c40884f157876ec..48d8df401cec155027bec18dacc056ef3f70d7fe 100644
--- a/common/utils/assertions.h
+++ b/common/utils/assertions.h
@@ -19,6 +19,9 @@
* contact@openairinterface.org
*/
+#ifndef __COMMON_UTILS_ASSERTIONS__H__
+#define __COMMON_UTILS_ASSERTIONS__H__
+
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
@@ -30,9 +33,6 @@
# include "backtrace.h"
#endif
-#ifndef ASSERTIONS_H_
-#define ASSERTIONS_H_
-
void output_log_mem(void);
#define _Assert_Exit_ \
fprintf(stderr, "\nExiting execution\n"); \
@@ -83,4 +83,4 @@ do { \
} \
} while(0)
-#endif /* ASSERTIONS_H_ */
+#endif /* __COMMON_UTILS_ASSERTIONS__H__ */
diff --git a/common/utils/itti_analyzer/common/queue.h b/common/utils/itti_analyzer/common/queue.h
deleted file mode 100644
index 294d48511086b20eb321e07641eb0599db4b75da..0000000000000000000000000000000000000000
--- a/common/utils/itti_analyzer/common/queue.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Copyright (c) 1991, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)queue.h 8.5 (Berkeley) 8/20/94
- */
-
-#ifndef _SYS_QUEUE_H_
-#define _SYS_QUEUE_H_
-
-/*
- * This file defines five types of data structures: singly-linked lists,
- * lists, simple queues, tail queues, and circular queues.
- *
- * A singly-linked list is headed by a single forward pointer. The
- * elements are singly linked for minimum space and pointer manipulation
- * overhead at the expense of O(n) removal for arbitrary elements. New
- * elements can be added to the list after an existing element or at the
- * head of the list. Elements being removed from the head of the list
- * should use the explicit macro for this purpose for optimum
- * efficiency. A singly-linked list may only be traversed in the forward
- * direction. Singly-linked lists are ideal for applications with large
- * datasets and few or no removals or for implementing a LIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may only be traversed in the forward direction.
- *
- * A simple queue is headed by a pair of pointers, one the head of the
- * list and the other to the tail of the list. The elements are singly
- * linked to save space, so elements can only be removed from the
- * head of the list. New elements can be added to the list after
- * an existing element, at the head of the list, or at the end of the
- * list. A simple queue may only be traversed in the forward direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * A circle queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or after
- * an existing element, at the head of the list, or at the end of the list.
- * A circle queue may be traversed in either direction, but has a more
- * complex end of list detection.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- * SLIST LIST STAILQ TAILQ CIRCLEQ
- * _HEAD + + + + +
- * _HEAD_INITIALIZER + + + + +
- * _ENTRY + + + + +
- * _INIT + + + + +
- * _EMPTY + + + + +
- * _FIRST + + + + +
- * _NEXT + + + + +
- * _PREV - - - + +
- * _LAST - - + + +
- * _FOREACH + + + + +
- * _FOREACH_REVERSE - - - + +
- * _INSERT_HEAD + + + + +
- * _INSERT_BEFORE - + - + +
- * _INSERT_AFTER + + + + +
- * _INSERT_TAIL - - + + +
- * _REMOVE_HEAD + - + - -
- * _REMOVE + + + + +
- */
-
-/*
- * List definitions.
- */
-#define LIST_HEAD(name, type) \
-struct name { \
- struct type *lh_first; /* first element */ \
-}
-
-#define LIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define LIST_ENTRY(type) \
-struct { \
- struct type *le_next; /* next element */ \
- struct type **le_prev; /* address of previous next element */ \
-}
-
-/*
- * List functions.
- */
-#define LIST_INIT(head) do { \
- (head)->lh_first = NULL; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_AFTER(listelm, elm, field) do { \
- if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \
- (listelm)->field.le_next->field.le_prev = \
- &(elm)->field.le_next; \
- (listelm)->field.le_next = (elm); \
- (elm)->field.le_prev = &(listelm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.le_prev = (listelm)->field.le_prev; \
- (elm)->field.le_next = (listelm); \
- *(listelm)->field.le_prev = (elm); \
- (listelm)->field.le_prev = &(elm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.le_next = (head)->lh_first) != NULL) \
- (head)->lh_first->field.le_prev = &(elm)->field.le_next;\
- (head)->lh_first = (elm); \
- (elm)->field.le_prev = &(head)->lh_first; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_REMOVE(elm, field) do { \
- if ((elm)->field.le_next != NULL) \
- (elm)->field.le_next->field.le_prev = \
- (elm)->field.le_prev; \
- *(elm)->field.le_prev = (elm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_FOREACH(var, head, field) \
- for ((var) = ((head)->lh_first); \
- (var); \
- (var) = ((var)->field.le_next))
-
-/*
- * List access methods.
- */
-#define LIST_EMPTY(head) ((head)->lh_first == NULL)
-#define LIST_FIRST(head) ((head)->lh_first)
-#define LIST_NEXT(elm, field) ((elm)->field.le_next)
-
-
-/*
- * Singly-linked List definitions.
- */
-#define SLIST_HEAD(name, type) \
-struct name { \
- struct type *slh_first; /* first element */ \
-}
-
-#define SLIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define SLIST_ENTRY(type) \
-struct { \
- struct type *sle_next; /* next element */ \
-}
-
-/*
- * Singly-linked List functions.
- */
-#define SLIST_INIT(head) do { \
- (head)->slh_first = NULL; \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
- (elm)->field.sle_next = (slistelm)->field.sle_next; \
- (slistelm)->field.sle_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_INSERT_HEAD(head, elm, field) do { \
- (elm)->field.sle_next = (head)->slh_first; \
- (head)->slh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_REMOVE_HEAD(head, field) do { \
- (head)->slh_first = (head)->slh_first->field.sle_next; \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_REMOVE(head, elm, type, field) do { \
- if ((head)->slh_first == (elm)) { \
- SLIST_REMOVE_HEAD((head), field); \
- } \
- else { \
- struct type *curelm = (head)->slh_first; \
- while(curelm->field.sle_next != (elm)) \
- curelm = curelm->field.sle_next; \
- curelm->field.sle_next = \
- curelm->field.sle_next->field.sle_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_FOREACH(var, head, field) \
- for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next)
-
-/*
- * Singly-linked List access methods.
- */
-#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
-#define SLIST_FIRST(head) ((head)->slh_first)
-#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define STAILQ_HEAD(name, type) \
-struct name { \
- struct type *stqh_first; /* first element */ \
- struct type **stqh_last; /* addr of last next element */ \
-}
-
-#define STAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).stqh_first }
-
-#define STAILQ_ENTRY(type) \
-struct { \
- struct type *stqe_next; /* next element */ \
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define STAILQ_INIT(head) do { \
- (head)->stqh_first = NULL; \
- (head)->stqh_last = &(head)->stqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \
- (head)->stqh_last = &(elm)->field.stqe_next; \
- (head)->stqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.stqe_next = NULL; \
- *(head)->stqh_last = (elm); \
- (head)->stqh_last = &(elm)->field.stqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\
- (head)->stqh_last = &(elm)->field.stqe_next; \
- (listelm)->field.stqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_REMOVE_HEAD(head, field) do { \
- if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \
- (head)->stqh_last = &(head)->stqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_REMOVE(head, elm, type, field) do { \
- if ((head)->stqh_first == (elm)) { \
- STAILQ_REMOVE_HEAD((head), field); \
- } else { \
- struct type *curelm = (head)->stqh_first; \
- while (curelm->field.stqe_next != (elm)) \
- curelm = curelm->field.stqe_next; \
- if ((curelm->field.stqe_next = \
- curelm->field.stqe_next->field.stqe_next) == NULL) \
- (head)->stqh_last = &(curelm)->field.stqe_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_FOREACH(var, head, field) \
- for ((var) = ((head)->stqh_first); \
- (var); \
- (var) = ((var)->field.stqe_next))
-
-#define STAILQ_CONCAT(head1, head2) do { \
- if (!STAILQ_EMPTY((head2))) { \
- *(head1)->stqh_last = (head2)->stqh_first; \
- (head1)->stqh_last = (head2)->stqh_last; \
- STAILQ_INIT((head2)); \
- } \
-} while (/*CONSTCOND*/0)
-
-/*
- * Singly-linked Tail queue access methods.
- */
-#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
-#define STAILQ_FIRST(head) ((head)->stqh_first)
-#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
-
-
-/*
- * Simple queue definitions.
- */
-#define SIMPLEQ_HEAD(name, type) \
-struct name { \
- struct type *sqh_first; /* first element */ \
- struct type **sqh_last; /* addr of last next element */ \
-}
-
-#define SIMPLEQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).sqh_first }
-
-#define SIMPLEQ_ENTRY(type) \
-struct { \
- struct type *sqe_next; /* next element */ \
-}
-
-/*
- * Simple queue functions.
- */
-#define SIMPLEQ_INIT(head) do { \
- (head)->sqh_first = NULL; \
- (head)->sqh_last = &(head)->sqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
- (head)->sqh_last = &(elm)->field.sqe_next; \
- (head)->sqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.sqe_next = NULL; \
- *(head)->sqh_last = (elm); \
- (head)->sqh_last = &(elm)->field.sqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
- (head)->sqh_last = &(elm)->field.sqe_next; \
- (listelm)->field.sqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_REMOVE_HEAD(head, field) do { \
- if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
- (head)->sqh_last = &(head)->sqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_REMOVE(head, elm, type, field) do { \
- if ((head)->sqh_first == (elm)) { \
- SIMPLEQ_REMOVE_HEAD((head), field); \
- } else { \
- struct type *curelm = (head)->sqh_first; \
- while (curelm->field.sqe_next != (elm)) \
- curelm = curelm->field.sqe_next; \
- if ((curelm->field.sqe_next = \
- curelm->field.sqe_next->field.sqe_next) == NULL) \
- (head)->sqh_last = &(curelm)->field.sqe_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_FOREACH(var, head, field) \
- for ((var) = ((head)->sqh_first); \
- (var); \
- (var) = ((var)->field.sqe_next))
-
-/*
- * Simple queue access methods.
- */
-#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == NULL)
-#define SIMPLEQ_FIRST(head) ((head)->sqh_first)
-#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
-
-
-/*
- * Tail queue definitions.
- */
-#define _TAILQ_HEAD(name, type, qual) \
-struct name { \
- qual type *tqh_first; /* first element */ \
- qual type *qual *tqh_last; /* addr of last next element */ \
-}
-#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,)
-
-#define TAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).tqh_first }
-
-#define _TAILQ_ENTRY(type, qual) \
-struct { \
- qual type *tqe_next; /* next element */ \
- qual type *qual *tqe_prev; /* address of previous next element */\
-}
-#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,)
-
-/*
- * Tail queue functions.
- */
-#define TAILQ_INIT(head) do { \
- (head)->tqh_first = NULL; \
- (head)->tqh_last = &(head)->tqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
- (head)->tqh_first->field.tqe_prev = \
- &(elm)->field.tqe_next; \
- else \
- (head)->tqh_last = &(elm)->field.tqe_next; \
- (head)->tqh_first = (elm); \
- (elm)->field.tqe_prev = &(head)->tqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.tqe_next = NULL; \
- (elm)->field.tqe_prev = (head)->tqh_last; \
- *(head)->tqh_last = (elm); \
- (head)->tqh_last = &(elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
- (elm)->field.tqe_next->field.tqe_prev = \
- &(elm)->field.tqe_next; \
- else \
- (head)->tqh_last = &(elm)->field.tqe_next; \
- (listelm)->field.tqe_next = (elm); \
- (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
- (elm)->field.tqe_next = (listelm); \
- *(listelm)->field.tqe_prev = (elm); \
- (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_REMOVE(head, elm, field) do { \
- if (((elm)->field.tqe_next) != NULL) \
- (elm)->field.tqe_next->field.tqe_prev = \
- (elm)->field.tqe_prev; \
- else \
- (head)->tqh_last = (elm)->field.tqe_prev; \
- *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_FOREACH(var, head, field) \
- for ((var) = ((head)->tqh_first); \
- (var); \
- (var) = ((var)->field.tqe_next))
-
-#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
- for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \
- (var); \
- (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)))
-
-#define TAILQ_CONCAT(head1, head2, field) do { \
- if (!TAILQ_EMPTY(head2)) { \
- *(head1)->tqh_last = (head2)->tqh_first; \
- (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
- (head1)->tqh_last = (head2)->tqh_last; \
- TAILQ_INIT((head2)); \
- } \
-} while (/*CONSTCOND*/0)
-
-/*
- * Tail queue access methods.
- */
-#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
-#define TAILQ_FIRST(head) ((head)->tqh_first)
-#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define TAILQ_LAST(head, headname) \
- (*(((struct headname *)((head)->tqh_last))->tqh_last))
-#define TAILQ_PREV(elm, headname, field) \
- (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-
-/*
- * Circular queue definitions.
- */
-#define CIRCLEQ_HEAD(name, type) \
-struct name { \
- struct type *cqh_first; /* first element */ \
- struct type *cqh_last; /* last element */ \
-}
-
-#define CIRCLEQ_HEAD_INITIALIZER(head) \
- { (void *)&head, (void *)&head }
-
-#define CIRCLEQ_ENTRY(type) \
-struct { \
- struct type *cqe_next; /* next element */ \
- struct type *cqe_prev; /* previous element */ \
-}
-
-/*
- * Circular queue functions.
- */
-#define CIRCLEQ_INIT(head) do { \
- (head)->cqh_first = (void *)(head); \
- (head)->cqh_last = (void *)(head); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
- (elm)->field.cqe_next = (listelm)->field.cqe_next; \
- (elm)->field.cqe_prev = (listelm); \
- if ((listelm)->field.cqe_next == (void *)(head)) \
- (head)->cqh_last = (elm); \
- else \
- (listelm)->field.cqe_next->field.cqe_prev = (elm); \
- (listelm)->field.cqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
- (elm)->field.cqe_next = (listelm); \
- (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
- if ((listelm)->field.cqe_prev == (void *)(head)) \
- (head)->cqh_first = (elm); \
- else \
- (listelm)->field.cqe_prev->field.cqe_next = (elm); \
- (listelm)->field.cqe_prev = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
- (elm)->field.cqe_next = (head)->cqh_first; \
- (elm)->field.cqe_prev = (void *)(head); \
- if ((head)->cqh_last == (void *)(head)) \
- (head)->cqh_last = (elm); \
- else \
- (head)->cqh_first->field.cqe_prev = (elm); \
- (head)->cqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.cqe_next = (void *)(head); \
- (elm)->field.cqe_prev = (head)->cqh_last; \
- if ((head)->cqh_first == (void *)(head)) \
- (head)->cqh_first = (elm); \
- else \
- (head)->cqh_last->field.cqe_next = (elm); \
- (head)->cqh_last = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_REMOVE(head, elm, field) do { \
- if ((elm)->field.cqe_next == (void *)(head)) \
- (head)->cqh_last = (elm)->field.cqe_prev; \
- else \
- (elm)->field.cqe_next->field.cqe_prev = \
- (elm)->field.cqe_prev; \
- if ((elm)->field.cqe_prev == (void *)(head)) \
- (head)->cqh_first = (elm)->field.cqe_next; \
- else \
- (elm)->field.cqe_prev->field.cqe_next = \
- (elm)->field.cqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_FOREACH(var, head, field) \
- for ((var) = ((head)->cqh_first); \
- (var) != (const void *)(head); \
- (var) = ((var)->field.cqe_next))
-
-#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \
- for ((var) = ((head)->cqh_last); \
- (var) != (const void *)(head); \
- (var) = ((var)->field.cqe_prev))
-
-/*
- * Circular queue access methods.
- */
-#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))
-#define CIRCLEQ_FIRST(head) ((head)->cqh_first)
-#define CIRCLEQ_LAST(head) ((head)->cqh_last)
-#define CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
-#define CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
-
-#define CIRCLEQ_LOOP_NEXT(head, elm, field) \
- (((elm)->field.cqe_next == (void *)(head)) \
- ? ((head)->cqh_first) \
- : (elm->field.cqe_next))
-#define CIRCLEQ_LOOP_PREV(head, elm, field) \
- (((elm)->field.cqe_prev == (void *)(head)) \
- ? ((head)->cqh_last) \
- : (elm->field.cqe_prev))
-
-#endif /* sys/queue.h */
diff --git a/common/utils/nr/nr_common.c b/common/utils/nr/nr_common.c
index 8a236c49f99bec55b955046cb939b97a31a82d07..5f07fc00aa7ca7905552d5881b92a0ff39e1669b 100644
--- a/common/utils/nr/nr_common.c
+++ b/common/utils/nr/nr_common.c
@@ -52,6 +52,7 @@ int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB) {
else return(N_RB-1-tmp2);
}
+/* TS 38.214 ch. 6.1.2.2.2 - Resource allocation type 1 for DL and UL */
int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) {
AssertFatal(NPRB>0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d) for BWPsize %d\n",NPRB,RBstart,BWPsize);
@@ -62,14 +63,21 @@ int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) {
int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) {
return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275));
}
+
/// Target code rate tables indexed by Imcs
+/* TS 38.214 table 5.1.3.1-1 - MCS index table 1 for PDSCH */
uint16_t nr_target_code_rate_table1[29] = {120, 157, 193, 251, 308, 379, 449, 526, 602, 679, 340, 378, 434, 490, 553, \
616, 658, 438, 466, 517, 567, 616, 666, 719, 772, 822, 873, 910, 948};
- // Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point
+
+/* TS 38.214 table 5.1.3.1-2 - MCS index table 2 for PDSCH */
+// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point
uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 490, 553, 616, 658, 466, 517, 567, \
616, 666, 719, 772, 822, 873, 1365, 711, 754, 797, 841, 885, 1833, 948};
+
+/* TS 38.214 table 5.1.3.1-3 - MCS index table 3 for PDSCH */
uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \
378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772};
+
uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \
336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \
1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \
diff --git a/common/utils/nr/nr_common.h b/common/utils/nr/nr_common.h
index 979cf863436a91430b0e1e562c71aa9c84f24965..5601c0fcbf8f5755b42fc484db8bbbd8ccdf6aa9 100644
--- a/common/utils/nr/nr_common.h
+++ b/common/utils/nr/nr_common.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __COMMON_UTILS_NR_NR_COMMON__H__
+#define __COMMON_UTILS_NR_NR_COMMON__H__
+
#include <stdint.h>
#include "assertions.h"
@@ -63,3 +66,5 @@ void SLIV2SL(int SLIV,int *S,int *L);
#define max(a,b) cmax(a,b)
#define min(a,b) cmin(a,b)
#endif
+
+#endif
diff --git a/common/utils/ocp_itti/intertask_interface.cpp b/common/utils/ocp_itti/intertask_interface.cpp
index 3d4d356dcf68aa5fb3b629cec010262952b4ec90..1680410ebb5294041eab45b1191922dda0feecc7 100644
--- a/common/utils/ocp_itti/intertask_interface.cpp
+++ b/common/utils/ocp_itti/intertask_interface.cpp
@@ -80,7 +80,7 @@ task_list_t tasks[TASK_MAX];
void *itti_malloc(task_id_t origin_task_id, task_id_t destination_task_id, ssize_t size) {
void *ptr = NULL;
- AssertFatal ((ptr=malloc (size)) != NULL, "Memory allocation of %zu bytes failed (%d -> %d)!\n",
+ AssertFatal ((ptr=calloc (size, 1)) != NULL, "Memory allocation of %zu bytes failed (%d -> %d)!\n",
size, origin_task_id, destination_task_id);
return ptr;
}
@@ -91,8 +91,16 @@ task_list_t tasks[TASK_MAX];
return (EXIT_SUCCESS);
}
+ // in the two following functions, the +32 in malloc is there to deal with gcc memory alignment
+ // because a struct size can be larger than sum(sizeof(struct components))
+ // We should remove the itti principle of a huge union for all types of messages in paramter "msg_t ittiMsg"
+ // to use a more C classical pointer casting "void * ittiMsg", later casted in the right struct
+ // but we would have to change all legacy macros, as per this example
+ // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_register_enb_req
+ // would become
+ // #define S1AP_REGISTER_ENB_REQ(mSGpTR) (s1ap_register_enb_req) mSGpTR)->ittiMsg
MessageDef *itti_alloc_new_message_sized(task_id_t origin_task_id, MessagesIds message_id, MessageHeaderSize size) {
- MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) + size);
+ MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, sizeof(MessageHeader) +32 + size);
temp->ittiMsgHeader.messageId = message_id;
temp->ittiMsgHeader.originTaskId = origin_task_id;
temp->ittiMsgHeader.ittiMsgSize = size;
@@ -100,7 +108,7 @@ task_list_t tasks[TASK_MAX];
}
MessageDef *itti_alloc_new_message(task_id_t origin_task_id, MessagesIds message_id) {
- int size=sizeof(MessageHeader) + messages_info[message_id].size;
+ int size=sizeof(MessageHeader) + 32 + messages_info[message_id].size;
MessageDef *temp = (MessageDef *)itti_malloc (origin_task_id, TASK_UNKNOWN, size);
temp->ittiMsgHeader.messageId = message_id;
temp->ittiMsgHeader.originTaskId = origin_task_id;
diff --git a/common/utils/ocp_itti/intertask_interface.h b/common/utils/ocp_itti/intertask_interface.h
index 0cd25ee23195a688be61ef3642f85e3f3761d5b6..026c8270d703672ec55706aa12b261580b1f9b02 100644
--- a/common/utils/ocp_itti/intertask_interface.h
+++ b/common/utils/ocp_itti/intertask_interface.h
@@ -256,6 +256,7 @@ typedef struct IttiMsgText_s {
//#include <proto.h>
#include <openair3/GTPV1-U/gtpv1u_eNB_task.h>
+#include <openair3/GTPV1-U/gtpv1u_gNB_task.h>
void *rrc_enb_process_itti_msg(void *);
#include <openair3/SCTP/sctp_eNB_task.h>
#include <openair3/S1AP/s1ap_eNB.h>
@@ -414,7 +415,7 @@ static const message_info_t messages_info[] = {
#undef MESSAGE_DEF
};
-typedef struct __attribute__ ((__packed__)) MessageDef_s {
+typedef struct MessageDef_s {
MessageHeader ittiMsgHeader; /**< Message header */
msg_t ittiMsg;
} MessageDef;
diff --git a/common/utils/telnetsrv/telnetsrv.c b/common/utils/telnetsrv/telnetsrv.c
index 06a5d350c75a452ef18e325813de53453912d66d..03f7af99bc2ca9cc8d81c7f834f7ad8dd2a2c7ce 100644
--- a/common/utils/telnetsrv/telnetsrv.c
+++ b/common/utils/telnetsrv/telnetsrv.c
@@ -53,6 +53,7 @@
#include <sys/resource.h>
#include "common/utils/load_module_shlib.h"
#include "common/config/config_userapi.h"
+#include "common/utils/threadPool/thread-pool.h"
#include "executables/softmodem-common.h"
#include <readline/history.h>
@@ -507,12 +508,22 @@ int process_command(char *buf) {
}
rt= CMDSTATUS_FOUND;
- } else if (strncasecmp(cmd,"get",3) == 0 || strncasecmp(cmd,"set",3) == 0) {
+ } else if (strcasecmp(cmd,"get") == 0 || strcasecmp(cmd,"set") == 0) {
rt= setgetvar(i,cmd[0],cmdb);
} else {
for (k=0 ; telnetparams.CmdParsers[i].cmd[k].cmdfunc != NULL ; k++) {
if (strncasecmp(cmd, telnetparams.CmdParsers[i].cmd[k].cmdname,sizeof(telnetparams.CmdParsers[i].cmd[k].cmdname)) == 0) {
- telnetparams.CmdParsers[i].cmd[k].cmdfunc(cmdb, telnetparams.telnetdbg, client_printf);
+ if (telnetparams.CmdParsers[i].cmd[k].qptr != NULL) {
+ notifiedFIFO_elt_t *msg =newNotifiedFIFO_elt(sizeof(telnetsrv_qmsg_t),0,NULL,NULL);
+ telnetsrv_qmsg_t *cmddata=NotifiedFifoData(msg);
+ cmddata->cmdfunc=(qcmdfunc_t)telnetparams.CmdParsers[i].cmd[k].cmdfunc;
+ cmddata->prnt=client_printf;
+ cmddata->debug=telnetparams.telnetdbg;
+ cmddata->cmdbuff=strdup(cmdb);
+ pushNotifiedFIFO(telnetparams.CmdParsers[i].cmd[k].qptr, msg);
+ } else {
+ telnetparams.CmdParsers[i].cmd[k].cmdfunc(cmdb, telnetparams.telnetdbg, client_printf);
+ }
rt= CMDSTATUS_FOUND;
}
} /* for k */
@@ -673,6 +684,16 @@ void run_telnetsrv(void) {
return;
}
+void poll_telnetcmdq(void *qid, void *arg) {
+ notifiedFIFO_elt_t *msg = pollNotifiedFIFO((notifiedFIFO_t *)qid);
+
+ if (msg != NULL) {
+ telnetsrv_qmsg_t *msgdata=NotifiedFifoData(msg);
+ msgdata->cmdfunc(msgdata->cmdbuff,msgdata->debug,msgdata->prnt,arg);
+ free(msgdata->cmdbuff);
+ delNotifiedFIFO_elt(msg);
+ }
+}
/*------------------------------------------------------------------------------------------------*/
/* load the commands delivered with the telnet server
*
@@ -758,6 +779,7 @@ int telnetsrv_autoinit(void) {
*/
int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd) {
int i;
+ notifiedFIFO_t *afifo=NULL;
if( modulename == NULL || var == NULL || cmd == NULL) {
fprintf(stderr,"[TELNETSRV] Telnet server, add_telnetcmd: invalid parameters\n");
@@ -769,6 +791,13 @@ int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmdde
strncpy(telnetparams.CmdParsers[i].module,modulename,sizeof(telnetparams.CmdParsers[i].module)-1);
telnetparams.CmdParsers[i].cmd = cmd;
telnetparams.CmdParsers[i].var = var;
+ if (cmd->cmdflags & TELNETSRV_CMDFLAG_PUSHINTPOOLQ) {
+ if (afifo == NULL) {
+ afifo = malloc(sizeof(notifiedFIFO_t));
+ initNotifiedFIFO(afifo);
+ }
+ cmd->qptr = afifo;
+ }
printf("[TELNETSRV] Telnet server: module %i = %s added to shell\n",
i,telnetparams.CmdParsers[i].module);
break;
@@ -797,8 +826,10 @@ int telnetsrv_checkbuildver(char *mainexec_buildversion, char **shlib_buildvers
}
int telnetsrv_getfarray(loader_shlibfunc_t **farray) {
- *farray=malloc(sizeof(loader_shlibfunc_t));
+ *farray=malloc(sizeof(loader_shlibfunc_t)*2);
(*farray)[0].fname=TELNET_ADDCMD_FNAME;
(*farray)[0].fptr=(int (*)(void) )add_telnetcmd;
- return 1;
+ (*farray)[1].fname=TELNET_POLLCMDQ_FNAME;
+ (*farray)[1].fptr=(int (*)(void) )poll_telnetcmdq;
+ return ( 2);
}
diff --git a/common/utils/telnetsrv/telnetsrv.h b/common/utils/telnetsrv/telnetsrv.h
index debb9f02ec962c63e798273bb19c481eff38f5c7..b66641d5c8b9588b8699c93b31326b5a418f5252 100644
--- a/common/utils/telnetsrv/telnetsrv.h
+++ b/common/utils/telnetsrv/telnetsrv.h
@@ -53,13 +53,26 @@
/* to add a set of new command to the telnet server shell */
typedef void(*telnet_printfunc_t)(const char* format, ...);
typedef int(*cmdfunc_t)(char*, int, telnet_printfunc_t prnt);
+typedef int(*qcmdfunc_t)(char*, int, telnet_printfunc_t prnt,void *arg);
+#define TELNETSRV_CMDFLAG_PUSHINTPOOLQ (1<<0) // ask the telnet server to push the command in a thread pool queue
typedef struct cmddef {
char cmdname[TELNET_CMD_MAXSIZE];
char helpstr[TELNET_HELPSTR_SIZE];
cmdfunc_t cmdfunc;
+ unsigned int cmdflags;
+ void *qptr;
} telnetshell_cmddef_t;
+/*----------------------------------------------------------------------------*/
+/* structure used to send a command via a message queue to enable */
+/* executing a command in a thread different from the telnet server thread */
+typedef struct telnetsrv_qmsg {
+ qcmdfunc_t cmdfunc;
+ telnet_printfunc_t prnt;
+ int debug;
+ char *cmdbuff;
+} telnetsrv_qmsg_t;
/*----------------------------------------------------------------------------*/
/*structure to be used when adding a module to the telnet server */
/* This is the first parameter of the add_telnetcmd function, which can be used */
@@ -111,9 +124,6 @@ typedef struct {
} telnetsrv_params_t;
-
-typedef int(*addcmdfunc_t)(char*, telnetshell_vardef_t*, telnetshell_cmddef_t*);
-
typedef void(*settelnetmodule_t)(char *name, void *ptr);
/*-------------------------------------------------------------------------------------------*/
@@ -133,7 +143,9 @@ VT escape sequence definition, for smarter display....
/*---------------------------------------------------------------------------------------------*/
#define TELNET_ADDCMD_FNAME "add_telnetcmd"
+#define TELNET_POLLCMDQ_FNAME "poll_telnetcmdq"
typedef int(*add_telnetcmd_func_t)(char *, telnetshell_vardef_t *, telnetshell_cmddef_t *);
+typedef void(*poll_telnetcmdq_func_t)(void *qid,void *arg);
#ifdef TELNETSERVERCODE
int add_telnetcmd(char *modulename, telnetshell_vardef_t *var, telnetshell_cmddef_t *cmd);
void set_sched(pthread_t tid, int pid,int priority);
diff --git a/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h b/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h
index 89ced509a4504a8c9b742bdbb3e1e9344936ab61..7a45b351f3231b24591cf15ac9e6a70df6441e54 100644
--- a/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h
+++ b/common/utils/telnetsrv/telnetsrv_cpumeasur_def.h
@@ -32,6 +32,8 @@
* \warning
*/
+#ifndef __TELNETSRV_CPUMEASUR_DEF__H__
+#define __TELNETSRV_CPUMEASUR_DEF__H__
#define CPU_PHYENB_MEASURE \
{ \
@@ -97,3 +99,5 @@
{"pdcp_ip", &(pdcpvars->pdcp_ip),0},\
{"ip_pdcp", &(pdcpvars->ip_pdcp),0},\
}
+
+#endif
diff --git a/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h b/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h
index 160111f15e8bca2abd60af3f63ef4d487ed6a2a6..c1aab51e23deff07ee933c4496a65279d9931359 100644
--- a/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h
+++ b/common/utils/telnetsrv/telnetsrv_ltemeasur_def.h
@@ -32,6 +32,8 @@
* \warning
*/
+#ifndef __TELNETSRV_LTEMEASUR_DEF__H__
+#define __TELNETSRV_LTEMEASUR_DEF__H__
#define LTEMAC_MEASURE \
{ \
@@ -125,3 +127,5 @@
{"timer_poll_retrans_tout", NULL, TELNET_VARTYPE_UINT, 0},\
{"timer_status_prohibit_tout", NULL, TELNET_VARTYPE_UINT, 0},\
}
+
+#endif
diff --git a/common/utils/telnetsrv/telnetsrv_measurements.h b/common/utils/telnetsrv/telnetsrv_measurements.h
index 80276bc2d03782c63c2339cdb542fd3a265e04e5..08136df0fda6d3325b8afd59f7f628c6086670cf 100644
--- a/common/utils/telnetsrv/telnetsrv_measurements.h
+++ b/common/utils/telnetsrv/telnetsrv_measurements.h
@@ -31,6 +31,10 @@
* \note
* \warning
*/
+
+#ifndef __TELNETSRV_MEASUREMENTS__H__
+#define __TELNETSRV_MEASUREMENTS__H__
+
#include <dlfcn.h>
#include "telnetsrv.h"
#include "openair1/PHY/defs_eNB.h"
@@ -97,3 +101,4 @@ extern uint64_t measurcmd_getstatvalue(telnet_ltemeasurdef_t *measur,telnet_prin
extern void measurcmd_display_measures(telnet_printfunc_t prnt, telnet_ltemeasurdef_t *statsptr, int stats_size);
#endif /* TELNETSRV_MEASURCMD_MAIN */
+#endif
diff --git a/common/utils/telnetsrv/telnetsrv_phycmd.h b/common/utils/telnetsrv/telnetsrv_phycmd.h
index e35b2a53ab4a6949403cf7a743f1781216b8d1e6..0d574027fbf825f26a2498f2734b91e605e62843 100644
--- a/common/utils/telnetsrv/telnetsrv_phycmd.h
+++ b/common/utils/telnetsrv/telnetsrv_phycmd.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __TELNETSRV_PHYCMD__H__
+#define __TELNETSRV_PHYCMD__H__
+
#ifdef TELNETSRV_PHYCMD_MAIN
#include "common/utils/LOG/log.h"
@@ -61,3 +64,4 @@ extern void add_phy_cmds(void);
/*-------------------------------------------------------------------------------------*/
+#endif
diff --git a/common/utils/telnetsrv/telnetsrv_proccmd.h b/common/utils/telnetsrv/telnetsrv_proccmd.h
index 1a0a8d25dc4006c74f5b9afe3c2b82db94db7e45..f130606b6c373031f927bc7140f2892f4f3e1819 100644
--- a/common/utils/telnetsrv/telnetsrv_proccmd.h
+++ b/common/utils/telnetsrv/telnetsrv_proccmd.h
@@ -30,6 +30,10 @@
* \note
* \warning
*/
+
+#ifndef __TELNETSRV_PROCCMD__H__
+#define __TELNETSRV_PROCCMD__H__
+
#include <dlfcn.h>
#include "telnetsrv.h"
@@ -79,3 +83,4 @@ telnetshell_cmddef_t proc_cmdarray[] = {
extern void add_proccmd_cmds(void);
#endif /* TELNETSRV_PROCCMD_MAIN */
+#endif
diff --git a/common/utils/threadPool/thread-pool.c b/common/utils/threadPool/thread-pool.c
index cbb2dbe3d91742afc2375ff3fd48f90b20c48404..e1446f15d71a70d374851ba9cfa5f4707590c58b 100644
--- a/common/utils/threadPool/thread-pool.c
+++ b/common/utils/threadPool/thread-pool.c
@@ -111,9 +111,10 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) {
pool->activated=true;
initNotifiedFIFO(&pool->incomingFifo);
char *saveptr, * curptr;
+ char *parms_cpy=strdup(params);
pool->nbThreads=0;
pool->restrictRNTI=false;
- curptr=strtok_r(params,",",&saveptr);
+ curptr=strtok_r(parms_cpy,",",&saveptr);
struct one_thread * ptr;
while ( curptr!=NULL ) {
int c=toupper(curptr[0]);
@@ -145,7 +146,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) {
curptr=strtok_r(NULL,",",&saveptr);
}
-
+ free(parms_cpy);
if (pool->activated && pool->nbThreads==0) {
printf("No servers created in the thread pool, exit\n");
exit(1);
diff --git a/doc/BUILD.md b/doc/BUILD.md
index 9ada32e532eec1829f68c1d357e808c0680c8939..97f904759695aeb3c43f659ab3fbbc079df71821 100644
--- a/doc/BUILD.md
+++ b/doc/BUILD.md
@@ -16,7 +16,6 @@ This page is valid on tags starting from **`2019.w09`**.
# Soft Modem Build Script
-oai EPC is developed in a distinct project with it's own [documentation](https://github.com/OPENAIRINTERFACE/openair-cn/wiki) , it is not described here.
OAI softmodem sources, which aim to implement 3GPP compliant UEs, eNodeB and gNodeB can be downloaded from the Eurecom [gitlab repository](./GET_SOURCES.md).
diff --git a/doc/FEATURE_SET.md b/doc/FEATURE_SET.md
index f71b9acb33e68ca1cff2dd347f62e811ad6bd309..23d32effbbdef58bf8a0d530b4eb7b397a9ae918 100644
--- a/doc/FEATURE_SET.md
+++ b/doc/FEATURE_SET.md
@@ -1,6 +1,8 @@
**Table of Contents**
-1. [OpenAirInterface eNB Feature Set](#openairinterface-enb-feature-set)
+1. [Functional Split Architecture](#functional-split-architecture)
+2. [OpenAirInterface Block Diagram](#openairinterface-block-diagram)
+2. [OpenAirInterface 4G-LTE eNB Feature Set](#openairinterface-4g-lte-enb-feature-set)
1. [eNB PHY Layer](#enb-phy-layer)
2. [eNB MAC Layer](#enb-mac-layer)
3. [eNB RLC Layer](#enb-rlc-layer)
@@ -9,29 +11,38 @@
6. [eNB X2AP](#enb-x2ap)
7. [eNB/MCE M2AP](#enbmce-m2ap)
8. [MCE/MME M3AP](#mcemme-m3ap)
- 9. [eNB Advanced Features](#enb-advanced-features)
-2. [OpenAirInterface Functional Split](#openairinterface-functional-split)
-3. [OpenAirInterface UE Feature Set](#openairinterface-ue-feature-set)
+3. [OpenAirInterface 4G-LTE UE Feature Set](#openairinterface-4g-lte-ue-feature-set)
1. [LTE UE PHY Layer](#lte-ue-phy-layer)
2. [LTE UE MAC Layer](#lte-ue-mac-layer)
3. [LTE UE RLC Layer](#lte-ue-rlc-layer)
4. [LTE UE PDCP Layer](#lte-ue-pdcp-layer)
5. [LTE UE RRC Layer](#lte-ue-rrc-layer)
-4. [OpenAirInterface Functional Split](#openairinterface-functional-split)
-5. [OpenAirInterface 5G-NR Feature Set](#openairinterface-5g-nr-feature-set)
+4. [OpenAirInterface 5G-NR gNB Feature Set](#openairinterface-5g-nr-feature-set)
1. [General Parameters](#general-parameters)
- 2. [gNB Features](#gnb-features)
- 1. [gNB Physical Layer](#gnb-phy-layer)
- 2. [gNB Higher Layers](#gnb-higher-layers)
- 3. [NR UE Features](#nr-ue-features)
- 1. [NR UE Physical Layer](#nr-ue-phy-layer)
- 2. [NR UE Higher Layers](#nr-ue-higher-layers)
+ 2. [gNB Physical Layer](#gnb-phy-layer)
+ 3. [gNB Higher Layers](#gnb-higher-layers)
+5. [OpenAirInterface 5G-NR UE Feature Set](#openairinterface-5g-nr-ue-feature-set)
+ 1. [UE Physical Layer](#ue-phy-layer)
+ 2. [UE Higher Layers](#ue-higher-layers)
-# OpenAirInterface Block diagram #
+
+# Functional Split Architecture #
+
+- RCC: Radio-Cloud Center
+- RAU: Radio-Access Unit
+- RRU: Remote Radio-Unit
+- IF4.5 / IF5 : similar to IEEE P1914.1
+- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation)
+- IF1 : F1 in 3GPP Release 15
+
+
+
+
+# OpenAirInterface Block Diagram #
-# OpenAirInterface eNB Feature Set #
+# OpenAirInterface 4G LTE eNB Feature Set #
## eNB PHY Layer ##
@@ -82,7 +93,11 @@ TDD UL: 20 MHz, 100 PRBS/ MCS **XX** | 3.0 Mbit/s | TM1: 4.21 Mbits/s
The MAC layer implements a subset of the **3GPP 36.321** release v8.6 in support of BCH, DLSCH, RACH, and ULSCH channels.
- RRC interface for CCCH, DCCH, and DTCH
-- Proportional fair scheduler (round robin scheduler soon)
+- Proportional fair scheduler (round robin scheduler soon), with the following improvements:
+ - Up to 30 users tested in the L2 simulator, CCE allocation in the preprocessor ; the scheduler was also simplified and made more modular
+ - Adaptative UL-HARQ
+ - Remove out-of-sync UEs
+ - No use of the `first_rb` in the UL scheduler ; respects `vrb_map_UL` and `vrb_map` in the DL
- DCI generation
- HARQ Support
- RA procedures and RNTI management
@@ -123,7 +138,7 @@ The current PDCP layer is header compliant with **3GPP 36.323** Rel 10.1.0 and i
## eNB RRC Layer ##
-The RRC layer is based on **3GPP 36.331** v14.3.0 and implements the following functions:
+The RRC layer is based on **3GPP 36.331** v15.6 and implements the following functions:
- System Information broadcast (SIB 1, 2, 3, and 13)
* SIB1: Up to 6 PLMN IDs broadcast
@@ -150,6 +165,10 @@ The X2AP layer is based on **3GPP 36.423** v14.6.0 and implements the following
- X2 timers (t_reloc_prep, tx2_reloc_overall)
- Handover Cancel
- X2-U interface implemented
+ - EN-DC is implemented
+ - X2AP : Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete
+ - RRC : Handling of RRC Connection Reconfiguration with 5G cell info, configuration of 5G-NR measurements
+ - S1AP : Handling of E-RAB Modification Indication / Confirmation
## eNB/MCE M2AP ##
@@ -171,11 +190,8 @@ The M3AP layer is based on **3GPP 36.444** v14.0.1:
- M3 Session Start Request
- M3 Session Start Response
-## eNB Advanced Features ##
-**To be completed**
-
-# OpenAirInterface UE Feature Set #
+# OpenAirInterface 4G LTE UE Feature Set #
## LTE UE PHY Layer ##
@@ -230,17 +246,6 @@ The NAS layer is based on **3GPP 24.301** and implements the following functions
- EMM attach/detach, authentication, tracking area update, and more
- ESM default/dedicated bearer, PDN connectivity, and more
-# OpenAirInterface Functional Split #
-
-- RCC: Radio-Cloud Center
-- RAU: Radio-Access Unit
-- RRU: Remote Radio-Unit
-
-
-
-- IF4.5 / IF5 : similar to IEEE P1914.1
-- FAPI (IF2) : specified by Small Cell Forum (open-nFAPI implementation)
-- IF1 : F1 in 3GPP Release 15
# OpenAirInterface 5G-NR Feature Set #
@@ -258,49 +263,103 @@ The following features are valid for the gNB and the 5G-NR UE.
* Highly efficient 3GPP compliant polar encoder and decoder
* Encoder and decoder for short blocks
-## gNB Features ##
-### gNB PHY Layer ###
+## gNB PHY Layer ##
-* Generation of PSS/SSS/PBCH for multiple beams and
-* Generation of PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc)
+* 30KHz SCS for FR1 and 120 KHz SCS for FR2
+* Generation of NR-PSS/NR-SSS
+* NR-PBCH supports multiple SSBs and flexible periodicity
+* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc)
- common search space configured by MIB
- user-specific search space configured by RRC
- - DCI formats: 00, 10
-* Generation of PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
- - Single symbol DMRS, dmrs-TypeA-Position Pos2, DMRS configuration type 1
- - PDSCH mapping type A
+ - DCI formats: 00, 10 (01 and 11 **under integration**)
+* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
+ - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1
+ - PDSCH mapping type A
+* NR-CSI Generation of sequence at PHY (**under integration**)
* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
* NR-PUCCH
- - Format 0 (ACK/NACK)
+ - Format 0 (2 bits, mainly for ACK/NACK)
+ - Format 2 (up to 64 bits, mainly for CSI feedback)
+* NR-PRACH
+ - Formats 0,1,2,3, A1-A3, B1-B3
+* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported)
+* Highly efficient 3GPP compliant polar encoder and decoder
+* Encoder and decoder for short block
-### gNB higher Layers ###
-
+## gNB Higher Layers ##
+
+**gNB RRC**
- NR RRC (38.331) Rel 15 messages using new asn1c
- LTE RRC (36.331) also updated to Rel 15
-- Generation of MIB
+- Generation of CellGroupConfig (for eNB) and MIB
- Application to read configuration file and program gNB RRC
-- RRC -> MAC configuration
-- MAC -> PHY configuration (using NR FAPI P5 interface)
-- FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
+- RRC can configure PDCP, RLC, MAC
+
+**gNB X2AP**
+- X2 setup with eNB
+- Handling of SgNB Addition Request / Addition Request Acknowledge / Reconfiguration Complete
+
+**gNB MAC**
+- MAC -> PHY configuration using NR FAPI P5 interface
+- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
+- Scheduler for RA procedreat gNB
+- MAC downlink scheduler (fixed allocations)
+- MAC header generation (including timing advance)
+- ACK / NACK handling and HARQ procedures for downlink
+- **As of May 2020** only DL was validated with COTS phone ; UL in progress, validated with OAI UE in noS1 mode
+
+# OpenAirInterface 5G-NR UE Feature Set #
+
+**as of May 2020** only supporting "noS1" mode (DL):
+- Creates TUN interface to PDCP to inject and receive user-place traffic
+- Will only work with OAI gNB configured in the same mode
+
+## UE PHY Layer ##
+
+* Initial synchronization
+* Time tracking based on PBCH DMRS
+* Time tracking based on PBCH DMRS
+* Frequency offset estimation
+* PBCH RX
+* PDCCH RX
+* PDSCH RX, including a first version of dual stream receiver for PDSCH
+* 30KHz SCS for FR1 and 120 KHz SCS for FR2
+* Generation of NR-PSS/NR-SSS
+* NR-PBCH supports multiple SSBs and flexible periodicity
+* Generation of NR-PDCCH for SIB1 (including generation of DCI, polar encoding, scrambling, modulation, RB mapping, etc)
+ - common search space configured by MIB
+ - user-specific search space configured by RRC
+ - DCI formats: 00, 10 (01 and 11 **under integration**)
+* Generation of NR-PDSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
+ - Single symbol DMRS, DMRS-TypeA-Position Pos2, DMRS configuration type 1
+ - PDSCH mapping type A
+* NR-CSI Generation of sequence at PHY (**under integration**)
+* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
+* NR-PUCCH
+ - Format 0 (2 bits, mainly for ACK/NACK)
+ - Format 2 (up to 64 bits, mainly for CSI feedback)
+* NR-PRACH
+ - Formats 0,1,2,3, A1-A3, B1-B3
+* Highly efficient 3GPP compliant LDPC encoder and decoder (BG1 and BG2 are supported)
+* Highly efficient 3GPP compliant polar encoder and decoder
+* Encoder and decoder for short block
+
+
+## UE Higher Layers ##
-For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/ba5368448d627743a28c770c29e8978e/OAI_Software_Architecture_for_Dual_Connectivity_in_E-UTRA_and_5G-NR_and_nFAPI_for_MAC-PHY_Interface.docx)
+**gNB MAC**
+- Initial sync and MIB detection
+- MAC -> PHY configuration of PHY via UE FAPI P5 interface
+- Basic MAC to control PHY via UE FAPI P7 interface
+- Random access procedure
-## NR UE Features ##
-### NR UE PHY Layer ###
+**RLC**
-- initial synchronization
-- Time tracking based on PDCCH DMRS
-- Frequency offset estimation
-- PBCH RX
-- PDCCH RX
-- PDSCH RX
- - including first version of dual stream receiver for PDSCH
+**PDCP**
-### NR UE higher Layers ###
-For more details see [this document](https://gitlab.eurecom.fr/oai/openairinterface5g/uploads/f7386f3a64806fd6b2ac1fc3d0252fff/UE_FAPI-like_interface.docx)
[OAI wiki home](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home)
diff --git a/doc/RUNMODEM.md b/doc/RUNMODEM.md
index 0c66b585478bc7f7cf5809a77b46c28e0f1e90ed..37eadd92f34a8de9cbfd9f4867dbea67d74ef7b0 100644
--- a/doc/RUNMODEM.md
+++ b/doc/RUNMODEM.md
@@ -56,9 +56,56 @@ oai supports [number of deployment](FEATURE_SET.md) model, the following are tes
1. [Monolithic eNodeB](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/HowToConnectCOTSUEwithOAIeNBNew) where the whole signal processing is performed in a single process
2. if4p5 mode, where frequency domain samples are carried over ethernet, from the RRU which implement part of L1(FFT,IFFT,part of PRACH), to a RAU
+# 5G NR
+As of February 2020, all 5G NR development is part of the develop branch (the branch develop-nr is no longer maintained). This also means that all new development will be merged into there once it passes all the CI.
+## NSA setup with COTS UE
+This setup requires an EPC, an OAI eNB and gNB, and a COTS Phone. A dedicated page describe the setup can be found [here](https://gitlab.eurecom.fr/oai/openairinterface5g/wikis/home/gNB-COTS-UE-testing).
+
+### Launch gNB
+
+```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf```
+
+### Launch eNB
+
+```bash sudo ./lte-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.50PRB.usrpb210.conf```
+
+
+
+## phy-test setup with OAI UE
+
+The OAI UE can also be used in front of a OAI gNB without the support of eNB or EPC. In this case both gNB and eNB need to be run with the --phy-test flag. At the gNB this flag does the following
+ - it reads the RRC configuration from the configuration file
+ - it encodes the RRCConfiguration and the RBconfig message and stores them in the binary files rbconfig.raw and reconfig.raw
+ - the MAC uses a pre-configured allocation of PDSCH and PUSCH with randomly generated payload
+
+At the UE the --phy-test flag will
+ - read the binary files rbconfig.raw and reconfig.raw from the current directory (a different directory can be specified with the flag --rrc_config_path) and process them.
+
+
+### Launch gNB
+
+```bash sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf --phy-test```
+
+### Launch UE in another window
+
+```bash sudo ./nr-uesoftmodem --phy-test [--rrc_config_path ../../../ci-scripts/rrc-files]```
+
+Some other useful paramters of the UE are
+
+ - --ue-fo-compensation: enables the frequency offset compenstation at the UE. This is useful when running over the air and/or without an external clock/time source
+ - --usrp-args: this is the equivalend paramter of sdr_addrs field in the gNB config file and can be used to identify the USRP and set some basic paramters (like the clock source)
+ - --clock-source: sets the clock-source (internal or external).
+ - --time-source: sets the time-source (internal or external).
+
+
+## noS1 setup with OAI UE
+
+Instead of randomly generated payload, in the phy-test mode we can also inject/receive user-plane traffic over a TUN interface. This is the so-called noS1 mode.
+
+This setup is described in the [rfsimulator page](../targets/ARCH/rfsimulator/README.md#5g-case). In theory this should also work with the real hardware target although this has yet to be tested.
diff --git a/doc/TESTING_GNB_W_COTS_UE.md b/doc/TESTING_GNB_W_COTS_UE.md
new file mode 100644
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+STATUS 2020/07/30 : under continuous improvement ; updated the configuration files links with CI approved reference files
+
+
+## Table of Contents ##
+
+1. [Configuration Overview](#configuration-overview)
+2. [SW Repository / Branch](#repository)
+3. [Architecture Setup](#architecture-setup)
+4. [Build / Install](#build-and-install)
+5. [Run / Test](#run-and-test)
+6. [Test case](#test-case)
+7. [Log file monitoring](#log-file-monitoring)
+6. [Required tools for debug](#required-tools-for-debug)
+7. [Status of interoperability](#status-of-interoperability)
+
+## Configuration Overview
+
+* Non Standalone (NSA) configuration : initial Control Plane established between UE and RAN eNB, then User Plane established between UE and gNB, Core network is 4G based supporting rel 15
+
+* Commercial UE: Oppo Reno 5G
+* OAI Software Defined gNB and eNB
+* eNB RF front end: USRP (ETTUS) B200 Mini or B210
+* gNB RF front end: USRP (ETTUS) B200 Mini or B210 (N310 will be needed for MIMO and wider BW's)
+* 5G TDD duplexing mode
+* 5G FR1 Band n78 (3.5 GHz)
+* BW: 40MHz
+* Antenna scheme: SISO
+
+## Repository
+
+https://gitlab.eurecom.fr/oai/openairinterface5g/tree/develop
+
+## Architecture Setup
+
+The scheme below depicts our typical setup:
+
+
+
+The photo depicts the FR1 setup part of the scheme above:
+
+
+
+
+## Build and Install
+
+General guidelines to build eNB and gNB :
+See https://gitlab.eurecom.fr/oai/openairinterface5g/blob/develop/doc/BUILD.md#building-ues-enodeb-and-gnodeb-executables
+
+
+- **eNB**
+
+```
+cd <your oai installation directory>/openairinterface5g/
+source oaienv
+cd cmake_targets/
+./build_oai -I -w USRP --eNB
+
+```
+
+- **gNB**
+
+```
+cd <your oai installation directory>/openairinterface5g/
+source oaienv
+cd cmake_targets/
+./build_oai -I -w USRP --gNB
+```
+
+
+- **EPC**
+
+for reference:
+https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md
+
+
+
+## Configuration Files
+
+Each component (EPC, eNB, gNB) has its own configuration file.
+These config files are passed as arguments of the run command line, using the option -O \<conf file\>
+
+The **REFERENCE** files for eNB and gNB, **used by the CI**, can be found here:
+[enb conf file](../ci-scripts/conf_files/enb.band7.tm1.fr1.25PRB.usrpb210.conf)
+[gnb conf file](../ci-scripts/conf_files/gnb.band78.tm1.fr1.106PRB.usrpb210.conf)
+
+These files have to be updated manually to set the IP addresses and frequency.
+
+
+**ATTENTION** : an **EXTERNAL** clock is used to sync the eNB and gNB,
+whether the clock is internal or external is defined in the configuration files (!! details needed !!)
+
+
+1- In the **eNB configuration file** :
+- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server
+```
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+```
+
+- look for S1 IP address, and update the **3 fields below** with the IP address of the **eNB** server
+```
+ NETWORK_INTERFACES :
+ {
+ ENB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ ENB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_ENB_IP_ADDR**";
+ ENB_INTERFACE_NAME_FOR_S1U = "eth0";
+ ENB_IPV4_ADDRESS_FOR_S1U = "**YOUR_ENB_IP_ADDR**";
+ ENB_PORT_FOR_S1U = 2152; # Spec 2152
+ ENB_IPV4_ADDRESS_FOR_X2C = "**YOUR_ENB_IP_ADDR**";
+ ENB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+
+```
+
+2- In the **gNB configuration file** :
+- look for MME IP address, and update the **ipv4 field** with the IP address of the **EPC** server
+```
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "**YOUR_EPC_IP_ADDR**";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+```
+- look for X2 IP address, and update the **4 fields** with the IP address of the **eNB** server / **gNB** server as below (notice : even if -in principle- S1 MME is not required for gNB setting)
+```
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+ target_enb_x2_ip_address = (
+ { ipv4 = "**YOUR_ENB_IP_ADDR**";
+ ipv6 = "192:168:30::17";
+ preference = "ipv4";
+ }
+ );
+
+ NETWORK_INTERFACES :
+ {
+
+ GNB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1_MME = "**YOUR_GNB_IP_ADDR**";
+ GNB_INTERFACE_NAME_FOR_S1U = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1U = "**YOUR_GNB_IP_ADDR**";
+ GNB_PORT_FOR_S1U = 2152; # Spec 2152
+ GNB_IPV4_ADDRESS_FOR_X2C = "**YOUR_GNB_IP_ADDR**";
+ GNB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+
+
+```
+
+
+
+3- The frequency setting requires a manual update in the .C and in the gNB conf file:
+
+
+In the C file **openair2/RRC/LTE/rrc_eNB.c:3217**
+set the nrarfcn to the same value as absoluteFrequencySSB in the **gNB config file**, that is **641272** in the example below
+
+C file :
+```
+MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272;
+```
+
+gNB config file :
+
+```
+ # absoluteFrequencySSB is the central frequency of SSB
+ absoluteFrequencySSB = 641272;
+ dl_frequencyBand = 78;
+ # the carrier frequency is assumed to be in the middle of the carrier, i.e. dl_absoluteFrequencyPointA_kHz + dl_carrierBandwidth*12*SCS_kHz/2
+ dl_absoluteFrequencyPointA = 640000;
+ #scs-SpecificCarrierList
+ dl_offstToCarrier = 0;
+ # subcarrierSpacing
+ # 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ dl_subcarrierSpacing = 1;
+ dl_carrierBandwidth = 106;
+```
+
+
+## Run and Test
+
+The order to run the different components is important:
+1- first, CN
+2- then, eNB
+3- then, gNB
+4- finally, switch UE from airplane mode OFF to ON
+
+It is recommended to redirect the run commands to the same log file (fur further analysis and debug), using ```| tee **YOUR_LOG_FILE**``` especially for eNB and gNB.
+It is not very useful for the CN.
+
+The test takes typically a few seconds, max 10-15 seconds. If it takes more than 30 seconds, there is a problem.
+
+- **EPC** (on EPC host):
+
+for reference:
+https://github.com/OPENAIRINTERFACE/openair-epc-fed/blob/master-documentation/docs/DEPLOY_HOME.md
+
+
+
+- **eNB** (on the eNB host):
+
+Execute:
+```
+~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./lte-softmodem -O **YOUR_ENB_CONF_FILE** | tee **YOUR_LOG_FILE**
+
+```
+
+
+- **gNB** (on the gNB host)
+
+
+Execute:
+```
+~/openairinterface5g/cmake_targets/ran_build/build$ sudo ./nr-softmodem -O **YOUR_GNB_CONF_FILE** -E | tee **YOUR_LOG_FILE**
+
+```
+
+**ATTENTION** : for the gNB execution,
+The -E option is required to enable the tri-quarter sampling rate when using a B2xx serie USRP
+The -E opton is not needed when using a a N300 USRP
+
+
+
+## Test Case
+
+The test case corresponds to the UE attachement, that is the UE connection and its initial access in 5G, as depicted below:
+
+**Source** : https://www.sharetechnote.com/html/5G/5G_LTE_Interworking.html
+
+
+
+The test reaches step **12. E-RAB modifcation confirmation** , eventhough not all the messages will appear in the log file.
+
+## Log file monitoring
+
+From the log file that is generated, we can monitor several important steps, to assess that the test was successful.
+Log files examples can be found here:
+[enb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_enb.log)
+[gnb log file](https://gitlab.eurecom.fr/oai/openairinterface5g/-/blob/rh_doc_update_3/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log)
+
+
+- eNB receives UE capabilities information, including its NR capabilites, and triggers sGNB Addition Request message:
+
+***eNBlog.1315 :***
+```
+[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE
+...
+[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode
+...
+<X2AP-PDU>
+ <initiatingMessage>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequest>
+ <protocolIEs>
+ <SgNBAdditionRequest-IEs>
+ <id>111</id>
+<criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequest-IEs>
+```
+
+- gNB receives sGNB Addition request, processes UE capabilities for the corresponding UE and triggers sGNB Addition Request ACK, carrying NR RRC Reconfiguration message:
+
+
+***gNBlog.2291 :***
+```
+<X2AP-PDU>
+ <successfulOutcome>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequestAcknowledge>
+ <protocolIEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>111</id>
+<criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+```
+
+
+- Upon reception of the sGNB Addition Request ACK, the eNB sends a new RRCConnectionReconfiguration message containing the NR Reconfiguration.
+The UE replies with a Reconfiguration Complete message:
+
+***eNBlog.1686 :***
+```
+[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1)
+```
+
+- The Random Access procedure of the UE to the gNB takes place:
+
+***gNBlog.2382 :***
+```
+[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with
+preamble 63, energy 35.7 dB, delay 6
+ [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA
+procedure for preamble index 63
+ [0m [0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2
+generation in frame 752, slot 7 using RA rnti 10b
+ [0m [0m[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating
+RAR DCI, state 1
+ [0m [0m[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24),
+time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0
+ [0m [0m[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b
+ [0m [0m[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame
+752 Subframe 17
+ [0m [0m[PHY] ULSCH received ok
+```
+
+- The eNB triggers the path switch procedure towards the MME, so that
+the traffic can be routed now from the SGW towards the gNB on the S1-U
+plane.
+
+***eNBlog.1691 :***
+```
+<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>50</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABModificationIndication>
+ <protocolIEs>
+ <E-RABModificationIndicationIEs>
+ <id>0</id>
+<criticality><reject/></criticality>
+ <value>
+<MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </E-RABModificationIndicationIEs>
+```
+
+
+Eventually, step **12. E-RAB Modification Confirmation** is successfully reached
+
+
+
+## Required tools for debug
+
+- **Wireshark** to trace X2AP and S1AP protocols
+- **Ttracer** for 5G messages
+- **GDB debugger** to check function calls
+
+
+## Status of interoperability
+
+The following parts have been validated with FR1 COTS UE:
+
+- Phone accepts the configurtion provided by OAI eNB:
+ this validates RRC and X2AP
+
+- Successful Random Access Procedure:
+ PRACH is correctly decoded at gNB
+ Phone correctly receives and decodes msg2 (NR PDCCH Format 1_0 and NR PDSCH)
+ msg3 is transmitted to gNB according to the configuration sent in msg2, and received correctly at gNB
+
+- Successful path switch of user plane traffic from 4G to 5G cell (E-RAB modification message):
+ this validates S1AP
+
+- Downlink traffic:
+ PDCCH DCI format 1_1 and correponding PDSCH are decoded correctlyby the phone
+ ACK/NACK (PUCCH format 0) are successfully received at gNB
+
+- On going:
+ validation of HARQ procedures
+ Integration with higher layers to replace dummy data with real traffic
+
+- Known limitations as of May 2020:
+ only dummy DL traffic
+ no UL traffic
+ no end-to-end traffic possible
+
+
diff --git a/doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg b/doc/testing_gnb_w_cots_ue_resources/attach_signaling_scheme.jpg
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diff --git a/doc/testing_gnb_w_cots_ue_resources/enb.conf b/doc/testing_gnb_w_cots_ue_resources/enb.conf
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+Active_eNBs = ( "eNB-Eurecom-LTEBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+eNBs =
+(
+ {
+ # real_time choice in {hard, rt-preempt, no}
+ real_time = "no";
+ ////////// Identification parameters:
+ eNB_ID = 0xe01;
+
+ cell_type = "CELL_MACRO_ENB";
+
+ eNB_name = "eNB-Eurecom-LTEBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+ plmn_list = (
+ { mcc = 222; mnc = 01; mnc_length = 2; }
+ );
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ component_carriers = (
+ {
+ node_function = "eNodeB_3GPP";
+ node_timing = "synch_to_ext_device";
+ node_synch_ref = 0;
+ nb_antenna_ports = 1;
+ ue_TransmissionMode = 1;
+ frame_type = "FDD";
+ tdd_config = 3;
+ tdd_config_s = 0;
+ prefix_type = "NORMAL";
+ eutra_band = 7;
+ downlink_frequency = 2680000000L; //2655000000L;
+ uplink_frequency_offset = -120000000;
+
+ Nid_cell = 0;
+ N_RB_DL = 25; //100;
+ Nid_cell_mbsfn = 0;
+ nb_antennas_tx = 1;
+ nb_antennas_rx = 1;
+ prach_root = 0;
+ tx_gain = 90;
+ rx_gain = 115;
+ pbch_repetition = "FALSE";
+ prach_config_index = 0;
+ prach_high_speed = "DISABLE";
+ prach_zero_correlation = 1;
+ prach_freq_offset = 2;
+ pucch_delta_shift = 1;
+ pucch_nRB_CQI = 0;
+ pucch_nCS_AN = 0;
+ pucch_n1_AN = 0;
+ pdsch_referenceSignalPower = -29;
+ pdsch_p_b = 0;
+ pusch_n_SB = 1;
+ pusch_enable64QAM = "DISABLE";
+ pusch_hoppingMode = "interSubFrame";
+ pusch_hoppingOffset = 0;
+ pusch_groupHoppingEnabled = "ENABLE";
+ pusch_groupAssignment = 0;
+ pusch_sequenceHoppingEnabled = "DISABLE";
+ pusch_nDMRS1 = 1;
+ phich_duration = "NORMAL";
+ phich_resource = "ONESIXTH";
+ srs_enable = "DISABLE";
+ /* srs_BandwidthConfig =;
+ srs_SubframeConfig =;
+ srs_ackNackST =;
+ srs_MaxUpPts =;*/
+
+ pusch_p0_Nominal = -96;
+ pusch_alpha = "AL1";
+ pucch_p0_Nominal = -96;
+ msg3_delta_Preamble = 6;
+ pucch_deltaF_Format1 = "deltaF2";
+ pucch_deltaF_Format1b = "deltaF3";
+ pucch_deltaF_Format2 = "deltaF0";
+ pucch_deltaF_Format2a = "deltaF0";
+ pucch_deltaF_Format2b = "deltaF0";
+
+ rach_numberOfRA_Preambles = 64;
+ rach_preamblesGroupAConfig = "DISABLE";
+/*
+ rach_sizeOfRA_PreamblesGroupA = ;
+ rach_messageSizeGroupA = ;
+ rach_messagePowerOffsetGroupB = ;
+*/
+ rach_powerRampingStep = 4;
+ rach_preambleInitialReceivedTargetPower = -108;
+ rach_preambleTransMax = 10;
+ rach_raResponseWindowSize = 10;
+ rach_macContentionResolutionTimer = 48;
+ rach_maxHARQ_Msg3Tx = 4;
+
+ pcch_default_PagingCycle = 128;
+ pcch_nB = "oneT";
+ bcch_modificationPeriodCoeff = 2;
+ ue_TimersAndConstants_t300 = 1000;
+ ue_TimersAndConstants_t301 = 1000;
+ ue_TimersAndConstants_t310 = 1000;
+ ue_TimersAndConstants_t311 = 10000;
+ ue_TimersAndConstants_n310 = 20;
+ ue_TimersAndConstants_n311 = 1;
+
+ //Parameters for SIB18
+ rxPool_sc_CP_Len = "normal";
+ rxPool_sc_Period = "sf40";
+ rxPool_data_CP_Len = "normal";
+ rxPool_ResourceConfig_prb_Num = 20;
+ rxPool_ResourceConfig_prb_Start = 5;
+ rxPool_ResourceConfig_prb_End = 44;
+ rxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ rxPool_ResourceConfig_offsetIndicator_choice = 0;
+ rxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+/* rxPool_dataHoppingConfig_hoppingParameter = 0;
+ rxPool_dataHoppingConfig_numSubbands = "ns1";
+ rxPool_dataHoppingConfig_rbOffset = 0;
+ rxPool_commTxResourceUC-ReqAllowed = "TRUE";
+*/
+ // Parameters for SIB19
+ discRxPool_cp_Len = "normal"
+ discRxPool_discPeriod = "rf32"
+ discRxPool_numRetx = 1;
+ discRxPool_numRepetition = 2;
+ discRxPool_ResourceConfig_prb_Num = 5;
+ discRxPool_ResourceConfig_prb_Start = 3;
+ discRxPool_ResourceConfig_prb_End = 21;
+ discRxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ discRxPool_ResourceConfig_offsetIndicator_choice = 0;
+ discRxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+
+ }
+ );
+
+ srb1_parameters :
+ {
+ # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
+ timer_poll_retransmit = 80;
+
+ # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
+ timer_reordering = 35;
+
+ # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
+ timer_status_prohibit = 0;
+
+ # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
+ poll_pdu = 4;
+
+ # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
+ poll_byte = 99999;
+
+ # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
+ max_retx_threshold = 4;
+ }
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+ enable_measurement_reports = "yes";
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "192.168.18.99";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+
+ NETWORK_INTERFACES :
+ {
+ ENB_INTERFACE_NAME_FOR_S1_MME = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24";
+
+ ENB_INTERFACE_NAME_FOR_S1U = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24";
+ ENB_PORT_FOR_S1U = 2152; # Spec 2152
+
+ ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24";
+ ENB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="debug";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ phy_test_mode = 0;
+ puSch10xSnr = 160;
+ puCch10xSnr = 160;
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa";
+ worker_config = "ENABLE";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 118;
+ eNB_instances = [0];
+
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
diff --git a/doc/testing_gnb_w_cots_ue_resources/gnb.conf b/doc/testing_gnb_w_cots_ue_resources/gnb.conf
new file mode 100755
index 0000000000000000000000000000000000000000..db8aef33ba6ea5dfb94a589596c3deba401eab3f
--- /dev/null
+++ b/doc/testing_gnb_w_cots_ue_resources/gnb.conf
@@ -0,0 +1,293 @@
+Active_gNBs = ( "gNB-Eurecom-5GNRBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+gNBs =
+(
+ {
+ ////////// Identification parameters:
+ gNB_ID = 0xe00;
+
+ cell_type = "CELL_MACRO_GNB";
+
+ gNB_name = "gNB-Eurecom-5GNRBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+
+ plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;});
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ ssb_SubcarrierOffset = 31; //0;
+ pdsch_AntennaPorts = 1;
+
+ servingCellConfigCommon = (
+ {
+ #spCellConfigCommon
+
+ physCellId = 0;
+
+# downlinkConfigCommon
+ #frequencyInfoDL
+ # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP)
+ absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell
+ dl_frequencyBand = 78;
+ # this is 3600 MHz
+ dl_absoluteFrequencyPointA = 640000;
+ #scs-SpecificCarrierList
+ dl_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ dl_subcarrierSpacing = 1;
+ dl_carrierBandwidth = 106;
+ #initialDownlinkBWP
+ #genericParameters
+ # this is RBstart=84,L=13 (275*(L-1))+RBstart
+ initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialDLBWPsubcarrierSpacing = 1;
+ #pdcch-ConfigCommon
+ initialDLBWPcontrolResourceSetZero = 0;
+ initialDLBWPsearchSpaceZero = 0;
+ #pdsch-ConfigCommon
+ #pdschTimeDomainAllocationList (up to 16 entries)
+ initialDLBWPk0_0 = 0;
+ #initialULBWPmappingType
+ #0=typeA,1=typeB
+ initialDLBWPmappingType_0 = 0;
+ #this is SS=1,L=13
+ initialDLBWPstartSymbolAndLength_0 = 40;
+
+ initialDLBWPk0_1 = 0;
+ initialDLBWPmappingType_1 = 0;
+ #this is SS=2,L=12
+ initialDLBWPstartSymbolAndLength_1 = 53;
+
+ initialDLBWPk0_2 = 0;
+ initialDLBWPmappingType_2 = 0;
+ #this is SS=1,L=12
+ initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
+ initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
+ #uplinkConfigCommon
+ #frequencyInfoUL
+ ul_frequencyBand = 78;
+ #scs-SpecificCarrierList
+ ul_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ ul_subcarrierSpacing = 1;
+ ul_carrierBandwidth = 106;
+ pMax = 20;
+ #initialUplinkBWP
+ #genericParameters
+ initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialULBWPsubcarrierSpacing = 1;
+ #rach-ConfigCommon
+ #rach-ConfigGeneric
+ prach_ConfigurationIndex = 98;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+ prach_msg1_FDM = 0;
+ prach_msg1_FrequencyStart = 0;
+ zeroCorrelationZoneConfig = 13;
+ preambleReceivedTargetPower = -118;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+ preambleTransMax = 6;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+ powerRampingStep = 1;
+#ra_ReponseWindow
+#1,2,4,8,10,20,40,80
+ ra_ResponseWindow = 5;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
+#oneHalf (0..15) 4,8,12,16,...60,64
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+ ra_ContentionResolutionTimer = 7;
+ rsrp_ThresholdSSB = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
+ prach_RootSequenceIndex = 1;
+ # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+ #
+ msg1_SubcarrierSpacing = 1,
+
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+ restrictedSetConfig = 0,
+ # pusch-ConfigCommon (up to 16 elements)
+ initialULBWPk2_0 = 2;
+ initialULBWPmappingType_0 = 1
+ # this is SS=0 L=11
+ initialULBWPstartSymbolAndLength_0 = 55;
+
+ initialULBWPk2_1 = 2;
+ initialULBWPmappingType_1 = 1;
+ # this is SS=0 L=12
+ initialULBWPstartSymbolAndLength_1 = 69;
+
+ initialULBWPk2_2 = 7;
+ initialULBWPmappingType_2 = 1;
+ # this is SS=10 L=4
+ initialULBWPstartSymbolAndLength_2 = 52;
+
+ msg3_DeltaPreamble = 1;
+ p0_NominalWithGrant =-90;
+
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+ pucchGroupHopping = 0;
+ hoppingId = 40;
+ p0_nominal = -90;
+# ssb_PositionsInBurs_BitmapPR
+# 1=short, 2=medium, 3=long
+ ssb_PositionsInBurst_PR = 2;
+ ssb_PositionsInBurst_Bitmap = 1; #0x80;
+
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+ ssb_periodicityServingCell = 2;
+
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+ dmrs_TypeA_Position = 0;
+
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ subcarrierSpacing = 1;
+
+
+ #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ referenceSubcarrierSpacing = 1;
+ # pattern1
+ # dl_UL_TransmissionPeriodicity
+ # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+ dl_UL_TransmissionPeriodicity = 6;
+ nrofDownlinkSlots = 7; //8; //7;
+ nrofDownlinkSymbols = 6; //0; //6;
+ nrofUplinkSlots = 2;
+ nrofUplinkSymbols = 4; //0; //4;
+
+ ssPBCH_BlockPower = 10;
+ }
+
+ );
+
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "192.168.18.99";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+ target_enb_x2_ip_address = (
+ { ipv4 = "192.168.18.199";
+ ipv6 = "192:168:30::17";
+ preference = "ipv4";
+ }
+ );
+
+ NETWORK_INTERFACES :
+ {
+
+ GNB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24";
+ GNB_INTERFACE_NAME_FOR_S1U = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24";
+ GNB_PORT_FOR_S1U = 2152; # Spec 2152
+ GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24";
+ GNB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 114;
+ eNB_instances = [0];
+ clock_src = "internal";
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
+ //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
+ parallel_config = "PARALLEL_SINGLE_THREAD";
+ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
+ worker_config = "WORKER_ENABLE";
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="medium";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="medium";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="medium";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_enb.log b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log
new file mode 100755
index 0000000000000000000000000000000000000000..9b9de24a86e8e29de56ba06007d1cdfc0c833843
--- /dev/null
+++ b/doc/testing_gnb_w_cots_ue_resources/oai_enb.log
@@ -0,0 +1,1912 @@
+[CONFIG] get parameters from libconfig ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf , debug flags: 0x00000000
+[CONFIG] function config_libconfig_init returned 0
+[CONFIG] config module libconfig loaded
+[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value)
+# /dev/cpu_dma_latency set to 0us
+[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value)
+[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value)
+[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value)
+[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value)
+log init done
+Reading in command-line options
+[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value)
+[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value)
+Getting ENBSParams
+[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value)
+[0m[1;31m[ENB_APP] Impossible value: PARALLEL_RU_L1_TRX_SPLITaaaaaa
+[0m[CONFIG] parallel_conf is set to 0
+[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value)
+[0m[1;31m[ENB_APP] Impossible value: ENABLE
+[0m[CONFIG] worker_conf is set to 0
+Configuration: nb_rrc_inst 1, nb_L1_inst 1, nb_ru 1
+[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value)
+[LIBCONFIG] loader.NB_IoT: 2/2 parameters successfully set, (1 to default value)
+ nb_nbiot_rrc_inst 0, nb_nbiot_L1_inst 0, nb_nbiot_macrlc_inst 0
+[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value)
+configuring for RAU/RRU
+CPU Freq is 2.992899
+ITTI init, useMME: 1
+[0m[TMR] Starting itti queue: TASK_UNKNOWN as task 0
+[0m[0m[TMR] Starting itti queue: TASK_TIMER as task 1
+[0m[0m[TMR] Starting itti queue: TASK_L2L1 as task 2
+[0m[0m[TMR] Starting itti queue: TASK_BM as task 3
+[0m[0m[TMR] Starting itti queue: TASK_PHY_ENB as task 4
+[0m[0m[TMR] Starting itti queue: TASK_MAC_ENB as task 5
+[0m[0m[TMR] Starting itti queue: TASK_RLC_ENB as task 6
+[0m[0m[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7
+[0m[0m[TMR] Starting itti queue: TASK_PDCP_ENB as task 8
+[0m[0m[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9
+[0m[0m[TMR] Starting itti queue: TASK_END_MARKER as task 10
+[0m[0m[TMR] Starting itti queue: TASK_RRC_ENB as task 11
+[0m[0m[TMR] Starting itti queue: TASK_RRC_GNB as task 12
+[0m[0m[TMR] Starting itti queue: TASK_RAL_ENB as task 13
+[0m[0m[TMR] Starting itti queue: TASK_S1AP as task 14
+[0m[0m[TMR] Starting itti queue: TASK_X2AP as task 15
+[0m[0m[TMR] Starting itti queue: TASK_M2AP_ENB as task 16
+[0m[0m[TMR] Starting itti queue: TASK_M2AP_MCE as task 17
+[0m[0m[TMR] Starting itti queue: TASK_M3AP as task 18
+[0m[0m[TMR] Starting itti queue: TASK_M3AP_MME as task 19
+[0m[0m[TMR] Starting itti queue: TASK_M3AP_MCE as task 20
+[0m[0m[TMR] Starting itti queue: TASK_SCTP as task 21
+[0m[0m[TMR] Starting itti queue: TASK_ENB_APP as task 22
+[0m[0m[TMR] Starting itti queue: TASK_GNB_APP as task 23
+[0m[0m[TMR] Starting itti queue: TASK_MCE_APP as task 24
+[0m[0m[TMR] Starting itti queue: TASK_MME_APP as task 25
+[0m[0m[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26
+[0m[0m[TMR] Starting itti queue: TASK_PHY_UE as task 27
+[0m[0m[TMR] Starting itti queue: TASK_MAC_UE as task 28
+[0m[0m[TMR] Starting itti queue: TASK_RLC_UE as task 29
+[0m[0m[TMR] Starting itti queue: TASK_PDCP_UE as task 30
+[0m[0m[TMR] Starting itti queue: TASK_RRC_UE as task 31
+[0m[0m[TMR] Starting itti queue: TASK_NAS_UE as task 32
+[0m[0m[TMR] Starting itti queue: TASK_RAL_UE as task 33
+[0m[0m[TMR] Starting itti queue: TASK_MSC as task 34
+[0m[0m[TMR] Starting itti queue: TASK_GTPV1_U as task 35
+[0m[0m[TMR] Starting itti queue: TASK_UDP as task 36
+[0m[0m[TMR] Starting itti queue: TASK_CU_F1 as task 37
+[0m[0m[TMR] Starting itti queue: TASK_DU_F1 as task 38
+[0m[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value)
+[0m[OPT] OPT disabled
+[0mreported resolution = 1 ns
+[0m[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200
+[0mRuntime table
+[0m[PHY] RC.eNB = 0x2b10b70
+[0m[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value)
+[0m[PHY] RC.eNB[0] = 0x2b10c20
+[0m[0m[PHY] RC.eNB[0][0] = 0x7f9fab347010
+[0m[0m[ENB_APP] Initializing northbound interface for L1
+[0m[0m[PHY] l1_north_init_eNB() RC.nb_L1_inst:1
+[0m[0m[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1
+[0m[0m[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks
+[0m[0m[PHY] read_config_and_init() RC.nb_L1_inst: 1
+[0m[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value)
+[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (15 to default value)
+[0m[MAC] [MAIN] Init function start:nb_macrlc_inst=1
+[0m[0m[PDCP] PDCP layer has been initialized
+[0mConfiguring local RRC for MACRLC
+[0m[ENB_APP] sched mode = default 0 [default]
+[0m[0m[MAC] read_config_and_init() RC.nb_macrlc_inst: 1
+[0m[0m[PHY] l1_north_init_eNB() RC.nb_L1_inst:1
+[0m[0m[PHY] l1_north_init_eNB() RC.nb_L1_CC[0]:1
+[0m[0m[PHY] l1_north_init_eNB() RC.eNB[0][0] installing callbacks
+[0m[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value)
+[0m[RRC] Instance 0: Southbound Transport local_mac
+[0m[0m[RRC] Setting node_type to ngran_eNB
+[0m[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value)
+[0m[RRC] num component carriers 1
+[0m[0m[RRC] enb_config::RCconfig_RRC() parameter number: 0, total number of parameters: 78, ccspath: eNBs.[0].component_carriers.[0]
+
+[0m[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value)
+phich.resource 0 (ONESIXTH), phich.duration 0 (NORMAL)
+No eMBMS configuration, skipping it
+[LIBCONFIG] eNBs.[0].component_carriers.[0].emtc_parameters: 88/88 parameters successfully set, (88 to default value)
+No eMTC configuration, skipping it
+[LIBCONFIG] eNBs.[0].component_carriers.[0].SLparameters: 39/39 parameters successfully set, (39 to default value)
+No SL configuration skipping it
+[LIBCONFIG] eNBs.[0].srb1_parameters: 6/6 parameters successfully set, (0 to default value)
+[0m[RRC] Node type 0
+ [0m[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] NETWORK_CONTROLLER: 6/6 parameters successfully set, (6 to default value)
+[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (18 to default value)
+Creating RC.ru[0]:0x2b41780
+Setting function for RU 0 to eNodeB_3GPP
+[0m[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 4
+[0m[0m[FLEXRAN_AGENT] FlexRAN Agent for eNB 0 is DISABLED
+[0m[0m[PDCP] PDCP layer has been initialized
+[0m[0m[PDCP] pdcp init,usegtp
+[0m[0m[93m[PDCP] ENB pdcp will use tun interface for MBMS
+[0m[NETLINK]Opened socket oaitun_enm1 with fd 84
+returnValue 0
+returnValue 0
+returnValue 0
+[0m[OIP] Interface oaitun_enm1 successfully configured, ip address 10.0.2.1, mask 255.255.255.0 broadcast address 10.0.2.255
+[0m[0m[ENB_APP] Creating ENB_APP eNB Task
+[0m[0m[TMR] Created Posix thread TASK_ENB_APP
+[0m[0m[RRC] Creating RRC eNB Task
+[0m[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[0m[TMR] Created Posix thread TASK_RRC_ENB
+[0m[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value)
+[0m[TMR] Created Posix thread TASK_SCTP
+[0m[0m[RRC] Entering main loop of RRC message task
+[0m[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value)
+[0m[TMR] Created Posix thread TASK_S1AP
+[0m[0m[TMR] Created Posix thread TASK_UDP
+[0m[0m[SCTP] Starting SCTP layer
+[0m[0m[S1AP] Starting S1AP layer
+[0m[0m[UDP] Initializing UDP task interface
+[0m[0m[UDP] Initializing UDP task interface: DONE
+[0m[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value)
+[LIBCONFIG] eNBs.[0].mme_ip_address.[0]: 5/5 parameters successfully set, (0 to default value)
+[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value)
+[0m[TMR] Created Posix thread TASK_GTPV1_U
+[0m[0m[GTPV1U] Configuring GTPu
+[0m[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (0 to default value)
+[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (1 to default value)
+[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value)
+[0m[GTPV1U] Configuring GTPu address : 192.168.18.199 -> c712a8c0
+[0m[0m[ENB_APP] default drx 2
+[0m[0m[ENB_APP] [eNB 0] eNB_app_register via S1AP for instance 0
+[0m[LIBCONFIG] (root): 3/3 parameters successfully set, (1 to default value)
+[0m[GTPV1U] Initializing GTPU stack 0x16968b0
+[0m[LIBCONFIG] eNBs.[0]: 20/20 parameters successfully set, (11 to default value)
+[LIBCONFIG] eNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value)
+[0m[S1AP] Registered new eNB[0] and macro eNB id 3585
+[0m[0m[S1AP] [eNB 0] check the mme registration state
+[0m[0m[GTPV1U] Tx UDP_INIT IP addr 192.168.18.199 (868)
+[0m[0m[UDP] Initializing UDP for local address 192.168.18.199 with port 2152
+[0m[0m[TMR] Created Posix thread TASK_X2AP
+[0m[0m[MAC] Creating MAC eNB Task
+[0m[LIBCONFIG] eNBs.[0].component_carriers.[0]: 78/78 parameters successfully set, (17 to default value)
+[LIBCONFIG] list eNBs.[0].target_enb_x2_ip_address not found in config file ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.minimassive.master.conf
+[LIBCONFIG] eNBs.[0]: 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] eNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value)
+[0m[UDP] Inserting new descriptor for task 35, sd 85
+[0m[LIBCONFIG] eNBs.[0].NETWORK_INTERFACES: 11/11 parameters successfully set, (2 to default value)
+[0m[UDP] Initializing UDP for local address 192.168.18.199 with port 2152: DONE
+[0m[0m[MAC] Starting main loop of MAC message task
+[0m[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value)
+[0m[SCTP] sctp_bindx SCTP_BINDX_ADD_ADDR socket bound to : 192.168.18.199
+[0m[0m[X2AP] Registered new eNB[0] and macro eNB id 3585
+[0m[0m[X2AP] eNB[0] eNB id 3585 acting as a listner (server)
+[0m[0m[TMR] Created Posix thread TASK_MAC_ENB
+[0m[0m[SCTP] Converted ipv4 address 192.168.18.99 to network type
+[0m[0m[RRC] [eNB 0] Received RRC_CONFIGURATION_REQ : 0x2b4a80c
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init...
+[0m[0m[SCTP] connectx assoc_id 903 in progress..., used 1 addresses
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release
+[0m[0m[SCTP] Inserted new descriptor for sd 86 in list, nb elements 1, assoc_id 903
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Rel14 RRC detected, MBMS flag 0
+[0m[0m[SCTP] Received SCTP_INIT_MSG_MULTI_REQ
+[0m[0m[RRC] [eNB 0] Node type 0
+ [0m[0m[SCTP] Creating new listen socket on port 36422 with
+[0m[0m[SCTP] ipv4 addresses:
+[0m[0m[SCTP] - 192.168.18.199
+[0m[0m[RRC] configuration->schedulingInfoSIB1_BR_r13[CC_id] 0
+[0m[0m[RRC] Configuring MIB (N_RB_DL 25,phich_Resource 0,phich_Duration 0)
+[0m[0m[RRC] [MIB] systemBandwidth 2, phich_duration 0, phich_resource 0, sfn 0
+[0m[0m[RRC] [MIB] schedulingInfoSIB1 0
+[0m[0m[RRC] [eNB 0] Configuration SIB2/3, eMBMS = 0
+[0m[0m[RRC] do_SIB23, size 38
+ [0m[0m[MAC] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25,Nid_cell 0,p 1,DL freq 2680000000,phich_config.resource 0, phich_config.duration 0)
+[0m[0m[MAC] config_mib() NFAPI_CONFIG_REQUEST(num_tlv:16) DL_BW:25 UL_BW:25 Ncp 0,p_eNB 1,earfcn 3350,band 7,phich_resource 0 phich_duration 0 phich_power_offset 6000 PSS 6000 SSS 6000 PCI 0 PBCH repetition 0
+[0m[0m[MAC] [CONFIG]SIB2/3 Contents (partial)
+[0m[0m[MAC] [CONFIG]pusch_config_common.n_SB = 1
+[0m[0m[MAC] [CONFIG]pusch_config_common.hoppingMode = 0
+[0m[0m[MAC] [CONFIG]pusch_config_common.pusch_HoppingOffset = 0
+[0m[0m[MAC] [CONFIG]pusch_config_common.enable64QAM = 0
+[0m[0m[MAC] [CONFIG]pusch_config_common.groupHoppingEnabled = 1
+[0m[0m[MAC] [CONFIG]pusch_config_common.groupAssignmentPUSCH = 0
+[0m[0m[MAC] [CONFIG]pusch_config_common.sequenceHoppingEnabled = 0
+[0m[0m[MAC] [CONFIG]pusch_config_common.cyclicShift = 1
+[0m[0m[PHY] Configuring MIB for instance 0, CCid 0 : (band 7,N_RB_DL 25, N_RB_UL 25, Nid_cell 0,eNB_tx_antenna_ports 1,Ncp 0,DL freq 3350,phich_config.resource 0, phich_config.duration 0)
+[0m[0m[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1
+[0m[0m[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32769
+[0m[0m[SCTP] Client association changed: 0
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] Peer addresses:
+[0m[0m[SCTP] - [192.168.18.99]
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] SCTP Status:
+[0m[0m[SCTP] assoc id .....: 903
+[0m[0m[SCTP] state ........: 4
+[0m[0m[SCTP] instrms ......: 2
+[0m[0m[SCTP] outstrms .....: 2
+[0m[0m[SCTP] fragmentation : 1452
+[0m[0m[SCTP] pending data .: 0
+[0m[0m[SCTP] unack data ...: 0
+[0m[0m[SCTP] rwnd .........: 106496
+[0m[0m[SCTP] peer info :
+[0m[0m[SCTP] state ....: 2
+[0m[0m[SCTP] cwnd .....: 4380
+[0m[0m[SCTP] srtt .....: 0
+[0m[0m[SCTP] rto ......: 3000
+[0m[0m[SCTP] mtu ......: 1500
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] Comm up notified for sd 86, assigned assoc_id 903
+[0m[0m[S1AP] 3585 -> 00e010
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>17</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <S1SetupRequest>
+ <protocolIEs>
+ <S1SetupRequestIEs>
+ <id>59</id>
+ <criticality><reject/></criticality>
+ <value>
+ <Global-ENB-ID>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <eNB-ID>
+ <macroENB-ID>
+ 00000000111000000001
+ </macroENB-ID>
+ </eNB-ID>
+ </Global-ENB-ID>
+ </value>
+ </S1SetupRequestIEs>
+ <S1SetupRequestIEs>
+ <id>60</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <ENBname>eNB-Eurecom-LTEBox</ENBname>
+ </value>
+ </S1SetupRequestIEs>
+ <S1SetupRequestIEs>
+ <id>64</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SupportedTAs>
+ <SupportedTAs-Item>
+ <tAC>00 01</tAC>
+ <broadcastPLMNs>
+ <PLMNidentity>22 F2 10</PLMNidentity>
+ </broadcastPLMNs>
+ </SupportedTAs-Item>
+ </SupportedTAs>
+ </value>
+ </S1SetupRequestIEs>
+ <S1SetupRequestIEs>
+ <id>137</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <PagingDRX><v128/></PagingDRX>
+ </value>
+ </S1SetupRequestIEs>
+ </protocolIEs>
+ </S1SetupRequest>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 59 bytes on stream 0 for assoc_id 903
+[0m[LIBCONFIG] loader.coding: 2/2 parameters successfully set, (1 to default value)
+[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 58 received from port 36412, on stream 0, PPID 18
+[0m[0m[S1AP] servedGUMMEIs.list.count 3
+[0m[0m[S1AP] servedPLMNs.list.count 1
+[0m[0m[S1AP] servedPLMNs.list.count 1
+[0m[0m[S1AP] servedPLMNs.list.count 1
+[0m[0m[ENB_APP] [eNB 0] Received S1AP_REGISTER_ENB_CNF: associated MME 1
+[0m[LOADER] library libcoding.so successfully loaded
+[0m[PHY] prach_config_common.rootSequenceIndex = 0
+[0m[0m[PHY] prach_config_common.prach_ConfigInfo.prach_ConfigIndex = 0
+[0m[0m[PHY] prach_config_common.prach_ConfigInfo.highSpeedFlag = 0
+[0m[0m[PHY] prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = 1
+[0m[0m[PHY] prach_config_common.prach_ConfigInfo.prach_FreqOffset = 2
+[0m[0m[PHY] pusch_config_common.n_SB = 1
+[0m[0m[PHY] pusch_config_common.hoppingMode = 0
+[0m[0m[PHY] pusch_config_common.pusch_HoppingOffset = 0
+[0m[0m[PHY] pusch_config_common.enable64QAM = 0
+[0m[0m[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupHoppingEnabled = 1
+[0m[0m[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH = 0
+[0m[0m[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled = 0
+[0m[0m[PHY] pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift = 2
+[0m[0m[PHY] eNB 0/0 configured
+[0m[0m[RRC] [eNB] handover active state is 0
+[0m[0m[RRC] [eNB] eMBMS active state is 0
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] ENB:OPENAIR RRC IN....
+[0m[0m[ENB_APP] START MAIN THREADS
+[0mRC.nb_L1_inst:1
+Initializing eNB threads single_thread_flag:0 wait_for_sync:0
+[0m[PHY] [lte-softmodem.c] eNB structure about to allocated RC.nb_L1_inst:1 RC.nb_L1_CC[0]:1
+[0m[0m[PHY] [lte-softmodem.c] eNB structure RC.eNB allocated
+[0m[0m[PHY] Initializing eNB 0 CC_id 0 single_thread_flag:0
+[0m[0m[PHY] Initializing eNB 0 CC_id 0
+[0m[0m[PHY] Registering with MAC interface module
+[0m[0m[PHY] Setting indication lists
+[0m[0m[PHY] [lte-softmodem.c] eNB structure allocated
+[0mwait_eNBs()
+Waiting for eNB L1 instances to all get configured ... sleeping 50ms (nb_L1_inst 1)
+RC.nb_L1_CC[0]:1
+eNB L1 are configured
+About to Init RU threads RC.nb_RU:1
+Initializing RU threads
+[0m[1;31m[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/targets/RT/USER/lte-ru.c:2739
+[0m[0m[PHY] Copying frame parms from eNB 0 to ru 0
+[0m[0m[PHY] Initializing RRU descriptor 0 : (local RF,synch_to_ext_device,0)
+[0mconfiguring ru_id 0 (start_rf 0x5b1a00)
+[0m[PHY] Starting ru_thread 0, is_slave 0, send_dmrs 0
+[0m[0m[PHY] Initializing RU proc 0 (eNodeB_3GPP,synch_to_ext_device),
+[0m[0m[PHY] init_RU_proc() DJP - added creation of pthread_prach
+[0m[0m[93m[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY.
+[0m[0m[HW] [SCHED][eNB] ru_thread started on CPU 1, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3
+[0m[0m[PHY] thread ru created id=7295
+[0m[0m[PHY] Starting RU 0 (eNodeB_3GPP,synch_to_ext_device),
+[0mwaiting for sync (ru_thread,-1/0xff4968,0x17af520,0x16952a0)
+channel 0, Setting tx_gain offset 0.000000, rx_gain offset 118.000000, tx_freq 2680000000.000000, rx_freq 2560000000.000000
+[0m[93m[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY.
+[0m[0m[PHY] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1
+[0m[0m[PHY] lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512
+[0m[0m[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1
+[0m[0m[HW] [SCHED][eNB] ru_thread_prach started on CPU 2, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3
+[0m[0m[PHY] [INIT] common.txdata[0] = 0x7f9fafc66010 (307200 bytes)
+[0m[0m[PHY] ru_thread_prach() RU configured - RACH processing thread running
+[0m[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value)
+[LOADER] library libdfts.so successfully loaded
+[0m[PHY] nb_tx 1
+[0m[0m[PHY] rxdata_7_5kHz[0] 0x2b9c1c0 for RU 0
+[0m[0m[PHY] [INIT] common.txdata_BF= 0x2b4ae80 (8 bytes)
+[0m[0m[PHY] txdataF_BF[0] 0x2bba1e0 for RU 0
+[0m[0m[PHY] rxdataF[0] 0x2bc1200 for RU 0
+[0m[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value)
+[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value)
+[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value)
+[LOADER] library liboai_device.so successfully loaded
+[0m[HW] UHD version 3.13.0.HEAD-0-g0ddc19e5 (3.13.0)
+[0m[0m[HW] Found USRP b200
+[0mFound USRP b200
+[0m[93m[HW] Clock source set neither in usrp_args nor on command line, using default!
+[0m[0m[93m[HW] Time source set neither in usrp_args nor on command line, using default!
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] Received notification for sd 87, type 32769
+[0m[0m[SCTP] Client association changed: 0
+[0m[0m[SCTP] Comm up notified for sd 87, assigned assoc_id 904
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] SCTP Status:
+[0m[0m[SCTP] assoc id .....: 904
+[0m[0m[SCTP] state ........: 4
+[0m[0m[SCTP] instrms ......: 32
+[0m[0m[SCTP] outstrms .....: 32
+[0m[0m[SCTP] fragmentation : 1452
+[0m[0m[SCTP] pending data .: 0
+[0m[0m[SCTP] unack data ...: 0
+[0m[0m[SCTP] rwnd .........: 106496
+[0m[0m[SCTP] peer info :
+[0m[0m[SCTP] state ....: 2
+[0m[0m[SCTP] cwnd .....: 4380
+[0m[0m[SCTP] srtt .....: 0
+[0m[0m[SCTP] rto ......: 3000
+[0m[0m[SCTP] mtu ......: 1500
+[0m[0m[SCTP] ----------------------
+[0mx2ap_eNB_handle_sctp_association_ind at 1 (called for instance 0)
+here comes the tree (instance 0):
+---------------------------------------------
+---------------------------------------------
+x2ap_eNB_handle_sctp_association_ind at 2
+here comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 2
+nextstream 0
+in_streams 0 out_streams 0
+cnx_id 1 assoc_id 0
+---------------------------------------------
+x2ap_eNB_handle_sctp_association_ind at 3
+here comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 2
+nextstream 0
+in_streams 32 out_streams 32
+cnx_id 1 assoc_id 904
+---------------------------------------------
+[0m[SCTP] Found data for descriptor 95
+[0m[0m[SCTP] [904][95] Msg of length 66 received from port 36422, on stream 0, PPID 27
+[0m<X2AP-PDU>
+ <initiatingMessage>
+ <procedureCode>36</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <ENDCX2SetupRequest>
+ <protocolIEs>
+ <ENDCX2SetupRequest-IEs>
+ <id>244</id>
+ <criticality><reject/></criticality>
+ <value>
+ <InitiatingNodeType-EndcX2Setup>
+ <init-en-gNB>
+ <En-gNB-ENDCX2SetupReqIEs>
+ <id>252</id>
+ <criticality><reject/></criticality>
+ <value>
+ <GlobalGNB-ID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <gNB-ID>
+ <gNB-ID>
+ 00000000000000000000111000000000
+ </gNB-ID>
+ </gNB-ID>
+ </GlobalGNB-ID>
+ </value>
+ </En-gNB-ENDCX2SetupReqIEs>
+ <En-gNB-ENDCX2SetupReqIEs>
+ <id>253</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ServedNRcellsENDCX2ManagementList>
+ <SEQUENCE>
+ <servedNRCellInfo>
+ <nrpCI>0</nrpCI>
+ <nrCellID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <nRcellIdentifier>
+ 000000000000000000000000111000000000
+ </nRcellIdentifier>
+ </nrCellID>
+ <fiveGS-TAC>00 64 90</fiveGS-TAC>
+ <broadcastPLMNs>
+ <PLMN-Identity>22 F2 10</PLMN-Identity>
+ </broadcastPLMNs>
+ <nrModeInfo>
+ <tdd>
+ <nRFreqInfo>
+ <nRARFCN>0</nRARFCN>
+ <freqBandListNr>
+ <FreqBandNrItem>
+ <freqBandIndicatorNr>1</freqBandIndicatorNr>
+ <supportedSULBandList>
+ <SupportedSULFreqBandItem>
+ <freqBandIndicatorNr>80</freqBandIndicatorNr>
+ </SupportedSULFreqBandItem>
+ </supportedSULBandList>
+ </FreqBandNrItem>
+ </freqBandListNr>
+ </nRFreqInfo>
+ <nR-TxBW>
+ <nRSCS><scs15/></nRSCS>
+ <nRNRB><nrb106/></nRNRB>
+ </nR-TxBW>
+ </tdd>
+ </nrModeInfo>
+ <measurementTimingConfiguration>00</measurementTimingConfiguration>
+ </servedNRCellInfo>
+ </SEQUENCE>
+ </ServedNRcellsENDCX2ManagementList>
+ </value>
+ </En-gNB-ENDCX2SetupReqIEs>
+ </init-en-gNB>
+ </InitiatingNodeType-EndcX2Setup>
+ </value>
+ </ENDCX2SetupRequest-IEs>
+ </protocolIEs>
+ </ENDCX2SetupRequest>
+ </value>
+ </initiatingMessage>
+</X2AP-PDU>
+[0m[X2AP] X2AP_ProcedureCode_id_endcX2Setup message!
+[0m[0m[X2AP] TAC: 006490
+[0m[0m[X2AP] PLMN: 22f210
+[0m<X2AP-PDU>
+ <successfulOutcome>
+ <procedureCode>36</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <ENDCX2SetupResponse>
+ <protocolIEs>
+ <ENDCX2SetupResponse-IEs>
+ <id>246</id>
+ <criticality><reject/></criticality>
+ <value>
+ <RespondingNodeType-EndcX2Setup>
+ <respond-eNB>
+ <ENB-ENDCX2SetupReqAckIEs>
+ <id>21</id>
+ <criticality><reject/></criticality>
+ <value>
+ <GlobalENB-ID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <eNB-ID>
+ <macro-eNB-ID>
+ 00000000111000000001
+ </macro-eNB-ID>
+ </eNB-ID>
+ </GlobalENB-ID>
+ </value>
+ </ENB-ENDCX2SetupReqAckIEs>
+ <ENB-ENDCX2SetupReqAckIEs>
+ <id>250</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ServedEUTRAcellsENDCX2ManagementList>
+ <SEQUENCE>
+ <servedEUTRACellInfo>
+ <pCI>0</pCI>
+ <cellId>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <eUTRANcellIdentifier>
+ 0000000011100000000100000000
+ </eUTRANcellIdentifier>
+ </cellId>
+ <tAC>00 01</tAC>
+ <broadcastPLMNs>
+ <PLMN-Identity>22 F2 10</PLMN-Identity>
+ </broadcastPLMNs>
+ <eUTRA-Mode-Info>
+ <fDD>
+ <uL-EARFCN>21350</uL-EARFCN>
+ <dL-EARFCN>3350</dL-EARFCN>
+ <uL-Transmission-Bandwidth><bw25/></uL-Transmission-Bandwidth>
+ <dL-Transmission-Bandwidth><bw25/></dL-Transmission-Bandwidth>
+ </fDD>
+ </eUTRA-Mode-Info>
+ </servedEUTRACellInfo>
+ </SEQUENCE>
+ </ServedEUTRAcellsENDCX2ManagementList>
+ </value>
+ </ENB-ENDCX2SetupReqAckIEs>
+ </respond-eNB>
+ </RespondingNodeType-EndcX2Setup>
+ </value>
+ </ENDCX2SetupResponse-IEs>
+ </protocolIEs>
+ </ENDCX2SetupResponse>
+ </value>
+ </successfulOutcome>
+</X2AP-PDU>
+[0m[SCTP] Successfully sent 53 bytes on stream 0 for assoc_id 904
+[0m[0m[SCTP] Found data for descriptor 95
+[0m[0m[SCTP] Received notification for sd 95, type 32777
+[0m[0m[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 940000000.000000
+[0m[0m[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 100000000.000000
+[0m[0m[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 260000000.000000
+[0m[0m[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 680000000.000000
+[0m[0m[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 1744000000.000000
+[0m[0m[HW] RX Gain 0 118.000000 (55.800000) => 62.200000 (max 76.000000)
+[0m[0m[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00
+[0m[0m[HW] Actual master clock: 30.720000MHz...
+[0m[0m[HW] Actual clock source internal...
+[0m[0m[HW] Actual time source internal...
+[0m[0m[HW] RF board max packet size 1916, size for 100µs jitter 768
+[0m[0m[HW] rx_max_num_samps 768
+[0m[0m[HW] RX Channel 0
+[0m[0m[HW] Actual RX sample rate: 7.680000MSps...
+[0m[0m[HW] Actual RX frequency: 2.560000GHz...
+[0m[0m[HW] Actual RX gain: 62.000000...
+[0m[0m[HW] Actual RX bandwidth: 20.000000M...
+[0m[0m[HW] Actual RX antenna: RX2...
+[0m[0m[HW] TX Channel 0
+[0m[0m[HW] Actual TX sample rate: 7.680000MSps...
+[0m[0m[HW] Actual TX frequency: 2.680000GHz...
+[0m[0m[HW] Actual TX gain: 89.750000...
+[0m[0m[HW] Actual TX bandwidth: 20.000000M...
+[0m[0m[HW] Actual TX antenna: TX/RX...
+[0m[0m[HW] Actual TX packet size: 1916
+[0m[0m[HW] Device timestamp: 1.703971...
+[0m[0m[HW] [RAU] has loaded USRP B200 device.
+[0msetup_RU_buffers: frame_parms = 0x7f9fab347e68
+[0m[PHY] Signaling main thread that RU 0 (is_slave 0,send_dmrs 0) is ready in state RU_RUN
+[0mwait RUs
+[0m[ENB_APP] Waiting for RUs to be configured ... RC.ru_mask:00
+[0m[0m[PHY] RUs configured
+[0m[0m[ENB_APP] RC.nb_RU:1
+[0mALL RUs ready - init eNBs
+[0m[ENB_APP] Not NFAPI mode - call init_eNB_afterRU()
+[0m[0m[PHY] init_eNB_afterRU() RC.nb_inst:1
+[0m[0m[PHY] RC.nb_CC[inst]:1
+[0m[0m[PHY] RC.nb_CC[inst:0][CC_id:0]:0x7f9fab347010
+[0m[0m[PHY] [eNB 0] phy_init_lte_eNB() About to wait for eNB to be configured[0m[0m[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0 nb_antennas_tx:0 nb_antennas_rx:1 nb_antenna_ports_eNB:1 PRACH[rootSequenceIndex:0 prach_Config_enabled:1 configIndex:0 highSpeed:0 zeroCorrelationZoneConfig:1 freqOffset:2]
+[0m[0m[PHY] [eNB 0] Initializing DL_FRAME_PARMS : N_RB_DL 25, PHICH Resource 1, PHICH Duration 0
+[0mpcfich_reg : 0,12,25,37
+[0m[PHY] [INIT] NB_ANTENNA_PORTS_ENB:6 fp->nb_antenna_ports_eNB:1
+[0m[0m[PHY] [INIT] common_vars->txdataF[0] = 0x7f9fafb87010 (286720 bytes)
+[0m[0m[PHY] [INIT] common_vars->txdataF[5] = 0x7f9fa80ff010 (286720 bytes)
+[0m[0m[PHY] Mapping RX ports from 1 RUs to eNB 0
+[0m[0m[PHY] Overwriting eNB->prach_vars.rxsigF[0]:0x330a6c0
+[0m[0m[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil)
+[0m[0m[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil)
+[0m[0m[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil)
+[0m[0m[PHY] Overwriting eNB->prach_vars_br.rxsigF.rxsigF[0]:(nil)
+[0m[0m[PHY] eNB->num_RU:1
+[0m[0m[PHY] Attaching RU 0 antenna 0 to eNB antenna 0
+[0m[0m[PHY] init_eNB_afterRU() ************* DJP ***** eNB->frame_parms.nb_antennas_tx:0 - GOING TO HARD CODE TO 1[0m[0m[PHY] inst 0, CC_id 0 : nb_antennas_rx 1
+[0m[0m[PHY] Initialise transport
+[0m[0m[PHY] init_eNB_proc(inst:0) RC.nb_CC[inst]:1
+[0m[0m[PHY] Initializing eNB processes instance:0 CC_id 0
+[0m[0m[PHY] eNB->single_thread_flag:0
+[0m[0m[93m[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY.
+[0m[0m[HW] [SCHED][eNB] eNB_thread_prach started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3
+[0m[0m[ENB_APP] ALL RUs ready - ALL eNBs ready
+[0m[0m[93m[HW] thread_top_init() called with affinity>0, but overruled by #ifndef CPU_AFFINITY.
+[0m[0m[HW] [SCHED][eNB] eNB_thread_prach_br started on CPU 0, sched_policy = SCHED_FIFO , priority = 99, CPU Affinity= CPU_0 CPU_1 CPU_2 CPU_3
+[0m[0m[ENB_APP] Sending sync to all threads
+[0m[0m[MME_APP] Creating MME_APP eNB Task
+[0mgot sync (ru_thread)
+[0m[TMR] Created Posix thread TASK_MME_APP
+[0m[0m[HW] Time in secs now: 22168192
+[0m[LIBCONFIG] MMEs.[0]: 1/1 parameters successfully set, (1 to default value)
+[0m[MCE_APP] Creating MCE_APP eNB Task
+[0m[0m[HW] Time in secs last pps: 21747824
+[0m[0m[PHY] RU 0 rf device ready
+[0m[0m[TMR] Created Posix thread TASK_MCE_APP
+[0m[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value)
+[LIBCONFIG] MCEs.[0]: 1/1 parameters successfully set, (1 to default value)
+[0m[ENB_APP] TYPE <CTRL-C> TO TERMINATE
+[0m[0m[ENB_APP] [MCE 0] MCE_app_register via M3AP for instance 0
+[0m[0m[1;31m[HW] [recv] received 0 samples out of 7680
+[0m[0m[1;31m[HW] ERROR_CODE_OVERFLOW (Out of sequence error)
+
+[0m[0m[1;31m[PHY] rx_rf: Asked for 7680 samples, got 0 from SDR
+[0m[0m[1;31m[PHY] problem receiving samples[0m[0m[1;31m[MAC] SCHED_MODE = 0
+[0m[0m[PHY] rx_rf: rfdevice timing drift of 22200737 samples (ts_off 0)
+[0m[0m[PHY] prach_I0 = 0.0 dB
+[0m[0m[PHY] max_I0 18, min_I0 0
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Decoding UL CCCH 59.e8.a9.2.18.72 (0x3a52693)
+[0m[0m[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb] Accept new connection from UE random UE identity (0x8721908a9e000000) MME code 0 TMSI 0 cause 1
+[0m[0m[MAC] UE 0 RNTI 43eb adding LC 1 idx 0 to scheduling control (total 1)
+[0m[0m[MAC] UE 0 RNTI 43eb adding LC 2 idx 1 to scheduling control (total 2)
+[0m[0m[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0
+[0m[0m[RRC] [FRAME 00738][eNB][MOD 00][RNTI 43eb]CALLING RLC CONFIG SRB1 (rbid 1)
+[0madd new uid is 0 43eb
+
+[0m[PDCP] [FRAME 00738][eNB][MOD 00][RNTI 43eb][SRB 01] Action ADD LCID 1 (SRB id 1) configured with SN size 5 bits and RLC AM
+[0m[0m[MAC] generate_Msg4 ra->Msg4_frame SFN/SF: 739.2, frameP SFN/SF: 739.2 FOR eNB_Mod: 0
+[0m[0m[MAC] [eNB 0][RAPROC] CC_id 0 Frame 739, subframeP 2: Generating Msg4 with RRC Piggyback (RNTI 43eb)
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 740.6 ULSCH in error in round 0, ul_cqi 132, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 741.4 ULSCH in error in round 1, ul_cqi 138, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 742.2 ULSCH in error in round 2, ul_cqi 134, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 743.0 ULSCH in error in round 3, ul_cqi 132, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 743.8 ULSCH in error in round 0, ul_cqi 140, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 744.6 ULSCH in error in round 1, ul_cqi 140, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 745.4 ULSCH in error in round 2, ul_cqi 142, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 746.2 ULSCH in error in round 3, ul_cqi 143, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 747.0 ULSCH in error in round 0, ul_cqi 143, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 748.8 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] [RAPROC] Logical Channel UL-DCCH, processing LTE_RRCConnectionSetupComplete from UE (SRB1 Active)
+[0m[0m[NAS] AttachRequest.c:40 EMM - attach_request len = 97
+[0m[0m[NAS] UeNetworkCapability.c:46 decode_ue_network_capability len = 7
+[0m[0m[NAS] UeNetworkCapability.c:63 uenetworkcapability decoded UMTS
+
+[0m[0m[NAS] UeNetworkCapability.c:74 uenetworkcapability decoded GPRS
+
+[0m[0m[NAS] UeNetworkCapability.c:82 uenetworkcapability decoded=6
+
+[0m[0m[NAS] UeNetworkCapability.c:86 uenetworkcapability then decoded=8
+
+[0m[0m[NAS] AttachRequest.c:285 EMM: Can't decode the message with iei 111
+
+[0m[0m[S1AP] [eNB 0] Build S1AP_NAS_FIRST_REQ adding in s_TMSI: GUMMEI mme_code 1 mme_group_id 32768 ue 43eb
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_CONNECTED
+[0m[0m[S1AP] [eNB 0] Chose MME 'MME 1' (assoc_id 903) through GUMMEI MCC 222 MNC 1 MMEGI 32768 MMEC 1
+[0m[0m[S1AP] Found usable eNB_ue_s1ap_id: 0x06692d 420141(10)
+[0m[0m[S1AP] GUMMEI_ID_PRESENT
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>12</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <InitialUEMessage>
+ <protocolIEs>
+ <InitialUEMessage-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </InitialUEMessage-IEs>
+ <InitialUEMessage-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>
+ 17 A0 9C 9B 3F 04 07 41 02 0B F6 22 F2 10 80 00
+ 01 00 00 00 37 07 F0 70 C0 40 10 00 10 00 2A 02
+ 1F D0 11 D1 27 23 80 80 21 10 01 00 00 10 81 06
+ 00 00 00 00 83 06 00 00 00 00 00 0D 00 00 0A 00
+ 00 05 00 00 10 00 00 11 00 52 22 F2 10 00 01 5C
+ 0A 00 31 04 E5 E0 34 01 90 11 03 57 58 A6 5D 01
+ 00 E0 C1 6F 04 F0 00 70 00
+ </NAS-PDU>
+ </value>
+ </InitialUEMessage-IEs>
+ <InitialUEMessage-IEs>
+ <id>67</id>
+ <criticality><reject/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </InitialUEMessage-IEs>
+ <InitialUEMessage-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </InitialUEMessage-IEs>
+ <InitialUEMessage-IEs>
+ <id>134</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <RRC-Establishment-Cause><highPriorityAccess/></RRC-Establishment-Cause>
+ </value>
+ </InitialUEMessage-IEs>
+ <InitialUEMessage-IEs>
+ <id>75</id>
+ <criticality><reject/></criticality>
+ <value>
+ <GUMMEI>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <mME-Group-ID>80 00</mME-Group-ID>
+ <mME-Code>01</mME-Code>
+ </GUMMEI>
+ </value>
+ </InitialUEMessage-IEs>
+ </protocolIEs>
+ </InitialUEMessage>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 164 bytes on stream 1 for assoc_id 903
+[0m[0m[93m[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room
+[0m[0m[93m[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room
+[0m[0m[93m[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room
+[0m[0m[93m[RLC] /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/rlc_v2/rlc_entity_am.c:941:generate_status: warning: cannot generate status PDU, not enough room
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 32 received from port 36412, on stream 1, PPID 18
+[0m[0m[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 752.3 ULSCH in error in round 0, ul_cqi 146, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 752.8 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63)
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>
+ 17 A8 76 C5 F5 05 07 56 08 29 22 10 10 00 00 11
+ 04
+ </NAS-PDU>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 65 received from port 36412, on stream 1, PPID 18
+[0m[0m[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[93m[MAC] [eNB 0][PUSCH 4] CC_id 0 761.2 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 10 PUCCH SNR 10
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>
+ 17 9B EE 3B BF 06 07 53 08 ED CA A1 31 56 26 D7
+ E1
+ </NAS-PDU>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 68 bytes on stream 1 for assoc_id 903
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 51 received from port 36412, on stream 1, PPID 18
+[0m[0m[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>47 86 59 47 B7 00 07 5E</NAS-PDU>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 59 bytes on stream 1 for assoc_id 903
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 38 received from port 36412, on stream 1, PPID 18
+[0m[0m[RRC] [eNB 0] Received S1AP_DOWNLINK_NAS: ue_initial_id 1, eNB_ue_s1ap_id 420141
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>
+ 27 F5 4A 60 81 01 02 1F DA 28 09 03 6F 61 69 04
+ 69 70 76 34
+ </NAS-PDU>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 71 bytes on stream 1 for assoc_id 903
+[0m[0m[1;31m[PHY] fill_ulsch UE_id 0 nb_rb = 0
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 235 received from port 36412, on stream 1, PPID 18
+[0m[0m[S1AP] Received NAS message with the E_RAB setup procedure
+[0m[0m[RRC] [eNB 0] Received S1AP_INITIAL_CONTEXT_SETUP_REQ: ue_initial_id 1, eNB_ue_s1ap_id 420141, nb_of_e_rabs 1
+[0m[0m[GTPV1U] Configured GTPu address : c712a8c0
+[0m[0m[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.199 length 4 gtp teid 3396329693
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (3396329693, 3396329693) bearer UE context index 0, msg index 0, id 5, gtp addr len 4
+[0m[0m[RRC] [eNB 0][UE 43eb] Selected security algorithms (0x7f9f9400213c): 0, 2, changed
+[0m[0m[RRC] [eNB 0][UE 43eb] Saved security key 107FB5D1A79727631F15C38738093134AAF72931EA06D9495605EDB00D8D8044
+[0m[0m[RRC] [0m
+KeNB:10 7f b5 d1 a7 97 27 63 1f 15 c3 87 38 09 31 34 aa f7 29 31 ea 06 d9 49 56 05 ed b0 0d 8d 80 44
+[0m[RRC] [0m
+KRRCenc:1b 33 28 35 5a 74 f3 6a 05 c6 cf 34 e9 be 54 63 7b a8 5a 48 1d 72 54 67 ae b0 12 a4 1d 3b 7d 86
+[0m[RRC] [0m
+KRRCint:ba a3 e0 18 79 1e 68 44 c6 60 dd c9 a8 8c 65 c2 e8 74 09 da 28 d6 f2 d9 6f ad da 41 d7 ec 8e 71
+[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate SecurityModeCommand (bytes 3)
+[0m[0m[RRC] calling rrc_data_req :securityModeCommand
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received securityModeComplete on UL-DCCH 1 from UE
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate UECapabilityEnquiry (bytes 3)
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE
+[0m[0m[RRC] got UE capabilities for UE 43eb
+[0m[0m[93m[RRC] drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated
+[0m[0m[RRC] [eNB 0] frame 0: requesting A2, A3, A4, and A5 event reporting
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>22</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UECapabilityInfoIndication>
+ <protocolIEs>
+ <UECapabilityInfoIndicationIEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UECapabilityInfoIndicationIEs>
+ <UECapabilityInfoIndicationIEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UECapabilityInfoIndicationIEs>
+ <UECapabilityInfoIndicationIEs>
+ <id>74</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UERadioCapability>
+ 04 43 DA 01 08 87 7D DB 80 51 81 80 01 04 0C 20
+ 71 63 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF
+ CC 58 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F
+ FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F
+ FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF
+ FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6
+ 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9
+ 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF
+ FF FF 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C
+ 00 8C 85 3C 10 65 3A 54 95 1F C0 77 7E 00 00 00
+ 00 02 04 BD 80 00 00 08 09 DF 00 00 00 02 F5 C0
+ 0C 00 A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08
+ 03 04 01 82 00 C1 08 60 84 30 42 18 21 0A 08 03
+ 04 01 82 00 C1 00 60 84 30 42 18 20 0C 10 06 08
+ 03 04 01 82 00 A1 80 01 04 30 00 20 86 00 04 10
+ C0 00 82 18 00 10 43 00 02 08 40 00 61 00 01 84
+ 00 82 10 00 18 40 08 21 00 01 84 00 82 10 00 18
+ 40 08 21 00 01 84 00 82 10 02 08 60 08 43 0C 01
+ 08 61 80 21 0C 30 04 21 84 00 86 10 02 18 40 08
+ 61 00 21 84 00 86 10 02 18 60 08 43 0C 01 08 61
+ 80 21 0C 30 04 21 84 00 86 10 02 18 40 08 61 00
+ 21 84 00 86 10 02 18 41 08 61 04 21 84 10 86 08
+ 43 04 21 82 10 C1 08 60 04 84 00 86 10 02 18 40
+ 08 61 00 21 84 00 86 10 02 18 21 0C 10 86 10 00
+ 18 40 00 60 80 30 03 00 25 A0 7D 54 6C 1E 00 00
+ 35 81 8C 00 08 20 60 00 02 08 18 20 00 80 06 10
+ 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80 06
+ 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00 80
+ 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20 00
+ 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02 00
+ 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00 02
+ 08 0D A1 00 0F F0 00 40 05 7C 20 63 00 02 08 3B
+ 60 00 80 8C 10 41 5B 08 18 C0 00 82 0E 98 00 20
+ 23 04 10 54 C2 06 30 00 20 83 8C 00 08 28 41 04
+ 14 60 83 84 00 08 20 E3 00 02 0A 00 41 05 18 20
+ E0 00 02 08 2B E1 03 00 00 10 01 DB 00 04 04 00
+ 82 0A D8 40 C0 00 04 10 74 C0 01 01 00 20 82 A6
+ 10 30 00 01 04 1C 20 00 41 40 08 20 A1 04 1C 00
+ 00 41 05 7C 20 61 00 02 08 3B 60 00 80 84 10 41
+ 5B 08 18 40 00 82 0E 98 00 20 21 04 10 54 C2 06
+ 10 00 20 82 BE 10 34 C0 01 00 35 F0 81 A6 00 08
+ 08 C1 05 08 20 06 BE 10 14 C2 06 30 00 20 A1 04
+ 00 D7 C2 02 98 40 46 08 38 40 00 80 1A F8 40 D3
+ 00 04 04 60 82 80 10 03 5F 08 0A 61 03 18 00 10
+ 50 02 00 6B E1 01 4C 20 23 04 1C 00 00 40 09 7C
+ 20 69 80 02 02 30 41 09 7C 20 29 84 0C 60 00 41
+ 09 7C 20 63 00 02 0A 10 48 09 7C 20 63 00 02 02
+ 10 49 09 7C 20 23 04 1C 20 00 48 09 7C 20 23 04
+ 0C 20 00 49 09 7C 20 63 00 02 0A 10 40 09 7C 20
+ 63 00 02 02 10 41 09 7C 20 23 04 1C 20 00 40 09
+ 7C 20 23 04 0C 20 00 41 09 7C 20 63 00 02 0A 00
+ 40 09 7C 20 23 04 1C 00 00 40 0F 6C 00 10 11 82
+ 0A 10 41 40 08 21 AD 84 0C 60 00 41 42 08 28 01
+ 04 35 B0 80 8C 10 70 80 01 05 00 20 86 B6 10 11
+ 82 0A 10 41 C0 00 04 10 B6 C0 01 01 18 20 A1 04
+ 10 96 C2 06 30 00 20 A1 04 10 96 C2 02 30 41 C2
+ 00 04 10 B6 C0 01 01 18 20 A0 04 10 96 C2 06 30
+ 00 20 A0 04 10 96 C2 02 30 41 C0 00 04 10 F4 C0
+ 01 01 18 20 A1 04 14 00 82 1A 98 40 C6 00 04 14
+ 20 82 80 10 43 53 08 08 C1 07 08 00 10 50 02 08
+ 6A 61 01 18 20 A1 04 1C 00 00 41 0B 4C 00 10 11
+ 82 0A 10 41 09 4C 20 63 00 02 0A 10 41 09 4C 20
+ 23 04 1C 20 00 41 0B 4C 00 10 11 82 0A 00 41 09
+ 4C 20 63 00 02 0A 00 41 09 4C 20 23 04 1C 00 00
+ 41 0B 18 00 10 50 82 0A 00 41 09 18 20 E1 00 02
+ 0A 00 41 09 18 20 A1 04 1C 00 00 41 07 18 04 12
+ 50 82 08 28 C1 27 08 00 10 41 C6 00 04 14 20 92
+ 0A 30 41 C2 01 04 90 31 80 41 24 25 F0 81 A6 00
+ 08 08 01 00 25 F0 80 A6 10 30 00 01 00 2D B0 00
+ 40 42 08 28 01 04 25 B0 81 84 00 08 28 01 04 25
+ B0 80 84 10 70 00 01 04 2D 30 00 40 42 08 28 01
+ 04 25 30 81 84 00 08 28 01 04 25 30 80 84 10 70
+ 00 01 04 1C 20 00 41 40 09 20 A1 04 1C 00 00 49
+ 09 7C 20 69 80 02 02 10 41 09 7C 20 29 84 0C 20
+ 00 41 05 7C 20 61 00 02 48 18 40 20 92 07 28 08
+ 24 EB B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F
+ FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF
+ FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF
+ FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC
+ 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2
+ BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF
+ FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF
+ EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF
+ F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63
+ FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95
+ FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF
+ FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF
+ 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF
+ 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F
+ FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF
+ FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF
+ FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB
+ 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC
+ AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF
+ FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F
+ FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF
+ FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8
+ FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5
+ 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF
+ FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF
+ D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF
+ E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7
+ FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B
+ FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F
+ FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F
+ FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF
+ FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6
+ 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9
+ 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF
+ FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF
+ F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF
+ F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1
+ FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA
+ FF F6 3F FF FF E5 7F F6 CE C0 00 0F D8 81 B3 B0
+ 00 00 8F 9D 80 00 1A C0 00 00 08 78 78 BC 5E 1E
+ 1E 1E 1D 0F 0E 43 C3 A1 E1 E1 E1 E1 C0 00 08 78
+ 78 78 71 17 8B C5 E1 E1 E1 E1 E1 E1 E1 E2 F1 78
+ BC 3C 3C 3C 3C 39 17 00 01 F5 80 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 80 82 00 80 20 08 02 00 80 20 08 02 00
+ 80 20 08 02 00 80 20 08 02 00 80 20 08 02 00 80
+ 60 01 80 06 00 18 00 60 01 80 04 00 40 04 00 40
+ 04 00 40 04 00 40 04 00 40 04 00 40 06 00 18 00
+ 60 01 80 04 00 40 04 00 40 04 00 40 06 00 18 00
+ 60 01 80 04 00 40 04 00 40 04 00 40 04 00 40 04
+ 00 20 08 02 00 80 00 40 04 00 40 04 00 40 04 00
+ 40 04 00 20 08 04 00 40 02 00 00 1F 04 01 20 03
+ E6 57 9A 04 01 4B 1F FF FF FF FF FF FE 69 4B BC
+ 50 0F 80 04 20 09 86 00 00 00 00 00 05 50 92 48
+ 81 01 00 02 F2 42 0B 51 40 01 34 00 00 00
+ </UERadioCapability>
+ </value>
+ </UECapabilityInfoIndicationIEs>
+ </protocolIEs>
+ [0m[RRC] RRCConnectionReconfiguration Encoded 1796 bits (225 bytes)
+[0m[0m[RRC] [eNB 0] Frame 0, Logical Channel DL-DCCH, Generate LTE_RRCConnectionReconfiguration (bytes 225, UE id 43eb)
+[0m </UECapabilityInfoIndication>[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m
+ </value>
+ </initiatingMessage>[0m[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action ADD LCID 2 (SRB id 2) configured with SN size 5 bits and RLC AM
+[0m
+</S1AP-PDU>
+[0m[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action ADD LCID 3 (DRB id 1) configured with SN size 12 bits and RLC AM
+[0m[0m[SCTP] Successfully sent 2206 bytes on stream 1 for assoc_id 903
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 2)
+[0m[0m[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][SRB 02] Action MODIFY LCID 2 RB id 2 reconfigured with SN size 5 and RLC AM
+[0m[0m[PDCP] [FRAME 00000][eNB][MOD 00][RNTI 43eb][DRB 01] Action MODIFY LCID 3 RB id 1 reconfigured with SN size 1 and RLC AM
+[0m[0m[RRC] [eNB 0] Frame 0 CC 0 : SRB2 is now active
+[0m[0m[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE rnti 43eb, reconfiguring DRB 1/LCID 3
+[0m[0m[RRC] [eNB 0] Frame 0 : Logical Channel UL-DCCH, Received LTE_RRCConnectionReconfigurationComplete from UE 0, reconfiguring DRB 1/LCID 3
+[0m[0m[MAC] UE 0 RNTI 43eb adding LC 3 idx 2 to scheduling control (total 3)
+[0m[0m[MAC] Added physicalConfigDedicated 0x7f9f600085d0 for 0.0
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate NR UECapabilityEnquiry (bytes 27)
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[S1AP] initial_ctxt_resp_p: e_rab ID 5, enb_addr 192.168.18.199, SIZE 4
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>27 22 5C 78 F3 02 07 43 00 03 52 00 C2</NAS-PDU>
+ </value[0m[SCTP] Successfully sent 43 bytes on stream 1 for assoc_id 903
+[0m>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 64 bytes on stream 1 for assoc_id 903
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] received ueCapabilityInformation on UL-DCCH 1 from UE
+[0m[0m[RRC] got UE capabilities for UE 43eb
+[0m[0m[93m[MAC] [eNB 0][PUSCH 7] CC_id 0 796.7 ULSCH in error in round 0, ul_cqi 152, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[RRC] [eNB 0] frame 0 subframe 0: UE rnti 43eb switching to NSA mode
+[0m[0m[RRC] Read in 2056 bytes for uecap
+[0m<X2AP-PDU>
+ <initiatingMessage>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequest>
+ <protocolIEs>
+ <SgNBAdditionRequest-IEs>
+ <id>111</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>248</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NRUESecurityCapabilities>
+ <nRencryptionAlgorithms>
+ 0000000000000000
+ </nRencryptionAlgorithms>
+ <nRintegrityProtectionAlgorithms>
+ 0000000000000000
+ </nRintegrityProtectionAlgorithms>
+ </NRUESecurityCapabilities>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>203</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBSecurityKey>
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ </SgNBSecurityKey>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>204</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UEAggregateMaximumBitRate>
+ <uEaggregateMaximumBitRateDownlink>100000000</uEaggregateMaximumBitRateDownlink>
+ <uEaggregateMaximumBitRateUplink>100000000</uEaggregateMaximumBitRateUplink>
+ </UEAggregateMaximumBitRate>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>205</id>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABs-ToBeAdded-SgNBAddReqList>
+ <ProtocolIE-Single-Container>
+ <id>209</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-ToBeAdded-SgNBAddReq-Item>
+ <e-RAB-ID>5</e-RAB-ID>
+ <drb-ID>1</drb-ID>
+ <en-DC-ResourceConfiguration>
+ <pDCPatSgNB><present/></pDCPatSgNB>
+ <mCGresources><not-present/></mCGresources>
+ <sCGresources><not-present/></sCGresources>
+ </en-DC-ResourceConfiguration>
+ <resource-configuration>
+ <sgNBPDCPpresent>
+ <full-E-RAB-Level-QoS-Parameters>
+ <qCI>1</qCI>
+ <allocationAndRetentionPriority>
+ <priorityLevel>15</priorityLevel>
+ <pre-emptionCapability><shall-not-trigger-pre-emption/></pre-emptionCapability>
+ <pre-emptionVulnerability><not-pre-emptable/></pre-emptionVulnerability>
+ </allocationAndRetentionPriority>
+ </full-E-RAB-Level-QoS-Parameters>
+ <s1-UL-GTPtunnelEndpoint>
+ <transportLayerAddress>
+ 11000000101010000001001001100011
+ </transportLayerAddress>
+ <gTP-TEID>00 00 00 02</gTP-TEID>
+ </s1-UL-GTPtunnelEndpoint>
+ </sgNBPDCPpresent>
+ </resource-configuration>
+ </E-RABs-ToBeAdded-SgNBAddReq-Item>
+ </value>
+ </ProtocolIE-Single-Container>
+ </E-RABs-ToBeAdded-SgNBAddReqList>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>206</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MeNBtoSgNBContainer>
+ 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63
+ 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58
+ FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5
+ 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF
+ FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF
+ D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF
+ E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7
+ FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B
+ FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C
+ 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02
+ 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00
+ A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04
+ 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43
+ 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18
+ 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C
+ 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61
+ 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86
+ 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08
+ 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61
+ 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86
+ 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61
+ 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86
+ 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00
+ 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06
+ 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80
+ 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00
+ 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20
+ 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02
+ 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00
+ 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08
+ 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40
+ C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01
+ 04 1C 60 00 41 40 08 20 A3 04 1C 00 00 41 07 4C
+ 00 10 10 02 08 2A 61 03 00 00 10 41 C2 00 04 14
+ 00 82 0A 10 41 C0 00 04 10 76 C0 01 01 08 20 82
+ B6 10 30 80 01 04 1D 30 00 40 42 08 20 A9 84 0C
+ 20 00 41 07 1C 00 10 10 82 08 28 E1 03 08 00 10
+ 43 D3 00 04 04 60 82 84 12 50 02 08 6A 61 03 18
+ 00 10 50 82 4A 00 41 0D 4C 20 23 04 1C 20 00 49
+ 40 08 21 A9 84 04 60 82 84 12 70 00 01 04 3D 30
+ 00 40 46 08 28 41 05 00 20 86 A6 10 31 80 01 05
+ 08 20 A0 04 10 D4 C2 02 30 41 C2 00 04 14 00 82
+ 1A 98 40 46 08 28 41 07 00 00 10 42 D3 00 04 04
+ 60 82 84 12 42 53 08 18 C0 00 82 84 12 42 53 08
+ 08 C1 07 08 00 12 42 D3 00 04 04 60 82 84 10 42
+ 53 08 18 C0 00 82 84 10 42 53 08 08 C1 07 08 00
+ 10 42 D3 00 04 04 60 82 80 10 42 53 08 18 C0 00
+ 82 80 10 42 53 08 08 C1 07 00 00 10 41 D3 00 04
+ 04 60 92 0A 98 40 C6 00 04 90 F1 C0 01 01 18 20
+ A1 04 14 00 82 1A 38 40 C6 00 04 14 20 82 80 10
+ 43 47 08 08 C1 07 08 00 10 50 02 08 68 E1 01 18
+ 20 A1 04 1C 00 00 41 0B 1C 00 10 11 82 0A 10 41
+ 09 1C 20 63 00 02 0A 10 41 09 1C 20 23 04 1C 20
+ 00 41 0B 18 00 12 50 82 0A 00 41 09 18 24 E1 00
+ 02 0A 00 41 09 18 24 A1 04 1C 00 00 41 0B 18 00
+ 10 50 82 4A 00 41 09 18 20 E1 00 02 4A 00 41 09
+ 18 20 A1 04 9C 00 00 41 0B 18 00 10 50 82 0A 00
+ 41 09 18 20 E1 00 02 0A 00 41 09 18 20 A1 04 1C
+ 00 00 41 07 18 04 12 50 82 08 28 C1 27 08 00 10
+ 41 C6 00 04 14 20 92 0A 30 41 C2 01 04 90 31 80
+ 41 24 2D 30 00 40 42 09 28 01 04 25 30 81 84 00
+ 09 28 01 04 25 30 80 84 12 70 00 01 04 2D 30 00
+ 40 42 08 28 01 04 25 30 81 84 00 08 28 01 04 25
+ 30 80 84 10 70 00 01 04 1C 20 10 49 40 08 20 A1
+ 04 9C 00 00 41 07 4C 00 10 10 82 48 2A 61 03 08
+ 00 12 40 C2 01 04 9B B6 3F FF FF E5 7F FB 1F FF
+ FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF
+ 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF
+ 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F
+ FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC AF
+ FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF
+ FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F FB
+ 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF FC
+ AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8 FF
+ FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5 7F
+ FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF FF
+ FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF D8
+ FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5
+ 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF
+ FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF
+ D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF
+ E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7
+ FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B
+ FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F
+ FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F
+ FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF
+ FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6
+ 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9
+ 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF
+ FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF
+ F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF
+ F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1
+ FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA
+ FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF
+ FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF
+ B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF
+ CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F
+ FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57
+ FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80
+ 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78
+ 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E
+ 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC
+ 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 04 04 10 04 01 00 40 10
+ 04 01 00 40 10 04 01 00 40 10 04 01 00 40 10 04
+ 03 00 0C 00 30 00 C0 03 00 0C 00 30 00 C0 02 00
+ 20 02 00 20 02 00 20 02 00 20 02 00 10 04 03 00
+ 0C 00 30 00 C0 02 00 20 02 00 20 02 00 20 02 00
+ 20 02 00 20 02 00 20 01 00 40 10 04 00 02 00 20
+ 02 00 20 02 00 20 01 00 40 10 04 00 3E 08 02 40
+ 07 CC AF 34 08 02 96 3F FF FF FF FF FF FC D2 97
+ 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34
+ 91 02 02 00 05 E4 84 12 E2 80 02 6B C0 C0 04 00
+ 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00
+ 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22
+ 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00
+ A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54
+ 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02
+ 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02
+ 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0
+ 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02
+ 00 01 00 80 80 10 02 00
+ </MeNBtoSgNBContainer>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ </protocolIEs>
+ </SgNBAdditionRequest>
+ </value>
+ </initiatingMessage>
+</X2AP-PDU>
+[0m[SCTP] Successfully sent 2161 bytes on stream 0 for assoc_id 904
+[0m[0m[SCTP] Found data for descriptor 95
+[0m[0m[SCTP] Received notification for sd 95, type 32777
+[0m[0m[SCTP] Found data for descriptor 95
+[0m[0m[SCTP] [904][95] Msg of length 371 received from port 36422, on stream 0, PPID 27
+[0m<X2AP-PDU>
+ <successfulOutcome>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequestAcknowledge>
+ <protocolIEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>111</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>207</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNB-UE-X2AP-ID>0</SgNB-UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>210</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-Admitted-ToBeAdded-SgNBAddReqAckList>
+ <ProtocolIE-Single-Container>
+ <id>213</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-Admitted-ToBeAdded-SgNBAddReqAck-Item>
+ <e-RAB-ID>5</e-RAB-ID>
+ <en-DC-ResourceConfiguration>
+ <pDCPatSgNB><present/></pDCPatSgNB>
+ <mCGresources><not-present/></mCGresources>
+ <sCGresources><not-present/></sCGresources>
+ </en-DC-ResourceConfiguration>
+ <resource-configuration>
+ <sgNBPDCPpresent>
+ <s1-DL-GTPtunnelEndpoint>
+ <transportLayerAddress>
+ 11000000101010000001001011000110
+ </transportLayerAddress>
+ <gTP-TEID>92 CC 30 02</gTP-TEID>
+ </s1-DL-GTPtunnelEndpoint>
+ </sgNBPDCPpresent>
+ </resource-configuration>
+ </E-RABs-Admitted-ToBeAdded-SgNBAddReqAck-Item>
+ </value>
+ </ProtocolIE-Single-Container>
+ </E-RABs-Admitted-ToBeAdded-SgNBAddReqAckList>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>211</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBtoMeNBContainer>
+ 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0
+ 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E
+ 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38
+ 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D
+ E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5
+ 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F
+ 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9
+ 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00
+ 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00
+ 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF
+ 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0
+ 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E
+ 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00
+ 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33
+ 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70
+ 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00
+ 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40
+ 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21
+ C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E
+ 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00
+ 60 00
+ </SgNBtoMeNBContainer>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ </protocolIEs>
+ </SgNBAdditionRequestAcknowledge>
+ </value>
+ </successfulOutcome>
+</X2AP-PDU>
+[0m[X2AP] x2ap_eNB_decode_successfuloutcome_message!
+[0m[0m[X2AP] X2AP Association id: 904
+[0m322: 180409a8440992e2078e0190437e30d041e641c8541e2100832ba16e63001a4e47c01349c4000000269618de3500053805100d601b4039d20268000134e4e18de32a31000d6666bee4e024bca15bc2c58f689c2e0050e0180421603b0091191f5e2462001acccd0003f0db00101c02d9009200202404632ce19665140ffff8000000087000410308143073704430000080801a700a201ac0368072ca8040ffff8000000087000410308143070dc210c00008059001012023256152c0e104160e0c10e10071281c0000205ef401000200000f400141001973865995188006b3335f7270125e50ade162c7b44e170028706aa41a808104420c203008c0034043000c018a17b408285ec90791a2b3800040007f4210840080402581c2082c1c1821c200e25038000040bde802000400001e80028200700101880040a04940bc16006000
+<CG-Config>
+ <criticalExtensions>
+ <c1>
+ <cg-Config>
+ <scg-CellGroupConfig>
+ 08 81 32 5C 40 F1 C0 32 08 6F C6 1A 08 3C C8 39
+ 0A 83 C4 20 10 65 74 2D CC 60 03 49 C8 F8 02 69
+ 38 80 00 00 04 D2 C3 1B C6 A0 00 A7 00 A2 01 AC
+ 03 68 07 3A 40 4D 00 00 26 9C 9C 31 BC 65 46 20
+ 01 AC CC D7 DC 9C 04 97 94 2B 78 58 B1 ED 13 85
+ C0 0A 1C 03 00 84 2C 07 60 12 23 23 EB C4 8C 40
+ 03 59 99 A0 00 7E 1B 60 02 03 80 5B 20 12 40 04
+ 04 80 8C 65 9C 32 CC A2 81 FF FF 00 00 00 01 0E
+ 00 08 20 61 02 86 0E 6E 08 86 00 00 10 10 03 4E
+ 01 44 03 58 06 D0 0E 59 50 08 1F FF F0 00 00 00
+ 10 E0 00 82 06 10 28 60 E1 B8 42 18 00 01 00 B2
+ 00 20 24 04 64 AC 2A 58 1C 20 82 C1 C1 82 1C 20
+ 0E 25 03 80 00 04 0B DE 80 20 00 40 00 01 E8 00
+ 28 20 03 2E 70 CB 32 A3 10 00 D6 66 6B EE 4E 02
+ 4B CA 15 BC 2C 58 F6 89 C2 E0 05 0E 0D 54 83 50
+ 10 20 88 41 84 06 01 18 00 68 08 60 01 80 31 42
+ F6 81 05 0B D9 20 F2 34 56 70 00 08 00 0F E8 42
+ 10 80 10 08 04 B0 38 41 05 83 83 04 38 40 1C 4A
+ 07 00 00 08 17 BD 00 40 00 80 00 03 D0 00 50 40
+ 0E 00 20 31 00
+ </scg-CellGroupConfig>
+ <scg-RB-Config>14 09 28 17 82 C0 0C 00</scg-RB-Config>
+ </cg-Config>
+ </c1>
+ </criticalExtensions>
+</CG-Config>
+[0m[RRC] Dumping scg_CellGroupConfig: 309[0m0881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100
+[0m[RRC] Dumping scg_RB_Config: 8[0m1409281782c00c00
+[0m[RRC] Dumping nr_SecondaryCellGroupConfig: 309[0m0881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100
+[0m[RRC] Dumping nr_RadioBearerConfig1: 8[0m1409281782c00c00
+len = 336
+ 22 02 8c 00 23 08 10 00 ac 24 a0 82 1e 32 04 d4 22 04 c9 71 03 c7 00 c8 21 bf 18 68 20 f3 20 e4 2a 0f 10 80 41 95 d0 b7 31 80 0d 27 23 e0 09 a4 e2 00 00 00 13 4b 0c 6f 1a 80 02 9c 02 88 06 b0 0d a0 1c e9 01 34 00 00 9a 72 70 c6 f1 95 18 80 06 b3 33 5f 72 70 12 5e 50 ad e1 62 c7 b4 4e 17 00 28 70 0c 02 10 b0 1d 80 48 8c 8f af 12 31 00 0d 66 66 80 01 f8 6d 80 08 0e 01 6c 80 49 00 10 12 02 31 96 70 cb 32 8a 07 ff fc 00 00 00 04 38 00 20 81 84 0a 18 39 b8 22 18 00 00 40 40 0d 38 05 10 0d 60 1b 40 39 65 40 20 7f ff c0 00 00 00 43 80 02 08 18 40 a1 83 86 e1 08 60 00 04 02 c8 00 80 90 11 92 b0 a9 60 70 82 0b 07 06 08 70 80 38 94 0e 00 00 10 2f 7a 00 80 01 00 00 07 a0 00 a0 80 0c b9 c3 2c ca 8c 40 03 59 99 af b9 38 09 2f 28 56 f0 b1 63 da 27 0b 80 14 38 35 52 0d 40 40 82 21 06 10 18 04 60 01 a0 21 80 06 00 c5 0b da 04 14 2f 64 83 c8 d1 59 c0 00 20 00 3f a1 08 42 00 40 20 12 c0 e1 04 16 0e 0c 10 e1 00 71 28 1c 00 00 20 5e f4 01 00 02 00 00 0f 40 01 41 00 38 00 80 c4 00 00 00 20 50 24 a0 5e 0b 00 30 00
+[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] UE State = RRC_RECONFIGURED (default DRB, xid 1)
+[0m[0m[RRC] E-RAB modification indication: nb nb_of_e_rabs 1 status 4
+[0m[0m[RRC] S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified 1, total e_rabs 1, index 1
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>50</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABModificationIndication>
+ <protocolIEs>
+ <E-RABModificationIndicationIEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </E-RABModificationIndicationIEs>
+ <E-RABModificationIndicationIEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </E-RABModificationIndicationIEs>
+ <E-RABModificationIndicationIEs>
+ <id>199</id>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABToBeModifiedListBearerModInd>
+ <ProtocolIE-SingleContainer>
+ <id>200</id>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABToBeModifiedItemBearerModInd>
+ <e-RAB-ID>5</e-RAB-ID>
+ <transportLayerAddress>
+ 11000000101010000001001011000110
+ </transportLayerAddress>
+ <dL-GTP-TEID>92 CC 30 02</dL-GTP-TEID>
+ </E-RABToBeModifiedItemBearerModInd>
+ </value>
+ </ProtocolIE-SingleContainer>
+ </E-RABToBeModifiedListBearerModInd>
+ </value>
+ </E-RABModificationIndicationIEs>
+ </protocolIEs>
+ </E-RABModificationIndication>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[S1AP] Size of encoded message: 43
+[0m[0m[S1AP] initial context setup response: failed e_rab ID 5
+[0m[0m[SCTP] Successfully sent 43 bytes on stream 1 for assoc_id 903
+[0m[0m[1;31m[SCTP] Sctp_sendmsg failed: Message too long
+[0m[0m[GTPV1U] NW_GTP_END_MARKER
+[0m[0m[93m[PDCP] Handed SDU is of size 0! Ignoring...
+[0m[0m[93m[GTPV1U] PDCP data request failed, cause: [UE:43eb]RB is not configured!
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 34 received from port 36412, on stream 1, PPID 18
+[0m[0m[93m[S1AP] Implementation of S1AP E-RAB Modification confirm handler is pending...
+[0m[0m[93m[MAC] [eNB 0][PUSCH 1] CC_id 0 874.5 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16
+[0m[0m[RRC] UE rnti 43eb failure timer 0/8
+[0m[0m[PHY] prach_I0 = 0.0 dB
+[0m[0m[PHY] max_I0 19, min_I0 12
+[0m[0m[93m[MAC] [eNB 0][PUSCH 4] CC_id 0 73.2 ULSCH in error in round 0, ul_cqi 159, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[93m[MAC] [eNB 0][PUSCH 7] CC_id 0 114.3 ULSCH in error in round 0, ul_cqi 165, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 10
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 218.4 ULSCH in error in round 0, ul_cqi 158, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 6] CC_id 0 226.2 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 13
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 19 PUCCH SNR 15
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 13
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 13 PUCCH SNR 15
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[93m[MAC] [eNB 0][PUSCH 2] CC_id 0 753.0 ULSCH in error in round 0, ul_cqi 164, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 18 PUCCH SNR 15
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[MAC] UE rnti 43eb : in synch, PHR 40 dB DL CQI 15 PUSCH SNR 15 PUCCH SNR 16
+[0m<S1AP-PDU>
+ <initiatingMessage>
+ <procedureCode>13</procedureCode>
+ <criticality><ignore/></criticality>
+ <value>
+ <UplinkNASTransport>
+ <protocolIEs>
+ <UplinkNASTransport-IEs>
+ <id>0</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MME-UE-S1AP-ID>553648130</MME-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>8</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ENB-UE-S1AP-ID>420141</ENB-UE-S1AP-ID>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>26</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NAS-PDU>
+ 27 D6 DB 4F 5E 03 07 45 0B 0B F6 22 F2 10 80 00
+ 01 00 00 00 37
+ </NAS-PDU>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>100</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <EUTRAN-CGI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <cell-ID>
+ 0000000011100000000100000000
+ </cell-ID>
+ </EUTRAN-CGI>
+ </value>
+ </UplinkNASTransport-IEs>
+ <UplinkNASTransport-IEs>
+ <id>67</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <TAI>
+ <pLMNidentity>22 F2 10</pLMNidentity>
+ <tAC>00 01</tAC>
+ </TAI>
+ </value>
+ </UplinkNASTransport-IEs>
+ </protocolIEs>
+ </UplinkNASTransport>
+ </value>
+ </initiatingMessage>
+</S1AP-PDU>
+[0m[SCTP] Successfully sent 72 bytes on stream 1 for assoc_id 903
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] [903][86] Msg of length 25 received from port 36412, on stream 1, PPID 18
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Logical Channel DL-DCCH, Generate RRCConnectionRelease (bytes 3)
+[0m[0m[RRC] sent RRC_DCCH_DATA_REQ to TASK_PDCP_ENB
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 927.5 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 928.3 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 929.1 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 929.9 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 930.7 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 931.5 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 932.3 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 933.1 ULSCH in error in round 3, ul_cqi 128, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 933.9 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 934.7 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 935.5 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 3] CC_id 0 936.3 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 936.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 937.6 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 938.4 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 939.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 940.0 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 940.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 941.6 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 942.4 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 943.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 944.0 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 944.8 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 945.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 946.4 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 947.2 ULSCH in error in round 1, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 948.0 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 948.8 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 949.6 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 950.4 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 951.2 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 952.0 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 952.8 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 953.6 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 954.4 ULSCH in error in round 2, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 955.2 ULSCH in error in round 3, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 956.0 ULSCH in error in round 0, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 956.8 ULSCH in error in round 1, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 957.6 ULSCH in error in round 2, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 958.4 ULSCH in error in round 3, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 959.2 ULSCH in error in round 0, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 960.0 ULSCH in error in round 1, ul_cqi 112, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 960.8 ULSCH in error in round 2, ul_cqi 122, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[93m[MAC] [eNB 0][PUSCH 0] CC_id 0 961.6 ULSCH in error in round 3, ul_cqi 116, UE_id 0, RNTI 43eb (len 63)
+[0m[0m[MAC] UE 0 rnti 43eb: UL Failure timer 1
+[0m[0m[93m[RRC] S1AP removed entry in hashtable s1ap_id2_s1ap_ids for eNB_ue_s1ap_id 420141
+[0m[0m[93m[RRC] S1AP removed entry in hashtable initial_id2_s1ap_ids for ue_initial_id 1
+[0m[0m[93m[S1AP] Removed UE context eNB_ue_s1ap_id 420141
+[0m[0m[SCTP] Successfully sent 24 bytes on stream 1 for assoc_id 903
+[0m[0m[RRC] Removing UE 43eb instance after UE_CONTEXT_RELEASE_Complete (ue_release_timer_rrc timeout)
+[0m[0m[93m[RRC] [eNB 0] Removing UE RNTI 43eb
+[0m[0m[RRC] Put UE 43eb into freeList
+[0m[0m[RRC] clean_eNb_dlsch dlsch[2] UE 43eb
+[0m[0m[MAC] clean eNb uci_vars[0] UE 43eb
+[0m[0m[MAC] clean eNb uci_vars[1] UE 43eb
+[0m[0m[MAC] clean eNb uci_vars[2] UE 43eb
+[0m[0m[MAC] clean eNb uci_vars[3] UE 43eb
+[0m[0m[RRC] remove UE 43eb from ul_config_pdu_list 0/1
+[0m[0m[MAC] Removing UE 0 from Primary CC_id 0 (rnti 43eb)
+[0m[0m[PDCP] remove uid is 0/0 43eb
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 43eb] Removed UE context
+[0m[0m[RRC] [release_UE_in_freeList] remove UE 43eb from freeList
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[SCTP] Found data for descriptor 86
+[0m[0m[SCTP] Received notification for sd 86, type 32777
+[0m[0m[PHY] prach_I0 = 0.0 dB
+[0m[0m[PHY] max_I0 18, min_I0 12
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m[0m[X2AP] X2 has 1 process ongoing
+[0m
\ No newline at end of file
diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg
new file mode 100755
index 0000000000000000000000000000000000000000..fccbd9a8a325b26a69a5be87d22852b0b840aad9
Binary files /dev/null and b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_lab.jpg differ
diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg
new file mode 100755
index 0000000000000000000000000000000000000000..23e3af3c89bdc98aca84f6256ab527d82d9c200d
Binary files /dev/null and b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.jpg differ
diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.vsdx b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.vsdx
new file mode 100755
index 0000000000000000000000000000000000000000..d424e04c7af285445d46de19cc83dec6028990d5
Binary files /dev/null and b/doc/testing_gnb_w_cots_ue_resources/oai_fr1_setup.vsdx differ
diff --git a/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log b/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log
new file mode 100755
index 0000000000000000000000000000000000000000..37b3c105165a1638f2faca61ad17cda578ce3a36
--- /dev/null
+++ b/doc/testing_gnb_w_cots_ue_resources/oai_gnb.log
@@ -0,0 +1,38680 @@
+[CONFIG] get parameters from libconfig ../../../targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.mozart.slave.conf , debug flags: 0x00000000
+[CONFIG] function config_libconfig_init returned 0
+[CONFIG] config module libconfig loaded
+[LIBCONFIG] config: 1/1 parameters successfully set, (1 to default value)
+Send signal 35 to display resource usage...
+[LIBCONFIG] log_config: 3/3 parameters successfully set, (1 to default value)
+[LIBCONFIG] log_config: 52/52 parameters successfully set, (46 to default value)
+[LIBCONFIG] log_config: 52/52 parameters successfully set, (52 to default value)
+[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value)
+[LIBCONFIG] log_config: 15/15 parameters successfully set, (15 to default value)
+log init done
+[0m[HW] # /dev/cpu_dma_latency set to 10 us
+[0m[0m[1;31m[HW] Can't set cpu frequency
+[0mReading in command-line options
+[0m[GNB_APP] Getting GNBSParams
+[0m[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] THREAD_STRUCT.[0]: 2/2 parameters successfully set, (0 to default value)
+[CONFIG] parallel_conf is set to 0
+[CONFIG] worker_conf is set to 1
+Configuration: nb_rrc_inst 1, nb_nr_L1_inst 1, nb_ru 1
+[LIBCONFIG] (root): 23/23 parameters successfully set, (19 to default value)
+[LIBCONFIG] (root): 5/5 parameters successfully set, (4 to default value)
+[LIBCONFIG] TTracer: 4/4 parameters successfully set, (4 to default value)
+configuring for RAU/RRU
+CPU Freq is 3.092986
+[0m[TMR] Starting itti queue: TASK_UNKNOWN as task 0
+[0m[0m[TMR] Starting itti queue: TASK_TIMER as task 1
+[0m[0m[TMR] Starting itti queue: TASK_L2L1 as task 2
+[0m[0m[TMR] Starting itti queue: TASK_BM as task 3
+[0m[0m[TMR] Starting itti queue: TASK_PHY_ENB as task 4
+[0m[0m[TMR] Starting itti queue: TASK_MAC_ENB as task 5
+[0m[0m[TMR] Starting itti queue: TASK_RLC_ENB as task 6
+[0m[0m[TMR] Starting itti queue: TASK_RRC_ENB_NB_IoT as task 7
+[0m[0m[TMR] Starting itti queue: TASK_PDCP_ENB as task 8
+[0m[0m[TMR] Starting itti queue: TASK_DATA_FORWARDING as task 9
+[0m[0m[TMR] Starting itti queue: TASK_END_MARKER as task 10
+[0m[0m[TMR] Starting itti queue: TASK_RRC_ENB as task 11
+[0m[0m[TMR] Starting itti queue: TASK_RRC_GNB as task 12
+[0m[0m[TMR] Starting itti queue: TASK_RAL_ENB as task 13
+[0m[0m[TMR] Starting itti queue: TASK_S1AP as task 14
+[0m[0m[TMR] Starting itti queue: TASK_X2AP as task 15
+[0m[0m[TMR] Starting itti queue: TASK_M2AP_ENB as task 16
+[0m[0m[TMR] Starting itti queue: TASK_M2AP_MCE as task 17
+[0m[0m[TMR] Starting itti queue: TASK_M3AP as task 18
+[0m[0m[TMR] Starting itti queue: TASK_M3AP_MME as task 19
+[0m[0m[TMR] Starting itti queue: TASK_M3AP_MCE as task 20
+[0m[0m[TMR] Starting itti queue: TASK_SCTP as task 21
+[0m[0m[TMR] Starting itti queue: TASK_ENB_APP as task 22
+[0m[0m[TMR] Starting itti queue: TASK_GNB_APP as task 23
+[0m[0m[TMR] Starting itti queue: TASK_MCE_APP as task 24
+[0m[0m[TMR] Starting itti queue: TASK_MME_APP as task 25
+[0m[0m[TMR] Starting itti queue: TASK_FLEXRAN_AGENT as task 26
+[0m[0m[TMR] Starting itti queue: TASK_PHY_UE as task 27
+[0m[0m[TMR] Starting itti queue: TASK_MAC_UE as task 28
+[0m[0m[TMR] Starting itti queue: TASK_RLC_UE as task 29
+[0m[0m[TMR] Starting itti queue: TASK_PDCP_UE as task 30
+[0m[0m[TMR] Starting itti queue: TASK_RRC_UE as task 31
+[0m[0m[TMR] Starting itti queue: TASK_NAS_UE as task 32
+[0m[0m[TMR] Starting itti queue: TASK_RAL_UE as task 33
+[0m[0m[TMR] Starting itti queue: TASK_MSC as task 34
+[0m[0m[TMR] Starting itti queue: TASK_GTPV1_U as task 35
+[0m[0m[TMR] Starting itti queue: TASK_UDP as task 36
+[0m[0m[TMR] Starting itti queue: TASK_CU_F1 as task 37
+[0m[0m[TMR] Starting itti queue: TASK_DU_F1 as task 38
+[0m[LIBCONFIG] opt: 3/3 parameters successfully set, (3 to default value)
+[0m[OPT] OPT disabled
+[0m[NETLINK] Error opening socket -1 (93:Protocol not supported)
+[NETLINK] Opened socket with fd -1
+[NETLINK] Error fcntl (9:Bad file descriptor)
+[0m[HW] Version: Branch: NR_RRC_harq_hacks Abrev. Hash: 94fa9c5 Date: Fri Jun 19 18:16:53 2020 +0200
+[0mWait for the ITTI initialize message
+[0m[TMR] Created Posix thread TASK_L2L1
+[0m[0m[SCTP] Starting SCTP layer
+[0m[0m[TMR] Created Posix thread TASK_SCTP
+[0m[LIBCONFIG] eNBs.[0]: 1/1 parameters successfully set, (1 to default value)
+[LIBCONFIG] gNBs.[0]: 1/1 parameters successfully set, (0 to default value)
+[0m[TMR] Created Posix thread TASK_X2AP
+[0m[0m[UDP] Initializing UDP task interface
+[0m[0m[UDP] Initializing UDP task interface: DONE
+[0m[0m[TMR] Created Posix thread TASK_UDP
+[0m[0m[TMR] Created Posix thread TASK_GTPV1_U
+[0m[0m[GTPV1U] Initializing GTPU stack 0x17ce250
+[0m[0m[PHY] gNB_app_task() Task ready initialize structures
+[0m[0m[TMR] Created Posix thread TASK_GNB_APP
+[0m[0m[NR_RRC] Creating NR RRC gNB Task
+[0m[0m[NR_PHY] RC.gNB = 0x7f518c0008c0
+[0m[LIBCONFIG] L1s.[0]: 24/24 parameters successfully set, (22 to default value)
+[0m[NR_PHY] RC.gNB[0] = 0x7f51a2f08010
+[0m[0m[NR_RRC] Entering main loop of NR_RRC message task
+[0m[0m[TMR] Created Posix thread TASK_RRC_GNB
+[0mInitializing northbound interface for L1
+[0m[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1
+[0m[0m[PHY] Installing callbacks for IF_Module - UL_indication
+[0m[0m[MAC] Allocating shared L1/L2 interface structure for instance 0 @ 0x7f518c001970
+[0m[0m[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks
+[0m[LIBCONFIG] MACRLCs.[0]: 20/20 parameters successfully set, (17 to default value)
+[0m[MAC] [MAIN] Init function start:nb_nr_macrlc_inst=1
+[0mNFAPI MODE:MONOLITHIC
+START MAIN THREADS
+RC.nb_nr_L1_inst:1
+Initializing gNB threads single_thread_flag:1 wait_for_sync:0
+[0m[PHY] gNB L1 structure RC.gNB allocated @ 0x7f518c0008c0
+[0m[0m[PHY] [lte-softmodem.c] gNB structure RC.gNB[0] allocated @ 0x7f51a2f08010
+[0m[0m[PHY] Initializing gNB 0 single_thread_flag:1
+[0m[0m[PHY] Initializing gNB 0
+[0m[0m[PHY] Registering with MAC interface module (before 0x7f518c001970)
+[0m[0m[PHY] Installing callbacks for IF_Module - UL_indication
+[0m[0m[PHY] Registering with MAC interface module (after 0x7f518c001970)
+[0m[0m[PHY] Setting indication lists
+[0m[0m[PHY] [nr-softmodem.c] gNB structure allocated
+[0mwait_gNBs()
+Waiting for gNB L1 instances to all get configured ... sleeping 50ms (nb_nr_sL1_inst 1)
+[0m[PDCP] PDCP layer has been initialized
+[0m[0m[PHY] Installing callbacks for IF_Module - UL_indication
+[0m[0m[PHY] gNB_app_task() RC.nb_nr_L1_inst:1
+[0m[0m[PHY] l1_north_init_gNB() RC.nb_nr_L1_inst:1
+[0m[0m[PHY] Installing callbacks for IF_Module - UL_indication
+[0m[0m[PHY] l1_north_init_gNB() RC.gNB[0] installing callbacks
+[0m[0m[GNB_APP] Allocating gNB_RRC_INST for 1 instances
+[0m[0m[PHY] gNB_app_task() RC.nb_nr_inst:1 RC.nrrrc:0x7f518c002860
+[0m[0m[PHY] gNB_app_task() Creating RRC instance RC.nrrrc[0]:0x7f518c002ad0 (1 of 1)
+[0m[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value)
+[LIBCONFIG] gNBs.[0].servingCellConfigCommon.[0]: 155/155 parameters successfully set, (83 to default value)
+[0m[RRC] Read in ServingCellConfigCommon (PhysCellId 0, ABSFREQSSB 641272, DLBand 78, ABSFREQPOINTA 640000, DLBW 106,RACH_TargetReceivedPower -100
+[0mChecking element 15 : 4294967295
+removing pdsch_TimeDomainAllocationList element 15
+List size now 15
+Checking element 14 : 4294967295
+removing pdsch_TimeDomainAllocationList element 14
+List size now 14
+Checking element 13 : 4294967295
+removing pdsch_TimeDomainAllocationList element 13
+List size now 13
+Checking element 12 : 4294967295
+removing pdsch_TimeDomainAllocationList element 12
+List size now 12
+Checking element 11 : 4294967295
+removing pdsch_TimeDomainAllocationList element 11
+List size now 11
+Checking element 10 : 4294967295
+removing pdsch_TimeDomainAllocationList element 10
+List size now 10
+Checking element 9 : 4294967295
+removing pdsch_TimeDomainAllocationList element 9
+List size now 9
+Checking element 8 : 4294967295
+removing pdsch_TimeDomainAllocationList element 8
+List size now 8
+Checking element 7 : 4294967295
+removing pdsch_TimeDomainAllocationList element 7
+List size now 7
+Checking element 6 : 4294967295
+removing pdsch_TimeDomainAllocationList element 6
+List size now 6
+Checking element 5 : 4294967295
+removing pdsch_TimeDomainAllocationList element 5
+List size now 5
+Checking element 4 : 4294967295
+removing pdsch_TimeDomainAllocationList element 4
+List size now 4
+Checking element 3 : 0
+Checking element 2 : 0
+Checking element 1 : 0
+Checking element 0 : 0
+NRRRC 0: Southbound Transport local_mac
+[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value)
+SSB SCO 31
+pdsch_AntennaPorts 1
+[0m[GNB_APP] Sending configuration message to NR_RRC task
+[0m[0m[X2AP] X2AP enabled
+[0m[0m[X2AP] GNB_ID: 0
+[0m[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value)
+[0m[NR_RRC] Received message NRRRC_CONFIGURATION_REQ
+[0m[0m[NR_RRC] [gNB 0] Received NRRRC_CONFIGURATION_REQ : 0x7f518c00407c
+[0m[0m[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Init...
+[0m[LIBCONFIG] gNBs.[0]: 14/14 parameters successfully set, (8 to default value)
+[LIBCONFIG] gNBs.[0].plmn_list.[0]: 3/3 parameters successfully set, (0 to default value)
+[LIBCONFIG] gNBs.[0].target_enb_x2_ip_address.[0]: 3/3 parameters successfully set, (0 to default value)
+[LIBCONFIG] gNBs.[0]: 2/2 parameters successfully set, (0 to default value)
+[LIBCONFIG] gNBs.[0].SCTP: 2/2 parameters successfully set, (0 to default value)
+[0m[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] Checking release
+[0m[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 7/7 parameters successfully set, (0 to default value)
+[0m[GTPV1U] Configuring GTPu
+[0m[LIBCONFIG] (root): 2/2 parameters successfully set, (0 to default value)
+[0m[NR_RRC] Done init_NR_SI
+[0m[LIBCONFIG] gNBs.[0].NETWORK_INTERFACES: 3/3 parameters successfully set, (0 to default value)
+[0m[MAC] Configuring common parameters from NR ServingCellConfig
+[0m[0m[PHY] config_common() dl_BandwidthP:40
+[0m[0m[GTPV1U] Configuring GTPu address : 192.168.18.198 -> c612a8c0
+[0m[0m[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000))
+[0m[0m[PHY] config_common() dl_BandwidthP:40
+[0m[0m[GNB_APP] [gNB 0] gNB_app_register for instance 0
+[0m[0m[GTPV1U] Tx UDP_INIT IP addr 192.168.18.198 (868)
+[0m[0m[PHY] Computing dl_frequency (pointA 640000 => 3600000000 (dlmin 3300000, nr_bandtable[27].N_OFFs_DL 620000))
+[0m[0m[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000
+[0m[0m[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000
+[0m[0m[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000
+[0m[0m[PHY] Scanning band 5, dl_min 869000, ul_min 824000
+[0m[0m[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000
+[0m[0m[UDP] Initializing UDP for local address 192.168.18.198 with port 2152
+[0m[0m[PHY] Scanning band 8, dl_min 925000, ul_min 880000
+[0m[0m[PHY] Scanning band 12, dl_min 728000, ul_min 698000
+[0m[0m[PHY] Scanning band 20, dl_min 791000, ul_min 832000
+[0m[0m[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000
+[0m[0m[PHY] Scanning band 28, dl_min 758000, ul_min 703000
+[0m[0m[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000
+[0m[0m[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000
+[0m[0m[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000
+[0m[0m[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000
+[0m[0m[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000
+[0m[0m[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000
+[0m[0m[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000
+[0m[0m[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000
+[0m[0m[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000
+[0m[0m[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000
+[0m[0m[PHY] Scanning band 71, dl_min 617000, ul_min 663000
+[0m[0m[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000
+[0m[0m[PHY] Scanning band 75, dl_min 1432000, ul_min 0
+[0m[0m[PHY] Scanning band 76, dl_min 1427000, ul_min 0
+[0m[0m[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000
+[0m[0m[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000
+[0m[0m[PHY] Scanning band 80, dl_min 0, ul_min 1710000
+[0m[0m[PHY] Scanning band 81, dl_min 0, ul_min 860000
+[0m[0m[PHY] Scanning band 82, dl_min 0, ul_min 832000
+[0m[0m[PHY] Scanning band 83, dl_min 0, ul_min 703000
+[0m[0m[PHY] Scanning band 84, dl_min 0, ul_min 1920000
+[0m[0m[PHY] Scanning band 86, dl_min 0, ul_min 1710000
+[0m[0m[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000
+[0m[0m[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000
+[0m[0m[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000
+[0m[0m[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000
+[0m[0m[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000
+[0m[0m[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000
+[0m[0m[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000
+[0m[0m[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000
+[0m[0m[PHY] DL frequency 3600000000: band 78, frame_type 1, UL frequency 3600000000
+[0m found_sequences 16
+[0m[MAC] Set TX/RX antenna number to 1 (num ssb 1: 80000000,0)
+[0m[0m[MAC] Setting TDD configuration period to 6
+[0m[0m[PHY] TDD has been properly configurated
+[0m[0m[1;31m[MAC] rrc_mac_config_req_gNB() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/openair2/LAYER2/NR_MAC_gNB/config.c:345 RC.nrmac[Mod_idP]->if_inst->NR_PHY_config_req:0x60f680
+[0m[0m[PHY] Scanning band 1, dl_min 2110000, ul_min 1920000
+[0m[0m[PHY] Scanning band 2, dl_min 1930000, ul_min 1850000
+[0m[0m[PHY] Scanning band 3, dl_min 1805000, ul_min 1710000
+[0m[0m[PHY] Scanning band 5, dl_min 869000, ul_min 824000
+[0m[0m[PHY] Scanning band 7, dl_min 2620000, ul_min 2500000
+[0m[0m[PHY] Scanning band 8, dl_min 925000, ul_min 880000
+[0m[0m[PHY] Scanning band 12, dl_min 728000, ul_min 698000
+[0m[0m[PHY] Scanning band 20, dl_min 791000, ul_min 832000
+[0m[0m[PHY] Scanning band 25, dl_min 1930000, ul_min 1850000
+[0m[0m[PHY] Scanning band 28, dl_min 758000, ul_min 703000
+[0m[0m[PHY] Scanning band 34, dl_min 2010000, ul_min 2010000
+[0m[0m[PHY] Scanning band 38, dl_min 2570000, ul_min 2570000
+[0m[0m[PHY] Scanning band 39, dl_min 1880000, ul_min 1880000
+[0m[0m[PHY] Scanning band 40, dl_min 2300000, ul_min 2300000
+[0m[0m[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000
+[0m[0m[PHY] Scanning band 41, dl_min 2496000, ul_min 2496000
+[0m[0m[PHY] Scanning band 50, dl_min 1432000, ul_min 1432000
+[0m[0m[PHY] Scanning band 51, dl_min 1427000, ul_min 1427000
+[0m[0m[PHY] Scanning band 66, dl_min 2110000, ul_min 1710000
+[0m[0m[PHY] Scanning band 70, dl_min 1995000, ul_min 1695000
+[0m[0m[PHY] Scanning band 71, dl_min 617000, ul_min 663000
+[0m[0m[PHY] Scanning band 74, dl_min 1475000, ul_min 1427000
+[0m[0m[PHY] Scanning band 75, dl_min 1432000, ul_min 0
+[0m[0m[PHY] Scanning band 76, dl_min 1427000, ul_min 0
+[0m[0m[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 77, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 78, dl_min 3300000, ul_min 3300000
+[0m[0m[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000
+[0m[0m[PHY] Scanning band 79, dl_min 4400000, ul_min 4400000
+[0m[0m[PHY] Scanning band 80, dl_min 0, ul_min 1710000
+[0m[0m[PHY] Scanning band 81, dl_min 0, ul_min 860000
+[0m[0m[PHY] Scanning band 82, dl_min 0, ul_min 832000
+[0m[0m[PHY] Scanning band 83, dl_min 0, ul_min 703000
+[0m[0m[PHY] Scanning band 84, dl_min 0, ul_min 1920000
+[0m[0m[PHY] Scanning band 86, dl_min 0, ul_min 1710000
+[0m[0m[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000
+[0m[0m[PHY] Scanning band 257, dl_min 26500000, ul_min 26500000
+[0m[0m[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000
+[0m[0m[PHY] Scanning band 258, dl_min 24250000, ul_min 24250000
+[0m[0m[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000
+[0m[0m[PHY] Scanning band 260, dl_min 37000000, ul_min 37000000
+[0m[0m[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000
+[0m[0m[PHY] Scanning band 261, dl_min 27500000, ul_min 27500000
+[0m[0m[PHY] DL frequency 3619080000: band 78, frame_type 1, UL frequency 3619080000
+[0m[0m[PHY] Configuring MIB for instance 0, : (Nid_cell 0,DL freq 3619080000, UL freq 3619080000)
+[0m[0m[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0
+[0m[0m[X2AP] Registered new eNB[0] and home eNB id 3584
+[0m[0m[X2AP] eNB[0] eNB id 3584 acting as a listner (server)
+[0m[0m[SCTP] Received SCTP_INIT_MSG_MULTI_REQ
+[0m[0m[UDP] Inserting new descriptor for task 35, sd 85
+[0m[0m[UDP] Initializing UDP for local address 192.168.18.198 with port 2152: DONE
+[0m[0m[PHY] gNB 0 configured
+[0m[0m[NR_RRC] [FRAME 00000][eNB][MOD 00][RNTI 0] gNB:OPENAIR NR RRC IN....
+[0m[0m[SCTP] Creating new listen socket on port 36422 with
+[0m[0m[SCTP] ipv4 addresses:
+[0m[0m[SCTP] - 192.168.18.198
+[0m[0m[X2AP] eNB[0] eNB id 3584 acting as an initiator (client)
+[0m[0m[SCTP] Converted ipv4 address 192.168.18.199 to network type
+[0m[0m[SCTP] sctp_connectx SUCCESS, used 1 addresses assoc_id 136
+[0m[0m[SCTP] Inserted new descriptor for sd 87 in list, nb elements 2, assoc_id 136
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] Received notification for sd 87, type 32769
+[0m[0m[SCTP] Client association changed: 0
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] Peer addresses:
+[0m[0m[SCTP] - [192.168.18.199]
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] SCTP Status:
+[0m[0m[SCTP] assoc id .....: 136
+[0m[0m[SCTP] state ........: 4
+[0m[0m[SCTP] instrms ......: 32
+[0m[0m[SCTP] outstrms .....: 32
+[0m[0m[SCTP] fragmentation : 1452
+[0m[0m[SCTP] pending data .: 0
+[0m[0m[SCTP] unack data ...: 0
+[0m[0m[SCTP] rwnd .........: 106496
+[0m[0m[SCTP] peer info :
+[0m[0m[SCTP] state ....: 2
+[0m[0m[SCTP] cwnd .....: 4380
+[0m[0m[SCTP] srtt .....: 0
+[0m[0m[SCTP] rto ......: 3000
+[0m[0m[SCTP] mtu ......: 1500
+[0m[0m[SCTP] ----------------------
+[0m[0m[SCTP] Comm up notified for sd 87, assigned assoc_id 136
+[0mhere comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 1
+nextstream 0
+in_streams 0 out_streams 0
+cnx_id 1 assoc_id -1
+---------------------------------------------
+here comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 1
+nextstream 0
+in_streams 0 out_streams 0
+cnx_id 1 assoc_id -1
+---------------------------------------------
+here comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 1
+nextstream 0
+in_streams 0 out_streams 0
+cnx_id 1 assoc_id -1
+---------------------------------------------
+here comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 0 (null)
+state 1
+nextstream 0
+in_streams 32 out_streams 32
+cnx_id 1 assoc_id 136
+---------------------------------------------
+[0m[X2AP] 3584 -> 00000e
+[0m[0m[X2AP] TAC: 25744 -> 006490
+[0m<X2AP-PDU>
+ <initiatingMessage>
+ <procedureCode>36</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <ENDCX2SetupRequest>
+ <protocolIEs>
+ <ENDCX2SetupRequest-IEs>
+ <id>244</id>
+ <criticality><reject/></criticality>
+ <value>
+ <InitiatingNodeType-EndcX2Setup>
+ <init-en-gNB>
+ <En-gNB-ENDCX2SetupReqIEs>
+ <id>252</id>
+ <criticality><reject/></criticality>
+ <value>
+ <GlobalGNB-ID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <gNB-ID>
+ <gNB-ID>
+ 00000000000000000000111000000000
+ </gNB-ID>
+ </gNB-ID>
+ </GlobalGNB-ID>
+ </value>
+ </En-gNB-ENDCX2SetupReqIEs>
+ <En-gNB-ENDCX2SetupReqIEs>
+ <id>253</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ServedNRcellsENDCX2ManagementList>
+ <SEQUENCE>
+ <servedNRCellInfo>
+ <nrpCI>0</nrpCI>
+ <nrCellID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <nRcellIdentifier>
+ 000000000000000000000000111000000000
+ </nRcellIdentifier>
+ </nrCellID>
+ <fiveGS-TAC>00 64 90</fiveGS-TAC>
+ <broadcastPLMNs>
+ <PLMN-Identity>22 F2 10</PLMN-Identity>
+ </broadcastPLMNs>
+ <nrModeInfo>
+ <tdd>
+ <nRFreqInfo>
+ <nRARFCN>0</nRARFCN>
+ <freqBandListNr>
+ <FreqBandNrItem>
+ <freqBandIndicatorNr>1</freqBandIndicatorNr>
+ <supportedSULBandList>
+ <SupportedSULFreqBandItem>
+ <freqBandIndicatorNr>80</freqBandIndicatorNr>
+ </SupportedSULFreqBandItem>
+ </supportedSULBandList>
+ </FreqBandNrItem>
+ </freqBandListNr>
+ </nRFreqInfo>
+ <nR-TxBW>
+ <nRSCS><scs15/></nRSCS>
+ <nRNRB><nrb106/></nRNRB>
+ </nR-TxBW>
+ </tdd>
+ </nrModeInfo>
+ <measurementTimingConfiguration>00</measurementTimingConfiguration>
+ </servedNRCellInfo>
+ </SEQUENCE>
+ </ServedNRcellsENDCX2ManagementList>
+ </value>
+ </En-gNB-ENDCX2SetupReqIEs>
+ </init-en-gNB>
+ </InitiatingNodeType-EndcX2Setup>
+ </value>
+ </ENDCX2SetupRequest-IEs>
+ </protocolIEs>
+ </ENDCX2SetupRequest>
+ </value>
+ </initiatingMessage>
+</X2AP-PDU>
+[0m[SCTP] Successfully sent 66 bytes on stream 0 for assoc_id 136
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] Received notification for sd 87, type 32777
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] [136][87] Msg of length 53 received from port 36422, on stream 0, PPID 27
+[0m<X2AP-PDU>
+ <successfulOutcome>
+ <procedureCode>36</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <ENDCX2SetupResponse>
+ <protocolIEs>
+ <ENDCX2SetupResponse-IEs>
+ <id>246</id>
+ <criticality><reject/></criticality>
+ <value>
+ <RespondingNodeType-EndcX2Setup>
+ <respond-eNB>
+ <ENB-ENDCX2SetupReqAckIEs>
+ <id>21</id>
+ <criticality><reject/></criticality>
+ <value>
+ <GlobalENB-ID>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <eNB-ID>
+ <macro-eNB-ID>
+ 00000000111000000001
+ </macro-eNB-ID>
+ </eNB-ID>
+ </GlobalENB-ID>
+ </value>
+ </ENB-ENDCX2SetupReqAckIEs>
+ <ENB-ENDCX2SetupReqAckIEs>
+ <id>250</id>
+ <criticality><reject/></criticality>
+ <value>
+ <ServedEUTRAcellsENDCX2ManagementList>
+ <SEQUENCE>
+ <servedEUTRACellInfo>
+ <pCI>0</pCI>
+ <cellId>
+ <pLMN-Identity>22 F2 10</pLMN-Identity>
+ <eUTRANcellIdentifier>
+ 0000000011100000000100000000
+ </eUTRANcellIdentifier>
+ </cellId>
+ <tAC>00 01</tAC>
+ <broadcastPLMNs>
+ <PLMN-Identity>22 F2 10</PLMN-Identity>
+ </broadcastPLMNs>
+ <eUTRA-Mode-Info>
+ <fDD>
+ <uL-EARFCN>21350</uL-EARFCN>
+ <dL-EARFCN>3350</dL-EARFCN>
+ <uL-Transmission-Bandwidth><bw25/></uL-Transmission-Bandwidth>
+ <dL-Transmission-Bandwidth><bw25/></dL-Transmission-Bandwidth>
+ </fDD>
+ </eUTRA-Mode-Info>
+ </servedEUTRACellInfo>
+ </SEQUENCE>
+ </ServedEUTRAcellsENDCX2ManagementList>
+ </value>
+ </ENB-ENDCX2SetupReqAckIEs>
+ </respond-eNB>
+ </RespondingNodeType-EndcX2Setup>
+ </value>
+ </ENDCX2SetupResponse-IEs>
+ </protocolIEs>
+ </ENDCX2SetupResponse>
+ </value>
+ </successfulOutcome>
+</X2AP-PDU>
+[0m[X2AP] x2ap_eNB_decode_successfuloutcome_message!
+[0mgNB L1 are configured
+About to Init RU threads RC.nb_RU:1
+Initializing RU threads
+configuring RU from file
+[LIBCONFIG] RUs.[0]: 27/27 parameters successfully set, (17 to default value)
+Set RU mask to 1
+Creating RC.ru[0]:0x3ae67d0
+Setting function for RU 0 to gNodeB_3GPP
+[0m[PHY] number of L1 instances 1, number of RU 1, number of CPU cores 10
+[0m[0m[1;31m[PHY] DJP - delete code above this /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-ru.c:2251
+[0m[0m[PHY] Copying frame parms from gNB in RC to gNB 0 in ru 0 and frame_parms in ru
+[0mconfiguring ru_id 0 (start_rf 0x5b7120)
+[0m[PHY] Starting ru_thread 0
+[0m[0m[PHY] Initializing RU proc 0 (,synch_to_ext_device),
+[0m[0m[PHY] Starting RU 0 (,synch_to_ext_device),
+[0m[0m[PHY] Initializing frame parms for mu 1, N_RB 106, Ncp 0
+[0m[0m[PHY] fp->scs=30000
+[0m[0m[PHY] fp->ofdm_symbol_size=1536
+[0m[0m[PHY] fp->nb_prefix_samples0=132
+[0m[0m[PHY] fp->nb_prefix_samples=108
+[0m[0m[PHY] fp->slots_per_subframe=2
+[0m[0m[PHY] fp->samples_per_subframe_wCP=43008
+[0m[0m[PHY] init_RU_proc() DJP - added creation of pthread_prach
+[0m[0m[PHY] fp->samples_per_frame_wCP=430080
+[0m[0m[PHY] fp->samples_per_subframe=46080
+[0m[0m[PHY] fp->samples_per_frame=460800
+[0m[0m[PHY] fp->dl_CarrierFreq=3619080000
+[0m[0m[PHY] fp->ul_CarrierFreq=3619080000
+[0mchannel 0, Setting tx_gain offset 0.000000, rx_gain offset 114.000000, tx_freq 3619080000.000000, rx_freq 3619080000.000000
+[0m[PHY] Initializing RU signal buffers (if_south local RF) nb_tx 1
+[0m[0m[PHY] [INIT] common.txdata[0] = 0x7f5198339040 (1843200 bytes)
+[0m[0m[PHY] nb_tx 1
+[0m[0m[PHY] rxdata_7_5kHz[0] 0x7f51980c1040 for RU 0
+[0m[0m[PHY] init feptx thread 0
+[0m[0m[PHY] [INIT] common.txdata_BF= 0x7f517c000aa0 (8 bytes)
+[0m[0m[PHY] txdataF_BF[0] 0x7f51a2e9c040 for RU 0
+[0m[0m[PHY] init feptx thread 1
+[0mwait RUs
+[0m[PHY] Waiting for RUs to be configured ... RC.ru_mask:01
+[0m[0m[PHY] rxdataF[0] 0x7f51a2e47040 for RU 0
+[0m[0m[1;31m[PHY] [INIT] nr_phy_init_RU() RC.nb_nr_L1_inst:1
+[0m[LIBCONFIG] device.recplay: 7/7 parameters successfully set, (7 to default value)
+[LIBCONFIG] device: 1/1 parameters successfully set, (1 to default value)
+[LIBCONFIG] loader: 2/2 parameters successfully set, (2 to default value)
+[LIBCONFIG] loader.oai_device: 2/2 parameters successfully set, (1 to default value)
+[LOADER] library liboai_device.so successfully loaded
+[0m[HW] UHD version 3.15.0.0-0-gaea0e2de (3.15.0)
+[0m[0m[HW] Found USRP b200
+[0mFound USRP b200
+[0m[PHY] ru_thread_prach() RACH waiting for RU to be configured
+[0m[0m[93m[HW] Time source set neither in usrp_args nor on command line, using default!
+[0m[0m[HW] cal 0: freq 3500000000.000000, offset 44.000000, diff 119080000.000000
+[0m[0m[HW] cal 1: freq 2660000000.000000, offset 49.800000, diff 959080000.000000
+[0m[0m[HW] cal 2: freq 2300000000.000000, offset 51.000000, diff 1319080000.000000
+[0m[0m[HW] cal 3: freq 1880000000.000000, offset 53.000000, diff 1739080000.000000
+[0m[0m[HW] cal 4: freq 816000000.000000, offset 57.000000, diff 2803080000.000000
+[0m[0m[HW] RX Gain 0 114.000000 (44.000000) => 70.000000 (max 76.000000)
+[0m[0m[HW] USRP TX_GAIN:89.75 gain_range:89.75 tx_gain:0.00
+[0m[0m[HW] Actual master clock: 46.080000MHz...
+[0m[0m[HW] Actual clock source internal...
+[0m[0m[HW] Actual time source internal...
+[0m[0m[PHY] ru_thread_prach() RACH waiting for RU to be configured
+[0m[0m[HW] RF board max packet size 1916, size for 100µs jitter 4608
+[0m[0m[HW] rx_max_num_samps 1916
+[0m[0m[HW] RX Channel 0
+[0m[0m[HW] Actual RX sample rate: 46.080000MSps...
+[0m[0m[HW] Actual RX frequency: 3.619080GHz...
+[0m[0m[HW] Actual RX gain: 70.000000...
+[0m[0m[HW] Actual RX bandwidth: 40.000000M...
+[0m[0m[HW] Actual RX antenna: RX2...
+[0m[0m[HW] TX Channel 0
+[0m[0m[HW] Actual TX sample rate: 46.080000MSps...
+[0m[0m[HW] Actual TX frequency: 3.619080GHz...
+[0m[0m[HW] Actual TX gain: 89.750000...
+[0m[0m[HW] Actual TX bandwidth: 40.000000M...
+[0m[0m[HW] Actual TX antenna: TX/RX...
+[0m[0m[HW] Actual TX packet size: 1916
+[0m[0m[HW] Device timestamp: 2.171687...
+[0m[0m[HW] [RAU] has loaded USRP B200 device.
+[0msetup_RU_buffers: frame_parms = 0x7f51a2ec7010
+[0m[PHY] RU 0 Setting N_TA_offset to 600 samples (factor 1.500000, UL Freq 3600000, N_RB 106)
+[0m[0m[PHY] Signaling main thread that RU 0 is ready
+[0mwaiting for sync (ru_thread,-1/0xf53a58,0x18e6f00,0x17ccc40)
+RC.ru_mask:00
+[0m[PHY] RUs configured
+[0mALL RUs READY!
+RC.nb_RU:1
+ALL RUs ready - init gNBs
+Not NFAPI mode - call init_eNB_afterRU()
+[0m[PHY] init_eNB_afterRU() RC.nb_nr_inst:1
+[0m[0m[PHY] RC.nb_nr_CC[inst:0]:0x7f51a2f08010
+[0m[0m[PHY] [gNB 0] phy_init_nr_gNB() About to wait for gNB to be configured
+[0m[LIBCONFIG] loader.dfts: 2/2 parameters successfully set, (1 to default value)
+[LOADER] library libdfts.so successfully loaded
+init_scrambling_luts: s 0 (1) ((1,1),(1,1),(1,1),(1,1))
+init_scrambling_luts: s 1 (-1) ((-1,1),(1,1),(1,1),(1,1))
+init_scrambling_luts: s 2 (1) ((1,-1),(1,1),(1,1),(1,1))
+init_scrambling_luts: s 3 (-1) ((-1,-1),(1,1),(1,1),(1,1))
+init_scrambling_luts: s 4 (1) ((1,1),(-1,1),(1,1),(1,1))
+init_scrambling_luts: s 5 (-1) ((-1,1),(-1,1),(1,1),(1,1))
+init_scrambling_luts: s 6 (1) ((1,-1),(-1,1),(1,1),(1,1))
+init_scrambling_luts: s 7 (-1) ((-1,-1),(-1,1),(1,1),(1,1))
+init_scrambling_luts: s 8 (1) ((1,1),(1,-1),(1,1),(1,1))
+init_scrambling_luts: s 9 (-1) ((-1,1),(1,-1),(1,1),(1,1))
+init_scrambling_luts: s a (1) ((1,-1),(1,-1),(1,1),(1,1))
+init_scrambling_luts: s b (-1) ((-1,-1),(1,-1),(1,1),(1,1))
+init_scrambling_luts: s c (1) ((1,1),(-1,-1),(1,1),(1,1))
+init_scrambling_luts: s d (-1) ((-1,1),(-1,-1),(1,1),(1,1))
+init_scrambling_luts: s e (1) ((1,-1),(-1,-1),(1,1),(1,1))
+init_scrambling_luts: s f (-1) ((-1,-1),(-1,-1),(1,1),(1,1))
+init_scrambling_luts: s 10 (1) ((1,1),(1,1),(-1,1),(1,1))
+init_scrambling_luts: s 11 (-1) ((-1,1),(1,1),(-1,1),(1,1))
+init_scrambling_luts: s 12 (1) ((1,-1),(1,1),(-1,1),(1,1))
+init_scrambling_luts: s 13 (-1) ((-1,-1),(1,1),(-1,1),(1,1))
+init_scrambling_luts: s 14 (1) ((1,1),(-1,1),(-1,1),(1,1))
+init_scrambling_luts: s 15 (-1) ((-1,1),(-1,1),(-1,1),(1,1))
+init_scrambling_luts: s 16 (1) ((1,-1),(-1,1),(-1,1),(1,1))
+init_scrambling_luts: s 17 (-1) ((-1,-1),(-1,1),(-1,1),(1,1))
+init_scrambling_luts: s 18 (1) ((1,1),(1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 19 (-1) ((-1,1),(1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1a (1) ((1,-1),(1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1b (-1) ((-1,-1),(1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1c (1) ((1,1),(-1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1d (-1) ((-1,1),(-1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1e (1) ((1,-1),(-1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 1f (-1) ((-1,-1),(-1,-1),(-1,1),(1,1))
+init_scrambling_luts: s 20 (1) ((1,1),(1,1),(1,-1),(1,1))
+init_scrambling_luts: s 21 (-1) ((-1,1),(1,1),(1,-1),(1,1))
+init_scrambling_luts: s 22 (1) ((1,-1),(1,1),(1,-1),(1,1))
+init_scrambling_luts: s 23 (-1) ((-1,-1),(1,1),(1,-1),(1,1))
+init_scrambling_luts: s 24 (1) ((1,1),(-1,1),(1,-1),(1,1))
+init_scrambling_luts: s 25 (-1) ((-1,1),(-1,1),(1,-1),(1,1))
+init_scrambling_luts: s 26 (1) ((1,-1),(-1,1),(1,-1),(1,1))
+init_scrambling_luts: s 27 (-1) ((-1,-1),(-1,1),(1,-1),(1,1))
+init_scrambling_luts: s 28 (1) ((1,1),(1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 29 (-1) ((-1,1),(1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2a (1) ((1,-1),(1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2b (-1) ((-1,-1),(1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2c (1) ((1,1),(-1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2d (-1) ((-1,1),(-1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2e (1) ((1,-1),(-1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 2f (-1) ((-1,-1),(-1,-1),(1,-1),(1,1))
+init_scrambling_luts: s 30 (1) ((1,1),(1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 31 (-1) ((-1,1),(1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 32 (1) ((1,-1),(1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 33 (-1) ((-1,-1),(1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 34 (1) ((1,1),(-1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 35 (-1) ((-1,1),(-1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 36 (1) ((1,-1),(-1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 37 (-1) ((-1,-1),(-1,1),(-1,-1),(1,1))
+init_scrambling_luts: s 38 (1) ((1,1),(1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 39 (-1) ((-1,1),(1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3a (1) ((1,-1),(1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3b (-1) ((-1,-1),(1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3c (1) ((1,1),(-1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3d (-1) ((-1,1),(-1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3e (1) ((1,-1),(-1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 3f (-1) ((-1,-1),(-1,-1),(-1,-1),(1,1))
+init_scrambling_luts: s 40 (1) ((1,1),(1,1),(1,1),(-1,1))
+init_scrambling_luts: s 41 (-1) ((-1,1),(1,1),(1,1),(-1,1))
+init_scrambling_luts: s 42 (1) ((1,-1),(1,1),(1,1),(-1,1))
+init_scrambling_luts: s 43 (-1) ((-1,-1),(1,1),(1,1),(-1,1))
+init_scrambling_luts: s 44 (1) ((1,1),(-1,1),(1,1),(-1,1))
+init_scrambling_luts: s 45 (-1) ((-1,1),(-1,1),(1,1),(-1,1))
+init_scrambling_luts: s 46 (1) ((1,-1),(-1,1),(1,1),(-1,1))
+init_scrambling_luts: s 47 (-1) ((-1,-1),(-1,1),(1,1),(-1,1))
+init_scrambling_luts: s 48 (1) ((1,1),(1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 49 (-1) ((-1,1),(1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4a (1) ((1,-1),(1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4b (-1) ((-1,-1),(1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4c (1) ((1,1),(-1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4d (-1) ((-1,1),(-1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4e (1) ((1,-1),(-1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 4f (-1) ((-1,-1),(-1,-1),(1,1),(-1,1))
+init_scrambling_luts: s 50 (1) ((1,1),(1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 51 (-1) ((-1,1),(1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 52 (1) ((1,-1),(1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 53 (-1) ((-1,-1),(1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 54 (1) ((1,1),(-1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 55 (-1) ((-1,1),(-1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 56 (1) ((1,-1),(-1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 57 (-1) ((-1,-1),(-1,1),(-1,1),(-1,1))
+init_scrambling_luts: s 58 (1) ((1,1),(1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 59 (-1) ((-1,1),(1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5a (1) ((1,-1),(1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5b (-1) ((-1,-1),(1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5c (1) ((1,1),(-1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5d (-1) ((-1,1),(-1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5e (1) ((1,-1),(-1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 5f (-1) ((-1,-1),(-1,-1),(-1,1),(-1,1))
+init_scrambling_luts: s 60 (1) ((1,1),(1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 61 (-1) ((-1,1),(1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 62 (1) ((1,-1),(1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 63 (-1) ((-1,-1),(1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 64 (1) ((1,1),(-1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 65 (-1) ((-1,1),(-1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 66 (1) ((1,-1),(-1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 67 (-1) ((-1,-1),(-1,1),(1,-1),(-1,1))
+init_scrambling_luts: s 68 (1) ((1,1),(1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 69 (-1) ((-1,1),(1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6a (1) ((1,-1),(1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6b (-1) ((-1,-1),(1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6c (1) ((1,1),(-1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6d (-1) ((-1,1),(-1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6e (1) ((1,-1),(-1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 6f (-1) ((-1,-1),(-1,-1),(1,-1),(-1,1))
+init_scrambling_luts: s 70 (1) ((1,1),(1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 71 (-1) ((-1,1),(1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 72 (1) ((1,-1),(1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 73 (-1) ((-1,-1),(1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 74 (1) ((1,1),(-1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 75 (-1) ((-1,1),(-1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 76 (1) ((1,-1),(-1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 77 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,1))
+init_scrambling_luts: s 78 (1) ((1,1),(1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 79 (-1) ((-1,1),(1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7a (1) ((1,-1),(1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7b (-1) ((-1,-1),(1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7c (1) ((1,1),(-1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7d (-1) ((-1,1),(-1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7e (1) ((1,-1),(-1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 7f (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,1))
+init_scrambling_luts: s 80 (1) ((1,1),(1,1),(1,1),(1,-1))
+init_scrambling_luts: s 81 (-1) ((-1,1),(1,1),(1,1),(1,-1))
+init_scrambling_luts: s 82 (1) ((1,-1),(1,1),(1,1),(1,-1))
+init_scrambling_luts: s 83 (-1) ((-1,-1),(1,1),(1,1),(1,-1))
+init_scrambling_luts: s 84 (1) ((1,1),(-1,1),(1,1),(1,-1))
+init_scrambling_luts: s 85 (-1) ((-1,1),(-1,1),(1,1),(1,-1))
+init_scrambling_luts: s 86 (1) ((1,-1),(-1,1),(1,1),(1,-1))
+init_scrambling_luts: s 87 (-1) ((-1,-1),(-1,1),(1,1),(1,-1))
+init_scrambling_luts: s 88 (1) ((1,1),(1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 89 (-1) ((-1,1),(1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8a (1) ((1,-1),(1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8b (-1) ((-1,-1),(1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8c (1) ((1,1),(-1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8d (-1) ((-1,1),(-1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8e (1) ((1,-1),(-1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 8f (-1) ((-1,-1),(-1,-1),(1,1),(1,-1))
+init_scrambling_luts: s 90 (1) ((1,1),(1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 91 (-1) ((-1,1),(1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 92 (1) ((1,-1),(1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 93 (-1) ((-1,-1),(1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 94 (1) ((1,1),(-1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 95 (-1) ((-1,1),(-1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 96 (1) ((1,-1),(-1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 97 (-1) ((-1,-1),(-1,1),(-1,1),(1,-1))
+init_scrambling_luts: s 98 (1) ((1,1),(1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 99 (-1) ((-1,1),(1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9a (1) ((1,-1),(1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9b (-1) ((-1,-1),(1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9c (1) ((1,1),(-1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9d (-1) ((-1,1),(-1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9e (1) ((1,-1),(-1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s 9f (-1) ((-1,-1),(-1,-1),(-1,1),(1,-1))
+init_scrambling_luts: s a0 (1) ((1,1),(1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a1 (-1) ((-1,1),(1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a2 (1) ((1,-1),(1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a3 (-1) ((-1,-1),(1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a4 (1) ((1,1),(-1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a5 (-1) ((-1,1),(-1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a6 (1) ((1,-1),(-1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a7 (-1) ((-1,-1),(-1,1),(1,-1),(1,-1))
+init_scrambling_luts: s a8 (1) ((1,1),(1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s a9 (-1) ((-1,1),(1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s aa (1) ((1,-1),(1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s ab (-1) ((-1,-1),(1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s ac (1) ((1,1),(-1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s ad (-1) ((-1,1),(-1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s ae (1) ((1,-1),(-1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s af (-1) ((-1,-1),(-1,-1),(1,-1),(1,-1))
+init_scrambling_luts: s b0 (1) ((1,1),(1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b1 (-1) ((-1,1),(1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b2 (1) ((1,-1),(1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b3 (-1) ((-1,-1),(1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b4 (1) ((1,1),(-1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b5 (-1) ((-1,1),(-1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b6 (1) ((1,-1),(-1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b7 (-1) ((-1,-1),(-1,1),(-1,-1),(1,-1))
+init_scrambling_luts: s b8 (1) ((1,1),(1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s b9 (-1) ((-1,1),(1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s ba (1) ((1,-1),(1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s bb (-1) ((-1,-1),(1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s bc (1) ((1,1),(-1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s bd (-1) ((-1,1),(-1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s be (1) ((1,-1),(-1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s bf (-1) ((-1,-1),(-1,-1),(-1,-1),(1,-1))
+init_scrambling_luts: s c0 (1) ((1,1),(1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c1 (-1) ((-1,1),(1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c2 (1) ((1,-1),(1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c3 (-1) ((-1,-1),(1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c4 (1) ((1,1),(-1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c5 (-1) ((-1,1),(-1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c6 (1) ((1,-1),(-1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c7 (-1) ((-1,-1),(-1,1),(1,1),(-1,-1))
+init_scrambling_luts: s c8 (1) ((1,1),(1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s c9 (-1) ((-1,1),(1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s ca (1) ((1,-1),(1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s cb (-1) ((-1,-1),(1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s cc (1) ((1,1),(-1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s cd (-1) ((-1,1),(-1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s ce (1) ((1,-1),(-1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s cf (-1) ((-1,-1),(-1,-1),(1,1),(-1,-1))
+init_scrambling_luts: s d0 (1) ((1,1),(1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d1 (-1) ((-1,1),(1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d2 (1) ((1,-1),(1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d3 (-1) ((-1,-1),(1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d4 (1) ((1,1),(-1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d5 (-1) ((-1,1),(-1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d6 (1) ((1,-1),(-1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d7 (-1) ((-1,-1),(-1,1),(-1,1),(-1,-1))
+init_scrambling_luts: s d8 (1) ((1,1),(1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s d9 (-1) ((-1,1),(1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s da (1) ((1,-1),(1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s db (-1) ((-1,-1),(1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s dc (1) ((1,1),(-1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s dd (-1) ((-1,1),(-1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s de (1) ((1,-1),(-1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s df (-1) ((-1,-1),(-1,-1),(-1,1),(-1,-1))
+init_scrambling_luts: s e0 (1) ((1,1),(1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e1 (-1) ((-1,1),(1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e2 (1) ((1,-1),(1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e3 (-1) ((-1,-1),(1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e4 (1) ((1,1),(-1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e5 (-1) ((-1,1),(-1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e6 (1) ((1,-1),(-1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e7 (-1) ((-1,-1),(-1,1),(1,-1),(-1,-1))
+init_scrambling_luts: s e8 (1) ((1,1),(1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s e9 (-1) ((-1,1),(1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s ea (1) ((1,-1),(1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s eb (-1) ((-1,-1),(1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s ec (1) ((1,1),(-1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s ed (-1) ((-1,1),(-1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s ee (1) ((1,-1),(-1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s ef (-1) ((-1,-1),(-1,-1),(1,-1),(-1,-1))
+init_scrambling_luts: s f0 (1) ((1,1),(1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f1 (-1) ((-1,1),(1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f2 (1) ((1,-1),(1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f3 (-1) ((-1,-1),(1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f4 (1) ((1,1),(-1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f5 (-1) ((-1,1),(-1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f6 (1) ((1,-1),(-1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f7 (-1) ((-1,-1),(-1,1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f8 (1) ((1,1),(1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s f9 (-1) ((-1,1),(1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s fa (1) ((1,-1),(1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s fb (-1) ((-1,-1),(1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s fc (1) ((1,1),(-1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s fd (-1) ((-1,1),(-1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s fe (1) ((1,-1),(-1,-1),(-1,-1),(-1,-1))
+init_scrambling_luts: s ff (-1) ((-1,-1),(-1,-1),(-1,-1),(-1,-1))
+in 0, out 0
+in 1, out ffffffff
+in 2, out 4ba5a933
+in 3, out b45a56cc
+in 4, out 7d910e5a
+in 5, out 826ef1a5
+in 6, out 3634a769
+in 7, out c9cb5896
+[LIBCONFIG] loader.ldpc: 2/2 parameters successfully set, (1 to default value)
+[LOADER] library libldpc.so successfully loaded
+[0m[PHY] Initialise nr transport
+[0m[0m[PHY] Allocating Transport Channel Buffers for PUCCH 0/2
+[0m[0m[PHY] Allocating Transport Channel Buffers for PUCCH 1/2
+[0m[0m[PHY] Allocating Transport Channel Buffers for DLSCH 0/2
+[0m[0m[PHY] Allocating Transport Channel Buffers for DLSCH 1/2
+[0m[0m[PHY] Allocating Transport Channel Buffer for ULSCH, UE 0
+[0m[0m[PHY] Allocating Transport Channel Buffer for ULSCH, UE 1
+[0mBefore ULSCH init : 0x3f4b300
+ULSCH_id 0 : 0x3f4b300
+ULSCH_id 0 (before rx antenna alloc) : 0x3f4b300
+ULSCH_id 0 (before llr alloc) : 0x3f4b300
+ULSCH_id 0 (after llr alloc) : 0x3f4b300
+ULSCH_id 1 : 0x3f4b300
+ULSCH_id 1 (before rx antenna alloc) : 0x3f4b300
+ULSCH_id 1 (before llr alloc) : 0x3f4b300
+ULSCH_id 1 (after llr alloc) : 0x3f4b300
+After ULSCH init : 0x3f4b300
+[0m[PHY] Mapping RX ports from 1 RUs to gNB 0
+[0m[0m[PHY] gNB->num_RU:1
+[0m[0m[PHY] Attaching RU 0 antenna 0 to gNB antenna 0
+[0m[0m[PHY] Initializing gNB processes instance:0 CC_id 0
+[0m[0m[PHY] gNB->single_thread_flag:1
+[0mALL RUs ready - ALL gNBs ready
+Sending sync to all threads
+About to call end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:983
+[CONFIG] calling config module end function...
+got sync (ru_thread)
+[CONFIG] free 398 config value pointers
+Called end_configmodule() from main() /home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/nr-softmodem.c:985
+TYPE <CTRL-C> TO TERMINATE
+Entering ITTI signals handler
+[0m[HW] Time in secs now: 112963128
+[0m[0m[HW] Time in secs last pps: 80717015
+[0m[0m[PHY] RU 0 rf device ready
+[0m[0m[PHY] RU 0 no asynch_south interface
+[0minitializing tx write thread
+end of tx write thread
+[0m[PHY] tx write thread ready
+[0m[0m[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[PHY] ru_thread_prach() RACH waiting for RU to be configured
+[0m[0m[PHY] ru_thread_prach() RU configured - RACH processing thread running
+[0m[0m[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] [136][87] Msg of length 2161 received from port 36422, on stream 0, PPID 27
+[0m<X2AP-PDU>
+ <initiatingMessage>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequest>
+ <protocolIEs>
+ <SgNBAdditionRequest-IEs>
+ <id>111</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>248</id>
+ <criticality><reject/></criticality>
+ <value>
+ <NRUESecurityCapabilities>
+ <nRencryptionAlgorithms>
+ 0000000000000000
+ </nRencryptionAlgorithms>
+ <nRintegrityProtectionAlgorithms>
+ 0000000000000000
+ </nRintegrityProtectionAlgorithms>
+ </NRUESecurityCapabilities>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>203</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBSecurityKey>
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ 0000000000000000000000000000000000000000000000000000000000000000
+ </SgNBSecurityKey>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>204</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UEAggregateMaximumBitRate>
+ <uEaggregateMaximumBitRateDownlink>100000000</uEaggregateMaximumBitRateDownlink>
+ <uEaggregateMaximumBitRateUplink>100000000</uEaggregateMaximumBitRateUplink>
+ </UEAggregateMaximumBitRate>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>205</id>
+ <criticality><reject/></criticality>
+ <value>
+ <E-RABs-ToBeAdded-SgNBAddReqList>
+ <ProtocolIE-Single-Container>
+ <id>209</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-ToBeAdded-SgNBAddReq-Item>
+ <e-RAB-ID>5</e-RAB-ID>
+ <drb-ID>1</drb-ID>
+ <en-DC-ResourceConfiguration>
+ <pDCPatSgNB><present/></pDCPatSgNB>
+ <mCGresources><not-present/></mCGresources>
+ <sCGresources><not-present/></sCGresources>
+ </en-DC-ResourceConfiguration>
+ <resource-configuration>
+ <sgNBPDCPpresent>
+ <full-E-RAB-Level-QoS-Parameters>
+ <qCI>1</qCI>
+ <allocationAndRetentionPriority>
+ <priorityLevel>15</priorityLevel>
+ <pre-emptionCapability><shall-not-trigger-pre-emption/></pre-emptionCapability>
+ <pre-emptionVulnerability><not-pre-emptable/></pre-emptionVulnerability>
+ </allocationAndRetentionPriority>
+ </full-E-RAB-Level-QoS-Parameters>
+ <s1-UL-GTPtunnelEndpoint>
+ <transportLayerAddress>
+ 11000000101010000001001001100011
+ </transportLayerAddress>
+ <gTP-TEID>00 00 00 02</gTP-TEID>
+ </s1-UL-GTPtunnelEndpoint>
+ </sgNBPDCPpresent>
+ </resource-configuration>
+ </E-RABs-ToBeAdded-SgNBAddReq-Item>
+ </value>
+ </ProtocolIE-Single-Container>
+ </E-RABs-ToBeAdded-SgNBAddReqList>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ <SgNBAdditionRequest-IEs>
+ <id>206</id>
+ <criticality><reject/></criticality>
+ <value>
+ <MeNBtoSgNBContainer>
+ 3A 03 08 78 8D DB 80 51 81 80 01 04 0C 20 71 63
+ 08 11 24 4C C1 93 67 0F A1 4A 99 3A 85 AF CC 58
+ FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF E5
+ 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7 FF
+ FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B FF
+ D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF FF
+ E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE C7
+ FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B
+ FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF DF F3 FF AF A2 0C 00 8C
+ 85 3C 10 65 3A 54 97 1F C0 68 FE 00 00 00 00 02
+ 04 BD 80 00 00 08 09 DF 00 00 00 02 EE C0 0C 00
+ A0 04 00 04 00 A0 06 00 48 20 0C 10 06 08 03 04
+ 01 82 10 C1 08 60 84 30 42 18 20 0C 10 06 08 43
+ 04 21 82 00 C1 00 60 80 30 40 18 20 0C 10 06 18
+ 02 10 C3 00 42 18 60 08 43 0C 01 08 61 80 21 0C
+ 30 04 21 86 00 84 30 C0 10 86 10 02 18 40 08 61
+ 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86
+ 10 02 18 20 0C 10 06 18 02 10 C3 00 42 18 60 08
+ 43 0C 01 08 61 00 21 84 00 86 10 02 18 41 08 61
+ 04 21 84 10 86 10 42 18 41 08 61 04 21 84 10 86
+ 10 42 18 41 08 60 84 30 42 18 21 0C 10 86 00 61
+ 00 21 84 00 86 10 02 18 40 08 61 00 21 84 00 86
+ 08 43 04 21 82 00 C1 00 60 04 B4 7D 54 6C 1E 00
+ 00 2E 81 8C 00 08 20 60 00 02 08 18 20 00 80 06
+ 10 00 20 81 86 00 08 00 62 00 02 00 18 E0 00 80
+ 06 58 00 20 01 98 00 08 00 68 00 02 00 1A 20 00
+ 80 06 90 00 20 01 A6 00 08 00 6C 00 02 00 1B 20
+ 00 80 06 D8 00 20 00 B8 10 00 5F 08 00 70 80 02
+ 00 1C A0 00 82 07 30 00 20 01 CE 00 08 20 74 00
+ 02 08 0D A1 00 0F F0 00 40 07 4C 00 10 11 82 08
+ 2A 61 03 18 00 10 41 C7 00 04 04 60 82 0A 38 40
+ C6 00 04 10 71 80 01 05 08 20 82 8C 10 70 80 01
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+ FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF 2B
+ FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F FF
+ FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F FE
+ C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF FF
+ 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6 3F
+ FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9 5F
+ FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF FF
+ FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF F6
+ 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF F9
+ 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF
+ FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA FF
+ F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF FF
+ F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1
+ FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF CA
+ FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF
+ FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF
+ B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF
+ CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F
+ FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57
+ FF B1 FF FF FF 2B FF B6 76 00 00 7E C4 0D 9D 80
+ 00 04 7C EC 00 00 BA 00 00 00 8B C5 E2 F1 78 78
+ 78 78 72 1E 1E 1E 1E 1E 1E 3F 8F C2 1E 1E 1E 1E
+ 1E 1E 1E 1E 1E 1E 2F 17 8B 90 F0 F0 F0 F1 78 BC
+ 5E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1C 8B 80 0F 74
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+ 78 A0 1F 00 08 40 13 0C 00 00 00 00 00 0A A1 34
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+ 01 04 10 40 00 28 C8 00 00 08 80 00 05 58 E1 00
+ 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06 0E 22
+ 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31 10 00
+ A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0 42 54
+ 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20 1A 02
+ 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80 00 02
+ 0C 30 00 1A 55 30 62 00 11 C0 48 16 0C 01 C4 D0
+ 00 00 00 40 04 03 40 4D 01 04 40 41 4E 9C 00 02
+ 00 01 00 80 80 10 02 00
+ </MeNBtoSgNBContainer>
+ </value>
+ </SgNBAdditionRequest-IEs>
+ </protocolIEs>
+ </SgNBAdditionRequest>
+ </value>
+ </initiatingMessage>
+</X2AP-PDU>
+[0m[X2AP] X2AP_ProcedureCode_id_sgNBAdditionPreparation message!
+[0m[0m[X2AP] X2AP Association id: 136
+[0m[0m[RRC] x2u tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 0
+[0m[0m[NR_RRC] Received message X2AP_ENDC_SGNB_ADDITION_REQ
+[0m[0m[NR_RRC] Received ENDC sgNB addition request from X2AP
+[0m<UL-DCCH-Message>
+ <message>
+ <c1>
+ <ueCapabilityInformation>
+ <rrc-TransactionIdentifier>1</rrc-TransactionIdentifier>
+ <criticalExtensions>
+ <c1>
+ <ueCapabilityInformation-r8>
+ <ue-CapabilityRAT-ContainerList>
+ <UE-CapabilityRAT-Container>
+ <rat-Type><eutra/></rat-Type>
+ <ueCapabilityRAT-Container>
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+ 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1 FF
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+ F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF B1
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+ FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F FF
+ FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57 FF
+ B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF FF
+ CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD 8F
+ FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE 57
+ FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC 7F FF
+ FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2 BF FD
+ 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF FE
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+ FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF FF
+ FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF EC
+ 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF F2
+ BF FD 8F FF FF F9 5F FE C7 FF FF FC AF FF 63 FF
+ FF FE 57 FF B1 FF FF FF 2B FF D8 FF FF FF 95 FF
+ EC 7F FF FF CA FF F6 3F FF FF E5 7F FB 1F FF FF
+ F2 BF FB 67 60 00 07 EC 40 D9 D8 00 00 47 CE C0
+ 00 0B A0 00 00 08 BC 5E 2F 17 87 87 87 87 21 E1
+ E1 E1 E1 E1 E3 F8 FC 21 E1 E1 E1 E1 E1 E1 E1 E1
+ E1 E2 F1 78 B9 0F 0F 0F 0F 17 8B C5 E1 E1 E1 E1
+ E1 E1 E1 E1 E1 E1 E1 C8 B8 00 F7 40 00 00 00 00
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+ 02 00 10 04 01 00 40 03 E0 80 24 00 7C CA F3 40
+ 80 29 63 FF FF FF FF FF FF CD 29 77 8A 01 F0 00
+ 84 01 30 C0 00 00 00 00 00 AA 13 49 10 20 20 00
+ 5E 48 41 2E 28 00 26 BC 0C 00 40 00 10 41 04 00
+ 02 8C 80 00 00 88 00 00
+ </ueCapabilityRAT-Container>
+ </UE-CapabilityRAT-Container>
+ <UE-CapabilityRAT-Container>
+ <rat-Type><nr/></rat-Type>
+ <ueCapabilityRAT-Container>
+ E1 00 00 00 01 4F 7E 03 02 00 00 01 40 48 07 06
+ 0E 22 0C 00 02 13 60 10 73 E4 20 F0 00 82 40 31
+ 10 00 A0 58 9B A0 21 94 34 08 81 07 41 86 04 C0
+ 42 54 41 01 00 80 06 08 1C 1C 22 03 C8 0F 00 20
+ 1A 02 6E 26 F0 00 09 00 00 00 00 72 A6 80 00 80
+ 00 02 0C 30 00 1A 55 30
+ </ueCapabilityRAT-Container>
+ </UE-CapabilityRAT-Container>
+ <UE-CapabilityRAT-Container>
+ <rat-Type><eutra-nr/></rat-Type>
+ <ueCapabilityRAT-Container>
+ 01 1C 04 81 60 C0 1C 4D 00 00 00 04 00 40 34 04
+ D0 10 44 04 14 E9 C0 00 20 00 10 08 08 01 00 20
+ </ueCapabilityRAT-Container>
+ </UE-CapabilityRAT-Container>
+ </ue-CapabilityRAT-ContainerList>
+ </ueCapabilityInformation-r8>
+ </c1>
+ </criticalExtensions>
+ </ueCapabilityInformation>
+ </c1>
+ </message>
+</UL-DCCH-Message>
+[0m[NR_RRC] Returning new UE context at 0x7f5188003980
+[0m<CellGroupConfig>
+ <cellGroupId>1</cellGroupId>
+ <rlc-BearerToAddModList>
+ <RLC-BearerConfig>
+ <logicalChannelIdentity>4</logicalChannelIdentity>
+ <servedRadioBearer>
+ <drb-Identity>1</drb-Identity>
+ </servedRadioBearer>
+ <reestablishRLC><true/></reestablishRLC>
+ <rlc-Config>
+ <am>
+ <ul-AM-RLC>
+ <sn-FieldLength><size18/></sn-FieldLength>
+ <t-PollRetransmit><ms45/></t-PollRetransmit>
+ <pollPDU><p64/></pollPDU>
+ <pollByte><kB500/></pollByte>
+ <maxRetxThreshold><t32/></maxRetxThreshold>
+ </ul-AM-RLC>
+ <dl-AM-RLC>
+ <sn-FieldLength><size18/></sn-FieldLength>
+ <t-Reassembly><ms15/></t-Reassembly>
+ <t-StatusProhibit><ms15/></t-StatusProhibit>
+ </dl-AM-RLC>
+ </am>
+ </rlc-Config>
+ <mac-LogicalChannelConfig>
+ <ul-SpecificParameters>
+ <priority>1</priority>
+ <prioritisedBitRate><infinity/></prioritisedBitRate>
+ <bucketSizeDuration><ms50/></bucketSizeDuration>
+ <logicalChannelGroup>1</logicalChannelGroup>
+ <logicalChannelSR-Mask><false/></logicalChannelSR-Mask>
+ <logicalChannelSR-DelayTimerApplied><false/></logicalChannelSR-DelayTimerApplied>
+ </ul-SpecificParameters>
+ </mac-LogicalChannelConfig>
+ </RLC-BearerConfig>
+ </rlc-BearerToAddModList>
+ <mac-CellGroupConfig>
+ <bsr-Config>
+ <periodicBSR-Timer><sf80/></periodicBSR-Timer>
+ <retxBSR-Timer><sf320/></retxBSR-Timer>
+ </bsr-Config>
+ <tag-Config>
+ <tag-ToAddModList>
+ <TAG>
+ <tag-Id>0</tag-Id>
+ <timeAlignmentTimer><infinity/></timeAlignmentTimer>
+ </TAG>
+ </tag-ToAddModList>
+ </tag-Config>
+ <phr-Config>
+ <setup>
+ <phr-PeriodicTimer><sf20/></phr-PeriodicTimer>
+ <phr-ProhibitTimer><sf0/></phr-ProhibitTimer>
+ <phr-Tx-PowerFactorChange><dB3/></phr-Tx-PowerFactorChange>
+ <multiplePHR><false/></multiplePHR>
+ <dummy><false/></dummy>
+ <phr-Type2OtherCell><false/></phr-Type2OtherCell>
+ <phr-ModeOtherCG><real/></phr-ModeOtherCG>
+ </setup>
+ </phr-Config>
+ <skipUplinkTxDynamic><false/></skipUplinkTxDynamic>
+ </mac-CellGroupConfig>
+ <physicalCellGroupConfig>
+ <p-NR-FR1>20</p-NR-FR1>
+ <pdsch-HARQ-ACK-Codebook><dynamic/></pdsch-HARQ-ACK-Codebook>
+ </physicalCellGroupConfig>
+ <spCellConfig>
+ <servCellIndex>1</servCellIndex>
+ <reconfigurationWithSync>
+ <spCellConfigCommon>
+ <physCellId>0</physCellId>
+ <downlinkConfigCommon>
+ <frequencyInfoDL>
+ <absoluteFrequencySSB>641272</absoluteFrequencySSB>
+ <frequencyBandList>
+ <FreqBandIndicatorNR>78</FreqBandIndicatorNR>
+ </frequencyBandList>
+ <absoluteFrequencyPointA>640000</absoluteFrequencyPointA>
+ <scs-SpecificCarrierList>
+ <SCS-SpecificCarrier>
+ <offsetToCarrier>0</offsetToCarrier>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ <carrierBandwidth>106</carrierBandwidth>
+ </SCS-SpecificCarrier>
+ </scs-SpecificCarrierList>
+ </frequencyInfoDL>
+ <initialDownlinkBWP>
+ <genericParameters>
+ <locationAndBandwidth>6366</locationAndBandwidth>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ </genericParameters>
+ <pdcch-ConfigCommon>
+ <setup>
+ <controlResourceSetZero>0</controlResourceSetZero>
+ <searchSpaceZero>0</searchSpaceZero>
+ </setup>
+ </pdcch-ConfigCommon>
+ <pdsch-ConfigCommon>
+ <setup>
+ <pdsch-TimeDomainAllocationList>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>40</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>53</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>54</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>57</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ </pdsch-TimeDomainAllocationList>
+ </setup>
+ </pdsch-ConfigCommon>
+ </initialDownlinkBWP>
+ </downlinkConfigCommon>
+ <uplinkConfigCommon>
+ <frequencyInfoUL>
+ <frequencyBandList>
+ <FreqBandIndicatorNR>78</FreqBandIndicatorNR>
+ </frequencyBandList>
+ <scs-SpecificCarrierList>
+ <SCS-SpecificCarrier>
+ <offsetToCarrier>0</offsetToCarrier>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ <carrierBandwidth>106</carrierBandwidth>
+ </SCS-SpecificCarrier>
+ </scs-SpecificCarrierList>
+ <p-Max>20</p-Max>
+ </frequencyInfoUL>
+ <initialUplinkBWP>
+ <genericParameters>
+ <locationAndBandwidth>6366</locationAndBandwidth>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ </genericParameters>
+ <rach-ConfigCommon>
+ <setup>
+ <rach-ConfigGeneric>
+ <prach-ConfigurationIndex>98</prach-ConfigurationIndex>
+ <msg1-FDM><one/></msg1-FDM>
+ <msg1-FrequencyStart>0</msg1-FrequencyStart>
+ <zeroCorrelationZoneConfig>13</zeroCorrelationZoneConfig>
+ <preambleReceivedTargetPower>-100</preambleReceivedTargetPower>
+ <preambleTransMax><n10/></preambleTransMax>
+ <powerRampingStep><dB2/></powerRampingStep>
+ <ra-ResponseWindow><sl20/></ra-ResponseWindow>
+ </rach-ConfigGeneric>
+ <ssb-perRACH-OccasionAndCB-PreamblesPerSSB>
+ <one><n60/></one>
+ </ssb-perRACH-OccasionAndCB-PreamblesPerSSB>
+ <ra-ContentionResolutionTimer><sf64/></ra-ContentionResolutionTimer>
+ <rsrp-ThresholdSSB>19</rsrp-ThresholdSSB>
+ <prach-RootSequenceIndex>
+ <l139>1</l139>
+ </prach-RootSequenceIndex>
+ <msg1-SubcarrierSpacing><kHz30/></msg1-SubcarrierSpacing>
+ <restrictedSetConfig><unrestrictedSet/></restrictedSetConfig>
+ </setup>
+ </rach-ConfigCommon>
+ <pusch-ConfigCommon>
+ <setup>
+ <groupHoppingEnabledTransformPrecoding><enabled/></groupHoppingEnabledTransformPrecoding>
+ <pusch-TimeDomainAllocationList>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>2</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>55</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>2</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>69</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>7</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>52</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ </pusch-TimeDomainAllocationList>
+ <msg3-DeltaPreamble>1</msg3-DeltaPreamble>
+ <p0-NominalWithGrant>-90</p0-NominalWithGrant>
+ </setup>
+ </pusch-ConfigCommon>
+ <pucch-ConfigCommon>
+ <setup>
+ <pucch-ResourceCommon>0</pucch-ResourceCommon>
+ <pucch-GroupHopping><neither/></pucch-GroupHopping>
+ <hoppingId>40</hoppingId>
+ <p0-nominal>-90</p0-nominal>
+ </setup>
+ </pucch-ConfigCommon>
+ </initialUplinkBWP>
+ <dummy><ms500/></dummy>
+ </uplinkConfigCommon>
+ <ssb-PositionsInBurst>
+ <mediumBitmap>
+ 10000000
+ </mediumBitmap>
+ </ssb-PositionsInBurst>
+ <ssb-periodicityServingCell><ms20/></ssb-periodicityServingCell>
+ <dmrs-TypeA-Position><pos2/></dmrs-TypeA-Position>
+ <ssbSubcarrierSpacing><kHz30/></ssbSubcarrierSpacing>
+ <tdd-UL-DL-ConfigurationCommon>
+ <referenceSubcarrierSpacing><kHz30/></referenceSubcarrierSpacing>
+ <pattern1>
+ <dl-UL-TransmissionPeriodicity><ms5/></dl-UL-TransmissionPeriodicity>
+ <nrofDownlinkSlots>7</nrofDownlinkSlots>
+ <nrofDownlinkSymbols>6</nrofDownlinkSymbols>
+ <nrofUplinkSlots>2</nrofUplinkSlots>
+ <nrofUplinkSymbols>4</nrofUplinkSymbols>
+ </pattern1>
+ </tdd-UL-DL-ConfigurationCommon>
+ <ss-PBCH-BlockPower>-25</ss-PBCH-BlockPower>
+ </spCellConfigCommon>
+ <newUE-Identity>9195</newUE-Identity>
+ <t304><ms2000/></t304>
+ <rach-ConfigDedicated>
+ <uplink>
+ <cfra>
+ <occasions>
+ <rach-ConfigGeneric>
+ <prach-ConfigurationIndex>98</prach-ConfigurationIndex>
+ <msg1-FDM><one/></msg1-FDM>
+ <msg1-FrequencyStart>0</msg1-FrequencyStart>
+ <zeroCorrelationZoneConfig>13</zeroCorrelationZoneConfig>
+ <preambleReceivedTargetPower>-100</preambleReceivedTargetPower>
+ <preambleTransMax><n10/></preambleTransMax>
+ <powerRampingStep><dB2/></powerRampingStep>
+ <ra-ResponseWindow><sl20/></ra-ResponseWindow>
+ </rach-ConfigGeneric>
+ </occasions>
+ <resources>
+ <ssb>
+ <ssb-ResourceList>
+ <CFRA-SSB-Resource>
+ <ssb>0</ssb>
+ <ra-PreambleIndex>63</ra-PreambleIndex>
+ </CFRA-SSB-Resource>
+ </ssb-ResourceList>
+ <ra-ssb-OccasionMaskIndex>0</ra-ssb-OccasionMaskIndex>
+ </ssb>
+ </resources>
+ </cfra>
+ </uplink>
+ </rach-ConfigDedicated>
+ </reconfigurationWithSync>
+ <rlf-TimersAndConstants>
+ <setup>
+ <t310><ms2000/></t310>
+ <n310><n10/></n310>
+ <n311><n1/></n311>
+ <ext1>
+ <t311-v1530><ms30000/></t311-v1530>
+ </ext1>
+ </setup>
+ </rlf-TimersAndConstants>
+ <spCellConfigDedicated>
+ <initialDownlinkBWP>
+ <pdsch-Config>
+ <setup>
+ <dmrs-DownlinkForPDSCH-MappingTypeA>
+ <setup>
+ <dmrs-AdditionalPosition><pos0/></dmrs-AdditionalPosition>
+ </setup>
+ </dmrs-DownlinkForPDSCH-MappingTypeA>
+ <resourceAllocation><resourceAllocationType1/></resourceAllocation>
+ <rbg-Size><config1/></rbg-Size>
+ <maxNrofCodeWordsScheduledByDCI><n1/></maxNrofCodeWordsScheduledByDCI>
+ <prb-BundlingType>
+ <staticBundling>
+ <bundleSize><wideband/></bundleSize>
+ </staticBundling>
+ </prb-BundlingType>
+ </setup>
+ </pdsch-Config>
+ </initialDownlinkBWP>
+ <downlinkBWP-ToAddModList>
+ <BWP-Downlink>
+ <bwp-Id>1</bwp-Id>
+ <bwp-Common>
+ <genericParameters>
+ <locationAndBandwidth>28875</locationAndBandwidth>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ </genericParameters>
+ <pdcch-ConfigCommon>
+ <setup>
+ <commonControlResourceSet>
+ <controlResourceSetId>1</controlResourceSetId>
+ <frequencyDomainResources>
+ 111111111111111100000000000000000000000000000
+ </frequencyDomainResources>
+ <duration>1</duration>
+ <cce-REG-MappingType>
+ <nonInterleaved></nonInterleaved>
+ </cce-REG-MappingType>
+ <precoderGranularity><sameAsREG-bundle/></precoderGranularity>
+ <tci-StatesPDCCH-ToAddList>
+ <TCI-StateId>0</TCI-StateId>
+ <TCI-StateId>1</TCI-StateId>
+ <TCI-StateId>2</TCI-StateId>
+ <TCI-StateId>3</TCI-StateId>
+ <TCI-StateId>4</TCI-StateId>
+ <TCI-StateId>5</TCI-StateId>
+ <TCI-StateId>6</TCI-StateId>
+ <TCI-StateId>7</TCI-StateId>
+ </tci-StatesPDCCH-ToAddList>
+ </commonControlResourceSet>
+ <commonSearchSpaceList>
+ <SearchSpace>
+ <searchSpaceId>1</searchSpaceId>
+ <controlResourceSetId>1</controlResourceSetId>
+ <monitoringSlotPeriodicityAndOffset>
+ <sl1></sl1>
+ </monitoringSlotPeriodicityAndOffset>
+ <monitoringSymbolsWithinSlot>
+ 11000000000000
+ </monitoringSymbolsWithinSlot>
+ <nrofCandidates>
+ <aggregationLevel1><n0/></aggregationLevel1>
+ <aggregationLevel2><n0/></aggregationLevel2>
+ <aggregationLevel4><n1/></aggregationLevel4>
+ <aggregationLevel8><n0/></aggregationLevel8>
+ <aggregationLevel16><n0/></aggregationLevel16>
+ </nrofCandidates>
+ <searchSpaceType>
+ <common>
+ <dci-Format0-0-AndFormat1-0>
+ </dci-Format0-0-AndFormat1-0>
+ </common>
+ </searchSpaceType>
+ </SearchSpace>
+ </commonSearchSpaceList>
+ <ra-SearchSpace>1</ra-SearchSpace>
+ </setup>
+ </pdcch-ConfigCommon>
+ <pdsch-ConfigCommon>
+ <setup>
+ <pdsch-TimeDomainAllocationList>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>40</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>53</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>54</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ <PDSCH-TimeDomainResourceAllocation>
+ <k0>0</k0>
+ <mappingType><typeA/></mappingType>
+ <startSymbolAndLength>57</startSymbolAndLength>
+ </PDSCH-TimeDomainResourceAllocation>
+ </pdsch-TimeDomainAllocationList>
+ </setup>
+ </pdsch-ConfigCommon>
+ </bwp-Common>
+ <bwp-Dedicated>
+ <pdcch-Config>
+ <setup>
+ <controlResourceSetToAddModList>
+ <ControlResourceSet>
+ <controlResourceSetId>1</controlResourceSetId>
+ <frequencyDomainResources>
+ 111111111111111100000000000000000000000000000
+ </frequencyDomainResources>
+ <duration>1</duration>
+ <cce-REG-MappingType>
+ <nonInterleaved></nonInterleaved>
+ </cce-REG-MappingType>
+ <precoderGranularity><sameAsREG-bundle/></precoderGranularity>
+ <tci-StatesPDCCH-ToAddList>
+ <TCI-StateId>0</TCI-StateId>
+ <TCI-StateId>1</TCI-StateId>
+ <TCI-StateId>2</TCI-StateId>
+ <TCI-StateId>3</TCI-StateId>
+ <TCI-StateId>4</TCI-StateId>
+ <TCI-StateId>5</TCI-StateId>
+ <TCI-StateId>6</TCI-StateId>
+ <TCI-StateId>7</TCI-StateId>
+ </tci-StatesPDCCH-ToAddList>
+ </ControlResourceSet>
+ </controlResourceSetToAddModList>
+ <searchSpacesToAddModList>
+ <SearchSpace>
+ <searchSpaceId>2</searchSpaceId>
+ <controlResourceSetId>1</controlResourceSetId>
+ <monitoringSlotPeriodicityAndOffset>
+ <sl1></sl1>
+ </monitoringSlotPeriodicityAndOffset>
+ <monitoringSymbolsWithinSlot>
+ 11000000000000
+ </monitoringSymbolsWithinSlot>
+ <nrofCandidates>
+ <aggregationLevel1><n0/></aggregationLevel1>
+ <aggregationLevel2><n0/></aggregationLevel2>
+ <aggregationLevel4><n4/></aggregationLevel4>
+ <aggregationLevel8><n0/></aggregationLevel8>
+ <aggregationLevel16><n0/></aggregationLevel16>
+ </nrofCandidates>
+ <searchSpaceType>
+ <ue-Specific>
+ <dci-Formats><formats0-1-And-1-1/></dci-Formats>
+ </ue-Specific>
+ </searchSpaceType>
+ </SearchSpace>
+ </searchSpacesToAddModList>
+ </setup>
+ </pdcch-Config>
+ <pdsch-Config>
+ <setup>
+ <dmrs-DownlinkForPDSCH-MappingTypeA>
+ <setup>
+ <dmrs-AdditionalPosition><pos0/></dmrs-AdditionalPosition>
+ </setup>
+ </dmrs-DownlinkForPDSCH-MappingTypeA>
+ <resourceAllocation><resourceAllocationType1/></resourceAllocation>
+ <rbg-Size><config1/></rbg-Size>
+ <maxNrofCodeWordsScheduledByDCI><n1/></maxNrofCodeWordsScheduledByDCI>
+ <prb-BundlingType>
+ <staticBundling>
+ <bundleSize><wideband/></bundleSize>
+ </staticBundling>
+ </prb-BundlingType>
+ </setup>
+ </pdsch-Config>
+ </bwp-Dedicated>
+ </BWP-Downlink>
+ </downlinkBWP-ToAddModList>
+ <firstActiveDownlinkBWP-Id>1</firstActiveDownlinkBWP-Id>
+ <defaultDownlinkBWP-Id>1</defaultDownlinkBWP-Id>
+ <uplinkConfig>
+ <initialUplinkBWP>
+ <pusch-Config>
+ <setup>
+ <txConfig><codebook/></txConfig>
+ <dmrs-UplinkForPUSCH-MappingTypeB>
+ <setup>
+ <transformPrecodingDisabled>
+ </transformPrecodingDisabled>
+ </setup>
+ </dmrs-UplinkForPUSCH-MappingTypeB>
+ <pusch-PowerControl>
+ <msg3-Alpha><alpha1/></msg3-Alpha>
+ <p0-AlphaSets>
+ <P0-PUSCH-AlphaSet>
+ <p0-PUSCH-AlphaSetId>0</p0-PUSCH-AlphaSetId>
+ <p0>0</p0>
+ <alpha><alpha1/></alpha>
+ </P0-PUSCH-AlphaSet>
+ </p0-AlphaSets>
+ <pathlossReferenceRSToAddModList>
+ <PUSCH-PathlossReferenceRS>
+ <pusch-PathlossReferenceRS-Id>0</pusch-PathlossReferenceRS-Id>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ </PUSCH-PathlossReferenceRS>
+ </pathlossReferenceRSToAddModList>
+ </pusch-PowerControl>
+ <resourceAllocation><resourceAllocationType1/></resourceAllocation>
+ <transformPrecoder><disabled/></transformPrecoder>
+ <codebookSubset><nonCoherent/></codebookSubset>
+ <maxRank>1</maxRank>
+ </setup>
+ </pusch-Config>
+ <srs-Config>
+ <setup>
+ <srs-ResourceSetToAddModList>
+ <SRS-ResourceSet>
+ <srs-ResourceSetId>0</srs-ResourceSetId>
+ <srs-ResourceIdList>
+ <SRS-ResourceId>0</SRS-ResourceId>
+ </srs-ResourceIdList>
+ <resourceType>
+ <aperiodic>
+ <aperiodicSRS-ResourceTrigger>1</aperiodicSRS-ResourceTrigger>
+ <slotOffset>2</slotOffset>
+ </aperiodic>
+ </resourceType>
+ <usage><codebook/></usage>
+ <alpha><alpha1/></alpha>
+ <p0>-80</p0>
+ </SRS-ResourceSet>
+ </srs-ResourceSetToAddModList>
+ <srs-ResourceToAddModList>
+ <SRS-Resource>
+ <srs-ResourceId>0</srs-ResourceId>
+ <nrofSRS-Ports><port1/></nrofSRS-Ports>
+ <transmissionComb>
+ <n2>
+ <combOffset-n2>0</combOffset-n2>
+ <cyclicShift-n2>0</cyclicShift-n2>
+ </n2>
+ </transmissionComb>
+ <resourceMapping>
+ <startPosition>2</startPosition>
+ <nrofSymbols><n1/></nrofSymbols>
+ <repetitionFactor><n1/></repetitionFactor>
+ </resourceMapping>
+ <freqDomainPosition>0</freqDomainPosition>
+ <freqDomainShift>0</freqDomainShift>
+ <freqHopping>
+ <c-SRS>61</c-SRS>
+ <b-SRS>0</b-SRS>
+ <b-hop>0</b-hop>
+ </freqHopping>
+ <groupOrSequenceHopping><neither/></groupOrSequenceHopping>
+ <resourceType>
+ <aperiodic>
+ </aperiodic>
+ </resourceType>
+ <sequenceId>40</sequenceId>
+ <spatialRelationInfo>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ </spatialRelationInfo>
+ </SRS-Resource>
+ </srs-ResourceToAddModList>
+ </setup>
+ </srs-Config>
+ </initialUplinkBWP>
+ <uplinkBWP-ToAddModList>
+ <BWP-Uplink>
+ <bwp-Id>1</bwp-Id>
+ <bwp-Common>
+ <genericParameters>
+ <locationAndBandwidth>28875</locationAndBandwidth>
+ <subcarrierSpacing><kHz30/></subcarrierSpacing>
+ </genericParameters>
+ <rach-ConfigCommon>
+ <setup>
+ <rach-ConfigGeneric>
+ <prach-ConfigurationIndex>98</prach-ConfigurationIndex>
+ <msg1-FDM><one/></msg1-FDM>
+ <msg1-FrequencyStart>0</msg1-FrequencyStart>
+ <zeroCorrelationZoneConfig>13</zeroCorrelationZoneConfig>
+ <preambleReceivedTargetPower>-100</preambleReceivedTargetPower>
+ <preambleTransMax><n10/></preambleTransMax>
+ <powerRampingStep><dB2/></powerRampingStep>
+ <ra-ResponseWindow><sl20/></ra-ResponseWindow>
+ </rach-ConfigGeneric>
+ <ssb-perRACH-OccasionAndCB-PreamblesPerSSB>
+ <one><n60/></one>
+ </ssb-perRACH-OccasionAndCB-PreamblesPerSSB>
+ <ra-ContentionResolutionTimer><sf64/></ra-ContentionResolutionTimer>
+ <rsrp-ThresholdSSB>19</rsrp-ThresholdSSB>
+ <prach-RootSequenceIndex>
+ <l139>1</l139>
+ </prach-RootSequenceIndex>
+ <msg1-SubcarrierSpacing><kHz30/></msg1-SubcarrierSpacing>
+ <restrictedSetConfig><unrestrictedSet/></restrictedSetConfig>
+ </setup>
+ </rach-ConfigCommon>
+ <pusch-ConfigCommon>
+ <setup>
+ <groupHoppingEnabledTransformPrecoding><enabled/></groupHoppingEnabledTransformPrecoding>
+ <pusch-TimeDomainAllocationList>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>2</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>55</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>2</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>69</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ <PUSCH-TimeDomainResourceAllocation>
+ <k2>7</k2>
+ <mappingType><typeB/></mappingType>
+ <startSymbolAndLength>52</startSymbolAndLength>
+ </PUSCH-TimeDomainResourceAllocation>
+ </pusch-TimeDomainAllocationList>
+ <msg3-DeltaPreamble>1</msg3-DeltaPreamble>
+ <p0-NominalWithGrant>-90</p0-NominalWithGrant>
+ </setup>
+ </pusch-ConfigCommon>
+ <pucch-ConfigCommon>
+ <setup>
+ <pucch-ResourceCommon>0</pucch-ResourceCommon>
+ <pucch-GroupHopping><neither/></pucch-GroupHopping>
+ <hoppingId>40</hoppingId>
+ <p0-nominal>-90</p0-nominal>
+ </setup>
+ </pucch-ConfigCommon>
+ </bwp-Common>
+ <bwp-Dedicated>
+ <pucch-Config>
+ <setup>
+ <resourceSetToAddModList>
+ <PUCCH-ResourceSet>
+ <pucch-ResourceSetId>0</pucch-ResourceSetId>
+ <resourceList>
+ <PUCCH-ResourceId>1</PUCCH-ResourceId>
+ <PUCCH-ResourceId>2</PUCCH-ResourceId>
+ </resourceList>
+ </PUCCH-ResourceSet>
+ <PUCCH-ResourceSet>
+ <pucch-ResourceSetId>1</pucch-ResourceSetId>
+ <resourceList>
+ <PUCCH-ResourceId>3</PUCCH-ResourceId>
+ <PUCCH-ResourceId>4</PUCCH-ResourceId>
+ </resourceList>
+ </PUCCH-ResourceSet>
+ </resourceSetToAddModList>
+ <resourceToAddModList>
+ <PUCCH-Resource>
+ <pucch-ResourceId>1</pucch-ResourceId>
+ <startingPRB>48</startingPRB>
+ <format>
+ <format0>
+ <initialCyclicShift>0</initialCyclicShift>
+ <nrofSymbols>1</nrofSymbols>
+ <startingSymbolIndex>13</startingSymbolIndex>
+ </format0>
+ </format>
+ </PUCCH-Resource>
+ <PUCCH-Resource>
+ <pucch-ResourceId>2</pucch-ResourceId>
+ <startingPRB>48</startingPRB>
+ <format>
+ <format0>
+ <initialCyclicShift>0</initialCyclicShift>
+ <nrofSymbols>1</nrofSymbols>
+ <startingSymbolIndex>12</startingSymbolIndex>
+ </format0>
+ </format>
+ </PUCCH-Resource>
+ <PUCCH-Resource>
+ <pucch-ResourceId>3</pucch-ResourceId>
+ <startingPRB>40</startingPRB>
+ <format>
+ <format2>
+ <nrofPRBs>16</nrofPRBs>
+ <nrofSymbols>1</nrofSymbols>
+ <startingSymbolIndex>13</startingSymbolIndex>
+ </format2>
+ </format>
+ </PUCCH-Resource>
+ <PUCCH-Resource>
+ <pucch-ResourceId>4</pucch-ResourceId>
+ <startingPRB>40</startingPRB>
+ <format>
+ <format2>
+ <nrofPRBs>16</nrofPRBs>
+ <nrofSymbols>1</nrofSymbols>
+ <startingSymbolIndex>12</startingSymbolIndex>
+ </format2>
+ </format>
+ </PUCCH-Resource>
+ </resourceToAddModList>
+ <format2>
+ <setup>
+ <maxCodeRate><zeroDot15/></maxCodeRate>
+ </setup>
+ </format2>
+ <dl-DataToUL-ACK>
+ <INTEGER>2</INTEGER>
+ <INTEGER>3</INTEGER>
+ <INTEGER>4</INTEGER>
+ <INTEGER>5</INTEGER>
+ <INTEGER>6</INTEGER>
+ <INTEGER>7</INTEGER>
+ <INTEGER>0</INTEGER>
+ <INTEGER>0</INTEGER>
+ </dl-DataToUL-ACK>
+ <spatialRelationInfoToAddModList>
+ <PUCCH-SpatialRelationInfo>
+ <pucch-SpatialRelationInfoId>1</pucch-SpatialRelationInfoId>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ <pucch-PathlossReferenceRS-Id>0</pucch-PathlossReferenceRS-Id>
+ <p0-PUCCH-Id>1</p0-PUCCH-Id>
+ <closedLoopIndex><i0/></closedLoopIndex>
+ </PUCCH-SpatialRelationInfo>
+ </spatialRelationInfoToAddModList>
+ <pucch-PowerControl>
+ <deltaF-PUCCH-f0>0</deltaF-PUCCH-f0>
+ <deltaF-PUCCH-f1>0</deltaF-PUCCH-f1>
+ <deltaF-PUCCH-f2>0</deltaF-PUCCH-f2>
+ <deltaF-PUCCH-f3>0</deltaF-PUCCH-f3>
+ <deltaF-PUCCH-f4>0</deltaF-PUCCH-f4>
+ <p0-Set>
+ <P0-PUCCH>
+ <p0-PUCCH-Id>1</p0-PUCCH-Id>
+ <p0-PUCCH-Value>0</p0-PUCCH-Value>
+ </P0-PUCCH>
+ </p0-Set>
+ <pathlossReferenceRSs>
+ <PUCCH-PathlossReferenceRS>
+ <pucch-PathlossReferenceRS-Id>0</pucch-PathlossReferenceRS-Id>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ </PUCCH-PathlossReferenceRS>
+ </pathlossReferenceRSs>
+ </pucch-PowerControl>
+ </setup>
+ </pucch-Config>
+ <pusch-Config>
+ <setup>
+ <txConfig><codebook/></txConfig>
+ <dmrs-UplinkForPUSCH-MappingTypeB>
+ <setup>
+ <transformPrecodingDisabled>
+ </transformPrecodingDisabled>
+ </setup>
+ </dmrs-UplinkForPUSCH-MappingTypeB>
+ <pusch-PowerControl>
+ <msg3-Alpha><alpha1/></msg3-Alpha>
+ <p0-AlphaSets>
+ <P0-PUSCH-AlphaSet>
+ <p0-PUSCH-AlphaSetId>0</p0-PUSCH-AlphaSetId>
+ <p0>0</p0>
+ <alpha><alpha1/></alpha>
+ </P0-PUSCH-AlphaSet>
+ </p0-AlphaSets>
+ <pathlossReferenceRSToAddModList>
+ <PUSCH-PathlossReferenceRS>
+ <pusch-PathlossReferenceRS-Id>0</pusch-PathlossReferenceRS-Id>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ </PUSCH-PathlossReferenceRS>
+ </pathlossReferenceRSToAddModList>
+ </pusch-PowerControl>
+ <resourceAllocation><resourceAllocationType1/></resourceAllocation>
+ <transformPrecoder><disabled/></transformPrecoder>
+ <codebookSubset><nonCoherent/></codebookSubset>
+ <maxRank>1</maxRank>
+ </setup>
+ </pusch-Config>
+ <srs-Config>
+ <setup>
+ <srs-ResourceSetToAddModList>
+ <SRS-ResourceSet>
+ <srs-ResourceSetId>0</srs-ResourceSetId>
+ <srs-ResourceIdList>
+ <SRS-ResourceId>0</SRS-ResourceId>
+ </srs-ResourceIdList>
+ <resourceType>
+ <aperiodic>
+ <aperiodicSRS-ResourceTrigger>1</aperiodicSRS-ResourceTrigger>
+ <slotOffset>2</slotOffset>
+ </aperiodic>
+ </resourceType>
+ <usage><codebook/></usage>
+ <alpha><alpha1/></alpha>
+ <p0>-80</p0>
+ </SRS-ResourceSet>
+ </srs-ResourceSetToAddModList>
+ <srs-ResourceToAddModList>
+ <SRS-Resource>
+ <srs-ResourceId>0</srs-ResourceId>
+ <nrofSRS-Ports><port1/></nrofSRS-Ports>
+ <transmissionComb>
+ <n2>
+ <combOffset-n2>0</combOffset-n2>
+ <cyclicShift-n2>0</cyclicShift-n2>
+ </n2>
+ </transmissionComb>
+ <resourceMapping>
+ <startPosition>2</startPosition>
+ <nrofSymbols><n1/></nrofSymbols>
+ <repetitionFactor><n1/></repetitionFactor>
+ </resourceMapping>
+ <freqDomainPosition>0</freqDomainPosition>
+ <freqDomainShift>0</freqDomainShift>
+ <freqHopping>
+ <c-SRS>61</c-SRS>
+ <b-SRS>0</b-SRS>
+ <b-hop>0</b-hop>
+ </freqHopping>
+ <groupOrSequenceHopping><neither/></groupOrSequenceHopping>
+ <resourceType>
+ <aperiodic>
+ </aperiodic>
+ </resourceType>
+ <sequenceId>40</sequenceId>
+ <spatialRelationInfo>
+ <referenceSignal>
+ <csi-RS-Index>0</csi-RS-Index>
+ </referenceSignal>
+ </spatialRelationInfo>
+ </SRS-Resource>
+ </srs-ResourceToAddModList>
+ </setup>
+ </srs-Config>
+ </bwp-Dedicated>
+ </BWP-Uplink>
+ </uplinkBWP-ToAddModList>
+ <firstActiveUplinkBWP-Id>1</firstActiveUplinkBWP-Id>
+ </uplinkConfig>
+ <pdsch-ServingCellConfig>
+ <setup>
+ <ext1>
+ <maxMIMO-Layers>2</maxMIMO-Layers>
+ </ext1>
+ </setup>
+ </pdsch-ServingCellConfig>
+ <tag-Id>0</tag-Id>
+ </spCellConfigDedicated>
+ </spCellConfig>
+</CellGroupConfig>
+<RadioBearerConfig>
+ <drb-ToAddModList>
+ <DRB-ToAddMod>
+ <cnAssociation>
+ <eps-BearerIdentity>5</eps-BearerIdentity>
+ </cnAssociation>
+ <drb-Identity>1</drb-Identity>
+ <pdcp-Config>
+ <drb>
+ <discardTimer><ms30/></discardTimer>
+ <pdcp-SN-SizeUL><len18bits/></pdcp-SN-SizeUL>
+ <pdcp-SN-SizeDL><len18bits/></pdcp-SN-SizeDL>
+ <headerCompression>
+ <notUsed></notUsed>
+ </headerCompression>
+ </drb>
+ <t-Reordering><ms0/></t-Reordering>
+ </pdcp-Config>
+ </DRB-ToAddMod>
+ </drb-ToAddModList>
+ <securityConfig>
+ <securityAlgorithmConfig>
+ <cipheringAlgorithm><nea0/></cipheringAlgorithm>
+ </securityAlgorithmConfig>
+ <keyToUse><master/></keyToUse>
+ </securityConfig>
+</RadioBearerConfig>
+[0m[RRC] Dumping NR_RRCReconfiguration message (309 bytes)
+[0m0881325c40f1c032086fc61a083cc8390a83c4201065742dcc600349c8f802693880000004d2c31bc6a000a700a201ac0368073a404d0000269c9c31bc65462001acccd7dc9c0497942b7858b1ed1385c00a1c0300842c0760122323ebc48c40035999a0007e1b600203805b2012400404808c659c32cca281ffff000000010e0008206102860e6e088600001010034e0144035806d00e5950081ffff000000010e0008206102860e1b84218000100b20020240464ac2a581c2082c1c1821c200e25038000040bde802000400001e8002820032e70cb32a31000d6666bee4e024bca15bc2c58f689c2e0050e0d54835010208841840601180068086001803142f681050bd920f23456700008000fe8421080100804b038410583830438401c4a0700000817bd004000800003d00050400e00203100
+[0m[RRC] Dumping scg_RB_Config message (8 bytes)
+[0m1409281782c00c00
+[0m[RRC] S1-U tunnel: index 0 target sgw ip 192.168.18.99 length 32 gtp teid 2
+[0m[0m[GTPV1U] Configured GTPu address : c612a8c0
+[0m[0m[GTPV1U] Copied to create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170
+[0m[0m[RRC] [FRAME 00000][eNB][MOD 00][RNTI 23eb] rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (2462855170, 2462855170) bearer UE context index 0, msg index 0, id 5, gtp addr len 4
+[0m[0m[RRC] S1-U create_tunnel_resp tunnel: index 0 target gNB ip 192.168.18.198 length 4 gtp teid 2462855170
+[0m[0m[RRC] X2AP sGNB Addition Request: index 0 target gNB ip 192.168.18.198 length 32 gtp teid 2462855170
+[0m[0m[MAC] [gNB 0] Adding UE with rnti 23eb (next avail 0, num_UEs 0)
+[0m[0m[MAC] gNB 0] Add NR UE_id 0 : rnti 23eb
+[0m[0m[PHY] Added new UE_id 0/23eb with initial secondaryCellGroup
+[0m<X2AP-PDU>
+ <successfulOutcome>
+ <procedureCode>27</procedureCode>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBAdditionRequestAcknowledge>
+ <protocolIEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>111</id>
+ <criticality><reject/></criticality>
+ <value>
+ <UE-X2AP-ID>0</UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>207</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNB-UE-X2AP-ID>0</SgNB-UE-X2AP-ID>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>210</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-Admitted-ToBeAdded-SgNBAddReqAckList>
+ <ProtocolIE-Single-Container>
+ <id>213</id>
+ <criticality><ignore/></criticality>
+ <value>
+ <E-RABs-Admitted-ToBeAdded-SgNBAddReqAck-Item>
+ <e-RAB-ID>5</e-RAB-ID>
+ <en-DC-ResourceConfiguration>
+ <pDCPatSgNB><present/></pDCPatSgNB>
+ <mCGresources><not-present/></mCGresources>
+ <sCGresources><not-present/></sCGresources>
+ </en-DC-ResourceConfiguration>
+ <resource-configuration>
+ <sgNBPDCPpresent>
+ <s1-DL-GTPtunnelEndpoint>
+ <transportLayerAddress>
+ 11000000101010000001001011000110
+ </transportLayerAddress>
+ <gTP-TEID>92 CC 30 02</gTP-TEID>
+ </s1-DL-GTPtunnelEndpoint>
+ </sgNBPDCPpresent>
+ </resource-configuration>
+ </E-RABs-Admitted-ToBeAdded-SgNBAddReqAck-Item>
+ </value>
+ </ProtocolIE-Single-Container>
+ </E-RABs-Admitted-ToBeAdded-SgNBAddReqAckList>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ <SgNBAdditionRequestAcknowledge-IEs>
+ <id>211</id>
+ <criticality><reject/></criticality>
+ <value>
+ <SgNBtoMeNBContainer>
+ 18 04 09 A8 44 09 92 E2 07 8E 01 90 43 7E 30 D0
+ 41 E6 41 C8 54 1E 21 00 83 2B A1 6E 63 00 1A 4E
+ 47 C0 13 49 C4 00 00 00 26 96 18 DE 35 00 05 38
+ 05 10 0D 60 1B 40 39 D2 02 68 00 01 34 E4 E1 8D
+ E3 2A 31 00 0D 66 66 BE E4 E0 24 BC A1 5B C2 C5
+ 8F 68 9C 2E 00 50 E0 18 04 21 60 3B 00 91 19 1F
+ 5E 24 62 00 1A CC CD 00 03 F0 DB 00 10 1C 02 D9
+ 00 92 00 20 24 04 63 2C E1 96 65 14 0F FF F8 00
+ 00 00 08 70 00 41 03 08 14 30 73 70 44 30 00 00
+ 80 80 1A 70 0A 20 1A C0 36 80 72 CA 80 40 FF FF
+ 80 00 00 00 87 00 04 10 30 81 43 07 0D C2 10 C0
+ 00 08 05 90 01 01 20 23 25 61 52 C0 E1 04 16 0E
+ 0C 10 E1 00 71 28 1C 00 00 20 5E F4 01 00 02 00
+ 00 0F 40 01 41 00 19 73 86 59 95 18 80 06 B3 33
+ 5F 72 70 12 5E 50 AD E1 62 C7 B4 4E 17 00 28 70
+ 6A A4 1A 80 81 04 42 0C 20 30 08 C0 03 40 43 00
+ 0C 01 8A 17 B4 08 28 5E C9 07 91 A2 B3 80 00 40
+ 00 7F 42 10 84 00 80 40 25 81 C2 08 2C 1C 18 21
+ C2 00 E2 50 38 00 00 40 BD E8 02 00 04 00 00 1E
+ 80 02 82 00 70 01 01 88 00 40 A0 49 40 BC 16 00
+ 60 00
+ </SgNBtoMeNBContainer>
+ </value>
+ </SgNBAdditionRequestAcknowledge-IEs>
+ </protocolIEs>
+ </SgNBAdditionRequestAcknowledge>
+ </value>
+ </successfulOutcome>
+</X2AP-PDU>
+[0m[X2AP] Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK
+[0m[0m[SCTP] Successfully sent 371 bytes on stream 0 for assoc_id 136
+[0m[0m[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[PHY] [gNB 0][RAPROC] Frame 751, slot 19 Initiating RA procedure with preamble 63, energy 35.7 dB, delay 6
+[0m[0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751, Slot 19 Initiating RA procedure for preamble index 63
+[0m[0m[MAC] [gNB 0][RAPROC] CC_id 0 Frame 751 Activating Msg2 generation in frame 752, slot 7 using RA rnti 10b
+[0m[0m[MAC] [gNB 0] [RAPROC] CC_id 0 Frame 752, slotP 7: Generating RAR DCI, state 1
+[0m[0m[MAC] [RAPROC] DCI type 1 payload: freq_alloc 120 (0,6,24), time_alloc 3, vrb to prb 0, mcs 0 tb_scaling 0
+[0m[0m[MAC] Frame 752: Subframe 7 : Adding common DL DCI for RA_RNTI 10b
+[0m[0m[MAC] Frame 752, Subframe 7: Setting Msg3 reception for Frame 752 Subframe 17
+[0m[0m[PHY] ULSCH received ok
+[0m[0m[MAC] [gNB 0][RAPROC] PUSCH with TC_RNTI c497 received correctly and UE_id 0 is now 5G connected
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 753 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 753 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 754 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 754 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 754 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 755 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 755 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 755 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 756 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 756 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 756 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[SCTP] Received notification for sd 87, type 32777
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 757 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 757 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 757 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 758 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 758 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 758 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 759 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 759 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 759 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 760 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 760 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 760 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 761 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 761 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 761 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 762 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 762 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 762 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 763 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 763 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 763 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 764 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 764 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 764 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 765 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 765 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 765 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 766 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 766 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 766 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 767 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 767 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 767 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 768 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 768 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 768 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 769 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 769 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 769 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 770 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 770 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 770 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 771 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 771 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 771 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 772 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 772 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 772 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 773 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 773 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 773 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 774 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 774 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 774 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 775 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 775 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 775 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 776 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 776 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 776 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 777 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 777 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 777 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 778 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 778 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 778 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 779 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 779 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 779 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 780 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 780 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 780 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 781 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 781 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 781 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 782 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 782 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 782 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 783 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 783 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 783 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 784 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 784 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 784 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 785 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 785 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 785 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 786 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 786 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 786 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 787 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 787 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 787 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 788 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 788 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 788 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 789 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 789 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 789 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 790 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 790 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 790 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 791 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 791 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 791 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 792 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 792 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 792 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 793 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 793 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 793 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 794 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 794 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 794 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 795 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 795 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 795 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 796 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 796 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 796 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 797 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 797 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 797 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 798 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 798 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 798 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 799 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 799 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 799 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 800 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 800 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 800 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 801 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 801 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 801 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 802 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 802 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 802 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 803 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 803 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 803 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 804 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 804 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 804 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 805 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 805 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 805 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 806 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 806 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 806 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 807 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 807 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 807 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 808 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 808 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 808 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 809 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 809 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 809 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 810 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 810 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 810 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 811 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 811 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 811 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 812 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 812 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 812 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 813 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 813 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 813 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 814 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 814 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 814 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 815 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 815 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 815 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 816 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 816 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 816 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 817 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 817 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 817 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 818 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 818 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 818 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 819 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 819 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 819 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 820 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 820 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 820 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 821 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 821 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 821 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 822 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 822 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 822 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 823 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 823 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 823 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 824 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 824 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 824 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 825 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 825 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 825 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 826 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 826 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 826 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 827 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 827 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 827 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 828 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 828 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 828 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 829 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 829 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 829 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 830 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 830 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 830 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 831 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 831 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 831 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 832 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 832 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 832 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 833 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 833 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 833 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 834 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 834 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 834 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 835 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 835 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 835 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 836 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 836 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 836 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 837 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 837 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 837 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 838 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 838 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 838 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 839 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 839 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 839 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 840 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 840 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 840 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 841 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 841 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 841 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 842 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 842 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 842 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 843 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 843 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 843 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 844 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 844 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 844 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 845 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 845 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 845 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 846 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 846 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 846 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 847 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 847 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 847 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 848 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 848 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 848 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 849 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 849 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 849 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 850 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 850 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 850 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 851 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 851 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 851 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 852 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 852 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 852 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 853 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 853 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 853 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 854 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 854 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 854 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 855 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 855 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 855 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 856 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 856 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 856 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 857 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 857 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 857 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 858 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 858 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 858 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 859 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 859 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 859 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 860 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 860 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 860 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 861 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 861 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 861 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 862 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 862 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 862 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 863 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 863 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 863 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 864 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 864 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 864 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 865 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 865 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 865 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 866 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 866 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 866 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 867 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 867 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 867 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 868 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 868 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 868 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 869 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 869 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 869 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 870 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 870 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 870 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 871 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 871 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 871 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 872 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 872 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 872 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 873 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 873 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 873 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 874 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 874 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 874 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 875 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 875 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 875 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 876 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 876 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 876 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 877 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 877 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 877 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 878 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 878 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 878 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 879 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 879 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 879 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 880 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 880 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 880 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 881 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 881 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 881 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 882 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 882 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 882 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 883 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 883 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 883 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 884 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 884 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 884 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 885 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 885 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 885 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 886 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 886 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 886 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 887 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 887 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 887 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 888 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 888 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 888 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 889 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 889 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 889 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 890 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 890 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 890 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 891 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 891 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 891 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 892 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 892 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 892 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 893 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 893 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 893 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 894 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 894 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 894 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 895 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 895 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 895 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 896 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 896 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 896 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 897 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 897 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 897 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 898 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 898 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 898 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 899 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 899 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 899 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 900 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 900 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 900 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 901 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 901 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 901 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 902 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 902 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 902 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 903 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 903 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 903 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 904 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 904 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 904 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 905 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 905 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 905 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 906 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 906 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 906 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 907 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 907 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 907 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 908 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 908 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 908 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 909 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 909 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 909 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 910 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 910 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 910 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 911 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 911 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 911 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 912 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 912 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 912 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 913 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 913 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 913 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 914 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 914 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 914 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 915 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 915 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 915 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 916 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 916 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 916 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 917 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 917 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 917 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 918 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 918 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 918 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 919 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 919 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 919 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 920 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 920 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 920 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 921 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 921 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 921 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 922 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 922 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 922 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 923 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 923 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 923 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 924 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 924 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 924 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 925 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 925 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 925 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 926 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 926 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 926 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 927 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 927 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 927 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 928 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 928 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 928 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 929 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 929 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 929 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 930 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 930 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 930 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 931 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 931 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 931 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 932 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 932 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 932 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 933 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 933 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 933 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 934 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 934 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 934 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 935 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 935 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 935 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 936 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 936 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 936 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 937 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 937 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 937 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 938 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 938 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 938 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 939 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 939 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 939 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 940 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 940 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 940 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 941 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 941 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 941 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 942 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 942 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 942 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 943 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 943 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 943 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 944 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 944 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 944 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 945 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 945 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 945 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 946 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 946 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 946 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 947 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 947 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 947 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 948 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 948 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 948 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 949 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 949 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 949 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 950 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 950 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 950 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 951 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 951 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 951 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 952 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 952 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 952 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 953 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 953 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 953 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 954 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 954 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 954 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 955 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 955 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 955 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 956 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 956 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 956 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 957 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 957 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 957 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 958 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 958 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 958 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 959 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 959 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 959 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 960 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 960 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 960 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 961 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 961 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 961 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 962 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 962 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 962 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 963 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 963 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 963 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 964 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 964 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 964 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 965 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 965 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 965 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 966 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 966 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 966 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 967 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 967 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 967 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 968 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 968 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 968 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 969 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 969 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 969 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 970 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 970 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 970 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 971 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 971 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 971 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 972 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 972 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 972 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 973 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 973 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 973 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 974 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 974 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 974 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 975 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 975 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 975 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 976 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 976 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 976 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 977 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 977 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 977 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 978 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 978 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 978 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 979 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 979 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 979 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 980 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 980 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 980 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 981 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 981 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 981 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 982 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 982 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 982 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 983 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 983 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 983 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 984 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 984 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 984 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 985 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 985 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 985 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 986 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 986 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 986 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 987 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 987 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 987 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 988 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 988 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 988 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 989 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 989 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 989 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 990 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 990 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 990 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 991 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 991 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 991 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 992 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 992 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 992 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 993 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 993 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 993 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 994 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 994 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 994 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 995 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 995 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 995 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 996 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 996 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 996 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 997 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 997 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 997 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 998 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 998 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 998 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 999 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 999 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 999 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1000 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1000 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1000 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1001 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1001 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1001 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1002 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1002 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1002 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1003 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1003 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1003 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1004 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1004 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1004 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1005 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1005 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1005 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1006 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1006 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1006 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1007 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1007 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1007 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1008 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1008 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1008 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1009 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1009 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1009 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1010 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1010 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1010 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1011 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1011 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1011 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1012 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1012 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1012 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1013 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1013 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1013 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1014 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1014 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1014 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1015 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1015 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1015 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1016 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1016 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1016 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1017 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1017 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1017 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1018 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1018 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1018 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1019 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1019 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1019 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1020 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1020 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1020 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1021 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1021 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1021 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1022 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1022 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1022 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1023 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1023 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1023 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 0 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 0 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 0 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 2 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 2 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 2 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 3 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 3 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 3 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 4 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 4 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 4 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 5 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 5 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 5 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 6 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 6 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 6 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 7 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 7 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 7 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 8 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 8 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 8 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 9 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 9 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 9 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 10 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 10 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 10 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 11 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 11 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 11 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 12 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 12 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 12 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 13 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 13 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 13 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 14 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 14 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 14 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 15 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 15 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 15 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 16 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 16 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 16 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 17 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 17 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 17 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 18 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 18 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 18 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 19 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 19 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 19 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 20 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 20 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 20 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 21 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 21 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 21 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 22 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 22 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 22 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 23 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 23 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 23 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 24 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 24 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 24 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 25 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 25 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 25 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 26 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 26 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 26 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 27 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 27 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 27 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 28 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 28 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 28 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 29 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 29 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 29 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 30 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 30 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 30 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 31 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 31 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 31 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 32 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 32 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 32 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 33 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 33 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 33 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 34 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 34 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 34 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 35 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 35 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 35 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 36 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 36 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 36 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 37 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 37 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 37 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 38 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 38 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 38 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 39 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 39 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 39 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 40 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 40 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 40 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 41 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 41 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 41 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 42 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 42 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 42 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 43 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 43 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 43 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 44 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 44 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 44 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 45 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 45 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 45 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 46 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 46 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 46 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 47 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 47 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 47 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 48 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 48 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 48 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 49 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 49 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 49 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 50 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 50 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 50 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 51 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 51 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 51 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 52 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 52 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 52 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 53 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 53 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 53 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 54 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 54 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 54 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 55 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 55 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 55 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 56 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 56 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 56 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 57 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 57 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 57 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 58 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 58 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 58 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 59 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 59 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 59 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 60 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 60 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 60 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 61 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 61 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 61 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 62 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 62 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 62 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 63 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 63 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 63 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 64 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 64 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 64 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 65 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 65 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 65 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 66 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 66 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 66 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 67 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 67 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 67 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 68 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 68 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 68 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 69 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 69 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 69 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 70 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 70 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 70 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 71 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 71 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 71 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 72 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 72 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 72 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 73 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 73 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 73 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 74 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 74 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 74 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 75 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 75 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 75 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 76 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 76 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 76 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 77 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 77 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 77 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 78 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 78 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 78 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 79 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 79 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 79 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 80 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 80 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 80 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 81 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 81 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 81 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 82 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 82 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 82 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 83 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 83 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 83 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 84 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 84 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 84 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 85 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 85 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 85 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 86 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 86 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 86 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 87 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 87 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 87 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 88 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 88 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 88 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 89 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 89 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 89 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 90 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 90 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 90 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 91 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 91 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 91 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 92 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 92 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 92 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 93 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 93 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 93 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 94 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 94 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 94 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 95 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 95 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 95 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 96 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 96 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 96 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 97 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 97 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 97 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 98 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 98 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 98 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 99 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 99 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 99 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 100 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 100 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 100 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 101 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 101 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 101 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 102 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 102 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 102 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 103 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 103 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 103 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 104 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 104 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 104 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 105 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 105 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 105 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 106 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 106 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 106 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 107 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 107 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 107 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 108 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 108 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 108 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 109 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 109 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 109 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 110 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 110 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 110 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 111 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 111 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 111 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 112 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 112 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 112 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 113 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 113 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 113 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 114 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 114 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 114 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 115 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 115 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 115 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 116 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 116 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 116 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 117 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 117 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 117 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 118 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 118 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 118 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 119 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 119 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 119 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 120 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 120 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 120 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 121 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 121 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 121 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 122 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 122 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 122 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 123 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 123 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 123 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 124 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 124 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 124 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 125 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 125 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 125 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 126 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 126 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 126 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 127 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 127 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 127 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 128 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 128 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 128 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 129 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 129 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 129 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 130 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 130 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 130 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 131 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 131 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 131 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 132 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 132 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 132 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 133 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 133 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 133 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 134 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 134 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 134 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 135 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 135 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 135 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 136 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 136 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 136 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 137 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 137 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 137 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 138 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 138 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 138 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 139 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 139 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 139 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 140 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 140 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 140 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 141 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 141 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 141 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 142 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 142 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 142 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 143 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 143 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 143 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 144 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 144 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 144 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 145 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 145 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 145 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 146 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 146 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 146 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 147 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 147 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 147 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 148 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 148 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 148 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 149 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 149 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 149 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 150 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 150 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 150 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 151 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 151 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 151 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 152 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 152 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 152 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 153 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 153 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 153 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 154 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 154 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 154 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 155 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 155 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 155 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 156 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 156 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 156 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 157 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 157 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 157 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 158 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 158 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 158 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 159 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 159 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 159 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 160 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 160 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 160 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 161 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 161 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 161 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 162 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 162 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 162 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 163 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 163 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 163 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 164 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 164 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 164 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 165 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 165 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 165 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 166 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 166 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 166 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 167 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 167 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 167 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 168 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 168 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 168 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 169 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 169 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 169 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 170 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 170 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 170 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 171 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 171 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 171 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 172 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 172 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 172 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 173 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 173 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 173 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 174 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 174 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 174 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 175 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 175 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 175 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 176 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 176 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 176 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 177 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 177 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 177 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 178 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 178 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 178 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 179 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 179 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 179 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 180 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 180 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 180 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 181 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 181 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 181 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 182 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 182 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 182 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 183 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 183 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 183 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 184 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 184 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 184 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 185 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 185 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 185 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 186 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 186 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 186 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 187 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 187 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 187 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 188 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 188 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 188 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 189 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 189 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 189 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 190 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 190 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 190 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 191 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 191 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 191 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 192 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 192 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 192 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 193 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 193 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 193 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 194 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 194 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 194 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 195 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 195 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 195 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 196 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 196 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 196 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 197 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 197 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 197 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 198 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 198 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 198 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 199 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 199 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 199 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 200 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 200 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 200 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 201 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 201 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 201 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 202 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 202 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 202 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 203 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 203 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 203 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 204 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 204 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 204 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 205 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 205 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 205 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 206 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 206 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 206 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 207 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 207 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 207 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 208 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 208 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 208 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 209 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 209 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 209 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 209 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 210 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 210 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 210 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 210 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 211 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 211 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 211 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 211 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 212 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 212 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 212 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 212 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 213 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 213 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 213 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 213 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 214 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 214 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 214 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 214 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 215 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 215 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 215 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 215 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 216, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 216 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 216 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 216 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 216 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 217 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 217 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 217 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 217 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 218 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 218 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 218 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 218 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 219 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 219 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 219 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 219 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 220 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 220 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 220 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 220 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 221 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 221 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 221 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 221 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 222 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 222 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 222 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 222 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 223 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 223 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 223 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 223 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 224, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 224 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 224 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 224 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 224 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 225 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 225 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 225 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 225 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 226 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 226 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 226 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 226 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 227 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 227 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 227 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 227 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 228 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 228 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 228 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 228 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 229 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 229 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 229 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 229 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 230 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 230 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 230 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 230 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 231 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 231 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 231 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 231 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 232, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 232 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 232 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 232 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 232 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 233 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 233 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 233 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 233 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 234 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 234 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 234 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 234 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 235 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 235 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 235 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 235 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 236 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 236 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 236 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 236 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 237 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 237 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 237 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 237 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 238 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 238 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 238 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 238 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 239 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 239 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 239 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 239 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 240, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 240 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 240 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 240 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 240 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 241 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 241 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 241 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 241 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 242 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 242 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 242 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 242 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 243 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 243 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 243 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 243 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 244 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 244 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 244 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 244 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 245 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 245 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 245 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 245 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 246 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 246 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 246 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 246 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 247 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 247 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 247 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 247 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 248, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 248 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 248 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 248 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 248 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 249 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 249 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 249 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 249 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 250 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 250 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 250 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 250 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 251 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 251 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 251 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 251 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 252 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 252 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 252 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 252 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 253 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 253 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 253 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 253 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 254 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 254 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 254 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 254 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 255 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 255 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 255 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 255 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 256, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 256 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 256 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 256 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 256 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 257 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 257 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 257 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 257 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 258 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 258 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 258 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 258 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 259 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 259 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 259 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 259 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 260 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 260 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 260 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 260 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 261 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 261 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 261 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 261 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 262 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 262 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 262 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 262 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 263 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 263 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 263 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 263 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 264, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 264 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 264 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 264 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 264 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 265 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 265 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 265 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 265 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 266 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 266 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 266 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 266 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 267 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 267 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 267 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 267 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 268 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 268 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 268 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 268 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 269 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 269 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 269 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 269 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 270 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 270 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 270 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 270 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 271 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 271 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 271 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 271 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 272, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 272 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 272 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 272 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 272 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 273 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 273 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 273 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 273 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 274 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 274 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 274 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 274 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 275 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 275 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 275 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 275 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 276 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 276 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 276 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 276 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 277 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 277 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 277 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 277 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 278 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 278 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 278 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 278 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 279 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 279 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 279 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 279 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 280, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 280 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 280 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 280 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 280 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 281 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 281 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 281 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 281 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 282 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 282 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 282 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 282 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 283 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 283 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 283 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 283 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 284 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 284 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 284 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 284 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 285 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 285 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 285 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 285 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 286 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 286 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 286 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 286 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 287 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 287 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 287 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 287 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 288, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 288 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 288 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 288 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 288 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 289 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 289 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 289 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 289 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 290 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 290 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 290 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 290 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 291 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 291 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 291 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 291 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 292 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 292 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 292 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 292 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 293 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 293 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 293 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 293 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 294 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 294 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 294 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 294 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 295 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 295 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 295 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 295 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 296, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 296 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 296 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 296 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 296 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 297 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 297 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 297 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 297 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 298 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 298 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 298 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 298 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 299 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 299 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 299 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 299 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 300 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 300 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 300 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 300 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 301 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 301 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 301 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 301 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 302 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 302 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 302 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 302 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 303 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 303 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 303 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 303 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 304, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 304 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 304 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 304 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 304 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 305 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 305 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 305 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 305 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 306 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 306 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 306 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 306 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 307 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 307 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 307 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 307 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 308 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 308 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 308 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 308 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 309 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 309 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 309 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 309 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 310 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 310 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 310 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 310 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 311 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 311 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 311 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 311 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 312, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 312 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 312 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 312 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 312 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 313 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 313 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 313 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 313 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 314 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 314 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 314 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 314 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 315 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 315 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 315 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 315 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 316 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 316 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 316 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 316 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 317 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 317 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 317 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 317 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 318 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 318 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 318 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 318 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 319 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 319 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 319 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 319 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 320, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 320 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 320 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 320 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 320 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 321 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 321 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 321 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 321 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 322 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 322 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 322 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 322 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 323 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 323 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 323 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 323 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 324 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 324 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 324 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 324 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 325 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 325 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 325 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 325 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 326 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 326 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 326 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 326 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 327 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 327 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 327 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 327 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 328, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 328 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 328 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 328 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 328 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 329 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 329 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 329 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 329 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 330 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 330 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 330 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 330 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 331 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 331 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 331 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 331 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 332 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 332 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 332 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 332 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 333 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 333 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 333 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 333 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 334 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 334 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 334 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 334 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 335 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 335 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 335 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 335 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 336, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 336 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 336 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 336 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 336 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 337 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 337 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 337 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 337 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 338 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 338 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 338 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 338 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 339 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 339 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 339 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 339 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 340 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 340 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 340 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 340 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 341 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 341 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 341 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 341 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 342 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 342 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 342 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 342 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 343 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 343 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 343 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 343 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 344, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 344 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 344 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 344 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 344 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 345 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 345 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 345 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 345 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 346 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 346 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 346 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 346 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 347 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 347 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 347 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 347 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 348 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 348 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 348 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 348 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 349 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 349 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 349 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 349 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 350 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 350 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 350 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 350 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 351 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 351 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 351 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 351 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 352, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 352 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 352 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 352 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 352 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 353 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 353 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 353 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 353 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 354 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 354 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 354 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 354 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 355 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 355 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 355 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 355 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 356 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 356 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 356 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 356 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 357 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 357 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 357 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 357 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 358 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 358 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 358 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 358 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 359 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 359 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 359 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 359 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 360, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 360 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 360 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 360 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 360 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 361 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 361 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 361 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 361 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 362 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 362 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 362 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 362 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 363 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 363 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 363 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 363 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 364 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 364 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 364 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 364 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 365 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 365 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 365 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 365 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 366 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 366 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 366 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 366 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 367 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 367 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 367 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 367 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 368, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 368 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 368 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 368 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 368 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 369 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 369 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 369 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 369 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 370 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 370 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 370 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 370 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 371 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 371 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 371 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 371 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 372 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 372 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 372 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 372 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 373 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 373 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 373 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 373 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 374 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 374 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 374 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 374 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 375 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 375 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 375 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 375 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 376, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 376 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 376 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 376 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 376 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 377 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 377 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 377 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 377 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 378 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 378 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 378 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 378 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 379 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 379 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 379 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 379 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 380 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 380 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 380 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 380 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 381 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 381 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 381 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 381 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 382 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 382 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 382 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 382 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 383 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 383 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 383 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 383 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 384, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 384 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 384 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 384 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 384 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 385 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 385 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 385 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 385 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 386 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 386 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 386 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 386 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 387 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 387 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 387 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 387 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 388 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 388 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 388 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 388 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 389 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 389 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 389 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 389 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 390 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 390 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 390 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 390 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 391 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 391 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 391 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 391 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 392, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 392 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 392 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 392 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 392 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 393 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 393 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 393 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 393 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 394 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 394 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 394 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 394 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 395 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 395 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 395 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 395 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 396 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 396 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 396 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 396 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 397 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 397 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 397 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 397 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 398 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 398 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 398 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 398 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 399 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 399 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 399 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 399 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 400, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 400 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 400 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 400 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 400 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 401 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 401 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 401 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 401 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 402 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 402 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 402 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 402 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 403 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 403 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 403 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 403 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 404 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 404 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 404 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 404 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 405 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 405 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 405 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 405 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 406 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 406 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 406 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 406 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 407 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 407 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 407 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 407 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 408, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 408 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 408 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 408 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 408 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 409 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 409 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 409 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 409 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 410 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 410 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 410 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 410 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 411 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 411 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 411 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 411 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 412 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 412 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 412 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 412 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 413 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 413 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 413 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 413 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 414 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 414 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 414 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 414 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 415 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 415 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 415 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 415 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 416, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 416 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 416 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 416 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 416 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 417 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 417 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 417 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 417 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 418 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 418 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 418 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 418 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 419 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 419 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 419 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 419 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 420 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 420 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 420 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 420 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 421 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 421 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 421 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 421 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 422 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 422 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 422 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 422 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 423 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 423 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 423 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 423 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 424, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 424 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 424 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 424 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 424 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 425 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 425 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 425 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 425 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 426 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 426 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 426 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 426 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 427 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 427 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 427 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 427 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 428 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 428 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 428 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 428 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 429 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 429 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 429 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 429 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 430 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 430 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 430 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 430 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 431 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 431 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 431 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 431 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 432, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 432 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 432 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 432 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 432 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 433 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 433 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 433 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 433 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 434 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 434 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 434 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 434 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 435 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 435 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 435 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 435 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 436 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 436 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 436 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 436 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 437 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 437 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 437 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 437 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 438 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 438 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 438 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 438 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 439 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 439 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 439 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 439 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 440, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 440 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 440 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 440 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 440 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 441 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 441 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 441 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 441 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 442 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 442 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 442 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 442 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 443 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 443 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 443 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 443 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 444 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 444 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 444 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 444 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 445 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 445 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 445 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 445 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 446 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 446 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 446 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 446 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 447 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 447 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 447 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 447 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 448, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 448 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 448 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 448 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 448 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 449 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 449 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 449 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 449 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 450 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 450 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 450 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 450 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 451 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 451 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 451 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 451 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 452 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 452 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 452 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 452 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 453 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 453 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 453 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 453 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 454 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 454 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 454 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 454 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 455 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 455 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 455 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 455 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 456, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 456 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 456 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 456 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 456 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 457 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 457 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 457 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 457 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 458 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 458 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 458 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 458 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 459 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 459 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 459 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 459 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 460 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 460 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 460 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 460 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 461 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 461 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 461 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 461 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 462 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 462 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 462 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 462 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 463 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 463 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 463 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 463 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 464, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 464 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 464 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 464 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 464 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 465 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 465 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 465 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 465 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 466 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 466 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 466 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 466 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 467 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 467 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 467 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 467 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 468 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 468 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 468 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 468 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 469 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 469 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 469 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 469 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 470 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 470 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 470 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 470 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 471 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 471 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 471 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 471 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 472, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 472 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 472 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 472 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 472 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 473 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 473 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 473 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 473 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 474 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 474 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 474 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 474 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 475 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 475 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 475 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 475 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 476 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 476 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 476 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 476 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 477 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 477 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 477 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 477 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 478 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 478 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 478 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 478 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 479 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 479 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 479 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 479 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 480, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 480 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 480 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 480 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 480 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 481 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 481 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 481 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 481 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 482 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 482 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 482 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 482 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 483 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 483 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 483 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 483 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 484 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 484 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 484 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 484 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 485 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 485 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 485 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 485 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 486 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 486 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 486 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 486 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 487 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 487 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 487 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 487 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 488, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 488 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 488 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 488 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 488 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 489 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 489 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 489 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 489 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 490 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 490 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 490 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 490 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 491 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 491 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 491 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 491 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 492 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 492 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 492 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 492 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 493 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 493 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 493 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 493 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 494 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 494 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 494 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 494 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 495 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 495 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 495 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 495 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 496, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 496 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 496 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 496 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 496 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 497 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 497 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 497 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 497 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 498 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 498 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 498 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 498 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 499 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 499 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 499 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 499 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 500 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 500 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 500 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 500 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 501 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 501 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 501 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 501 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 502 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 502 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 502 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 502 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 503 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 503 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 503 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 503 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 504, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 504 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 504 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 504 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 504 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 505 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 505 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 505 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 505 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 506 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 506 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 506 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 506 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 507 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 507 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 507 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 507 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 508 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 508 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 508 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 508 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 509 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 509 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 509 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 509 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 510 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 510 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 510 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 510 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 511 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 511 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 511 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 511 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 512, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 512 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 512 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 512 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 512 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 513 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 513 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 513 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 513 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 514 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 514 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 514 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 514 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 515 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 515 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 515 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 515 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 516 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 516 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 516 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 516 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 517 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 517 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 517 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 517 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 518 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 518 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 518 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 518 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 519 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 519 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 519 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 519 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 520, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 520 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 520 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 520 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 520 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 521 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 521 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 521 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 521 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 522 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 522 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 522 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 522 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 523 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 523 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 523 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 523 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 524 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 524 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 524 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 524 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 525 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 525 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 525 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 525 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 526 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 526 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 526 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 526 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 527 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 527 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 527 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 527 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 528, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 528 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 528 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 528 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 528 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 529 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 529 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 529 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 529 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 530 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 530 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 530 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 530 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 531 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 531 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 531 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 531 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 532 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 532 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 532 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 532 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 533 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 533 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 533 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 533 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 534 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 534 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 534 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 534 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 535 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 535 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 535 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 535 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 536, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 536 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 536 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 536 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 536 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 537 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 537 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 537 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 537 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 538 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 538 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 538 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 538 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 539 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 539 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 539 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 539 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 540 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 540 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 540 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 540 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 541 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 541 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 541 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 541 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 542 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 542 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 542 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 542 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 543 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 543 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 543 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 543 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 544, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 544 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 544 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 544 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 544 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 545 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 545 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 545 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 545 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 546 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 546 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 546 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 546 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 547 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 547 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 547 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 547 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 548 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 548 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 548 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 548 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 549 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 549 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 549 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 549 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 550 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 550 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 550 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 550 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 551 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 551 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 551 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 551 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 552, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 552 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 552 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 552 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 552 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 553 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 553 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 553 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 553 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 554 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 554 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 554 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 554 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 555 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 555 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 555 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 555 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 556 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 556 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 556 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 556 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 557 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 557 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 557 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 557 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 558 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 558 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 558 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 558 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 559 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 559 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 559 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 559 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 560, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 560 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 560 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 560 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 560 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 561 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 561 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 561 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 561 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 562 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 562 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 562 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 562 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 563 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 563 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 563 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 563 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 564 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 564 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 564 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 564 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 565 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 565 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 565 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 565 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 566 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 566 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 566 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 566 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 567 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 567 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 567 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 567 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 568, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 568 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 568 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 568 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 568 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 569 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 569 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 569 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 569 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 570 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 570 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 570 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 570 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 571 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 571 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 571 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 571 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 572 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 572 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 572 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 572 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 573 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 573 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 573 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 573 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 574 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 574 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 574 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 574 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 575 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 575 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 575 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 575 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 576, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 576 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 576 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 576 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 576 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 577 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 577 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 577 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 577 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 578 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 578 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 578 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 578 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 579 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 579 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 579 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 579 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 580 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 580 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 580 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 580 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 581 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 581 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 581 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 581 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 582 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 582 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 582 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 582 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 583 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 583 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 583 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 583 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 584, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 584 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 584 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 584 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 584 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 585 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 585 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 585 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 585 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 586 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 586 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 586 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 586 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 587 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 587 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 587 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 587 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 588 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 588 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 588 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 588 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 589 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 589 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 589 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 589 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 590 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 590 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 590 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 590 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 591 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 591 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 591 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 591 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 592, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 592 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 592 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 592 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 592 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 593 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 593 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 593 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 593 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 594 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 594 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 594 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 594 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 595 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 595 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 595 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 595 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 596 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 596 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 596 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 596 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 597 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 597 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 597 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 597 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 598 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 598 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 598 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 598 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 599 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 599 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 599 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 599 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 600, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 600 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 600 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 600 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 600 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 601 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 601 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 601 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 601 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 602 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 602 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 602 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 602 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 603 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 603 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 603 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 603 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 604 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 604 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 604 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 604 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 605 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 605 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 605 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 605 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 606 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 606 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 606 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 606 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 607 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 607 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 607 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 607 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 608, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 608 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 608 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 608 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 608 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 609 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 609 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 609 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 609 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 610 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 610 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 610 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 610 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 611 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 611 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 611 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 611 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 612 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 612 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 612 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 612 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 613 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 613 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 613 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 613 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 614 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 614 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 614 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 614 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 615 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 615 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 615 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 615 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 616, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 616 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 616 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 616 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 616 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 617 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 617 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 617 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 617 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 618 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 618 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 618 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 618 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 619 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 619 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 619 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 619 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 620 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 620 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 620 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 620 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 621 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 621 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 621 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 621 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 622 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 622 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 622 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 622 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 623 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 623 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 623 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 623 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 624, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 624 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 624 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 624 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 624 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 625 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 625 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 625 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 625 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 626 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 626 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 626 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 626 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 627 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 627 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 627 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 627 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 628 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 628 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 628 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 628 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 629 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 629 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 629 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 629 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 630 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 630 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 630 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 630 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 631 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 631 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 631 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 631 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 632, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 632 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 632 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 632 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 632 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 633 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 633 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 633 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 633 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 634 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 634 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 634 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 634 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 635 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 635 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 635 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 635 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 636 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 636 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 636 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 636 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 637 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 637 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 637 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 637 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 638 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 638 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 638 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 638 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 639 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 639 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 639 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 639 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 640, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 640 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 640 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 640 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 640 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 641 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 641 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 641 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 641 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 642 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 642 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 642 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 642 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 643 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 643 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 643 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 643 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 644 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 644 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 644 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 644 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 645 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 645 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 645 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 645 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 646 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 646 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 646 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 646 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 647 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 647 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 647 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 647 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 648, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 648 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 648 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 648 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 648 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 649 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 649 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 649 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 649 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 650 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 650 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 650 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 650 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 651 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 651 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 651 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 651 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 652 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 652 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 652 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 652 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 653 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 653 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 653 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 653 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 654 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 654 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 654 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 654 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 655 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 655 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 655 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 655 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 656, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 656 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 656 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 656 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 656 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 657 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 657 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 657 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 657 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 658 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 658 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 658 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 658 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 659 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 659 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 659 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 659 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 660 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 660 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 660 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 660 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 661 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 661 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 661 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 661 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 662 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 662 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 662 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 662 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 663 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 663 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 663 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 663 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 664, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 664 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 664 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 664 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 664 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 665 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 665 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 665 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 665 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 666 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 666 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 666 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 666 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 667 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 667 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 667 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 667 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 668 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 668 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 668 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 668 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 669 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 669 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 669 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 669 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 670 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 670 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 670 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 670 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 671 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 671 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 671 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 671 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 672, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 672 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 672 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 672 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 672 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 673 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 673 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 673 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 673 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 674 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 674 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 674 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 674 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 675 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 675 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 675 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 675 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 676 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 676 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 676 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 676 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 677 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 677 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 677 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 677 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 678 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 678 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 678 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 678 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 679 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 679 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 679 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 679 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 680, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 680 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 680 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 680 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 680 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 681 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 681 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 681 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 681 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 682 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 682 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 682 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 682 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 683 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 683 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 683 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 683 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 684 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 684 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 684 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 684 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 685 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 685 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 685 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 685 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 686 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 686 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 686 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 686 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 687 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 687 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 687 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 687 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 688, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 688 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 688 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 688 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 688 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 689 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 689 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 689 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 689 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 690 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 690 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 690 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 690 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 691 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 691 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 691 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 691 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 692 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 692 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 692 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 692 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 693 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 693 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 693 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 693 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 694 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 694 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 694 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 694 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 695 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 695 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 695 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 695 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 696, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 696 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 696 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 696 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 696 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 697 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 697 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 697 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 697 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 698 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 698 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 698 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 698 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 699 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 699 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 699 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 699 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 700 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 700 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 700 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 700 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 701 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 701 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 701 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 701 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 702 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 702 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 702 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 702 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 703 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 703 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 703 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 703 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 704, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 704 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 704 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 704 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 704 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 705 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 705 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 705 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 705 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 706 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 706 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 706 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 706 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 707 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 707 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 707 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 707 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 708 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 708 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 708 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 708 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 709 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 709 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 709 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 709 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 710 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 710 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 710 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 710 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 711 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 711 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 711 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 711 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 712, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 712 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 712 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 712 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 712 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 713 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 713 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 713 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 713 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 714 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 714 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 714 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 714 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 715 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 715 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 715 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 715 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 716 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 716 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 716 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 716 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 717 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 717 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 717 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 717 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 718 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 718 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 718 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 718 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 719 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 719 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 719 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 719 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 720, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 720 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 720 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 720 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 720 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 721 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 721 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 721 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 721 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 722 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 722 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 722 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 722 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 723 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 723 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 723 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 723 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 724 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 724 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 724 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 724 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 725 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 725 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 725 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 725 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 726 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 726 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 726 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 726 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 727 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 727 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 727 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 727 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 728, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 728 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 728 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 728 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 728 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 729 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 729 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 729 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 729 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 730 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 730 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 730 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 730 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 731 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 731 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 731 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 731 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 732 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 732 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 732 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 732 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 733 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 733 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 733 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 733 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 734 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 734 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 734 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 734 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 735 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 735 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 735 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 735 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 736, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 736 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 736 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 736 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 736 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 737 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 737 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 737 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 737 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 738 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 738 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 738 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 738 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 739 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 739 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 739 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 739 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 740 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 740 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 740 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 740 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 741 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 741 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 741 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 741 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 742 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 742 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 742 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 742 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 743 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 743 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 743 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 743 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 744, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 744 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 744 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 744 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 744 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 745 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 745 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 745 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 745 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 746 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 746 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 746 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 746 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 747 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 747 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 747 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 747 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 748 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 748 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 748 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 748 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 749 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 749 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 749 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 749 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 750 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 750 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 750 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 750 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 751 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 751 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 751 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 751 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 752, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 752 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 752 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 752 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 752 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 753 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 753 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 753 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 753 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 754 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 754 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 754 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 754 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 755 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 755 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 755 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 755 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 756 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 756 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 756 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 756 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 757 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 757 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 757 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 757 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 758 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 758 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 758 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 758 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 759 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 759 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 759 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 759 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 760, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 760 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 760 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 760 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 760 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 761 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 761 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 761 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 761 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 762 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 762 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 762 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 762 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 763 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 763 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 763 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 763 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 764 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 764 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 764 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 764 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 765 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 765 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 765 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 765 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 766 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 766 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 766 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 766 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 767 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 767 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 767 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 767 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 768, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 768 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 768 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 768 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 768 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 769 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 769 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 769 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 769 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 770 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 770 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 770 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 770 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 771 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 771 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 771 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 771 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 772 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 772 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 772 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 772 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 773 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 773 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 773 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 773 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 774 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 774 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 774 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 774 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 775 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 775 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 775 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 775 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 776, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 776 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 776 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 776 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 776 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 777 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 777 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 777 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 777 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 778 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 778 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 778 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 778 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 779 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 779 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 779 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 779 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 780 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 780 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 780 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 780 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 781 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 781 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 781 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 781 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 782 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 782 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 782 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 782 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 783 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 783 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 783 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 783 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 784, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 784 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 784 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 784 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 784 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 785 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 785 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 785 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 785 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 786 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 786 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 786 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 786 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 787 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 787 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 787 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 787 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 788 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 788 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 788 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 788 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 789 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 789 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 789 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 789 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 790 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 790 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 790 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 790 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 791 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 791 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 791 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 791 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 792, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 792 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 792 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 792 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 792 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 793 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 793 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 793 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 793 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 794 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 794 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 794 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 794 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 795 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 795 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 795 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 795 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 796 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 796 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 796 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 796 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 797 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 797 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 797 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 797 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 798 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 798 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 798 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 798 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 799 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 799 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 799 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 799 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 800, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 800 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 800 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 800 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 800 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 801 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 801 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 801 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 801 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 802 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 802 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 802 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 802 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 803 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 803 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 803 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 803 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 804 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 804 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 804 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 804 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 805 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 805 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 805 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 805 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 806 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 806 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 806 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 806 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 807 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 807 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 807 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 807 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 808, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 808 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 808 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 808 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 808 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 809 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 809 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 809 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 809 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 810 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 810 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 810 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 810 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 811 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 811 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 811 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 811 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 812 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 812 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 812 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 812 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 813 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 813 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 813 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 813 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 814 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 814 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 814 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 814 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 815 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 815 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 815 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 815 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 816, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 816 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 816 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 816 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 816 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 817 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 817 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 817 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 817 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 818 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 818 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 818 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 818 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 819 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 819 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 819 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 819 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 820 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 820 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 820 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 820 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 821 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 821 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 821 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 821 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 822 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 822 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 822 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 822 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 823 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 823 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 823 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 823 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 824, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 824 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 824 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 824 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 824 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 825 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 825 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 825 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 825 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 826 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 826 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 826 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 826 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 827 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 827 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 827 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 827 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 828 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 828 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 828 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 828 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 829 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 829 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 829 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 829 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 830 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 830 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 830 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 830 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 831 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 831 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 831 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 831 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 832, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 832 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 832 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 832 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 832 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 833 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 833 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 833 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 833 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 834 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 834 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 834 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 834 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 835 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 835 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 835 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 835 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 836 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 836 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 836 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 836 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 837 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 837 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 837 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 837 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 838 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 838 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 838 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 838 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 839 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 839 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 839 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 839 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 840, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 840 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 840 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 840 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 840 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 841 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 841 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 841 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 841 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 842 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 842 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 842 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 842 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 843 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 843 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 843 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 843 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 844 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 844 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 844 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 844 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 845 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 845 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 845 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 845 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 846 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 846 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 846 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 846 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 847 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 847 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 847 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 847 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 848, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 848 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 848 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 848 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 848 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 849 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 849 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 849 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 849 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 850 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 850 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 850 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 850 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 851 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 851 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 851 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 851 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 852 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 852 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 852 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 852 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 853 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 853 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 853 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 853 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 854 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 854 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 854 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 854 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 855 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 855 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 855 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 855 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 856, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 856 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 856 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 856 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 856 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 857 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 857 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 857 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 857 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 858 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 858 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 858 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 858 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 859 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 859 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 859 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 859 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 860 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 860 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 860 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 860 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 861 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 861 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 861 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 861 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 862 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 862 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 862 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 862 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 863 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 863 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 863 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 863 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 864, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 864 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 864 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 864 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 864 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 865 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 865 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 865 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 865 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 866 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 866 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 866 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 866 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 867 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 867 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 867 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 867 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 868 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 868 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 868 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 868 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 869 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 869 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 869 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 869 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 870 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 870 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 870 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 870 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 871 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 871 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 871 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 871 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 872, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 872 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 872 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 872 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 872 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 873 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 873 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 873 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 873 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 874 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 874 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 874 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 874 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 875 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 875 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 875 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 875 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 876 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 876 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 876 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 876 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 877 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 877 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 877 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 877 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 878 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 878 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 878 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 878 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 879 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 879 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 879 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 879 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 880, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 880 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 880 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 880 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 880 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 881 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 881 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 881 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 881 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 882 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 882 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 882 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 882 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 883 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 883 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 883 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 883 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 884 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 884 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 884 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 884 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 885 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 885 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 885 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 885 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 886 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 886 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 886 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 886 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 887 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 887 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 887 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 887 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 888, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 888 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 888 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 888 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 888 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 889 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 889 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 889 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 889 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 890 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 890 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 890 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 890 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 891 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 891 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 891 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 891 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 892 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 892 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 892 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 892 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 893 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 893 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 893 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 893 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 894 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 894 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 894 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 894 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 895 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 895 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 895 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 895 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 896, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 896 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 896 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 896 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 896 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 897 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 897 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 897 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 897 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 898 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 898 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 898 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 898 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 899 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 899 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 899 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 899 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 900 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 900 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 900 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 900 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 901 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 901 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 901 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 901 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 902 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 902 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 902 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 902 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 903 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 903 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 903 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 903 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 904, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 904 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 904 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 904 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 904 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 905 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 905 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 905 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 905 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 906 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 906 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 906 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 906 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 907 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 907 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 907 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 907 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 908 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 908 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 908 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 908 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 909 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 909 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 909 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 909 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 910 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 910 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 910 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 910 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 911 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 911 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 911 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 911 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 912, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 912 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 912 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 912 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 912 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 913 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 913 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 913 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 913 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 914 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 914 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 914 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 914 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 915 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 915 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 915 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 915 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 916 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 916 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 916 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 916 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 917 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 917 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 917 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 917 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 918 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 918 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 918 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 918 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 919 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 919 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 919 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 919 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 920, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 920 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 920 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 920 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 920 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 921 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 921 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 921 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 921 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 922 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 922 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 922 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 922 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 923 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 923 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 923 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 923 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 924 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 924 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 924 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 924 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 925 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 925 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 925 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 925 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 926 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 926 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 926 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 926 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 927 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 927 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 927 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 927 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 928, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 928 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 928 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 928 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 928 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 929 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 929 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 929 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 929 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 930 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 930 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 930 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 930 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 931 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 931 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 931 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 931 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 932 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 932 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 932 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 932 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 933 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 933 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 933 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 933 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 934 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 934 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 934 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 934 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 935 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 935 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 935 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 935 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 936, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 936 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 936 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 936 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 936 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 937 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 937 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 937 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 937 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 938 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 938 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 938 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 938 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 939 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 939 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 939 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 939 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 940 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 940 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 940 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 940 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 941 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 941 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 941 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 941 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 942 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 942 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 942 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 942 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 943 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 943 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 943 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 943 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 944, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 944 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 944 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 944 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 944 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 945 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 945 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 945 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 945 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 946 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 946 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 946 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 946 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 947 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 947 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 947 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 947 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 948 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 948 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 948 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 948 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 949 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 949 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 949 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 949 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 950 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 950 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 950 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 950 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 951 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 951 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 951 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 951 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 952, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 952 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 952 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 952 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 952 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 953 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 953 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 953 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 953 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 954 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 954 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 954 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 954 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 955 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 955 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 955 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 955 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 956 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 956 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 956 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 956 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 957 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 957 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 957 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 957 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 958 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 958 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 958 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 958 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 959 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 959 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 959 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 959 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 960, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 960 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 960 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 960 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 960 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 961 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 961 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 961 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 961 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 962 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 962 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 962 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 962 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 963 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 963 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 963 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 963 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 964 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 964 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 964 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 964 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 965 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 965 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 965 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 965 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 966 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 966 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 966 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 966 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 967 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 967 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 967 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 967 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 968, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 968 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 968 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 968 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 968 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 969 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 969 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 969 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 969 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 970 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 970 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 970 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 970 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 971 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 971 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 971 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 971 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 972 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 972 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 972 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 972 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 973 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 973 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 973 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 973 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 974 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 974 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 974 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 974 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 975 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 975 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 975 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 975 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 976, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 976 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 976 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 976 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 976 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 977 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 977 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 977 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 977 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 978 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 978 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 978 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 978 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 979 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 979 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 979 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 979 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 980 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 980 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 980 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 980 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 981 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 981 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 981 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 981 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 982 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 982 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 982 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 982 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 983 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 983 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 983 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 983 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 984, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 984 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 984 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 984 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 984 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 985 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 985 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 985 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 985 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 986 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 986 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 986 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 986 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 987 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 987 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 987 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 987 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 988 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 988 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 988 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 988 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 989 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 989 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 989 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 989 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 990 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 990 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 990 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 990 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 991 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 991 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 991 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 991 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 992, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 992 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 992 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 992 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 992 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 993 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 993 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 993 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 993 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 994 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 994 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 994 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 994 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 995 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 995 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 995 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 995 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 996 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 996 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 996 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 996 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 997 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 997 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 997 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 997 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 998 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 998 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 998 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 998 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 999 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 999 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 999 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 999 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 1000, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1000 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1000 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1000 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1000 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1001 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1001 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1001 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1001 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1002 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1002 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1002 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1002 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1003 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1003 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1003 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1003 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1004 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1004 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1004 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1004 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1005 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1005 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1005 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1005 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1006 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1006 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1006 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1006 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1007 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1007 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1007 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1007 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 1008, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1008 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1008 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1008 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1008 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1009 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1009 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1009 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1009 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1010 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1010 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1010 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1010 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1011 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1011 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1011 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1011 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1012 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1012 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1012 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1012 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1013 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1013 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1013 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1013 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1014 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1014 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1014 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1014 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1015 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1015 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1015 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1015 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 1016, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1016 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1016 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1016 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1016 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1017 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1017 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1017 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1017 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1018 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1018 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1018 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1018 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1019 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1019 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1019 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1019 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1020 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1020 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1020 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1020 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1021 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1021 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1021 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1021 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1022 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1022 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1022 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1022 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1023 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1023 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 1023 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 1023 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 0, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 0 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 0 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 0 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 0 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 0 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 1 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 1 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 1 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 1 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 2 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 2 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 2 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 2 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 3 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 3 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 3 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 3 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 4 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 4 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 4 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 4 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 5 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 5 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 5 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 5 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 6 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 6 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 6 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 6 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 7 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 7 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 7 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 7 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 8, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 8 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 8 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 8 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 8 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 8 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 9 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 9 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 9 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 9 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 10 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 10 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 10 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 10 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 11 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 11 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 11 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 11 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 12 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 12 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 12 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 12 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 13 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 13 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 13 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 13 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 14 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 14 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 14 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 14 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 15 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 15 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 15 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 15 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 16, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 16 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 16 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 16 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 16 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 16 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 17 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 17 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 17 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 17 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 18 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 18 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 18 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 18 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 19 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 19 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 19 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 19 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 20 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 20 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 20 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 20 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 21 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 21 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 21 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 21 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 22 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 22 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 22 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 22 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 23 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 23 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 23 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 23 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 24, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 24 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 24 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 24 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 24 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 24 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 25 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 25 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 25 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 25 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 26 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 26 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 26 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 26 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 27 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 27 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 27 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 27 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 28 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 28 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 28 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 28 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 29 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 29 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 29 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 29 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 30 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 30 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 30 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 30 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 31 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 31 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 31 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 31 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 32, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 32 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 32 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 32 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 32 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 32 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 33 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 33 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 33 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 33 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 34 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 34 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 34 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 34 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 35 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 35 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 35 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 35 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 36 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 36 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 36 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 36 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 37 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 37 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 37 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 37 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 38 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 38 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 38 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 38 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 39 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 39 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 39 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 39 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 40, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 40 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 40 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 40 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 40 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 40 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 41 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 41 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 41 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 41 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 42 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 42 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 42 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 42 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 43 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 43 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 43 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 43 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 44 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 44 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 44 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 44 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 45 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 45 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 45 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 45 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 46 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 46 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 46 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 46 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 47 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 47 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 47 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 47 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 48, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 48 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 48 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 48 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 48 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 48 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 49 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 49 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 49 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 49 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 50 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 50 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 50 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 50 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 51 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 51 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 51 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 51 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 52 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 52 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 52 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 52 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 53 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 53 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 53 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 53 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 54 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 54 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 54 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 54 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 55 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 55 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 55 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 55 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 56, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 56 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 56 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 56 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 56 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 56 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 57 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 57 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 57 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 57 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 58 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 58 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 58 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 58 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 59 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 59 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 59 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 59 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 60 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 60 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 60 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 60 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 61 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 61 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 61 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 61 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 62 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 62 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 62 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 62 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 63 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 63 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 63 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 63 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 64, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 64 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 64 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 64 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 64 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 64 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 65 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 65 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 65 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 65 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 66 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 66 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 66 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 66 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 67 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 67 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 67 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 67 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 68 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 68 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 68 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 68 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 69 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 69 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 69 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 69 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 70 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 70 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 70 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 70 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 71 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 71 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 71 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 71 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 72, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] [gNB 0] Frame 72 : MIB->BCH CC_id 0, Received 3 bytes
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 72 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 72 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 72 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 72 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 73 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 73 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 73 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 73 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 74 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 74 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 74 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 74 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 75 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 75 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 75 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 75 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 76 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 76 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 76 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 76 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 77 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 77 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 77 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 77 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 78 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 78 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 78 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 78 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 79 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 79 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 79 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 79 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 80, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 80 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 80 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 80 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 80 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 81 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 81 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 81 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 81 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 82 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 82 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 82 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 82 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 83 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 83 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 83 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 83 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 84 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 84 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 84 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 84 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 85 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 85 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 85 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 85 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 86 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 86 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 86 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 86 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 87 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 87 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 87 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 87 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 88, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 88 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 88 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 88 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 88 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 89 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 89 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 89 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 89 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 90 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 90 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 90 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 90 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 91 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 91 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 91 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 91 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 92 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 92 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 92 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 92 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 93 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 93 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 93 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 93 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 94 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 94 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 94 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 94 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 95 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 95 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 95 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 95 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 96, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 96 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 96 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 96 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 96 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 97 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 97 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 97 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 97 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 98 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 98 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 98 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 98 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 99 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 99 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 99 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 99 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 100 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 100 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 100 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 100 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 101 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 101 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 101 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 101 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 102 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 102 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 102 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 102 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 103 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 103 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 103 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 103 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 104, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 104 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 104 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 104 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 104 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 105 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 105 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 105 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 105 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 106 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 106 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 106 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 106 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 107 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 107 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 107 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 107 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 108 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 108 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 108 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 108 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 109 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 109 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 109 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 109 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 110 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 110 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 110 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 110 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 111 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 111 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 111 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 111 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 112, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 112 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 112 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 112 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 112 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 113 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 113 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 113 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 113 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 114 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 114 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 114 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 114 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 115 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 115 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 115 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 115 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 116 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 116 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 116 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 116 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 117 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 117 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 117 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 117 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 118 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 118 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 118 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 118 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 119 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 119 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 119 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 119 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 120, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 120 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 120 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 120 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 120 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 121 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 121 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 121 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 121 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 122 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 122 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 122 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 122 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 123 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 123 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 123 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 123 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 124 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 124 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 124 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 124 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 125 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 125 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 125 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 125 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 126 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 126 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 126 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 126 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 127 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 127 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 127 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 127 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 128, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 128 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 128 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 128 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 128 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 129 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 129 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 129 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 129 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 130 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 130 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 130 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 130 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 131 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 131 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 131 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 131 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 132 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 132 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 132 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 132 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 133 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 133 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 133 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 133 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 134 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 134 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 134 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 134 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 135 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 135 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 135 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 135 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 136, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 136 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 136 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 136 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 136 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 137 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 137 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 137 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 137 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 138 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 138 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 138 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 138 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 139 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 139 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 139 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 139 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 140 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 140 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 140 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 140 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 141 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 141 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 141 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 141 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 142 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 142 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 142 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 142 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 143 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 143 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 143 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 143 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 144, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 144 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 144 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 144 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 144 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 145 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 145 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 145 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 145 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 146 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 146 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 146 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 146 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 147 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 147 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 147 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 147 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 148 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 148 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 148 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 148 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 149 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 149 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 149 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 149 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 150 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 150 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 150 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 150 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 151 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 151 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 151 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 151 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 152, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 152 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 152 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 152 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 152 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 153 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 153 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 153 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 153 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 154 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 154 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 154 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 154 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 155 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 155 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 155 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 155 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 156 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 156 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 156 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 156 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 157 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 157 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 157 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 157 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 158 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 158 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 158 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 158 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 159 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 159 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 159 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 159 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 160, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 160 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 160 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 160 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 160 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 161 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 161 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 161 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 161 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 162 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 162 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 162 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 162 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 163 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 163 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 163 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 163 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 164 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 164 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 164 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 164 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 165 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 165 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 165 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 165 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 166 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 166 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 166 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 166 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 167 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 167 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 167 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 167 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 168, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 168 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 168 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 168 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 168 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 169 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 169 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 169 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 169 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 170 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 170 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 170 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 170 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 171 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 171 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 171 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 171 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 172 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 172 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 172 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 172 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 173 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 173 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 173 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 173 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 174 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 174 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 174 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 174 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 175 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 175 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 175 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 175 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 176, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 176 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 176 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 176 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 176 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 177 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 177 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 177 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 177 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 178 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 178 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 178 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 178 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 179 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 179 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 179 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 179 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 180 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 180 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 180 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 180 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 181 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 181 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 181 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 181 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 182 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 182 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 182 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 182 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 183 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 183 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 183 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 183 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Frame 184, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 184 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 184 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 184 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 184 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 185 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 185 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 185 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 185 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 186 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 186 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 186 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 186 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 187 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 187 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 187 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 187 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 188 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 188 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 188 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 188 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 189 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 189 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 189 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 189 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 190 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 190 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 190 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 190 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 191 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 191 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 191 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 191 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Frame 192, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 192 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 192 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 192 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 192 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 193 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 193 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 193 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 193 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 194 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 194 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 194 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 194 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 195 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 195 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 195 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 195 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 196 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 196 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 196 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 196 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 197 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 197 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 197 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 197 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 198 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 198 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 198 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 198 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 199 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 199 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 199 slot 8
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 199 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Frame 200, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 200 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 200 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 200 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 200 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 201 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 201 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 201 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 201 slot 9
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 202 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 202 slot 7
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 202 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 202 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 203 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 203 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 203 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 203 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 204 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 204 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 204 slot 8
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] Scheduling pucch reception for frame 204 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 205 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 205 slot 7
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Scheduling pucch reception for frame 205 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 205 slot 9
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 206 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 2
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 206 slot 7
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 206 slot 8
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 206 slot 9
+[0mPUCCH 0 : maxpos 0
+[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 2
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 3
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 4
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 0
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 5
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 207 slot 6
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 0 rv 3
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[MAC] Scheduling pucch reception for frame 207 slot 7
+[0mPUCCH 0 : maxpos 1
+[0m[MAC] Scheduling pucch reception for frame 207 slot 8
+[0mPUCCH 0 : maxpos 2
+[0m[MAC] Scheduling pucch reception for frame 207 slot 9
+[0mPUCCH 0 : maxpos 3
+[0m[MAC] Frame 208, slot 0: Adding BCH PDU in position 0 (length 3)
+[0m[0m[MAC] In nr_schedule_uss_dlsch_phytest frame 208 slot 1
+[0m[0m[MAC] [gNB scheduler phytest] DCI type 1 payload: freq_alloc 211 (0,106,106), time_alloc 2, vrb to prb 0, mcs 9 tb_scaling 0 ndi 1 rv 1
+[0m[0m[SCTP] Found data for descriptor 87
+[0m[0m[MAC] DLSCH PDU: start PRB 0 n_PRB 106 startSymbolAndLength 54 start symbol 1 nb_symbols 12 nb_layers 1 nb_codewords 1 mcs 9 TBS: 2433
+[0m[0m[SCTP] Received notification for sd 87, type 32773
+[0mhere comes the tree (instance 0):
+---------------------------------------------
+-----------------------
+eNB id 3585 (null)
+state 1
+nextstream 0
+in_streams 32 out_streams 32
+cnx_id 1 assoc_id 136
+---------------------------------------------
+[0m[1;31m[X2AP] x2ap_enb_data_p not NULL and sctp state not SCTP_STATE_ESTABLISHED, what to do?
+[0mLinux signal Aborted...
+/home/eurecom/panos/NR_RRC_harq_hacks/openairinterface5g/executables/softmodem-common.c:187 signal_handler() Exiting OAI softmodem: softmodem starting exit procedure
+
+Exiting ru_thread
diff --git a/executables/main-fs6.c b/executables/main-fs6.c
index 45a627188771b87e8691a0b4d92d3e3322c8bbc6..c4a0d85b347f17d8754f262adf39f1f4359961e2 100644
--- a/executables/main-fs6.c
+++ b/executables/main-fs6.c
@@ -401,7 +401,7 @@ void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_
hULUE(newUDPheader)->O_ACK=eNB->ulsch[UE_id]->harq_processes[harq_pid]->O_ACK;
memcpy(hULUE(newUDPheader)->o_ACK, eNB->ulsch[UE_id]->harq_processes[harq_pid]->o_ACK,
sizeof(eNB->ulsch[UE_id]->harq_processes[harq_pid]->o_ACK));
- hULUE(newUDPheader)->ta=lte_est_timing_advance_pusch(eNB, UE_id);
+ hULUE(newUDPheader)->ta=lte_est_timing_advance_pusch(&eNB->frame_parms, eNB->pusch_vars[UE_id]->drs_ch_estimates_time);
hULUE(newUDPheader)->segment=segmentID;
memcpy(hULUE(newUDPheader)->o, eNB->ulsch[UE_id]->harq_processes[harq_pid]->o,
sizeof(eNB->ulsch[UE_id]->harq_processes[harq_pid]->o));
@@ -917,7 +917,7 @@ void phy_procedures_eNB_TX_fromsplit(uint8_t *bufferZone, int nbBlocks, PHY_VARS
if (NFAPI_MODE==NFAPI_MONOLITHIC || NFAPI_MODE==NFAPI_MODE_PNF) {
if (is_pmch_subframe(frame,subframe,fp)) {
- pmch_procedures(eNB,proc);
+ pmch_procedures(eNB,proc,0);
} else {
// this is not a pmch subframe, so generate PSS/SSS/PBCH
common_signal_procedures(eNB,frame, subframe);
@@ -1194,6 +1194,8 @@ void phy_procedures_eNB_TX_tosplit(uint8_t *bufferZone, PHY_VARS_eNB *eNB, L1_rx
for (int i=0; i<NUMBER_OF_UE_MAX; i++) {
int harq_pid;
LTE_eNB_ULSCH_t *ulsch = eNB->ulsch[i];
+ if (ulsch == NULL)
+ continue;
if (ulsch->ue_type > NOCE)
harq_pid = 0;
@@ -1209,9 +1211,10 @@ void phy_procedures_eNB_TX_tosplit(uint8_t *bufferZone, PHY_VARS_eNB *eNB, L1_rx
for (int k=0; k<8; k++) {
ulsch_harq = ulsch->harq_processes[k];
+ if (ulsch_harq == NULL)
+ continue;
- if (ulsch &&
- (ulsch->rnti>0) &&
+ if ((ulsch->rnti>0) &&
(ulsch_harq->status == ACTIVE) &&
(ulsch_harq->frame == frame) &&
(ulsch_harq->subframe == subframe) &&
@@ -1510,6 +1513,7 @@ void *cu_fs6(void *arg) {
char remoteIP[1024];
strncpy(remoteIP,get_softmodem_params()->split73+3, 1023); //three first char should be cu: or du:
char port_def[256]=DU_PORT;
+
for (int i=0; i <1000; i++)
if (remoteIP[i]==':') {
strncpy(port_def,remoteIP+i+1,255);
@@ -1558,12 +1562,14 @@ void *du_fs6(void *arg) {
char remoteIP[1024];
strncpy(remoteIP,get_softmodem_params()->split73+3,1023); //three first char should be cu: or du:
char port_def[256]=CU_PORT;
+
for (int i=0; i <1000; i++)
if (remoteIP[i]==':') {
strncpy(port_def,remoteIP+i+1,255);
remoteIP[i]=0;
break;
}
+
AssertFatal(createUDPsock(NULL, DU_PORT, remoteIP, port_def, &sockFS6), "");
if (ru->rfdevice.trx_start_func(&ru->rfdevice) != 0)
diff --git a/executables/main-ocp.c b/executables/main-ocp.c
index d2ee9418dcaa2efb4059324a1e177d25f27967fe..cd221b155a29fe904cbfe35d7f21872cd6756c91 100644
--- a/executables/main-ocp.c
+++ b/executables/main-ocp.c
@@ -80,6 +80,7 @@ int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
int split73;
char * split73_config;
int split73;
+int usrp_tx_thread = 0;
static void *ru_thread( void *param );
void kill_RU_proc(RU_t *ru) {
@@ -1122,9 +1123,6 @@ int restart_L1L2(module_id_t enb_id) {
sync_var = -1;
pthread_mutex_unlock(&sync_mutex);
RC.ru_mask |= (1 << ru->idx);
- /* copy the changed frame parameters to the RU */
- /* TODO this should be done for all RUs associated to this eNB */
- memcpy(&ru->frame_parms, &RC.eNB[enb_id][0]->frame_parms, sizeof(LTE_DL_FRAME_PARMS));
/* reset the list of connected UEs in the MAC, since in this process with
* loose all UEs (have to reconnect) */
init_UE_info(&RC.mac[enb_id]->UE_info);
@@ -1152,6 +1150,7 @@ int restart_L1L2(module_id_t enb_id) {
}
int main ( int argc, char **argv ) {
+ //mtrace();
int i;
int CC_id = 0;
int node_type = ngran_eNB;
@@ -1165,6 +1164,7 @@ int main ( int argc, char **argv ) {
T_Config_Init();
#endif
configure_linux();
+ set_softmodem_sighandler();
cpuf=get_cpu_freq_GHz();
set_taus_seed (0);
@@ -1345,7 +1345,7 @@ int main ( int argc, char **argv ) {
// end of CI modifications
//getchar();
if(IS_SOFTMODEM_DOFORMS)
- load_softscope("enb");
+ load_softscope("enb", NULL);
itti_wait_tasks_end();
oai_exit=1;
diff --git a/executables/nr-gnb.c b/executables/nr-gnb.c
index 9003f6835778ce51024d387ac2cfef93f86d7362..27b0ed08ddbde4c335b8d670aaa98ec95f89f031 100644
--- a/executables/nr-gnb.c
+++ b/executables/nr-gnb.c
@@ -47,7 +47,7 @@
#include "SCHED/sched_eNB.h"
#include "SCHED_NR/sched_nr.h"
#include "SCHED_NR/fapi_nr_l1.h"
-#include "PHY/LTE_TRANSPORT/transport_proto.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#undef MALLOC //there are two conflicting definitions, so we better make sure we don't use it at all
//#undef FRAME_LENGTH_COMPLEX_SAMPLES //there are two conflicting definitions, so we better make sure we don't use it at all
@@ -61,7 +61,6 @@
#include "PHY/phy_extern.h"
-
#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
#include "RRC/LTE/rrc_extern.h"
#include "PHY_INTERFACE/phy_interface.h"
@@ -162,14 +161,14 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t
/*if (gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus||
gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs ||
gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs ||
- gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles ||
+ gNB->UL_INFO.rach_ind.number_of_pdus ||
gNB->UL_INFO.cqi_ind.number_of_cqis
) {
- LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d preambles:%05d:%d cqis:%d] RX:%04d%d TX:%04d%d \n",
+ LOG_D(PHY, "UL_info[rx_ind:%05d:%d harqs:%05d:%d crcs:%05d:%d rach_pdus:%0d.%d:%d cqis:%d] RX:%04d%d TX:%04d%d \n",
NFAPI_SFNSF2DEC(gNB->UL_INFO.rx_ind.sfn_sf), gNB->UL_INFO.rx_ind.rx_indication_body.number_of_pdus,
NFAPI_SFNSF2DEC(gNB->UL_INFO.harq_ind.sfn_sf), gNB->UL_INFO.harq_ind.harq_indication_body.number_of_harqs,
NFAPI_SFNSF2DEC(gNB->UL_INFO.crc_ind.sfn_sf), gNB->UL_INFO.crc_ind.crc_indication_body.number_of_crcs,
- NFAPI_SFNSF2DEC(gNB->UL_INFO.rach_ind.sfn_sf), gNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles,
+ gNB->UL_INFO.rach_ind.sfn, gNB->UL_INFO.rach_ind.slot,gNB->UL_INFO.rach_ind.number_of_pdus,
gNB->UL_INFO.cqi_ind.number_of_cqis,
frame_rx, slot_rx,
frame_tx, slot_tx);
@@ -202,6 +201,13 @@ static inline int rxtx(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int frame_t
if (rx_slot_type == NR_UPLINK_SLOT || rx_slot_type == NR_MIXED_SLOT) {
// UE-specific RX processing for subframe n
// TODO: check if this is correct for PARALLEL_RU_L1_TRX_SPLIT
+
+ // Do PRACH RU processing
+ int prach_id=find_nr_prach(gNB,frame_rx,slot_rx,0,SEARCH_EXIST);
+ if (prach_id>=0) {
+ L1_nr_prach_procedures(gNB,frame_rx,slot_rx,&gNB->prach_vars.list[prach_id].pdu);
+ gNB->prach_vars.list[prach_id].frame=-1;
+ }
phy_procedures_gNB_uespec_RX(gNB, frame_rx, slot_rx);
}
@@ -734,9 +740,7 @@ void init_gNB_proc(int inst) {
gNB_L1_rxtx_proc_t *L1_proc,*L1_proc_tx;
// LOG_I(PHY,"%s(inst:%d) RC.nb_nr_CC[inst]:%d \n",__FUNCTION__,inst,RC.nb_nr_CC[inst]);
gNB = RC.gNB[inst];
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing gNB processes instance:%d CC_id %d \n",inst,CC_id);
-#endif
proc = &gNB->proc;
L1_proc = &proc->L1_proc;
@@ -950,9 +954,7 @@ void init_gNB(int single_thread_flag,int wait_for_sync) {
NR_POLAR_PBCH_PAYLOAD_BITS,
NR_POLAR_PBCH_AGGREGATION_LEVEL);*/
LOG_I(PHY,"Initializing gNB %d single_thread_flag:%d\n",inst,gNB->single_thread_flag);
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing gNB %d\n",inst);
-#endif
LOG_I(PHY,"Registering with MAC interface module (before %p)\n",gNB->if_inst);
AssertFatal((gNB->if_inst = NR_IF_Module_init(inst))!=NULL,"Cannot register interface");
@@ -961,12 +963,14 @@ void init_gNB(int single_thread_flag,int wait_for_sync) {
gNB->if_inst->NR_PHY_config_req = nr_phy_config_request;
memset((void *)&gNB->UL_INFO,0,sizeof(gNB->UL_INFO));
LOG_I(PHY,"Setting indication lists\n");
+
gNB->UL_INFO.rx_ind.pdu_list = gNB->rx_pdu_list;
gNB->UL_INFO.crc_ind.crc_list = gNB->crc_pdu_list;
/*gNB->UL_INFO.sr_ind.sr_indication_body.sr_pdu_list = gNB->sr_pdu_list;
gNB->UL_INFO.harq_ind.harq_indication_body.harq_pdu_list = gNB->harq_pdu_list;
gNB->UL_INFO.cqi_ind.cqi_pdu_list = gNB->cqi_pdu_list;
gNB->UL_INFO.cqi_ind.cqi_raw_pdu_list = gNB->cqi_raw_pdu_list;*/
+
gNB->prach_energy_counter = 0;
}
diff --git a/executables/nr-ru.c b/executables/nr-ru.c
index f947395f4a077708c5bf61c029401235f8409762..969ad21b8eecad6ab51b79efbd7dc47c5d145580 100644
--- a/executables/nr-ru.c
+++ b/executables/nr-ru.c
@@ -51,6 +51,7 @@
#include "PHY/defs_nr_common.h"
#include "PHY/phy_extern.h"
#include "PHY/LTE_TRANSPORT/transport_proto.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/INIT/phy_init.h"
#include "SCHED/sched_eNB.h"
#include "SCHED_NR/sched_nr.h"
@@ -117,6 +118,7 @@ uint16_t sl_ahead;
extern int emulate_rf;
extern int numerology;
+extern int usrp_tx_thread;
/*************************************************************/
/* Functions to attach and configure RRU */
@@ -289,7 +291,7 @@ void fh_if5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp)
// southbound IF4p5 fronthaul
void fh_if4p5_south_out(RU_t *ru, int frame, int slot, uint64_t timestamp)
{
- nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
if (ru == RC.ru[0]) VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TRX_TST, ru->proc.timestamp_tx&0xffffffff );
LOG_D(PHY,"Sending IF4p5 for frame %d subframe %d\n",ru->proc.frame_tx,ru->proc.tti_tx);
@@ -500,7 +502,7 @@ void fh_if5_north_asynch_in(RU_t *ru,int *frame,int *slot) {
void fh_if4p5_north_asynch_in(RU_t *ru,int *frame,int *slot) {
NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms;
- nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
RU_proc_t *proc = &ru->proc;
uint16_t packet_type;
uint32_t symbol_number,symbol_mask,symbol_mask_full=0;
@@ -697,7 +699,7 @@ void rx_rf(RU_t *ru,int *frame,int *slot) {
void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
RU_proc_t *proc = &ru->proc;
NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms;
- nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
void *txp[ru->nb_tx];
unsigned int txs;
int i,txsymb;
@@ -770,10 +772,10 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
siglen+sf_extension,
ru->nb_tx,
flags);
- LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %d\n",ru->idx,
- (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot);
+ LOG_D(PHY,"[TXPATH] RU %d tx_rf, writing to TS %llu, frame %d, unwrapped_frame %d, slot %di, returned %d\n",ru->idx,
+ (long long unsigned int)timestamp,frame,proc->frame_tx_unwrap,slot, txs);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0 );
- AssertFatal(txs == siglen+sf_extension,"TX : Timeout (sent %u/%d)\n", txs, siglen);
+ //AssertFatal(txs == 0,"trx write function error %d\n", txs);
}
}
@@ -789,7 +791,7 @@ void *ru_thread_asynch_rxtx( void *param ) {
static int ru_thread_asynch_rxtx_status;
RU_t *ru = (RU_t *)param;
RU_proc_t *proc = &ru->proc;
- nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
int slot=0, frame=0;
// wait for top-level synchronization and do one acquisition to get timestamp for setting frame/subframe
wait_sync("ru_thread_asynch_rxtx");
@@ -1034,10 +1036,10 @@ int wakeup_prach_ru(RU_t *ru) {
void fill_rf_config(RU_t *ru, char *rf_config_file) {
int i;
NR_DL_FRAME_PARMS *fp = ru->nr_frame_parms;
- nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config; //tmp index
+ nfapi_nr_config_request_scf_t *config = &ru->config; //tmp index
openair0_config_t *cfg = &ru->openair0_cfg;
- int mu = gNB_config->ssb_config.scs_common.value;
- int N_RB = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value;
+ int mu = config->ssb_config.scs_common.value;
+ int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value;
if (mu == NR_MU_0) { //or if LTE
if(N_RB == 100) {
@@ -1122,7 +1124,7 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) {
AssertFatal(0 == 1,"Numerology %d not supported for the moment\n",mu);
}
- if (gNB_config->cell_config.frame_duplex_type.value==TDD)
+ if (config->cell_config.frame_duplex_type.value==TDD)
cfg->duplex_mode = duplex_mode_TDD;
else //FDD
cfg->duplex_mode = duplex_mode_FDD;
@@ -1161,7 +1163,7 @@ int setup_RU_buffers(RU_t *ru) {
int card,ant;
//uint16_t N_TA_offset = 0;
NR_DL_FRAME_PARMS *frame_parms;
- //nfapi_nr_config_request_t *gNB_config = ru->gNB_list[0]->gNB_config; //tmp index
+ nfapi_nr_config_request_scf_t *config = &ru->config;
if (ru) {
frame_parms = ru->nr_frame_parms;
@@ -1170,12 +1172,54 @@ int setup_RU_buffers(RU_t *ru) {
printf("ru pointer is NULL\n");
return(-1);
}
+ int mu = config->ssb_config.scs_common.value;
+ int N_RB = config->carrier_config.dl_grid_size[config->ssb_config.scs_common.value].value;
- /* if (frame_parms->frame_type == TDD) {
- if (frame_parms->N_RB_DL == 100) ru->N_TA_offset = 624;
- else if (frame_parms->N_RB_DL == 50) ru->N_TA_offset = 624/2;
- else if (frame_parms->N_RB_DL == 25) ru->N_TA_offset = 624/4;
- } */
+
+ if (config->cell_config.frame_duplex_type.value == TDD) {
+ int N_TA_offset = config->carrier_config.uplink_frequency.value < 6000000 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2
+
+ double factor=1;
+
+ switch (mu) {
+ case 0: //15 kHz scs
+ AssertFatal(N_TA_offset == 400,"scs_common 15kHz only for FR1\n");
+ if (N_RB <= 25) factor = .25; // 7.68 Ms/s
+ else if (N_RB <=50) factor = .5; // 15.36 Ms/s
+ else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s
+ else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s
+ else AssertFatal(1==0,"Too many PRBS for mu=0\n");
+ break;
+ case 1: //30 kHz sc
+ AssertFatal(N_TA_offset == 400,"scs_common 30kHz only for FR1\n");
+ if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s
+ else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s
+ break;
+ case 2: //60 kHz scs
+ AssertFatal(1==0,"scs_common should not be 60 kHz\n");
+ break;
+ case 3: //120 kHz scs
+ AssertFatal(N_TA_offset == 431,"scs_common 120kHz only for FR2\n");
+ break;
+ case 4: //240 kHz scs
+ AssertFatal(1==0,"scs_common should not be 60 kHz\n");
+ if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s
+ else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s
+ else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB);
+ break;
+
+ if (N_RB == 100) ru->N_TA_offset = 624;
+ else if (N_RB == 50) ru->N_TA_offset = 624/2;
+ else if (N_RB == 25) ru->N_TA_offset = 624/4;
+ }
+ if (frame_parms->threequarter_fs == 1) factor = factor*.75;
+ ru->N_TA_offset = (int)(N_TA_offset * factor);
+ LOG_I(PHY,"RU %d Setting N_TA_offset to %d samples (factor %f, UL Freq %d, N_RB %d)\n",ru->idx,ru->N_TA_offset,factor,
+ config->carrier_config.uplink_frequency.value, N_RB);
+ }
+ else ru->N_TA_offset = 0;
+
+
if (ru->openair0_cfg.mmapped_dma == 1) {
// replace RX signal buffers with mmaped HW versions
for (i=0; i<ru->nb_rx; i++) {
@@ -1388,7 +1432,7 @@ void *ru_thread( void *param ) {
int i = 0;
int aa;
- nfapi_nr_config_request_scf_t *cfg = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
// set default return value
ru_thread_status = 0;
@@ -1400,7 +1444,7 @@ void *ru_thread( void *param ) {
if(emulate_rf) {
fill_rf_config(ru,ru->rf_config_file);
- nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp);
+ nr_init_frame_parms(&ru->config, fp);
nr_dump_frame_parms(fp);
nr_phy_init_RU(ru);
@@ -1420,8 +1464,10 @@ void *ru_thread( void *param ) {
AssertFatal(ret==0,"Cannot connect to remote radio\n");
}
+ memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config));
+
if (ru->if_south == LOCAL_RF) { // configure RF parameters only
- nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, fp);
+ nr_init_frame_parms(&ru->config, fp);
nr_dump_frame_parms(fp);
fill_rf_config(ru,ru->rf_config_file);
nr_phy_init_RU(ru);
@@ -1463,6 +1509,18 @@ void *ru_thread( void *param ) {
// if this is a slave RRU, try to synchronize on the DL frequency
if ((ru->is_slave) && (ru->if_south == LOCAL_RF)) do_ru_synch(ru);
+
+ // start trx write thread
+ if(usrp_tx_thread == 1){
+ if (ru->start_write_thread){
+ if(ru->start_write_thread(ru) != 0){
+ LOG_E(HW,"Could not start tx write thread\n");
+ }
+ else{
+ LOG_I(PHY,"tx write thread ready\n");
+ }
+ }
+ }
}
pthread_mutex_lock(&proc->mutex_FH1);
@@ -1522,6 +1580,17 @@ void *ru_thread( void *param ) {
for (aa=0;aa<ru->nb_rx;aa++)
memcpy((void*)RC.gNB[0]->common_vars.rxdataF[aa],
(void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t));
+
+ // Do PRACH RU processing
+ int prach_id=find_nr_prach_ru(ru,proc->frame_rx,proc->tti_rx,SEARCH_EXIST);
+ if (prach_id>=0) {
+ rx_nr_prach_ru(ru,
+ ru->prach_list[prach_id].fmt,
+ ru->prach_list[prach_id].numRA,
+ ru->prach_list[prach_id].prachStartSymbol,
+ proc->frame_rx,proc->tti_rx);
+ free_nr_ru_prach_entry(ru,prach_id);
+ }
}
// At this point, all information for subframe has been received on FH interface
@@ -1672,14 +1741,15 @@ int stop_rf(RU_t *ru) {
return 0;
}
+int start_write_thread(RU_t *ru) {
+ return(ru->rfdevice.trx_write_init(&ru->rfdevice));
+}
void init_RU_proc(RU_t *ru) {
int i=0;
RU_proc_t *proc;
char name[100];
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing RU proc %d (%s,%s),\n",ru->idx,NB_functions[ru->function],NB_timing[ru->if_timing]);
-#endif
proc = &ru->proc;
memset((void *)proc,0,sizeof(RU_proc_t));
proc->ru = ru;
@@ -1892,7 +1962,7 @@ void configure_ru(int idx,
RU_t *ru = RC.ru[idx];
RRU_config_t *config = (RRU_config_t *)arg;
RRU_capabilities_t *capabilities = (RRU_capabilities_t *)arg;
- nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
int ret;
LOG_I(PHY, "Received capabilities from RRU %d\n",idx);
@@ -1915,15 +1985,15 @@ void configure_ru(int idx,
//config->tdd_config_S[0] = ru->nr_frame_parms->tdd_config_S;
config->att_tx[0] = ru->att_tx;
config->att_rx[0] = ru->att_rx;
- config->N_RB_DL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value;
- config->N_RB_UL[0] = gNB_config->carrier_config.dl_grid_size[gNB_config->ssb_config.scs_common.value].value;
+ config->N_RB_DL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value;
+ config->N_RB_UL[0] = cfg->carrier_config.dl_grid_size[cfg->ssb_config.scs_common.value].value;
config->threequarter_fs[0] = ru->nr_frame_parms->threequarter_fs;
/* if (ru->if_south==REMOTE_IF4p5) {
config->prach_FreqOffset[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_FreqOffset;
config->prach_ConfigIndex[0] = ru->nr_frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
LOG_I(PHY,"REMOTE_IF4p5: prach_FrequOffset %d, prach_ConfigIndex %d\n",
config->prach_FreqOffset[0],config->prach_ConfigIndex[0]);*/
- nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms);
+ nr_init_frame_parms(&ru->config, ru->nr_frame_parms);
nr_phy_init_RU(ru);
}
@@ -1931,23 +2001,23 @@ void configure_rru(int idx,
void *arg) {
RRU_config_t *config = (RRU_config_t *)arg;
RU_t *ru = RC.ru[idx];
- nfapi_nr_config_request_scf_t *gNB_config = &ru->gNB_list[0]->gNB_config;
+ nfapi_nr_config_request_scf_t *cfg = &ru->config;
ru->nr_frame_parms->nr_band = config->band_list[0];
ru->nr_frame_parms->dl_CarrierFreq = config->tx_freq[0];
ru->nr_frame_parms->ul_CarrierFreq = config->rx_freq[0];
if (ru->nr_frame_parms->dl_CarrierFreq == ru->nr_frame_parms->ul_CarrierFreq) {
- gNB_config->cell_config.frame_duplex_type.value = TDD;
+ cfg->cell_config.frame_duplex_type.value = TDD;
//ru->nr_frame_parms->tdd_config = config->tdd_config[0];
//ru->nr_frame_parms->tdd_config_S = config->tdd_config_S[0];
} else
- gNB_config->cell_config.frame_duplex_type.value = FDD;
+ cfg->cell_config.frame_duplex_type.value = FDD;
ru->att_tx = config->att_tx[0];
ru->att_rx = config->att_rx[0];
- int mu = gNB_config->ssb_config.scs_common.value;
- gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0];
- gNB_config->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0];
+ int mu = cfg->ssb_config.scs_common.value;
+ cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_DL[0];
+ cfg->carrier_config.dl_grid_size[mu].value = config->N_RB_UL[0];
ru->nr_frame_parms->threequarter_fs = config->threequarter_fs[0];
//ru->nr_frame_parms->pdsch_config_common.referenceSignalPower = ru->max_pdschReferenceSignalPower-config->att_tx[0];
@@ -1962,7 +2032,7 @@ void configure_rru(int idx,
}
fill_rf_config(ru,ru->rf_config_file);
- nr_init_frame_parms(&ru->gNB_list[0]->gNB_config, ru->nr_frame_parms);
+ nr_init_frame_parms(&ru->config, ru->nr_frame_parms);
nr_phy_init_RU(ru);
}
@@ -2067,6 +2137,7 @@ void set_function_spec_param(RU_t *ru) {
ru->fh_south_out = tx_rf; // local synchronous RF TX
ru->start_rf = start_rf; // need to start the local RF interface
ru->stop_rf = stop_rf;
+ ru->start_write_thread = start_write_thread; // starting RF TX in different thread
printf("configuring ru_id %u (start_rf %p)\n", ru->idx, start_rf);
/*
if (ru->function == gNodeB_3GPP) { // configure RF parameters only for 3GPP eNodeB, we need to get them from RAU otherwise
@@ -2092,6 +2163,7 @@ void set_function_spec_param(RU_t *ru) {
ru->fh_south_asynch_in = NULL; // no asynchronous UL
ru->start_rf = NULL; // no local RF
ru->stop_rf = NULL;
+ ru->start_write_thread = NULL;
ru->nr_start_if = nr_start_if; // need to start if interface for IF5
ru->ifdevice.host_type = RAU_HOST;
ru->ifdevice.eth_params = &ru->eth_params;
@@ -2118,6 +2190,7 @@ void set_function_spec_param(RU_t *ru) {
ru->fh_north_asynch_in = NULL;
ru->start_rf = NULL; // no local RF
ru->stop_rf = NULL;
+ ru->start_write_thread = NULL;
ru->nr_start_if = nr_start_if; // need to start if interface for IF4p5
ru->ifdevice.host_type = RAU_HOST;
ru->ifdevice.eth_params = &ru->eth_params;
@@ -2147,7 +2220,6 @@ void init_NR_RU(char *rf_config_file)
PHY_VARS_gNB *gNB0= (PHY_VARS_gNB *)NULL;
NR_DL_FRAME_PARMS *fp = (NR_DL_FRAME_PARMS *)NULL;
int i;
- int CC_id;
// create status mask
RC.ru_mask = 0;
pthread_mutex_init(&RC.ru_mutex,NULL);
diff --git a/executables/nr-softmodem-common.h b/executables/nr-softmodem-common.h
index ccb3f28d98e59c7ccb08cc8e6c2483027f6469ca..c968fee7b6e4bcc9ffe466df4fdb21049b8d4f7a 100644
--- a/executables/nr-softmodem-common.h
+++ b/executables/nr-softmodem-common.h
@@ -57,6 +57,7 @@
#define CONFIG_HLP_DLSHIFT "dynamic shift for LLR compuation for TM3/4 (default 0)\n"
#define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n"
#define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n"
+#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n"
#define CONFIG_HLP_DMAMAP "sets flag for improved EXMIMO UE performance\n"
#define CONFIG_HLP_EXCCLK "tells hardware to use a clock reference (0:internal(default), 1:external, 2:gpsdo)\n"
#define CONFIG_HLP_USIM "use XOR autentication algo in case of test usim mode\n"
@@ -89,6 +90,7 @@
#define CONFIG_HLP_EMULATE_RF "Emulated RF enabled(disable by defult)\n"
#define CONFIG_HLP_PARALLEL_CMD "three config for level of parallelism 'PARALLEL_SINGLE_THREAD', 'PARALLEL_RU_L1_SPLIT', or 'PARALLEL_RU_L1_TRX_SPLIT'\n"
#define CONFIG_HLP_WORKER_CMD "two option for worker 'WORKER_DISABLE' or 'WORKER_ENABLE'\n"
+#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n"
#define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n"
#define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n"
@@ -143,6 +145,10 @@ extern int sync_var;
extern int transmission_mode;
extern double cpuf;
+extern int emulate_rf;
+extern int numerology;
+extern int usrp_tx_thread;
+
extern volatile int start_eNB;
extern volatile int start_UE;
diff --git a/executables/nr-softmodem.c b/executables/nr-softmodem.c
index 6dd3807f3cc1f5a92ff0aee0b30b9e3d80fe4806..a3d0b325d67211d38d0bd1054857d7ac06648635 100644
--- a/executables/nr-softmodem.c
+++ b/executables/nr-softmodem.c
@@ -75,7 +75,7 @@ unsigned short config_frames[4] = {2,9,11,13};
#include "system.h"
#include <openair2/GNB_APP/gnb_app.h>
-
+#include "PHY/TOOLS/phy_scope_interface.h"
#include "PHY/TOOLS/nr_phy_scope.h"
#include "stats.h"
#include "nr-softmodem.h"
@@ -84,9 +84,6 @@ unsigned short config_frames[4] = {2,9,11,13};
#include "NB_IoT_interface.h"
#include "x2ap_eNB.h"
-short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655};
-
-
pthread_cond_t nfapi_sync_cond;
pthread_mutex_t nfapi_sync_mutex;
int nfapi_sync_var=-1; //!< protected by mutex \ref nfapi_sync_mutex
@@ -156,7 +153,6 @@ char channels[128] = "0";
int rx_input_level_dBm;
-uint32_t do_forms=0;
int otg_enabled;
//int number_of_cards = 1;
@@ -178,10 +174,12 @@ extern void reset_opp_meas(void);
extern void print_opp_meas(void);
extern void init_eNB_afterRU(void);
+extern void *udp_eNB_task(void *args_p);
int transmission_mode=1;
int emulate_rf = 0;
int numerology = 0;
+int usrp_tx_thread = 0;
static char *parallel_config = NULL;
@@ -384,10 +382,10 @@ int create_gNB_tasks(uint32_t gnb_nb) {
if (gnb_nb > 0) {
/* Last task to create, others task must be ready before its start */
- if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) {
+ /*if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) {
LOG_E(GNB_APP, "Create task for gNB APP failed\n");
return -1;
- }
+ }*/
if(itti_create_task(TASK_SCTP, sctp_eNB_task, NULL) < 0){
LOG_E(SCTP, "Create task for SCTP failed\n");
return -1;
@@ -402,35 +400,39 @@ int create_gNB_tasks(uint32_t gnb_nb) {
}
}
- /*
- if (EPC_MODE_ENABLED) {
- if (gnb_nb > 0) {
- if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) {
- LOG_E(SCTP, "Create task for SCTP failed\n");
- return -1;
- }
+ if (EPC_MODE_ENABLED && (get_softmodem_params()->phy_test==0 && get_softmodem_params()->do_ra==0)) {
+ if (gnb_nb > 0) {
+ /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) {
+ LOG_E(SCTP, "Create task for SCTP failed\n");
+ return -1;
+ }
- if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) {
- LOG_E(S1AP, "Create task for S1AP failed\n");
- return -1;
- }
- if(!emulate_rf){
- if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) {
- LOG_E(UDP_, "Create task for UDP failed\n");
- return -1;
- }
- }
+ if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) {
+ LOG_E(S1AP, "Create task for S1AP failed\n");
+ return -1;
+ }*/
- if (itti_create_task (TASK_GTPV1_U, >pv1u_eNB_task, NULL) < 0) {
- LOG_E(GTPU, "Create task for GTPV1U failed\n");
- return -1;
- }
+
+ if(!emulate_rf){
+ if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) {
+ LOG_E(UDP_, "Create task for UDP failed\n");
+ return -1;
}
+ }
+ if (itti_create_task (TASK_GTPV1_U, >pv1u_gNB_task, NULL) < 0) {
+ LOG_E(GTPU, "Create task for GTPV1U failed\n");
+ return -1;
+ }
}
- */
+ }
+
if (gnb_nb > 0) {
+ if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) {
+ LOG_E(GNB_APP, "Create task for gNB APP failed\n");
+ return -1;
+ }
LOG_I(NR_RRC,"Creating NR RRC gNB Task\n");
if (itti_create_task (TASK_RRC_GNB, rrc_gnb_task, NULL) < 0) {
@@ -448,7 +450,11 @@ static void get_options(void) {
paramdef_t cmdline_params[] = CMDLINE_PARAMS_DESC_GNB ;
+ CONFIG_SETRTFLAG(CONFIG_NOEXITONHELP);
+ get_common_options(SOFTMODEM_GNB_BIT );
config_process_cmdline( cmdline_params,sizeof(cmdline_params)/sizeof(paramdef_t),NULL);
+ CONFIG_CLEARRTFLAG(CONFIG_NOEXITONHELP);
+
@@ -708,7 +714,6 @@ int stop_L1L2(module_id_t gnb_id) {
*/
int restart_L1L2(module_id_t gnb_id) {
RU_t *ru = RC.ru[gnb_id];
- int cc_id;
MessageDef *msg_p = NULL;
LOG_W(GNB_APP, "restarting nr-softmodem\n");
/* block threads */
@@ -718,9 +723,6 @@ int restart_L1L2(module_id_t gnb_id) {
RC.ru_mask |= (1 << ru->idx);
- /* copy the changed frame parameters to the RU */
- /* TODO this should be done for all RUs associated to this gNB */
- memcpy(&ru->nr_frame_parms, &RC.gNB[gnb_id]->frame_parms, sizeof(NR_DL_FRAME_PARMS));
set_function_spec_param(RC.ru[gnb_id]);
LOG_I(GNB_APP, "attempting to create ITTI tasks\n");
// No more rrc thread, as many race conditions are hidden behind
@@ -812,7 +814,6 @@ int main( int argc, char **argv )
configure_linux();
printf("Reading in command-line options\n");
get_options ();
- get_common_options(SOFTMODEM_GNB_BIT );
if (CONFIG_ISFLAGSET(CONFIG_ABORT) ) {
fprintf(stderr,"Getting configuration failed\n");
@@ -820,6 +821,10 @@ int main( int argc, char **argv )
}
openair0_cfg[0].threequarter_fs = threequarter_fs;
+ EPC_MODE_ENABLED = !IS_SOFTMODEM_NOS1; //!get_softmodem_params()->phy_test;
+
+ if (get_softmodem_params()->do_ra)
+ AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n");
#if T_TRACER
T_Config_Init();
@@ -950,12 +955,14 @@ if(!IS_SOFTMODEM_NOS1)
printf("RC.nb_RU:%d\n", RC.nb_RU);
// once all RUs are ready initialize the rest of the gNBs ((dependence on final RU parameters after configuration)
printf("ALL RUs ready - init gNBs\n");
-
- if (do_forms==1) {
+ if(IS_SOFTMODEM_DOFORMS) {
+
scopeParms_t p;
p.argc=&argc;
p.argv=argv;
- startScope(&p);
+ p.gNB=RC.gNB[0];
+ p.ru=RC.ru[0];
+ load_softscope("nr",&p);
}
if (nfapi_mode != 1 && nfapi_mode != 2) {
diff --git a/executables/nr-softmodem.h b/executables/nr-softmodem.h
index 27e3ba1e3e328758f452df56460efc43b8cac554..d6cfe6b906acef4026dcf08d7b03433b32fd1986 100644
--- a/executables/nr-softmodem.h
+++ b/executables/nr-softmodem.h
@@ -19,21 +19,13 @@
/*----------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
#define CMDLINE_PARAMS_DESC_GNB { \
{"mmapped-dma", CONFIG_HLP_DMAMAP, PARAMFLAG_BOOL, uptr:&mmapped_dma, defintval:0, TYPE_INT, 0}, \
- {"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&wait_for_sync, defintval:0, TYPE_INT, 0}, \
{"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \
{"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \
- {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:DEFAULT_DLF, TYPE_UINT64, 0}, \
- {"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \
- {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:(uint32_t *)&do_forms, defintval:0, TYPE_INT8, 0}, \
{"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, i8ptr:&threequarter_fs, defintval:0, TYPE_INT8, 0}, \
{"K" , CONFIG_HLP_ITTIL, PARAMFLAG_NOFREE, strptr:&itti_dump_file, defstrval:"/tmp/itti.dump", TYPE_STRING, 0}, \
{"m" , CONFIG_HLP_DLMCS, 0, uptr:&target_dl_mcs, defintval:0, TYPE_UINT, 0}, \
{"t" , CONFIG_HLP_ULMCS, 0, uptr:&target_ul_mcs, defintval:0, TYPE_UINT, 0}, \
- {"q" , CONFIG_HLP_STMON, PARAMFLAG_BOOL, iptr:&opp_enabled, defintval:0, TYPE_INT, 0}, \
- {"numerology" , CONFIG_HLP_NUMEROLOGY, PARAMFLAG_BOOL, iptr:&numerology, defintval:0, TYPE_INT, 0}, \
- {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \
- {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \
- {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \
+ {"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, iptr:&usrp_tx_thread, defstrval:0, TYPE_INT, 0}, \
{"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \
}
diff --git a/executables/nr-ue.c b/executables/nr-ue.c
index a0251b26dffae81cb2dd09ac059d087c7e0f81eb..4b7ff204613081ceda45f7738eac6c58ead36751 100644
--- a/executables/nr-ue.c
+++ b/executables/nr-ue.c
@@ -21,7 +21,7 @@
#include "executables/thread-common.h"
#include "executables/nr-uesoftmodem.h"
-#include "LAYER2/NR_MAC_UE/mac.h"
+#include "NR_MAC_UE/mac.h"
//#include "RRC/LTE/rrc_extern.h"
#include "PHY_INTERFACE/phy_interface_extern.h"
@@ -32,12 +32,10 @@
#include "PHY/phy_extern_nr_ue.h"
#include "PHY/INIT/phy_init.h"
#include "PHY/MODULATION/modulation_UE.h"
-#include "LAYER2/NR_MAC_UE/mac_proto.h"
+#include "NR_MAC_UE/mac_proto.h"
#include "RRC/NR_UE/rrc_proto.h"
-//#ifndef NO_RAT_NR
-#include "SCHED_NR/phy_frame_config_nr.h"
-//#endif
+#include "SCHED_NR_UE/phy_frame_config_nr.h"
#include "SCHED_NR_UE/defs.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
@@ -123,7 +121,7 @@ extern double cpuf;
#ifndef NO_RAT_NR
#define DURATION_RX_TO_TX (NR_UE_CAPABILITY_SLOT_RX_TO_TX) /* for NR this will certainly depends to such UE capability which is not yet defined */
#else
- #define DURATION_RX_TO_TX (4) /* For LTE, this duration is fixed to 4 and it is linked to LTE standard for both modes FDD/TDD */
+ #define DURATION_RX_TO_TX (6) /* For LTE, this duration is fixed to 4 and it is linked to LTE standard for both modes FDD/TDD */
#endif
#define FRAME_PERIOD 100000000ULL
@@ -142,15 +140,24 @@ void init_nr_ue_vars(PHY_VARS_NR_UE *ue,
uint8_t abstraction_flag)
{
+ int nb_connected_gNB = 1, gNB_id;
+
memcpy(&(ue->frame_parms), frame_parms, sizeof(NR_DL_FRAME_PARMS));
ue->Mod_id = UE_id;
ue->mac_enabled = 1;
+
+ // Setting UE mode to NOT_SYNCHED by default
+ for (gNB_id = 0; gNB_id < nb_connected_gNB; gNB_id++){
+ ue->UE_mode[gNB_id] = NOT_SYNCHED;
+ ue->prach_resources[gNB_id] = (NR_PRACH_RESOURCES_t *)malloc16_clear(sizeof(NR_PRACH_RESOURCES_t));
+ }
+
// initialize all signal buffers
- // initialize all signal buffers
- init_nr_ue_signal(ue,1,abstraction_flag);
+ init_nr_ue_signal(ue, nb_connected_gNB, abstraction_flag);
+
// intialize transport
- init_nr_ue_transport(ue,abstraction_flag);
+ init_nr_ue_transport(ue, abstraction_flag);
}
/*!
@@ -357,59 +364,33 @@ static void UE_synch(void *arg) {
}
void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
- uint32_t nb_rb, start_rb;
- uint8_t nb_symb_sch, start_symbol, mcs, precod_nbr_layers, harq_pid, rvidx;
- uint16_t n_rnti;
-
- nr_dcireq_t dcireq;
- nr_scheduled_response_t scheduled_response;
-
- // program PUSCH. this should actually be done by the MAC upon reception of an UL DCI
- if (proc->nr_tti_tx == 8 || UE->frame_parms.frame_type == FDD){
-
- dcireq.module_id = UE->Mod_id;
- dcireq.gNB_index = 0;
- dcireq.cc_id = 0;
- dcireq.frame = proc->frame_rx;
- dcireq.slot = proc->nr_tti_rx;
-
- scheduled_response.dl_config = NULL;
- scheduled_response.ul_config = &dcireq.ul_config_req;
- scheduled_response.tx_request = NULL;
- scheduled_response.module_id = UE->Mod_id;
- scheduled_response.CC_id = 0;
- scheduled_response.frame = proc->frame_rx;
- scheduled_response.slot = proc->nr_tti_rx;
- //--------------------------Temporary configuration-----------------------------//
- n_rnti = 0x1234;
- nb_rb = 50;
- start_rb = 0;
- nb_symb_sch = 12;
- start_symbol = 2;
- precod_nbr_layers = 1;
- mcs = 9;
- harq_pid = 0;
- rvidx = 0;
- //------------------------------------------------------------------------------//
-
- scheduled_response.ul_config->slot = 8;
- scheduled_response.ul_config->number_pdus = 1;
- scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.rnti = n_rnti;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = nb_rb;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = start_rb;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = nb_symb_sch;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = start_symbol;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.mcs = mcs;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = rvidx;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers;
- scheduled_response.ul_config->ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid;
-
- nr_ue_scheduled_response(&scheduled_response);
-
+
+
+ fapi_nr_config_request_t *cfg = &UE->nrUE_config;
+ int tx_slot_type = nr_ue_slot_select(cfg, proc->frame_tx, proc->nr_tti_tx);
+ uint8_t gNB_id = 0;
+
+ if (tx_slot_type == NR_UPLINK_SLOT || tx_slot_type == NR_MIXED_SLOT){
+
+ // trigger L2 to run ue_scheduler thru IF module
+ // [TODO] mapping right after NR initial sync
+ if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) {
+ nr_uplink_indication_t ul_indication;
+ memset((void*)&ul_indication, 0, sizeof(ul_indication));
+
+ ul_indication.module_id = UE->Mod_id;
+ ul_indication.gNB_index = gNB_id;
+ ul_indication.cc_id = UE->CC_id;
+ ul_indication.frame_rx = proc->frame_rx;
+ ul_indication.slot_rx = proc->nr_tti_rx;
+ ul_indication.frame_tx = proc->frame_tx;
+ ul_indication.slot_tx = proc->nr_tti_tx;
+
+ UE->if_inst->ul_indication(&ul_indication);
+ }
+
if (UE->mode != loop_through_memory) {
- uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx];
+ uint8_t thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_rx];
phy_procedures_nrUE_TX(UE,proc,0,thread_id);
}
}
@@ -417,41 +398,26 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
- nr_dcireq_t dcireq;
- nr_scheduled_response_t scheduled_response;
- uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period;
-
- //program DCI for slot 1
- //TODO: all of this has to be moved to the MAC!!!
- if (proc->nr_tti_rx == NR_DOWNLINK_SLOT || UE->frame_parms.frame_type == FDD){
- dcireq.module_id = UE->Mod_id;
- dcireq.gNB_index = 0;
- dcireq.cc_id = 0;
- dcireq.frame = proc->frame_rx;
- dcireq.slot = proc->nr_tti_rx;
- nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
-
- // we should have received a DL DCI here, so configure DL accordingly
- scheduled_response.dl_config = &dcireq.dl_config_req;
- scheduled_response.ul_config = NULL;
- scheduled_response.tx_request = NULL;
- scheduled_response.module_id = UE->Mod_id;
- scheduled_response.CC_id = 0;
- if (!((proc->frame_rx)%(1<<(ssb_period-1)))) {
- if(proc->frame_rx > dcireq.dl_config_req.sfn)
- UE->frame_gap = proc->frame_rx - dcireq.dl_config_req.sfn;
- if(proc->frame_rx < dcireq.dl_config_req.sfn)
- UE->frame_gap = dcireq.dl_config_req.sfn - proc->frame_rx;
- proc->frame_rx = dcireq.dl_config_req.sfn;
- }
- scheduled_response.frame = proc->frame_rx;
- scheduled_response.slot = proc->nr_tti_rx;
+ fapi_nr_config_request_t *cfg = &UE->nrUE_config;
+ int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx);
+ uint8_t gNB_id = 0;
- nr_ue_scheduled_response(&scheduled_response);
- }
+ if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){
+
+ if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) {
+ nr_downlink_indication_t dl_indication;
+ memset((void*)&dl_indication, 0, sizeof(dl_indication));
+
+ dl_indication.module_id = UE->Mod_id;
+ dl_indication.gNB_index = gNB_id;
+ dl_indication.cc_id = UE->CC_id;
+ dl_indication.frame = proc->frame_rx;
+ dl_indication.slot = proc->nr_tti_rx;
+
+ UE->if_inst->dl_indication(&dl_indication, NULL);
+ }
// Process Rx data for one sub-frame
- if ( proc->nr_tti_rx >=0 && proc->nr_tti_rx <= 1 ) {
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
#else
@@ -471,7 +437,6 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
}
}
- // no UL for now
// no UL for now
/*
if (UE->mac_enabled==1) {
@@ -487,6 +452,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
}
}
*/
+
}
/*!
@@ -503,12 +469,12 @@ typedef struct processingData_s {
} processingData_t;
void UE_processing(void *arg) {
- processingData_t *rxtxD=(processingData_t *) arg;
+ processingData_t *rxtxD = (processingData_t *) arg;
UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
PHY_VARS_NR_UE *UE = rxtxD->UE;
uint8_t gNB_id = 0;
- // params for UL time alignment procedure
+
// params for UL time alignment procedure
NR_UL_TIME_ALIGNMENT_t *ul_time_alignment = &UE->ul_time_alignment[gNB_id];
uint8_t numerology = UE->frame_parms.numerology_index;
@@ -523,7 +489,7 @@ void UE_processing(void *arg) {
if (frame_tx == ul_time_alignment->ta_frame && slot_tx == ul_time_alignment->ta_slot) {
LOG_D(PHY,"Applying timing advance -- frame %d -- slot %d\n", frame_tx, slot_tx);
- //if (nfapi_mode!=3){
+
//if (nfapi_mode!=3){
nr_process_timing_advance(UE->Mod_id, UE->CC_id, ul_time_alignment->ta_command, numerology, bwp_ul_NB_RB);
ul_time_alignment->ta_frame = -1;
@@ -533,9 +499,7 @@ void UE_processing(void *arg) {
}
processSlotRX(UE, proc);
-
processSlotTX(UE, proc);
-
}
void dummyWrite(PHY_VARS_NR_UE *UE,openair0_timestamp timestamp, int writeBlockSize) {
@@ -590,8 +554,7 @@ void readFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp, bool toTrash)
void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) {
- LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode);
- void *dummy_tx[UE->frame_parms.nb_antennas_tx];
+ LOG_I(PHY,"Resynchronizing RX by %d samples (mode = %d)\n",UE->rx_offset,UE->mode);
*timestamp += UE->frame_parms.get_samples_per_slot(1,&UE->frame_parms);
for ( int size=UE->rx_offset ; size > 0 ; size -= UE->frame_parms.samples_per_subframe ) {
@@ -611,11 +574,6 @@ void syncInFrame(PHY_VARS_NR_UE *UE, openair0_timestamp *timestamp) {
}
int computeSamplesShift(PHY_VARS_NR_UE *UE) {
- if (IS_SOFTMODEM_RFSIM) {
- LOG_E(PHY,"SET rx_offset %d \n",UE->rx_offset);
- //UE->rx_offset_diff=0;
- return 0;
- }
// compute TO compensation that should be applied for this frame
if ( UE->rx_offset < UE->frame_parms.samples_per_frame/2 &&
@@ -682,8 +640,11 @@ void *UE_thread(void *arg) {
if (res) {
syncRunning=false;
syncData_t *tmp=(syncData_t *)NotifiedFifoData(res);
- // shift the frame index with all the frames we trashed meanwhile we perform the synch search
- decoded_frame_rx=(tmp->proc.decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER;
+ if (UE->is_synchronized) {
+ decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx);
+ // shift the frame index with all the frames we trashed meanwhile we perform the synch search
+ decoded_frame_rx=(decoded_frame_rx + (!UE->init_sync_frame) + trashed_frames) % MAX_FRAME_NUMBER;
+ }
delNotifiedFIFO_elt(res);
} else {
readFrame(UE, ×tamp, true);
@@ -728,6 +689,7 @@ void *UE_thread(void *arg) {
absolute_slot++;
+
// whatever means thread_idx
// Fix me: will be wrong when slot 1 is slow, as slot 2 finishes
// Slot 3 will overlap if RX_NB_TH is 2
@@ -740,20 +702,20 @@ void *UE_thread(void *arg) {
curMsg->UE=UE;
// update thread index for received subframe
curMsg->UE->current_thread_id[slot_nr] = thread_idx;
- curMsg->proc.CC_id = 0;
+ curMsg->proc.CC_id = UE->CC_id;
curMsg->proc.nr_tti_rx= slot_nr;
curMsg->proc.subframe_rx=slot_nr/(nb_slot_frame/10);
curMsg->proc.nr_tti_tx = (absolute_slot + DURATION_RX_TO_TX) % nb_slot_frame;
curMsg->proc.subframe_tx=curMsg->proc.nr_tti_rx;
- curMsg->proc.frame_rx = ((absolute_slot/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER;
- curMsg->proc.frame_tx = (((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame)+UE->frame_gap) % MAX_FRAME_NUMBER;
+ curMsg->proc.frame_rx = (absolute_slot/nb_slot_frame) % MAX_FRAME_NUMBER;
+ curMsg->proc.frame_tx = ((absolute_slot+DURATION_RX_TO_TX)/nb_slot_frame) % MAX_FRAME_NUMBER;
curMsg->proc.decoded_frame_rx=-1;
//LOG_I(PHY,"Process slot %d thread Idx %d total gain %d\n", slot_nr, thread_idx, UE->rx_total_gain_dB);
#ifdef OAI_ADRV9371_ZC706
/*uint32_t total_gain_dB_prev = 0;
if (total_gain_dB_prev != UE->rx_total_gain_dB) {
- total_gain_dB_prev = UE->rx_total_gain_dB;
+ total_gain_dB_prev = UE->rx_total_gain_dB;
openair0_cfg[0].rx_gain[0] = UE->rx_total_gain_dB;
UE->rfdevice.trx_set_gains_func(&UE->rfdevice,&openair0_cfg[0]);
}*/
@@ -766,7 +728,7 @@ void *UE_thread(void *arg) {
for (int i=0; i<UE->frame_parms.nb_antennas_tx; i++)
txp[i] = (void *)&UE->common_vars.txdata[i][UE->frame_parms.get_samples_slot_timestamp(
- ((curMsg->proc.nr_tti_rx + DURATION_RX_TO_TX)%nb_slot_frame),&UE->frame_parms,0)];
+ ((curMsg->proc.nr_tti_rx + DURATION_RX_TO_TX -2)%nb_slot_frame),&UE->frame_parms,0)];
int readBlockSize, writeBlockSize;
@@ -792,7 +754,7 @@ void *UE_thread(void *arg) {
UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp+
UE->frame_parms.get_samples_slot_timestamp(slot_nr,
- &UE->frame_parms,DURATION_RX_TO_TX) - firstSymSamp -
+ &UE->frame_parms,DURATION_RX_TO_TX -2) - firstSymSamp -
openair0_cfg[0].tx_sample_advance,
txp,
writeBlockSize,
@@ -835,9 +797,10 @@ void *UE_thread(void *arg) {
usleep(200);
}
- if ( decoded_frame_rx != curMsg->proc.frame_rx &&
- ((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx )
- LOG_D(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n",
+ if ( (decoded_frame_rx != curMsg->proc.frame_rx) &&
+ (((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx) &&
+ (((decoded_frame_rx+2) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx))
+ LOG_E(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n",
decoded_frame_rx, curMsg->proc.frame_rx );
nbSlotProcessing++;
@@ -858,6 +821,7 @@ void *UE_thread(void *arg) {
pushNotifiedFIFO_nothreadSafe(&freeBlocks,res);
}
+
} // while !oai_exit
return NULL;
diff --git a/executables/nr-uesoftmodem.c b/executables/nr-uesoftmodem.c
index 9b2b704833fb878ed5f9796892bb8f9811584f5a..2fbea2bbfb40a1376f1a26cb1aa9e4d431859bf0 100644
--- a/executables/nr-uesoftmodem.c
+++ b/executables/nr-uesoftmodem.c
@@ -44,7 +44,6 @@
#include "SCHED/sched_common_vars.h"
#include "PHY/MODULATION/modulation_vars.h"
//#include "../../SIMU/USER/init_lte.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "LAYER2/MAC/mac_vars.h"
#include "RRC/LTE/rrc_vars.h"
@@ -76,37 +75,12 @@ unsigned short config_frames[4] = {2,9,11,13};
#include <openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h>
#include <openair1/SCHED_NR_UE/fapi_nr_ue_l1.h>
-#include <forms.h>
-
-
/* Callbacks, globals and object handlers */
-extern void reset_stats( FL_OBJECT *, long );
-//extern void initTpool(char *params, tpool_t *pool, bool performanceMeas);
-
-/* Forms and Objects */
-
-typedef struct {
- FL_FORM *stats_form;
- void *vdata;
- char *cdata;
- long ldata;
- FL_OBJECT *stats_text;
- FL_OBJECT *stats_button;
-} FD_stats_form;
-
-extern FD_stats_form *create_form_stats_form( void );
-
-#include "PHY/TOOLS/nr_phy_scope.h"
//#include "stats.h"
// current status is that every UE has a DL scope for a SINGLE eNB (eNB_id=0)
-// at eNB 0, an UL scope for every UE
-FD_phy_scope_nrue *form_nrue[NUMBER_OF_UE_MAX];
-//FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
-//FD_stats_form *form_stats=NULL,*form_stats_l2=NULL;
-char title[255];
-static pthread_t forms_thread; //xforms
-
+#include "PHY/TOOLS/phy_scope_interface.h"
+#include "PHY/TOOLS/nr_phy_scope.h"
#include <executables/nr-uesoftmodem.h>
#include "executables/softmodem-common.h"
#include "executables/thread-common.h"
@@ -176,14 +150,11 @@ char ref[128] = "internal";
char channels[128] = "0";
-static char *parallel_config = NULL;
-static char *worker_config = NULL;
-
int rx_input_level_dBm;
//static int online_log_messages=0;
-uint32_t do_forms=0;
+
int otg_enabled;
//int number_of_cards = 1;
@@ -198,6 +169,7 @@ uint64_t num_missed_slots=0; // counter for the number of missed slots
int transmission_mode=1;
int numerology = 0;
+int usrp_tx_thread = 0;
/* flag set by eNB conf file to specify if the radio head is local or remote (default option is local) */
//uint8_t local_remote_radio = BBU_LOCAL_RADIO_HEAD;
@@ -274,7 +246,7 @@ void exit_function(const char *file, const char *function, const int line, const
}
-void reset_stats(FL_OBJECT *button, long arg) {
+void reset_stats(long arg) {
//int i,j,k;
/*PHY_VARS_eNB *phy_vars_eNB = PHY_vars_eNB_g[0][0];
@@ -304,35 +276,6 @@ void reset_stats(FL_OBJECT *button, long arg) {
}*/
}
-static void *scope_thread(void *arg) {
- sleep(5);
-
- while (!oai_exit) {
- phy_scope_nrUE(form_nrue[0],
- PHY_vars_UE_g[0][0],
- 0,0,1);
- usleep(100*1000);
- }
-
- pthread_exit((void *)arg);
-}
-
-
-void init_scope(void) {
- int fl_argc=1;
-
- if (do_forms==1) {
- char *name="5G-UE-scope";
- fl_initialize (&fl_argc, &name, NULL, 0, 0);
- int UE_id = 0;
- form_nrue[UE_id] = create_phy_scope_nrue();
- sprintf (title, "NR DL SCOPE UE");
- fl_show_form (form_nrue[UE_id]->phy_scope_nrue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title);
- threadCreate(&forms_thread, scope_thread, NULL, "scope", -1, OAI_PRIORITY_RT_LOW);
- }
-
-}
-
void *l2l1_task(void *arg) {
MessageDef *message_p = NULL;
int result;
@@ -720,6 +663,9 @@ int main( int argc, char **argv ) {
PHY_vars_UE_g = malloc(sizeof(PHY_VARS_NR_UE **));
PHY_vars_UE_g[0] = malloc(sizeof(PHY_VARS_NR_UE *)*MAX_NUM_CCs);
+ if (get_softmodem_params()->do_ra)
+ AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n");
+
for (int CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
printf("frame_parms %d\n",frame_parms[CC_id]->ofdm_symbol_size);
frame_parms[CC_id]->nb_antennas_tx = nb_antenna_tx;
@@ -746,11 +692,6 @@ int main( int argc, char **argv ) {
init_nr_ue_vars(UE[CC_id],frame_parms[CC_id],0,abstraction_flag);
- if (get_softmodem_params()->phy_test==1)
- UE[CC_id]->mac_enabled = 0;
- else
- UE[CC_id]->mac_enabled = 1;
-
UE[CC_id]->mac_enabled = 1;
UE[CC_id]->if_inst = nr_ue_if_module_init(0);
UE[CC_id]->UE_scan = UE_scan;
@@ -763,15 +704,49 @@ int main( int argc, char **argv ) {
UE[CC_id]->rx_total_gain_dB = (int)rx_gain[CC_id][0] + rx_gain_off;
UE[CC_id]->tx_power_max_dBm = tx_max_power[CC_id];
- if (frame_parms[CC_id]->frame_type==FDD) {
+ if (UE[CC_id]->frame_parms.frame_type == FDD) {
UE[CC_id]->N_TA_offset = 0;
} else {
- if (frame_parms[CC_id]->N_RB_DL == 100)
- UE[CC_id]->N_TA_offset = 624;
- else if (frame_parms[CC_id]->N_RB_DL == 50)
- UE[CC_id]->N_TA_offset = 624/2;
- else if (frame_parms[CC_id]->N_RB_DL == 25)
- UE[CC_id]->N_TA_offset = 624/4;
+ int N_RB = UE[CC_id]->frame_parms.N_RB_DL;
+ int N_TA_offset = UE[CC_id]->frame_parms.ul_CarrierFreq < 6e9 ? 400 : 431; // reference samples for 25600Tc @ 30.72 Ms/s for FR1, same @ 61.44 Ms/s for FR2
+ double factor=1;
+ switch (UE[CC_id]->frame_parms.numerology_index) {
+ case 0: //15 kHz scs
+ AssertFatal(N_TA_offset == 400, "scs_common 15kHz only for FR1\n");
+ if (N_RB <= 25) factor = .25; // 7.68 Ms/s
+ else if (N_RB <=50) factor = .5; // 15.36 Ms/s
+ else if (N_RB <=75) factor = 1.0; // 30.72 Ms/s
+ else if (N_RB <=100) factor = 1.0; // 30.72 Ms/s
+ else AssertFatal(1==0,"Too many PRBS for mu=0\n");
+ break;
+ case 1: //30 kHz sc
+ AssertFatal(N_TA_offset == 400, "scs_common 30kHz only for FR1\n");
+ if (N_RB <= 106) factor = 2.0; // 61.44 Ms/s
+ else if (N_RB <= 275) factor = 4.0; // 122.88 Ms/s
+ break;
+ case 2: //60 kHz scs
+ AssertFatal(1==0,"scs_common should not be 60 kHz\n");
+ break;
+ case 3: //120 kHz scs
+ AssertFatal(N_TA_offset == 431, "scs_common 120kHz only for FR2\n");
+ break;
+ case 4: //240 kHz scs
+ AssertFatal(1==0,"scs_common should not be 60 kHz\n");
+ if (N_RB <= 32) factor = 1.0; // 61.44 Ms/s
+ else if (N_RB <= 66) factor = 2.0; // 122.88 Ms/s
+ else AssertFatal(1==0,"N_RB %d is too big for curretn FR2 implementation\n",N_RB);
+ break;
+
+ if (N_RB == 100)
+ UE[CC_id]->N_TA_offset = 624;
+ else if (N_RB == 50)
+ UE[CC_id]->N_TA_offset = 624/2;
+ else if (N_RB == 25)
+ UE[CC_id]->N_TA_offset = 624/4;
+ }
+ if (UE[CC_id]->frame_parms.threequarter_fs == 1) factor = factor*.75;
+ UE[CC_id]->N_TA_offset = (int)(N_TA_offset * factor);
+ LOG_I(PHY,"UE %d Setting N_TA_offset to %d samples (factor %f, UL Freq %lu, N_RB %d)\n", UE[CC_id]->Mod_id, UE[CC_id]->N_TA_offset, factor, UE[CC_id]->frame_parms.ul_CarrierFreq, N_RB);
}
}
@@ -782,7 +757,10 @@ int main( int argc, char **argv ) {
memset (&UE_PF_PO[0][0], 0, sizeof(UE_PF_PO_t)*NUMBER_OF_UE_MAX*MAX_NUM_CCs);
configure_linux();
mlockall(MCL_CURRENT | MCL_FUTURE);
- init_scope();
+
+ if(IS_SOFTMODEM_DOFORMS) {
+ load_softscope("nr",PHY_vars_UE_g[0][0]);
+ }
number_of_cards = 1;
for(int CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
diff --git a/executables/nr-uesoftmodem.h b/executables/nr-uesoftmodem.h
index ba293324e3b275c7caa24d27aea69426790c6974..418ed54fc6871fc7358c417dfc53bd8457836fae 100644
--- a/executables/nr-uesoftmodem.h
+++ b/executables/nr-uesoftmodem.h
@@ -4,7 +4,6 @@
#include <executables/softmodem-common.h>
#include "PHY/defs_nr_UE.h"
#include "SIMULATION/ETH_TRANSPORT/proto.h"
-#include <openair2/LAYER2/NR_MAC_gNB/mac_proto.h>
/***************************************************************************************************************************************/
/* command line options definitions, CMDLINE_XXXX_DESC macros are used to initialize paramdef_t arrays which are then used as argument
@@ -62,19 +61,11 @@
{"single-thread-disable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&single_thread_flag, defintval:1, TYPE_INT, 0}, \
{"nr-dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, iptr:(int32_t *)&nr_dlsch_demod_shift, defintval:0, TYPE_INT, 0}, \
{"A" , CONFIG_HLP_TADV, 0, uptr:&timing_advance, defintval:0, TYPE_UINT, 0}, \
- {"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:0,TYPE_UINT64, 0}, \
- {"a" , CONFIG_HLP_CHOFF, 0, iptr:&chain_offset, defintval:0, TYPE_INT, 0}, \
- {"d" , CONFIG_HLP_SOFTS, PARAMFLAG_BOOL, uptr:&do_forms, defintval:0, TYPE_INT, 0}, \
{"E" , CONFIG_HLP_TQFS, PARAMFLAG_BOOL, iptr:&threequarter_fs, defintval:0, TYPE_INT, 0}, \
{"m" , CONFIG_HLP_DLMCS, 0, uptr:&target_dl_mcs, defintval:0, TYPE_UINT, 0}, \
{"t" , CONFIG_HLP_ULMCS, 0, uptr:&target_ul_mcs, defintval:0, TYPE_UINT, 0}, \
- {"q" , CONFIG_HLP_STMON, PARAMFLAG_BOOL, iptr:&opp_enabled, defintval:0, TYPE_INT, 0}, \
{"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, iptr:&tddflag, defintval:0, TYPE_INT, 0}, \
{"V" , CONFIG_HLP_VCD, PARAMFLAG_BOOL, iptr:&vcdflag, defintval:0, TYPE_INT, 0}, \
- {"numerology" , CONFIG_HLP_NUMEROLOGY, 0, iptr:&numerology, defintval:0, TYPE_INT, 0}, \
- {"emulate-rf" , CONFIG_HLP_EMULATE_RF, PARAMFLAG_BOOL, iptr:&emulate_rf, defintval:0, TYPE_INT, 0}, \
- {"parallel-config", CONFIG_HLP_PARALLEL_CMD,0, strptr:(char **)¶llel_config, defstrval:NULL, TYPE_STRING, 0}, \
- {"worker-config", CONFIG_HLP_WORKER_CMD, 0, strptr:(char **)&worker_config, defstrval:NULL, TYPE_STRING, 0}, \
{"s" , CONFIG_HLP_SNR, 0, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0}, \
{"nbiot-disable", CONFIG_HLP_DISABLNBIOT, PARAMFLAG_BOOL, iptr:&nonbiotflag, defintval:0, TYPE_INT, 0}, \
{"ue-timing-correction-disable", CONFIG_HLP_DISABLETIMECORR, PARAMFLAG_BOOL, iptr:&UE_no_timing_correction, defintval:0, TYPE_INT, 0}, \
diff --git a/executables/softmodem-common.h b/executables/softmodem-common.h
index 0ac7b6449e553ed8fce94dc99ff6d35bed579815..449d2e095765d01b5e4544e3d60d2b6f77c130c3 100644
--- a/executables/softmodem-common.h
+++ b/executables/softmodem-common.h
@@ -55,6 +55,7 @@ extern "C"
#define CONFIG_HLP_DUMPFRAME "dump UE received frame to rxsig_frame0.dat and exit\n"
#define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n"
#define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n"
+#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n"
#define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n"
#define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0"
#define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n"
@@ -97,6 +98,7 @@ extern "C"
#define SPLIT73 softmodem_params.split73
#define TP_CONFIG softmodem_params.threadPoolConfig
#define PHY_TEST softmodem_params.phy_test
+#define DO_RA softmodem_params.do_ra
#define WAIT_FOR_SYNC softmodem_params.wait_for_sync
#define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag
#define CHAIN_OFFSET softmodem_params.chain_offset
@@ -114,6 +116,7 @@ extern "C"
{"split73", CONFIG_HLP_SPLIT73, 0, strptr:(char **)&SPLIT73, defstrval:NULL, TYPE_STRING, sizeof(SPLIT73)},\
{"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \
{"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \
+ {"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, iptr:&DO_RA, defintval:0, TYPE_INT, 0}, \
{"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \
{"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \
{"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \
@@ -205,6 +208,7 @@ typedef struct {
char split73[1024];
char threadPoolConfig[1024];
int phy_test;
+ int do_ra;
uint8_t usim_test;
int emulate_rf;
int wait_for_sync; //eNodeB only
diff --git a/executables/split_headers.h b/executables/split_headers.h
index 4e328f74c418c7f902014b99630dd4fbe2130e7a..dc451773c5bf887030ded0c2a691f4473b0d7032 100644
--- a/executables/split_headers.h
+++ b/executables/split_headers.h
@@ -28,6 +28,7 @@
#include <stdint.h>
#include <stdbool.h>
#include <openair1/PHY/defs_eNB.h>
+#include <common/utils/telnetsrv/telnetsrv_proccmd.h>
#define CU_PORT "7878"
#define DU_PORT "8787"
@@ -279,7 +280,7 @@ int init_rf(RU_t *ru);
void rx_rf(RU_t *ru, L1_rxtx_proc_t *proc);
void tx_rf(RU_t *ru, L1_rxtx_proc_t *proc);
void common_signal_procedures (PHY_VARS_eNB *eNB,int frame, int subframe);
-void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc);
+void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, int fembms_flag);
bool dlsch_procedures(PHY_VARS_eNB *eNB,
L1_rxtx_proc_t *proc,
int harq_pid,
@@ -325,5 +326,6 @@ void fep_full(RU_t *ru, int subframe);
void feptx_prec(RU_t *ru,int frame,int subframe);
void feptx_ofdm(RU_t *ru, int frame, int subframe);
void oai_subframe_ind(uint16_t sfn, uint16_t sf);
+void softmodem_printresources(int sig, telnet_printfunc_t pf);
extern uint16_t sf_ahead;
#endif
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
index cbcd26c3e352ba2c9679dbbf4c2f55319577a3ab..e1d06335f54c540ae4c536ee2d1dd90bab06686d 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
@@ -18,6 +18,7 @@
#define FAPI_NR_RX_PDU_TYPE_SIB 0x02
#define FAPI_NR_RX_PDU_TYPE_DLSCH 0x03
#define FAPI_NR_DCI_IND 0x04
+#define FAPI_NR_RX_PDU_TYPE_RAR 0x05
#define FAPI_NR_SIBS_MASK_SIB1 0x1
@@ -42,6 +43,7 @@
#define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
+#define FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH 0x03
#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
index 576144e1df9508bdf4c5e78aeb2028a98b5642fe..246ab13e866c9d4df2671d5e914f08d5abd4430f 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
@@ -22,6 +22,8 @@
#include "fapi_nr_ue_constants.h"
#include "PHY/impl_defs_nr.h"
+#define NFAPI_UE_MAX_NUM_CB 8
+
/*
typedef unsigned int uint32_t;
typedef unsigned short uint16_t;
@@ -60,7 +62,7 @@ typedef struct {
uint8_t CoreSetType;
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
-
+ uint16_t scrambling_rnti;
uint8_t tci_state_pdcch;
uint8_t tci_present_in_dci;
} fapi_nr_coreset_t;
@@ -156,22 +158,29 @@ typedef struct {
fapi_nr_tx_request_body_t *tx_request_body;
} fapi_nr_tx_request_t;
- typedef struct {
- uint8_t preamble_index;
- uint8_t prach_configuration_index;
- uint16_t preamble_length;
- uint8_t power_ramping_step;
- uint16_t preamble_received_target_power;
- uint8_t msg1_fdm;
- uint8_t msg1_frequency_start;
- uint8_t zero_correlation_zone_config;
- uint8_t subcarrier_spacing;
- uint8_t restrictedset_config;
- uint16_t root_sequence_index;
- uint16_t rsrp_threshold_ssb;
- uint16_t rsrp_threshold_sul;
- uint16_t prach_freq_offset;
- } fapi_nr_ul_config_prach_pdu;
+/// This struct replaces:
+/// PRACH-ConfigInfo from 38.331 RRC spec
+/// PRACH-ConfigSIB or PRACH-Config
+typedef struct {
+ /// PHY cell ID
+ uint16_t phys_cell_id;
+ /// Num PRACH occasions
+ uint8_t num_prach_ocas;
+ /// PRACH format
+ uint8_t prach_format;
+ /// Num RA
+ uint8_t num_ra;
+ uint8_t prach_start_symbol;
+ /// 38.211 (NCS 38.211 6.3.3.1).
+ uint16_t num_cs;
+ /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2).
+ uint16_t root_seq_id;
+ /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set.
+ uint8_t restricted_set;
+ /// see TS 38.211 (6.3.3.2).
+ uint16_t freq_msg1;
+ // nfapi_nr_ul_beamforming_t beamforming;
+} fapi_nr_ul_config_prach_pdu;
typedef struct {
@@ -256,40 +265,124 @@ typedef struct {
} fapi_nr_ul_config_pucch_pdu;
- typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t;
- typedef struct{
- uint8_t aperiodicSRS_ResourceTrigger;
- } fapi_nr_ul_srs_config_t;
- typedef struct {
- uint8_t bandwidth_part_ind;
- uint16_t number_rbs;
- uint16_t start_rb;
- uint8_t frame_offset;
- uint16_t number_symbols;
- uint16_t start_symbol;
- pusch_freq_hopping_t pusch_freq_hopping;
- uint8_t mcs;
- uint8_t ndi;
- uint8_t rv;
- uint8_t harq_process_nbr;
- int8_t accumulated_delta_PUSCH;
- int8_t absolute_delta_PUSCH;
- uint8_t n_layers;
- uint8_t tpmi;
- uint8_t n_dmrs_cdm_groups;
- uint8_t dmrs_ports[4];
- uint8_t n_front_load_symb;
- fapi_nr_ul_srs_config_t srs_config;
- uint8_t csi_reportTriggerSize;
- uint8_t maxCodeBlockGroupsPerTransportBlock;
- uint8_t ptrs_dmrs_association_port;
- uint8_t beta_offset_ind;
- } fapi_nr_ul_config_pusch_pdu_rel15_t;
+typedef struct
+{
+ uint8_t rv_index;
+ uint8_t harq_process_id;
+ uint8_t new_data_indicator;
+ uint32_t tb_size;
+ uint16_t num_cb;
+ uint8_t cb_present_and_position[(NFAPI_UE_MAX_NUM_CB+7) / 8];
-typedef struct {
+} nfapi_nr_ue_pusch_data_t;
+
+typedef struct
+{
+ uint16_t harq_ack_bit_length;
+ uint16_t csi_part1_bit_length;
+ uint16_t csi_part2_bit_length;
+ uint8_t alpha_scaling;
+ uint8_t beta_offset_harq_ack;
+ uint8_t beta_offset_csi1;
+ uint8_t beta_offset_csi2;
+
+} nfapi_nr_ue_pusch_uci_t;
+
+typedef struct
+{
+ uint16_t ptrs_port_index;//PT-RS antenna ports [TS38.214, sec6.2.3.1 and 38.212, section 7.3.1.1.2] Bitmap occupying the 12 LSBs with: bit 0: antenna port 0 bit 11: antenna port 11 and for each bit 0: PTRS port not used 1: PTRS port used
+ uint8_t ptrs_dmrs_port;//DMRS port corresponding to PTRS.
+ uint8_t ptrs_re_offset;//PT-RS resource element offset value taken from 0~11
+} nfapi_nr_ue_ptrs_ports_t;
+
+typedef struct
+{
+ uint8_t num_ptrs_ports;
+ nfapi_nr_ue_ptrs_ports_t* ptrs_ports_list;
+ uint8_t ptrs_time_density;
+ uint8_t ptrs_freq_density;
+ uint8_t ul_ptrs_power;
+
+}nfapi_nr_ue_pusch_ptrs_t;
+
+typedef struct
+{
+ uint8_t low_papr_group_number;//Group number for Low PAPR sequence generation.
+ uint16_t low_papr_sequence_number;//[TS38.211, sec 5.2.2] For DFT-S-OFDM.
+ uint8_t ul_ptrs_sample_density;//Number of PTRS groups [But I suppose this sentence is misplaced, so as the next one. --Chenyu]
+ uint8_t ul_ptrs_time_density_transform_precoding;//Number of samples per PTRS group
+
+} nfapi_nr_ue_dfts_ofdm_t;
+
+typedef struct
+{
+ uint16_t beam_idx;//Index of the digital beam weight vector pre-stored at cell configuration. The vector maps this input port to output TXRUs. Value: 0->65535
+
+}nfapi_nr_ue_dig_bf_interface_t;
+
+typedef struct
+{
+ nfapi_nr_ue_dig_bf_interface_t* dig_bf_interface_list;
+
+} nfapi_nr_ue_ul_beamforming_number_of_prgs_t;
+
+typedef struct
+{
+ uint16_t num_prgs;
+ uint16_t prg_size;
+ //watchout: dig_bf_interface here, in table 3-43 it's dig_bf_interfaces
+ uint8_t dig_bf_interface;
+ nfapi_nr_ue_ul_beamforming_number_of_prgs_t* prgs_list;//
+
+} nfapi_nr_ue_ul_beamforming_t;
+
+typedef struct
+{
+ uint16_t pdu_bit_map;//Bitmap indicating presence of optional PDUs (see above)
uint16_t rnti;
- fapi_nr_ul_config_pusch_pdu_rel15_t ulsch_pdu_rel15;
-} fapi_nr_ul_config_pusch_pdu;
+ uint32_t handle;//An opaque handling returned in the RxData.indication and/or UCI.indication message
+ //BWP
+ uint16_t bwp_size;
+ uint16_t bwp_start;
+ uint8_t subcarrier_spacing;
+ uint8_t cyclic_prefix;
+ //pusch information always include
+ uint16_t target_code_rate;
+ uint8_t qam_mod_order;
+ uint8_t mcs_index;
+ uint8_t mcs_table;
+ uint8_t transform_precoding;
+ uint16_t data_scrambling_id;
+ uint8_t nrOfLayers;
+ //DMRS
+ uint16_t ul_dmrs_symb_pos;
+ uint8_t dmrs_config_type;
+ uint16_t ul_dmrs_scrambling_id;
+ uint8_t scid;
+ uint8_t num_dmrs_cdm_grps_no_data;
+ uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
+ //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
+ uint8_t resource_alloc;
+ uint8_t rb_bitmap[36];//
+ uint16_t rb_start;
+ uint16_t rb_size;
+ uint8_t vrb_to_prb_mapping;
+ uint8_t frequency_hopping;
+ uint16_t tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE]
+ uint8_t uplink_frequency_shift_7p5khz;
+ //Resource Allocation in time domain
+ uint8_t start_symbol_index;
+ uint8_t nr_of_symbols;
+ //Optional Data only included if indicated in pduBitmap
+ nfapi_nr_ue_pusch_data_t pusch_data;
+ nfapi_nr_ue_pusch_uci_t pusch_uci;
+ nfapi_nr_ue_pusch_ptrs_t pusch_ptrs;
+ nfapi_nr_ue_dfts_ofdm_t dfts_ofdm;
+ //beamforming
+ nfapi_nr_ue_ul_beamforming_t beamforming;
+ //OAI specific
+ int8_t absolute_delta_PUSCH;
+} nfapi_nr_ue_pusch_pdu_t;
typedef struct {
@@ -300,7 +393,7 @@ typedef struct {
union {
fapi_nr_ul_config_prach_pdu prach_config_pdu;
fapi_nr_ul_config_pucch_pdu pucch_config_pdu;
- fapi_nr_ul_config_pusch_pdu ulsch_config_pdu;
+ nfapi_nr_ue_pusch_pdu_t pusch_config_pdu;
fapi_nr_ul_config_srs_pdu srs_config_pdu;
};
} fapi_nr_ul_config_request_pdu_t;
@@ -341,7 +434,6 @@ typedef struct {
uint8_t SubcarrierSpacing;
uint16_t number_rbs;
uint16_t start_rb;
- uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint16_t dlDmrsSymbPos;
diff --git a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
index 8a25a04f7bd2953ddaae0646b474f0c82190bc93..f84917f12e4bc8bc4057e39762bb0c3d98f90a31 100644
--- a/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
+++ b/nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface_scf.h
@@ -19,6 +19,7 @@
#define NFAPI_MAX_NUM_UL_UE_PER_GROUP 6
#define NFAPI_MAX_NUM_UL_PDU 8
+#define NFAPI_MAX_NUM_UCI_INDICATION 8
#define NFAPI_MAX_NUM_GROUPS 8
#define NFAPI_MAX_NUM_CB 8
@@ -85,7 +86,7 @@ typedef enum {
NFAPI_NR_PHY_MSG_TYPE_CRC_INDICATION= 0X86,
NFAPI_NR_PHY_MSG_TYPE_UCI_INDICATION= 0X87,
NFAPI_NR_PHY_MSG_TYPE_SRS_INDICATION= 0X88,
- NFAPI_NR_PHY_MSG_TYPE_PACH_INDICATION= 0X89
+ NFAPI_NR_PHY_MSG_TYPE_RACH_INDICATION= 0X89
//RESERVED 0X8a ~ 0xff
} nfapi_nr_phy_msg_type_e;
@@ -363,7 +364,7 @@ typedef struct
//table 3-22
typedef struct
{
- nfapi_uint8_tlv_t phy_cell_id;//Physical Cell ID, ð‘_{ð¼ð·}^{ð‘ð‘’ð‘™ð‘™} [38.211, sec 7.4.2.1] Value: 0 ->1007
+ nfapi_uint16_tlv_t phy_cell_id;//Physical Cell ID, ð‘_{ð¼ð·}^{ð‘ð‘’ð‘™ð‘™} [38.211, sec 7.4.2.1] Value: 0 ->1007
nfapi_uint8_tlv_t frame_duplex_type;//Frame duplex type Value: 0 = FDD 1 = TDD
} nfapi_nr_cell_config_t;
@@ -622,22 +623,35 @@ typedef struct {
//table 3-37
-#define DCI_PAYLOAD_BTYE_LEN 12 //? TS38.212 sec 7.3.1
+#define DCI_PAYLOAD_BYTE_LEN 8 // 12 ? TS38.212 sec 7.3.1
+#define MAX_DCI_CORESET 8
-typedef struct
-{
- uint16_t rnti;//
- uint16_t scrambling_id;//
- uint16_t scrambling_rnti;/* */
- uint8_t cce_index;//
- uint8_t aggregation_level;//
- nfapi_nr_tx_precoding_and_beamforming_t* precoding_and_beamforming_list;
- //tx power info
- uint8_t beta_pdcch_1_0;/*PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of
-SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 */
- uint8_t power_control_offset_ss;//PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB, 1: 0dB, 2: 3dB, 3: 6dB
- uint16_t payload_size_bits;//The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0-> DCI_PAYLOAD_BTYE_LEN*8
- uint8_t payload[DCI_PAYLOAD_BTYE_LEN];//DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
+typedef struct {
+ // The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
+ uint16_t RNTI[MAX_DCI_CORESET];
+ // For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured,
+ // otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
+ uint16_t ScramblingId[MAX_DCI_CORESET];
+ // For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI.
+ // Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
+ uint16_t ScramblingRNTI[MAX_DCI_CORESET];
+ // CCE start Index used to send the DCI Value: 0->135
+ uint8_t CceIndex[MAX_DCI_CORESET];
+ // Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
+ uint8_t AggregationLevel[MAX_DCI_CORESET];
+ // Precoding and Beamforming structure See Table 3-43
+ nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
+ // PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI.
+ // This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1]
+ // Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
+ uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
+ // PDCCH power value used for all other PDCCH Formats.
+ // This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
+ uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
+ // The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8
+ uint16_t PayloadSizeBits[MAX_DCI_CORESET];
+ // DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
+ uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_dci_pdu_t;
@@ -652,9 +666,6 @@ typedef struct {
uint16_t *beamIdx[275];
} nr_beamforming_t;
-#define MAX_DCI_CORESET 8
-#define DCI_PAYLOAD_BYTE_LEN 8
-
typedef struct {
///Bandwidth part size [TS38.213 sec12]. Number of contiguous PRBs allocated to the BWP,Value: 1->275
uint16_t BWPSize;
@@ -684,26 +695,8 @@ typedef struct {
uint8_t precoderGranularity;
///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot
uint16_t numDlDci;
- ///The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
- uint16_t RNTI[MAX_DCI_CORESET];
- ///For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
- uint16_t ScramblingId[MAX_DCI_CORESET];
- ///For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
- uint16_t ScramblingRNTI[MAX_DCI_CORESET];
- ///CCE start Index used to send the DCI Value: 0->135
- uint8_t CceIndex[MAX_DCI_CORESET];
- ///Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
- uint8_t AggregationLevel[MAX_DCI_CORESET];
- ///Precoding and Beamforming structure See Table 3-43
- nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET];
- ///PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
- uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET];
- ///PDCCH power value used for all other PDCCH Formats. This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
- uint8_t powerControlOffsetSS[MAX_DCI_CORESET];
-///The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BTYE_LEN*8
- uint16_t PayloadSizeBits[MAX_DCI_CORESET];
- ///DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
- uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN];
+ ///DL DCI PDU
+ nfapi_nr_dl_dci_pdu_t dci_pdu;
} nfapi_nr_dl_tti_pdcch_pdu_rel15_t;
typedef struct {
@@ -1036,10 +1029,12 @@ typedef struct
{
uint16_t phys_cell_id;
uint8_t num_prach_ocas;
+ // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities
+ // We added 9 = A1/B1 10 = A2/B2 11 A3/B3
uint8_t prach_format;
uint8_t num_ra;
uint8_t prach_start_symbol;
- uint16_t num_cs;//
+ uint16_t num_cs;
nfapi_nr_ul_beamforming_t beamforming;
} nfapi_nr_prach_pdu_t;
@@ -1125,6 +1120,7 @@ typedef struct
uint16_t ul_dmrs_symb_pos;
uint8_t dmrs_config_type;
uint16_t ul_dmrs_scrambling_id;
+ uint16_t pusch_identity;
uint8_t scid;
uint8_t num_dmrs_cdm_grps_no_data;
uint16_t dmrs_ports;//DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
@@ -1497,7 +1493,7 @@ typedef struct
//for dci_pusch_pdu
typedef struct
{
- uint8_t pdu_bit_map;
+ uint8_t pduBitmap;
uint32_t handle;
uint16_t rnti;
uint8_t ul_cqi;
@@ -1512,15 +1508,15 @@ typedef struct
//for PUCCH PDU Format 0/1
typedef struct
{
- uint8_t pdu_bit_map;
+ uint8_t pduBitmap;
uint32_t handle;
uint16_t rnti;
uint8_t pucch_format;//PUCCH format Value: 0 -> 1 0: PUCCH Format0 1: PUCCH Format1
uint8_t ul_cqi;
uint16_t timing_advance;
uint16_t rssi;
- nfapi_nr_sr_pdu_0_1_t sr;//67
- nfapi_nr_harq_pdu_0_1_t harq;//68
+ nfapi_nr_sr_pdu_0_1_t *sr;//67
+ nfapi_nr_harq_pdu_0_1_t *harq;//68
}nfapi_nr_uci_pucch_pdu_format_0_1_t;
@@ -1528,7 +1524,7 @@ typedef struct
//PUCCH PDU Format 2/3/4
typedef struct
{
- uint8_t pdu_bit_map;
+ uint8_t pduBitmap;
uint32_t handle;
uint16_t rnti;
uint8_t pucch_format;//PUCCH format Value: 0 -> 2 0: PUCCH Format2 1: PUCCH Format3 2: PUCCH Format4
@@ -1542,28 +1538,22 @@ typedef struct
}nfapi_nr_uci_pucch_pdu_format_2_3_4_t;
-//for SR, HARQ and CSI Part 1/ 2 PDUs
-
-typedef struct
-{
- nfapi_nr_uci_pusch_pdu_t* pusch_pdu;
- nfapi_nr_uci_pucch_pdu_format_0_1_t* pucch_pdu_format_0_1;
- nfapi_nr_uci_pucch_pdu_format_2_3_4_t* pucch_pdu_format_2_3_4;
- nfapi_nr_sr_pdu_0_1_t* sr_pdu_0_1;
- nfapi_nr_sr_pdu_2_3_4_t* sr_pdu_2_3_4;
- nfapi_nr_harq_pdu_0_1_t* harq_pdu_0_1;
- nfapi_nr_harq_pdu_2_3_4_t* harq_pdu_2_3_4;
- nfapi_nr_csi_part1_pdu_t* csi_part1_pdu;
- nfapi_nr_csi_part2_pdu_t* csi_part2_pdu;
-
-} nfapi_nr_uci_pdu_information_t;
+typedef enum {
+ NFAPI_NR_UCI_PDCCH_PDU_TYPE = 0,
+ NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE = 1,
+ NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE = 2,
+} nfapi_nr_uci_pdu_type_e;
typedef struct
{
- uint16_t pdu_type;
+ uint16_t pdu_type; // 0 for PDU on PUSCH, 1 for PUCCH format 0 or 1, 2 for PUCCH format 2 to 4
uint16_t pdu_size;
- nfapi_nr_uci_pdu_information_t uci_pdu;
-
+ union
+ {
+ nfapi_nr_uci_pusch_pdu_t pusch_pdu;
+ nfapi_nr_uci_pucch_pdu_format_0_1_t pucch_pdu_format_0_1;
+ nfapi_nr_uci_pucch_pdu_format_2_3_4_t pucch_pdu_format_2_3_4;
+ };
} nfapi_nr_uci_t;
typedef struct
@@ -1571,7 +1561,7 @@ typedef struct
uint16_t sfn;
uint16_t slot;
uint16_t num_ucis;
- nfapi_nr_uci_t* uci_list;
+ nfapi_nr_uci_t *uci_list;
} nfapi_nr_uci_indication_t;
diff --git a/nfapi/open-nFAPI/nfapi/src/nfapi.c b/nfapi/open-nFAPI/nfapi/src/nfapi.c
index 156a48ec05dd9d8504d7be28d67a1cfbfc3dfc64..61c6875bc642c4866ac0cd2903b61424c5e9c270 100644
--- a/nfapi/open-nFAPI/nfapi/src/nfapi.c
+++ b/nfapi/open-nFAPI/nfapi/src/nfapi.c
@@ -526,7 +526,7 @@ uint32_t pullarray8(uint8_t **in, uint8_t out[], uint32_t max_len, uint32_t len,
return 0;
}
- if((end - out) >= sizeof(uint8_t) * len)
+ if((end - (*in)) >= sizeof(uint8_t) * len)
{
memcpy(out, (*in), len);
(*in)+=len;
diff --git a/openair1/PHY/CODING/TESTBENCH/ldpctest.c b/openair1/PHY/CODING/TESTBENCH/ldpctest.c
index ce6f9996dede49d94e4f1c645455e18a3158588a..b42ac6e4c8fe21f93cb76f1c2ed396283c6bb368 100644
--- a/openair1/PHY/CODING/TESTBENCH/ldpctest.c
+++ b/openair1/PHY/CODING/TESTBENCH/ldpctest.c
@@ -27,7 +27,7 @@
#include "SIMULATION/TOOLS/sim.h"
#include "PHY/CODING/nrLDPC_extern.h"
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
-
+#include "openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h"
#define MAX_NUM_DLSCH_SEGMENTS 16
#define MAX_BLOCK_LENGTH 8448
@@ -102,7 +102,8 @@ int test_ldpc(short No_iteration,
unsigned int *crc_misses,
time_stats_t *time_optim,
time_stats_t *time_decoder,
- n_iter_stats_t *dec_iter)
+ n_iter_stats_t *dec_iter,
+ short run_cuda)
{
//clock initiate
//time_stats_t time,time_optim,tinput,tprep,tparity,toutput, time_decoder;
@@ -114,7 +115,6 @@ int test_ldpc(short No_iteration,
double sigma;
sigma = 1.0/sqrt(2*SNR);
-
opp_enabled=1;
cpu_freq_GHz = get_cpu_freq_GHz();
//short test_input[block_length];
@@ -396,16 +396,26 @@ int test_ldpc(short No_iteration,
decParams.numMaxIter=No_iteration;
decParams.outMode = nrLDPC_outMode_BIT;
//decParams.outMode =nrLDPC_outMode_LLRINT8;
-
-
- for(j=0;j<n_segments;j++) {
+#ifdef CUDA_FLAG
+ set_compact_BG(Zc,BG);
+ init_LLR_DMA_for_CUDA(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length);
+#endif
+ for(j=0;j<n_segments;j++) {
start_meas(time_decoder);
- // decode the sequence
- // decoder supports BG2, Z=128 & 256
- //esimated_output=ldpc_decoder(channel_output_fixed, block_length, No_iteration, (double)((float)nom_rate/(float)denom_rate));
- ///nrLDPC_decoder(&decParams, channel_output_fixed, estimated_output, NULL);
+#ifdef CUDA_FLAG
+ if(run_cuda){
+ n_iter = nrLDPC_decoder_LYC(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], block_length, time_decoder);
+ }
+ else{
+ // decode the sequence
+ // decoder supports BG2, Z=128 & 256
+ //esimated_output=ldpc_decoder(channel_output_fixed, block_length, No_iteration, (double)((float)nom_rate/(float)denom_rate));
+ ///nrLDPC_decoder(&decParams, channel_output_fixed, estimated_output, NULL);
n_iter = nrLDPC_decoder(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], p_nrLDPC_procBuf, p_decoder_profiler);
-
+ }
+#else
+ n_iter = nrLDPC_decoder(&decParams, (int8_t*)channel_output_fixed[j], (int8_t*)estimated_output[j], p_nrLDPC_procBuf, p_decoder_profiler);
+#endif
stop_meas(time_decoder);
}
@@ -506,6 +516,9 @@ int test_ldpc(short No_iteration,
int main(int argc, char *argv[])
{
+#ifdef CUDA_FLAG
+ warmup_for_GPU();
+#endif
unsigned int errors, errors_bit, crc_misses;
double errors_bit_uncoded;
short block_length=8448; // decoder supports length: 1201 -> 1280, 2401 -> 2560
@@ -513,6 +526,8 @@ int main(int argc, char *argv[])
short No_iteration=5;
int n_segments=1;
//double rate=0.333;
+ short run_cuda = 0;
+
int nom_rate=1;
int denom_rate=3;
double SNR0=-2.0,SNR,SNR_lin;
@@ -531,7 +546,7 @@ int main(int argc, char *argv[])
short BG=0,Zc,Kb=0;
- while ((c = getopt (argc, argv, "q:r:s:S:l:n:d:i:t:u:h")) != -1)
+ while ((c = getopt (argc, argv, "q:r:s:S:l:G:n:d:i:t:u:h")) != -1)
switch (c)
{
case 'q':
@@ -549,6 +564,10 @@ int main(int argc, char *argv[])
case 'l':
block_length = atoi(optarg);
break;
+
+ case 'G':
+ run_cuda = atoi(optarg);
+ break;
case 'n':
n_trials = atoi(optarg);
@@ -584,6 +603,7 @@ int main(int argc, char *argv[])
printf("-r Nominator rate, (1, 2, 22), Default: 1\n");
printf("-d Denominator rate, (3, 5, 25), Default: 1\n");
printf("-l Block length (l > 3840 -> BG1, rest BG2 ), Default: 8448\n");
+ printf("-G give 1 to run cuda for LDPC, Default: 0\n");
printf("-n Number of simulation trials, Default: 1\n");
//printf("-M MCS2 for TB 2\n");
printf("-s SNR per information bit (EbNo) in dB, Default: -2\n");
@@ -674,7 +694,8 @@ int main(int argc, char *argv[])
&crc_misses,
time_optim,
time_decoder,
- dec_iter);
+ dec_iter,
+ run_cuda);
printf("SNR %f, BLER %f (%u/%d)\n", SNR, (float)decoded_errors[i]/(float)n_trials, decoded_errors[i], n_trials);
printf("SNR %f, BER %f (%u/%d)\n", SNR, (float)errors_bit/(float)n_trials/(float)block_length/(double)n_segments, decoded_errors[i], n_trials);
diff --git a/openair1/PHY/CODING/TESTBENCH/polartest.c b/openair1/PHY/CODING/TESTBENCH/polartest.c
index 806d8de28ce6c12887bb65797830f76891959680..d9adf3e24f679b37f80b0643eea4c12c76595d66 100644
--- a/openair1/PHY/CODING/TESTBENCH/polartest.c
+++ b/openair1/PHY/CODING/TESTBENCH/polartest.c
@@ -12,7 +12,6 @@
#include "PHY/CODING/coding_defs.h"
#include "SIMULATION/TOOLS/sim.h"
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
-//#include "PHY/NR_TRANSPORT/nr_transport.h"
//#include "common/utils/LOG/log.h"
//#define DEBUG_DCI_POLAR_PARAMS
@@ -27,7 +26,7 @@ int main(int argc, char *argv[])
{
//Default simulation values (Aim for iterations = 1000000.)
int decoder_int16=0;
- int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, -1=UCI
+ int itr, iterations = 1000, arguments, polarMessageType = 0; //0=PBCH, 1=DCI, 2=UCI
double SNRstart = -20.0, SNRstop = 0.0, SNRinc= 0.5; //dB
double SNR, SNR_lin;
int16_t nBitError = 0; // -1 = Decoding failed (All list entries have failed the CRC checks).
@@ -42,6 +41,7 @@ int main(int argc, char *argv[])
switch (arguments) {
case 's':
SNRstart = atof(optarg);
+ SNRstop = SNRstart + 2;
break;
case 'd':
@@ -91,7 +91,7 @@ int main(int argc, char *argv[])
case 'k':
testLength=atoi(optarg);
- if (testLength < 12 || testLength > 60) {
+ if (testLength < 12 || testLength > 127) {
printf("Illegal packet bitlength %d \n",testLength);
exit(-1);
}
@@ -120,12 +120,13 @@ int main(int argc, char *argv[])
crcTableInit();
if (polarMessageType == 0) { //PBCH
- aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL;
+ aggregation_level = NR_POLAR_PBCH_AGGREGATION_LEVEL;
} else if (polarMessageType == 1) { //DCI
- coderLength = 108*aggregation_level;
- } else if (polarMessageType == -1) { //UCI
- printf("UCI testing not supported yet\n");
- exit(-1);
+ coderLength = 108*aggregation_level;
+ } else if (polarMessageType == 2) { //UCI
+ //pucch2 parameters, 1 symbol, aggregation_level = NPRB
+ AssertFatal(aggregation_level>2,"For UCI formats, aggregation (N_RB) should be > 2\n");
+ coderLength = 16*aggregation_level;
}
//Logging
diff --git a/openair1/PHY/CODING/coding_defs.h b/openair1/PHY/CODING/coding_defs.h
index 9b111309cdcfd8cb4aca31cc0d4ddf6634815c84..7f466c709723e476b8afb97c023ee1cb5dcb0410 100644
--- a/openair1/PHY/CODING/coding_defs.h
+++ b/openair1/PHY/CODING/coding_defs.h
@@ -382,12 +382,24 @@ unsigned int crc16 (unsigned char * inptr, int bitlen);
@param bitlen length of inputs in bits*/
unsigned int crc12 (unsigned char * inptr, int bitlen);
+/*!\fn uint32_t crc12(uint8_t *inPtr, int32_t bitlen)
+\brief This computes an 11-bit crc based on 3GPP NR specifications.
+@param inPtr Pointer to input byte stream
+@param bitlen length of inputs in bits*/
+unsigned int crc11 (unsigned char * inptr, int bitlen);
+
/*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen)
\brief This computes a 8-bit crc based on 3GPP UMTS specifications.
@param inPtr Pointer to input byte stream
@param bitlen length of inputs in bits*/
unsigned int crc8 (unsigned char * inptr, int bitlen);
+/*!\fn uint32_t crc8(uint8_t *inPtr, int32_t bitlen)
+\brief This computes a 6-bit crc based on 3GPP NR specifications.
+@param inPtr Pointer to input byte stream
+@param bitlen length of inputs in bits*/
+unsigned int crc6 (unsigned char * inptr, int bitlen);
+
int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type);
/*!\fn void phy_viterbi_dot11_sse2(int8_t *y, uint8_t *decoded_bytes, uint16_t n,int offset,int traceback)
@@ -463,6 +475,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t nb_symb_sch,
uint16_t nb_dmrs_prb,
uint16_t nb_rb_oh,
+ uint8_t tb_scaling,
uint8_t Nl);
uint32_t nr_compute_tbslbrm(uint16_t table,
diff --git a/openair1/PHY/CODING/crc_byte.c b/openair1/PHY/CODING/crc_byte.c
index ee5c302adb03264058bcfcf113deb5ad9719b3c9..555f314429b5636def3f9e0103764b181206e7ef 100644
--- a/openair1/PHY/CODING/crc_byte.c
+++ b/openair1/PHY/CODING/crc_byte.c
@@ -90,7 +90,9 @@ static unsigned int crc24bTable[256];
static unsigned int crc24cTable[256];
static unsigned short crc16Table[256];
static unsigned short crc12Table[256];
+static unsigned short crc11Table[256];
static unsigned char crc8Table[256];
+static unsigned char crc6Table[256];
void crcTableInit (void)
{
@@ -102,7 +104,9 @@ void crcTableInit (void)
crc24cTable[c] = crcbit (&c, 1, poly24c);
crc16Table[c] = (unsigned short) (crcbit (&c, 1, poly16) >> 16);
crc12Table[c] = (unsigned short) (crcbit (&c, 1, poly12) >> 16);
+ crc11Table[c] = (unsigned short) (crcbit (&c, 1, poly11) >> 16);
crc8Table[c] = (unsigned char) (crcbit (&c, 1, poly8) >> 24);
+ crc6Table[c] = (unsigned char) (crcbit (&c, 1, poly6) >> 24);
} while (++c);
}
@@ -207,6 +211,24 @@ crc12 (unsigned char * inptr, int bitlen)
return crc;
}
+unsigned int
+crc11 (unsigned char * inptr, int bitlen)
+{
+ int octetlen, resbit;
+ unsigned int crc = 0;
+ octetlen = bitlen / 8; /* Change in octets */
+ resbit = (bitlen % 8);
+
+ while (octetlen-- > 0) {
+ crc = (crc << 8) ^ (crc11Table[(*inptr++) ^ (crc >> 24)] << 16);
+ }
+
+ if (resbit > 0)
+ crc = (crc << resbit) ^ (crc11Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 16);
+
+ return crc;
+}
+
unsigned int
crc8 (unsigned char * inptr, int bitlen)
{
@@ -225,6 +247,24 @@ crc8 (unsigned char * inptr, int bitlen)
return crc;
}
+unsigned int
+crc6 (unsigned char * inptr, int bitlen)
+{
+ int octetlen, resbit;
+ unsigned int crc = 0;
+ octetlen = bitlen / 8; /* Change in octets */
+ resbit = (bitlen % 8);
+
+ while (octetlen-- > 0) {
+ crc = crc6Table[(*inptr++) ^ (crc >> 24)] << 24;
+ }
+
+ if (resbit > 0)
+ crc = (crc << resbit) ^ (crc8Table[((*inptr) >> (8 - resbit)) ^ (crc >> (32 - resbit))] << 24);
+
+ return crc;
+}
+
int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type)
{
uint32_t crc=0,oldcrc=0;
@@ -284,6 +324,7 @@ int check_crc(uint8_t* decoded_bytes, uint32_t n, uint32_t F, uint8_t crc_type)
AssertFatal(1,"Invalid crc_type \n");
}
+
if (crc == oldcrc)
return(1);
else
diff --git a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h
index 9053b24117eac5c7948c1f1a99f9bfa4b62fb033..d6a471388d8693bb961fc90336725d6ecda5cf1d 100644
--- a/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h
+++ b/openair1/PHY/CODING/nrLDPC_decoder/nrLDPC_mPass.h
@@ -140,25 +140,25 @@ static inline void nrLDPC_llr2llrProcBuf(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrL
*/
static inline void nrLDPC_llr2CnProcBuf_BG1(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrLDPC_procBuf* p_procBuf, uint16_t Z)
{
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
- const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
- const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
- const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
-
- const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->posBnInCnProcBuf[0];
- const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->posBnInCnProcBuf[1];
- const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->posBnInCnProcBuf[2];
- const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->posBnInCnProcBuf[3];
- const uint8_t (*lut_posBnInCnProcBuf_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->posBnInCnProcBuf[4];
- const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->posBnInCnProcBuf[5];
- const uint8_t (*lut_posBnInCnProcBuf_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->posBnInCnProcBuf[6];
- const uint8_t (*lut_posBnInCnProcBuf_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->posBnInCnProcBuf[7];
- const uint8_t (*lut_posBnInCnProcBuf_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint8_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->posBnInCnProcBuf[8];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
+ const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
+ const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
+ const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
+
+ const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->posBnInCnProcBuf[0];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->posBnInCnProcBuf[1];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->posBnInCnProcBuf[2];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->posBnInCnProcBuf[3];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->posBnInCnProcBuf[4];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->posBnInCnProcBuf[5];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->posBnInCnProcBuf[6];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->posBnInCnProcBuf[7];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint8_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->posBnInCnProcBuf[8];
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
@@ -357,19 +357,19 @@ static inline void nrLDPC_llr2CnProcBuf_BG1(t_nrLDPC_lut* p_lut, int8_t* llr, t_
*/
static inline void nrLDPC_llr2CnProcBuf_BG2(t_nrLDPC_lut* p_lut, int8_t* llr, t_nrLDPC_procBuf* p_procBuf, uint16_t Z)
{
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
-
- const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->posBnInCnProcBuf[0];
- const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->posBnInCnProcBuf[1];
- const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->posBnInCnProcBuf[2];
- const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->posBnInCnProcBuf[3];
- const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->posBnInCnProcBuf[4];
- const uint8_t (*lut_posBnInCnProcBuf_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint8_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->posBnInCnProcBuf[5];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
+
+ const uint8_t (*lut_posBnInCnProcBuf_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->posBnInCnProcBuf[0];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->posBnInCnProcBuf[1];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->posBnInCnProcBuf[2];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->posBnInCnProcBuf[3];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->posBnInCnProcBuf[4];
+ const uint8_t (*lut_posBnInCnProcBuf_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint8_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->posBnInCnProcBuf[5];
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
@@ -496,26 +496,26 @@ static inline void nrLDPC_cn2bnProcBuf_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
-
- const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
- const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
- const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
- const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
- const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
- const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
-
- const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0];
- const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
- const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
- const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
- const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
- const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
+
+ const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
+
+ const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
int8_t* cnProcBufRes = p_procBuf->cnProcBufRes;
int8_t* bnProcBuf = p_procBuf->bnProcBuf;
@@ -639,34 +639,34 @@ static inline void nrLDPC_cn2bnProcBuf_BG1(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
- const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
- const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
- const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
-
- const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
- const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
- const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
- const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
- const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
- const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
- const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6];
- const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7];
- const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8];
-
- const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
- const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
- const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
- const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
- const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
- const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6];
- const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7];
- const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
+ const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
+ const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
+ const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
+
+ const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8];
+
+ const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8];
int8_t* cnProcBufRes = p_procBuf->cnProcBufRes;
int8_t* bnProcBuf = p_procBuf->bnProcBuf;
@@ -837,26 +837,26 @@ static inline void nrLDPC_bn2cnProcBuf_BG2(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
-
- const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
- const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
- const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
- const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
- const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
- const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
-
- const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0];
- const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
- const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
- const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
- const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
- const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG2_R15[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG2_R15[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG2_R15[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG2_R15[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG2_R15[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG10) [lut_numCnInCnGroups_BG2_R15[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG2_R15[5]]) p_lut->circShift[5];
+
+ const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
+
+ const uint8_t (*lut_bnPosBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint8_t(*)[lut_numCnInCnGroups[0]]) p_lut->bnPosBnProcBuf[0];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG10) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
int8_t* cnProcBuf = p_procBuf->cnProcBuf;
int8_t* bnProcBufRes = p_procBuf->bnProcBufRes;
@@ -979,34 +979,34 @@ static inline void nrLDPC_bn2cnProcBuf_BG1(t_nrLDPC_lut* p_lut, t_nrLDPC_procBuf
const uint8_t* lut_numCnInCnGroups = p_lut->numCnInCnGroups;
const uint32_t* lut_startAddrCnGroups = p_lut->startAddrCnGroups;
- const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
- const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
- const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
- const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
- const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
- const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
- const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
- const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
- const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
-
- const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
- const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
- const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
- const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
- const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
- const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
- const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6];
- const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7];
- const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8];
-
- const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
- const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
- const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
- const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
- const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
- const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6];
- const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7];
- const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8];
+ const uint16_t (*lut_circShift_CNG3) [lut_numCnInCnGroups_BG1_R13[0]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[0]]) p_lut->circShift[0];
+ const uint16_t (*lut_circShift_CNG4) [lut_numCnInCnGroups_BG1_R13[1]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[1]]) p_lut->circShift[1];
+ const uint16_t (*lut_circShift_CNG5) [lut_numCnInCnGroups_BG1_R13[2]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[2]]) p_lut->circShift[2];
+ const uint16_t (*lut_circShift_CNG6) [lut_numCnInCnGroups_BG1_R13[3]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[3]]) p_lut->circShift[3];
+ const uint16_t (*lut_circShift_CNG7) [lut_numCnInCnGroups_BG1_R13[4]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[4]]) p_lut->circShift[4];
+ const uint16_t (*lut_circShift_CNG8) [lut_numCnInCnGroups_BG1_R13[5]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[5]]) p_lut->circShift[5];
+ const uint16_t (*lut_circShift_CNG9) [lut_numCnInCnGroups_BG1_R13[6]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[6]]) p_lut->circShift[6];
+ const uint16_t (*lut_circShift_CNG10)[lut_numCnInCnGroups_BG1_R13[7]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[7]]) p_lut->circShift[7];
+ const uint16_t (*lut_circShift_CNG19)[lut_numCnInCnGroups_BG1_R13[8]] = (const uint16_t(*)[lut_numCnInCnGroups_BG1_R13[8]]) p_lut->circShift[8];
+
+ const uint32_t (*lut_startAddrBnProcBuf_CNG3) [lut_numCnInCnGroups[0]] = (const uint32_t(*)[lut_numCnInCnGroups[0]]) p_lut->startAddrBnProcBuf[0];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint32_t(*)[lut_numCnInCnGroups[1]]) p_lut->startAddrBnProcBuf[1];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint32_t(*)[lut_numCnInCnGroups[2]]) p_lut->startAddrBnProcBuf[2];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint32_t(*)[lut_numCnInCnGroups[3]]) p_lut->startAddrBnProcBuf[3];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint32_t(*)[lut_numCnInCnGroups[4]]) p_lut->startAddrBnProcBuf[4];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint32_t(*)[lut_numCnInCnGroups[5]]) p_lut->startAddrBnProcBuf[5];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint32_t(*)[lut_numCnInCnGroups[6]]) p_lut->startAddrBnProcBuf[6];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint32_t(*)[lut_numCnInCnGroups[7]]) p_lut->startAddrBnProcBuf[7];
+ const uint32_t (*lut_startAddrBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint32_t(*)[lut_numCnInCnGroups[8]]) p_lut->startAddrBnProcBuf[8];
+
+ const uint8_t (*lut_bnPosBnProcBuf_CNG4) [lut_numCnInCnGroups[1]] = (const uint8_t(*)[lut_numCnInCnGroups[1]]) p_lut->bnPosBnProcBuf[1];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG5) [lut_numCnInCnGroups[2]] = (const uint8_t(*)[lut_numCnInCnGroups[2]]) p_lut->bnPosBnProcBuf[2];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG6) [lut_numCnInCnGroups[3]] = (const uint8_t(*)[lut_numCnInCnGroups[3]]) p_lut->bnPosBnProcBuf[3];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG7) [lut_numCnInCnGroups[4]] = (const uint8_t(*)[lut_numCnInCnGroups[4]]) p_lut->bnPosBnProcBuf[4];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG8) [lut_numCnInCnGroups[5]] = (const uint8_t(*)[lut_numCnInCnGroups[5]]) p_lut->bnPosBnProcBuf[5];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG9) [lut_numCnInCnGroups[6]] = (const uint8_t(*)[lut_numCnInCnGroups[6]]) p_lut->bnPosBnProcBuf[6];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG10)[lut_numCnInCnGroups[7]] = (const uint8_t(*)[lut_numCnInCnGroups[7]]) p_lut->bnPosBnProcBuf[7];
+ const uint8_t (*lut_bnPosBnProcBuf_CNG19)[lut_numCnInCnGroups[8]] = (const uint8_t(*)[lut_numCnInCnGroups[8]]) p_lut->bnPosBnProcBuf[8];
int8_t* cnProcBuf = p_procBuf->cnProcBuf;
int8_t* bnProcBufRes = p_procBuf->bnProcBufRes;
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0
new file mode 100644
index 0000000000000000000000000000000000000000..3223238db843f5e24bbd613e72e6c2f246e6fe62
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I0
@@ -0,0 +1,48 @@
+int h_base_0 [46*68] = {
+ 250, 69, 226, 159, -1, 100, 10, -1, -1, 59, 229, 110, 191, 9, -1, 195, 23, -1, 190, 35, 239, 31, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 2, -1, 239, 117, 124, 71, -1, 222, 104, 173, -1, 220, 102, -1, 109, 132, 142, 155, -1, 255, -1, 28, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 106, 111, 185, -1, 63, 117, 93, 229, 177, 95, 39, -1, -1, 142, 225, 225, -1, 245, 205, 251, 117, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 121, 89, -1, 84, 20, -1, 150, 131, 243, -1, 136, 86, 246, 219, 211, -1, 240, 76, 244, -1, 144, 12, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 157, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 205, 236, -1, 194, -1, -1, -1, -1, -1, -1, -1, -1, 231, -1, -1, -1, 28, -1, -1, -1, -1, 123, 115, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 183, -1, -1, -1, -1, -1, 22, -1, -1, -1, 28, 67, -1, 244, -1, -1, -1, 11, 157, -1, 211, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 220, 44, -1, -1, 159, -1, -1, 31, 167, -1, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 112, 4, -1, 7, -1, -1, -1, -1, -1, -1, -1, -1, 211, -1, -1, -1, 102, -1, -1, 164, -1, 109, 241, -1, 90, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 103, 182, -1, -1, -1, -1, -1, -1, -1, -1, 109, 21, -1, 142, -1, -1, -1, 14, 61, -1, 216, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 98, 149, -1, 167, -1, -1, 160, 49, -1, -1, -1, -1, -1, 58, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 77, 41, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 83, -1, -1, -1, 182, -1, -1, -1, -1, 78, 252, 22, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 160, 42, -1, -1, -1, -1, -1, -1, -1, -1, 21, 32, -1, 234, -1, -1, -1, -1, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 177, -1, -1, 248, -1, -1, -1, 151, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 185, -1, -1, 62, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 206, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 55, -1, -1, 206, 127, 16, -1, -1, -1, 229, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 40, 96, -1, -1, -1, -1, -1, -1, -1, -1, 65, -1, -1, 63, -1, -1, -1, -1, 75, -1, -1, -1, -1, -1, -1, 179, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 64, -1, 49, -1, -1, -1, -1, -1, -1, -1, 49, -1, -1, -1, -1, -1, -1, -1, -1, 51, -1, 154, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 164, -1, 59, 1, -1, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 42, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 233, 8, -1, -1, -1, -1, 155, 147, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 60, 73, -1, -1, -1, -1, -1, 72, 127, -1, 224, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 151, -1, -1, 186, -1, -1, -1, -1, -1, 217, -1, 47, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 160, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 249, -1, -1, -1, 121, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 109, -1, -1, -1, 131, 171, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 142, 188, -1, -1, -1, 158, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 156, 147, -1, -1, -1, -1, -1, -1, -1, 170, -1, -1, -1, -1, -1, -1, -1, 152, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 112, -1, -1, 86, 236, -1, -1, -1, -1, -1, -1, 116, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 222, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 23, -1, -1, -1, -1, 136, 116, -1, -1, -1, -1, -1, -1, 182, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 195, -1, 243, -1, 215, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 61, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 25, -1, -1, -1, -1, 104, -1, 194, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 128, -1, -1, -1, 165, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 181, -1, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 86, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 236, -1, -1, -1, 84, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 216, -1, -1, -1, -1, -1, -1, -1, -1, -1, 73, -1, -1, 120, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 95, -1, -1, -1, -1, -1, 177, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 172, -1, -1, 61, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 221, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 112, -1, 199, -1, -1, -1, -1, -1, -1, -1, -1, -1, 121, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 2, 187, -1, -1, -1, -1, -1, -1, -1, -1, 41, -1, -1, -1, -1, -1, -1, -1, -1, -1, 211, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 127, -1, -1, -1, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, 164, -1, 159, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 161, -1, -1, -1, -1, 197, -1, -1, -1, -1, -1, 207, -1, -1, -1, -1, -1, -1, -1, -1, -1, 103, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 37, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 105, 51, -1, -1, 120, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 198, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 220, -1, -1, -1, -1, -1, -1, -1, -1, -1, 122, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 167, -1, -1, -1, -1, -1, -1, -1, -1, 151, 157, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 173, -1, 139, -1, -1, -1, 149, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 157, -1, -1, -1, -1, -1, -1, -1, 137, -1, -1, -1, -1, -1, -1, -1, -1, 149, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 167, -1, 173, -1, -1, -1, -1, -1, 139, -1, -1, -1, -1, -1, -1, -1, -1, 151, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 149, -1, -1, -1, 157, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 137, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 151, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 163, -1, 173, -1, -1, -1, -1, -1, -1, 139, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 139, -1, -1, -1, -1, -1, -1, 157, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 149, -1, -1, -1, -1, 151, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I1 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I1
new file mode 100644
index 0000000000000000000000000000000000000000..6137aee2f83ad91f3f13efa14524c241ab7cefd7
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I1
@@ -0,0 +1,48 @@
+int h_base_1 [46*68] = {
+ 307, 19, 50, 369, -1, 181, 216, -1, -1, 317, 288, 109, 17, 357, -1, 215, 106, -1, 242, 180, 330, 346, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 76, -1, 76, 73, 288, 144, -1, 331, 331, 178, -1, 295, 342, -1, 217, 99, 354, 114, -1, 331, -1, 112, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 205, 250, 328, -1, 332, 256, 161, 267, 160, 63, 129, -1, -1, 200, 88, 53, -1, 131, 240, 205, 13, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 276, 87, -1, 0, 275, -1, 199, 153, 56, -1, 132, 305, 231, 341, 212, -1, 304, 300, 271, -1, 39, 357, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 332, 181, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 195, 14, -1, 115, -1, -1, -1, -1, -1, -1, -1, -1, 166, -1, -1, -1, 241, -1, -1, -1, -1, 51, 157, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 278, -1, -1, -1, -1, -1, 257, -1, -1, -1, 1, 351, -1, 92, -1, -1, -1, 253, 18, -1, 225, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 9, 62, -1, -1, 316, -1, -1, 333, 290, -1, -1, -1, -1, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 307, 179, -1, 165, -1, -1, -1, -1, -1, -1, -1, -1, 18, -1, -1, -1, 39, -1, -1, 224, -1, 368, 67, -1, 170, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 366, 232, -1, -1, -1, -1, -1, -1, -1, -1, 321, 133, -1, 57, -1, -1, -1, 303, 63, -1, 82, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 101, 339, -1, 274, -1, -1, 111, 383, -1, -1, -1, -1, -1, 354, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 48, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, 47, -1, -1, -1, -1, 188, 334, 115, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 77, 186, -1, -1, -1, -1, -1, -1, -1, -1, 174, 232, -1, 50, -1, -1, -1, -1, 74, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 313, -1, -1, 177, -1, -1, -1, 266, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 115, -1, -1, 370, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 142, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 248, -1, -1, 137, 89, 347, -1, -1, -1, 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 241, 2, -1, -1, -1, -1, -1, -1, -1, -1, 210, -1, -1, 318, -1, -1, -1, -1, 55, -1, -1, -1, -1, -1, -1, 269, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 13, -1, 338, -1, -1, -1, -1, -1, -1, -1, 57, -1, -1, -1, -1, -1, -1, -1, -1, 289, -1, 57, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 260, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 303, -1, 81, 358, -1, -1, -1, 375, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 130, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 163, 280, -1, -1, -1, -1, 132, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 145, 213, -1, -1, -1, -1, -1, 344, 242, -1, 197, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 187, -1, -1, 206, -1, -1, -1, -1, -1, 264, -1, 341, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 59, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 205, -1, -1, -1, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 328, -1, -1, -1, 213, 97, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 30, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 11, 233, -1, -1, -1, 22, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 24, 89, -1, -1, -1, -1, -1, -1, -1, 61, -1, -1, -1, -1, -1, -1, -1, 27, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 298, -1, -1, 158, 235, -1, -1, -1, -1, -1, -1, 339, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 234, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 72, -1, -1, -1, -1, 17, 383, -1, -1, -1, -1, -1, -1, 312, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 71, -1, 81, -1, 76, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 136, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 194, -1, -1, -1, -1, 194, -1, 101, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 222, -1, -1, -1, 19, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 244, -1, 274, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 252, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5, -1, -1, -1, 147, -1, -1, -1, -1, -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 159, -1, -1, -1, -1, -1, -1, -1, -1, -1, 229, -1, -1, 260, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 90, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 100, -1, -1, -1, -1, -1, 215, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 258, -1, -1, 256, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 201, -1, 175, -1, -1, -1, -1, -1, -1, -1, -1, -1, 287, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 323, 8, -1, -1, -1, -1, -1, -1, -1, -1, 361, -1, -1, -1, -1, -1, -1, -1, -1, -1, 105, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 230, -1, -1, -1, -1, -1, -1, 148, -1, -1, -1, -1, -1, -1, -1, 202, -1, 312, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 320, -1, -1, -1, -1, 335, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, 266, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 313, 297, -1, -1, 21, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 269, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 82, -1, -1, -1, -1, -1, -1, -1, -1, -1, 115, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 185, -1, -1, -1, -1, -1, -1, -1, -1, 177, 289, -1, 214, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 258, -1, 93, -1, -1, -1, 346, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 297, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 175, -1, -1, -1, -1, -1, -1, -1, 37, -1, -1, -1, -1, -1, -1, -1, -1, 312, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 52, -1, 314, -1, -1, -1, -1, -1, 139, -1, -1, -1, -1, -1, -1, -1, -1, 288, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 113, -1, -1, -1, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 218, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 113, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 132, -1, 114, -1, -1, -1, -1, -1, -1, 168, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 80, -1, -1, -1, -1, -1, -1, 78, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 274, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 135, -1, -1, -1, -1, 149, -1, -1, -1, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I2 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I2
new file mode 100644
index 0000000000000000000000000000000000000000..debaee7f7e01a25dcf221da254bb0f4b737fa9e1
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I2
@@ -0,0 +1,48 @@
+int h_base_2 [46*68] = {
+ 73, 15, 103, 49, -1, 240, 39, -1, -1, 15, 162, 215, 164, 133, -1, 298, 110, -1, 113, 16, 189, 32, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 303, -1, 294, 27, 261, 161, -1, 133, 4, 80, -1, 129, 300, -1, 76, 266, 72, 83, -1, 260, -1, 301, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 68, 7, 80, -1, 280, 38, 227, 202, 200, 71, 106, -1, -1, 295, 283, 301, -1, 184, 246, 230, 276, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 220, 208, -1, 30, 197, -1, 61, 175, 79, -1, 281, 303, 253, 164, 53, -1, 44, 28, 77, -1, 319, 68, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 233, 205, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 83, 292, -1, 50, -1, -1, -1, -1, -1, -1, -1, -1, 318, -1, -1, -1, 201, -1, -1, -1, -1, 267, 279, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 289, -1, -1, -1, -1, -1, 21, -1, -1, -1, 293, 13, -1, 232, -1, -1, -1, 302, 138, -1, 235, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 12, 88, -1, -1, 207, -1, -1, 50, 25, -1, -1, -1, -1, -1, 76, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 295, 133, -1, 130, -1, -1, -1, -1, -1, -1, -1, -1, 231, -1, -1, -1, 296, -1, -1, 110, -1, 269, 245, -1, 154, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I3 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I3
new file mode 100644
index 0000000000000000000000000000000000000000..13c6ddca76efbd15f3796becf0e4b37c3a4dd451
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I3
@@ -0,0 +1,48 @@
+int h_base_3 [46*68] = {
+ 223, 16, 94, 91, -1, 74, 10, -1, -1, 0, 205, 216, 21, 215, -1, 14, 70, -1, 141, 198, 104, 81, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 141, -1, 45, 151, 46, 119, -1, 157, 133, 87, -1, 206, 93, -1, 79, 9, 118, 194, -1, 31, -1, 187, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 207, 203, 31, -1, 176, 180, 186, 95, 153, 177, 70, -1, -1, 77, 214, 77, -1, 198, 117, 223, 90, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 201, 18, -1, 165, 5, -1, 45, 142, 16, -1, 34, 155, 213, 147, 69, -1, 96, 74, 99, -1, 30, 158, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 170, 10, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 164, 59, -1, 86, -1, -1, -1, -1, -1, -1, -1, -1, 80, -1, -1, -1, 182, -1, -1, -1, -1, 130, 153, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 158, -1, -1, -1, -1, -1, 119, -1, -1, -1, 113, 21, -1, 63, -1, -1, -1, 51, 136, -1, 116, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 17, 76, -1, -1, 104, -1, -1, 100, 150, -1, -1, -1, -1, -1, 158, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 33, 95, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, 217, -1, -1, -1, 204, -1, -1, 39, -1, 58, 44, -1, 201, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 9, 37, -1, -1, -1, -1, -1, -1, -1, -1, 213, 105, -1, 89, -1, -1, -1, 185, 109, -1, 218, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 82, 165, -1, 174, -1, -1, 19, 194, -1, -1, -1, -1, -1, 103, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 52, 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, 35, -1, -1, -1, -1, 32, 84, 201, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 142, 175, -1, -1, -1, -1, -1, -1, -1, -1, 136, 3, -1, 28, -1, -1, -1, -1, 182, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 81, -1, -1, 56, -1, -1, -1, 72, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 217, -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 175, -1, -1, 211, 191, 51, -1, -1, -1, 43, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 90, 120, -1, -1, -1, -1, -1, -1, -1, -1, 131, -1, -1, 209, -1, -1, -1, -1, 209, -1, -1, -1, -1, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 154, -1, 164, -1, -1, -1, -1, -1, -1, -1, 43, -1, -1, -1, -1, -1, -1, -1, -1, 189, -1, 101, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 56, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 110, -1, 200, 63, -1, -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 199, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 110, 200, -1, -1, -1, -1, 143, 186, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 8, 6, -1, -1, -1, -1, -1, 103, 198, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 105, -1, -1, 210, -1, -1, -1, -1, -1, 121, -1, 214, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 183, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 192, -1, -1, -1, 131, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 220, -1, -1, -1, 50, 106, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 53, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 3, -1, -1, -1, 148, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 88, 203, -1, -1, -1, -1, -1, -1, -1, 168, -1, -1, -1, -1, -1, -1, -1, 122, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 49, -1, -1, 157, 64, -1, -1, -1, -1, -1, -1, 193, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 124, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 1, -1, -1, -1, -1, 166, 65, -1, -1, -1, -1, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 107, -1, 176, -1, 212, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 127, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 208, -1, -1, -1, -1, 141, -1, 174, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 146, -1, -1, -1, 153, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 217, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 150, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 11, -1, -1, -1, 53, -1, -1, -1, -1, -1, -1, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 34, -1, -1, -1, -1, -1, -1, -1, -1, -1, 130, -1, -1, 210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 123, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 175, -1, -1, -1, -1, -1, 49, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 177, -1, -1, 128, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 192, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 209, -1, 58, -1, -1, -1, -1, -1, -1, -1, -1, -1, 30, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 114, 49, -1, -1, -1, -1, -1, -1, -1, -1, 161, -1, -1, -1, -1, -1, -1, -1, -1, -1, 137, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 82, -1, -1, -1, -1, -1, -1, 186, -1, -1, -1, -1, -1, -1, -1, 68, -1, 150, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 192, -1, -1, -1, -1, 173, -1, -1, -1, -1, -1, 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, 187, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 222, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 157, 0, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 195, -1, -1, -1, -1, -1, -1, -1, -1, -1, 138, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 123, -1, -1, -1, -1, -1, -1, -1, -1, 90, 73, -1, 10, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 12, -1, 77, -1, -1, -1, 49, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 67, -1, -1, -1, -1, -1, -1, -1, 45, -1, -1, -1, -1, -1, -1, -1, -1, 96, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 23, -1, 215, -1, -1, -1, -1, -1, 60, -1, -1, -1, -1, -1, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 114, -1, -1, -1, 91, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 206, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 22, -1, 134, -1, -1, -1, -1, -1, -1, 161, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 84, -1, -1, -1, -1, -1, -1, 4, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 184, -1, -1, -1, -1, 121, -1, -1, -1, 29, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I4 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I4
new file mode 100644
index 0000000000000000000000000000000000000000..f7c89c694766353be8d02df9ad8bbe7007d82f7e
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I4
@@ -0,0 +1,48 @@
+int h_base_4 [46*68] = {
+ 211, 198, 188, 186, -1, 219, 4, -1, -1, 29, 144, 116, 216, 115, -1, 233, 144, -1, 95, 216, 73, 261, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 179, -1, 162, 223, 256, 160, -1, 76, 202, 117, -1, 109, 15, -1, 72, 152, 158, 147, -1, 156, -1, 119, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 258, 167, 220, -1, 133, 243, 202, 218, 63, 0, 3, -1, -1, 74, 229, 0, -1, 216, 269, 200, 234, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 187, 145, -1, 166, 108, -1, 82, 132, 197, -1, 41, 162, 57, 36, 115, -1, 242, 165, 0, -1, 113, 108, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 246, 235, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 261, 181, -1, 72, -1, -1, -1, -1, -1, -1, -1, -1, 283, -1, -1, -1, 254, -1, -1, -1, -1, 79, 144, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 80, -1, -1, -1, -1, -1, 144, -1, -1, -1, 169, 90, -1, 59, -1, -1, -1, 177, 151, -1, 108, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 169, 189, -1, -1, 154, -1, -1, 184, 104, -1, -1, -1, -1, -1, 164, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 54, 0, -1, 252, -1, -1, -1, -1, -1, -1, -1, -1, 41, -1, -1, -1, 98, -1, -1, 46, -1, 15, 230, -1, 54, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 162, 159, -1, -1, -1, -1, -1, -1, -1, -1, 93, 134, -1, 45, -1, -1, -1, 132, 76, -1, 209, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 178, 1, -1, 28, -1, -1, 267, 234, -1, -1, -1, -1, -1, 201, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 55, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 274, -1, -1, -1, 181, -1, -1, -1, -1, 273, 39, 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 225, 162, -1, -1, -1, -1, -1, -1, -1, -1, 244, 151, -1, 238, -1, -1, -1, -1, 243, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 231, -1, -1, 0, -1, -1, -1, 216, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 47, -1, -1, 36, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 186, -1, -1, 253, 16, 0, -1, -1, -1, 79, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 170, 0, -1, -1, -1, -1, -1, -1, -1, -1, 183, -1, -1, 108, -1, -1, -1, -1, 68, -1, -1, -1, -1, -1, -1, 64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 270, -1, 13, -1, -1, -1, -1, -1, -1, -1, 99, -1, -1, -1, -1, -1, -1, -1, -1, 54, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 153, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 137, -1, 0, 0, -1, -1, -1, 162, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 161, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 151, 0, -1, -1, -1, -1, 241, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 0, -1, -1, -1, -1, -1, 118, 144, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 265, -1, -1, 81, -1, -1, -1, -1, -1, 90, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 228, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 64, -1, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 266, -1, -1, -1, 9, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 72, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 189, 72, -1, -1, -1, 257, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 180, 0, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, 165, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 236, -1, -1, 199, 0, -1, -1, -1, -1, -1, -1, 266, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 205, -1, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, 183, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, 0, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 277, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 45, -1, -1, -1, -1, 36, -1, 72, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 275, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 155, -1, 62, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 180, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, 42, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, 90, -1, -1, 252, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 144, -1, -1, -1, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 166, -1, -1, 19, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 211, -1, 36, -1, -1, -1, -1, -1, -1, -1, -1, -1, 162, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, 76, -1, -1, -1, -1, -1, -1, -1, -1, -1, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 197, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, 108, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 199, -1, -1, -1, -1, 278, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, 205, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 216, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 16, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 72, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 190, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 153, -1, 0, -1, -1, -1, 165, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 117, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 216, -1, -1, -1, -1, -1, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 0, -1, 0, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, 183, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 27, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 35, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 243, -1, 0, -1, -1, -1, -1, -1, -1, 270, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 18, -1, -1, -1, -1, -1, -1, 0, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 57, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 168, -1, -1, -1, -1, 0, -1, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I5 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I5
new file mode 100644
index 0000000000000000000000000000000000000000..475e6a2920ac206b67379a45a0c0a85503313b9d
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I5
@@ -0,0 +1,48 @@
+int h_base_5 [46*68] = {
+ 294, 118, 167, 330, -1, 207, 165, -1, -1, 243, 250, 1, 339, 201, -1, 53, 347, -1, 304, 167, 47, 188, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 77, -1, 225, 96, 338, 268, -1, 112, 302, 50, -1, 167, 253, -1, 334, 242, 257, 133, -1, 9, -1, 302, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 226, 35, 213, -1, 302, 111, 265, 128, 237, 294, 127, -1, -1, 110, 286, 125, -1, 131, 163, 210, 7, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 97, 94, -1, 49, 279, -1, 139, 166, 91, -1, 106, 246, 345, 269, 185, -1, 249, 215, 143, -1, 121, 121, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 42, 256, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 219, 130, -1, 251, -1, -1, -1, -1, -1, -1, -1, -1, 322, -1, -1, -1, 295, -1, -1, -1, -1, 258, 283, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 294, -1, -1, -1, -1, -1, 73, -1, -1, -1, 330, 99, -1, 172, -1, -1, -1, 150, 284, -1, 305, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 3, 103, -1, -1, 224, -1, -1, 297, 215, -1, -1, -1, -1, -1, 39, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 348, 75, -1, 22, -1, -1, -1, -1, -1, -1, -1, -1, 312, -1, -1, -1, 224, -1, -1, 17, -1, 59, 314, -1, 244, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 156, 88, -1, -1, -1, -1, -1, -1, -1, -1, 293, 111, -1, 92, -1, -1, -1, 152, 23, -1, 337, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 175, 253, -1, 27, -1, -1, 231, 49, -1, -1, -1, -1, -1, 267, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 25, 322, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 200, -1, -1, -1, 351, -1, -1, -1, -1, 166, 338, 192, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 123, 217, -1, -1, -1, -1, -1, -1, -1, -1, 142, 110, -1, 176, -1, -1, -1, -1, 76, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 311, -1, -1, 251, -1, -1, -1, 265, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 94, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 22, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 322, -1, -1, 277, 156, 66, -1, -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 176, 348, -1, -1, -1, -1, -1, -1, -1, -1, 15, -1, -1, 81, -1, -1, -1, -1, 176, -1, -1, -1, -1, -1, -1, 113, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 190, -1, 293, -1, -1, -1, -1, -1, -1, -1, 332, -1, -1, -1, -1, -1, -1, -1, -1, 331, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 110, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 228, -1, 247, 116, -1, -1, -1, 190, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 47, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 286, 246, -1, -1, -1, -1, 181, 73, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 87, 110, -1, -1, -1, -1, -1, 147, 258, -1, 204, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 89, -1, -1, 65, -1, -1, -1, -1, -1, 155, -1, 244, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 30, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 162, -1, -1, -1, 264, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 346, -1, -1, -1, 143, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 280, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 157, 236, -1, -1, -1, 113, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 18, 6, -1, -1, -1, -1, -1, -1, -1, 181, -1, -1, -1, -1, -1, -1, -1, 304, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 38, -1, -1, 170, 249, -1, -1, -1, -1, -1, -1, 288, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 194, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 279, -1, -1, -1, -1, 255, 111, -1, -1, -1, -1, -1, -1, 54, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 325, -1, 326, -1, 226, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 99, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 91, -1, -1, -1, -1, 326, -1, 268, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 102, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 40, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 273, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 104, -1, -1, -1, 243, -1, -1, -1, -1, -1, -1, 107, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 171, -1, -1, -1, -1, -1, -1, -1, -1, -1, 16, -1, -1, 95, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 212, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 101, -1, -1, -1, -1, -1, 297, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 279, -1, -1, 222, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 351, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 265, -1, 338, -1, -1, -1, -1, -1, -1, -1, -1, -1, 83, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 56, 304, -1, -1, -1, -1, -1, -1, -1, -1, 141, -1, -1, -1, -1, -1, -1, -1, -1, -1, 101, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 60, -1, -1, -1, -1, -1, -1, 320, -1, -1, -1, -1, -1, -1, -1, 112, -1, 54, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 100, -1, -1, -1, -1, 210, -1, -1, -1, -1, -1, 195, -1, -1, -1, -1, -1, -1, -1, -1, -1, 268, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 135, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 15, 35, -1, -1, 188, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 319, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 236, -1, -1, -1, -1, -1, -1, -1, -1, -1, 85, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 164, -1, -1, -1, -1, -1, -1, -1, -1, 196, 209, -1, 246, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 236, -1, 264, -1, -1, -1, 37, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 272, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 304, -1, -1, -1, -1, -1, -1, -1, 237, -1, -1, -1, -1, -1, -1, -1, -1, 135, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 123, -1, 77, -1, -1, -1, -1, -1, 25, -1, -1, -1, -1, -1, -1, -1, -1, 272, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 288, -1, -1, -1, 83, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 3, -1, 53, -1, -1, -1, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 79, -1, -1, -1, -1, -1, -1, 244, -1, 293, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 272, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 82, -1, -1, -1, -1, 67, -1, -1, -1, 235, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I6 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I6
new file mode 100644
index 0000000000000000000000000000000000000000..f9500d8d045cce83ba848a1007bbd1585433c13f
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I6
@@ -0,0 +1,48 @@
+int h_base_6 [46*68] = {
+ 0, 0, 0, 0, -1, 0, 0, -1, -1, 0, 0, 0, 0, 0, -1, 0, 0, -1, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 22, -1, 11, 124, 0, 10, -1, 0, 0, 2, -1, 16, 60, -1, 0, 6, 30, 0, -1, 168, -1, 31, 105, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 132, 37, 21, -1, 180, 4, 149, 48, 38, 122, 195, -1, -1, 155, 28, 85, -1, 47, 179, 42, 66, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 4, 6, -1, 33, 113, -1, 49, 21, 6, -1, 151, 83, 154, 87, 5, -1, 92, 173, 120, -1, 2, 142, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 24, 204, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 185, 100, -1, 24, -1, -1, -1, -1, -1, -1, -1, -1, 65, -1, -1, -1, 207, -1, -1, -1, -1, 161, 72, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, -1, -1, -1, -1, -1, 27, -1, -1, -1, 163, 50, -1, 48, -1, -1, -1, 24, 38, -1, 91, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 145, 88, -1, -1, 112, -1, -1, 153, 159, -1, -1, -1, -1, -1, 76, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 172, 2, -1, 131, -1, -1, -1, -1, -1, -1, -1, -1, 141, -1, -1, -1, 96, -1, -1, 99, -1, 101, 35, -1, 116, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, 10, -1, -1, -1, -1, -1, -1, -1, -1, 145, 53, -1, 201, -1, -1, -1, 4, 164, -1, 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 126, 77, -1, 156, -1, -1, 16, 12, -1, -1, -1, -1, -1, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 184, 194, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 123, -1, -1, -1, 16, -1, -1, -1, -1, 104, 109, 124, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, 20, -1, -1, -1, -1, -1, -1, -1, -1, 203, 153, -1, 104, -1, -1, -1, -1, 207, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 52, -1, -1, 147, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 16, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 202, -1, -1, 118, 130, 1, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 173, 6, -1, -1, -1, -1, -1, -1, -1, -1, 81, -1, -1, 182, -1, -1, -1, -1, 53, -1, -1, -1, -1, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 88, -1, 198, -1, -1, -1, -1, -1, -1, -1, 160, -1, -1, -1, -1, -1, -1, -1, -1, 122, -1, 182, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 91, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 184, -1, 30, 3, -1, -1, -1, 155, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 41, 167, -1, -1, -1, -1, 68, 148, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 12, 6, -1, -1, -1, -1, -1, 166, 184, -1, 191, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, -1, -1, 12, -1, -1, -1, -1, -1, 15, -1, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 30, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 6, -1, -1, -1, 86, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 96, -1, -1, -1, 42, 199, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 44, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 58, 130, -1, -1, -1, 131, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 45, 18, -1, -1, -1, -1, -1, -1, -1, 132, -1, -1, -1, -1, -1, -1, -1, 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 9, -1, -1, 125, 191, -1, -1, -1, -1, -1, -1, 28, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 4, -1, -1, -1, -1, 74, 16, -1, -1, -1, -1, -1, -1, 28, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 21, -1, 142, -1, 192, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 197, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 98, -1, -1, -1, -1, 140, -1, 22, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 4, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 40, -1, 93, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 92, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 136, -1, -1, -1, 106, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, 88, -1, -1, 112, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 4, -1, -1, -1, -1, -1, 49, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 125, -1, -1, 194, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 126, -1, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 10, 30, -1, -1, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, 92, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 4, -1, -1, -1, -1, -1, -1, 153, -1, -1, -1, -1, -1, -1, -1, 197, -1, 155, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 4, -1, -1, -1, -1, 45, -1, -1, -1, -1, -1, 168, -1, -1, -1, -1, -1, -1, -1, -1, -1, 185, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 200, 177, -1, -1, 43, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 82, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, 135, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 91, -1, -1, -1, -1, -1, -1, -1, -1, 64, 198, -1, 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 4, -1, 28, -1, -1, -1, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 188, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 10, -1, -1, -1, -1, -1, -1, -1, 84, -1, -1, -1, -1, -1, -1, -1, -1, 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, 2, -1, 75, -1, -1, -1, -1, -1, 142, -1, -1, -1, -1, -1, -1, -1, -1, 128, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ 163, -1, -1, -1, 10, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 162, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 163, -1, 99, -1, -1, -1, -1, -1, -1, 98, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ 4, -1, -1, -1, -1, -1, -1, 6, -1, 142, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 181, -1, -1, -1, -1, 45, -1, -1, -1, 153, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I7 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I7
new file mode 100644
index 0000000000000000000000000000000000000000..aa2e90086f16e714493d4d7b9965388c996443c6
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_I7
@@ -0,0 +1,48 @@
+int h_base_7 [46*68] = {
+ 135, 227, 126, 134, -1, 84, 83, -1, -1, 53, 225, 205, 128, 75, -1, 135, 217, -1, 220, 90, 105, 137, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 96, -1, 236, 136, 221, 128, -1, 92, 172, 56, -1, 11, 189, -1, 95, 85, 153, 87, -1, 163, -1, 216, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 189, 4, 225, -1, 151, 236, 117, 179, 92, 24, 68, -1, -1, 6, 101, 33, -1, 96, 125, 67, 230, -1, -1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 128, 23, -1, 162, 220, -1, 43, 186, 96, -1, 1, 216, 22, 24, 167, -1, 200, 32, 235, -1, 172, 219, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 64, 211, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 2, 171, -1, 47, -1, -1, -1, -1, -1, -1, -1, -1, 143, -1, -1, -1, 210, -1, -1, -1, -1, 180, 180, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h
new file mode 100644
index 0000000000000000000000000000000000000000..9a6086998e0d6e8d54425f3ad99aa6b24e3fe025
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG1_compact_in_C.h
@@ -0,0 +1,478 @@
+
+h_element host_h_compact1_I0 [46*19] =
+{{0 ,0,250},{1 ,0,2},{2 ,0,106},{3 ,0,121},{4 ,0,157},{5 ,0,205},{6 ,0,183},{7 ,0,220},{8 ,0,112},{9 ,0,103},{10 ,1,98},{11 ,0,77},{12 ,0,160},{13 ,0,177},{14 ,0,206},{15 ,0,40},{16 ,1,64},{17 ,0,7},{18 ,1,42},{19 ,0,60},{20 ,0,151},{21 ,1,249},{22 ,0,64},{23 ,1,156},{24 ,0,112},{25 ,1,23},{26 ,0,195},{27 ,1,25},{28 ,0,128},{29 ,1,86},{30 ,0,216},{31 ,1,95},{32 ,0,221},{33 ,1,2},{34 ,0,127},{35 ,1,161},{36 ,0,37},{37 ,1,198},{38 ,0,167},{39 ,1,173},{40 ,0,157},{41 ,1,167},{42 ,0,149},{43 ,1,151},{44 ,0,139},{45 ,1,149},
+{0 ,1,69},{1 ,2,239},{2 ,1,111},{3 ,1,89},{4 ,1,102},{5 ,1,236},{6 ,6,22},{7 ,1,44},{8 ,1,4},{9 ,1,182},{10 ,2,149},{11 ,1,41},{12 ,1,42},{13 ,3,248},{14 ,12,55},{15 ,1,96},{16 ,3,49},{17 ,14,164},{18 ,12,233},{19 ,1,73},{20 ,3,186},{21 ,5,121},{22 ,12,142},{23 ,2,147},{24 ,3,86},{25 ,6,136},{26 ,2,243},{27 ,6,104},{28 ,4,165},{29 ,14,236},{30 ,10,73},{31 ,7,177},{32 ,12,112},{33 ,2,187},{34 ,7,167},{35 ,6,197},{36 ,14,105},{37 ,13,220},{38 ,9,151},{39 ,3,139},{40 ,8,137},{41 ,3,173},{42 ,4,157},{43 ,16,163},{44 ,7,157},{45 ,6,151},
+{0 ,2,226},{1 ,3,117},{2 ,2,185},{3 ,3,84},{4 ,26,0},{5 ,3,194},{6 ,10,28},{7 ,4,159},{8 ,3,7},{9 ,10,109},{10 ,4,167},{11 ,12,83},{12 ,10,21},{13 ,7,151},{14 ,15,206},{15 ,10,65},{16 ,11,49},{17 ,16,59},{18 ,13,8},{19 ,7,72},{20 ,9,217},{21 ,16,109},{22 ,13,188},{23 ,10,170},{24 ,4,236},{25 ,7,116},{26 ,4,215},{27 ,8,194},{28 ,19,181},{29 ,18,84},{30 ,13,120},{31 ,22,172},{32 ,14,199},{33 ,11,41},{34 ,15,164},{35 ,12,207},{36 ,15,51},{37 ,23,122},{38 ,10,157},{39 ,7,149},{40 ,17,149},{41 ,9,139},{42 ,24,137},{43 ,18,173},{44 ,9,163},{45 ,10,167},
+{0 ,3,159},{1 ,4,124},{2 ,4,63},{3 ,4,20},{0 ,0,-1},{5 ,12,231},{6 ,11,67},{7 ,7,31},{8 ,12,211},{9 ,11,21},{10 ,7,160},{11 ,16,182},{12 ,11,32},{13 ,20,185},{14 ,16,127},{15 ,13,63},{16 ,20,51},{17 ,17,1},{18 ,18,155},{19 ,8,127},{20 ,11,47},{21 ,20,131},{22 ,17,158},{23 ,18,152},{24 ,11,116},{25 ,14,182},{26 ,15,61},{27 ,49,0},{28 ,21,63},{29 ,25,6},{30 ,24,9},{31 ,25,61},{32 ,24,121},{33 ,21,211},{34 ,17,159},{35 ,22,103},{36 ,18,120},{37 ,59,0},{38 ,12,163},{39 ,19,0},{40 ,62,0},{41 ,18,151},{42 ,64,0},{43 ,25,139},{44 ,22,173},{45 ,67,0},
+{0 ,5,100},{1 ,5,71},{2 ,5,117},{3 ,6,150},{0 ,0,-1},{5 ,16,28},{6 ,13,244},{7 ,8,167},{8 ,16,102},{9 ,13,142},{10 ,8,49},{11 ,21,78},{12 ,13,234},{13 ,23,62},{14 ,17,16},{15 ,18,75},{16 ,22,154},{17 ,21,144},{18 ,19,147},{19 ,10,224},{20 ,22,160},{21 ,21,171},{22 ,44,0},{23 ,45,0},{24 ,22,222},{25 ,47,0},{26 ,48,0},{0 ,0,-1},{28 ,50,0},{29 ,51,0},{30 ,52,0},{31 ,53,0},{32 ,54,0},{33 ,55,0},{34 ,56,0},{35 ,57,0},{36 ,58,0},{0 ,0,-1},{38 ,60,0},{39 ,61,0},{0 ,0,-1},{41 ,63,0},{0 ,0,-1},{43 ,65,0},{44 ,66,0},{0 ,0,-1},
+{0 ,6,10},{1 ,7,222},{2 ,6,93},{3 ,7,131},{0 ,0,-1},{5 ,21,123},{6 ,17,11},{7 ,14,104},{8 ,19,164},{9 ,17,14},{10 ,14,58},{11 ,22,252},{12 ,18,7},{13 ,35,0},{14 ,21,229},{15 ,25,179},{16 ,38,0},{17 ,39,0},{18 ,40,0},{19 ,41,0},{20 ,42,0},{21 ,43,0},{0 ,0,-1},{0 ,0,-1},{24 ,46,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,9,59},{1 ,8,104},{2 ,7,229},{3 ,8,243},{0 ,0,-1},{5 ,22,115},{6 ,18,157},{7 ,29,0},{8 ,21,109},{9 ,18,61},{10 ,32,0},{11 ,23,22},{12 ,34,0},{0 ,0,-1},{14 ,36,0},{15 ,37,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,10,229},{1 ,9,173},{2 ,8,177},{3 ,10,136},{0 ,0,-1},{5 ,27,0},{6 ,20,211},{0 ,0,-1},{8 ,22,241},{9 ,20,216},{0 ,0,-1},{11 ,33,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,11,110},{1 ,11,220},{2 ,9,95},{3 ,11,86},{0 ,0,-1},{0 ,0,-1},{6 ,28,0},{0 ,0,-1},{8 ,24,90},{9 ,31,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,12,191},{1 ,12,102},{2 ,10,39},{3 ,12,246},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{8 ,30,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,13,9},{1 ,14,109},{2 ,13,142},{3 ,13,219},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,15,195},{1 ,15,132},{2 ,14,225},{3 ,14,211},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,16,23},{1 ,16,142},{2 ,15,225},{3 ,16,240},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,18,190},{1 ,17,155},{2 ,17,245},{3 ,17,76},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,19,35},{1 ,19,255},{2 ,18,205},{3 ,18,244},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,20,239},{1 ,21,28},{2 ,19,251},{3 ,20,144},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,21,31},{1 ,22,0},{2 ,20,117},{3 ,21,12},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,22,1},{1 ,23,0},{2 ,24,0},{3 ,22,1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{0 ,23,0},{1 ,24,0},{2 ,25,0},{3 ,25,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+};
+
+
+h_element host_h_compact2_I0 [68*30] =
+{{0 ,0,250},{0 ,1,69},{0 ,2,226},{0 ,3,159},{1 ,4,124},{0 ,5,100},{0 ,6,10},{1 ,7,222},{1 ,8,104},{0 ,9,59},{0 ,10,229},{0 ,11,110},{0 ,12,191},{0 ,13,9},{1 ,14,109},{0 ,15,195},{0 ,16,23},{1 ,17,155},{0 ,18,190},{0 ,19,35},{0 ,20,239},{0 ,21,31},{0 ,22,1},{0 ,23,0},{1 ,24,0},{2 ,25,0},{4 ,26,0},{5 ,27,0},{6 ,28,0},{7 ,29,0},{8 ,30,0},{9 ,31,0},{10 ,32,0},{11 ,33,0},{12 ,34,0},{13 ,35,0},{14 ,36,0},{15 ,37,0},{16 ,38,0},{17 ,39,0},{18 ,40,0},{19 ,41,0},{20 ,42,0},{21 ,43,0},{22 ,44,0},{23 ,45,0},{24 ,46,0},{25 ,47,0},{26 ,48,0},{27 ,49,0},{28 ,50,0},{29 ,51,0},{30 ,52,0},{31 ,53,0},{32 ,54,0},{33 ,55,0},{34 ,56,0},{35 ,57,0},{36 ,58,0},{37 ,59,0},{38 ,60,0},{39 ,61,0},{40 ,62,0},{41 ,63,0},{42 ,64,0},{43 ,65,0},{44 ,66,0},{45 ,67,0},
+{1 ,0,2},{2 ,1,111},{1 ,2,239},{1 ,3,117},{2 ,4,63},{1 ,5,71},{2 ,6,93},{2 ,7,229},{2 ,8,177},{1 ,9,173},{2 ,10,39},{1 ,11,220},{1 ,12,102},{2 ,13,142},{2 ,14,225},{1 ,15,132},{1 ,16,142},{2 ,17,245},{2 ,18,205},{1 ,19,255},{2 ,20,117},{1 ,21,28},{1 ,22,0},{1 ,23,0},{2 ,24,0},{3 ,25,0},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{2 ,0,106},{3 ,1,89},{2 ,2,185},{3 ,3,84},{3 ,4,20},{2 ,5,117},{3 ,6,150},{3 ,7,131},{3 ,8,243},{2 ,9,95},{3 ,10,136},{3 ,11,86},{3 ,12,246},{3 ,13,219},{3 ,14,211},{2 ,15,225},{3 ,16,240},{3 ,17,76},{3 ,18,244},{2 ,19,251},{3 ,20,144},{3 ,21,12},{3 ,22,1},{11 ,23,22},{8 ,24,90},{15 ,25,179},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{3 ,0,121},{4 ,1,102},{10 ,2,149},{5 ,3,194},{7 ,4,159},{21 ,5,121},{6 ,6,22},{7 ,7,31},{7 ,8,167},{20 ,9,217},{6 ,10,28},{6 ,11,67},{5 ,12,231},{6 ,13,244},{7 ,14,104},{14 ,15,206},{5 ,16,28},{6 ,17,11},{6 ,18,157},{8 ,19,164},{6 ,20,211},{5 ,21,123},{5 ,22,115},{13 ,23,62},{30 ,24,9},{29 ,25,6},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
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+};
+
+//--------------------------------------------------BG1_I0-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I1-----------------------------------------------------------------
+
+h_element host_h_compact1_I1 [46*19] =
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+};
+
+
+h_element host_h_compact2_I1 [68*30] =
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+};
+
+//--------------------------------------------------BG1_I1-----------------------------------------------------------------
+
+//--------------------------------------------------BG1_I2-----------------------------------------------------------------
+
+h_element host_h_compact1_I2 [46*19] =
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+};
+
+
+h_element host_h_compact2_I2 [68*30] =
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+};
+
+//--------------------------------------------------BG1_I2-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I3-----------------------------------------------------------------
+
+h_element host_h_compact1_I3 [46*19] =
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+};
+
+h_element host_h_compact2_I3 [68*30] =
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+};
+
+
+//--------------------------------------------------BG1_I3-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I4-----------------------------------------------------------------
+h_element host_h_compact1_I4 [46*19] =
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+};
+
+
+h_element host_h_compact2_I4 [68*30] =
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+};
+
+
+//--------------------------------------------------BG1_I4-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I5-----------------------------------------------------------------
+h_element host_h_compact1_I5 [46*19] =
+{{0 ,0,294},{1 ,0,77},{2 ,0,226},{3 ,0,97},{4 ,0,42},{5 ,0,219},{6 ,0,294},{7 ,0,3},{8 ,0,348},{9 ,0,156},{10 ,1,175},{11 ,0,25},{12 ,0,123},{13 ,0,311},{14 ,0,22},{15 ,0,176},{16 ,1,190},{17 ,0,110},{18 ,1,47},{19 ,0,87},{20 ,0,89},{21 ,1,162},{22 ,0,280},{23 ,1,18},{24 ,0,38},{25 ,1,279},{26 ,0,325},{27 ,1,91},{28 ,0,102},{29 ,1,273},{30 ,0,171},{31 ,1,101},{32 ,0,351},{33 ,1,56},{34 ,0,60},{35 ,1,100},{36 ,0,135},{37 ,1,319},{38 ,0,164},{39 ,1,236},{40 ,0,304},{41 ,1,123},{42 ,0,288},{43 ,1,210},{44 ,0,79},{45 ,1,82},
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+};
+
+
+h_element host_h_compact2_I5 [68*30] =
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+};
+//--------------------------------------------------BG1_I5-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I6-----------------------------------------------------------------
+h_element host_h_compact1_I6 [46*19] =
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+};
+
+
+h_element host_h_compact2_I6 [68*30] =
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+};
+
+//--------------------------------------------------BG1_I6-----------------------------------------------------------------
+
+
+//--------------------------------------------------BG1_I7-----------------------------------------------------------------
+h_element host_h_compact1_I7 [46*19] =
+{{0 ,0,135},{1 ,0,96},{2 ,0,189},{3 ,0,128},{4 ,0,64},{5 ,0,2},{6 ,0,199},{7 ,0,77},{8 ,0,181},{9 ,0,169},{10 ,1,116},{11 ,0,45},{12 ,0,186},{13 ,0,220},{14 ,0,124},{15 ,0,39},{16 ,1,78},{17 ,0,183},{18 ,1,183},{19 ,0,179},{20 ,0,77},{21 ,1,197},{22 ,0,25},{23 ,1,185},{24 ,0,32},{25 ,1,27},{26 ,0,163},{27 ,1,165},{28 ,0,32},{29 ,1,232},{30 ,0,170},{31 ,1,73},{32 ,0,103},{33 ,1,199},{34 ,0,161},{35 ,1,231},{36 ,0,11},{37 ,1,59},{38 ,0,121},{39 ,1,115},{40 ,0,4},{41 ,1,53},{42 ,0,222},{43 ,1,22},{44 ,0,191},{45 ,1,177},
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+};
+
+
+h_element host_h_compact2_I7 [68*30] =
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+{24 ,0,32},{29 ,1,232},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{26 ,0,163},{31 ,1,73},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{28 ,0,32},{33 ,1,199},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{30 ,0,170},{35 ,1,231},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{32 ,0,103},{37 ,1,59},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{34 ,0,161},{39 ,1,115},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{36 ,0,11},{41 ,1,53},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{38 ,0,121},{43 ,1,22},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{40 ,0,4},{45 ,1,177},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{42 ,0,222},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},
+{44 ,0,191},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1},{0 ,0,-1}
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I0 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I0
new file mode 100644
index 0000000000000000000000000000000000000000..d4bdc783d63f156d779aed2897c6728ee257147e
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I0
@@ -0,0 +1,44 @@
+int h_base_8 [42*52] = {
+ 9, 117, 204, 26, -1, -1, 189, -1, -1, 205, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 167, -1, -1, 166, 253, 125, 226, 156, 224, 252, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 81, 114, -1, 44, 52, -1, -1, -1, 240, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 8, 58, -1, 158, 104, 209, 54, 18, 128, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 179, 214, -1, -1, -1, -1, -1, -1, -1, -1, -1, 71, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 231, 41, -1, -1, -1, 194, -1, 159, -1, -1, -1, 103, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 155, -1, -1, -1, -1, 228, -1, 45, -1, 28, -1, 158, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 129, -1, -1, -1, 147, -1, 140, -1, -1, -1, 3, -1, 116, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 142, 94, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 230, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 203, -1, -1, -1, -1, -1, -1, 205, -1, 61, 247, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 11, 185, -1, -1, -1, -1, 0, 117, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 11, -1, -1, -1, -1, -1, -1, 236, -1, 210, -1, -1, -1, 56, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 63, -1, 111, -1, -1, -1, -1, -1, -1, -1, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 83, 2, -1, -1, -1, -1, -1, -1, 38, -1, -1, -1, -1, 222, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 115, -1, -1, -1, -1, 145, -1, -1, -1, -1, 3, -1, 232, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 51, -1, -1, -1, -1, -1, -1, -1, -1, -1, 175, 213, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 203, -1, -1, -1, -1, -1, -1, -1, 142, -1, 8, 242, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 254, -1, -1, -1, 124, -1, -1, -1, -1, -1, 114, 64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 220, -1, -1, -1, -1, -1, 194, 50, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 87, 20, -1, -1, -1, -1, -1, -1, -1, -1, 185, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 26, -1, -1, 105, -1, -1, -1, -1, -1, -1, 29, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 76, -1, -1, -1, -1, -1, -1, -1, 42, -1, -1, -1, -1, 210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 222, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 23, -1, -1, 235, -1, 238, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 46, 139, -1, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 228, -1, -1, -1, -1, 156, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 29, -1, -1, -1, -1, 143, -1, -1, -1, -1, 160, 122, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 8, -1, -1, -1, -1, -1, 151, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 98, 101, -1, -1, 135, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 18, -1, -1, -1, 28, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 71, -1, -1, 240, -1, 9, -1, 84, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 106, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 242, -1, -1, -1, -1, 44, -1, -1, -1, -1, -1, -1, 166, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 132, -1, -1, -1, -1, 164, -1, -1, 235, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 147, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 85, 36, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 57, -1, -1, -1, 40, -1, -1, -1, -1, -1, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 140, -1, 38, -1, -1, -1, -1, 154, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 219, -1, -1, 151, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 31, -1, -1, -1, 66, -1, -1, -1, -1, -1, 38, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 239, -1, -1, -1, -1, -1, -1, 172, -1, -1, -1, -1, 34, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, 75, -1, -1, 120, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 129, -1, -1, -1, 229, -1, -1, -1, -1, -1, 118, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I1 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I1
new file mode 100644
index 0000000000000000000000000000000000000000..99909bcf5f9af1f3ffc4e8b5f1b6f7e760e3bbca
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I1
@@ -0,0 +1,44 @@
+int h_base_9 [42*52] = {
+ 174, 97, 166, 66, -1, -1, 71, -1, -1, 172, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 27, -1, -1, 36, 48, 92, 31, 187, 185, 3, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 25, 114, -1, 117, 110, -1, -1, -1, 114, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 136, 175, -1, 113, 72, 123, 118, 28, 186, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 72, 74, -1, -1, -1, -1, -1, -1, -1, -1, -1, 29, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 10, 44, -1, -1, -1, 121, -1, 80, -1, -1, -1, 48, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 129, -1, -1, -1, -1, 92, -1, 100, -1, 49, -1, 184, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 80, -1, -1, -1, 186, -1, 16, -1, -1, -1, 102, -1, 143, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 118, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 152, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 28, -1, -1, -1, -1, -1, -1, 132, -1, 185, 178, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 59, 104, -1, -1, -1, -1, 22, 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 32, -1, -1, -1, -1, -1, -1, 92, -1, 174, -1, -1, -1, 154, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 39, -1, 93, -1, -1, -1, -1, -1, -1, -1, 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 49, 125, -1, -1, -1, -1, -1, -1, 35, -1, -1, -1, -1, 166, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 19, -1, -1, -1, -1, 118, -1, -1, -1, -1, 21, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, 63, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 87, -1, -1, -1, -1, -1, -1, -1, 177, -1, 135, 64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 158, -1, -1, -1, 23, -1, -1, -1, -1, -1, 9, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 186, -1, -1, -1, -1, -1, 6, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 58, 42, -1, -1, -1, -1, -1, -1, -1, -1, 156, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 76, -1, -1, 61, -1, -1, -1, -1, -1, -1, 153, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 157, -1, -1, -1, -1, -1, -1, -1, 175, -1, -1, -1, -1, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 20, 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 106, -1, -1, 86, -1, 95, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 182, 153, -1, -1, -1, -1, -1, -1, 64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 45, -1, -1, -1, -1, 21, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 67, -1, -1, -1, -1, 137, -1, -1, -1, -1, 55, 85, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 103, -1, -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 70, 111, -1, -1, 168, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 110, -1, -1, -1, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 120, -1, -1, 154, -1, 52, -1, 56, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 170, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 84, -1, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 165, -1, -1, -1, -1, 179, -1, -1, 124, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 177, 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 77, -1, -1, -1, 184, -1, -1, -1, -1, -1, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 25, -1, 151, -1, -1, -1, -1, 170, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 37, -1, -1, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 84, -1, -1, -1, 151, -1, -1, -1, -1, -1, 190, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 93, -1, -1, -1, -1, -1, -1, 132, -1, -1, -1, -1, 57, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 103, -1, -1, -1, -1, -1, -1, -1, 107, -1, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 147, -1, -1, -1, 7, -1, -1, -1, -1, -1, 60, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2
new file mode 100644
index 0000000000000000000000000000000000000000..df209d30ce663a85911ef4c962a4d99b7d261a88
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I2
@@ -0,0 +1,44 @@
+int h_base_10 [42*52] = {
+ 0, 0, 0, 0, -1, -1, 0, -1, -1, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 137, -1, -1, 124, 0, 0, 88, 0, 0, 55, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 20, 94, -1, 99, 9, -1, -1, -1, 108, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 38, 15, -1, 102, 146, 12, 57, 53, 46, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 136, -1, -1, -1, -1, -1, -1, -1, -1, -1, 157, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 131, -1, -1, -1, 142, -1, 141, -1, -1, -1, 64, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, 124, -1, 99, -1, 45, -1, 148, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, 45, -1, 148, -1, -1, -1, 96, -1, 78, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 87, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, -1, -1, -1, 97, -1, 51, 85, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 17, -1, -1, -1, -1, 156, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, 7, -1, 4, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, 113, -1, -1, -1, -1, -1, -1, -1, 48, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 112, -1, -1, -1, -1, -1, -1, 102, -1, -1, -1, -1, 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, -1, 138, -1, -1, -1, -1, 57, -1, 27, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, 73, 99, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, -1, -1, -1, -1, 79, -1, 111, 143, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, 24, -1, -1, -1, -1, -1, 109, 18, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, 18, 86, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, 158, -1, -1, -1, -1, -1, -1, -1, -1, 154, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, 148, -1, -1, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, 17, -1, -1, -1, -1, 33, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, 75, -1, 158, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, 69, -1, -1, -1, -1, -1, -1, 87, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 0, -1, -1, -1, -1, 100, -1, -1, -1, -1, 13, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, 32, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, 126, -1, -1, 110, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, 154, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 0, -1, -1, 35, -1, 51, -1, 134, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, 20, -1, -1, -1, -1, -1, -1, 122, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 0, -1, -1, -1, -1, 88, -1, -1, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 19, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, 157, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 0, -1, 63, -1, -1, -1, -1, 82, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, 144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 0, -1, -1, -1, 93, -1, -1, -1, -1, -1, 19, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 0, -1, -1, -1, -1, -1, -1, 24, -1, -1, -1, -1, 138, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, 36, -1, -1, 143, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 0, -1, -1, -1, 2, -1, -1, -1, -1, -1, 55, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3
new file mode 100644
index 0000000000000000000000000000000000000000..d9efe76f46a3569fb09152f46d25770ec6478059
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I3
@@ -0,0 +1,44 @@
+int h_base_11 [42*52] = {
+ 72, 110, 23, 181, -1, -1, 95, -1, -1, 8, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 53, -1, -1, 156, 115, 156, 115, 200, 29, 31, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 152, 131, -1, 46, 191, -1, -1, -1, 91, -1, 0, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 185, 6, -1, 36, 124, 124, 110, 156, 133, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 200, 16, -1, -1, -1, -1, -1, -1, -1, -1, -1, 101, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 185, 138, -1, -1, -1, 170, -1, 219, -1, -1, -1, 193, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 123, -1, -1, -1, -1, 55, -1, 31, -1, 222, -1, 209, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 103, -1, -1, -1, 13, -1, 105, -1, -1, -1, 150, -1, 181, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 147, 43, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 152, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 2, -1, -1, -1, -1, -1, -1, 30, -1, 184, 83, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 174, 150, -1, -1, -1, -1, 8, 56, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 99, -1, -1, -1, -1, -1, -1, 138, -1, 110, -1, -1, -1, 99, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 46, -1, 217, -1, -1, -1, -1, -1, -1, -1, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 37, 113, -1, -1, -1, -1, -1, -1, 143, -1, -1, -1, -1, 140, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 36, -1, -1, -1, -1, 95, -1, -1, -1, -1, 40, -1, 116, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 116, -1, -1, -1, -1, -1, -1, -1, -1, -1, 200, 110, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 75, -1, -1, -1, -1, -1, -1, -1, 158, -1, 134, 97, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 48, -1, -1, -1, 132, -1, -1, -1, -1, -1, 206, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 68, -1, -1, -1, -1, -1, 16, 156, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 35, 138, -1, -1, -1, -1, -1, -1, -1, -1, 86, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 6, -1, -1, 20, -1, -1, -1, -1, -1, -1, 141, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 80, -1, -1, -1, -1, -1, -1, -1, 43, -1, -1, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 49, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 156, -1, -1, 54, -1, 134, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 153, 88, -1, -1, -1, -1, -1, -1, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 211, -1, -1, -1, -1, 94, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 90, -1, -1, -1, -1, 6, -1, -1, -1, -1, 221, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 27, -1, -1, -1, -1, -1, 118, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 216, 212, -1, -1, 193, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 108, -1, -1, -1, 61, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 106, -1, -1, 44, -1, 185, -1, 176, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 147, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 182, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 108, -1, -1, -1, -1, 21, -1, -1, -1, -1, -1, -1, 110, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 71, -1, -1, -1, -1, 12, -1, -1, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 29, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 201, 69, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 91, -1, -1, -1, 165, -1, -1, -1, -1, -1, 55, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 1, -1, 175, -1, -1, -1, -1, 83, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 40, -1, -1, 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 37, -1, -1, -1, 97, -1, -1, -1, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 106, -1, -1, -1, -1, -1, -1, 181, -1, -1, -1, -1, 154, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 98, -1, -1, -1, -1, -1, -1, -1, 35, -1, -1, 36, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 120, -1, -1, -1, 101, -1, -1, -1, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4
new file mode 100644
index 0000000000000000000000000000000000000000..2522b14f2e6de993d2466005612da0e6400bf27d
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I4
@@ -0,0 +1,44 @@
+int h_base_12 [42*52] = {
+ 3, 26, 53, 35, -1, -1, 115, -1, -1, 127, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 19, -1, -1, 94, 104, 66, 84, 98, 69, 50, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 95, 106, -1, 92, 110, -1, -1, -1, 111, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 120, 121, -1, 22, 4, 73, 49, 128, 79, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 42, 24, -1, -1, -1, -1, -1, -1, -1, -1, -1, 51, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 40, 140, -1, -1, -1, 84, -1, 137, -1, -1, -1, 71, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 109, -1, -1, -1, -1, 87, -1, 107, -1, 133, -1, 139, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 97, -1, -1, -1, 135, -1, 35, -1, -1, -1, 108, -1, 65, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 70, 69, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 88, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 97, -1, -1, -1, -1, -1, -1, 40, -1, 24, 49, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 46, 41, -1, -1, -1, -1, 101, 96, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 28, -1, -1, -1, -1, -1, -1, 30, -1, 116, -1, -1, -1, 64, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 33, -1, 122, -1, -1, -1, -1, -1, -1, -1, 131, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 76, 37, -1, -1, -1, -1, -1, -1, 62, -1, -1, -1, -1, 47, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 143, -1, -1, -1, -1, 51, -1, -1, -1, -1, 130, -1, 97, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 139, -1, -1, -1, -1, -1, -1, -1, -1, -1, 96, 128, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 48, -1, -1, -1, -1, -1, -1, -1, 9, -1, 28, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 120, -1, -1, -1, 43, -1, -1, -1, -1, -1, 65, 42, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 17, -1, -1, -1, -1, -1, 106, 142, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 79, 28, -1, -1, -1, -1, -1, -1, -1, -1, 41, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 2, -1, -1, 103, -1, -1, -1, -1, -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 91, -1, -1, -1, -1, -1, -1, -1, 75, -1, -1, -1, -1, 81, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 54, 132, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 68, -1, -1, 115, -1, 56, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 30, 42, -1, -1, -1, -1, -1, -1, 101, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 128, -1, -1, -1, -1, 63, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 142, -1, -1, -1, -1, 28, -1, -1, -1, -1, 100, 133, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 13, -1, -1, -1, -1, -1, 10, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 106, 77, -1, -1, 43, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 133, -1, -1, -1, 25, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 87, -1, -1, 56, -1, 104, -1, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 80, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 139, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 32, -1, -1, -1, -1, 89, -1, -1, -1, -1, -1, -1, 71, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 135, -1, -1, -1, -1, 6, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 37, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 25, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 60, -1, -1, -1, 137, -1, -1, -1, -1, -1, 93, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 121, -1, 129, -1, -1, -1, -1, 26, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 97, -1, -1, 56, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 1, -1, -1, -1, 70, -1, -1, -1, -1, -1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 119, -1, -1, -1, -1, -1, -1, 32, -1, -1, -1, -1, 142, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, 73, -1, -1, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 48, -1, -1, -1, 47, -1, -1, -1, -1, -1, 19, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I5 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I5
new file mode 100644
index 0000000000000000000000000000000000000000..f392ef5182761aa4f29c9d76be42143bc1269f3b
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I5
@@ -0,0 +1,44 @@
+int h_base_13 [42*52] = {
+ 156, 143, 14, 3, -1, -1, 40, -1, -1, 123, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 17, -1, -1, 65, 63, 1, 55, 37, 171, 133, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 98, 168, -1, 107, 82, -1, -1, -1, 142, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 53, 174, -1, 174, 127, 17, 89, 17, 105, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 86, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, 83, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 79, 84, -1, -1, -1, 35, -1, 103, -1, -1, -1, 60, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 47, -1, -1, -1, -1, 154, -1, 10, -1, 155, -1, 29, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 48, -1, -1, -1, 125, -1, 24, -1, -1, -1, 47, -1, 55, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 53, 31, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 161, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 104, -1, -1, -1, -1, -1, -1, 142, -1, 99, 64, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 111, 25, -1, -1, -1, -1, 174, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 91, -1, -1, -1, -1, -1, -1, 175, -1, 24, -1, -1, -1, 141, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 122, -1, 11, -1, -1, -1, -1, -1, -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 29, 91, -1, -1, -1, -1, -1, -1, 27, -1, -1, -1, -1, 127, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 11, -1, -1, -1, -1, 145, -1, -1, -1, -1, 8, -1, 166, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 137, -1, -1, -1, -1, -1, -1, -1, -1, -1, 103, 40, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 78, -1, -1, -1, -1, -1, -1, -1, 158, -1, 17, 165, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 134, -1, -1, -1, 23, -1, -1, -1, -1, -1, 62, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 173, -1, -1, -1, -1, -1, 31, 22, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 13, 135, -1, -1, -1, -1, -1, -1, -1, -1, 145, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 128, -1, -1, 52, -1, -1, -1, -1, -1, -1, 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 156, -1, -1, -1, -1, -1, -1, -1, 166, -1, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 18, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 110, -1, -1, 132, -1, 150, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 113, 108, -1, -1, -1, -1, -1, -1, 61, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 72, -1, -1, -1, -1, 136, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 36, -1, -1, -1, -1, 38, -1, -1, -1, -1, 53, 145, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 42, -1, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 64, 24, -1, -1, 149, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 139, -1, -1, -1, 161, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 84, -1, -1, 173, -1, 93, -1, 29, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 117, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 148, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 116, -1, -1, -1, -1, 73, -1, -1, -1, -1, -1, -1, 142, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 105, -1, -1, -1, -1, 137, -1, -1, 29, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 41, 162, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 126, -1, -1, -1, 152, -1, -1, -1, -1, -1, 172, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 73, -1, 154, -1, -1, -1, -1, 129, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 167, -1, -1, 38, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 112, -1, -1, -1, 7, -1, -1, -1, -1, -1, 19, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 109, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, 105, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 160, -1, -1, -1, -1, -1, -1, -1, 156, -1, -1, 82, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 132, -1, -1, -1, 6, -1, -1, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I6 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I6
new file mode 100644
index 0000000000000000000000000000000000000000..2cbaa1aca38fb2002f07dd8a80576db26e471f08
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I6
@@ -0,0 +1,44 @@
+int h_base_14 [42*52] = {
+ 143, 19, 176, 165, -1, -1, 196, -1, -1, 13, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 18, -1, -1, 27, 3, 102, 185, 17, 14, 180, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 126, 163, -1, 47, 183, -1, -1, -1, 132, -1, 1, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 36, 48, -1, 18, 111, 203, 3, 191, 160, 0, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 43, 27, -1, -1, -1, -1, -1, -1, -1, -1, -1, 117, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 136, 49, -1, -1, -1, 36, -1, 132, -1, -1, -1, 62, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 7, -1, -1, -1, -1, 34, -1, 198, -1, 168, -1, 12, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 163, -1, -1, -1, 78, -1, 143, -1, -1, -1, 107, -1, 58, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 101, 177, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 22, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 186, -1, -1, -1, -1, -1, -1, 27, -1, 205, 81, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 125, 60, -1, -1, -1, -1, 177, 51, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 39, -1, -1, -1, -1, -1, -1, 29, -1, 35, -1, -1, -1, 8, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 18, -1, 155, -1, -1, -1, -1, -1, -1, -1, 49, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 32, 53, -1, -1, -1, -1, -1, -1, 95, -1, -1, -1, -1, 186, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 91, -1, -1, -1, -1, 20, -1, -1, -1, -1, 52, -1, 109, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 174, -1, -1, -1, -1, -1, -1, -1, -1, -1, 108, 102, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 125, -1, -1, -1, -1, -1, -1, -1, 31, -1, 54, 176, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 57, -1, -1, -1, 201, -1, -1, -1, -1, -1, 142, 35, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 129, -1, -1, -1, -1, -1, 203, 140, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 110, 124, -1, -1, -1, -1, -1, -1, -1, -1, 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 196, -1, -1, 35, -1, -1, -1, -1, -1, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 10, -1, -1, -1, -1, -1, -1, -1, 122, -1, -1, -1, -1, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 202, 126, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 52, -1, -1, 170, -1, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 113, 161, -1, -1, -1, -1, -1, -1, 88, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 197, -1, -1, -1, -1, 194, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 164, -1, -1, -1, -1, 172, -1, -1, -1, -1, 49, 161, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 168, -1, -1, -1, -1, -1, 193, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 14, 186, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 50, -1, -1, -1, 27, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 70, -1, -1, 17, -1, 50, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 115, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 189, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 110, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, 163, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 163, -1, -1, -1, -1, 173, -1, -1, 179, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 197, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 191, 193, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 157, -1, -1, -1, 167, -1, -1, -1, -1, -1, 181, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 197, -1, 167, -1, -1, -1, -1, 179, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 181, -1, -1, 193, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 157, -1, -1, -1, 173, -1, -1, -1, -1, -1, 191, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 181, -1, -1, -1, -1, -1, -1, 157, -1, -1, -1, -1, 173, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 193, -1, -1, -1, -1, -1, -1, -1, 163, -1, -1, 179, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 191, -1, -1, -1, 197, -1, -1, -1, -1, -1, 167, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I7 b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I7
new file mode 100644
index 0000000000000000000000000000000000000000..c6cd7c09fff09eda9395d300dc24be28418f2c4f
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/bgs/BG2_I7
@@ -0,0 +1,44 @@
+int h_base_15 [42*52] = {
+ 145, 131, 71, 21, -1, -1, 23, -1, -1, 112, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 142, -1, -1, 174, 183, 27, 96, 23, 9, 167, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 74, 31, -1, 3, 53, -1, -1, -1, 155, -1, 0, -1, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 239, 171, -1, 95, 110, 159, 199, 43, 75, 1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 29, 140, -1, -1, -1, -1, -1, -1, -1, -1, -1, 180, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 121, 41, -1, -1, -1, 169, -1, 88, -1, -1, -1, 207, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 137, -1, -1, -1, -1, 72, -1, 172, -1, 124, -1, 56, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 86, -1, -1, -1, 186, -1, 87, -1, -1, -1, 172, -1, 154, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 176, 169, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 225, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 167, -1, -1, -1, -1, -1, -1, 238, -1, 48, 68, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 38, 217, -1, -1, -1, -1, 208, 232, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 178, -1, -1, -1, -1, -1, -1, 214, -1, 168, -1, -1, -1, 51, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 124, -1, 122, -1, -1, -1, -1, -1, -1, -1, 72, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 48, 57, -1, -1, -1, -1, -1, -1, 167, -1, -1, -1, -1, 219, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 82, -1, -1, -1, -1, 232, -1, -1, -1, -1, 204, -1, 162, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 38, -1, -1, -1, -1, -1, -1, -1, -1, -1, 217, 157, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 170, -1, -1, -1, -1, -1, -1, -1, 23, -1, 175, 202, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 196, -1, -1, -1, 173, -1, -1, -1, -1, -1, 195, 218, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 128, -1, -1, -1, -1, -1, 211, 210, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 39, 84, -1, -1, -1, -1, -1, -1, -1, -1, 88, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 117, -1, -1, 227, -1, -1, -1, -1, -1, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 238, -1, -1, -1, -1, -1, -1, -1, 13, -1, -1, -1, -1, 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 195, 44, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 5, -1, -1, 94, -1, 111, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 81, 19, -1, -1, -1, -1, -1, -1, 130, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 66, -1, -1, -1, -1, 95, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 146, -1, -1, -1, -1, 66, -1, -1, -1, -1, 190, 86, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 64, -1, -1, -1, -1, -1, 181, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 7, 144, -1, -1, 16, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 25, -1, -1, -1, 57, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 37, -1, -1, 139, -1, 221, -1, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, 201, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 46, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ 179, -1, -1, -1, -1, 14, -1, -1, -1, -1, -1, -1, 116, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, 46, -1, -1, -1, -1, 2, -1, -1, 106, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1, -1,
+ 184, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 135, 141, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1, -1,
+ -1, 85, -1, -1, -1, 225, -1, -1, -1, -1, -1, 175, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1, -1,
+ 178, -1, 112, -1, -1, -1, -1, 106, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 154, -1, -1, 114, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1, -1,
+ -1, 42, -1, -1, -1, 41, -1, -1, -1, -1, -1, 105, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1, -1,
+ 167, -1, -1, -1, -1, -1, -1, 45, -1, -1, -1, -1, 189, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1, -1,
+ -1, -1, 78, -1, -1, -1, -1, -1, -1, -1, 67, -1, -1, 180, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, -1,
+ -1, 53, -1, -1, -1, 215, -1, -1, -1, -1, -1, 230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0,
+};
\ No newline at end of file
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu
new file mode 100644
index 0000000000000000000000000000000000000000..931d5003385af8b4144fdbef244ed2176272a90e
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu
@@ -0,0 +1,552 @@
+ /*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.cu
+ * \brief LDPC cuda support BG1 all length
+ * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN
+ * \email tyhsu@cs.nctu.edu.tw
+ * \date 13-05-2020
+ * \version
+ * \note
+ * \warning
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <cuda_runtime.h>
+#include <cuda.h>
+#include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h"
+#include "PHY/CODING/nrLDPC_decoder/nrLDPCdecoder_defs.h"
+
+#include "bgs/BG1_I0"
+#include "bgs/BG1_I1"
+#include "bgs/BG1_I2"
+#include "bgs/BG1_I3"
+#include "bgs/BG1_I4"
+#include "bgs/BG1_I5"
+#include "bgs/BG1_I6"
+#include "bgs/BG1_I7"
+#include "bgs/BG2_I0"
+#include "bgs/BG2_I1"
+#include "bgs/BG2_I2"
+#include "bgs/BG2_I3"
+#include "bgs/BG2_I4"
+#include "bgs/BG2_I5"
+#include "bgs/BG2_I6"
+#include "bgs/BG2_I7"
+
+#define MAX_ITERATION 2
+#define MC 1
+
+#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); }
+inline void cudaAssert(cudaError_t code, const char *file, int line)
+{
+ if (code != cudaSuccess){
+ fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
+ exit(code);
+ }
+}
+
+typedef struct{
+ char x;
+ char y;
+ short value;
+} h_element;
+#include "bgs/BG1_compact_in_C.h"
+
+__device__ char dev_const_llr[68*384];
+__device__ char dev_dt [46*68*384];
+__device__ char dev_llr[68*384];
+__device__ unsigned char dev_tmp[68*384];
+
+h_element h_compact1 [46*19] = {};
+h_element h_compact2 [68*30] = {};
+
+__device__ h_element dev_h_compact1[46*19]; // used in kernel 1
+__device__ h_element dev_h_compact2[68*30]; // used in kernel 2
+
+// __device__ __constant__ h_element dev_h_compact1[46*19]; // used in kernel 1
+// __device__ __constant__ h_element dev_h_compact2[68*30]; // used in kernel 2
+
+// row and col element count
+__device__ __constant__ char h_ele_row_bg1_count[46] = {
+ 19, 19, 19, 19, 3, 8, 9, 7, 10, 9,
+ 7, 8, 7, 6, 7, 7, 6, 6, 6, 6,
+ 6, 6, 5, 5, 6, 5, 5, 4, 5, 5,
+ 5, 5, 5, 5, 5, 5, 5, 4, 5, 5,
+ 4, 5, 4, 5, 5, 4};
+__device__ __constant__ char h_ele_col_bg1_count[68] = {
+ 30, 28, 7, 11, 9, 4, 8, 12, 8, 7,
+ 12, 10, 12, 11, 10, 7, 10, 10, 13, 7,
+ 8, 11, 12, 5, 6, 6, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1};
+__device__ __constant__ char h_ele_row_bg2_count[42] = {
+ 8, 10, 8, 10, 4, 6, 6, 6, 4, 5,
+ 5, 5, 4, 5, 5, 4, 5, 5, 4, 4,
+ 4, 4, 3, 4, 4, 3, 5, 3, 4, 3,
+ 5, 3, 4, 4, 4, 4, 4, 3, 4, 4,
+ 4, 4};
+__device__ __constant__ char h_ele_col_bg2_count[52] = {
+ 22, 23, 10, 5, 5, 14, 7, 13, 6, 8,
+ 9, 16, 9, 12, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1};
+
+
+__global__ void warmup()
+{
+ // warm up gpu for time measurement
+}
+
+extern "C"
+void warmup_for_GPU(){
+
+ warmup<<<20,1024 >>>();
+
+}
+
+extern "C"
+void set_compact_BG(int Zc,short BG){
+
+ int row,col;
+ if(BG == 1){
+ row = 46;
+ col = 68;
+ }
+ else{
+ row = 42;
+ col = 52;
+ }
+ int compact_row = 30;
+ int compact_col = 19;
+ if(BG==2){compact_row = 10, compact_col = 23;}
+ int memorySize_h_compact1 = row * compact_col * sizeof(h_element);
+ int memorySize_h_compact2 = compact_row * col * sizeof(h_element);
+ int lift_index = 0;
+ short lift_set[][9] = {
+ {2,4,8,16,32,64,128,256},
+ {3,6,12,24,48,96,192,384},
+ {5,10,20,40,80,160,320},
+ {7,14,28,56,112,224},
+ {9,18,36,72,144,288},
+ {11,22,44,88,176,352},
+ {13,26,52,104,208},
+ {15,30,60,120,240},
+ {0}
+ };
+
+ for(int i = 0; lift_set[i][0] != 0; i++){
+ for(int j = 0; lift_set[i][j] != 0; j++){
+ if(Zc == lift_set[i][j]){
+ lift_index = i;
+ break;
+ }
+ }
+ }
+ printf("\nZc = %d BG = %d\n",Zc,BG);
+ switch(lift_index){
+ case 0:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I0, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I0, memorySize_h_compact2) );
+ break;
+ case 1:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I1, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I1, memorySize_h_compact2) );
+ break;
+ case 2:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I2, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I2, memorySize_h_compact2) );
+ break;
+ case 3:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I3, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I3, memorySize_h_compact2) );
+ break;
+ case 4:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I4, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I4, memorySize_h_compact2) );
+ break;
+ case 5:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I5, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I5, memorySize_h_compact2) );
+ break;
+ case 6:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I6, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I6, memorySize_h_compact2) );
+ break;
+ case 7:
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact1, host_h_compact1_I7, memorySize_h_compact1) );
+ cudaCheck( cudaMemcpyToSymbol(dev_h_compact2, host_h_compact2_I7, memorySize_h_compact2) );
+ break;
+ }
+
+ // return 0;
+}
+
+
+// Kernel 1
+__global__ void ldpc_cnp_kernel_1st_iter(/*char * dev_llr,*/ int BG, int row, int col, int Zc)
+{
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp %d\n", threadIdx.x);
+ int iMCW = blockIdx.y; // codeword id
+ int iBlkRow = blockIdx.x; // block row in h_base
+ int iBlkCol; // block col in h_base
+ int iSubRow = threadIdx.x; // row index in sub_block of h_base
+ int iCol; // overall col index in h_base
+ int offsetR;
+ int shift_t;
+
+// For 2-min algorithm.
+ int Q_sign = 0;
+ int sq;
+ int Q, Q_abs;
+ int R_temp;
+
+ int sign = 1;
+ int rmin1 = INT32_MAX;
+ int rmin2 = INT32_MAX;
+ char idx_min = 0;
+
+ h_element h_element_t;
+ int s = (BG==1)? h_ele_row_bg1_count[iBlkRow]:h_ele_row_bg2_count[iBlkRow];
+ offsetR = (iMCW * row*col*Zc) + iBlkRow * Zc + iSubRow; // row*col*Zc = size of dev_dt
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("s: %d, offset %d\n", s, offsetR);
+// The 1st recursion
+ for(int i = 0; i < s; i++) // loop through all the ZxZ sub-blocks in a row
+ {
+ h_element_t = dev_h_compact1[i*row+iBlkRow]; // compact_col == row
+
+ iBlkCol = h_element_t.y;
+ shift_t = h_element_t.value;
+
+ shift_t = (iSubRow + shift_t) % Zc;
+ iCol = (iMCW * col*Zc) + iBlkCol * Zc + shift_t; // col*Zc = size of llr
+ Q = dev_llr[iCol];
+ Q_abs = (Q>0)? Q : -Q;
+ sq = Q < 0;
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("i %d, icol %d, Q: %d\n", i, iCol, Q);
+ // quick version
+ sign = sign * (1 - sq * 2);
+ Q_sign |= sq << i;
+
+ if (Q_abs < rmin1){
+ rmin2 = rmin1;
+ rmin1 = Q_abs;
+ idx_min = i;
+ } else if (Q_abs < rmin2){
+ rmin2 = Q_abs;
+ }
+ }
+
+// if(blockIdx.x == 0 && threadIdx.x == 1)printf("min1 %d, min2 %d, min1_idx %d\n", rmin1, rmin2, idx_min);
+
+// The 2nd recursion
+ for(int i = 0; i < s; i++){
+ // v0: Best performance so far. 0.75f is the value of alpha.
+ sq = 1 - 2 * ((Q_sign >> i) & 0x01);
+ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2);
+ // write results to global memory
+ h_element_t = dev_h_compact1[i*row+iBlkRow];
+ int addr_temp = offsetR + h_element_t.y * row * Zc;
+ dev_dt[addr_temp] = R_temp;
+// if(blockIdx.x == 0 && threadIdx.x == 1)printf("R_temp %d, temp_addr %d\n", R_temp, addr_temp);
+ }
+}
+
+// Kernel_1
+__global__ void ldpc_cnp_kernel(/*char * dev_llr, char * dev_dt,*/ int BG, int row, int col, int Zc)
+{
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("cnp\n");
+ int iMCW = blockIdx.y;
+ int iBlkRow = blockIdx.x; // block row in h_base
+ int iBlkCol; // block col in h_base
+ int iSubRow = threadIdx.x; // row index in sub_block of h_base
+ int iCol; // overall col index in h_base
+ int offsetR;
+ int shift_t;
+
+// For 2-min algorithm.
+ int Q_sign = 0;
+ int sq;
+ int Q, Q_abs;
+ int R_temp;
+
+ int sign = 1;
+ int rmin1 = INT32_MAX;
+ int rmin2 = INT32_MAX;
+ char idx_min = 0;
+
+ h_element h_element_t;
+ int s = (BG==1)? h_ele_row_bg1_count[iBlkRow]: h_ele_row_bg2_count[iBlkRow];
+ offsetR = (iMCW *row*col*Zc) + iBlkRow * Zc + iSubRow; // row * col * Zc = size of dev_dt
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("s: %d, offset %d\n", s, offsetR);
+// The 1st recursion
+ for(int i = 0; i < s; i++) // loop through all the ZxZ sub-blocks in a row
+ {
+ h_element_t = dev_h_compact1[i*row+iBlkRow];
+
+ iBlkCol = h_element_t.y;
+ shift_t = h_element_t.value;
+ shift_t = (iSubRow + shift_t) % Zc;
+ iCol = iBlkCol * Zc + shift_t;
+
+ R_temp = dev_dt[offsetR + iBlkCol * row * Zc];
+
+ Q = dev_llr[iMCW * (col*Zc) + iCol] - R_temp;
+ Q_abs = (Q>0)? Q : -Q;
+// if(blockIdx.x == 0 && threadIdx.x == 1) printf("i %d, icol %d, Q: %d\n", i, iCol, Q);
+ sq = Q < 0;
+ sign = sign * (1 - sq * 2);
+ Q_sign |= sq << i;
+
+ if (Q_abs < rmin1){
+ rmin2 = rmin1;
+ rmin1 = Q_abs;
+ idx_min = i;
+ } else if (Q_abs < rmin2){
+ rmin2 = Q_abs;
+ }
+
+ }
+
+// if(blockIdx.x == 0 && threadIdx.x == 1)printf("min1 %d, min2 %d, min1_idx %d\n", rmin1, rmin2, idx_min);
+
+// The 2nd recursion
+ for(int i = 0; i < s; i ++){
+ sq = 1 - 2 * ((Q_sign >> i) & 0x01);
+ R_temp = 0.75f * sign * sq * (i != idx_min ? rmin1 : rmin2);
+
+
+ // write results to global memory
+ h_element_t = dev_h_compact1[i*row+iBlkRow];
+ int addr_temp = h_element_t.y * row * Zc + offsetR;
+ dev_dt[addr_temp] = R_temp;
+// if(blockIdx.x == 0 && threadIdx.x == 1)printf("R_temp %d, temp_addr %d\n", R_temp, addr_temp);
+ }
+}
+
+// Kernel 2: VNP processing
+__global__ void
+ldpc_vnp_kernel_normal(/*char * dev_llr, char * dev_dt, char * dev_const_llr,*/ int BG, int row, int col, int Zc)
+{
+ int iMCW = blockIdx.y;
+ int iBlkCol = blockIdx.x;
+ int iBlkRow;
+ int iSubCol = threadIdx.x;
+ int iRow;
+ int iCol;
+
+ int shift_t, sf;
+ int APP;
+
+ h_element h_element_t;
+
+ // update all the llr values
+ iCol = iBlkCol * Zc + iSubCol;
+ APP = dev_const_llr[iMCW *col*Zc + iCol];
+ int offsetDt = iMCW *row*col*Zc + iBlkCol * row * Zc;
+ int s = (BG==1)? h_ele_col_bg1_count[iBlkCol]:h_ele_col_bg2_count[iBlkCol];
+
+ for(int i = 0; i < s; i++)
+ {
+ h_element_t = dev_h_compact2[i*col+iBlkCol];
+
+ shift_t = h_element_t.value%Zc;
+ iBlkRow = h_element_t.x;
+
+ sf = iSubCol - shift_t;
+ sf = (sf + Zc) % Zc;
+
+ iRow = iBlkRow * Zc + sf;
+ APP = APP + dev_dt[offsetDt + iRow];
+ }
+ if(APP > SCHAR_MAX) APP = SCHAR_MAX;
+ if(APP < SCHAR_MIN) APP = SCHAR_MIN;
+ // write back to device global memory
+ dev_llr[iMCW *col*Zc + iCol] = APP;
+}
+
+
+__global__ void pack_decoded_bit(/*char *dev, unsigned char *host,*/ int col, int Zc)
+{
+ __shared__ unsigned char tmp[128];
+ int iMCW = blockIdx.y;
+ int tid = iMCW * col*Zc + blockIdx.x*128 + threadIdx.x;
+ int btid = threadIdx.x;
+ tmp[btid] = 0;
+
+ if(dev_llr[tid] < 0){
+ tmp[btid] = 1 << (7-(btid&7));
+ }
+ __syncthreads();
+
+ if(threadIdx.x < 16){
+ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] = 0;
+ for(int i = 0; i < 8; i++){
+ dev_tmp[iMCW * col*Zc + blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i];
+ }
+ }
+}
+
+void read_BG(int BG, int *h, int row, int col)
+{
+ int compact_row = 30, compact_col = 19;
+ if(BG==2){compact_row = 10, compact_col = 23;}
+
+ h_element h_element_temp;
+
+ // init the compact matrix
+ for(int i = 0; i < compact_col; i++){
+ for(int j = 0; j < row; j++){
+ h_element_temp.x = 0;
+ h_element_temp.y = 0;
+ h_element_temp.value = -1;
+ h_compact1[i*row+j] = h_element_temp; // h[i][0-11], the same column
+ }
+ }
+ // scan the h matrix, and gengerate compact mode of h
+ for(int i = 0; i < row; i++){
+ int k = 0;
+ for(int j = 0; j < col; j++){
+ if(h[i*col+j] != -1){
+ h_element_temp.x = i;
+ h_element_temp.y = j;
+ h_element_temp.value = h[i*col+j];
+ h_compact1[k*row+i] = h_element_temp;
+ k++;
+ }
+ }
+ }
+
+ // h_compact2
+ // init the compact matrix
+ for(int i = 0; i < compact_row; i++){
+ for(int j = 0; j < col; j++){
+ h_element_temp.x = 0;
+ h_element_temp.y = 0;
+ h_element_temp.value = -1;
+ h_compact2[i*col+j] = h_element_temp;
+ }
+ }
+
+ for(int j = 0; j < col; j++){
+ int k=0;
+ for(int i = 0; i < row; i++){
+ if(h[i*col+j] != -1){
+ // although h is transposed, the (x,y) is still (iBlkRow, iBlkCol)
+ h_element_temp.x = i;
+ h_element_temp.y = j;
+ h_element_temp.value = h[i*col+j];
+ h_compact2[k*col+j] = h_element_temp;
+ k++;
+ }
+ }
+ }
+
+ /*
+ for(int i = 0; i < compact_col; i++){
+ for(int j = 0; j < row; j++){
+ printf("%3d, ", h_compact1[i*row+j].value);
+ }
+ printf("\n");
+ }
+
+ for(int i = 0; i < compact_row; i++){
+ for(int j = 0; j < col; j++){
+ printf("%3d,", h_compact2[i*col+j].value);
+ }
+ printf("\n");
+ }
+ */
+}
+
+extern "C"
+void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length){
+
+ uint16_t Zc = p_decParams->Z;
+ uint8_t BG = p_decParams->BG;
+ uint8_t row,col;
+ if(BG == 1){
+ row = 46;
+ col = 68;
+ }
+ else{
+ row = 42;
+ col = 52;
+ }
+ unsigned char *hard_decision = (unsigned char*)p_out;
+ int memorySize_llr_cuda = col * Zc * sizeof(char) * MC;
+ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) );
+ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) );
+ cudaDeviceSynchronize();
+
+}
+
+extern "C"
+int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder)
+{
+
+
+ uint16_t Zc = p_decParams->Z;
+ uint8_t BG = p_decParams->BG;
+ uint8_t numMaxIter = p_decParams->numMaxIter;
+ e_nrLDPC_outMode outMode = p_decParams->outMode;
+ cudaError_t cudaStatus;
+ uint8_t row,col;
+ if(BG == 1){
+ row = 46;
+ col = 68;
+ }
+ else{
+ row = 42;
+ col = 52;
+ }
+
+// alloc memory
+ unsigned char *hard_decision = (unsigned char*)p_out;
+// gpu
+ int memorySize_llr_cuda = col * Zc * sizeof(char) * MC;
+ cudaCheck( cudaMemcpyToSymbol(dev_const_llr, p_llr, memorySize_llr_cuda) );
+ cudaCheck( cudaMemcpyToSymbol(dev_llr, p_llr, memorySize_llr_cuda) );
+
+// Define CUDA kernel dimension
+ int blockSizeX = Zc;
+ dim3 dimGridKernel1(row, MC, 1); // dim of the thread blocks
+ dim3 dimBlockKernel1(blockSizeX, 1, 1);
+
+ dim3 dimGridKernel2(col, MC, 1);
+ dim3 dimBlockKernel2(blockSizeX, 1, 1);
+ cudaDeviceSynchronize();
+
+// lauch kernel
+
+ for(int ii = 0; ii < MAX_ITERATION; ii++){
+ // first kernel
+ if(ii == 0){
+ ldpc_cnp_kernel_1st_iter
+ <<<dimGridKernel1, dimBlockKernel1>>>
+ (/*dev_llr,*/ BG, row, col, Zc);
+ }else{
+ ldpc_cnp_kernel
+ <<<dimGridKernel1, dimBlockKernel1>>>
+ (/*dev_llr,*/ BG, row, col, Zc);
+ }
+ // second kernel
+ ldpc_vnp_kernel_normal
+ <<<dimGridKernel2, dimBlockKernel2>>>
+ // (dev_llr, dev_const_llr,BG, row, col, Zc);
+ (BG, row, col, Zc);
+ }
+
+ int pack = (block_length/128)+1;
+ dim3 pack_block(pack, MC, 1);
+ pack_decoded_bit<<<pack_block,128>>>(/*dev_llr,*/ /*dev_tmp,*/ col, Zc);
+
+ cudaCheck( cudaMemcpyFromSymbol((void*)hard_decision, (const void*)dev_tmp, (block_length/8)*sizeof(unsigned char)) );
+ cudaDeviceSynchronize();
+
+
+ return MAX_ITERATION;
+
+}
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h
new file mode 100644
index 0000000000000000000000000000000000000000..c290cedf7d101be98bdb31ac8e5d55d7d0eacc3d
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h
@@ -0,0 +1,34 @@
+#ifndef __NR_LDPC_DECODER_LYC__H__
+#define __NR_LDPC_DECODER_LYC__H__
+
+
+/*! \file PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC.h
+ * \brief LDPC cuda support BG1 all length
+ * \author NCTU OpinConnect Terng-Yin Hsu,WEI-YING,LIN
+ * \email tyhsu@cs.nctu.edu.tw
+ * \date 13-05-2020
+ * \version
+ * \note
+ * \warning
+ */
+
+
+/***
+ \brief LDPC decoder
+ \param p_decParams LDPC decoder parameters
+ \param p_llr Input LLRs
+ \param p_llrOut Output vector
+ \param p_profiler LDPC profiler statistics
+****/
+
+int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length, time_stats_t *time_decoder);
+
+
+void init_LLR_DMA_for_CUDA(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length);
+
+void warmup_for_GPU(void);
+
+void set_compact_BG(int Zc, short BG);
+
+
+#endif
diff --git a/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu
new file mode 100644
index 0000000000000000000000000000000000000000..0d22a312bd5d78e39e8776d4d96a40092dc6d442
--- /dev/null
+++ b/openair1/PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_decoder_LYC_debug.cu
@@ -0,0 +1,396 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <cuda_runtime.h>
+#include <cuda.h>
+#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_types.h"
+#include "PHY/CODING/nrLDPC_decoder_LYC/nrLDPC_defs.h"
+
+#define MAX_ITERATION 5
+#define CW 1
+
+#define cudaCheck(ans) { cudaAssert((ans), __FILE__, __LINE__); }
+inline void cudaAssert(cudaError_t code, const char *file, int line)
+{
+ if (code != cudaSuccess){
+ fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
+ exit(code);
+ }
+}
+// row and col element count
+
+
+
+typedef struct{
+ char x;
+ char y;
+ short value;
+} h_element;
+
+__device__ __constant__ char h_element_count1_bg1[46] = {
+ 19, 19, 19, 19, 3, 8, 9, 7, 10, 9,
+ 7, 8, 7, 6, 7, 7, 6, 6, 6, 6,
+ 6, 6, 5, 5, 6, 5, 5, 4, 5, 5,
+ 5, 5, 5, 5, 5, 5, 5, 4, 5, 5,
+ 4, 5, 4, 5, 5, 4};
+__device__ __constant__ char h_element_count2_bg1[68] = {
+ 30, 28, 7, 11, 9, 4, 8, 12, 8, 7,
+ 12, 10, 12, 11, 10, 7, 10, 10, 13, 7,
+ 8, 11, 12, 5, 6, 6, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1};
+__device__ __constant__ char h_element_count1_bg2[42] = {
+ 8, 10, 8, 10, 4, 6, 6, 6, 4, 5,
+ 5, 5, 4, 5, 5, 4, 5, 5, 4, 4,
+ 4, 4, 3, 4, 4, 3, 5, 3, 4, 3,
+ 5, 3, 4, 4, 4, 4, 4, 3, 4, 4,
+ 4, 4};
+__device__ __constant__ char h_element_count2_bg2[52] = {
+ 22, 23, 10, 5, 5, 14, 7, 13, 6, 8,
+ 9, 16, 9, 12, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1};
+
+// BG
+__device__ __constant__ h_element dev_h_base1_1[316]={
+ { .x= 0, .y= 0, .value=307 }, { .x= 0, .y= 1, .value= 19 }, { .x= 0, .y= 2, .value= 50 }, { .x= 0, .y= 3, .value=369 }, { .x= 0, .y= 5, .value=181 }, { .x= 0, .y= 6, .value=216 }, { .x= 0, .y= 9, .value=317 }, { .x= 0, .y=10, .value=288 }, { .x= 0, .y=11, .value=109 }, { .x= 0, .y=12, .value= 17 },
+ { .x= 0, .y=13, .value=357 }, { .x= 0, .y=15, .value=215 }, { .x= 0, .y=16, .value=106 }, { .x= 0, .y=18, .value=242 }, { .x= 0, .y=19, .value=180 }, { .x= 0, .y=20, .value=330 }, { .x= 0, .y=21, .value=346 }, { .x= 0, .y=22, .value= 1 }, { .x= 0, .y=23, .value= 0 }, { .x= 1, .y= 0, .value= 76 },
+ { .x= 1, .y= 2, .value= 76 }, { .x= 1, .y= 3, .value= 73 }, { .x= 1, .y= 4, .value=288 }, { .x= 1, .y= 5, .value=144 }, { .x= 1, .y= 7, .value=331 }, { .x= 1, .y= 8, .value=331 }, { .x= 1, .y= 9, .value=178 }, { .x= 1, .y=11, .value=295 }, { .x= 1, .y=12, .value=342 }, { .x= 1, .y=14, .value=217 },
+ { .x= 1, .y=15, .value= 99 }, { .x= 1, .y=16, .value=354 }, { .x= 1, .y=17, .value=114 }, { .x= 1, .y=19, .value=331 }, { .x= 1, .y=21, .value=112 }, { .x= 1, .y=22, .value= 0 }, { .x= 1, .y=23, .value= 0 }, { .x= 1, .y=24, .value= 0 }, { .x= 2, .y= 0, .value=205 }, { .x= 2, .y= 1, .value=250 },
+ { .x= 2, .y= 2, .value=328 }, { .x= 2, .y= 4, .value=332 }, { .x= 2, .y= 5, .value=256 }, { .x= 2, .y= 6, .value=161 }, { .x= 2, .y= 7, .value=267 }, { .x= 2, .y= 8, .value=160 }, { .x= 2, .y= 9, .value= 63 }, { .x= 2, .y=10, .value=129 }, { .x= 2, .y=13, .value=200 }, { .x= 2, .y=14, .value= 88 },
+ { .x= 2, .y=15, .value= 53 }, { .x= 2, .y=17, .value=131 }, { .x= 2, .y=18, .value=240 }, { .x= 2, .y=19, .value=205 }, { .x= 2, .y=20, .value= 13 }, { .x= 2, .y=24, .value= 0 }, { .x= 2, .y=25, .value= 0 }, { .x= 3, .y= 0, .value=276 }, { .x= 3, .y= 1, .value= 87 }, { .x= 3, .y= 3, .value= 0 },
+ { .x= 3, .y= 4, .value=275 }, { .x= 3, .y= 6, .value=199 }, { .x= 3, .y= 7, .value=153 }, { .x= 3, .y= 8, .value= 56 }, { .x= 3, .y=10, .value=132 }, { .x= 3, .y=11, .value=305 }, { .x= 3, .y=12, .value=231 }, { .x= 3, .y=13, .value=341 }, { .x= 3, .y=14, .value=212 }, { .x= 3, .y=16, .value=304 },
+ { .x= 3, .y=17, .value=300 }, { .x= 3, .y=18, .value=271 }, { .x= 3, .y=20, .value= 39 }, { .x= 3, .y=21, .value=357 }, { .x= 3, .y=22, .value= 1 }, { .x= 3, .y=25, .value= 0 }, { .x= 4, .y= 0, .value=332 }, { .x= 4, .y= 1, .value=181 }, { .x= 4, .y=26, .value= 0 }, { .x= 5, .y= 0, .value=195 },
+ { .x= 5, .y= 1, .value= 14 }, { .x= 5, .y= 3, .value=115 }, { .x= 5, .y=12, .value=166 }, { .x= 5, .y=16, .value=241 }, { .x= 5, .y=21, .value= 51 }, { .x= 5, .y=22, .value=157 }, { .x= 5, .y=27, .value= 0 }, { .x= 6, .y= 0, .value=278 }, { .x= 6, .y= 6, .value=257 }, { .x= 6, .y=10, .value= 1 },
+ { .x= 6, .y=11, .value=351 }, { .x= 6, .y=13, .value= 92 }, { .x= 6, .y=17, .value=253 }, { .x= 6, .y=18, .value= 18 }, { .x= 6, .y=20, .value=225 }, { .x= 6, .y=28, .value= 0 }, { .x= 7, .y= 0, .value= 9 }, { .x= 7, .y= 1, .value= 62 }, { .x= 7, .y= 4, .value=316 }, { .x= 7, .y= 7, .value=333 },
+ { .x= 7, .y= 8, .value=290 }, { .x= 7, .y=14, .value=114 }, { .x= 7, .y=29, .value= 0 }, { .x= 8, .y= 0, .value=307 }, { .x= 8, .y= 1, .value=179 }, { .x= 8, .y= 3, .value=165 }, { .x= 8, .y=12, .value= 18 }, { .x= 8, .y=16, .value= 39 }, { .x= 8, .y=19, .value=224 }, { .x= 8, .y=21, .value=368 },
+ { .x= 8, .y=22, .value= 67 }, { .x= 8, .y=24, .value=170 }, { .x= 8, .y=30, .value= 0 }, { .x= 9, .y= 0, .value=366 }, { .x= 9, .y= 1, .value=232 }, { .x= 9, .y=10, .value=321 }, { .x= 9, .y=11, .value=133 }, { .x= 9, .y=13, .value= 57 }, { .x= 9, .y=17, .value=303 }, { .x= 9, .y=18, .value= 63 },
+ { .x= 9, .y=20, .value= 82 }, { .x= 9, .y=31, .value= 0 }, { .x=10, .y= 1, .value=101 }, { .x=10, .y= 2, .value=339 }, { .x=10, .y= 4, .value=274 }, { .x=10, .y= 7, .value=111 }, { .x=10, .y= 8, .value=383 }, { .x=10, .y=14, .value=354 }, { .x=10, .y=32, .value= 0 }, { .x=11, .y= 0, .value= 48 },
+ { .x=11, .y= 1, .value=102 }, { .x=11, .y=12, .value= 8 }, { .x=11, .y=16, .value= 47 }, { .x=11, .y=21, .value=188 }, { .x=11, .y=22, .value=334 }, { .x=11, .y=23, .value=115 }, { .x=11, .y=33, .value= 0 }, { .x=12, .y= 0, .value= 77 }, { .x=12, .y= 1, .value=186 }, { .x=12, .y=10, .value=174 },
+ { .x=12, .y=11, .value=232 }, { .x=12, .y=13, .value= 50 }, { .x=12, .y=18, .value= 74 }, { .x=12, .y=34, .value= 0 }, { .x=13, .y= 0, .value=313 }, { .x=13, .y= 3, .value=177 }, { .x=13, .y= 7, .value=266 }, { .x=13, .y=20, .value=115 }, { .x=13, .y=23, .value=370 }, { .x=13, .y=35, .value= 0 },
+ { .x=14, .y= 0, .value=142 }, { .x=14, .y=12, .value=248 }, { .x=14, .y=15, .value=137 }, { .x=14, .y=16, .value= 89 }, { .x=14, .y=17, .value=347 }, { .x=14, .y=21, .value= 12 }, { .x=14, .y=36, .value= 0 }, { .x=15, .y= 0, .value=241 }, { .x=15, .y= 1, .value= 2 }, { .x=15, .y=10, .value=210 },
+ { .x=15, .y=13, .value=318 }, { .x=15, .y=18, .value= 55 }, { .x=15, .y=25, .value=269 }, { .x=15, .y=37, .value= 0 }, { .x=16, .y= 1, .value= 13 }, { .x=16, .y= 3, .value=338 }, { .x=16, .y=11, .value= 57 }, { .x=16, .y=20, .value=289 }, { .x=16, .y=22, .value= 57 }, { .x=16, .y=38, .value= 0 },
+ { .x=17, .y= 0, .value=260 }, { .x=17, .y=14, .value=303 }, { .x=17, .y=16, .value= 81 }, { .x=17, .y=17, .value=358 }, { .x=17, .y=21, .value=375 }, { .x=17, .y=39, .value= 0 }, { .x=18, .y= 1, .value=130 }, { .x=18, .y=12, .value=163 }, { .x=18, .y=13, .value=280 }, { .x=18, .y=18, .value=132 },
+ { .x=18, .y=19, .value= 4 }, { .x=18, .y=40, .value= 0 }, { .x=19, .y= 0, .value=145 }, { .x=19, .y= 1, .value=213 }, { .x=19, .y= 7, .value=344 }, { .x=19, .y= 8, .value=242 }, { .x=19, .y=10, .value=197 }, { .x=19, .y=41, .value= 0 }, { .x=20, .y= 0, .value=187 }, { .x=20, .y= 3, .value=206 },
+ { .x=20, .y= 9, .value=264 }, { .x=20, .y=11, .value=341 }, { .x=20, .y=22, .value= 59 }, { .x=20, .y=42, .value= 0 }, { .x=21, .y= 1, .value=205 }, { .x=21, .y= 5, .value=102 }, { .x=21, .y=16, .value=328 }, { .x=21, .y=20, .value=213 }, { .x=21, .y=21, .value= 97 }, { .x=21, .y=43, .value= 0 },
+ { .x=22, .y= 0, .value= 30 }, { .x=22, .y=12, .value= 11 }, { .x=22, .y=13, .value=233 }, { .x=22, .y=17, .value= 22 }, { .x=22, .y=44, .value= 0 }, { .x=23, .y= 1, .value= 24 }, { .x=23, .y= 2, .value= 89 }, { .x=23, .y=10, .value= 61 }, { .x=23, .y=18, .value= 27 }, { .x=23, .y=45, .value= 0 },
+ { .x=24, .y= 0, .value=298 }, { .x=24, .y= 3, .value=158 }, { .x=24, .y= 4, .value=235 }, { .x=24, .y=11, .value=339 }, { .x=24, .y=22, .value=234 }, { .x=24, .y=46, .value= 0 }, { .x=25, .y= 1, .value= 72 }, { .x=25, .y= 6, .value= 17 }, { .x=25, .y= 7, .value=383 }, { .x=25, .y=14, .value=312 },
+ { .x=25, .y=47, .value= 0 }, { .x=26, .y= 0, .value= 71 }, { .x=26, .y= 2, .value= 81 }, { .x=26, .y= 4, .value= 76 }, { .x=26, .y=15, .value=136 }, { .x=26, .y=48, .value= 0 }, { .x=27, .y= 1, .value=194 }, { .x=27, .y= 6, .value=194 }, { .x=27, .y= 8, .value=101 }, { .x=27, .y=49, .value= 0 },
+ { .x=28, .y= 0, .value=222 }, { .x=28, .y= 4, .value= 19 }, { .x=28, .y=19, .value=244 }, { .x=28, .y=21, .value=274 }, { .x=28, .y=50, .value= 0 }, { .x=29, .y= 1, .value=252 }, { .x=29, .y=14, .value= 5 }, { .x=29, .y=18, .value=147 }, { .x=29, .y=25, .value= 78 }, { .x=29, .y=51, .value= 0 },
+ { .x=30, .y= 0, .value=159 }, { .x=30, .y=10, .value=229 }, { .x=30, .y=13, .value=260 }, { .x=30, .y=24, .value= 90 }, { .x=30, .y=52, .value= 0 }, { .x=31, .y= 1, .value=100 }, { .x=31, .y= 7, .value=215 }, { .x=31, .y=22, .value=258 }, { .x=31, .y=25, .value=256 }, { .x=31, .y=53, .value= 0 },
+ { .x=32, .y= 0, .value=102 }, { .x=32, .y=12, .value=201 }, { .x=32, .y=14, .value=175 }, { .x=32, .y=24, .value=287 }, { .x=32, .y=54, .value= 0 }, { .x=33, .y= 1, .value=323 }, { .x=33, .y= 2, .value= 8 }, { .x=33, .y=11, .value=361 }, { .x=33, .y=21, .value=105 }, { .x=33, .y=55, .value= 0 },
+ { .x=34, .y= 0, .value=230 }, { .x=34, .y= 7, .value=148 }, { .x=34, .y=15, .value=202 }, { .x=34, .y=17, .value=312 }, { .x=34, .y=56, .value= 0 }, { .x=35, .y= 1, .value=320 }, { .x=35, .y= 6, .value=335 }, { .x=35, .y=12, .value= 2 }, { .x=35, .y=22, .value=266 }, { .x=35, .y=57, .value= 0 },
+ { .x=36, .y= 0, .value=210 }, { .x=36, .y=14, .value=313 }, { .x=36, .y=15, .value=297 }, { .x=36, .y=18, .value= 21 }, { .x=36, .y=58, .value= 0 }, { .x=37, .y= 1, .value=269 }, { .x=37, .y=13, .value= 82 }, { .x=37, .y=23, .value=115 }, { .x=37, .y=59, .value= 0 }, { .x=38, .y= 0, .value=185 },
+ { .x=38, .y= 9, .value=177 }, { .x=38, .y=10, .value=289 }, { .x=38, .y=12, .value=214 }, { .x=38, .y=60, .value= 0 }, { .x=39, .y= 1, .value=258 }, { .x=39, .y= 3, .value= 93 }, { .x=39, .y= 7, .value=346 }, { .x=39, .y=19, .value=297 }, { .x=39, .y=61, .value= 0 }, { .x=40, .y= 0, .value=175 },
+ { .x=40, .y= 8, .value= 37 }, { .x=40, .y=17, .value=312 }, { .x=40, .y=62, .value= 0 }, { .x=41, .y= 1, .value= 52 }, { .x=41, .y= 3, .value=314 }, { .x=41, .y= 9, .value=139 }, { .x=41, .y=18, .value=288 }, { .x=41, .y=63, .value= 0 }, { .x=42, .y= 0, .value=113 }, { .x=42, .y= 4, .value= 14 },
+ { .x=42, .y=24, .value=218 }, { .x=42, .y=64, .value= 0 }, { .x=43, .y= 1, .value=113 }, { .x=43, .y=16, .value=132 }, { .x=43, .y=18, .value=114 }, { .x=43, .y=25, .value=168 }, { .x=43, .y=65, .value= 0 }, { .x=44, .y= 0, .value= 80 }, { .x=44, .y= 7, .value= 78 }, { .x=44, .y= 9, .value=163 },
+ { .x=44, .y=22, .value=274 }, { .x=44, .y=66, .value= 0 }, { .x=45, .y= 1, .value=135 }, { .x=45, .y= 6, .value=149 }, { .x=45, .y=10, .value= 15 }, { .x=45, .y=67, .value= 0 } };
+__device__ __constant__ h_element* dev_h_compact1[46]={
+ &(dev_h_base1_1[ 0]), &(dev_h_base1_1[ 19]), &(dev_h_base1_1[ 38]), &(dev_h_base1_1[ 57]), &(dev_h_base1_1[ 76]), &(dev_h_base1_1[ 79]), &(dev_h_base1_1[ 87]), &(dev_h_base1_1[ 96]), &(dev_h_base1_1[103]), &(dev_h_base1_1[113]),
+ &(dev_h_base1_1[122]), &(dev_h_base1_1[129]), &(dev_h_base1_1[137]), &(dev_h_base1_1[144]), &(dev_h_base1_1[150]), &(dev_h_base1_1[157]), &(dev_h_base1_1[164]), &(dev_h_base1_1[170]), &(dev_h_base1_1[176]), &(dev_h_base1_1[182]),
+ &(dev_h_base1_1[188]), &(dev_h_base1_1[194]), &(dev_h_base1_1[200]), &(dev_h_base1_1[205]), &(dev_h_base1_1[210]), &(dev_h_base1_1[216]), &(dev_h_base1_1[221]), &(dev_h_base1_1[226]), &(dev_h_base1_1[230]), &(dev_h_base1_1[235]),
+ &(dev_h_base1_1[240]), &(dev_h_base1_1[245]), &(dev_h_base1_1[250]), &(dev_h_base1_1[255]), &(dev_h_base1_1[260]), &(dev_h_base1_1[265]), &(dev_h_base1_1[270]), &(dev_h_base1_1[275]), &(dev_h_base1_1[279]), &(dev_h_base1_1[284]),
+ &(dev_h_base1_1[289]), &(dev_h_base1_1[293]), &(dev_h_base1_1[298]), &(dev_h_base1_1[302]), &(dev_h_base1_1[307]), &(dev_h_base1_1[312]) };
+__device__ __constant__ h_element dev_h_base2_1[316]={
+ { .x= 0, .y= 0, .value=307 }, { .x= 1, .y= 0, .value= 76 }, { .x= 2, .y= 0, .value=205 }, { .x= 3, .y= 0, .value=276 }, { .x= 4, .y= 0, .value=332 }, { .x= 5, .y= 0, .value=195 }, { .x= 6, .y= 0, .value=278 }, { .x= 7, .y= 0, .value= 9 }, { .x= 8, .y= 0, .value=307 }, { .x= 9, .y= 0, .value=366 },
+ { .x=11, .y= 0, .value= 48 }, { .x=12, .y= 0, .value= 77 }, { .x=13, .y= 0, .value=313 }, { .x=14, .y= 0, .value=142 }, { .x=15, .y= 0, .value=241 }, { .x=17, .y= 0, .value=260 }, { .x=19, .y= 0, .value=145 }, { .x=20, .y= 0, .value=187 }, { .x=22, .y= 0, .value= 30 }, { .x=24, .y= 0, .value=298 },
+ { .x=26, .y= 0, .value= 71 }, { .x=28, .y= 0, .value=222 }, { .x=30, .y= 0, .value=159 }, { .x=32, .y= 0, .value=102 }, { .x=34, .y= 0, .value=230 }, { .x=36, .y= 0, .value=210 }, { .x=38, .y= 0, .value=185 }, { .x=40, .y= 0, .value=175 }, { .x=42, .y= 0, .value=113 }, { .x=44, .y= 0, .value= 80 },
+ { .x= 0, .y= 1, .value= 19 }, { .x= 2, .y= 1, .value=250 }, { .x= 3, .y= 1, .value= 87 }, { .x= 4, .y= 1, .value=181 }, { .x= 5, .y= 1, .value= 14 }, { .x= 7, .y= 1, .value= 62 }, { .x= 8, .y= 1, .value=179 }, { .x= 9, .y= 1, .value=232 }, { .x=10, .y= 1, .value=101 }, { .x=11, .y= 1, .value=102 },
+ { .x=12, .y= 1, .value=186 }, { .x=15, .y= 1, .value= 2 }, { .x=16, .y= 1, .value= 13 }, { .x=18, .y= 1, .value=130 }, { .x=19, .y= 1, .value=213 }, { .x=21, .y= 1, .value=205 }, { .x=23, .y= 1, .value= 24 }, { .x=25, .y= 1, .value= 72 }, { .x=27, .y= 1, .value=194 }, { .x=29, .y= 1, .value=252 },
+ { .x=31, .y= 1, .value=100 }, { .x=33, .y= 1, .value=323 }, { .x=35, .y= 1, .value=320 }, { .x=37, .y= 1, .value=269 }, { .x=39, .y= 1, .value=258 }, { .x=41, .y= 1, .value= 52 }, { .x=43, .y= 1, .value=113 }, { .x=45, .y= 1, .value=135 }, { .x= 0, .y= 2, .value= 50 }, { .x= 1, .y= 2, .value= 76 },
+ { .x= 2, .y= 2, .value=328 }, { .x=10, .y= 2, .value=339 }, { .x=23, .y= 2, .value= 89 }, { .x=26, .y= 2, .value= 81 }, { .x=33, .y= 2, .value= 8 }, { .x= 0, .y= 3, .value=369 }, { .x= 1, .y= 3, .value= 73 }, { .x= 3, .y= 3, .value= 0 }, { .x= 5, .y= 3, .value=115 }, { .x= 8, .y= 3, .value=165 },
+ { .x=13, .y= 3, .value=177 }, { .x=16, .y= 3, .value=338 }, { .x=20, .y= 3, .value=206 }, { .x=24, .y= 3, .value=158 }, { .x=39, .y= 3, .value= 93 }, { .x=41, .y= 3, .value=314 }, { .x= 1, .y= 4, .value=288 }, { .x= 2, .y= 4, .value=332 }, { .x= 3, .y= 4, .value=275 }, { .x= 7, .y= 4, .value=316 },
+ { .x=10, .y= 4, .value=274 }, { .x=24, .y= 4, .value=235 }, { .x=26, .y= 4, .value= 76 }, { .x=28, .y= 4, .value= 19 }, { .x=42, .y= 4, .value= 14 }, { .x= 0, .y= 5, .value=181 }, { .x= 1, .y= 5, .value=144 }, { .x= 2, .y= 5, .value=256 }, { .x=21, .y= 5, .value=102 }, { .x= 0, .y= 6, .value=216 },
+ { .x= 2, .y= 6, .value=161 }, { .x= 3, .y= 6, .value=199 }, { .x= 6, .y= 6, .value=257 }, { .x=25, .y= 6, .value= 17 }, { .x=27, .y= 6, .value=194 }, { .x=35, .y= 6, .value=335 }, { .x=45, .y= 6, .value=149 }, { .x= 1, .y= 7, .value=331 }, { .x= 2, .y= 7, .value=267 }, { .x= 3, .y= 7, .value=153 },
+ { .x= 7, .y= 7, .value=333 }, { .x=10, .y= 7, .value=111 }, { .x=13, .y= 7, .value=266 }, { .x=19, .y= 7, .value=344 }, { .x=25, .y= 7, .value=383 }, { .x=31, .y= 7, .value=215 }, { .x=34, .y= 7, .value=148 }, { .x=39, .y= 7, .value=346 }, { .x=44, .y= 7, .value= 78 }, { .x= 1, .y= 8, .value=331 },
+ { .x= 2, .y= 8, .value=160 }, { .x= 3, .y= 8, .value= 56 }, { .x= 7, .y= 8, .value=290 }, { .x=10, .y= 8, .value=383 }, { .x=19, .y= 8, .value=242 }, { .x=27, .y= 8, .value=101 }, { .x=40, .y= 8, .value= 37 }, { .x= 0, .y= 9, .value=317 }, { .x= 1, .y= 9, .value=178 }, { .x= 2, .y= 9, .value= 63 },
+ { .x=20, .y= 9, .value=264 }, { .x=38, .y= 9, .value=177 }, { .x=41, .y= 9, .value=139 }, { .x=44, .y= 9, .value=163 }, { .x= 0, .y=10, .value=288 }, { .x= 2, .y=10, .value=129 }, { .x= 3, .y=10, .value=132 }, { .x= 6, .y=10, .value= 1 }, { .x= 9, .y=10, .value=321 }, { .x=12, .y=10, .value=174 },
+ { .x=15, .y=10, .value=210 }, { .x=19, .y=10, .value=197 }, { .x=23, .y=10, .value= 61 }, { .x=30, .y=10, .value=229 }, { .x=38, .y=10, .value=289 }, { .x=45, .y=10, .value= 15 }, { .x= 0, .y=11, .value=109 }, { .x= 1, .y=11, .value=295 }, { .x= 3, .y=11, .value=305 }, { .x= 6, .y=11, .value=351 },
+ { .x= 9, .y=11, .value=133 }, { .x=12, .y=11, .value=232 }, { .x=16, .y=11, .value= 57 }, { .x=20, .y=11, .value=341 }, { .x=24, .y=11, .value=339 }, { .x=33, .y=11, .value=361 }, { .x= 0, .y=12, .value= 17 }, { .x= 1, .y=12, .value=342 }, { .x= 3, .y=12, .value=231 }, { .x= 5, .y=12, .value=166 },
+ { .x= 8, .y=12, .value= 18 }, { .x=11, .y=12, .value= 8 }, { .x=14, .y=12, .value=248 }, { .x=18, .y=12, .value=163 }, { .x=22, .y=12, .value= 11 }, { .x=32, .y=12, .value=201 }, { .x=35, .y=12, .value= 2 }, { .x=38, .y=12, .value=214 }, { .x= 0, .y=13, .value=357 }, { .x= 2, .y=13, .value=200 },
+ { .x= 3, .y=13, .value=341 }, { .x= 6, .y=13, .value= 92 }, { .x= 9, .y=13, .value= 57 }, { .x=12, .y=13, .value= 50 }, { .x=15, .y=13, .value=318 }, { .x=18, .y=13, .value=280 }, { .x=22, .y=13, .value=233 }, { .x=30, .y=13, .value=260 }, { .x=37, .y=13, .value= 82 }, { .x= 1, .y=14, .value=217 },
+ { .x= 2, .y=14, .value= 88 }, { .x= 3, .y=14, .value=212 }, { .x= 7, .y=14, .value=114 }, { .x=10, .y=14, .value=354 }, { .x=17, .y=14, .value=303 }, { .x=25, .y=14, .value=312 }, { .x=29, .y=14, .value= 5 }, { .x=32, .y=14, .value=175 }, { .x=36, .y=14, .value=313 }, { .x= 0, .y=15, .value=215 },
+ { .x= 1, .y=15, .value= 99 }, { .x= 2, .y=15, .value= 53 }, { .x=14, .y=15, .value=137 }, { .x=26, .y=15, .value=136 }, { .x=34, .y=15, .value=202 }, { .x=36, .y=15, .value=297 }, { .x= 0, .y=16, .value=106 }, { .x= 1, .y=16, .value=354 }, { .x= 3, .y=16, .value=304 }, { .x= 5, .y=16, .value=241 },
+ { .x= 8, .y=16, .value= 39 }, { .x=11, .y=16, .value= 47 }, { .x=14, .y=16, .value= 89 }, { .x=17, .y=16, .value= 81 }, { .x=21, .y=16, .value=328 }, { .x=43, .y=16, .value=132 }, { .x= 1, .y=17, .value=114 }, { .x= 2, .y=17, .value=131 }, { .x= 3, .y=17, .value=300 }, { .x= 6, .y=17, .value=253 },
+ { .x= 9, .y=17, .value=303 }, { .x=14, .y=17, .value=347 }, { .x=17, .y=17, .value=358 }, { .x=22, .y=17, .value= 22 }, { .x=34, .y=17, .value=312 }, { .x=40, .y=17, .value=312 }, { .x= 0, .y=18, .value=242 }, { .x= 2, .y=18, .value=240 }, { .x= 3, .y=18, .value=271 }, { .x= 6, .y=18, .value= 18 },
+ { .x= 9, .y=18, .value= 63 }, { .x=12, .y=18, .value= 74 }, { .x=15, .y=18, .value= 55 }, { .x=18, .y=18, .value=132 }, { .x=23, .y=18, .value= 27 }, { .x=29, .y=18, .value=147 }, { .x=36, .y=18, .value= 21 }, { .x=41, .y=18, .value=288 }, { .x=43, .y=18, .value=114 }, { .x= 0, .y=19, .value=180 },
+ { .x= 1, .y=19, .value=331 }, { .x= 2, .y=19, .value=205 }, { .x= 8, .y=19, .value=224 }, { .x=18, .y=19, .value= 4 }, { .x=28, .y=19, .value=244 }, { .x=39, .y=19, .value=297 }, { .x= 0, .y=20, .value=330 }, { .x= 2, .y=20, .value= 13 }, { .x= 3, .y=20, .value= 39 }, { .x= 6, .y=20, .value=225 },
+ { .x= 9, .y=20, .value= 82 }, { .x=13, .y=20, .value=115 }, { .x=16, .y=20, .value=289 }, { .x=21, .y=20, .value=213 }, { .x= 0, .y=21, .value=346 }, { .x= 1, .y=21, .value=112 }, { .x= 3, .y=21, .value=357 }, { .x= 5, .y=21, .value= 51 }, { .x= 8, .y=21, .value=368 }, { .x=11, .y=21, .value=188 },
+ { .x=14, .y=21, .value= 12 }, { .x=17, .y=21, .value=375 }, { .x=21, .y=21, .value= 97 }, { .x=28, .y=21, .value=274 }, { .x=33, .y=21, .value=105 }, { .x= 0, .y=22, .value= 1 }, { .x= 1, .y=22, .value= 0 }, { .x= 3, .y=22, .value= 1 }, { .x= 5, .y=22, .value=157 }, { .x= 8, .y=22, .value= 67 },
+ { .x=11, .y=22, .value=334 }, { .x=16, .y=22, .value= 57 }, { .x=20, .y=22, .value= 59 }, { .x=24, .y=22, .value=234 }, { .x=31, .y=22, .value=258 }, { .x=35, .y=22, .value=266 }, { .x=44, .y=22, .value=274 }, { .x= 0, .y=23, .value= 0 }, { .x= 1, .y=23, .value= 0 }, { .x=11, .y=23, .value=115 },
+ { .x=13, .y=23, .value=370 }, { .x=37, .y=23, .value=115 }, { .x= 1, .y=24, .value= 0 }, { .x= 2, .y=24, .value= 0 }, { .x= 8, .y=24, .value=170 }, { .x=30, .y=24, .value= 90 }, { .x=32, .y=24, .value=287 }, { .x=42, .y=24, .value=218 }, { .x= 2, .y=25, .value= 0 }, { .x= 3, .y=25, .value= 0 },
+ { .x=15, .y=25, .value=269 }, { .x=29, .y=25, .value= 78 }, { .x=31, .y=25, .value=256 }, { .x=43, .y=25, .value=168 }, { .x= 4, .y=26, .value= 0 }, { .x= 5, .y=27, .value= 0 }, { .x= 6, .y=28, .value= 0 }, { .x= 7, .y=29, .value= 0 }, { .x= 8, .y=30, .value= 0 }, { .x= 9, .y=31, .value= 0 },
+ { .x=10, .y=32, .value= 0 }, { .x=11, .y=33, .value= 0 }, { .x=12, .y=34, .value= 0 }, { .x=13, .y=35, .value= 0 }, { .x=14, .y=36, .value= 0 }, { .x=15, .y=37, .value= 0 }, { .x=16, .y=38, .value= 0 }, { .x=17, .y=39, .value= 0 }, { .x=18, .y=40, .value= 0 }, { .x=19, .y=41, .value= 0 },
+ { .x=20, .y=42, .value= 0 }, { .x=21, .y=43, .value= 0 }, { .x=22, .y=44, .value= 0 }, { .x=23, .y=45, .value= 0 }, { .x=24, .y=46, .value= 0 }, { .x=25, .y=47, .value= 0 }, { .x=26, .y=48, .value= 0 }, { .x=27, .y=49, .value= 0 }, { .x=28, .y=50, .value= 0 }, { .x=29, .y=51, .value= 0 },
+ { .x=30, .y=52, .value= 0 }, { .x=31, .y=53, .value= 0 }, { .x=32, .y=54, .value= 0 }, { .x=33, .y=55, .value= 0 }, { .x=34, .y=56, .value= 0 }, { .x=35, .y=57, .value= 0 }, { .x=36, .y=58, .value= 0 }, { .x=37, .y=59, .value= 0 }, { .x=38, .y=60, .value= 0 }, { .x=39, .y=61, .value= 0 },
+ { .x=40, .y=62, .value= 0 }, { .x=41, .y=63, .value= 0 }, { .x=42, .y=64, .value= 0 }, { .x=43, .y=65, .value= 0 }, { .x=44, .y=66, .value= 0 }, { .x=45, .y=67, .value= 0 } };
+__device__ __constant__ h_element* dev_h_compact2[68]={
+ &(dev_h_base2_1[ 0]), &(dev_h_base2_1[ 30]), &(dev_h_base2_1[ 58]), &(dev_h_base2_1[ 65]), &(dev_h_base2_1[ 76]), &(dev_h_base2_1[ 85]), &(dev_h_base2_1[ 89]), &(dev_h_base2_1[ 97]), &(dev_h_base2_1[109]), &(dev_h_base2_1[117]),
+ &(dev_h_base2_1[124]), &(dev_h_base2_1[136]), &(dev_h_base2_1[146]), &(dev_h_base2_1[158]), &(dev_h_base2_1[169]), &(dev_h_base2_1[179]), &(dev_h_base2_1[186]), &(dev_h_base2_1[196]), &(dev_h_base2_1[206]), &(dev_h_base2_1[219]),
+ &(dev_h_base2_1[226]), &(dev_h_base2_1[234]), &(dev_h_base2_1[245]), &(dev_h_base2_1[257]), &(dev_h_base2_1[262]), &(dev_h_base2_1[268]), &(dev_h_base2_1[274]), &(dev_h_base2_1[275]), &(dev_h_base2_1[276]), &(dev_h_base2_1[277]),
+ &(dev_h_base2_1[278]), &(dev_h_base2_1[279]), &(dev_h_base2_1[280]), &(dev_h_base2_1[281]), &(dev_h_base2_1[282]), &(dev_h_base2_1[283]), &(dev_h_base2_1[284]), &(dev_h_base2_1[285]), &(dev_h_base2_1[286]), &(dev_h_base2_1[287]),
+ &(dev_h_base2_1[288]), &(dev_h_base2_1[289]), &(dev_h_base2_1[290]), &(dev_h_base2_1[291]), &(dev_h_base2_1[292]), &(dev_h_base2_1[293]), &(dev_h_base2_1[294]), &(dev_h_base2_1[295]), &(dev_h_base2_1[296]), &(dev_h_base2_1[297]),
+ &(dev_h_base2_1[298]), &(dev_h_base2_1[299]), &(dev_h_base2_1[300]), &(dev_h_base2_1[301]), &(dev_h_base2_1[302]), &(dev_h_base2_1[303]), &(dev_h_base2_1[304]), &(dev_h_base2_1[305]), &(dev_h_base2_1[306]), &(dev_h_base2_1[307]),
+ &(dev_h_base2_1[308]), &(dev_h_base2_1[309]), &(dev_h_base2_1[310]), &(dev_h_base2_1[311]), &(dev_h_base2_1[312]), &(dev_h_base2_1[313]), &(dev_h_base2_1[314]), &(dev_h_base2_1[315]) };
+
+
+
+
+__device__ void cnp_1st(int row, char* dev_llr, char* dev_buf, int blk, int thd)
+{
+ int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x;
+
+ for(int i = 0; i < row; i++)
+ {
+ int cnt = h_element_count1_bg1[i];
+ int min1 = INT32_MAX, min2 = INT32_MAX;
+ int sign = 0, tsign = 1, idx = 0;
+ int irow = subrow + Zc*i;
+
+ for(int j = 0; j < cnt; j++)
+ {
+ h_element tmp = dev_h_compact1[i][j];
+ int icol = tmp.y * Zc + (subcol+tmp.value)%Zc;
+
+ int Q = dev_llr[icol];
+ int Q_abs = (Q>0)? Q:-Q;
+ char sq = (Q<0);
+ tsign = tsign*(1-sq*2);
+ sign |= (sq << j);
+
+ if(threadIdx.x == thd && i == blk){
+ printf("dev_llr[%d](Q): %d, total_sign: %d, sign: %d\n", icol, dev_llr[icol], tsign, sign);
+ }
+
+
+ if(Q_abs < min1){
+ min2 = min1;
+ min1 = Q_abs;
+ idx = j;
+ }else if(Q_abs < min2){
+ min2 = Q_abs;
+ }
+ }
+
+ if(threadIdx.x == thd && i == blk){
+ printf("sign: %d, idx: %d, min1: %d, min2: %d\n", sign, idx, min1, min2);
+ }
+
+
+ for(int j = 0; j < cnt; j++)
+ {
+ char sq = 1 - 2 * ((sign >> j) & 0x01);
+ int temp = tsign * sq * ((j != idx)? min1 : min2);
+ h_element tmp = dev_h_compact1[i][j];
+ int addr = irow + tmp.y * row * Zc;
+ dev_buf[addr] = temp;
+
+ if(threadIdx.x == thd && i == blk){
+ printf("temp: %d, addr: %d\n", temp, addr);
+ }
+ }
+ }
+ __syncthreads();
+}
+
+__device__ void bnp(int row, int col, char* dev_llr, char* dev_const_llr, char* dev_buf, int blk, int thd)
+{
+ int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x;
+ for(int i = 0; i < col; i++)
+ {
+ int cnt = h_element_count2_bg1[i];
+ int icol = i * Zc + subcol;
+ int sum = dev_const_llr[icol];
+
+ for(int j = 0; j < cnt; j++)
+ {
+ h_element tmp = dev_h_compact2[i][j];
+ int irow = tmp.x * Zc + (subrow + Zc - tmp.value)%Zc;
+ int addr = i * row * Zc + irow;
+ sum = sum + dev_buf[addr];
+
+ if(threadIdx.x == thd && i == blk){
+ printf("dev_buf[%d]: %d, sum: %d, x: %d, value: %d, irow: %d\n", addr, dev_buf[addr], sum, tmp.x, tmp.value, irow);
+ }
+
+ }
+ if(sum > SCHAR_MAX) sum = SCHAR_MAX;
+ if(sum < SCHAR_MIN) sum = SCHAR_MIN;
+ dev_llr[icol] = sum;
+ }
+ __syncthreads();
+}
+
+
+__device__ void cnp(int row, char* dev_llr, char* dev_buf, int blk, int thd)
+{
+ int subrow = threadIdx.x, subcol = threadIdx.x, Zc = blockDim.x;
+
+ for(int i = 0; i < row; i++)
+ {
+ int cnt = h_element_count1_bg1[i];
+ int min1 = INT32_MAX, min2 = INT32_MAX;
+ int sign = 0, tsign = 1, idx = 0;
+ int irow = subrow + Zc*i;
+
+ for(int j = 0; j < cnt; j++)
+ {
+ h_element tmp = dev_h_compact1[i][j];
+ int icol = tmp.y * Zc + (subcol+tmp.value)%Zc;
+
+ int Q_last = dev_buf[tmp.y * row * Zc + irow];
+
+ int Q = dev_llr[icol] - Q_last;
+ int Q_abs = (Q>0)? Q:-Q;
+ char sq = (Q<0);
+ tsign = tsign*(1-sq*2);
+ sign |= (sq << j);
+
+ if(threadIdx.x == thd && i == blk){
+ printf("dev_llr[%d](Q): %d, total_sign: %d, sign: %d, last Q: %d, last_pos: %d\n", icol, dev_llr[icol], tsign, sign, Q_last, tmp.y * row * Zc + irow);
+ }
+
+
+ if(Q_abs < min1){
+ min2 = min1;
+ min1 = Q_abs;
+ idx = j;
+ }else if(Q_abs < min2){
+ min2 = Q_abs;
+ }
+ }
+
+ if(threadIdx.x == thd && i == blk){
+ printf("sign: %d, idx: %d, min1: %d, min2: %d\n", sign, idx, min1, min2);
+ }
+
+
+ for(int j = 0; j < cnt; j++)
+ {
+ char sq = 1 - 2 * ((sign >> j) & 0x01);
+ int temp = tsign * sq * ((j != idx)? min1 : min2);
+ h_element tmp = dev_h_compact1[i][j];
+ int addr = irow + tmp.y * row * Zc;
+ dev_buf[addr] = temp;
+
+
+ if(threadIdx.x == thd && i == blk){
+ printf("temp: %d, addr: %d\n", temp, addr);
+ }
+ }
+ }
+ __syncthreads();
+}
+
+
+
+__global__ void ldpc_decoder_gpu(int BG, char *dev_llr, char *dev_const_llr, char *dev_buf, int blk, int thd)
+{
+ int iteration = 5;
+ int row = 46, col = 68;
+ if(BG == 2){
+ row = 42;
+ col = 52;
+ }
+ //extern __shared__ sh_llr[];
+ //for()
+
+ for(int i = 0; i < iteration; i++){
+ if(i == 0){
+ cnp_1st(row, dev_llr, dev_buf, blk, thd);
+ }else{
+ cnp(row, dev_llr, dev_buf, blk, thd);
+ }
+
+ bnp(row, col, dev_llr, dev_const_llr, dev_buf, blk, thd);
+ }
+
+}
+
+
+__global__ void pack_decoded_bit(char *dev, unsigned char *host)
+{
+ __shared__ unsigned char tmp[256];
+ int tid = blockIdx.x*128 + threadIdx.x;
+ int btid = threadIdx.x;
+ tmp[btid] = 0;
+
+ if(dev[tid] < 0){
+ tmp[btid] = 1 << (7-(btid&7));
+ }
+ __syncthreads();
+
+ if(threadIdx.x < 16){
+ host[blockIdx.x*16+threadIdx.x] = 0;
+ for(int i = 0; i < 8; i++){
+ host[blockIdx.x*16+threadIdx.x] += tmp[threadIdx.x*8+i];
+ }
+ }
+}
+
+
+//void nrLDPC_decoder_LYC(int BG, int row, int col, int Zc, int block_length)
+extern "C"
+int32_t nrLDPC_decoder_LYC(t_nrLDPC_dec_params* p_decParams, int8_t* p_llr, int8_t* p_out, int block_length)
+{
+ // alloc mem
+ unsigned char *decision = (unsigned char*)p_out;
+
+ uint16_t Zc = p_decParams->Z;
+ uint8_t BG = p_decParams->BG;
+ uint8_t numMaxIter = p_decParams->numMaxIter;
+ e_nrLDPC_outMode outMode = p_decParams->outMode;
+
+ uint8_t row,col;
+ if(BG == 1){
+ row = 46;
+ col = 68;
+ }
+ else{
+ row = 42;
+ col = 52;
+ }
+ // gpu mem size
+ int memsize_llr = col * Zc * sizeof(char);
+ int memsize_buf = col * Zc * row * sizeof(char);
+
+ // gpu
+ char *dev_llr;
+ char *dev_const_llr;
+ char *dev_buf;
+ unsigned char *dev_tmp;
+
+ // gpu alloc
+ int p;
+ cudaCheck( cudaMallocPitch((void**)&dev_llr, (size_t*)&p, memsize_llr, 1) );
+ cudaCheck( cudaMallocPitch((void**)&dev_const_llr, (size_t*)&p, memsize_llr, 1) );
+ cudaCheck( cudaMallocPitch((void**)&dev_buf, (size_t*)&p, memsize_buf, 1) );
+ cudaCheck( cudaMallocPitch((void**)&dev_tmp, (size_t*)&p, memsize_llr, 1) );
+
+ // gpu memcpy
+ cudaCheck( cudaMemcpy((void*)dev_llr, p_llr, memsize_llr, cudaMemcpyHostToDevice) );
+ cudaCheck( cudaMemcpy((void*)dev_const_llr, p_llr, memsize_llr, cudaMemcpyHostToDevice) );
+ //cudaCheck( cudaMemcpy((void*)dev_const_llr, (const void*)p_llr, memsize_llr, cudaMemcpyHostToDevice) );
+
+ // gpu argument
+ dim3 block(CW, 1, 1);
+ dim3 thread(Zc, 1, 1);
+
+ // debug info
+ int blk, thd;
+ fprintf(stderr, "block thread focus: \n");
+ scanf("%d%d", &blk, &thd);
+
+ ldpc_decoder_gpu<<<block, thread, memsize_llr>>>(BG, dev_llr, dev_const_llr, dev_buf, blk, thd);
+
+ int pack = block_length/128;
+ pack_decoded_bit<<<pack, 128>>>(dev_llr, dev_tmp);
+
+ cudaCheck( cudaMemcpy((void*)decision, (const void*)dev_tmp, block_length*sizeof(unsigned char), cudaMemcpyDeviceToHost) );
+
+ return MAX_ITERATION;
+
+}
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c
index 53119a1c2b69b35462a60ebc59f32ab482449be5..18db8a01fbc5b65fb2ab09d442181b67f1b56429 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoder.c
@@ -569,7 +569,7 @@ int8_t polar_decoder_dci(double *input,
}
void init_polar_deinterleaver_table(t_nrPolar_params *polarParams) {
- AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K);
+ AssertFatal(polarParams->K > 17, "K = %d < 18, is not allowed\n",polarParams->K);
AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K);
int bit_i,ip,ipmod64;
int numbytes = polarParams->K>>3;
@@ -670,7 +670,9 @@ uint32_t polar_decoder_int16(int16_t *input,
A32_flip[1+offset]=((uint8_t *)&Aprime)[2];
A32_flip[2+offset]=((uint8_t *)&Aprime)[1];
A32_flip[3+offset]=((uint8_t *)&Aprime)[0];
- crc = (uint64_t)(crc24c(A32_flip,8*offset+len)>>8);
+ if (crclen == 24) crc = (uint64_t)((crc24c(A32_flip,8*offset+len)>>8)&0xffffff);
+ else if (crclen == 11) crc = (uint64_t)((crc11(A32_flip,8*offset+len)>>21)&0x7ff);
+ else if (crclen == 6) crc = (uint64_t)((crc6(A32_flip,8*offset+len)>>26)&0x3f);
} else if (len<=64) {
Ar = (B[0]>>crclen) | (B[1]<<(64-crclen));;
uint8_t A64_flip[8+offset];
@@ -688,7 +690,9 @@ uint32_t polar_decoder_int16(int16_t *input,
A64_flip[5+offset]=((uint8_t *)&Aprime)[2];
A64_flip[6+offset]=((uint8_t *)&Aprime)[1];
A64_flip[7+offset]=((uint8_t *)&Aprime)[0];
- crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8);
+ if (crclen==24) crc = (uint64_t)(crc24c(A64_flip,8*offset+len)>>8)&0xffffff;
+ else if (crclen==11) crc = (uint64_t)(crc11(A64_flip,8*offset+len)>>21)&0x7ff;
+ else if (crclen==6) crc = (uint64_t)(crc6(A64_flip,8*offset+len)>>26)&0x3f;
}
#if 0
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c
index daa23460987445274babe7919f10202fb243847a..42d500ae8670f509e3ccecde96558d0e102d8fcd 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_decoding_tools.c
@@ -197,8 +197,10 @@ decoder_node_t *add_nodes(int level, int first_leaf_index, t_nrPolar_params *pol
}
for (int i=0;i<Nv;i++) {
- if (polarParams->information_bit_pattern[i+first_leaf_index]>0)
- all_frozen_below=0;
+ if (polarParams->information_bit_pattern[i+first_leaf_index]>0) {
+ all_frozen_below=0;
+ break;
+ }
}
if (all_frozen_below==0)
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
index 6e01a05d0f959e80903db894b90e9b7e7028e560..a44a08a701256dcf1877abd7d1eeae4a491161df 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
@@ -146,7 +146,7 @@ void polar_encoder_dci(uint32_t *in,
uint16_t n_RNTI);
void polar_encoder_fast(uint64_t *A,
- uint32_t *out,
+ void *out,
int32_t crcmask,
uint8_t ones_flag,
t_nrPolar_params *polarParams);
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c
index 8e4b45f744fa34c1ac79af5ebef19ddcf2abaa03..27c062c217c1493292a1d567048a53c973dfa318 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_encoder.c
@@ -295,8 +295,8 @@ static inline void polar_rate_matching(t_nrPolar_params *polarParams,void *in,vo
void build_polar_tables(t_nrPolar_params *polarParams) {
// build table b -> c'
- AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K);
- AssertFatal(polarParams->K < 129, "K = %d > 64, is not supported yet\n",polarParams->K);
+ AssertFatal(polarParams->K > 17, "K = %d < 18, is not possible\n",polarParams->K);
+ AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K);
int bit_i,ip;
int numbytes = polarParams->K>>3;
int residue = polarParams->K&7;
@@ -327,7 +327,7 @@ void build_polar_tables(t_nrPolar_params *polarParams) {
AssertFatal(polarParams->N==512 || polarParams->N==256 || polarParams->N==128,"N = %d, not done yet\n",polarParams->N);
// build G bit vectors for information bit positions and convert the bit as bytes tables in nr_polar_kronecker_power_matrices.c to 64 bit packed vectors.
// keep only rows of G which correspond to information/crc bits
- polarParams->G_N_tab = (uint64_t **)malloc(polarParams->K * sizeof(int64_t *));
+ polarParams->G_N_tab = (uint64_t **)malloc((polarParams->K + polarParams->n_pc) * sizeof(int64_t *));
int k=0;
for (int i=0; i<polarParams->N; i++) {
@@ -408,18 +408,18 @@ void build_polar_tables(t_nrPolar_params *polarParams) {
}
void polar_encoder_fast(uint64_t *A,
- uint32_t *out,
+ void *out,
int32_t crcmask,
uint8_t ones_flag,
t_nrPolar_params *polarParams) {
- AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K);
+ // AssertFatal(polarParams->K > 32, "K = %d < 33, is not supported yet\n",polarParams->K);
AssertFatal(polarParams->K < 129, "K = %d > 128, is not supported yet\n",polarParams->K);
AssertFatal(polarParams->payloadBits < 65, "payload bits = %d > 64, is not supported yet\n",polarParams->payloadBits);
uint64_t B[4]= {0,0,0,0},Cprime[4]= {0,0,0,0};
int bitlen = polarParams->payloadBits;
// append crc
AssertFatal(bitlen<129,"support for payloads <= 128 bits\n");
- AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n");
+ // AssertFatal(polarParams->crcParityBits == 24,"support for 24-bit crc only for now\n");
//int bitlen0=bitlen;
uint64_t tcrc=0;
uint8_t offset = 0;
@@ -444,7 +444,9 @@ void polar_encoder_fast(uint64_t *A,
A32_flip[1+offset]=((uint8_t *)&Aprime)[2];
A32_flip[2+offset]=((uint8_t *)&Aprime)[1];
A32_flip[3+offset]=((uint8_t *)&Aprime)[0];
- tcrc = (uint64_t)((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8)));
+ if (polarParams->crcParityBits == 24) tcrc = (uint64_t)(((crcmask^(crc24c(A32_flip,8*offset+bitlen)>>8)))&0xffffff);
+ else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)(((crcmask^(crc11(A32_flip,bitlen)>>21)))&0x7ff);
+ else if (polarParams->crcParityBits == 6) tcrc = (uint64_t)(((crcmask^(crc6(A32_flip,bitlen)>>26)))&0x3f);
} else if (bitlen<=64) {
uint8_t A64_flip[8+offset];
if (ones_flag) {
@@ -461,7 +463,8 @@ void polar_encoder_fast(uint64_t *A,
A64_flip[5+offset]=((uint8_t *)&Aprime)[2];
A64_flip[6+offset]=((uint8_t *)&Aprime)[1];
A64_flip[7+offset]=((uint8_t *)&Aprime)[0];
- tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8)));
+ if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A64_flip,8*offset+bitlen)>>8)))&0xffffff;
+ else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A64_flip,bitlen)>>21)))&0x7ff;
}
else if (bitlen<=128) {
uint8_t A128_flip[16+offset];
@@ -479,7 +482,8 @@ void polar_encoder_fast(uint64_t *A,
A128_flip[10+offset]=((uint8_t*)&Aprime)[5]; A128_flip[11+offset]=((uint8_t*)&Aprime)[4];
A128_flip[12+offset]=((uint8_t*)&Aprime)[3]; A128_flip[13+offset]=((uint8_t*)&Aprime)[2];
A128_flip[14+offset]=((uint8_t*)&Aprime)[1]; A128_flip[15+offset]=((uint8_t*)&Aprime)[0];
- tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8)));
+ if (polarParams->crcParityBits == 24) tcrc = (uint64_t)((crcmask^(crc24c(A128_flip,8*offset+bitlen)>>8)))&0xffffff;
+ else if (polarParams->crcParityBits == 11) tcrc = (uint64_t)((crcmask^(crc11(A128_flip,bitlen)>>21)))&0x7ff;
}
int n;
@@ -522,6 +526,7 @@ void polar_encoder_fast(uint64_t *A,
#ifdef DEBUG_POLAR_ENCODER
+ printf("Polar encoder: (N,K) : (%d,%d)\n",polarParams->N,polarParams->K);
if (polarParams->K<65)
printf("A %llx B %llx Cprime %llx (payload bits %d,crc %x)\n",
(unsigned long long)(A[0]&(((uint64_t)1<<bitlen)-1)),
@@ -546,7 +551,7 @@ void polar_encoder_fast(uint64_t *A,
crc24c((uint8_t *)A,bitlen)>>8);
}
-#endif
+ #endif
/* printf("Bbytes : %x.%x.%x.%x.%x.%x.%x.%x\n",Bbyte[0],Bbyte[1],Bbyte[2],Bbyte[3],Bbyte[4],Bbyte[5],Bbyte[6],Bbyte[7]);
printf("%llx,%llx,%llx,%llx,%llx,%llx,%llx,%llx\n",polarParams->cprime_tab[0][Bbyte[0]] ,
polarParams->cprime_tab[1][Bbyte[1]] ,
@@ -671,5 +676,5 @@ void polar_encoder_fast(uint64_t *A,
}
}
memset((void*)out,0,polarParams->encoderLength>>3);
- polar_rate_matching(polarParams,(void *)D,(void *)out);
+ polar_rate_matching(polarParams,(void *)D, out);
}
diff --git a/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h b/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h
index 42051eb1b57c766eb6d2001b6061d113df307ab5..1ab664e5a21da20c9b08de6a95e99e23087d3490 100644
--- a/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h
+++ b/openair1/PHY/CODING/nrPolar_tools/nr_polar_uci_defs.h
@@ -33,8 +33,8 @@
#ifndef __NR_POLAR_UCI_DEFS__H__
#define __NR_POLAR_UCI_DEFS__H__
-#define NR_POLAR_UCI_MESSAGE_TYPE -1 //int8_t
-#define NR_POLAR_UCI_CRC_ERROR_CORRECTION_BITS 3
+#define NR_POLAR_UCI_PUCCH_MESSAGE_TYPE 2 //int8_t
+#define NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS 3
#define NR_POLAR_PUCCH_PAYLOAD_BITS 32
#define NR_POLAR_PUCCH_E 32
diff --git a/openair1/PHY/CODING/nr_polar_init.c b/openair1/PHY/CODING/nr_polar_init.c
index f6a06b3f7fc830ff77084540ded4f556ccf0426b..f6a700117dd4a4ac9b2b98d2f78ebd1a319dbba1 100644
--- a/openair1/PHY/CODING/nr_polar_init.c
+++ b/openair1/PHY/CODING/nr_polar_init.c
@@ -43,11 +43,12 @@ static void nr_polar_init(t_nrPolar_params * *polarParams,
uint8_t aggregation_level,
int decoder_flag) {
t_nrPolar_params *currentPtr = *polarParams;
- uint16_t aggregation_prime = nr_polar_aggregation_prime(aggregation_level);
+ uint16_t aggregation_prime = (messageType >= 2) ? aggregation_level : nr_polar_aggregation_prime(aggregation_level);
//Parse the list. If the node is already created, return without initialization.
while (currentPtr != NULL) {
//printf("currentPtr->idx %d, (%d,%d)\n",currentPtr->idx,currentPtr->payloadBits,currentPtr->encoderLength);
+ //LOG_D(PHY,"Looking for index %d\n",(messageType * messageLength * aggregation_prime));
if (currentPtr->idx == (messageType * messageLength * aggregation_prime)) return;
else currentPtr = currentPtr->nextPtr;
}
@@ -55,8 +56,9 @@ static void nr_polar_init(t_nrPolar_params * *polarParams,
// printf("currentPtr %p (polarParams %p)\n",currentPtr,polarParams);
//Else, initialize and add node to the end of the linked list.
t_nrPolar_params *newPolarInitNode = calloc(sizeof(t_nrPolar_params),1);
-
+
if (newPolarInitNode != NULL) {
+ // LOG_D(PHY,"Setting new polarParams index %d, messageType %d, messageLength %d, aggregation_prime %d\n",(messageType * messageLength * aggregation_prime),messageType,messageLength,aggregation_prime);
newPolarInitNode->idx = (messageType * messageLength * aggregation_prime);
newPolarInitNode->nextPtr = NULL;
//printf("newPolarInitNode->idx %d, (%d,%d,%d:%d)\n",newPolarInitNode->idx,messageType,messageLength,aggregation_prime,aggregation_level);
@@ -87,15 +89,44 @@ static void nr_polar_init(t_nrPolar_params * *polarParams,
newPolarInitNode->crcCorrectionBits = NR_POLAR_DCI_CRC_ERROR_CORRECTION_BITS;
newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P
//printf("Initializing polar parameters for DCI (K %d, E %d, L %d)\n",newPolarInitNode->payloadBits,newPolarInitNode->encoderLength,aggregation_level);
- } else if (messageType == -1) { //UCI
+ } else if (messageType == 2) { //UCI PUCCH2
+ AssertFatal(aggregation_level>2,"Aggregation level (%d) for PUCCH 2 encoding is NPRB and should be > 2\n",aggregation_level);
+ AssertFatal(messageLength>11,"Message length %d is too short for polar encoding of UCI\n",messageLength);
+ newPolarInitNode->n_max = NR_POLAR_PUCCH_N_MAX;
+ newPolarInitNode->i_il = NR_POLAR_PUCCH_I_IL;
+ newPolarInitNode->encoderLength = aggregation_level * 16;
+
+ newPolarInitNode->i_seg = 0;
+
+ if ((messageLength >= 360 && newPolarInitNode->encoderLength >= 1088)||
+ (messageLength >= 1013)) newPolarInitNode->i_seg = 1;
+
+ newPolarInitNode->crcParityBits = 11;
+ newPolarInitNode->n_pc = 0;
+ newPolarInitNode->n_pc_wm = 0;
+
+ if (messageLength < 20) {
+ newPolarInitNode->crcParityBits = 6;
+ newPolarInitNode->n_pc = 3;
+ if ((newPolarInitNode->encoderLength - messageLength - 6 + 3) < 193) newPolarInitNode->n_pc_wm = 1;
+ }
+
+
+
+ newPolarInitNode->i_bil = NR_POLAR_PUCCH_I_BIL;
+
+ newPolarInitNode->payloadBits = messageLength;
+ newPolarInitNode->crcCorrectionBits = NR_POLAR_PUCCH_CRC_ERROR_CORRECTION_BITS;
+ //newPolarInitNode->crc_generator_matrix=crc24c_generator_matrix(newPolarInitNode->payloadBits+newPolarInitNode->crcParityBits);//G_P
+ //LOG_D(PHY,"New polar node, encoderLength %d, aggregation_level %d\n",newPolarInitNode->encoderLength,aggregation_level);
} else {
AssertFatal(1 == 0, "[nr_polar_init] Incorrect Message Type(%d)", messageType);
}
newPolarInitNode->K = newPolarInitNode->payloadBits + newPolarInitNode->crcParityBits; // Number of bits to encode.
newPolarInitNode->N = nr_polar_output_length(newPolarInitNode->K,
- newPolarInitNode->encoderLength,
- newPolarInitNode->n_max);
+ newPolarInitNode->encoderLength,
+ newPolarInitNode->n_max);
newPolarInitNode->n = log2(newPolarInitNode->N);
newPolarInitNode->G_N = nr_polar_kronecker_power_matrices(newPolarInitNode->n);
//polar_encoder vectors:
@@ -191,16 +222,19 @@ t_nrPolar_params *nr_polar_params (int8_t messageType,
nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList,
messageType,messageLength,aggregation_level,decoding_flag);
t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList;
- const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level);
+ const int tag=messageType * messageLength * (messageType>=2 ? aggregation_level : nr_polar_aggregation_prime(aggregation_level));
+
+
while (polarParams != NULL) {
+ // LOG_D(PHY,"nr_polar_params : tag %d (from nr_polar_init %d)\n",tag,polarParams->idx);
if (polarParams->idx == tag)
return polarParams;
polarParams = polarParams->nextPtr;
}
- AssertFatal(false,"Polar Init tables internal failure\n");
+ AssertFatal(false,"Polar Init tables internal failure, no polarParams found\n");
return NULL;
}
diff --git a/openair1/PHY/CODING/nr_rate_matching.c b/openair1/PHY/CODING/nr_rate_matching.c
index 0cffc2d85200d7783381e4739884d5960665b671..5294e79b9f33a96709d3e994e4cb1792ea2ea351 100644
--- a/openair1/PHY/CODING/nr_rate_matching.c
+++ b/openair1/PHY/CODING/nr_rate_matching.c
@@ -364,8 +364,8 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm,
if (ind < Foffset) { // case where we have some bits before the filler and the rest after
memcpy((void*)e,(void*)(w+ind),Foffset-ind);
- if (E + F <= Ncb) { // E+F doesn't contain all coded bits
- memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind);
+ if (E + F <= Ncb-ind) { // E+F doesn't contain all coded bits
+ memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F),E-Foffset+ind);
k=E;
}
else {
@@ -375,11 +375,12 @@ int nr_rate_matching_ldpc(uint8_t Ilbrm,
}
else {
if (E + F <= Ncb-ind) { //E+F doesn't contain all coded bits
- memcpy((void*)(e+Foffset-ind),(void*)(w+Foffset+F-ind),E-Foffset+ind);
+ memcpy((void*)(e),(void*)(w+ind),E);
k=E;
}
else {
-
+ memcpy((void*)(e),(void*)(w+ind),Ncb-ind);
+ k=Ncb-ind;
}
}
diff --git a/openair1/PHY/INIT/lte_init.c b/openair1/PHY/INIT/lte_init.c
index 2d65521ab39cc381c0fa32cb313030f445402234..2c7e3e88eb5b06cc8c9a03f7e8713266687b06f0 100644
--- a/openair1/PHY/INIT/lte_init.c
+++ b/openair1/PHY/INIT/lte_init.c
@@ -275,6 +275,7 @@ void phy_config_request(PHY_Config_t *phy_config) {
fp->soundingrs_ul_config_common.srs_MaxUpPts = cfg->srs_config.max_up_pts.value;
fp->num_MBSFN_config = 0;
fp->NonMBSFN_config_flag =cfg->fembms_config.non_mbsfn_config_flag.value;
+ fp->FeMBMS_active = fp->NonMBSFN_config_flag;
fp->NonMBSFN_config.non_mbsfn_SubframeConfig = cfg->fembms_config.non_mbsfn_subframeconfig.value;
fp->NonMBSFN_config.radioframeAllocationPeriod = cfg->fembms_config.radioframe_allocation_period.value;
fp->NonMBSFN_config.radioframeAllocationOffset = cfg->fembms_config.radioframe_allocation_offset.value;
diff --git a/openair1/PHY/INIT/lte_init_ru.c b/openair1/PHY/INIT/lte_init_ru.c
index dddd6b1bd50b134456e540dca75a574ee09ed2cf..baea52083f0cb035262b4517af29b5df970dc8d9 100644
--- a/openair1/PHY/INIT/lte_init_ru.c
+++ b/openair1/PHY/INIT/lte_init_ru.c
@@ -186,7 +186,6 @@ void phy_free_RU(RU_t *ru) {
int i,j,p;
RU_CALIBRATION *calibration = &ru->calibration;
LOG_I(PHY, "Feeing RU signal buffers (if_south %s) nb_tx %d\n", ru_if_types[ru->if_south], ru->nb_tx);
- free_and_zero(ru->frame_parms);
if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so free memory for time-domain signals
for (i = 0; i < ru->nb_tx; i++) free_and_zero(ru->common.txdata[i]);
diff --git a/openair1/PHY/INIT/lte_init_ue.c b/openair1/PHY/INIT/lte_init_ue.c
index 082db61da94f53302e9a7a94588060f3fa0ed059..64a5992a64345b80a0550bc90a581e96d75d2bc2 100644
--- a/openair1/PHY/INIT/lte_init_ue.c
+++ b/openair1/PHY/INIT/lte_init_ue.c
@@ -137,7 +137,7 @@ void phy_config_sib2_ue(module_id_t Mod_id,int CC_id,
if (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) {
fp->MBSFN_config[i].fourFrames_flag = 0;
fp->MBSFN_config[i].mbsfn_SubframeConfig = mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]; // 6-bit subframe configuration
- LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] pattern is %d\n", i,
+ LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] oneFrame pattern is %d\n", i,
fp->MBSFN_config[i].mbsfn_SubframeConfig);
} else if (mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames) { // 24-bit subframe configuration
fp->MBSFN_config[i].fourFrames_flag = 1;
@@ -145,7 +145,7 @@ void phy_config_sib2_ue(module_id_t Mod_id,int CC_id,
mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[2]|
(mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[1]<<8)|
(mbsfn_SubframeConfigList->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]<<16);
- LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] pattern is %x\n", i,
+ LOG_I(PHY, "[CONFIG] LTE_MBSFN_SubframeConfig[%d] fourFrame pattern is %x\n", i,
fp->MBSFN_config[i].mbsfn_SubframeConfig);
}
}
@@ -212,7 +212,7 @@ void phy_config_sib1_fembms_ue(module_id_t Mod_id,int CC_id,
LTE_DL_FRAME_PARMS *fp = &ue->frame_parms;
if (nonMBSFN_SubframeConfig != NULL) {
- fp->NonMBSFN_config_flag = 0;
+ fp->NonMBSFN_config_flag = 1;
fp->NonMBSFN_config.radioframeAllocationPeriod=nonMBSFN_SubframeConfig->radioFrameAllocationPeriod_r14;
fp->NonMBSFN_config.radioframeAllocationOffset=nonMBSFN_SubframeConfig->radioFrameAllocationOffset_r14;
fp->NonMBSFN_config.non_mbsfn_SubframeConfig=(nonMBSFN_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | nonMBSFN_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
diff --git a/openair1/PHY/INIT/lte_parms.c b/openair1/PHY/INIT/lte_parms.c
index 12a5646df652e7237195d80f57ef75d05a33abce..f5b7a6c7e86022f5a2e8e389e78957a8830de204 100644
--- a/openair1/PHY/INIT/lte_parms.c
+++ b/openair1/PHY/INIT/lte_parms.c
@@ -93,6 +93,11 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms,
frame_parms->N_RBGS = 4;
frame_parms->N_RBG = 25;
+ frame_parms->ofdm_symbol_size_khz_1dot25 = 2*2*6144*osf;
+ frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2*2;
+ frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf);
+ frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf);
+
break;
case 75:
@@ -104,6 +109,12 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms,
frame_parms->nb_prefix_samples0=(frame_parms->nb_prefix_samples0*3)>>2;
frame_parms->N_RBGS = 4;
frame_parms->N_RBG = 25;
+
+ frame_parms->ofdm_symbol_size_khz_1dot25 = 2*6144*osf;
+ frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2;
+ frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf);
+ frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf);
+
break;
case 50:
@@ -115,6 +126,10 @@ int init_frame_parms(LTE_DL_FRAME_PARMS *frame_parms,
frame_parms->nb_prefix_samples0>>=(1-log2_osf);
frame_parms->N_RBGS = 3;
frame_parms->N_RBG = 17;
+ frame_parms->ofdm_symbol_size_khz_1dot25 = 2*6144*osf;
+ frame_parms->first_carrier_offset_khz_1dot25 = frame_parms->ofdm_symbol_size_khz_1dot25 - 1800*2;
+ frame_parms->nb_prefix_samples_khz_1dot25>>=(2-log2_osf);
+ frame_parms->nb_prefix_samples0_khz_1dot25>>=(2-log2_osf);
break;
case 25:
diff --git a/openair1/PHY/INIT/nr_init.c b/openair1/PHY/INIT/nr_init.c
index af411fc7d776e4a4ac4d0d4308ab4901ac4d59a9..136092f2d4a60c7d8b4496f39044683a871cdc55 100644
--- a/openair1/PHY/INIT/nr_init.c
+++ b/openair1/PHY/INIT/nr_init.c
@@ -25,7 +25,8 @@
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "PHY/INIT/phy_init.h"
#include "PHY/CODING/nrPolar_tools/nr_polar_pbch_defs.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
/*#include "RadioResourceConfigCommonSIB.h"
#include "RadioResourceConfigDedicated.h"
#include "TDD-Config.h"
@@ -39,7 +40,6 @@
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "SCHED_NR/fapi_nr_l1.h"
-#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
#include "nfapi_nr_interface.h"
/*
@@ -112,6 +112,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
);*/
LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_gNB][MOD %02"PRIu8"][]\n", gNB->Mod_id);
crcTableInit();
+ init_scrambling_luts();
+ init_pucch2_luts();
load_nrLDPClib();
// PBCH DMRS gold sequences generation
nr_init_pbch_dmrs(gNB);
@@ -130,6 +132,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
}
}
+ nr_generate_modulation_table();
nr_init_pdcch_dmrs(gNB, cfg->cell_config.phy_cell_id.value);
nr_init_pbch_interleaver(gNB->nr_pbch_interleaver);
//PDSCH DMRS init
@@ -151,11 +154,11 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
}
}
-
nr_init_pdsch_dmrs(gNB, cfg->cell_config.phy_cell_id.value);
//PUSCH DMRS init
gNB->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(2*sizeof(uint32_t ***));
+
uint32_t ****pusch_dmrs = gNB->nr_gold_pusch_dmrs;
for(int nscid=0; nscid<2; nscid++) {
@@ -174,6 +177,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
}
uint32_t Nid_pusch[2] = {cfg->cell_config.phy_cell_id.value,cfg->cell_config.phy_cell_id.value};
+ LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[0],Nid_pusch[1]);
nr_gold_pusch(gNB, &Nid_pusch[0]);
/// Transport init necessary for NR synchro
@@ -230,6 +234,8 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
*/
prach_vars->prach_ifft = (int32_t *)malloc16_clear(1024*2*sizeof(int32_t));
+ init_prach_list(gNB);
+
int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
@@ -403,7 +409,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
fp->dl_CarrierFreq = 3500000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value);
fp->ul_CarrierFreq = 3500000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000);
fp->nr_band = 78;
- fp->threequarter_fs= 0;
+// fp->threequarter_fs= 0;
gNB_config->carrier_config.dl_bandwidth.value = config_bandwidth(mu, N_RB_DL, fp->nr_band);
@@ -415,6 +421,7 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
void nr_phy_config_request(NR_PHY_Config_t *phy_config) {
uint8_t Mod_id = phy_config->Mod_id;
+ uint8_t short_sequence, num_sequences, rootSequenceIndex, fd_occasion;
NR_DL_FRAME_PARMS *fp = &RC.gNB[Mod_id]->frame_parms;
nfapi_nr_config_request_scf_t *gNB_config = &RC.gNB[Mod_id]->gNB_config;
@@ -478,6 +485,14 @@ void nr_phy_config_request(NR_PHY_Config_t *phy_config) {
return;
}
+ fd_occasion = 0;
+ nfapi_nr_prach_config_t *prach_config = &gNB_config->prach_config;
+ short_sequence = prach_config->prach_sequence_length.value;
+ num_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value;
+ rootSequenceIndex = prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value;
+
+ compute_nr_prach_seq(short_sequence, num_sequences, rootSequenceIndex, RC.gNB[Mod_id]->X_u);
+
RC.gNB[Mod_id]->configured = 1;
LOG_I(PHY,"gNB %d configured\n",Mod_id);
}
@@ -490,6 +505,12 @@ void init_nr_transport(PHY_VARS_gNB *gNB) {
LOG_I(PHY, "Initialise nr transport\n");
uint16_t grid_size = cfg->carrier_config.dl_grid_size[fp->numerology_index].value;
+ for (i=0; i<NUMBER_OF_NR_PUCCH_MAX; i++) {
+ LOG_I(PHY,"Allocating Transport Channel Buffers for PUCCH %d/%d\n",i,NUMBER_OF_NR_PUCCH_MAX);
+ gNB->pucch[i] = new_gNB_pucch();
+ AssertFatal(gNB->pucch[i]!=NULL,"Can't initialize pucch %d \n", i);
+ }
+
for (i=0; i<NUMBER_OF_NR_DLSCH_MAX; i++) {
LOG_I(PHY,"Allocating Transport Channel Buffers for DLSCH %d/%d\n",i,NUMBER_OF_NR_DLSCH_MAX);
diff --git a/openair1/PHY/INIT/nr_init_ru.c b/openair1/PHY/INIT/nr_init_ru.c
index 2dcf035866e36f60c865e18f8bf60d593867ac56..28b13112ce608d246f49a6f09a4d1258ba9ebec4 100644
--- a/openair1/PHY/INIT/nr_init_ru.c
+++ b/openair1/PHY/INIT/nr_init_ru.c
@@ -22,6 +22,7 @@
#include "phy_init.h"
#include "SCHED/sched_common.h"
#include "PHY/phy_extern.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "SIMULATION/TOOLS/sim.h"
/*#include "RadioResourceConfigCommonSIB.h"
#include "RadioResourceConfigDedicated.h"
@@ -44,9 +45,11 @@ int nr_phy_init_RU(RU_t *ru) {
nfapi_nr_config_request_scf_t *cfg;
ru->nb_log_antennas=0;
for (int n=0;n<RC.nb_nr_L1_inst;n++) {
- cfg = &RC.gNB[n]->gNB_config;
+ cfg = &ru->config;
if (cfg->carrier_config.num_tx_ant.value > ru->nb_log_antennas) ru->nb_log_antennas = cfg->carrier_config.num_tx_ant.value;
}
+ // copy configuration from gNB[0] in to RU, assume that all gNB instances sharing RU use the same configuration (at least the parts that are needed by the RU, numerology and PRACH)
+
AssertFatal(ru->nb_log_antennas > 0 && ru->nb_log_antennas < 13, "ru->nb_log_antennas %d ! \n",ru->nb_log_antennas);
if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals
// Time-domain signals
@@ -107,7 +110,8 @@ int nr_phy_init_RU(RU_t *ru) {
ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*));
for (i=0; i<ru->nb_rx; i++) {
- ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) );
+ // largest size for PRACH FFT is 4x98304 (16*24576)
+ ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( 4*98304*2*sizeof(int16_t) );
LOG_D(PHY,"[INIT] prach_vars->rxsigF[%d] = %p\n",i,ru->prach_rxsigF[i]);
}
@@ -117,9 +121,9 @@ int nr_phy_init_RU(RU_t *ru) {
LOG_E(PHY,"[INIT] %s() RC.nb_nr_L1_inst:%d \n", __FUNCTION__, RC.nb_nr_L1_inst);
int beam_count = 0;
- if (ru->nb_log_antennas>1) {
+ if (ru->nb_tx>1) {//Enable beamforming when nb_tx > 1
for (p=0;p<ru->nb_log_antennas;p++) {
- if ((fp->L_ssb >> p) & 0x01)
+ if ((fp->L_ssb >> (63-p)) & 0x01)//64 bit-map with the MSB @2â¶Â³ corresponds to SSB ssb_index 0
beam_count++;
}
AssertFatal(ru->nb_bfw==(beam_count*ru->nb_tx),"Number of beam weights from config file is %d while the expected number is %d",ru->nb_bfw,(beam_count*ru->nb_tx));
@@ -127,7 +131,7 @@ int nr_phy_init_RU(RU_t *ru) {
int l_ind = 0;
for (i=0; i<RC.nb_nr_L1_inst; i++) {
for (p=0;p<ru->nb_log_antennas;p++) {
- if ((fp->L_ssb >> p) & 0x01) {
+ if ((fp->L_ssb >> (63-p)) & 0x01) {
ru->beam_weights[i][p] = (int32_t **)malloc16_clear(ru->nb_tx*sizeof(int32_t*));
for (j=0; j<ru->nb_tx; j++) {
ru->beam_weights[i][p][j] = (int32_t *)malloc16_clear(fp->ofdm_symbol_size*sizeof(int32_t));
@@ -144,6 +148,8 @@ int nr_phy_init_RU(RU_t *ru) {
ru->common.sync_corr = (uint32_t*)malloc16_clear( LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*sizeof(uint32_t)*fp->samples_per_subframe_wCP );
+ init_prach_ru_list(ru);
+
return(0);
}
diff --git a/openair1/PHY/INIT/nr_init_ue.c b/openair1/PHY/INIT/nr_init_ue.c
index 5c812e340fa3ca6f24eaa7c739ca0f16722c3025..fed58dea12ddbbe5da86228ab7caecfbef8dfa40 100644
--- a/openair1/PHY/INIT/nr_init_ue.c
+++ b/openair1/PHY/INIT/nr_init_ue.c
@@ -39,6 +39,7 @@
#include "PHY/NR_REFSIG/pss_nr.h"
#include "PHY/NR_REFSIG/ul_ref_seq_nr.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
+#include "PHY/NR_REFSIG/nr_refsig.h"
//uint8_t dmrs1_tab_ue[8] = {0,2,3,4,6,8,9,10};
@@ -77,19 +78,19 @@ void phy_config_sib2_ue(uint8_t Mod_id,int CC_id,
LOG_I(PHY,"[UE%d] Applying radioResourceConfigCommon from eNB%d\n",Mod_id,eNB_id);
- fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex;
+ ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex;
- fp->prach_config_common.prach_Config_enabled=1;
- fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex;
- fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag;
- fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig;
- fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset;
+ ue->prach_vars[eNB_id]->prach_Config_enabled=1;
+ //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_ConfigIndex;
+ ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.highSpeedFlag;
+ ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig;
+ //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo.prach_FreqOffset;
- compute_prach_seq(fp->prach_config_common.rootSequenceIndex,
- fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
- fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
- fp->prach_config_common.prach_ConfigInfo.highSpeedFlag,
- fp->frame_type,ue->X_u);
+ //compute_prach_seq(fp->prach_config_common.rootSequenceIndex,
+ // fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
+ // fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
+ // fp->prach_config_common.prach_ConfigInfo.highSpeedFlag,
+ // fp->frame_type,ue->X_u);
@@ -226,12 +227,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_
LOG_I(PHY,"[UE%d] Handover triggered: Applying radioResourceConfigCommon from eNB %d\n",
Mod_id,eNB_id);
- fp->prach_config_common.rootSequenceIndex =radioResourceConfigCommon->prach_Config.rootSequenceIndex;
- fp->prach_config_common.prach_Config_enabled=1;
- fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex;
- fp->prach_config_common.prach_ConfigInfo.highSpeedFlag =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag;
- fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig;
- fp->prach_config_common.prach_ConfigInfo.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset;
+ ue->prach_vars[eNB_id]->prach_pdu.root_seq_id =radioResourceConfigCommon->prach_Config.rootSequenceIndex;
+ ue->prach_vars[eNB_id]->prach_Config_enabled=1;
+ //ue->prach_vars[eNB_id]->prach_pdu.prach_ConfigIndex =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex;
+ ue->prach_vars[eNB_id]->prach_pdu.restricted_set =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->highSpeedFlag;
+ ue->prach_vars[eNB_id]->prach_pdu.num_cs =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->zeroCorrelationZoneConfig;
+ //ue->prach_vars[eNB_id]->prach_pdu.prach_FreqOffset =radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_FreqOffset;
// prach_fmt = get_prach_fmt(radioResourceConfigCommon->prach_Config.prach_ConfigInfo->prach_ConfigIndex,fp->frame_type);
// N_ZC = (prach_fmt <4)?839:139;
@@ -239,12 +240,12 @@ void phy_config_sib13_ue(uint8_t Mod_id,int CC_id,uint8_t eNB_id,int mbsfn_Area_
// prach_root_sequence_map4[fp->prach_config_common.rootSequenceIndex];
//compute_prach_seq(u,N_ZC, PHY_vars_UE_g[Mod_id]->X_u);
- compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex,
- PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
- PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
- PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag,
- fp->frame_type,
- PHY_vars_UE_g[Mod_id][CC_id]->X_u);
+ //compute_prach_seq(PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.rootSequenceIndex,
+ // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
+ // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
+ // PHY_vars_UE_g[Mod_id][CC_id]->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag,
+ // fp->frame_type,
+ // PHY_vars_UE_g[Mod_id][CC_id]->X_u);
fp->pucch_config_common.deltaPUCCH_Shift = 1+radioResourceConfigCommon->pucch_ConfigCommon->deltaPUCCH_Shift;
@@ -657,8 +658,8 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
abstraction_flag = 0;
fp->nb_antennas_tx = 1;
fp->nb_antennas_rx=1;
- dmrs_UplinkConfig_t *dmrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig;
- ptrs_UplinkConfig_t *ptrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig;
+ // dmrs_UplinkConfig_t *dmrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig;
+ // ptrs_UplinkConfig_t *ptrs_Uplink_Config = &ue->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig;
printf("Initializing UE vars (abstraction %"PRIu8") for eNB TXant %"PRIu8", UE RXant %"PRIu8"\n",abstraction_flag,fp->nb_antennas_tx,fp->nb_antennas_rx);
//LOG_D(PHY,"[MSC_NEW][FRAME 00000][PHY_UE][MOD %02u][]\n", ue->Mod_id+NB_eNB_INST);
phy_init_nr_top(ue);
@@ -681,6 +682,8 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
ue->bitrate[eNB_id] = 0;
ue->total_received_bits[eNB_id] = 0;
}
+ // init NR modulation lookup tables
+ nr_generate_modulation_table();
/////////////////////////PUSCH init/////////////////////////
///////////
@@ -710,9 +713,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
}
//------------- config DMRS parameters--------------//
- dmrs_Uplink_Config->pusch_dmrs_type = pusch_dmrs_type1;
- dmrs_Uplink_Config->pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0;
- dmrs_Uplink_Config->pusch_maxLength = pusch_len1;
+ // dmrs_Uplink_Config->pusch_dmrs_type = pusch_dmrs_type1;
+ // dmrs_Uplink_Config->pusch_dmrs_AdditionalPosition = pusch_dmrs_pos0;
+ // dmrs_Uplink_Config->pusch_maxLength = pusch_len1;
//-------------------------------------------------//
ue->dmrs_DownlinkConfig.pdsch_dmrs_type = pdsch_dmrs_type1;
ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition = pdsch_dmrs_pos0;
@@ -745,15 +748,13 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
/////////////////////////PUSCH PTRS init/////////////////////////
///////////
- ue->ptrs_configured = 0; // flag to be toggled by RCC
-
//------------- config PTRS parameters--------------//
- ptrs_Uplink_Config->timeDensity.ptrs_mcs1 = 0; // setting MCS values to 0 indicate abscence of time_density field in the configuration
- ptrs_Uplink_Config->timeDensity.ptrs_mcs2 = 0;
- ptrs_Uplink_Config->timeDensity.ptrs_mcs3 = 0;
- ptrs_Uplink_Config->frequencyDensity.n_rb0 = 0; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration
- ptrs_Uplink_Config->frequencyDensity.n_rb1 = 0;
- ptrs_Uplink_Config->resourceElementOffset = 0;
+ // ptrs_Uplink_Config->timeDensity.ptrs_mcs1 = 2; // setting MCS values to 0 indicate abscence of time_density field in the configuration
+ // ptrs_Uplink_Config->timeDensity.ptrs_mcs2 = 4;
+ // ptrs_Uplink_Config->timeDensity.ptrs_mcs3 = 10;
+ // ptrs_Uplink_Config->frequencyDensity.n_rb0 = 25; // setting N_RB values to 0 indicate abscence of frequency_density field in the configuration
+ // ptrs_Uplink_Config->frequencyDensity.n_rb1 = 75;
+ // ptrs_Uplink_Config->resourceElementOffset = 0;
//-------------------------------------------------//
///////////
@@ -960,7 +961,9 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
// enable MIB/SIB decoding by default
ue->decode_MIB = 1;
ue->decode_SIB = 1;
- init_prach_tables(839);
+
+ init_nr_prach_tables(839);
+
return 0;
}
diff --git a/openair1/PHY/INIT/nr_parms.c b/openair1/PHY/INIT/nr_parms.c
index c3fe9c54b1b065a1776d5691807caf45e7e00562..6045930b17e3f2b7d1c2cd11abc3ec83b07d4124 100644
--- a/openair1/PHY/INIT/nr_parms.c
+++ b/openair1/PHY/INIT/nr_parms.c
@@ -308,7 +308,7 @@ int nr_init_frame_parms(nfapi_nr_config_request_scf_t* cfg,
int num_tx_ant = (cfg == NULL) ? fp->Lmax : cfg->carrier_config.num_tx_ant.value;
for (int p=0; p<num_tx_ant; p++)
- fp->N_ssb += ((fp->L_ssb >> p) & 0x01);
+ fp->N_ssb += ((fp->L_ssb >> (63-p)) & 0x01);
return 0;
@@ -389,7 +389,7 @@ int nr_init_frame_parms_ue(NR_DL_FRAME_PARMS *fp,
fp->N_ssb = 0;
for (int p=0; p<fp->Lmax; p++)
- fp->N_ssb += ((fp->L_ssb >> p) & 0x01);
+ fp->N_ssb += ((fp->L_ssb >> (63-p)) & 0x01);
return 0;
}
diff --git a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c
index aaa138fcd9d8ca066a678496c30b015e70c5edde..f85162e095d4c711439ae0a9eceb2baf38bf1e83 100644
--- a/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c
+++ b/openair1/PHY/LTE_ESTIMATION/lte_adjust_sync_eNB.c
@@ -112,18 +112,12 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms,
}
-int lte_est_timing_advance_pusch(PHY_VARS_eNB *eNB,
- module_id_t UE_id)
+int lte_est_timing_advance_pusch(LTE_DL_FRAME_PARMS *frame_parms,
+ int32_t **ul_ch_estimates_time)
{
int temp, i, aa, max_pos=0, max_val=0;
short Re,Im;
- RU_t *ru;
- ru = RC.ru[UE_id];
- LTE_DL_FRAME_PARMS *frame_parms = (eNB==NULL) ? ru->frame_parms : &eNB->frame_parms;
- LTE_eNB_PUSCH *eNB_pusch_vars = (eNB!=NULL) ? eNB->pusch_vars[UE_id] : (LTE_eNB_PUSCH*)NULL;
- RU_CALIBRATION *calibration = &ru->calibration;
- int32_t **ul_ch_estimates_time = (eNB==NULL) ? calibration->drs_ch_estimates_time : eNB_pusch_vars->drs_ch_estimates_time;
uint8_t cyclic_shift = 0;
int sync_pos = (frame_parms->ofdm_symbol_size-cyclic_shift*frame_parms->ofdm_symbol_size/12)%(frame_parms->ofdm_symbol_size);
@@ -149,7 +143,7 @@ int lte_est_timing_advance_pusch(PHY_VARS_eNB *eNB,
max_pos = max_pos-frame_parms->ofdm_symbol_size;
//#ifdef DEBUG_PHY
- LOG_D(PHY,"frame %d: max_pos = %d, sync_pos=%d\n",eNB->proc.frame_rx,max_pos,sync_pos);
+ LOG_D(PHY,"max_pos = %d, sync_pos=%d\n",max_pos,sync_pos);
//#endif //DEBUG_PHY
return max_pos - sync_pos;
diff --git a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c
index 333a6f08665ef8a34dd6c0a4ad480f931264aba8..4ad050ccea24e42c8b9bfbbe143086707dc588a6 100644
--- a/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c
+++ b/openair1/PHY/LTE_ESTIMATION/lte_dl_mbsfn_channel_estimation.c
@@ -22,7 +22,7 @@
/*! \file config_ue.c
* \brief This includes FeMBMS UE Channel Estimation Procedures for FeMBMS 1.25KHz Carrier Spacing
* \author Javier Morgade
- * \date 2019
+ * \date 2020
* \version 0.1
* \email: javier.morgade@ieee.org
* @ingroup _phy
@@ -768,8 +768,8 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
module_id_t eNB_id,
uint8_t eNB_offset,
int subframe) {
- int pilot_khz_1dot25[600] __attribute__((aligned(16)));
- unsigned char aarx/*,aa*/;
+ int pilot_khz_1dot25[2*2*600] __attribute__((aligned(16)));
+ unsigned char aarx,aa;
//unsigned int rb;
int16_t ch[2];
short *pil,*rxF,*dl_ch/*,*ch0,*ch1,*ch11,*chp,*ch_prev*/;
@@ -783,7 +783,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].rxdataF;
ch_offset = 0;//(l*(ue->frame_parms.ofdm_symbol_size));
symbol_offset = 0;//ch_offset;//phy_vars_ue->lte_frame_parms.ofdm_symbol_size*l;
- AssertFatal( ue->frame_parms.N_RB_DL==25,"OFDM symbol size %d not yet supported for FeMBMS\n",ue->frame_parms.N_RB_DL);
+ //AssertFatal( ue->frame_parms.N_RB_DL==25,"OFDM symbol size %d not yet supported for FeMBMS\n",ue->frame_parms.N_RB_DL);
if( (subframe&0x1) == 0) {
f=filt24_0_khz_1dot25;
@@ -823,7 +823,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
k=3;
}
- if(ue->frame_parms.N_RB_DL==25) {
+ if(1/*ue->frame_parms.N_RB_DL==25*/) {
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
multadd_real_vector_complex_scalar(fl,
@@ -843,7 +843,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
rxF+=12;
dl_ch+=16;
- for(pilot_cnt=2; pilot_cnt<299; pilot_cnt+=2) {
+ for(pilot_cnt=2; pilot_cnt<ue->frame_parms.N_RB_DL*12-1/*299*/; pilot_cnt+=2) {
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
multadd_real_vector_complex_scalar(f,
@@ -866,7 +866,7 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
rxF = (int16_t *)&rxdataF[aarx][((symbol_offset+1+k))]; //Skip DC offset
- for(pilot_cnt=0; pilot_cnt<297; pilot_cnt+=2) {
+ for(pilot_cnt=0; pilot_cnt<ue->frame_parms.N_RB_DL*12-3/*297*/; pilot_cnt+=2) {
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
multadd_real_vector_complex_scalar(f,
@@ -905,6 +905,32 @@ int lte_dl_mbsfn_khz_1dot25_channel_estimation(PHY_VARS_UE *ue,
}
}
+ // do ifft of channel estimate
+ for (aa=0; aa<ue->frame_parms.nb_antennas_rx*ue->frame_parms.nb_antennas_tx; aa++) {
+ if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa]) {
+ switch (ue->frame_parms.N_RB_DL) {
+ case 25:
+ idft(IDFT_6144,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
+ (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
+ 1);
+ break;
+ case 50:
+ idft(IDFT_12288,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
+ (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
+ 1);
+ break;
+ case 100:
+ idft(IDFT_24576,(int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates[0][aa][8],
+ (int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[subframe]].dl_ch_estimates_time[0][aa],
+ 1);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+
return(0);
}
diff --git a/openair1/PHY/LTE_ESTIMATION/lte_estimation.h b/openair1/PHY/LTE_ESTIMATION/lte_estimation.h
index 01883224db2c647a44f0c857b9f48456f19e3bcd..fc40280853ec3adb48cc6866041508b8e3e0838b 100644
--- a/openair1/PHY/LTE_ESTIMATION/lte_estimation.h
+++ b/openair1/PHY/LTE_ESTIMATION/lte_estimation.h
@@ -220,8 +220,12 @@ void phy_adjust_gain (PHY_VARS_UE *phy_vars_ue,
uint32_t rx_power_fil_dB,
unsigned char eNB_id);
-int lte_ul_channel_estimation(PHY_VARS_eNB *phy_vars_eNB,
+int32_t lte_ul_channel_estimation(LTE_DL_FRAME_PARMS *frame_parms,
L1_rxtx_proc_t *proc,
+ LTE_eNB_ULSCH_t * ulsch,
+ int32_t **ul_ch_estimates,
+ int32_t **ul_ch_estimates_time,
+ int32_t **rxdataF_ext,
module_id_t UE_id,
uint8_t l,
uint8_t Ns);
@@ -258,7 +262,8 @@ int lte_est_timing_advance(LTE_DL_FRAME_PARMS *frame_parms,
unsigned char number_of_cards,
short coef);
-int lte_est_timing_advance_pusch(PHY_VARS_eNB* phy_vars_eNB,module_id_t UE_id);
+int lte_est_timing_advance_pusch(LTE_DL_FRAME_PARMS *frame_parms,
+ int32_t **ul_ch_estimates_time);
void lte_eNB_I0_measurements(PHY_VARS_eNB *phy_vars_eNB,
int subframe,
diff --git a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c
index 7caaf07406b0355d970165fd8a1eb793f9710197..755111feb812e7f0ad1dec9084dc17520ba0fd6f 100644
--- a/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c
+++ b/openair1/PHY/LTE_ESTIMATION/lte_ul_channel_estimation.c
@@ -34,23 +34,17 @@ static int16_t ru_90c[2*128] = {32767, 0,32766, -402,32758, -804,32746, -1206,32
#define SCALE 0x3FFF
-int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB,
+int32_t lte_ul_channel_estimation(LTE_DL_FRAME_PARMS *frame_parms,
L1_rxtx_proc_t *proc,
+ LTE_eNB_ULSCH_t * ulsch,
+ int32_t **ul_ch_estimates,
+ int32_t **ul_ch_estimates_time,
+ int32_t **rxdataF_ext,
module_id_t UE_id,
unsigned char l,
unsigned char Ns) {
- RU_t *ru;
- ru = RC.ru[UE_id];
- LTE_DL_FRAME_PARMS *frame_parms = (eNB!=NULL) ? &eNB->frame_parms : ru->frame_parms;
- LTE_eNB_PUSCH *pusch_vars = (eNB!=NULL) ? eNB->pusch_vars[UE_id] : NULL;
- RU_CALIBRATION *calibration = &ru->calibration;
- int32_t **ul_ch_estimates = (eNB!=NULL) ? pusch_vars->drs_ch_estimates : calibration->drs_ch_estimates;
- AssertFatal(ul_ch_estimates != NULL, "ul_ch_estimates is null (eNB %p, pusch %p, pusch->drs_ch_estimates %p, pusch->drs_ch_estimates[0] %p ul_ch_estimates %p UE_id %d)\n",eNB,pusch_vars,
- pusch_vars->drs_ch_estimates,pusch_vars->drs_ch_estimates[0],ul_ch_estimates,UE_id);
- int32_t **ul_ch_estimates_time = (eNB!=NULL) ? pusch_vars->drs_ch_estimates_time : calibration->drs_ch_estimates_time;
+ AssertFatal(ul_ch_estimates != NULL, "ul_ch_estimates is null ");
AssertFatal(ul_ch_estimates_time != NULL, "ul_ch_estimates_time is null\n");
- int32_t **rxdataF_ext = (eNB!=NULL) ? pusch_vars->rxdataF_ext : calibration->rxdataF_ext;
-
int subframe = proc->subframe_rx;
uint8_t harq_pid;
@@ -83,16 +77,16 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB,
#endif
int32_t temp_in_ifft_0[2048*2] __attribute__((aligned(32)));
- if (eNB->ulsch[UE_id]->ue_type > 0) harq_pid = 0;
+ if (ulsch->ue_type > 0) harq_pid = 0;
else {
harq_pid = subframe2harq_pid(frame_parms,proc->frame_rx,subframe);
}
- uint16_t N_rb_alloc = eNB->ulsch[UE_id]->harq_processes[harq_pid]->nb_rb;
+ uint16_t N_rb_alloc = ulsch->harq_processes[harq_pid]->nb_rb;
int32_t tmp_estimates[N_rb_alloc*12] __attribute__((aligned(16)));
Msc_RS = N_rb_alloc*12;
cyclic_shift = (frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.cyclicShift +
- eNB->ulsch[UE_id]->harq_processes[harq_pid]->n_DMRS2 +
+ ulsch->harq_processes[harq_pid]->n_DMRS2 +
frame_parms->pusch_config_common.ul_ReferenceSignalsPUSCH.nPRS[(subframe<<1)+Ns]) % 12;
Msc_idx_ptr = (uint16_t *) bsearch(&Msc_RS, dftsizes, 34, sizeof(uint16_t), compareints);
@@ -276,7 +270,7 @@ int32_t lte_ul_channel_estimation(PHY_VARS_eNB *eNB,
#if T_TRACER
if (aa == 0)
- T(T_ENB_PHY_UL_CHANNEL_ESTIMATE, T_INT(0), T_INT(eNB->ulsch[UE_id]->rnti),
+ T(T_ENB_PHY_UL_CHANNEL_ESTIMATE, T_INT(0), T_INT(ulsch->rnti),
T_INT(proc->frame_rx), T_INT(subframe),
T_INT(0), T_BUFFER(ul_ch_estimates_time[0], 512 * 4));
diff --git a/openair1/PHY/LTE_REFSIG/lte_refsig.h b/openair1/PHY/LTE_REFSIG/lte_refsig.h
index 45402436f70abbc6756682b999fe1532f5c74c6e..84a2676082fe151c208e31709cd4d0078b2fb012 100644
--- a/openair1/PHY/LTE_REFSIG/lte_refsig.h
+++ b/openair1/PHY/LTE_REFSIG/lte_refsig.h
@@ -106,6 +106,16 @@ int lte_dl_mbsfn(PHY_VARS_eNB *phy_vars_eNB, int32_t *output,
short amp,
int subframe,
unsigned char l);
+/*! \brief This function generates the 1.25KHz MBSFN reference signal sequence (36-211, Sec 6.10.1.2)
+@param phy_vars_eNB Pointer to eNB variables
+@param output Output vector for OFDM symbol (Frequency Domain)
+@param amp Q15 amplitude
+*/
+
+int lte_dl_mbsfn_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB, int32_t *output,
+ short amp,
+ int subframe);
+
/*!\brief This function generates the cell-specific reference signal sequence (36-211, Sec 6.10.1.1) for channel estimation upon reception
diff --git a/openair1/PHY/LTE_REFSIG/mod_table.h b/openair1/PHY/LTE_REFSIG/mod_table.h
index 7bdc1f518f1c072c2381e13ec726154af1e66493..29ae9f4495dfcfea473fbbeb1f0b9fba5d521857 100644
--- a/openair1/PHY/LTE_REFSIG/mod_table.h
+++ b/openair1/PHY/LTE_REFSIG/mod_table.h
@@ -19,9 +19,14 @@
* contact@openairinterface.org
*/
+#ifndef __PHY_LTE_REFSIG_MOD_TABLE__H__
+#define __PHY_LTE_REFSIG_MOD_TABLE__H__
+
#define MOD_TABLE_SIZE_SHORT 304
#define MOD_TABLE_QPSK_OFFSET 1
#define MOD_TABLE_16QAM_OFFSET 5
#define MOD_TABLE_64QAM_OFFSET 21
#define MOD_TABLE_PSS_OFFSET 85
short mod_table[MOD_TABLE_SIZE_SHORT] = {0,0,768,768,768,-768,-768,768,-768,-768,343,343,343,1030,1030,343,1030,1030,343,-343,343,-1030,1030,-343,1030,-1030,-343,343,-343,1030,-1030,343,-1030,1030,-343,-343,-343,-1030,-1030,-343,-1030,-1030,503,503,503,168,168,503,168,168,503,838,503,1173,168,838,168,1173,838,503,838,168,1173,503,1173,168,838,838,838,1173,1173,838,1173,1173,503,-503,503,-168,168,-503,168,-168,503,-838,503,-1173,168,-838,168,-1173,838,-503,838,-168,1173,-503,1173,-168,838,-838,838,-1173,1173,-838,1173,-1173,-503,503,-503,168,-168,503,-168,168,-503,838,-503,1173,-168,838,-168,1173,-838,503,-838,168,-1173,503,-1173,168,-838,838,-838,1173,-1173,838,-1173,1173,-503,-503,-503,-168,-168,-503,-168,-168,-503,-838,-503,-1173,-168,-838,-168,-1173,-838,-503,-838,-168,-1173,-503,-1173,-168,-838,-838,-838,-1173,-1173,-838,-1173,-1173,1086,0,1081,-108,1065,-215,1038,-320,1001,-422,954,-519,897,-612,832,-698,758,-777,677,-849,589,-912,495,-966,397,-1011,294,-1046,189,-1070,81,-1083,-27,-1086,-135,-1078,-242,-1059,-346,-1030,-447,-990,-543,-941,-634,-882,-719,-814,-796,-739,-866,-656,-927,-566,-979,-471,-1021,-371,-1053,-268,-1074,-162,-1085,-54,-1085,54,-1074,162,-1053,268,-1021,371,-979,471,-927,566,-866,656,-796,739,-719,814,-634,882,-543,941,-447,990,-346,1030,-242,1059,-135,1078,-27,1086,81,1083,189,1070,294,1045,397,1011,495,966,589,912,677,849,758,777,832,698,897,612,954,519,1001,422,1038,320,1065,215,1081,108,16384,0,8192,0,4096,0,2048,0};
+
+#endif
diff --git a/openair1/PHY/LTE_TRANSPORT/dci_tools.c b/openair1/PHY/LTE_TRANSPORT/dci_tools.c
index ce409de1318460a5e4cb3f5a5cf2c17d6aaff15a..8de011acef3a3cdf9d31f3880cc6063bc998693b 100644
--- a/openair1/PHY/LTE_TRANSPORT/dci_tools.c
+++ b/openair1/PHY/LTE_TRANSPORT/dci_tools.c
@@ -2006,11 +2006,6 @@ void fill_ulsch(PHY_VARS_eNB *eNB,int UE_id,nfapi_ul_config_ulsch_pdu *ulsch_pdu
return;
}
- //AssertFatal(ulsch->harq_processes[harq_pid]->nb_rb>0,"nb_rb = 0\n");
- if(ulsch->harq_processes[harq_pid]->nb_rb == 0) {
- LOG_E(PHY, "fill_ulsch UE_id %d nb_rb = 0\n", UE_id);
- }
-
ulsch->harq_processes[harq_pid]->frame = frame;
ulsch->harq_processes[harq_pid]->subframe = subframe;
ulsch->harq_processes[harq_pid]->handled = 0;
diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c
index 15eb5206a196530371d121b960144945d17afe68..3eb44d98fa69abb1935cd7d24e4ea7d0a95ada5f 100644
--- a/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c
+++ b/openair1/PHY/LTE_TRANSPORT/dlsch_coding.c
@@ -20,12 +20,12 @@
*/
/*! \file PHY/LTE_TRANSPORT/dlsch_coding.c
- * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03
- * \author R. Knopp
+ * \brief Top-level routines for implementing Turbo-coded (DLSCH) transport channels from 36-212, V8.6 2009-03, V14.1 2017 (includes FeMBMS support)
+ * \author R. Knopp, J. Morgade
* \date 2011
* \version 0.1
* \company Eurecom
- * \email: knopp@eurecom.fr
+ * \email: knopp@eurecom.fr, jaiver.morgade@ieee.org
* \note
* \warning
*/
@@ -386,6 +386,109 @@ int dlsch_encoding(PHY_VARS_eNB *eNB,
return(-1);
}
+ for (int r=0, r_offset=0; r<hadlsch->C; r++) {
+
+ union turboReqUnion id= {.s={dlsch->rnti,frame,subframe,r,0}};
+ notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboEncode_t), id.p, proc->respEncode, TPencode);
+ turboEncode_t * rdata=(turboEncode_t *) NotifiedFifoData(req);
+ rdata->input=hadlsch->c[r];
+ rdata->Kr_bytes= ( r<hadlsch->Cminus ? hadlsch->Kminus : hadlsch->Kplus) >>3;
+ rdata->filler=(r==0) ? hadlsch->F : 0;
+ rdata->r=r;
+ rdata->harq_pid=harq_pid;
+ rdata->dlsch=dlsch;
+ rdata->rm_stats=rm_stats;
+ rdata->te_stats=te_stats;
+ rdata->i_stats=i_stats;
+ rdata->round=hadlsch->round;
+ rdata->r_offset=r_offset;
+ rdata->G=G;
+
+ if ( proc->threadPool->activated ) {
+ pushTpool(proc->threadPool,req);
+ proc->nbEncode++;
+ } else {
+ TPencode(rdata);
+ delNotifiedFIFO_elt(req);
+ }
+
+ int Qm=hadlsch->Qm;
+ int C=hadlsch->C;
+ int Nl=hadlsch->Nl;
+ int Gp = G/Nl/Qm;
+ int GpmodC = Gp%C;
+ if (r < (C-(GpmodC)))
+ r_offset += Nl*Qm * (Gp/C);
+ else
+ r_offset += Nl*Qm * ((GpmodC==0?0:1) + (Gp/C));
+ }
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT);
+ return(0);
+}
+
+int dlsch_encoding_fembms_pmch(PHY_VARS_eNB *eNB,
+ L1_rxtx_proc_t *proc,
+ unsigned char *a,
+ uint8_t num_pdcch_symbols,
+ LTE_eNB_DLSCH_t *dlsch,
+ int frame,
+ uint8_t subframe,
+ time_stats_t *rm_stats,
+ time_stats_t *te_stats,
+ time_stats_t *i_stats) {
+ LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
+ unsigned char harq_pid = dlsch->harq_ids[frame%2][subframe];
+ if((harq_pid < 0) || (harq_pid >= dlsch->Mdlharq)) {
+ LOG_E(PHY,"dlsch_encoding illegal harq_pid %d %s:%d\n", harq_pid, __FILE__, __LINE__);
+ return(-1);
+ }
+
+ LTE_DL_eNB_HARQ_t *hadlsch=dlsch->harq_processes[harq_pid];
+ uint8_t beamforming_mode=0;
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN);
+
+ if(hadlsch->mimo_mode == TM7)
+ beamforming_mode = 7;
+ else if(hadlsch->mimo_mode == TM8)
+ beamforming_mode = 8;
+ else if(hadlsch->mimo_mode == TM9_10)
+ beamforming_mode = 9;
+
+ unsigned int G = get_G_khz_1dot25(frame_parms,hadlsch->nb_rb,
+ hadlsch->rb_alloc,
+ hadlsch->Qm, // mod order
+ hadlsch->Nl,
+ num_pdcch_symbols,
+ frame,subframe,beamforming_mode);
+
+ proc->nbEncode=0;
+
+ // if (hadlsch->Ndi == 1) { // this is a new packet
+ if (hadlsch->round == 0) { // this is a new packet
+ // Add 24-bit crc (polynomial A) to payload
+ unsigned int A=hadlsch->TBS; //6228;
+ unsigned int crc = crc24a(a,
+ A)>>8;
+ a[A>>3] = ((uint8_t *)&crc)[2];
+ a[1+(A>>3)] = ((uint8_t *)&crc)[1];
+ a[2+(A>>3)] = ((uint8_t *)&crc)[0];
+ // printf("CRC %x (A %d)\n",crc,A);
+ hadlsch->B = A+24;
+ // hadlsch->b = a;
+ memcpy(hadlsch->b,a,(A/8)+4);
+
+ if (lte_segmentation(hadlsch->b,
+ hadlsch->c,
+ hadlsch->B,
+ &hadlsch->C,
+ &hadlsch->Cplus,
+ &hadlsch->Cminus,
+ &hadlsch->Kplus,
+ &hadlsch->Kminus,
+ &hadlsch->F)<0)
+ return(-1);
+ }
+
for (int r=0, r_offset=0; r<hadlsch->C; r++) {
union turboReqUnion id= {.s={dlsch->rnti,frame,subframe,r,0}};
@@ -425,3 +528,5 @@ int dlsch_encoding(PHY_VARS_eNB *eNB,
return(0);
}
+
+
diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c
index 475c8bd521d8ea8b777d3bf04a40e799497858cd..8c07421b7e2bd017e0c0e270167f49a939680440 100644
--- a/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c
+++ b/openair1/PHY/LTE_TRANSPORT/dlsch_modulation.c
@@ -20,12 +20,12 @@
*/
/*! \file PHY/LTE_TRANSPORT/dlsch_modulation.c
- * \brief Top-level routines for generating the PDSCH physical channel from 36-211, V8.6 2009-03
- * \author R. Knopp, F. Kaltenberger
+ * \brief Top-level routines for generating the PDSCH physical channel from 36-211, V8.6 2009-03, V14.1 2017 (FeMBMS)
+ * \author R. Knopp, F. Kaltenberger, J. Morgade
* \date 2011
* \version 0.1
* \company Eurecom
- * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr
+ * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr, javier.morgade@ieee.irg
* \note
* \warning
*/
@@ -2910,3 +2910,260 @@ int mch_modulation(int32_t **txdataF,
return (re_allocated);
}
+
+int allocate_REs_in_RB_MCH_khz_1dot25(int32_t **txdataF,
+ uint32_t *jj,
+ uint16_t re_offset,
+ uint32_t symbol_offset,
+ uint8_t *x0,
+ uint8_t subframe,
+ uint8_t mod_order,
+ int16_t amp,
+ int16_t *qam_table_s,
+ uint32_t *re_allocated,
+ uint8_t skip_dc,
+ LTE_DL_FRAME_PARMS *frame_parms)
+{
+ uint32_t tti_offset;
+ uint8_t re,offset;
+ uint8_t qam64_table_offset_re = 0;
+ uint8_t qam64_table_offset_im = 0;
+ uint8_t qam16_table_offset_re = 0;
+ uint8_t qam16_table_offset_im = 0;
+ int16_t gain_lin_QPSK;//,gain_lin_16QAM1,gain_lin_16QAM2;
+ int16_t re_off=re_offset;
+ gain_lin_QPSK = (int16_t)((amp*ONE_OVER_SQRT2_Q15)>>15);
+ uint8_t first_re,last_re;
+ int inc;
+#ifdef DEBUG_DLSCH_MODULATION
+ LOG_I(PHY,"allocate_re_MCH khz_1dot25 (mod %d): symbol_offset %d re_offset %d (%d), jj %d -> %d,%d, gain_lin_QPSK %d,txdataF %p\n",mod_order,symbol_offset,re_offset,skip_dc,*jj, x0[*jj], x0[1+*jj],gain_lin_QPSK,&txdataF[0][symbol_offset]);
+#endif
+
+ /*last_re=12;
+ first_re=0;
+ inc=1;
+
+ if ((l==2)||(l==10)) {
+ inc=2;
+ first_re=1;
+ } else if (l==6) {
+ inc=2;
+ }*/
+ last_re=144; //12*12
+ if ((subframe&0x1)==0){ // n_sf mod 2 == 0: even
+ first_re=1;
+ offset=0;
+ }else{
+ first_re=0;
+ offset=3;
+ }
+ inc=1;
+
+ for (re=first_re; re<last_re; re+=inc) {
+ if( ((re-offset)%6) == 0 )
+ continue; //pilot
+ //if ((subframe&0x1)==0) // n_sf mod 2 == 0: even
+ //k = 6*m;
+ //else
+ //k = 6*m + 3;
+ //if ((skip_dc == 1) && (re==(6+first_re)))
+ if ((skip_dc == 1) && (re==(72+first_re))){
+ re_off=re_off - frame_parms->ofdm_symbol_size_khz_1dot25+1;
+ }
+
+ tti_offset = symbol_offset + re_off + re;
+
+ //LOG_I(PHY,"re %d (jj %d)\n",re,*jj);
+ *re_allocated = *re_allocated + 1;
+
+
+ switch (mod_order) {
+
+ case 2: //QPSK
+
+ LOG_D(PHY,"%d : %d,%d => ",tti_offset,((int16_t*)&txdataF[0][tti_offset])[0],((int16_t*)&txdataF[0][tti_offset])[1]);
+ ((int16_t*)&txdataF[0][tti_offset])[0] = (x0[*jj]==1) ? (-gain_lin_QPSK) : gain_lin_QPSK; //I //b_i
+
+ *jj = *jj + 1;
+
+ ((int16_t*)&txdataF[0][tti_offset])[1] = (x0[*jj]==1) ? (-gain_lin_QPSK) : gain_lin_QPSK; //Q //b_{i+1}
+
+ *jj = *jj + 1;
+
+ LOG_D(PHY,"subframe%d alloc[%d][%d][%d](%d,%d)\n",subframe,tti_offset,symbol_offset,tti_offset-symbol_offset,((int16_t*)&txdataF[0][tti_offset])[0],((int16_t*)&txdataF[0][tti_offset])[1]);
+ break;
+
+
+ case 4: //16QAM
+
+ qam16_table_offset_re = 0;
+ qam16_table_offset_im = 0;
+
+ if (x0[*jj] == 1)
+ qam16_table_offset_re+=2;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam16_table_offset_im+=2;
+
+ *jj=*jj+1;
+
+
+ if (x0[*jj] == 1)
+ qam16_table_offset_re+=1;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam16_table_offset_im+=1;
+
+ *jj=*jj+1;
+
+
+ ((int16_t *)&txdataF[0][tti_offset])[0]=qam_table_s[qam16_table_offset_re];//(int16_t)(((int32_t)amp*qam16_table[qam16_table_offset_re])>>15);
+ ((int16_t *)&txdataF[0][tti_offset])[1]=qam_table_s[qam16_table_offset_im];//(int16_t)(((int32_t)amp*qam16_table[qam16_table_offset_im])>>15);
+
+ break;
+
+ case 6: //64QAM
+
+ qam64_table_offset_re = 0;
+ qam64_table_offset_im = 0;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_re+=4;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_im+=4;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_re+=2;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_im+=2;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_re+=1;
+
+ *jj=*jj+1;
+
+ if (x0[*jj] == 1)
+ qam64_table_offset_im+=1;
+
+ *jj=*jj+1;
+
+ ((int16_t *)&txdataF[0][tti_offset])[0]=qam_table_s[qam64_table_offset_re];//(int16_t)(((int32_t)amp*qam64_table[qam64_table_offset_re])>>15);
+ ((int16_t *)&txdataF[0][tti_offset])[1]=qam_table_s[qam64_table_offset_im];//(int16_t)(((int32_t)amp*qam64_table[qam64_table_offset_im])>>15);
+
+ break;
+
+ }
+ }
+ return(0);
+}
+
+int mch_modulation_khz_1dot25(int32_t **txdataF,
+ int16_t amp,
+ uint32_t subframe_offset,
+ LTE_DL_FRAME_PARMS *frame_parms,
+ LTE_eNB_DLSCH_t *dlsch)
+{
+ uint8_t nsymb,nsymb_pmch;
+ uint32_t i,jj,re_allocated,symbol_offset;
+ uint16_t l,rb,re_offset;
+ uint8_t skip_dc=0;
+ uint8_t mod_order = dlsch->harq_processes[0]->Qm;
+ int16_t qam16_table_a[4],qam64_table_a[8];//,qam16_table_b[4],qam64_table_b[8];
+ int16_t *qam_table_s;
+
+ nsymb_pmch = 1;
+ nsymb = (frame_parms->Ncp == NORMAL) ? 14 : 12;
+
+ if (mod_order == 4)
+ for (i=0; i<4; i++) {
+ qam16_table_a[i] = (int16_t)(((int32_t)qam16_table[i]*amp)>>15);
+ }
+ else if (mod_order == 6)
+ for (i=0; i<8; i++) {
+ qam64_table_a[i] = (int16_t)(((int32_t)qam64_table[i]*amp)>>15);
+ }
+
+ jj=0;
+ re_allocated=0;
+
+
+
+
+
+ // LOG_I(PHY,"num_pdcch_symbols %d, nsymb %d\n",num_pdcch_symbols,nsymb);
+ for (l=0; l<nsymb_pmch; l++) {
+
+#ifdef DEBUG_DLSCH_MODULATION
+ LOG_I(PHY,"Generating khz_1dot25 MCH (mod %d) in subframe %d for symbol %d\n",mod_order, subframe_offset,l);
+#endif
+
+ re_offset = frame_parms->first_carrier_offset_khz_1dot25;
+ symbol_offset = (uint32_t)frame_parms->ofdm_symbol_size*(l+(subframe_offset*nsymb));
+
+ for (rb=0; rb<frame_parms->N_RB_DL; rb++) {
+
+
+ if ((frame_parms->N_RB_DL&1) == 1) { // ODD N_RB_DL
+
+ if (rb==(frame_parms->N_RB_DL>>1))
+ skip_dc = 1;
+ else
+ skip_dc = 0;
+
+ }
+
+ if (mod_order == 4)
+ qam_table_s = qam16_table_a;
+ else if (mod_order == 6)
+ qam_table_s = qam64_table_a;
+ else
+ qam_table_s = NULL;
+
+ //LOG_I(PHY,"Allocated rb %d, subframe_offset %d,amp %d\n",rb,subframe_offset,amp);
+ allocate_REs_in_RB_MCH_khz_1dot25(txdataF,
+ &jj,
+ re_offset,
+ symbol_offset,
+ dlsch->harq_processes[0]->eDL,
+ subframe_offset,
+ mod_order,
+ amp,
+ qam_table_s,
+ &re_allocated,
+ skip_dc,
+ frame_parms);
+
+ re_offset+=144; // go to next RB 12*12
+
+ // check if we crossed the symbol boundary and skip DC
+ if (re_offset >= frame_parms->ofdm_symbol_size_khz_1dot25) {
+ if (skip_dc == 0) //even number of RBs (doesn't straddle DC)
+ re_offset=1;
+ else
+ re_offset=73; // odd number of RBs
+ }
+ }
+ }
+
+#ifdef DEBUG_DLSCH_MODULATION
+ LOG_I(PHY,"generate_dlsch(MCH) : jj = %d,re_allocated = %d (G %d)\n",jj,re_allocated,get_G(frame_parms,dlsch->harq_processes[0]->nb_rb,dlsch->harq_processes[0]->rb_alloc,mod_order,1,2,0,subframe_offset,1/*transmission mode*/));
+ LOG_I(PHY,"generate_dlsch(MCH) : jj = %d,re_allocated = %d\n",jj,re_allocated);
+#endif
+
+ return (re_allocated);
+}
+
diff --git a/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h b/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h
index 9673ba15b503df82ee7ca7befb7f09d1bd2e6fd0..5a08b7a40238256aef630e97749ad8f7d283b05c 100644
--- a/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h
+++ b/openair1/PHY/LTE_TRANSPORT/dlsch_tbs_full.h
@@ -19,6 +19,9 @@
* contact@openairinterface.org
*/
+#ifndef __DLSCH_TBS_FULL__H__
+#define __DLSCH_TBS_FULL__H__
+
#define TBStable_rowCnt 27
/** \brief "Transport block size table"
@@ -54,3 +57,4 @@ unsigned int TBStable[TBStable_rowCnt][110] = {{16,32,56,88,120,152,176,208,224,
};
unsigned int TBStable1C[32] = {40, 56, 72, 120, 136, 144, 176, 208, 224, 256, 280, 296, 328, 336, 392, 488, 552, 600, 632, 696, 776, 840, 904, 1000, 1064, 1128, 1224, 1288, 1384, 1480, 1608, 1736};
+#endif
diff --git a/openair1/PHY/LTE_TRANSPORT/pbch.c b/openair1/PHY/LTE_TRANSPORT/pbch.c
index 37997c94b49e97b8acd53c83673e75dc0caac716..dfa990269ec864293d57ebf0eac259cd4d483b91 100644
--- a/openair1/PHY/LTE_TRANSPORT/pbch.c
+++ b/openair1/PHY/LTE_TRANSPORT/pbch.c
@@ -20,12 +20,12 @@
*/
/*! \file PHY/LTE_TRANSPORT/pbch.c
-* \brief Top-level routines for generating and decoding the PBCH/BCH physical/transport channel V8.6 2009-03
-* \author R. Knopp, F. Kaltenberger
+* \brief Top-level routines for generating and decoding the PBCH/BCH physical/transport channel V8.6 2009-03, V14.1 (FeMBMS)
+* \author R. Knopp, F. Kaltenberger, J. Morgade
* \date 2011
* \version 0.1
* \company Eurecom
-* \email: knopp@eurecom.fr,florian.kaltenberger.fr
+* \email: knopp@eurecom.fr,florian.kaltenberger.fr, javier.morgade@ieee.org
* \note
* \warning
*/
@@ -139,6 +139,285 @@ int allocate_pbch_REs_in_RB(LTE_DL_FRAME_PARMS *frame_parms,
return(0);
}
+void pbch_scrambling_fembms(LTE_DL_FRAME_PARMS *frame_parms,
+ uint8_t *pbch_e,
+ uint32_t length)
+{
+ int i;
+ uint8_t reset;
+ uint32_t x1, x2, s=0;
+
+ reset = 1;
+ // x1 is set in lte_gold_generic
+ x2 = frame_parms->Nid_cell + (1<<9); //this is c_init for FeMBMS in 36.211 Sec 6.6.1
+ // msg("pbch_scrambling: Nid_cell = %d\n",x2);
+
+ for (i=0; i<length; i++) {
+ if ((i&0x1f)==0) {
+ s = lte_gold_generic(&x1, &x2, reset);
+ // printf("lte_gold[%d]=%x\n",i,s);
+ reset = 0;
+ }
+
+ pbch_e[i] = (pbch_e[i]&1) ^ ((s>>(i&0x1f))&1);
+
+ }
+}
+
+int generate_pbch_fembms(LTE_eNB_PBCH *eNB_pbch,
+ int32_t **txdataF,
+ int amp,
+ LTE_DL_FRAME_PARMS *frame_parms,
+ uint8_t *pbch_pdu,
+ uint8_t frame_mod4)
+{
+
+ int i, l;
+
+ uint32_t pbch_D,pbch_E;//,pbch_coded_bytes;
+ uint8_t pbch_a[PBCH_A>>3];
+ uint8_t RCC;
+
+ uint32_t nsymb = (frame_parms->Ncp==NORMAL) ? 14:12;
+ uint32_t pilots;
+#ifdef INTERFERENCE_MITIGATION
+ uint32_t pilots_2;
+#endif
+ uint32_t second_pilot = (frame_parms->Ncp==NORMAL) ? 4 : 3;
+ uint32_t jj=0;
+ uint32_t re_allocated=0;
+ uint32_t rb, re_offset, symbol_offset;
+ uint16_t amask=0;
+
+ pbch_D = 16+PBCH_A;
+
+ pbch_E = (frame_parms->Ncp==NORMAL) ? 1920 : 1728; //RE/RB * #RB * bits/RB (QPSK)
+ // pbch_E_bytes = pbch_coded_bits>>3;
+
+ LOG_D(PHY,"%s(eNB_pbch:%p txdataF:%p amp:%d frame_parms:%p pbch_pdu:%p frame_mod4:%d)\n", __FUNCTION__, eNB_pbch, txdataF, amp, frame_parms, pbch_pdu, frame_mod4==0);
+
+ if (frame_mod4==0) {
+ bzero(pbch_a,PBCH_A>>3);
+ bzero(eNB_pbch->pbch_e,pbch_E);
+ memset(eNB_pbch->pbch_d,LTE_NULL,96);
+ // Encode data
+
+ // CRC attachment
+ // crc = (uint16_t) (crc16(pbch_pdu, pbch_crc_bits-16) >> 16);
+
+ /*
+ // scramble crc with PBCH CRC mask (Table 5.3.1.1-1 of 3GPP 36.212-860)
+ switch (frame_parms->nb_antenna_ports_eNB) {
+ case 1:
+ crc = crc ^ (uint16_t) 0;
+ break;
+ case 2:
+ crc = crc ^ (uint16_t) 0xFFFF;
+ break;
+ case 4:
+ crc = crc ^ (uint16_t) 0xAAAA;
+ break;
+ default:
+ msg("[PBCH] Unknown number of TX antennas!\n");
+ break;
+ }
+ */
+
+ // Fix byte endian of PBCH (bit 23 goes in first)
+ for (i=0; i<(PBCH_A>>3); i++)
+ pbch_a[(PBCH_A>>3)-i-1] = pbch_pdu[i];
+
+ // pbch_data[i] = ((char*) &crc)[0];
+ // pbch_data[i+1] = ((char*) &crc)[1];
+ //#ifdef DEBUG_PBCH
+
+ for (i=0; i<(PBCH_A>>3); i++)
+ LOG_D(PHY,"[PBCH] pbch_data[%d] = %x\n",i,pbch_a[i]);
+
+ //#endif
+
+ if (frame_parms->nb_antenna_ports_eNB == 1)
+ amask = 0x0000;
+ else {
+ switch (frame_parms->nb_antenna_ports_eNB) {
+ case 1:
+ amask = 0x0000;
+ break;
+
+ case 2:
+ amask = 0xffff;
+ break;
+
+ case 4:
+ amask = 0x5555;
+ }
+ }
+
+ ccodelte_encode(PBCH_A,2,pbch_a,eNB_pbch->pbch_d+96,amask);
+
+
+#ifdef DEBUG_PBCH_ENCODING
+
+ for (i=0; i<16+PBCH_A; i++)
+ LOG_D(PHY,"%d : (%d,%d,%d)\n",i,*(eNB_pbch->pbch_d+96+(3*i)),*(eNB_pbch->pbch_d+97+(3*i)),*(eNB_pbch->pbch_d+98+(3*i)));
+
+#endif //DEBUG_PBCH_ENCODING
+
+ // Bit collection
+ /*
+ j2=0;
+ for (j=0;j<pbch_crc_bits*3+12;j++) {
+ if ((pbch_coded_data[j]&0x80) > 0) { // bit is to be transmitted
+ pbch_coded_data2[j2++] = pbch_coded_data[j]&1;
+ //Bit is repeated
+ if ((pbch_coded_data[j]&0x40)>0)
+ pbch_coded_data2[j2++] = pbch_coded_data[j]&1;
+ }
+ }
+
+ #ifdef DEBUG_PBCH
+ msg("[PBCH] rate matched bits=%d, pbch_coded_bits=%d, pbch_crc_bits=%d\n",j2,pbch_coded_bits,pbch_crc_bits);
+ #endif
+
+ #ifdef DEBUG_PBCH
+ LOG_M"pbch_encoded_output2.m","pbch_encoded_out2",
+ pbch_coded_data2,
+ pbch_coded_bits,
+ 1,
+ 4);
+ #endif //DEBUG_PBCH
+ */
+#ifdef DEBUG_PBCH_ENCODING
+ LOG_D(PHY,"Doing PBCH interleaving for %d coded bits, e %p\n",pbch_D,eNB_pbch->pbch_e);
+#endif
+ RCC = sub_block_interleaving_cc(pbch_D,eNB_pbch->pbch_d+96,eNB_pbch->pbch_w);
+
+ lte_rate_matching_cc(RCC,pbch_E,eNB_pbch->pbch_w,eNB_pbch->pbch_e);
+
+#ifdef DEBUG_PBCH_ENCODING
+ LOG_D(PHY,"PBCH_e:\n");
+
+ for (i=0; i<pbch_E; i++)
+ LOG_D(PHY,"%d %d\n",i,*(eNB_pbch->pbch_e+i));
+
+ LOG_D(PHY,"\n");
+#endif
+
+
+
+#ifdef DEBUG_PBCH
+ if (frame_mod4==0) {
+ LOG_M("pbch_e.m","pbch_e",
+ eNB_pbch->pbch_e,
+ pbch_E,
+ 1,
+ 4);
+
+ for (i=0; i<16; i++)
+ printf("e[%d] %d\n",i,eNB_pbch->pbch_e[i]);
+ }
+#endif //DEBUG_PBCH
+ // scrambling
+
+ pbch_scrambling_fembms(frame_parms,
+ eNB_pbch->pbch_e,
+ pbch_E);
+#ifdef DEBUG_PBCH
+ if (frame_mod4==0) {
+ LOG_M("pbch_e_s.m","pbch_e_s",
+ eNB_pbch->pbch_e,
+ pbch_E,
+ 1,
+ 4);
+
+ for (i=0; i<16; i++)
+ printf("e_s[%d] %d\n",i,eNB_pbch->pbch_e[i]);
+ }
+#endif //DEBUG_PBCH
+ } // frame_mod4==0
+
+ // modulation and mapping (slot 1, symbols 0..3)
+ for (l=(nsymb>>1); l<(nsymb>>1)+4; l++) {
+
+ pilots=0;
+#ifdef INTERFERENCE_MITIGATION
+ pilots_2 = 0;
+#endif
+
+ if ((l==0) || (l==(nsymb>>1))) {
+ pilots=1;
+#ifdef INTERFERENCE_MITIGATION
+ pilots_2=1;
+#endif
+ }
+
+ if ((l==1) || (l==(nsymb>>1)+1)) {
+ pilots=1;
+ }
+
+ if ((l==second_pilot)||(l==(second_pilot+(nsymb>>1)))) {
+ pilots=1;
+ }
+
+#ifdef DEBUG_PBCH
+ LOG_D(PHY,"[PBCH] l=%d, pilots=%d\n",l,pilots);
+#endif
+
+
+ re_offset = frame_parms->ofdm_symbol_size-3*12;
+ symbol_offset = frame_parms->ofdm_symbol_size*l;
+
+ for (rb=0; rb<6; rb++) {
+
+#ifdef DEBUG_PBCH
+ LOG_D(PHY,"RB %d, jj %d, re_offset %d, symbol_offset %d, pilots %d, nushift %d\n",rb,jj,re_offset, symbol_offset, pilots,frame_parms->nushift);
+#endif
+ allocate_pbch_REs_in_RB(frame_parms,
+ txdataF,
+ &jj,
+ re_offset,
+ symbol_offset,
+ &eNB_pbch->pbch_e[frame_mod4*(pbch_E>>2)],
+ pilots,
+#ifdef INTERFERENCE_MITIGATION
+ (pilots_2==1)?(amp/3):amp,
+#else
+ amp,
+#endif
+ &re_allocated);
+
+ re_offset+=12; // go to next RB
+
+ // check if we crossed the symbol boundary and skip DC
+
+ if (re_offset >= frame_parms->ofdm_symbol_size)
+ re_offset=1;
+ }
+
+ // }
+ }
+
+#ifdef DEBUG_PBCH
+ printf("[PBCH] txdataF=\n");
+
+ for (i=0; i<frame_parms->ofdm_symbol_size; i++) {
+ printf("%d=>(%d,%d)",i,((short*)&txdataF[0][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[0],
+ ((short*)&txdataF[0][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[1]);
+
+ if (frame_parms->nb_antenna_ports_eNB!=1) {
+ printf("(%d,%d)\n",((short*)&txdataF[1][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[0],
+ ((short*)&txdataF[1][frame_parms->ofdm_symbol_size*(nsymb>>1)+i])[1]);
+ } else {
+ printf("\n");
+ }
+ }
+
+#endif
+
+
+ return(0);
+}
+
void pbch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
uint8_t *pbch_e,
uint32_t length)
diff --git a/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c b/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c
index 475102b57c908cb66ee401139fe29e04998683c3..47ef6428cbdddef09f274b2f93e33b20ecec1096 100644
--- a/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c
+++ b/openair1/PHY/LTE_TRANSPORT/pilots_mbsfn.c
@@ -20,12 +20,12 @@
*/
/*! \file PHY/LTE_TRANSPORT/pilots_mbsfn.c
-* \brief Top-level routines for generating DL mbsfn reference signals
-* \authors S. Paranche, R. Knopp
+* \brief Top-level routines for generating DL mbsfn reference signals / DL mbsfn reference signals for FeMBMS
+* \authors S. Paranche, R. Knopp, J. Morgade
* \date 2012
* \version 0.1
* \company Eurecom
-* \email: knopp@eurecom.fr
+* \email: knopp@eurecom.fr, javier.morgade@ieee.org
* \note
* \warning
*/
@@ -85,3 +85,31 @@ int generate_mbsfn_pilot(PHY_VARS_eNB *eNB,
}
+int generate_mbsfn_pilot_khz_1dot25(PHY_VARS_eNB *eNB,
+ L1_rxtx_proc_t *proc,
+ int32_t **txdataF,
+ int16_t amp)
+
+{
+
+ LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
+ uint32_t subframe_offset,Nsymb;
+ int subframe = proc->subframe_tx;
+
+
+ if (subframe<0 || subframe>= 10) {
+ LOG_E(PHY,"generate_mbsfn_pilots_subframe: subframe not in range (%d)\n",subframe);
+ return(-1);
+ }
+
+ Nsymb = (frame_parms->Ncp==NORMAL) ? 7 : 6;
+
+ subframe_offset = subframe*frame_parms->ofdm_symbol_size*Nsymb<<1;
+
+ lte_dl_mbsfn_khz_1dot25(eNB,
+ &txdataF[0][subframe_offset+0],
+ amp,subframe);
+
+ return(0);
+}
+
diff --git a/openair1/PHY/LTE_TRANSPORT/pmch.c b/openair1/PHY/LTE_TRANSPORT/pmch.c
index 90e2836b1e729dc09d18bdf87a09952a73714ed3..7b508239a9fa6090fadad3da69ef733a2cbcfece 100644
--- a/openair1/PHY/LTE_TRANSPORT/pmch.c
+++ b/openair1/PHY/LTE_TRANSPORT/pmch.c
@@ -128,3 +128,53 @@ void generate_mch(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc,uint8_t *a)
}
+void generate_mch_khz_1dot25(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc,uint8_t *a)
+{
+
+ int G;
+ int subframe = proc->subframe_tx;
+ int frame = proc->frame_tx;
+ //int bits;
+
+ G = get_G_khz_1dot25(&eNB->frame_parms,
+ eNB->frame_parms.N_RB_DL,
+ eNB->dlsch_MCH->harq_processes[0]->rb_alloc,
+ get_Qm(eNB->dlsch_MCH->harq_processes[0]->mcs),1,
+ 2,proc->frame_tx,subframe,0);
+
+ //FeMBMS
+ eNB->dlsch_MCH->harq_processes[0]->Qm = get_Qm(eNB->dlsch_MCH->harq_processes[0]->mcs);
+
+
+ generate_mbsfn_pilot_khz_1dot25(eNB,proc,
+ eNB->common_vars.txdataF,
+ AMP);
+
+
+ AssertFatal(dlsch_encoding_fembms_pmch(eNB,
+ proc,
+ // a,
+ eNB->dlsch_MCH->harq_processes[0]->pdu,
+ 1,
+ eNB->dlsch_MCH,
+ proc->frame_tx,
+ subframe,
+ &eNB->dlsch_rate_matching_stats,
+ &eNB->dlsch_turbo_encoding_stats,
+ &eNB->dlsch_interleaving_stats)==0,
+ "problem in dlsch_encoding");
+
+
+ /*for(bits=0;bits<G;bits++)
+ printf("%d",eNB->dlsch_MCH->harq_processes[0]->e[bits]);
+ printf("\n");*/
+
+ dlsch_scrambling(&eNB->frame_parms,1,eNB->dlsch_MCH,0,G,0,frame,subframe<<1);
+
+ mch_modulation_khz_1dot25(eNB->common_vars.txdataF,
+ AMP,
+ subframe,
+ &eNB->frame_parms,
+ eNB->dlsch_MCH);
+}
+
diff --git a/openair1/PHY/LTE_TRANSPORT/pmch_common.c b/openair1/PHY/LTE_TRANSPORT/pmch_common.c
index 03bf5a378b2c5ed1872dab3fa409624c3b406526..8d65dd2744d336769dc7e284b370f48d6d76d587 100644
--- a/openair1/PHY/LTE_TRANSPORT/pmch_common.c
+++ b/openair1/PHY/LTE_TRANSPORT/pmch_common.c
@@ -37,23 +37,84 @@
int is_fembms_cas_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms) {
- uint32_t period;
-
- if(frame_parms->NonMBSFN_config_flag ) {
- period = 4<<frame_parms->NonMBSFN_config.radioframeAllocationPeriod;
-
- if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) {
+ //uint32_t period;
+
+ //if(frame_parms->NonMBSFN_config_flag ) {
+ // period = 4<<frame_parms->NonMBSFN_config.radioframeAllocationPeriod;
+
+ // if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) {
+ // switch (subframe) {
+ // case 0:
+ // return(1); //This should be CAS
+ // break;
+ // }
+ // }
+ //}
+ if(frame_parms->NonMBSFN_config_flag || frame_parms->FeMBMS_active){
+ if ((frame&3)==0) {
switch (subframe) {
case 0:
- return(1); //This should be CAS
- break;
+ return(1); //This should be CAS
+ break;
}
- }
+ }
+
}
return (0);
}
+int is_fembms_nonMBSFN_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms){
+ uint32_t period;
+ if(frame_parms->NonMBSFN_config_flag ) {
+ period = 4<<frame_parms->NonMBSFN_config.radioframeAllocationPeriod;
+ if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) {
+ switch (subframe) {
+ case 0:
+ return(1); //This should be CAS
+ break;
+ case 1:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x100) > 0)
+ return(1);
+ break;
+ case 2:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x80) > 0)
+ return(1);
+ break;
+ case 3:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x40) > 0)
+ return(1);
+ break;
+ case 4:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x20) > 0)
+ return(1);
+ break;
+ case 5:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x10) > 0)
+ return(1);
+ break;
+ case 6:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x8) > 0)
+ return(1);
+ break;
+ case 7:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x4) > 0)
+ return(1);
+ break;
+ case 8:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x2) > 0)
+ return(1);
+ break;
+ case 9:
+ if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x1) > 0)
+ return(1);
+ break;
+ }
+ }
+ }
+ return (0);
+}
+
int is_fembms_pmch_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms) {
uint32_t period;
@@ -62,63 +123,67 @@ int is_fembms_pmch_subframe(uint32_t frame, int subframe, LTE_DL_FRAME_PARMS *fr
if ((frame % period) == frame_parms->NonMBSFN_config.radioframeAllocationOffset) {
switch (subframe) {
+ case 0:
+ return(0);
+ break;
case 1:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x100) > 0)
- return(1);
+ return(0);
break;
case 2:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x80) > 0)
- return(1);
+ return(0);
break;
case 3:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x40) > 0)
- return(1);
+ return(0);
break;
case 4:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x20) > 0)
- return(1);
+ return(0);
break;
case 5:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x10) > 0)
- return(1);
+ return(0);
break;
case 6:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x8) > 0)
- return(1);
+ return(0);
break;
case 7:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x4) > 0)
- return(1);
+ return(0);
break;
case 8:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x2) > 0)
- return(1);
+ return(0);
break;
case 9:
if ((frame_parms->NonMBSFN_config.non_mbsfn_SubframeConfig & 0x1) > 0)
- return(1);
+ return(0);
break;
}
- } else { //Then regular MBSFN FeMBMS subframe
+ } else if((frame_parms->FeMBMS_active == 1 || frame_parms->NonMBSFN_config_flag == 1 ) && !is_fembms_cas_subframe(frame,subframe,frame_parms) ) { //Then regular MBSFN FeMBMS subframe
return(1);
}
+ return(1);
}
return(0);
diff --git a/openair1/PHY/LTE_TRANSPORT/prach_extern.h b/openair1/PHY/LTE_TRANSPORT/prach_extern.h
index 2f8a83e24f2a052e3359cd499e8dddf395a5671d..47fbd93ad7c964d2a15dd5215ca315e80a69f90b 100644
--- a/openair1/PHY/LTE_TRANSPORT/prach_extern.h
+++ b/openair1/PHY/LTE_TRANSPORT/prach_extern.h
@@ -29,6 +29,10 @@
* \note
* \warning
*/
+
+#ifndef __PHY_LTE_TRANSPORT_PRACH_EXTERN__H__
+#define __PHY_LTE_TRANSPORT_PRACH_EXTERN__H__
+
#include "PHY/sse_intrin.h"
#include "PHY/defs_eNB.h"
#include "PHY/phy_extern.h"
@@ -91,3 +95,4 @@ void compute_prach_seq(uint16_t rootSequenceIndex,
lte_frame_type_t frame_type,
uint32_t X_u[64][839]);
+#endif
diff --git a/openair1/PHY/LTE_TRANSPORT/pucch_extern.h b/openair1/PHY/LTE_TRANSPORT/pucch_extern.h
index 899b90430670af54af65a918d859689646e1129c..b15137488803b1d42c8ab9f3faf34efb9fc49c5a 100644
--- a/openair1/PHY/LTE_TRANSPORT/pucch_extern.h
+++ b/openair1/PHY/LTE_TRANSPORT/pucch_extern.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __PHY_LTE_TRANSPORT_PUCCH_EXTERN__H__
+#define __PHY_LTE_TRANSPORT_PUCCH_EXTERN__H__
+
#include <stdint.h>
/* PUCCH format3 >> */
@@ -76,3 +79,5 @@ extern uint8_t Np4_TBL[4];
// alpha_TBL
extern int16_t alphaTBL_re[12];
extern int16_t alphaTBL_im[12];
+
+#endif
diff --git a/openair1/PHY/LTE_TRANSPORT/transport_common.h b/openair1/PHY/LTE_TRANSPORT/transport_common.h
index 321789d54b380a95c221c38e497e85de12925092..ab2921c2b9405a65ae5ef8bce9d5b21840b73b39 100644
--- a/openair1/PHY/LTE_TRANSPORT/transport_common.h
+++ b/openair1/PHY/LTE_TRANSPORT/transport_common.h
@@ -67,6 +67,7 @@
#if !defined(SI_RNTI)
#define SI_RNTI (rnti_t)0xffff
+ #define SI_RNTI_MBMS (rnti_t)0xfff9
#endif
#if !defined(M_RNTI)
#define M_RNTI (rnti_t)0xfffd
diff --git a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h
index e4f5d9a17f10b3d3090a53df586229751a568267..1944f06fab7a410dc21ee3a9130dba4f4c1bf311 100644
--- a/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h
+++ b/openair1/PHY/LTE_TRANSPORT/transport_common_proto.h
@@ -270,6 +270,9 @@ int is_pmch_subframe(frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parm
*/
int is_fembms_cas_subframe(frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms);
+int is_fembms_nonMBSFN_subframe (frame_t frame, int subframe, LTE_DL_FRAME_PARMS *frame_parms);
+
+
/*!
\brief Return the status of MBSFN in this frame/subframe
@param frame Frame index
diff --git a/openair1/PHY/LTE_TRANSPORT/transport_extern.h b/openair1/PHY/LTE_TRANSPORT/transport_extern.h
index 357d31ca1076099d14ac7cc7795192ba63420ce8..8b33449ccaf06762fc5b786e4969c12c7dfc67c9 100644
--- a/openair1/PHY/LTE_TRANSPORT/transport_extern.h
+++ b/openair1/PHY/LTE_TRANSPORT/transport_extern.h
@@ -22,7 +22,7 @@
extern unsigned int dlsch_tbs25[27][25],TBStable[27][110],TBStable1C[32];
extern unsigned short lte_cqi_eff1024[16];
extern char lte_cqi_snr_dB[15];
-extern short conjugate[8],conjugate2[8];
+extern const short conjugate[8],conjugate2[8];
extern short minus_one[8];
extern short minus_one[8];
extern short *ul_ref_sigs[30][2][34];
diff --git a/openair1/PHY/LTE_TRANSPORT/transport_proto.h b/openair1/PHY/LTE_TRANSPORT/transport_proto.h
index 3988923bb98cdd77b93996ebb7fac009aee0ac12..4ce113f78ee5d590de3e15048de9f86c68534ac4 100644
--- a/openair1/PHY/LTE_TRANSPORT/transport_proto.h
+++ b/openair1/PHY/LTE_TRANSPORT/transport_proto.h
@@ -123,6 +123,42 @@ int32_t dlsch_encoding(PHY_VARS_eNB *eNB,
time_stats_t *te_stats,
time_stats_t *i_stats);
+/** \fn dlsch_encoding(PHY_VARS_eNB *eNB,
+ uint8_t *input_buffer,
+ LTE_DL_FRAME_PARMS *frame_parms,
+ uint8_t num_pdcch_symbols,
+ LTE_eNB_DLSCH_t *dlsch,
+ int frame,
+ uint8_t subframe)
+ \brief This function performs a subset of the bit-coding functions for LTE as described in 36-212, Release 8.Support is limited to turbo-coded channels (DLSCH/ULSCH). The implemented functions are:
+ - CRC computation and addition
+ - Code block segmentation and sub-block CRC addition
+ - Channel coding (Turbo coding)
+ - Rate matching (sub-block interleaving, bit collection, selection and transmission
+ - Code block concatenation
+ @param eNB Pointer to eNB PHY context
+ @param input_buffer Pointer to input buffer for sub-frame
+ @param frame_parms Pointer to frame descriptor structure
+ @param num_pdcch_symbols Number of PDCCH symbols in this subframe
+ @param dlsch Pointer to dlsch to be encoded
+ @param frame Frame number
+ @param subframe Subframe number
+ @param rm_stats Time statistics for rate-matching
+ @param te_stats Time statistics for turbo-encoding
+ @param i_stats Time statistics for interleaving
+ @returns status
+*/
+int32_t dlsch_encoding_fembms_pmch(PHY_VARS_eNB *eNB,
+ L1_rxtx_proc_t *proc,
+ uint8_t *a,
+ uint8_t num_pdcch_symbols,
+ LTE_eNB_DLSCH_t *dlsch,
+ int frame,
+ uint8_t subframe,
+ time_stats_t *rm_stats,
+ time_stats_t *te_stats,
+ time_stats_t *i_stats);
+
@@ -269,6 +305,30 @@ int mch_modulation(int32_t **txdataF,
LTE_DL_FRAME_PARMS *frame_parms,
LTE_eNB_DLSCH_t *dlsch);
+/*
+ \brief This function is the top-level routine for generation of the sub-frame signal (frequency-domain) for MCH.
+ @param txdataF Table of pointers for frequency-domain TX signals
+ @param amp Amplitude of signal
+ @param subframe_offset Offset of this subframe in units of subframes (usually 0)
+ @param frame_parms Pointer to frame descriptor
+ @param dlsch Pointer to DLSCH descriptor for this allocation
+*/
+int mch_modulation_khz_1dot25(int32_t **txdataF,
+ int16_t amp,
+ uint32_t subframe_offset,
+ LTE_DL_FRAME_PARMS *frame_parms,
+ LTE_eNB_DLSCH_t *dlsch);
+
+
+/** \brief Top-level generation function for eNB TX of MBSFN
+ @param phy_vars_eNB Pointer to eNB variables
+ @param a Pointer to transport block
+ @param abstraction_flag
+
+*/
+void generate_mch_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB,L1_rxtx_proc_t *proc,uint8_t *a);
+
+
/** \brief Top-level generation function for eNB TX of MBSFN
@param phy_vars_eNB Pointer to eNB variables
@param a Pointer to transport block
@@ -318,6 +378,12 @@ int32_t generate_pilots_slot(PHY_VARS_eNB *phy_vars_eNB,
uint16_t slot,
int first_pilot_only);
+int32_t generate_mbsfn_pilot_khz_1dot25(PHY_VARS_eNB *phy_vars_eNB,
+ L1_rxtx_proc_t *proc,
+ int32_t **txdataF,
+ int16_t amp);
+
+
int32_t generate_mbsfn_pilot(PHY_VARS_eNB *phy_vars_eNB,
L1_rxtx_proc_t *proc,
int32_t **txdataF,
@@ -350,6 +416,13 @@ int32_t generate_pbch(LTE_eNB_PBCH *eNB_pbch,
uint8_t *pbch_pdu,
uint8_t frame_mod4);
+int32_t generate_pbch_fembms(LTE_eNB_PBCH *eNB_pbch,
+ int32_t **txdataF,
+ int32_t amp,
+ LTE_DL_FRAME_PARMS *frame_parms,
+ uint8_t *pbch_pdu,
+ uint8_t frame_mod16);
+
diff --git a/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c b/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c
index 90492b999991905e8829d35447dda2716bb61913..92fe77720115b933095a05521fe8677021e6ef19 100644
--- a/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c
+++ b/openair1/PHY/LTE_TRANSPORT/ulsch_decoding.c
@@ -495,7 +495,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
}
AssertFatal(sumKr>0,
- "[eNB] ulsch_decoding.c: FATAL sumKr is 0! (Nid_cell %d, rnti %x, x2 %x): harq_pid %d round %d, RV %d, O_RI %d, O_ACK %d, G %d, subframe %d\n",
+ "[eNB] ulsch_decoding.c: FATAL sumKr is 0! (Nid_cell %d, rnti %x, x2 %x): harq_pid %d round %d, RV %d, O_RI %d, O_ACK %d, G %u, subframe %d\n",
frame_parms->Nid_cell,ulsch->rnti,x2,
harq_pid,
ulsch_harq->round,
diff --git a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c
index f357e385f0d8e01af770485425788f81b074ae81..1b23fc99bf3de76c424a4142ba1514a5243c2d0e 100644
--- a/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c
+++ b/openair1/PHY/LTE_TRANSPORT/ulsch_demodulation.c
@@ -1047,7 +1047,11 @@ void rx_ulsch(PHY_VARS_eNB *eNB,
l%(frame_parms->symbols_per_tti/2),
l/(frame_parms->symbols_per_tti/2),
frame_parms);
- lte_ul_channel_estimation(eNB,proc,
+ lte_ul_channel_estimation(&eNB->frame_parms,proc,
+ eNB->ulsch[UE_id],
+ eNB->pusch_vars[UE_id]->drs_ch_estimates,
+ eNB->pusch_vars[UE_id]->drs_ch_estimates_time,
+ eNB->pusch_vars[UE_id]->rxdataF_ext,
UE_id,
l%(frame_parms->symbols_per_tti/2),
l/(frame_parms->symbols_per_tti/2));
diff --git a/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c b/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c
index 2fd84f563cce242bff6367c7849ade59866adbdd..556a9f2d237f5e4cbf84dae7541d69b570e0d2a6 100644
--- a/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c
+++ b/openair1/PHY/LTE_UE_TRANSPORT/dlsch_demodulation.c
@@ -821,15 +821,14 @@ int rx_pdsch(PHY_VARS_UE *ue,
pllr_symbol_cw0 += llr_offset_symbol;
pllr_symbol_cw1 += llr_offset_symbol;
- /*
- LOG_I(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %p @LLR Buff(symb) %p\n",
+ LOG_D(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %p @LLR Buff(symb) %p energy: %d\n",
frame, subframe,symbol,
nb_rb,dlsch0_harq->Qm,
pdsch_vars[eNB_id]->llr_length[symbol],
pdsch_vars[eNB_id]->llr_offset[symbol],
(int16_t*)pdsch_vars[eNB_id]->llr[0],
- pllr_symbol_cw0);
- */
+ pllr_symbol_cw0,
+ signal_energy(pdsch_vars[eNB_id]->rxdataF_comp0[0], 7*2*frame_parms->N_RB_DL*12));
switch (dlsch0_harq->Qm) {
case 2 :
if ((rx_type==rx_standard) || (codeword_TB1 == -1)) {
diff --git a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c
index e4083863f0da352bfd5c74998414cbd768526601..ab7c2b90910d4df9eff3fe17d0139843bd73038c 100644
--- a/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c
+++ b/openair1/PHY/LTE_UE_TRANSPORT/prach_ue.c
@@ -55,7 +55,7 @@ int32_t generate_prach( PHY_VARS_UE *ue, uint8_t eNB_id, uint8_t subframe, uint1
uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex;
uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index;
int16_t *prachF = ue->prach_vars[eNB_id]->prachF;
- static int16_t prach_tmp[45600*2] __attribute__((aligned(32)));
+ static int16_t prach_tmp[45600*4] __attribute__((aligned(32)));
int16_t *prach = prach_tmp;
int16_t *prach2;
int16_t amp = ue->prach_vars[eNB_id]->amp;
diff --git a/openair1/PHY/LTE_UE_TRANSPORT/sldch.c b/openair1/PHY/LTE_UE_TRANSPORT/sldch.c
index 9c9d36c9746f5a8143544a21de67b5512210dd50..8769d5f81bff04e5b87d40b19e4a2ca0282b32d5 100644
--- a/openair1/PHY/LTE_UE_TRANSPORT/sldch.c
+++ b/openair1/PHY/LTE_UE_TRANSPORT/sldch.c
@@ -29,8 +29,6 @@
* \note
* \warning
*/
-#ifndef __LTE_TRANSPORT_SLSS__C__
-#define __LTE_TRANSPORT_SLSS__C__
#include "PHY/defs_UE.h"
extern int multicast_link_write_sock(int groupP, char *dataP, uint32_t sizeP);
@@ -63,4 +61,3 @@ void generate_sldch(PHY_VARS_UE *ue,SLDCH_t *sldch,int frame_tx,int subframe_tx)
}
-#endif
diff --git a/openair1/PHY/LTE_UE_TRANSPORT/slsch.c b/openair1/PHY/LTE_UE_TRANSPORT/slsch.c
index e51e33626df38a277c41922b6150bfd392bff901..e4e94a232d7be7c27ebe098a8bc8a87c06a753f1 100644
--- a/openair1/PHY/LTE_UE_TRANSPORT/slsch.c
+++ b/openair1/PHY/LTE_UE_TRANSPORT/slsch.c
@@ -29,8 +29,6 @@
* \note
* \warning
*/
-#ifndef __LTE_TRANSPORT_SLSS__C__
-#define __LTE_TRANSPORT_SLSS__C__
#include "PHY/defs_UE.h"
extern int
@@ -66,5 +64,3 @@ void generate_slsch(PHY_VARS_UE *ue,SLSCH_t *slsch,int frame_tx,int subframe_tx)
}
}
-
-#endif
diff --git a/openair1/PHY/LTE_UE_TRANSPORT/slss.c b/openair1/PHY/LTE_UE_TRANSPORT/slss.c
index 18bc5a28dec8826a63ebef68eec43654561bf6da..3cd1c1acb09f00f59fee1b185f7e400d1a3a5978 100644
--- a/openair1/PHY/LTE_UE_TRANSPORT/slss.c
+++ b/openair1/PHY/LTE_UE_TRANSPORT/slss.c
@@ -29,8 +29,6 @@
* \note
* \warning
*/
-#ifndef __LTE_TRANSPORT_SLSS__C__
-#define __LTE_TRANSPORT_SLSS__C__
#include "PHY/defs_UE.h"
@@ -39,5 +37,3 @@ void generate_slss(PHY_VARS_UE *ue,SLSS_t *slss,int frame_tx,int subframe_tx) {
AssertFatal(1==0,"Should get here yet for UE %d\n",ue->Mod_id);
}
-
-#endif
diff --git a/openair1/PHY/MODULATION/beamforming.c b/openair1/PHY/MODULATION/beamforming.c
index 79e220ac37d2ecb8a7ef8873b4355e87c54da666..b1f419b1724b8462489ba9d25789685265ddf52b 100644
--- a/openair1/PHY/MODULATION/beamforming.c
+++ b/openair1/PHY/MODULATION/beamforming.c
@@ -155,7 +155,7 @@ int nr_beam_precoding(int32_t **txdataF,
memset(&txdataF_BF[aa][symbol*frame_parms->ofdm_symbol_size],0,sizeof(int32_t)*(frame_parms->ofdm_symbol_size));
for (p=0; p<nb_antenna_ports; p++) {
- if ((frame_parms->L_ssb >> p) & 0x01) {
+ if ((frame_parms->L_ssb >> (63-p)) & 0x01) {
multadd_cpx_vector((int16_t*)&txdataF[p][symbol*frame_parms->ofdm_symbol_size],
(int16_t*)beam_weights[p][aa],
(int16_t*)&txdataF_BF[aa][symbol*frame_parms->ofdm_symbol_size],
diff --git a/openair1/PHY/MODULATION/nr_modulation.c b/openair1/PHY/MODULATION/nr_modulation.c
index b27b692e66122244cba89b409b0bc9343d235a88..764b02065f70de8421e65cb1609a114a68ba59d5 100644
--- a/openair1/PHY/MODULATION/nr_modulation.c
+++ b/openair1/PHY/MODULATION/nr_modulation.c
@@ -20,34 +20,138 @@
*/
#include "nr_modulation.h"
-
-extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
+#include "PHY/NR_REFSIG/nr_mod_table.h"
void nr_modulation(uint32_t *in,
uint32_t length,
uint16_t mod_order,
int16_t *out)
{
- uint16_t offset;
- uint8_t idx, b_idx;
-
- offset = (mod_order==2)? NR_MOD_TABLE_QPSK_OFFSET : (mod_order==4)? NR_MOD_TABLE_QAM16_OFFSET : \
- (mod_order==6)? NR_MOD_TABLE_QAM64_OFFSET: (mod_order==8)? NR_MOD_TABLE_QAM256_OFFSET : 0;
-
- for (int i=0; i<length/mod_order; i++)
- {
- idx = 0;
- for (int j=0; j<mod_order; j++)
- {
- b_idx = (i*mod_order+j)&0x1f;
- if (i && (!b_idx))
- in++;
- idx ^= (((*in)>>b_idx)&1)<<(mod_order-j-1);
+ uint16_t mask = ((1<<mod_order)-1);
+ int32_t* nr_mod_table32;
+ int32_t* out32 = (int32_t*) out;
+ uint8_t* in_bytes = (uint8_t*) in;
+ uint64_t* in64 = (uint64_t*) in;
+ int64_t* out64 = (int64_t*) out;
+ uint8_t idx;
+ uint32_t i,j;
+ uint32_t bit_cnt;
+ uint64_t x,x1,x2;
+
+#if defined(__SSE2__)
+ __m128i *nr_mod_table128;
+ __m128i *out128;
+#endif
+
+ LOG_D(PHY,"nr_modulation: length %d, mod_order %d\n",length,mod_order);
+
+ switch (mod_order) {
+
+#if defined(__SSE2__)
+ case 2:
+ nr_mod_table128 = (__m128i*) nr_qpsk_byte_mod_table;
+ out128 = (__m128i*) out;
+ for (i=0; i<length/8; i++)
+ out128[i] = nr_mod_table128[in_bytes[i]];
+ // the bits that are left out
+ i = i*8/2;
+ nr_mod_table32 = (int32_t*) nr_qpsk_mod_table;
+ while (i<length/2){
+ idx = ((in_bytes[(i*2)/8]>>((i*2)&0x7)) & mask);
+ out32[i] = nr_mod_table32[idx];
+ i++;
+ }
+ return;
+#else
+ case 2:
+ nr_mod_table32 = (int32_t*) nr_qpsk_mod_table;
+ for (i=0; i<length/mod_order; i++) {
+ idx = ((in[i*2/32]>>((i*2)&0x1f)) & mask);
+ out32[i] = nr_mod_table32[idx];
+ }
+ return;
+#endif
+
+ case 4:
+ out64 = (int64_t*) out;
+ for (i=0; i<length/8; i++)
+ out64[i] = nr_16qam_byte_mod_table[in_bytes[i]];
+ // the bits that are left out
+ i = i*8/4;
+ while (i<length/4){
+ idx = ((in_bytes[(i*4)/8]>>((i*4)&0x7)) & mask);
+ out32[i] = nr_16qam_mod_table[idx];
+ i++;
+ }
+ return;
+
+ case 6:
+ j = 0;
+ for (i=0; i<length/192; i++) {
+ x = in64[i*3];
+ x1 = x&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x>>12)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x>>24)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x>>36)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x>>48)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x2 = (x>>60);
+ x = in64[i*3+1];
+ x2 |= x<<4;
+ x1 = x2&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>12)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>24)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>36)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>48)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x2 = ((x>>56)&0xf0) | (x2>>60);
+ x = in64[i*3+2];
+ x2 |= x<<8;
+ x1 = x2&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>12)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>24)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>36)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x2>>48)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x2 = ((x>>52)&0xff0) | (x2>>60);
+ out64[j++] = nr_64qam_mod_table[x2];
+ }
+ i *= 24;
+ bit_cnt = i * 8;
+ while (bit_cnt < length) {
+ x = *((uint32_t*)(in_bytes+i));
+ x1 = x&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ x1 = (x>>12)&4095;
+ out64[j++] = nr_64qam_mod_table[x1];
+ i += 3;
+ bit_cnt += 24;
}
+ return;
+
+ case 8:
+ nr_mod_table32 = (int32_t*) nr_256qam_mod_table;
+ for (i=0; i<length/8; i++)
+ out32[i] = nr_mod_table32[in_bytes[i]];
+ return;
- out[i<<1] = nr_mod_table[(offset+idx)<<1];
- out[(i<<1)+1] = nr_mod_table[((offset+idx)<<1)+1];
+ default:
+ break;
}
+ AssertFatal(false,"Invalid or unsupported modulation order %d\n",mod_order);
+
}
void nr_layer_mapping(int16_t **mod_symbs,
diff --git a/openair1/PHY/MODULATION/ofdm_mod.c b/openair1/PHY/MODULATION/ofdm_mod.c
index 855e649cc5e629a128ba9ffcc680f07c6525956d..e1d21af9b9fb14de87f2cb1f1d6bbec055af400e 100644
--- a/openair1/PHY/MODULATION/ofdm_mod.c
+++ b/openair1/PHY/MODULATION/ofdm_mod.c
@@ -88,7 +88,7 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input
if(nb_symbols == 0) return;
- short temp[4096*4] __attribute__((aligned(32)));
+ short temp[2*2*6144*4] __attribute__((aligned(32)));
unsigned short i,j;
short k;
@@ -125,9 +125,23 @@ void PHY_ofdm_mod(int *input, /// pointer to complex input
case 3072:
idftsize = IDFT_3072;
break;
+
case 4096:
idftsize = IDFT_4096;
break;
+
+ case 6144:
+ idftsize= IDFT_6144;
+ break;
+
+ case 12288:
+ idftsize= IDFT_12288;
+ break;
+
+ case 24576:
+ idftsize= IDFT_24576;
+ break;
+
default:
idftsize = IDFT_512;
break;
diff --git a/openair1/PHY/MODULATION/slot_fep_nr.c b/openair1/PHY/MODULATION/slot_fep_nr.c
index c5c4d0b63821ac78cbb6d43a382f0c65be4cfcb2..cf0a50a0186dc19601385b2f496f8d88c523cd7a 100644
--- a/openair1/PHY/MODULATION/slot_fep_nr.c
+++ b/openair1/PHY/MODULATION/slot_fep_nr.c
@@ -25,6 +25,7 @@
#include "nr_modulation.h"
#include "PHY/LTE_ESTIMATION/lte_estimation.h"
#include "PHY/NR_UE_ESTIMATION/nr_estimation.h"
+#include <common/utils/LOG/log.h>
//#define DEBUG_FEP
@@ -211,10 +212,10 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
}
int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue,
- unsigned char symbol,
- unsigned char Ns,
- int sample_offset,
- int no_prefix)
+ unsigned char symbol,
+ unsigned char Ns,
+ int sample_offset,
+ int no_prefix)
{
NR_DL_FRAME_PARMS *frame_parms = &ue->frame_parms;
NR_UE_COMMON *common_vars = &ue->common_vars;
@@ -338,7 +339,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue,
#endif
- dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
+ dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset],
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
#if UE_TIMING_TRACE
stop_meas(&ue->rx_dft_stats);
@@ -362,7 +363,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue,
dft(dftsize,(int16_t *)tmp_dft_in,
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
} else { // use dft input from RX buffer directly
- dft(dftsize,(int16_t *) &common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
+ dft(dftsize,(int16_t *) &common_vars->rxdata[aa][rx_offset],
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
}
#if UE_TIMING_TRACE
@@ -394,12 +395,13 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms,
int sample_offset,
int no_prefix)
{
- uint32_t slot_offset;
- uint32_t rxdata_offset;
+ int32_t slot_offset, rxdata_offset;
unsigned int nb_prefix_samples = (no_prefix ? 0 : frame_parms->nb_prefix_samples);
unsigned int nb_prefix_samples0 = (no_prefix ? 0 : frame_parms->nb_prefix_samples0);
+ int tmp_dft_in[8192] __attribute__ ((aligned (32)));
+
dft_size_idx_t dftsize;
switch (frame_parms->ofdm_symbol_size) {
@@ -442,14 +444,29 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms,
slot_offset = frame_parms->get_samples_slot_timestamp(Ns,frame_parms,0);
-
if(symbol == 0)
rxdata_offset = slot_offset + nb_prefix_samples0 - SOFFSET;
else
rxdata_offset = slot_offset + nb_prefix_samples0 + (symbol * (frame_parms->ofdm_symbol_size + nb_prefix_samples)) - SOFFSET;
- dft(dftsize,(int16_t *)&rxdata[rxdata_offset],
- (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1);
+ if(sample_offset>rxdata_offset) {
+ memcpy((void *)tmp_dft_in,
+ (void *) &rxdata[frame_parms->samples_per_frame-sample_offset+rxdata_offset],
+ (sample_offset-rxdata_offset)*sizeof(int));
+
+ memcpy((void *)&tmp_dft_in[sample_offset-rxdata_offset],
+ (void *) &rxdata[0],
+ (frame_parms->ofdm_symbol_size-sample_offset+rxdata_offset)*sizeof(int));
+
+ dft(dftsize,(int16_t *)&tmp_dft_in,
+ (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1);
+ }
+ else
+ dft(dftsize,(int16_t *)&rxdata[rxdata_offset-sample_offset],
+ (int16_t *)&rxdataF[symbol * frame_parms->ofdm_symbol_size], 1);
+
+ // clear DC carrier from OFDM symbols
+ rxdataF[symbol * frame_parms->ofdm_symbol_size] = 0;
return(0);
}
diff --git a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c
index f94a82c111820ba61af2d9bf5eb9e3173dfd9c6e..3f7c7817f77fac6807f87a0bac462e9b0f4a1075 100644
--- a/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c
+++ b/openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c
@@ -28,7 +28,7 @@
#include "PHY/NR_UE_ESTIMATION/filt16a_32.h"
//#define DEBUG_CH
-
+//#define DEBUG_PUSCH
int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
unsigned char Ns,
@@ -116,7 +116,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
//------------------generate DMRS------------------//
- nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->dmrs_config_type);
+ if (pusch_pdu->transform_precoding==1) // if transform precoding is disabled
+ nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, pusch_pdu->rb_start*NR_NB_SC_PER_RB, pusch_pdu->dmrs_config_type);
+ else
+ nr_pusch_dmrs_rx(gNB, Ns, gNB->nr_gold_pusch_dmrs[pusch_pdu->scid][Ns][symbol], &pilot[0], 1000, 0, nb_rb_pusch, 0, pusch_pdu->dmrs_config_type);
//------------------------------------------------//
@@ -129,8 +132,9 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
memset(ul_ch,0,4*(gNB->frame_parms.ofdm_symbol_size));
#ifdef DEBUG_PUSCH
+ printf("symbol_offset %d, nushift %d\n",symbol_offset,nushift);
printf("ch est pilot addr %p RB_DL %d\n",&pilot[0], gNB->frame_parms.N_RB_UL);
- printf("k %d, first_carrier %d\n",k,gNB->frame_parms.first_carrier_offset);
+ printf("bwp_start_subcarrier %d, k %d, first_carrier %d\n",bwp_start_subcarrier,k,gNB->frame_parms.first_carrier_offset);
printf("rxF addr %p p %d\n", rxF,p);
printf("ul_ch addr %p nushift %d\n",ul_ch,nushift);
#endif
@@ -145,7 +149,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
#ifdef DEBUG_PUSCH
printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1]));
printf("pilot 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]);
- printf("data 0 : rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",rxF[2],rxF[3],&rxF[2],ch[0],ch[1],pil[0],pil[1]);
+ printf("data 0 : rxF - > (%d,%d)\n",rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fl,
@@ -163,6 +167,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
#ifdef DEBUG_PUSCH
printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data 1 : rxF - > (%d,%d)\n",rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fml,
ch,
@@ -178,6 +183,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
#ifdef DEBUG_PUSCH
printf("pilot 2 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data 2 : rxF - > (%d,%d)\n",rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fmm,
ch,
@@ -198,7 +204,8 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PUSCH
- printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fml,
ch,
@@ -214,6 +221,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
#ifdef DEBUG_PUSCH
printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fmm,
ch,
@@ -235,6 +243,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PUSCH
printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data %u : rxF - > (%d,%d)\n",pilot_cnt,rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fm,
ch,
@@ -253,6 +262,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
#ifdef DEBUG_PUSCH
printf("ch 0 %d\n",((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1]));
printf("pilot %u: rxF - > (%d,%d) addr %p ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+1,rxF[0],rxF[1],&rxF[0],ch[0],ch[1],pil[0],pil[1]);
+ printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+1,rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fmr,
ch,
@@ -268,6 +278,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PUSCH
printf("pilot %u: rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("data %u : rxF - > (%d,%d)\n",pilot_cnt+2,rxF[2],rxF[3]);
#endif
multadd_real_vector_complex_scalar(fr,
ch,
@@ -275,70 +286,69 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
8);
- // check if PRB crosses DC and improve estimates around DC
- if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) {
- ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset];
- uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier);
- uint16_t idxPil = idxDC/2;
- re_offset = k;
- pil = (int16_t *)&pilot[0];
- pil += (idxPil-2);
- ul_ch += (idxDC-4);
- ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10);
- re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size;
- rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)];
- ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
- ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
-
- // for proper allignment of SIMD vectors
- if((gNB->frame_parms.N_RB_UL&1)==0) {
-
- multadd_real_vector_complex_scalar(fdcl,
- ch,
- ul_ch-4,
- 8);
-
- pil += 4;
- re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size;
+ // check if PRB crosses DC and improve estimates around DC
+ if ((bwp_start_subcarrier < gNB->frame_parms.ofdm_symbol_size) && (bwp_start_subcarrier+nb_rb_pusch*12 >= gNB->frame_parms.ofdm_symbol_size)) {
+ ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset];
+ uint16_t idxDC = 2*(gNB->frame_parms.ofdm_symbol_size - bwp_start_subcarrier);
+ uint16_t idxPil = idxDC/2;
+ re_offset = k;
+ pil = (int16_t *)&pilot[0];
+ pil += (idxPil-2);
+ ul_ch += (idxDC-4);
+ ul_ch = memset(ul_ch, 0, sizeof(int16_t)*10);
+ re_offset = (re_offset+idxDC/2-2) % gNB->frame_parms.ofdm_symbol_size;
rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)];
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
+
+ // for proper allignment of SIMD vectors
+ if((gNB->frame_parms.N_RB_UL&1)==0) {
+
+ multadd_real_vector_complex_scalar(fdcl,
+ ch,
+ ul_ch-4,
+ 8);
- multadd_real_vector_complex_scalar(fdcr,
- ch,
- ul_ch-4,
- 8);
- } else {
+ pil += 4;
+ re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size;
+ rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)];
+ ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
+ ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
- multadd_real_vector_complex_scalar(fdclh,
- ch,
- ul_ch,
- 8);
+ multadd_real_vector_complex_scalar(fdcr,
+ ch,
+ ul_ch-4,
+ 8);
+ }
+ else {
+ multadd_real_vector_complex_scalar(fdclh,
+ ch,
+ ul_ch,
+ 8);
- pil += 4;
- re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size;
- rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)];
- ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
- ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
+ pil += 4;
+ re_offset = (re_offset+4) % gNB->frame_parms.ofdm_symbol_size;
+ rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+nushift+re_offset)];
+ ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
+ ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
- multadd_real_vector_complex_scalar(fdcrh,
- ch,
- ul_ch,
- 8);
+ multadd_real_vector_complex_scalar(fdcrh,
+ ch,
+ ul_ch,
+ 8);
+ }
}
-
- }
#ifdef DEBUG_PDSCH
- ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset];
- for(uint16_t idxP=0; idxP<ceil((float)nb_rb_pusch*12/8); idxP++) {
- for(uint8_t idxI=0; idxI<16; idxI+=2) {
- printf("%d\t%d\t",ul_ch[idxP*16+idxI],ul_ch[idxP*16+idxI+1]);
+ ul_ch = (int16_t *)&ul_ch_estimates[aarx][ch_offset];
+ for(uint16_t idxP=0; idxP<ceil((float)nb_rb_pusch*12/8); idxP++) {
+ for(uint8_t idxI=0; idxI<16; idxI+=2) {
+ printf("%d\t%d\t",ul_ch[idxP*16+idxI],ul_ch[idxP*16+idxI+1]);
+ }
+ printf("%d\n",idxP);
}
- printf("%d\n",idxP);
- }
#endif
-
- } else { //pusch_dmrs_type2 |p_r,p_l,d,d,d,d,p_r,p_l,d,d,d,d|
+ }
+ else { //pusch_dmrs_type2 |p_r,p_l,d,d,d,d,p_r,p_l,d,d,d,d|
// Treat first DMRS specially (left edge)
@@ -422,13 +432,12 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ul_ch_128 = (__m128i *)&ul_ch_estimates[aarx][ch_offset];
ul_ch_128[0] = _mm_slli_epi16 (ul_ch_128[0], 2);
- }
-
+ }
// Convert to time domain
- switch (gNB->frame_parms.ofdm_symbol_size) {
+ switch (gNB->frame_parms.ofdm_symbol_size) {
case 128:
idft(IDFT_128,(int16_t*) &ul_ch_estimates[aarx][symbol_offset],
(int16_t*) ul_ch_estimates_time[aarx],
diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.c b/openair1/PHY/NR_REFSIG/dmrs_nr.c
index ed37a79d0f243f43aa9c61a39fab2dfdbba02dcc..7042c152fdf8ee0544b7d4f68c0cb0bcb64414cc 100644
--- a/openair1/PHY/NR_REFSIG/dmrs_nr.c
+++ b/openair1/PHY/NR_REFSIG/dmrs_nr.c
@@ -33,146 +33,34 @@
#include "PHY/NR_REFSIG/ss_pbch_nr.h"
#include "PHY/NR_REFSIG/dmrs_nr.h"
-/***********************************************************************/
-
-// TS 38.211 Table 6.4.1.1.3-3: PUSCH DMRS positions l' within a slot for single-symbol DMRS and intra-slot frequency hopping disabled.
-// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B.
-// When l' = l0, it is represented by 1
-// E.g. when symbol duration is 12 in colomn 7, value 1057 ('10000100001') which means l' = l0, 5, 10.
-
-int32_t table_6_4_1_1_3_3_pusch_dmrs_positions_l [12][8] = { // Duration in symbols
-{-1, -1, -1, -1, 1, 1, 1, 1}, //<4 // (DMRS l' position)
-{1, 1, 1, 1, 1, 1, 1, 1}, //4 // (DMRS l' position)
-{1, 1, 1, 1, 1, 5, 5, 5}, //5 // (DMRS l' position)
-{1, 1, 1, 1, 1, 5, 5, 5}, //6 // (DMRS l' position)
-{1, 1, 1, 1, 1, 5, 5, 5}, //7 // (DMRS l' position)
-{1, 129, 129, 129, 1, 65, 73, 73}, //8 // (DMRS l' position)
-{1, 129, 129, 129, 1, 65, 73, 73}, //9 // (DMRS l' position)
-{1, 513, 577, 577, 1, 257, 273, 585}, //10 // (DMRS l' position)
-{1, 513, 577, 577, 1, 257, 273, 585}, //11 // (DMRS l' position)
-{1, 513, 577, 2337, 1, 1025, 1057, 585}, //12 // (DMRS l' position)
-{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //13 // (DMRS l' position)
-{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //14 // (DMRS l' position)
-};
-
-
-// TS 38.211 Table 6.4.1.1.3-4: PUSCH DMRS positions l' within a slot for double-symbol DMRS and intra-slot frequency hopping disabled.
-// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B.
-// When l' = l0, it is represented by 1
-
-int32_t table_6_4_1_1_3_4_pusch_dmrs_positions_l [12][8] = { // Duration in symbols
-{-1, -1, -1, -1, -1, -1, -1, -1}, //<4 // (DMRS l' position)
-{1, 1, -1, -1, -1, -1, -1, -1}, //4 // (DMRS l' position)
-{1, 1, -1, -1, 1, 1, -1, -1}, //5 // (DMRS l' position)
-{1, 1, -1, -1, 1, 1, -1, -1}, //6 // (DMRS l' position)
-{1, 1, -1, -1, 1, 1, -1, -1}, //7 // (DMRS l' position)
-{1, 1, -1, -1, 1, 33, -1, -1}, //8 // (DMRS l' position)
-{1, 1, -1, -1, 1, 33, -1, -1}, //9 // (DMRS l' position)
-{1, 257, -1, -1, 1, 129, -1, -1}, //10 // (DMRS l' position)
-{1, 257, -1, -1, 1, 129, -1, -1}, //11 // (DMRS l' position)
-{1, 257, -1, -1, 1, 513, -1, -1}, //12 // (DMRS l' position)
-{1, 1025, -1, -1, 1, 513, -1, -1}, //13 // (DMRS l' position)
-{1, 1025, -1, -1, 1, 513, -1, -1}, //14 // (DMRS l' position)
-};
-
-int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength) {
-
- uint8_t row, colomn;
- int32_t l_prime;
-
- colomn = additional_pos;
-
- if (mapping_type == typeB)
- colomn += 4;
-
- if (duration_in_symbols < 4)
- row = 0;
- else
- row = duration_in_symbols - 3;
-
- if (pusch_maxLength == pusch_len1)
- l_prime = table_6_4_1_1_3_3_pusch_dmrs_positions_l[row][colomn];
- else
- l_prime = table_6_4_1_1_3_4_pusch_dmrs_positions_l[row][colomn];
-
- AssertFatal(l_prime>0,"invalid l_prime < 0\n");
-
- return l_prime;
-}
-
-/*******************************************************************
-*
-* NAME : is_dmrs_symbol
-*
-* PARAMETERS : l ofdm symbol index within slot
-* k subcarrier index
-* start_sc first subcarrier index
-* k_prime index alternating 0 and 1
-* n index starting 0,1,...
-* delta see Table 6.4.1.1.3
-* duration_in_symbols number of scheduled PUSCH ofdm symbols
-* dmrs_UplinkConfig DMRS uplink configuration
-* mapping_type PUSCH mapping type (A or B)
-* ofdm_symbol_size IFFT size
-*
-* RETURN : 0 if symbol(k,l) is data, or 1 if symbol(k,l) is dmrs
-*
-* DESCRIPTION : 3GPP TS 38.211 6.4.1.1 Demodulation reference signal for PUSCH
-*
-*********************************************************************/
-
-uint8_t is_dmrs_symbol(uint8_t l,
- uint16_t k,
- uint16_t start_sc,
- uint8_t k_prime,
- uint16_t n,
- uint8_t delta,
- uint8_t duration_in_symbols,
- uint8_t dmrs_type,
- uint16_t ofdm_symbol_size) {
-
- uint8_t is_dmrs_freq, is_dmrs_time, l0;
- int32_t l_prime_mask;
- pusch_dmrs_AdditionalPosition_t additional_pos = pusch_dmrs_pos0;
- pusch_maxLength_t pusch_maxLength = pusch_len1;
- uint8_t mapping_type = typeB;
-
- is_dmrs_freq = 0;
- is_dmrs_time = 0;
-
-
- l0 = get_l0_ul(mapping_type, 2);
- l_prime_mask = get_l_prime(duration_in_symbols, mapping_type, additional_pos, pusch_maxLength);
-
- if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%ofdm_symbol_size))
- is_dmrs_freq = 1;
-
-
- if (l_prime_mask == 1){
-
- if (l == l0)
- is_dmrs_time = 1;
-
- } else if ( (l==l0) || (((l_prime_mask>>l)&1) == 1 && l!=0) )
- is_dmrs_time = 1;
- if (pusch_maxLength == pusch_len2){
- if (((l_prime_mask>>(l-1))&1) == 1 && l!=0 && l!=1)
- is_dmrs_time = 1;
-
- if (l-1 == l0)
- is_dmrs_time = 1;
-
- }
-
- if (is_dmrs_time && is_dmrs_freq)
- return 1;
+uint8_t allowed_xlsch_re_in_dmrs_symbol(uint16_t k,
+ uint16_t start_sc,
+ uint8_t numDmrsCdmGrpsNoData,
+ uint8_t dmrs_type) {
+ uint8_t delta;
+ uint16_t diff;
+ if (k>start_sc)
+ diff = k-start_sc;
else
- return 0;
-
+ diff = start_sc-k;
+ for (int i = 0; i<numDmrsCdmGrpsNoData; i++){
+ if (dmrs_type==NFAPI_NR_DMRS_TYPE1) {
+ delta = i;
+ if (((diff)%2) == delta)
+ return (0);
+ }
+ else {
+ delta = i<<1;
+ if ( (((diff)%6) == delta) || (((k-start_sc)%6) == (delta+1)) )
+ return (0);
+ }
+ }
+ return (1);
}
+
/*******************************************************************
*
* NAME : pseudo_random_gold_sequence
@@ -364,25 +252,6 @@ void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2
#endif
}
-/*******************************************************************
-*
-* NAME : get_l0_ul
-*
-* PARAMETERS : mapping_type : PUSCH mapping type
-* dmrs_typeA_position : higher layer parameter
-*
-* RETURN : demodulation reference signal for PUSCH
-*
-* DESCRIPTION : see TS 38.211 V15.4.0 Demodulation reference signals for PUSCH
-*
-*********************************************************************/
-
-uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position) {
-
- return ((mapping_type==typeA)?dmrs_typeA_position:0);
-
-}
-
/*******************************************************************
*
* NAME : get_dmrs_freq_idx_ul
diff --git a/openair1/PHY/NR_REFSIG/dmrs_nr.h b/openair1/PHY/NR_REFSIG/dmrs_nr.h
index f1dfffff8b516b96d5b821cd6e28c0600b23d6ab..c76f58ad181d091727f8a425fdde719b2682782b 100644
--- a/openair1/PHY/NR_REFSIG/dmrs_nr.h
+++ b/openair1/PHY/NR_REFSIG/dmrs_nr.h
@@ -54,20 +54,12 @@
int pseudo_random_sequence(int M_PN, uint32_t *c, uint32_t cinit);
void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2][14], uint16_t Nid_cell);
void generate_dmrs_pbch(uint32_t dmrs_pbch_bitmap[DMRS_PBCH_I_SSB][DMRS_PBCH_N_HF][DMRS_BITMAP_SIZE], uint16_t Nid_cell);
-uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position);
uint16_t get_dmrs_freq_idx_ul(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t dmrs_type);
-int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength);
-
-uint8_t is_dmrs_symbol(uint8_t l,
- uint16_t k,
- uint16_t start_sc,
- uint8_t k_prime,
- uint16_t n,
- uint8_t delta,
- uint8_t duration_in_symbols,
- uint8_t dmrs_type,
- uint16_t ofdm_symbol_size);
+uint8_t allowed_xlsch_re_in_dmrs_symbol(uint16_t k,
+ uint16_t start_sc,
+ uint8_t numDmrsCdmGrpsNoData,
+ uint8_t dmrs_type);
#undef EXTERN
diff --git a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c
index f933a8c7ab322a8295f83d9e314209a2e7d56200..4eeb8a6e96f18214cfdcf2877e15b64b9328ba84 100644
--- a/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c
+++ b/openair1/PHY/NR_REFSIG/nr_dmrs_rx.c
@@ -32,7 +32,7 @@
//#define NR_PBCH_DMRS_LENGTH_DWORD 5
//#define NR_PBCH_DMRS_LENGTH 144
-//#define DEBUG_PDCCH
+//#define DEBUG_PUSCH
#include "refsig_defs_ue.h"
#include "PHY/defs_nr_UE.h"
@@ -45,7 +45,7 @@ int wt1[8][2] = {{1,1},{1,1},{1,1},{1,1},{1,-1},{1,-1},{1,-1},{1,-1}};
int wf2[12][2] = {{1,1},{1,-1},{1,1},{1,-1},{1,1},{1,-1},{1,1},{1,1},{1,1},{1,-1},{1,1},{1,1}};
int wt2[12][2] = {{1,1},{1,1},{1,1},{1,1},{1,1},{1,1},{1,-1},{1,-1},{1,-1},{1,-1},{1,-1},{1,-1}};
-
+// complex conjugate of mod table
short nr_rx_mod_table[14] = {0,0,23170,-23170,-23170,23170,23170,-23170,23170,23170,-23170,-23170,-23170,23170};
short nr_rx_nmod_table[14] = {0,0,-23170,23170,23170,-23170,-23170,23170,-23170,-23170,23170,23170,23170,-23170};
@@ -57,39 +57,42 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB,
unsigned short p,
unsigned char lp,
unsigned short nb_pusch_rb,
+ uint32_t re_offset,
uint8_t dmrs_type)
{
- int8_t w;
+ int8_t w, nb_dmrs;
short *mod_table;
unsigned char idx=0;
-
+ int k;
typedef int array_of_w[2];
array_of_w *wf;
array_of_w *wt;
-
wf = (dmrs_type==pusch_dmrs_type1) ? wf1 : wf2;
wt = (dmrs_type==pusch_dmrs_type1) ? wt1 : wt2;
+ int dmrs_offset = re_offset/((dmrs_type==pusch_dmrs_type1)?2:3);
+
if (dmrs_type > 2)
- LOG_E(PHY,"Bad PUSCH DMRS config type %d\n", dmrs_type);
+ LOG_E(PHY,"PUSCH DMRS config type %d not valid\n", dmrs_type+1);
if ((p>=1000) && (p<((dmrs_type==pusch_dmrs_type1) ? 1008 : 1012))) {
if (gNB->frame_parms.Ncp == NORMAL) {
-
- for (int i=0; i<nb_pusch_rb*((dmrs_type==pusch_dmrs_type1) ? 6:4); i++) {
-
+ nb_dmrs = ((dmrs_type==pusch_dmrs_type1) ? 6:4);
+ for (int i=dmrs_offset; i<dmrs_offset+(nb_pusch_rb*nb_dmrs); i++) {
+ k = i-dmrs_offset;
w = (wf[p-1000][i&1])*(wt[p-1000][lp]);
mod_table = (w==1) ? nr_rx_mod_table : nr_rx_nmod_table;
idx = ((((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1);
- ((int16_t*)output)[i<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
- ((int16_t*)output)[(i<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1];
+ ((int16_t*)output)[k<<1] = mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
+ ((int16_t*)output)[(k<<1)+1] = mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1];
#ifdef DEBUG_PUSCH
- printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb);
- printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]);
- printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1),
- (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[i<<1], ((int16_t*)output)[(i<<1)+1]);
+ printf("nr_pusch_dmrs_rx dmrs config type %d port %d nb_pusch_rb %d\n", dmrs_type, p, nb_pusch_rb);
+ printf("wf[%d] = %d wt[%d]= %d\n", i&1, wf[p-1000][i&1], lp, wt[p-1000][lp]);
+ printf("i %d idx %d pusch gold %u b0-b1 %d-%d mod_dmrs %d %d\n", i, idx, nr_gold_pusch[(i<<1)>>5], (((nr_gold_pusch[(i<<1)>>5])>>((i<<1)&0x1f))&1),
+ (((nr_gold_pusch[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1), ((int16_t*)output)[k<<1], ((int16_t*)output)[(k<<1)+1]);
#endif
+
}
} else {
LOG_E(PHY,"extended cp not supported for PUSCH DMRS yet\n");
@@ -102,7 +105,6 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB,
}
-
int nr_pdsch_dmrs_rx(PHY_VARS_NR_UE *ue,
unsigned int Ns,
unsigned int *nr_gold_pdsch,
diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c
new file mode 100644
index 0000000000000000000000000000000000000000..b0f9e6d03c55562555bfb1048b86e5c132758fa4
--- /dev/null
+++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.c
@@ -0,0 +1,87 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+#include "nr_refsig.h"
+#include "nr_mod_table.h"
+
+void nr_generate_modulation_table() {
+ float sqrt2 = 0.70711;
+ float sqrt10 = 0.31623;
+ float sqrt42 = 0.15430;
+ float sqrt170 = 0.076696;
+ float val = 32768.0;
+ uint32_t i,j;
+ short* table;
+
+ // QPSK
+ for (i=0; i<4; i++) {
+ nr_qpsk_mod_table[i*2] = (short)(1-2*(i&1))*val*sqrt2*sqrt2;
+ nr_qpsk_mod_table[i*2+1] = (short)(1-2*((i>>1)&1))*val*sqrt2*sqrt2;
+ //printf("%d j%d\n",nr_qpsk_mod_table[i*2],nr_qpsk_mod_table[i*2+1]);
+ }
+
+#if defined(__SSE2__)
+ //QPSK m128
+ table = (short*) nr_qpsk_byte_mod_table;
+ for (i=0; i<256; i++) {
+ for (j=0; j<4; j++) {
+ table[i*8+(j*2)] = (short)(1-2*((i>>(j*2))&1))*val*sqrt2*sqrt2;
+ table[i*8+(j*2)+1] = (short)(1-2*((i>>(j*2+1))&1))*val*sqrt2*sqrt2;
+ //printf("%d j%d\n",nr_qpsk_byte_mod_table[i*8+(j*2)],nr_qpsk_byte_mod_table[i*8+(j*2)+1]);
+ }
+ }
+#endif
+
+ //16QAM
+ table = (short*) nr_16qam_byte_mod_table;
+ for (i=0; i<256; i++) {
+ for (j=0; j<2; j++) {
+ table[i*4+(j*2)] = (short)((1-2*((i>>(j*4))&1))*(2-(1-2*((i>>(j*4+2))&1))))*val*sqrt10*sqrt2;
+ table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*4+1))&1))*(2-(1-2*((i>>(j*4+3))&1))))*val*sqrt10*sqrt2;
+ //printf("%d j%d\n",nr_16qam_byte_mod_table[i*4+(j*2)],nr_16qam_byte_mod_table[i*4+(j*2)+1]);
+ }
+ }
+
+ table = (short*) nr_16qam_mod_table;
+ for (i=0; i<16; i++) {
+ table[i*2] = (short)((1-2*(i&1))*(2-(1-2*((i>>2)&1))))*val*sqrt10*sqrt2;
+ table[i*2+1] = (short)((1-2*((i>>1)&1))*(2-(1-2*((i>>3)&1))))*val*sqrt10*sqrt2;
+ //printf("%d j%d\n",table[i*2],table[i*2+1]);
+ }
+
+ //64QAM
+ table = (short*) nr_64qam_mod_table;
+ for (i=0; i<4096; i++) {
+ for (j=0; j<2; j++) {
+ table[i*4+(j*2)] = (short)((1-2*((i>>(j*6))&1))*(4-(1-2*((i>>(j*6+2))&1))*(2-(1-2*((i>>(j*6+4))&1)))))*val*sqrt42*sqrt2;
+ table[i*4+(j*2)+1] = (short)((1-2*((i>>(j*6+1))&1))*(4-(1-2*((i>>(j*6+3))&1))*(2-(1-2*((i>>(j*6+5))&1)))))*val*sqrt42*sqrt2;
+ //printf("%d j%d\n",table[i*4+(j*2)],table[i*4+(j*2)+1]);
+ }
+ }
+
+ //256QAM
+ table = (short*) nr_256qam_mod_table;
+ for (i=0; i<256; i++) {
+ table[i*2] = (short)((1-2*(i&1))*(8-(1-2*((i>>2)&1))*(4-(1-2*((i>>4)&1))*(2-(1-2*((i>>6)&1))))))*val*sqrt170*sqrt2;
+ table[i*2+1] = (short)((1-2*((i>>1)&1))*(8-(1-2*((i>>3)&1))*(4-(1-2*((i>>5)&1))*(2-(1-2*((i>>7)&1))))))*val*sqrt170*sqrt2;
+ }
+}
+
diff --git a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m
index 13a8d4ad09c38741bca610bccb6bd15e79204b89..6e1415bf2843d23f5d7fc29fad7608c5d12f6258 100644
--- a/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m
+++ b/openair1/PHY/NR_REFSIG/nr_gen_mod_table.m
@@ -45,7 +45,7 @@ for r=0:1 %0 -- 1 LS
for j=0:1 %0 -- 1 MS
%% Formula is dispalayed
-qpsk_table(2*r+j+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK);
+qpsk_table(2*j+r+1) = ((1-r*2)*QPSK + 1j*(1-2*j)*QPSK);
end
end
@@ -61,7 +61,7 @@ for b0=0:1
for b1=0:1
for b2=0:1
for b3=0:1
-qam16_table2(b0*8+b1*4+b2*2+b3*1+1) = qam16_table(b0*2+b2*1+1) + 1j*qam16_table(b1*2+b3*1+1);
+qam16_table2(b3*8+b2*4+b1*2+b0*1+1) = qam16_table(b0*2+b2*1+1) + 1j*qam16_table(b1*2+b3*1+1);
end
end
end
@@ -84,7 +84,7 @@ for b2=0:1
for b3=0:1
for b4=0:1
for b5=0:1
-qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1);
+qam64_table2(b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1);
end
end
end
@@ -116,7 +116,50 @@ for b6=0:1
for b7=0:1
%%qam64_table2(b0*32+b1*16+b2*8+b3*4+b4*2+b5*1+1) = qam64_table(b0*4+b2*2+b4*1+1) + 1j*qam64_table(b1*4+b3*2+b5*1+1);
-qam256_table2(b0*128+b1*64+b2*32+b3*16+b4*8+b5*4+b6*2+b7*1+1) = qam256_table(b0*8+b2*4+b4*2+b6*1+1) + 1j*qam256_table(b1*8+b3*4+b5*2+b7*1+1);
+qam256_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1) = qam256_table(b0*8+b2*4+b4*2+b6*1+1) + 1j*qam256_table(b1*8+b3*4+b5*2+b7*1+1);
+end
+end
+end
+end
+end
+end
+end
+end
+
+%%QPSK byte
+for b0=0:1
+for b1=0:1
+for b2=0:1
+for b3=0:1
+for b4=0:1
+for b5=0:1
+for b6=0:1
+for b7=0:1
+qpsk_byte_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1,:)=[(1-b0*2)*QPSK (1-2*b1)*QPSK (1-b2*2)*QPSK (1-2*b3)*QPSK ...
+ (1-b4*2)*QPSK (1-2*b5)*QPSK (1-b6*2)*QPSK (1-2*b7)*QPSK];
+
+end
+end
+end
+end
+end
+end
+end
+end
+
+%%16QAM byte
+qam16_byte_table2=[];
+for b0=0:1
+for b1=0:1
+for b2=0:1
+for b3=0:1
+for b4=0:1
+for b5=0:1
+for b6=0:1
+for b7=0:1
+qam16_byte_table2(b7*128+b6*64+b5*32+b4*16+b3*8+b2*4+b1*2+b0*1+1,:)=[qam16_table(b0*2+b2*1+1) qam16_table(b1*2+b3*1+1) ...
+ qam16_table(b4*2+b6*1+1) qam16_table(b5*2+b7*1+1) ];
+
end
end
end
@@ -133,6 +176,8 @@ save mod_table.mat table
table2 = zeros(1,length(table)*2);
table2(1:2:end) = real(table);
table2(2:2:end) = imag(table);
+qpsk_byte_table2=round(K * qpsk_byte_table2'(:));
+qam16_byte_table2=round(K * qam16_byte_table2'(:));
fd = fopen("nr_mod_table.h","w");
fprintf(fd,"#define NR_MOD_TABLE_SIZE_SHORT %d\n", length(table)*2);
@@ -144,4 +189,10 @@ fprintf(fd,"#define NR_MOD_TABLE_QAM256_OFFSET %d\n", 87);
fprintf(fd,"short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {");
fprintf(fd,"%d,",table2(1:end-1));
fprintf(fd,"%d};\n",table2(end));
+fprintf(fd,"short nr_qpsk_mod_table[2048] = {");
+fprintf(fd,"%d,",qpsk_byte_table2(1:end-1));
+fprintf(fd,"%d};\n",qpsk_byte_table2(end));
+fprintf(fd,"short nr_qam16_mod_table[1024] = {");
+fprintf(fd,"%d,",qam16_byte_table2(1:end-1));
+fprintf(fd,"%d};\n",qam16_byte_table2(end));
fclose(fd);
diff --git a/openair1/PHY/NR_REFSIG/nr_gold.c b/openair1/PHY/NR_REFSIG/nr_gold.c
index 472d03e64907ac0ec9e609fd92f328a612fd9b50..4b007f1292e7780fddebf6fdaf38e8ac38ccb471 100644
--- a/openair1/PHY/NR_REFSIG/nr_gold.c
+++ b/openair1/PHY/NR_REFSIG/nr_gold.c
@@ -88,6 +88,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
uint16_t N_n_scid[NR_MAX_NB_CODEWORDS]={Nid, Nid}; // Not correct, appropriate scrambling IDs have to be updated to support DCI 1_1
uint8_t n_scid=0; // again works only for 1_0
for (uint8_t slot=0; slot<fp->slots_per_frame; slot++) {
+
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid));
diff --git a/openair1/PHY/NR_REFSIG/nr_mod_table.h b/openair1/PHY/NR_REFSIG/nr_mod_table.h
index a99842969906e03b4214acb8089de687395a631c..aa8b99f584b6d2554c1fbbd6563c1a64db5b9470 100644
--- a/openair1/PHY/NR_REFSIG/nr_mod_table.h
+++ b/openair1/PHY/NR_REFSIG/nr_mod_table.h
@@ -1,7 +1,44 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+#ifndef __PHY_NR_REFSIG_NR_MOD_TABLE__H__
+#define __PHY_NR_REFSIG_NR_MOD_TABLE__H__
+
#define NR_MOD_TABLE_SIZE_SHORT 686
#define NR_MOD_TABLE_BPSK_OFFSET 1
#define NR_MOD_TABLE_QPSK_OFFSET 3
#define NR_MOD_TABLE_QAM16_OFFSET 7
#define NR_MOD_TABLE_QAM64_OFFSET 23
#define NR_MOD_TABLE_QAM256_OFFSET 87
-short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,16384,16384,-16384,-16384,16384,16384,16384,-16384,-16384,16384,-16384,-16384,7327,7327,7327,21981,21981,7327,21981,21981,7327,-7327,7327,-21981,21981,-7327,21981,-21981,-7327,7327,-7327,21981,-21981,7327,-21981,21981,-7327,-7327,-7327,-21981,-21981,-7327,-21981,-21981,10726,10726,10726,3576,3576,10726,3576,3576,10726,17876,10726,25027,3576,17876,3576,25027,17876,10726,17876,3576,25027,10726,25027,3576,17876,17876,17876,25027,25027,17876,25027,25027,10726,-10726,10726,-3576,3576,-10726,3576,-3576,10726,-17876,10726,-25027,3576,-17876,3576,-25027,17876,-10726,17876,-3576,25027,-10726,25027,-3576,17876,-17876,17876,-25027,25027,-17876,25027,-25027,-10726,10726,-10726,3576,-3576,10726,-3576,3576,-10726,17876,-10726,25027,-3576,17876,-3576,25027,-17876,10726,-17876,3576,-25027,10726,-25027,3576,-17876,17876,-17876,25027,-25027,17876,-25027,25027,-10726,-10726,-10726,-3576,-3576,-10726,-3576,-3576,-10726,-17876,-10726,-25027,-3576,-17876,-3576,-25027,-17876,-10726,-17876,-3576,-25027,-10726,-25027,-3576,-17876,-17876,-17876,-25027,-25027,-17876,-25027,-25027,8886,8886,8886,12439,12439,8886,12439,12439,8886,5332,8886,1778,12439,5332,12439,1778,5332,8886,5332,12439,1778,8886,1778,12439,5332,5332,5332,1778,1778,5332,1778,1778,8886,19547,8886,15993,12439,19547,12439,15993,8886,23101,8886,26655,12439,23101,12439,26655,5332,19547,5332,15993,1778,19547,1778,15993,5332,23101,5332,26655,1778,23101,1778,26655,19547,8886,19547,12439,15993,8886,15993,12439,19547,5332,19547,1778,15993,5332,15993,1778,23101,8886,23101,12439,26655,8886,26655,12439,23101,5332,23101,1778,26655,5332,26655,1778,19547,19547,19547,15993,15993,19547,15993,15993,19547,23101,19547,26655,15993,23101,15993,26655,23101,19547,23101,15993,26655,19547,26655,15993,23101,23101,23101,26655,26655,23101,26655,26655,8886,-8886,8886,-12439,12439,-8886,12439,-12439,8886,-5332,8886,-1778,12439,-5332,12439,-1778,5332,-8886,5332,-12439,1778,-8886,1778,-12439,5332,-5332,5332,-1778,1778,-5332,1778,-1778,8886,-19547,8886,-15993,12439,-19547,12439,-15993,8886,-23101,8886,-26655,12439,-23101,12439,-26655,5332,-19547,5332,-15993,1778,-19547,1778,-15993,5332,-23101,5332,-26655,1778,-23101,1778,-26655,19547,-8886,19547,-12439,15993,-8886,15993,-12439,19547,-5332,19547,-1778,15993,-5332,15993,-1778,23101,-8886,23101,-12439,26655,-8886,26655,-12439,23101,-5332,23101,-1778,26655,-5332,26655,-1778,19547,-19547,19547,-15993,15993,-19547,15993,-15993,19547,-23101,19547,-26655,15993,-23101,15993,-26655,23101,-19547,23101,-15993,26655,-19547,26655,-15993,23101,-23101,23101,-26655,26655,-23101,26655,-26655,-8886,8886,-8886,12439,-12439,8886,-12439,12439,-8886,5332,-8886,1778,-12439,5332,-12439,1778,-5332,8886,-5332,12439,-1778,8886,-1778,12439,-5332,5332,-5332,1778,-1778,5332,-1778,1778,-8886,19547,-8886,15993,-12439,19547,-12439,15993,-8886,23101,-8886,26655,-12439,23101,-12439,26655,-5332,19547,-5332,15993,-1778,19547,-1778,15993,-5332,23101,-5332,26655,-1778,23101,-1778,26655,-19547,8886,-19547,12439,-15993,8886,-15993,12439,-19547,5332,-19547,1778,-15993,5332,-15993,1778,-23101,8886,-23101,12439,-26655,8886,-26655,12439,-23101,5332,-23101,1778,-26655,5332,-26655,1778,-19547,19547,-19547,15993,-15993,19547,-15993,15993,-19547,23101,-19547,26655,-15993,23101,-15993,26655,-23101,19547,-23101,15993,-26655,19547,-26655,15993,-23101,23101,-23101,26655,-26655,23101,-26655,26655,-8886,-8886,-8886,-12439,-12439,-8886,-12439,-12439,-8886,-5332,-8886,-1778,-12439,-5332,-12439,-1778,-5332,-8886,-5332,-12439,-1778,-8886,-1778,-12439,-5332,-5332,-5332,-1778,-1778,-5332,-1778,-1778,-8886,-19547,-8886,-15993,-12439,-19547,-12439,-15993,-8886,-23101,-8886,-26655,-12439,-23101,-12439,-26655,-5332,-19547,-5332,-15993,-1778,-19547,-1778,-15993,-5332,-23101,-5332,-26655,-1778,-23101,-1778,-26655,-19547,-8886,-19547,-12439,-15993,-8886,-15993,-12439,-19547,-5332,-19547,-1778,-15993,-5332,-15993,-1778,-23101,-8886,-23101,-12439,-26655,-8886,-26655,-12439,-23101,-5332,-23101,-1778,-26655,-5332,-26655,-1778,-19547,-19547,-19547,-15993,-15993,-19547,-15993,-15993,-19547,-23101,-19547,-26655,-15993,-23101,-15993,-26655,-23101,-19547,-23101,-15993,-26655,-19547,-26655,-15993,-23101,-23101,-23101,-26655,-26655,-23101,-26655,-26655};
+
+short nr_qpsk_mod_table[8];
+
+int32_t nr_16qam_mod_table[16];
+#if defined(__SSE2__)
+__m128i nr_qpsk_byte_mod_table[2048];
+#endif
+
+int64_t nr_16qam_byte_mod_table[1024];
+
+int64_t nr_64qam_mod_table[4096];
+
+int32_t nr_256qam_mod_table[512];
+#endif
diff --git a/openair1/PHY/NR_REFSIG/nr_refsig.h b/openair1/PHY/NR_REFSIG/nr_refsig.h
index 5af0e880999dcac8e8dec184be57835197e61fcb..786fb2af358eeb530b74b42a0c04e82bc317f004 100644
--- a/openair1/PHY/NR_REFSIG/nr_refsig.h
+++ b/openair1/PHY/NR_REFSIG/nr_refsig.h
@@ -26,7 +26,7 @@
#include "PHY/defs_gNB.h"
#include "PHY/LTE_REFSIG/lte_refsig.h"
-
+#include "PHY/sse_intrin.h"
/*!\brief This function generates the NR Gold sequence (38-211, Sec 5.2.1) for the PBCH DMRS.
@param PHY_VARS_gNB* gNB structure provides configuration, frame parameters and the pointers to the 32 bits sequence storage tables
@@ -48,5 +48,14 @@ int nr_pusch_dmrs_rx(PHY_VARS_gNB *gNB,
unsigned short p,
unsigned char lp,
unsigned short nb_pusch_rb,
+ uint32_t re_offset,
uint8_t dmrs_type);
+
+void init_scrambling_luts(void);
+
+void nr_generate_modulation_table(void);
+
+extern __m64 byte2m64_re[256];
+extern __m64 byte2m64_im[256];
+
#endif
diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.c b/openair1/PHY/NR_REFSIG/ptrs_nr.c
index 12f76b950f139e2e100bc758f8a8ef673ef411bb..785252126af64cb1e5df2948c2a27038e906f1dd 100644
--- a/openair1/PHY/NR_REFSIG/ptrs_nr.c
+++ b/openair1/PHY/NR_REFSIG/ptrs_nr.c
@@ -38,18 +38,18 @@
/***********************************************************************/
- //#define max(a,b) (((a) > (b)) ? (a) : (b))
+//#define max(a,b) (((a) > (b)) ? (a) : (b))
// TS 38.211 Table 6.4.1.2.2.1-1: The parameter kRE_ref.
// The first 4 colomns are DM-RS Configuration type 1 and the last 4 colomns are DM-RS Configuration type 2.
int16_t table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref [6][8] = {
-{ 0, 2, 6, 8, 0, 1, 6, 7},
-{ 2, 4, 8, 10, 1, 6, 7, 0},
-{ 1, 3, 7, 9, 2, 3, 8, 9},
-{ 3, 5, 9, 11, 3, 8, 9, 2},
-{-1, -1, -1, -1, 4, 5, 10, 11},
-{-1, -1, -1, -1, 5, 10, 11, 4},
+ { 0, 2, 6, 8, 0, 1, 6, 7},
+ { 2, 4, 8, 10, 1, 6, 7, 0},
+ { 1, 3, 7, 9, 2, 3, 8, 9},
+ { 3, 5, 9, 11, 3, 8, 9, 2},
+ {-1, -1, -1, -1, 4, 5, 10, 11},
+ {-1, -1, -1, -1, 5, 10, 11, 4},
};
@@ -68,55 +68,20 @@ int16_t table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref [6][8] = {
*********************************************************************/
int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset) {
-
uint8_t colomn;
int16_t k_RE_ref;
-
colomn = resourceElementOffset;
if (pusch_dmrs_type == 2)
colomn += 4;
k_RE_ref = table_6_4_1_2_2_1_1_pusch_ptrs_kRE_ref[dmrs_antenna_port][colomn];
-
AssertFatal(k_RE_ref>=0,"invalid k_RE_ref < 0. Check PTRS Configuration\n");
-
return k_RE_ref;
}
-/*******************************************************************
-*
-* NAME : get_K_ptrs
-*
-* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration
-* N_RB number of RBs scheduled for PUSCH
-*
-* RETURN : the parameter K_ptrs
-*
-* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-2
-*
-*********************************************************************/
-
-uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){
-
- uint16_t nrb0, nrb1;
-
- nrb0 = ptrs_UplinkConfig->frequencyDensity.n_rb0;
- nrb1 = ptrs_UplinkConfig->frequencyDensity.n_rb1;
- if (nrb0 == 0 || nrb0 == 0)
- return 2;
-
- if (N_RB < nrb0){
- LOG_I(PHY,"PUSH PT-RS is not present.\n");
- return 0;
- }
- else if (N_RB >= nrb0 && N_RB < nrb1)
- return 2;
- else
- return 4;
-}
/*******************************************************************
*
@@ -126,7 +91,7 @@ uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){
* duration_in_symbols number of scheduled PUSCH ofdm symbols
* start_symbol first ofdm symbol of PUSCH within slot
* L_ptrs the parameter L_ptrs
-* ofdm_symbol_size FFT size
+* ul_dmrs_symb_pos bitmap of the time domain positions of the DMRS symbols in the scheduled PUSCH
*
* RETURN : sets the bit map of PTRS ofdm symbol indicies
*
@@ -137,54 +102,31 @@ uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB){
void set_ptrs_symb_idx(uint16_t *ptrs_symbols,
uint8_t duration_in_symbols,
uint8_t start_symbol,
- uint8_t dmrs_type,
uint8_t L_ptrs,
- uint8_t pusch_maxLength,
- uint16_t ofdm_symbol_size) {
+ uint16_t ul_dmrs_symb_pos) {
- uint8_t i, last_symbol, is_dmrs_symbol1, is_dmrs_symbol2;
- int16_t l_ref;
-
- *ptrs_symbols = 0;
- i = 0;
- is_dmrs_symbol1 = 0;
- is_dmrs_symbol2 = 0;
- l_ref = start_symbol;
- last_symbol = start_symbol + duration_in_symbols - 1;
+ uint8_t i = 0, last_symbol, is_dmrs_symbol, l_ref;
+ int8_t l_counter;
+ l_ref = start_symbol;
+ last_symbol = start_symbol + duration_in_symbols - 1;
while ( (l_ref + i*L_ptrs) <= last_symbol) {
- is_dmrs_symbol1 = is_dmrs_symbol(max((l_ref + (i-1)*L_ptrs + 1), l_ref),
- 0,
- 0,
- 0,
- 0,
- 0,
- duration_in_symbols,
- dmrs_type,
- ofdm_symbol_size);
-
- is_dmrs_symbol2 = is_dmrs_symbol(l_ref + i*L_ptrs,
- 0,
- 0,
- 0,
- 0,
- 0,
- duration_in_symbols,
- dmrs_type,
- ofdm_symbol_size);
-
- if ( is_dmrs_symbol1 + is_dmrs_symbol2 > 0 ) {
-
- if (pusch_maxLength == 2)
- l_ref = l_ref + i*L_ptrs + 1;
- else
- l_ref = l_ref + i*L_ptrs;
-
- i = 1;
-
- continue;
+ is_dmrs_symbol = 0;
+
+ for(l_counter = l_ref + i*L_ptrs; l_counter >= max(l_ref + (i-1)*L_ptrs + 1, l_ref); l_counter--) {
+ if((ul_dmrs_symb_pos >> l_counter) & 0x01) {
+ is_dmrs_symbol = 1;
+ break;
+ }
+
+ }
+
+ if (is_dmrs_symbol) {
+ l_ref = l_counter;
+ i = 1;
+ continue;
}
*ptrs_symbols = *ptrs_symbols | (1<<(l_ref + i*L_ptrs));
@@ -192,53 +134,19 @@ void set_ptrs_symb_idx(uint16_t *ptrs_symbols,
}
}
-/*******************************************************************
-*
-* NAME : get_L_ptrs
-*
-* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration
-* I_mcs MCS index used for PUSCH
-*
-* RETURN : the parameter L_ptrs
-*
-* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-1
-*
-*********************************************************************/
-
-uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs) {
-
- uint8_t mcs1, mcs2, mcs3;
-
- mcs1 = ptrs_UplinkConfig->timeDensity.ptrs_mcs1;
- mcs2 = ptrs_UplinkConfig->timeDensity.ptrs_mcs2;
- mcs3 = ptrs_UplinkConfig->timeDensity.ptrs_mcs3;
-
- if (mcs1 == 0 || mcs2 == 0 || mcs3 == 0)
- return 1;
-
- if (I_mcs < mcs1){
- LOG_I(PHY,"PUSH PT-RS is not present.\n");
- return 0;
- }
- else if (I_mcs >= mcs1 && I_mcs < mcs2)
- return 4;
- else if (I_mcs >= mcs2 && I_mcs < mcs3)
- return 2;
- else
- return 1;
-}
-
/*******************************************************************
*
* NAME : is_ptrs_subcarrier
*
* PARAMETERS : k subcarrier index
-* K_ptrs the parameter K_ptrs
* n_rnti UE CRNTI
+* dmrs_antenna_port DMRS antenna port
+* K_ptrs the parameter K_ptrs
+* pusch_dmrs_type the DMRS configuration type used for PUSCH
* N_RB number of RBs scheduled for PUSCH
* k_RE_ref the parameter k_RE_ref
* start_sc first subcarrier index
-* ofdm_symbol_size FFT size
+* ofdm_symbol_size number of samples in an OFDM symbol
*
* RETURN : 1 if subcarrier k is PTRS, or 0 otherwise
*
@@ -246,107 +154,48 @@ uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs) {
*
*********************************************************************/
-uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size) {
-
- uint16_t k_RB_ref, i, sc;
-
- i = 0;
- sc = 0;
- k_RB_ref = 0;
-
- if (N_RB % K_ptrs == 0)
- k_RB_ref = n_rnti % K_ptrs;
- else
- k_RB_ref = n_rnti % (N_RB % K_ptrs);
-
- while (k > sc){
-
- sc = (start_sc + k_RE_ref + (i*K_ptrs + k_RB_ref)*NR_NB_SC_PER_RB)%ofdm_symbol_size;
- i++;
-
- }
-
- if (k == sc)
- return 1;
- else
- return 0;
-
-}
-
-/*******************************************************************
-*
-* NAME : is_ptrs_symbol
-*
-* PARAMETERS : l ofdm symbol index within slot
-* k subcarrier index
-* n_rnti UE CRNTI
-* N_RB number of RBs scheduled for PUSCH
-* duration_in_symbols number of scheduled PUSCH ofdm symbols
-* dmrs_antenna_port DMRS antenna port
-* K_ptrs the parameter K_ptrs
-* ptrs_symbols bit mask of ptrs
-* start_sc first subcarrier index
-* ofdm_symbol_size FFT size
-* pusch_dmrs_type PUSCH DMRS type (1 or 2)
-* ptrs_UplinkConfig PTRS uplink configuration
-*
-* RETURN : 0 if symbol(k,l) is data, or 1 if symbol(k,l) is ptrs
-*
-* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH
-*
-*********************************************************************/
-
-uint8_t is_ptrs_symbol(uint8_t l,
- uint16_t k,
- uint16_t n_rnti,
- uint16_t N_RB,
- uint8_t duration_in_symbols,
- uint8_t dmrs_antenna_port,
- uint8_t K_ptrs,
- uint16_t ptrs_symbols,
- uint16_t start_sc,
- uint16_t ofdm_symbol_size,
- pusch_dmrs_type_t pusch_dmrs_type,
- uint8_t resourceElementOffset) {
-
- uint8_t is_ptrs_freq, is_ptrs_time;
- int16_t k_RE_ref;
-
- is_ptrs_freq = 0;
- is_ptrs_time = 0;
-
- k_RE_ref = get_kRE_ref(dmrs_antenna_port, pusch_dmrs_type, resourceElementOffset);
-
- is_ptrs_freq = is_ptrs_subcarrier(k, K_ptrs, n_rnti, N_RB, k_RE_ref, start_sc, ofdm_symbol_size);
+uint8_t is_ptrs_subcarrier(uint16_t k,
+ uint16_t n_rnti,
+ uint8_t dmrs_antenna_port,
+ uint8_t pusch_dmrs_type,
+ uint8_t K_ptrs,
+ uint16_t N_RB,
+ uint8_t k_RE_ref,
+ uint16_t start_sc,
+ uint16_t ofdm_symbol_size)
+{
+ // int16_t k_RE_ref = get_kRE_ref(dmrs_antenna_port, pusch_dmrs_type, resourceElementOffset);
+ uint16_t k_RB_ref;
- if (is_ptrs_freq == 0)
- return 0;
+ if (N_RB % K_ptrs == 0)
+ k_RB_ref = n_rnti % K_ptrs;
+ else
+ k_RB_ref = n_rnti % (N_RB % K_ptrs);
- if (((ptrs_symbols>>l)&1) == 1)
- is_ptrs_time = 1;
+ if (k < start_sc)
+ k += ofdm_symbol_size;
- if (is_ptrs_time && is_ptrs_freq)
+ if ((k - k_RE_ref - k_RB_ref*NR_NB_SC_PER_RB - start_sc) % (K_ptrs*NR_NB_SC_PER_RB) == 0)
return 1;
- else
- return 0;
+ return 0;
}
/*
int main(int argc, char const *argv[])
{
- dmrs_UplinkConfig_t dmrs_Uplink_Config;
- ptrs_UplinkConfig_t ptrs_Uplink_Config;
- uint8_t resourceElementOffset;
- uint8_t dmrs_antenna_port;
- uint8_t L_ptrs, K_ptrs;
- int16_t k_RE_ref;
- uint16_t N_RB, ptrs_symbols, ofdm_symbol_size, k;
- uint8_t duration_in_symbols, I_mcs;
- uint8_t start_symbol, l;
- uint8_t ptrs_symbol_flag;
- uint16_t n_rnti;
+ dmrs_UplinkConfig_t dmrs_Uplink_Config;
+ ptrs_UplinkConfig_t ptrs_Uplink_Config;
+ uint8_t resourceElementOffset;
+ uint8_t dmrs_antenna_port;
+ uint8_t L_ptrs, K_ptrs;
+ int16_t k_RE_ref;
+ uint16_t N_RB, ptrs_symbols, ofdm_symbol_size, k;
+ uint8_t duration_in_symbols, I_mcs;
+ uint8_t start_symbol, l;
+ uint8_t ptrs_symbol_flag;
+ uint16_t n_rnti;
dmrs_Uplink_Config.pusch_dmrs_type = pusch_dmrs_type1;
dmrs_Uplink_Config.pusch_dmrs_AdditionalPosition = pusch_dmrs_pos1;
@@ -362,13 +211,13 @@ int main(int argc, char const *argv[])
n_rnti = 0x1234;
resourceElementOffset = 0;
ptrs_symbols = 0;
- dmrs_antenna_port = 0;
- N_RB = 50;
- duration_in_symbols = 14;
- ofdm_symbol_size = 2048;
- I_mcs = 9;
- start_symbol = 0;
- ptrs_symbol_flag = 0;
+ dmrs_antenna_port = 0;
+ N_RB = 50;
+ duration_in_symbols = 14;
+ ofdm_symbol_size = 2048;
+ I_mcs = 9;
+ start_symbol = 0;
+ ptrs_symbol_flag = 0;
k_RE_ref = get_kRE_ref(dmrs_antenna_port, dmrs_Uplink_Config.pusch_dmrs_type, resourceElementOffset);
@@ -418,6 +267,6 @@ int main(int argc, char const *argv[])
printf("\n");
- return 0;
+ return 0;
}
*/
diff --git a/openair1/PHY/NR_REFSIG/ptrs_nr.h b/openair1/PHY/NR_REFSIG/ptrs_nr.h
index 291ff4a55585137647ac947c16fd2c7434fb376e..e8a4e61232278c63ef559e36dadb82c94c020316 100644
--- a/openair1/PHY/NR_REFSIG/ptrs_nr.h
+++ b/openair1/PHY/NR_REFSIG/ptrs_nr.h
@@ -49,32 +49,36 @@
int16_t get_kRE_ref(uint8_t dmrs_antenna_port, uint8_t pusch_dmrs_type, uint8_t resourceElementOffset);
-uint8_t get_K_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint16_t N_RB);
-
void set_ptrs_symb_idx(uint16_t *ptrs_symbols,
uint8_t duration_in_symbols,
uint8_t start_symbol,
- uint8_t dmrs_type,
uint8_t L_ptrs,
- uint8_t pusch_maxLength,
- uint16_t ofdm_symbol_size);
-
-uint8_t get_L_ptrs(ptrs_UplinkConfig_t *ptrs_UplinkConfig, uint8_t I_mcs);
-
-uint8_t is_ptrs_subcarrier(uint16_t k, uint8_t K_ptrs, uint16_t n_rnti, uint16_t N_RB, int16_t k_RE_ref, uint16_t start_sc, uint16_t ofdm_symbol_size);
+ uint16_t ul_dmrs_symb_pos);
+
+uint8_t is_ptrs_subcarrier(uint16_t k,
+ uint16_t n_rnti,
+ uint8_t dmrs_antenna_port,
+ uint8_t pusch_dmrs_type,
+ uint8_t K_ptrs,
+ uint16_t N_RB,
+ uint8_t k_RE_ref,
+ uint16_t start_sc,
+ uint16_t ofdm_symbol_size);
+
+/*******************************************************************
+*
+* NAME : is_ptrs_symbol
+*
+* PARAMETERS : l ofdm symbol index within slot
+* ptrs_symbols bit mask of ptrs
+*
+* RETURN : 1 if symbol is ptrs, or 0 otherwise
+*
+* DESCRIPTION : 3GPP TS 38.211 6.4.1.2 Phase-tracking reference signal for PUSCH
+*
+*********************************************************************/
-uint8_t is_ptrs_symbol(uint8_t l,
- uint16_t k,
- uint16_t n_rnti,
- uint16_t N_RB,
- uint8_t duration_in_symbols,
- uint8_t dmrs_antenna_port,
- uint8_t K_ptrs,
- uint16_t ptrs_symbols,
- uint16_t start_sc,
- uint16_t ofdm_symbol_size,
- pusch_dmrs_type_t pusch_dmrs_type,
- uint8_t resourceElementOffset);
+static inline uint8_t is_ptrs_symbol(uint8_t l, uint16_t ptrs_symbols) { return ((ptrs_symbols >> l) & 1); }
diff --git a/openair1/PHY/NR_REFSIG/scrambling_luts.c b/openair1/PHY/NR_REFSIG/scrambling_luts.c
new file mode 100644
index 0000000000000000000000000000000000000000..790d3f771966262ebc8f08287a5ed2cefd427038
--- /dev/null
+++ b/openair1/PHY/NR_REFSIG/scrambling_luts.c
@@ -0,0 +1,63 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/* Lookup tables for 3GPP scrambling/unscrambling */
+
+/* Author R. Knopp / EURECOM / OpenAirInterface.org */
+#ifndef __SCRAMBLING_LUTS__C__
+#define __SCRAMBLING_LUTS__C__
+
+#include "PHY/impl_defs_nr.h"
+#include "PHY/sse_intrin.h"
+#include <common/utils/LOG/log.h>
+
+__m64 byte2m64_re[256];
+__m64 byte2m64_im[256];
+
+void init_byte2m64(void) {
+
+ for (int s=0;s<256;s++) {
+ byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*(s&1)),0);
+ byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>1)&1)),0);
+ byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*((s>>2)&1)),1);
+ byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>3)&1)),1);
+ byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*((s>>4)&1)),2);
+ byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>5)&1)),2);
+ byte2m64_re[s] = _mm_insert_pi16(byte2m64_re[s],(1-2*((s>>6)&1)),3);
+ byte2m64_im[s] = _mm_insert_pi16(byte2m64_im[s],(1-2*((s>>7)&1)),3);
+ LOG_T(PHY,"init_scrambling_luts: s %x (%d) ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ ((uint16_t*)&s)[0],
+ (1-2*(s&1)),
+ ((int16_t*)&byte2m64_re[s])[0],((int16_t*)&byte2m64_im[s])[0],
+ ((int16_t*)&byte2m64_re[s])[1],((int16_t*)&byte2m64_im[s])[1],
+ ((int16_t*)&byte2m64_re[s])[2],((int16_t*)&byte2m64_im[s])[2],
+ ((int16_t*)&byte2m64_re[s])[3],((int16_t*)&byte2m64_im[s])[3]);
+
+ }
+}
+
+void init_scrambling_luts(void) {
+
+ init_byte2m64();
+
+}
+
+#endif
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci.c b/openair1/PHY/NR_TRANSPORT/nr_dci.c
index d62687bd9c42afc220f790d348ba7fd4158eb203..3a44ebc49a0c589ef13d1c45b3ea95c7b6bca970 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci.c
@@ -131,12 +131,13 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format,
void nr_pdcch_scrambling(uint32_t *in,
uint32_t size,
uint32_t Nid,
- uint32_t n_RNTI,
+ uint32_t scrambling_RNTI,
uint32_t *out) {
uint8_t reset;
uint32_t x1, x2, s=0;
reset = 1;
- x2 = (n_RNTI<<16) + Nid;
+ x2 = (scrambling_RNTI<<16) + Nid;
+ LOG_D(PHY,"PDCCH Scrambling x2 %x : scrambling_RNTI %x \n", x2, scrambling_RNTI);
for (int i=0; i<size; i++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
@@ -154,13 +155,13 @@ void nr_pdcch_scrambling(uint32_t *in,
uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
- nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu,
+ nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu,
uint32_t **gold_pdcch_dmrs,
int32_t *txdataF,
int16_t amp,
NR_DL_FRAME_PARMS frame_parms) {
- int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1]; // 3 for the max coreset duration
+ int16_t mod_dmrs[NR_MAX_CSET_DURATION][NR_MAX_PDCCH_DMRS_LENGTH>>1] __attribute__((aligned(16))); // 3 for the max coreset duration
uint16_t cset_start_sc;
uint8_t cset_start_symb, cset_nsymb;
int k,l,k_prime,dci_idx, dmrs_idx;
@@ -206,8 +207,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED,
"Interleaved CCE REG MAPPING not supported\n");
uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
- (n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
- uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
+ (n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
+ uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
@@ -228,18 +229,20 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
/// DCI payload processing
// CRC attachment + Scrambling + Channel coding + Rate matching
uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
- uint16_t n_RNTI = pdcch_pdu_rel15->RNTI[d];
- uint16_t Nid = pdcch_pdu_rel15->ScramblingId[d];
-
+
+ uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d];
+ uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d];
+ uint16_t scrambling_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[d];
+
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE,
- pdcch_pdu_rel15->PayloadSizeBits[d],
- pdcch_pdu_rel15->AggregationLevel[d],
+ pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],
+ pdcch_pdu_rel15->dci_pdu.AggregationLevel[d],
0,NULL);
- polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr);
+ polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], (void*)encoder_output, n_RNTI,1,currentPtr);
#ifdef DEBUG_CHANNEL_CODING
- printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]);
+ printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]);
printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
- ((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]);
+ ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1]);
printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
for (int i=0; i<encoded_length>>5; i++)
@@ -249,7 +252,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
#endif
/// Scrambling
uint32_t scrambled_output[NR_MAX_DCI_SIZE_DWORD]= {0};
- nr_pdcch_scrambling(encoder_output, encoded_length, Nid, n_RNTI, scrambled_output);
+ nr_pdcch_scrambling(encoder_output, encoded_length, Nid, scrambling_RNTI, scrambled_output);
#ifdef DEBUG_CHANNEL_CODING
printf("scrambled output: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\t [4]->0x%08x\t [5]->0x%08x\t \
[6]->0x%08x \t [7]->0x%08x \t [8]->0x%08x \t [9]->0x%08x\t [10]->0x%08x\t [11]->0x%08x\n",
@@ -257,7 +260,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
scrambled_output[6], scrambled_output[7], scrambled_output[8], scrambled_output[9], scrambled_output[10],scrambled_output[11] );
#endif
/// QPSK modulation
- int16_t mod_dci[NR_MAX_DCI_SIZE>>1];
+ int16_t mod_dci[NR_MAX_DCI_SIZE>>1] __attribute__((aligned(16)));
nr_modulation(scrambled_output, encoded_length, DMRS_MOD_ORDER, mod_dci); //Qm = 2 as DMRS is QPSK modulated
#ifdef DEBUG_DCI
@@ -272,8 +275,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
cset_start_sc -= frame_parms.ofdm_symbol_size;
/*Reorder REG list for a freq first mapping*/
- uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE;
- uint8_t reg_idx0 = pdcch_pdu_rel15->CceIndex[d]*NR_NB_REG_PER_CCE;
+ uint8_t reg_idx0 = pdcch_pdu_rel15->dci_pdu.CceIndex[d]*NR_NB_REG_PER_CCE;
+ uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE;
/*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) {
@@ -295,8 +298,8 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
for (int m=0; m<NR_NB_SC_PER_RB; m++) {
if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
- ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
- ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
+ ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
+ ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS
printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
index c7b14571b7d14f5d846eca804ee3418134e4454a..02ecfc44044fa5bb09a58f6bc2edff4fea11419f 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
@@ -140,7 +140,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) {
int C=-1;
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
- int L = pdcch_pdu_rel15->AggregationLevel[d];
+ int L = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d];
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
@@ -151,10 +151,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m) {
C = N_reg/(bsize*R);
}
- LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->CceIndex[d]);
+ LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu.CceIndex[d]);
for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
cce = &gNB->cce_list[d][cce_idx];
- cce->cce_idx = pdcch_pdu_rel15->CceIndex[d] + cce_idx;
+ cce->cce_idx = pdcch_pdu_rel15->dci_pdu.CceIndex[d] + cce_idx;
LOG_D(PHY, "cce_idx %d\n", cce->cce_idx);
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
@@ -210,17 +210,17 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
- //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i];
+ //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i];
-
- int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->RNTI[i],gNB,SEARCH_EXIST_OR_FREE);
+ int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE);
if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){
- LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->RNTI[i],dlsch_id);
+ LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id);
return;
}
dlsch = gNB->dlsch[dlsch_id][0];
- int harq_pid = 0;//extract_harq_pid(i,pdu_rel15);
+ int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value);
+ int harq_pid = slot % num_slots_tdd;
dlsch->slot_tx[slot] = 1;
dlsch->harq_ids[frame%2][slot] = harq_pid;
@@ -228,7 +228,7 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
"illegal harq_pid %d\n",harq_pid);
dlsch->harq_mask |= (1<<harq_pid);
- dlsch->rnti = pdcch_pdu_rel15->RNTI[i];
+ dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i];
nr_fill_cce_list(gNB,0);
/*
@@ -248,7 +248,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
- //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->Payload[i];
+ //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i];
// if there's no DL DCI then generate CCE list
if (gNB->pdcch_pdu) nr_fill_cce_list(gNB,0);
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
index 4518280f6b560ea0e686cc528bed38a684e45301..2849986833b2311bbc7ffe7d21e45dc145597120 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.c
@@ -34,6 +34,8 @@
#include "nr_dci.h"
#include "nr_sch_dmrs.h"
#include "PHY/MODULATION/nr_modulation.h"
+#include "PHY/NR_REFSIG/dmrs_nr.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
//#define DEBUG_DLSCH
//#define DEBUG_DLSCH_MAPPING
@@ -47,7 +49,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in,
uint8_t reset, b_idx;
uint32_t x1, x2, s=0;
-
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, 1);
reset = 1;
x2 = (n_RNTI<<15) + (q<<14) + Nid;
@@ -62,7 +64,7 @@ void nr_pdsch_codeword_scrambling(uint8_t *in,
*out ^= (((in[i])&1) ^ ((s>>b_idx)&1))<<b_idx;
//printf("i %d b_idx %d in %d s 0x%08x out 0x%08x\n", i, b_idx, in[i], s, *out);
}
-
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_CODEWORD_SCRAMBLING, 0);
}
void nr_pdsch_codeword_scrambling_optim(uint8_t *in,
@@ -126,22 +128,29 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats) {
- int harq_pid = 0;
+ int harq_pid = dlsch->harq_ids[frame%2][slot];
NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15;
uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5];
int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs;
int16_t **tx_layers = (int16_t**)dlsch->txdataF;
int8_t Wf[2], Wt[2], l0, l_prime[2], delta;
-
uint8_t dmrs_Type = rel15->dmrsConfigType;
- int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4;
- uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1;
- int16_t mod_dmrs[n_dmrs<<1];
-
- uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords;
+ int nb_re_dmrs;
+ uint16_t n_dmrs;
+ if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1) {
+ nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData;
+ n_dmrs = ((rel15->rbSize+rel15->rbStart)*6)<<1;
+ }
+ else {
+ nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData;
+ n_dmrs = ((rel15->rbSize+rel15->rbStart)*4)<<1;
+ }
+ uint16_t nb_re;
+ nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords;
uint8_t Qm = rel15->qamModOrder[0];
uint32_t encoded_length = nb_re*Qm;
+ int16_t mod_dmrs[n_dmrs<<1] __attribute__ ((aligned(16)));
/// CRC, coding, interleaving and rate matching
AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n");
@@ -193,11 +202,13 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
/// Modulation
start_meas(dlsch_modulation_stats);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 1);
for (int q=0; q<rel15->NrOfCodewords; q++)
nr_modulation(scrambled_output[q],
encoded_length,
Qm,
mod_symbs[q]);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_PDSCH_MODULATION, 0);
stop_meas(dlsch_modulation_stats);
#ifdef DEBUG_DLSCH
printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_re);
@@ -297,15 +308,16 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
}
else {
-
- ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15;
- ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15;
+ if( (l != dmrs_symbol) || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,rel15->numDmrsCdmGrpsNoData,dmrs_Type)) {
+ ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)] = (amp * tx_layers[ap][m<<1]) >> 15;
+ ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)] = (amp * tx_layers[ap][(m<<1) + 1]) >> 15;
#ifdef DEBUG_DLSCH_MAPPING
- printf("m %d\t l %d \t k %d \t txdataF: %d %d\n",
-m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)],
- ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]);
+ printf("m %d\t l %d \t k %d \t txdataF: %d %d\n",
+ m, l, k, ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + (2*txdataF_offset)],
+ ((int16_t*)txdataF[ap])[((l*frame_parms->ofdm_symbol_size + k)<<1) + 1 + (2*txdataF_offset)]);
#endif
- m++;
+ m++;
+ }
}
if (++k >= frame_parms->ofdm_symbol_size)
k -= frame_parms->ofdm_symbol_size;
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
index f48905b68cbfdb12dea65554ee6aa87aff2a7e89..3a6851ee8fa69dad1e9b451ec616e5b3d212ef4c 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch.h
@@ -90,7 +90,7 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
-void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB);
+void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB);
void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch);
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
index 856a7863f435de682b7c237bb7c04ac720415e8d..52377ac9453292efb508403bcceb2169117a915e 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
@@ -36,7 +36,7 @@
#include "PHY/CODING/coding_defs.h"
#include "PHY/CODING/lte_interleaver_inline.h"
#include "PHY/CODING/nrLDPC_extern.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
@@ -49,7 +49,7 @@
//#define DEBUG_DLSCH_FREE 1
-void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB)
+void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr, uint16_t N_RB)
{
int i;
int r;
@@ -64,7 +64,6 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB)
a_segments = a_segments/273;
}
- uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment
#ifdef DEBUG_DLSCH_FREE
@@ -82,7 +81,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB)
#endif
if (dlsch->harq_processes[i]->b) {
- free16(dlsch->harq_processes[i]->b,dlsch_bytes);
+ free16(dlsch->harq_processes[i]->b,a_segments*1056);
dlsch->harq_processes[i]->b = NULL;
#ifdef DEBUG_DLSCH_FREE
LOG_D(PHY,"Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b);
@@ -131,7 +130,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t **dlschptr,uint16_t N_RB)
}
free16(dlsch,sizeof(NR_gNB_DLSCH_t));
- dlsch = NULL;
+ *dlschptr = NULL;
}
}
@@ -151,7 +150,7 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms,
if (N_RB != 273) {
a_segments = a_segments*N_RB;
- a_segments = a_segments/273;
+ a_segments = (a_segments + 272) / 273;
}
uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment
@@ -336,13 +335,19 @@ int nr_dlsch_encoding(unsigned char *a,
uint32_t E;
uint8_t Ilbrm = 1;
uint32_t Tbslbrm = 950984; //max tbs
- uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4;
+ uint8_t nb_re_dmrs;
+
+ if (rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1)
+ nb_re_dmrs = 6*rel15->numDmrsCdmGrpsNoData;
+ else
+ nb_re_dmrs = 4*rel15->numDmrsCdmGrpsNoData;
+
uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos);
uint16_t R=rel15->targetCodeRate[0];
float Coderate = 0.0;
uint8_t Nl = 4;
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_IN);
A = rel15->TBSize[0]<<3;
@@ -460,6 +465,9 @@ int nr_dlsch_encoding(unsigned char *a,
}
+ F = dlsch->harq_processes[harq_pid]->F;
+
+ Kr = dlsch->harq_processes[harq_pid]->K;
for (r=0; r<dlsch->harq_processes[harq_pid]->C; r++) {
if (F>0) {
@@ -531,7 +539,7 @@ int nr_dlsch_encoding(unsigned char *a,
r_offset += E;
}
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_OUT);
return 0;
}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c
index 2e6fc707bdc0e6c051e0c3a71bec7a9dc87a37bb..7702d770ee63be176e31f8d5ace7d08c742e124d 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_dlsch_tools.c
@@ -274,25 +274,7 @@ int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) {
return first_free_index;
}
-int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) {
- uint16_t i;
- int16_t first_free_index=-1;
-
- AssertFatal(gNB!=NULL,"gNB is null\n");
- for (i=0; i<NUMBER_OF_NR_ULSCH_MAX; i++) {
- AssertFatal(gNB->ulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i);
- AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i);
- LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index);
- if ((gNB->ulsch[i][0]->harq_mask >0) &&
- (gNB->ulsch[i][0]->rnti==rnti)) return i;
- else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
- }
- if (type == SEARCH_EXIST) return -1;
- if (first_free_index != -1)
- gNB->ulsch[first_free_index][0]->rnti = 0;
- return first_free_index;
-}
void nr_fill_dlsch(PHY_VARS_gNB *gNB,
int frame,
@@ -316,26 +298,3 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB,
}
-void nr_fill_ulsch(PHY_VARS_gNB *gNB,
- int frame,
- int slot,
- nfapi_nr_pusch_pdu_t *ulsch_pdu) {
-
-
- int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE);
- AssertFatal( (ulsch_id>=0) && (ulsch_id<NUMBER_OF_NR_ULSCH_MAX),
- "illegal or no ulsch_id found!!! rnti %04x ulsch_id %d\n",ulsch_pdu->rnti,ulsch_id);
-
- NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0];
- int harq_pid = ulsch_pdu->pusch_data.harq_process_id;
- ulsch->rnti = ulsch_pdu->rnti;
- //ulsch->rnti_type;
- ulsch->harq_mask |= 1<<harq_pid;
- ulsch->harq_process_id[slot] = harq_pid;
-
- memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t));
-
- LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid);
-
-}
-
diff --git a/openair1/PHY/NR_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_TRANSPORT/nr_pbch.c
index b6a4787193e559a1672aead2634209e351c23d66..bd1278b2eb192e82bba8f817e17716effaed7101 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_pbch.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_pbch.c
@@ -32,7 +32,7 @@
*/
#include "PHY/defs_gNB.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/LTE_REFSIG/lte_refsig.h"
#include "PHY/sse_intrin.h"
@@ -40,7 +40,7 @@
//#define DEBUG_PBCH_ENCODING
//#define DEBUG_PBCH_DMRS
-extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
+extern short nr_qpsk_mod_table[8];
uint8_t nr_pbch_payload_interleaving_pattern[32] = {16, 23, 18, 17, 8, 30, 10, 6, 24, 7, 0, 5, 3, 2, 1, 4,
9, 11, 12, 13, 14, 15, 19, 20, 21, 22, 25, 26, 27, 28, 29, 31
@@ -61,9 +61,9 @@ int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs,
/// QPSK modulation
for (int m=0; m<NR_PBCH_DMRS_LENGTH; m++) {
- idx = ((((gold_pbch_dmrs[(m<<1)>>5])>>((m<<1)&0x1f))&1)<<1) ^ (((gold_pbch_dmrs[((m<<1)+1)>>5])>>(((m<<1)+1)&0x1f))&1);
- mod_dmrs[m<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
- mod_dmrs[(m<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1) + 1];
+ idx = (((gold_pbch_dmrs[(m<<1)>>5])>>((m<<1)&0x1f))&3);
+ mod_dmrs[m<<1] = nr_qpsk_mod_table[idx<<1];
+ mod_dmrs[(m<<1)+1] = nr_qpsk_mod_table[(idx<<1) + 1];
#ifdef DEBUG_PBCH_DMRS
printf("m %d idx %d gold seq %d b0-b1 %d-%d mod_dmrs %d %d\n", m, idx, gold_pbch_dmrs[(m<<1)>>5], (((gold_pbch_dmrs[(m<<1)>>5])>>((m<<1)&0x1f))&1),
(((gold_pbch_dmrs[((m<<1)+1)>>5])>>(((m<<1)+1)&0x1f))&1), mod_dmrs[(m<<1)], mod_dmrs[(m<<1)+1]);
@@ -297,7 +297,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch,
a_reversed |= (((uint64_t)pbch->pbch_a_prime>>i)&1)<<(31-i);
/// CRC, coding and rate matching
- polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0,
+ polar_encoder_fast (&a_reversed, (void*)pbch->pbch_e, 0, 0,
nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL)
);
#ifdef DEBUG_PBCH_ENCODING
@@ -323,9 +323,9 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch,
/// QPSK modulation
for (int i=0; i<NR_POLAR_PBCH_E>>1; i++) {
- idx = (((pbch->pbch_e[(i<<1)>>5]>>((i<<1)&0x1f))&1)<<1) ^ ((pbch->pbch_e[((i<<1)+1)>>5]>>(((i<<1)+1)&0x1f))&1);
- mod_pbch_e[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
- mod_pbch_e[(i<<1)+1] = nr_mod_table[((NR_MOD_TABLE_QPSK_OFFSET + idx)<<1)+1];
+ idx = ((pbch->pbch_e[(i<<1)>>5]>>((i<<1)&0x1f))&3);
+ mod_pbch_e[i<<1] = nr_qpsk_mod_table[idx<<1];
+ mod_pbch_e[(i<<1)+1] = nr_qpsk_mod_table[(idx<<1)+1];
#ifdef DEBUG_PBCH
printf("i %d idx %d mod_pbch %d %d\n", i, idx, mod_pbch_e[2*i], mod_pbch_e[2*i+1]);
#endif
diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.c b/openair1/PHY/NR_TRANSPORT/nr_prach.c
index 7ab553fe6bcdff35a0cc326e2ee64de2f4951e7e..e263c2c2ccea2dfa297659a822320751c0dbfca7 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_prach.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_prach.c
@@ -31,141 +31,246 @@
*/
#include "PHY/defs_gNB.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
-#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h"
-
-extern uint16_t NCS_unrestricted_delta_f_RA_125[16];
-extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15];
-extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13];
-extern uint16_t NCS_unrestricted_delta_f_RA_5[16];
-extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16];
-extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14];
-extern uint16_t NCS_unrestricted_delta_f_RA_15[16];
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
+
extern uint16_t prach_root_sequence_map_0_3[838];
extern uint16_t prach_root_sequence_map_abc[138];
-extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9];
-extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9];
-extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10];
extern uint16_t nr_du[838];
-extern int16_t nr_ru[2*839];
+extern const char *prachfmt[9];
-void rx_nr_prach_ru(RU_t *ru,
- int frame,
- int subframe) {
+void init_prach_list(PHY_VARS_gNB *gNB) {
- AssertFatal(ru!=NULL,"ru is null\n");
+ AssertFatal(gNB!=NULL,"gNB is null\n");
+ for (int i=0; i<NUMBER_OF_NR_PRACH_MAX; i++) gNB->prach_vars.list[i].frame=-1;
+}
- int16_t **rxsigF=NULL;
- NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms;
- int16_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
- int16_t *prach[ru->nb_rx];
- uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range);
+int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type) {
- rxsigF = ru->prach_rxsigF;
+ uint16_t i;
+ int16_t first_free_index=-1;
- AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n");
- for (int aa=0; aa<ru->nb_rx; aa++)
- prach[aa] = (int16_t*)&ru->common.rxdata[aa][(subframe*fp->samples_per_subframe)-ru->N_TA_offset];
-
+ AssertFatal(gNB!=NULL,"gNB is null\n");
+ for (i=0; i<NUMBER_OF_NR_PRACH_MAX; i++) {
+ LOG_D(PHY,"searching for PRACH in %d.%d with numRA %d: prach_index %d=> %d.%d numRA %d\n", frame,slot,numRA,i,
+ gNB->prach_vars.list[i].frame,gNB->prach_vars.list[i].slot,gNB->prach_vars.list[i].pdu.num_ra);
+ if ((gNB->prach_vars.list[i].frame == frame) &&
+ (gNB->prach_vars.list[i].slot == slot) &&
+ (gNB->prach_vars.list[i].pdu.num_ra == numRA)) return i;
+ else if ((gNB->prach_vars.list[i].frame == -1) && (first_free_index==-1)) first_free_index=i;
+ }
+ if (type == SEARCH_EXIST) return -1;
+ return first_free_index;
+}
- int mu = fp->numerology_index;
- int Ncp;
- int16_t *prach2;
+void nr_fill_prach(PHY_VARS_gNB *gNB,
+ int SFN,
+ int Slot,
+ nfapi_nr_prach_pdu_t *prach_pdu) {
+ int prach_id = find_nr_prach(gNB,SFN,Slot,prach_pdu->num_ra,SEARCH_EXIST_OR_FREE);
+ AssertFatal( (prach_id>=0) && (prach_id<NUMBER_OF_NR_PRACH_MAX),
+ "illegal or no prach_id found!!! numRA %d prach_id %d\n",prach_pdu->num_ra,prach_id);
- switch (prach_fmt) {
- case 0:
- Ncp = 3168;
- break;
+ gNB->prach_vars.list[prach_id].frame=SFN;
+ gNB->prach_vars.list[prach_id].slot=Slot;
+ memcpy((void*)&gNB->prach_vars.list[prach_id].pdu,(void*)prach_pdu,sizeof(*prach_pdu));
- case 1:
- Ncp = 21024;
- break;
+}
- case 2:
- Ncp = 4688;
- break;
+void init_prach_ru_list(RU_t *ru) {
- case 3:
- Ncp = 3168;
- break;
+ AssertFatal(ru!=NULL,"ruis null\n");
+ for (int i=0; i<NUMBER_OF_NR_RU_PRACH_MAX; i++) ru->prach_list[i].frame=-1;
+ pthread_mutex_init(&ru->prach_list_mutex,NULL);
+}
- case 0xa1:
- Ncp = 288/(1<<mu);
- break;
+int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type) {
- case 0xa2:
- Ncp = 576/(1<<mu);
- break;
+ uint16_t i;
+ int16_t first_free_index=-1;
- case 0xa3:
- Ncp = 864/(1<<mu);
- break;
+ AssertFatal(ru!=NULL,"ru is null\n");
+ pthread_mutex_lock(&ru->prach_list_mutex);
+ for (i=0; i<NUMBER_OF_NR_RU_PRACH_MAX; i++) {
+ LOG_D(PHY,"searching for PRACH in %d.%d : prach_index %d=> %d.%d\n", frame,slot,i,
+ ru->prach_list[i].frame,ru->prach_list[i].slot);
+ if ((ru->prach_list[i].frame == frame) &&
+ (ru->prach_list[i].slot == slot)) {
+ pthread_mutex_unlock(&ru->prach_list_mutex);
+ return i;
+ }
+ else if ((ru->prach_list[i].frame == -1) && (first_free_index==-1)) first_free_index=i;
+ }
+ pthread_mutex_unlock(&ru->prach_list_mutex);
+ if (type == SEARCH_EXIST) return -1;
- case 0xb1:
- Ncp = 216/(1<<mu);
- break;
+ return first_free_index;
+}
- case 0xb2:
- Ncp = 360/(1<<mu);
- break;
+void nr_fill_prach_ru(RU_t *ru,
+ int SFN,
+ int Slot,
+ nfapi_nr_prach_pdu_t *prach_pdu) {
- case 0xb3:
- Ncp = 504/(1<<mu);
- break;
+ int prach_id = find_nr_prach_ru(ru,SFN,Slot,SEARCH_EXIST_OR_FREE);
+ AssertFatal( (prach_id>=0) && (prach_id<NUMBER_OF_NR_PRACH_MAX),
+ "illegal or no prach_id found!!! prach_id %d\n",prach_id);
- case 0xb4:
- Ncp = 936/(1<<mu);
- break;
+ pthread_mutex_lock(&ru->prach_list_mutex);
+ ru->prach_list[prach_id].frame = SFN;
+ ru->prach_list[prach_id].slot = Slot;
+ ru->prach_list[prach_id].fmt = prach_pdu->prach_format;
+ ru->prach_list[prach_id].numRA = prach_pdu->num_ra;
+ ru->prach_list[prach_id].prachStartSymbol = prach_pdu->prach_start_symbol;
+ pthread_mutex_unlock(&ru->prach_list_mutex);
- case 0xc0:
- Ncp = 1240/(1<<mu);
- break;
+}
+
+void free_nr_ru_prach_entry(RU_t *ru,
+ int prach_id) {
+
+ pthread_mutex_lock(&ru->prach_list_mutex);
+ ru->prach_list[prach_id].frame=-1;
+ pthread_mutex_unlock(&ru->prach_list_mutex);
+
+}
- case 0xc2:
- Ncp = 2048/(1<<mu);
- break;
- default:
- AssertFatal(1==0,"unknown prach format %x\n",prach_fmt);
+void rx_nr_prach_ru(RU_t *ru,
+ int prachFormat,
+ int numRA,
+ int prachStartSymbol,
+ int frame,
+ int slot) {
+
+ AssertFatal(ru!=NULL,"ru is null\n");
+
+ int16_t **rxsigF=NULL;
+ NR_DL_FRAME_PARMS *fp=ru->nr_frame_parms;
+ int slot2=slot;
+
+ int16_t *prach[ru->nb_rx];
+ int prach_sequence_length = ru->config.prach_config.prach_sequence_length.value;
+
+ int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[numRA].k1.value;
+
+ rxsigF = ru->prach_rxsigF;
+
+ AssertFatal(ru->if_south == LOCAL_RF,"we shouldn't call this if if_south != LOCAL_RF\n");
+
+ for (int aa=0; aa<ru->nb_rx; aa++){
+ if (prach_sequence_length == 0) slot2=(slot/fp->slots_per_subframe)*fp->slots_per_subframe;
+ prach[aa] = (int16_t*)&ru->common.rxdata[aa][(slot2*fp->get_samples_per_slot(slot,fp))-ru->N_TA_offset];
+ }
+
+ int dftlen=0;
+ int mu = fp->numerology_index;
+ int Ncp = 0;
+ int16_t *prach2;
+
+ if (prach_sequence_length == 0) {
+ LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %d, msg1_frequencyStart %d\n",
+ ru->idx,frame,slot2,prachFormat,msg1_frequencystart);
+ AssertFatal(prachFormat<4,"Illegal prach format %d for length 839\n",prachFormat);
+ switch (prachFormat) {
+ case 0:
+ Ncp = 3168;
+ break;
+
+ case 1:
+ Ncp = 21024;
+ break;
+
+ case 2:
+ Ncp = 4688;
+ break;
+
+ case 3:
+ Ncp = 3168;
+ break;
+
+ }
+ }
+ else {
+ LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d,startSymbol %d\n",
+ ru->idx,frame,slot,prachfmt[prachFormat],msg1_frequencystart,prachStartSymbol);
+
+ switch (prachFormat) {
+ case 0: //A1
+ Ncp = 288/(1<<mu);
+ break;
+
+ case 1: //A2
+ Ncp = 576/(1<<mu);
+ break;
+
+ case 2: //A3
+ Ncp = 864/(1<<mu);
+ break;
+
+ case 3: //B1
+ Ncp = 216/(1<<mu);
break;
+
+ case 4: //B2
+ Ncp = 360/(1<<mu);
+ break;
+
+ case 5: //B3
+ Ncp = 504/(1<<mu);
+ break;
+
+ case 6: //B4
+ Ncp = 936/(1<<mu);
+ break;
+
+ case 7: //C0
+ Ncp = 1240/(1<<mu);
+ break;
+
+ case 8: //C2
+ Ncp = 2048/(1<<mu);
+ break;
+
+ default:
+ AssertFatal(1==0,"unknown prach format %x\n",prachFormat);
+ break;
+ }
}
-
// Do forward transform
if (LOG_DEBUGFLAG(PRACH)) {
- LOG_D(PHY,"rx_prach: Doing FFT for N_RB_UL %d nb_rx:%d Ncp:%d\n",fp->N_RB_UL, ru->nb_rx, Ncp);
+ LOG_D(PHY,"rx_prach: Doing PRACH FFT for nb_rx:%d Ncp:%d\n",ru->nb_rx, Ncp);
}
AssertFatal(mu==1,"only 30 kHz SCS handled for now\n");
// Note: Assumes PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below
int kbar = 1;
int K = 24;
- if (prach_fmt == 3) {
+ if (prach_sequence_length == 0 && prachFormat == 3) {
K=4;
kbar=10;
}
- else if (prach_fmt > 3) {
+ else if (prach_sequence_length == 1) {
// Note: Assumes that PRACH SCS is same as PUSCH SCS
K=1;
kbar=2;
}
- int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart;
+ int n_ra_prb = msg1_frequencystart;
int k = (12*n_ra_prb) - 6*fp->N_RB_UL;
- int N_ZC = (prach_fmt<4)?839:139;
+ int N_ZC = (prach_sequence_length==0)?839:139;
if (k<0) k+=(fp->ofdm_symbol_size);
k*=K;
k+=kbar;
int reps=1;
- int dftlen=0;
for (int aa=0; aa<ru->nb_rx; aa++) {
AssertFatal(prach[aa]!=NULL,"prach[%d] is null\n",aa);
-
// do DFT
if (fp->N_RB_UL <= 100)
AssertFatal(1==0,"N_RB_UL %d not support for NR PRACH yet\n",fp->N_RB_UL);
@@ -173,175 +278,232 @@ void rx_nr_prach_ru(RU_t *ru,
if (fp->threequarter_fs==0) {
//40 MHz @ 61.44 Ms/s
//50 MHz @ 61.44 Ms/s
- prach2 = prach[aa] + (Ncp<<2);
- if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2)
- dft(DFT_49152,prach2,rxsigF[aa],1);
- if (prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1);
- reps++;
- }
- if (prach_fmt == 2) {
- dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1);
- dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1);
- reps+=2;
- }
- if (prach_fmt == 3) {
- for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1);
- reps=4;
- }
- if (prach_fmt >3) {
- dft(DFT_2048,prach2,rxsigF[aa],1);
- if (prach_fmt != 0xc0) {
- dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1);
+ prach2 = prach[aa] + (Ncp<<2); // Ncp is for 30.72 Ms/s, so multiply by 2 for I/Q, and 2 to bring to 61.44 Ms/s
+ if (prach_sequence_length == 0) {
+ if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
+ dftlen=49152;
+ dft(DFT_49152,prach2,rxsigF[aa],1);
+ }
+ if (prachFormat == 1 || prachFormat == 2) {
+ dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1);
reps++;
}
- }
- if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) {
- dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1);
- dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1);
- reps+=2;
- }
- if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) {
- dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1);
- dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1);
- reps+=2;
- }
- if (prach_fmt == 0xc2) {
- for (int i=6;i<11;i++) dft(DFT_2048,prach2+(3072*i),rxsigF[aa]+(3072*i),1);
- reps+=6;
+ if (prachFormat == 2) {
+ dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1);
+ dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1);
+ reps+=2;
+ }
+ if (prachFormat == 3) {
+ dftlen=12288;
+ for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1);
+ reps=4;
+ }
+ }// 839 sequence
+ else {
+ if ((mu==0 &&
+ (prachStartSymbol == 0 || prachStartSymbol == 7)) ||
+ (mu==1 && prachStartSymbol == 0)) prach2+=64; // 32 samples @ 61.44 Ms/s in first symbol of each half subframe (15/30 kHz only)
+
+ if (mu==0) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==1) {
+ dftlen=2048;
+ dft(DFT_2048,prach2,rxsigF[aa],1);
+ if (prachFormat != 7) { // !=C0
+ dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1);
+ reps++;
+ }
+ if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) {
+ dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1);
+ dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1);
+ reps+=2;
+ }
+ if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) {
+ dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1);
+ dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1);
+ reps+=2;
+ }
+ if (prachFormat == 6) {
+ for (int i=6;i<12;i++) dft(DFT_2048,prach2+(4096*i),rxsigF[aa]+(4096*i),1);
+ reps+=6;
+ }
+ }
+ else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n");
}
- } else {
+ } else { // threequarter sampling
// 40 MHz @ 46.08 Ms/s
- prach2 = prach[aa] + (3*Ncp);
- AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n");
- if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_36864,prach2,rxsigF[aa],1);
- reps++;
- }
- if (prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1);
- reps++;
- }
- if (prach_fmt == 2) {
- dft(DFT_36864,prach2+(98304*2),rxsigF[aa]+(98304*2),1);
- dft(DFT_36864,prach2+(98304*3),rxsigF[aa]+(98304*3),1);
- reps+=2;
- }
- if (prach_fmt == 3) {
- for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1);
- reps=4;
- }
- if (prach_fmt >3) {
- dft(DFT_1536,prach2,rxsigF[aa],1);
- if (prach_fmt != 0xc0) {
- dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1);
+ prach2 = prach[aa] + (3*Ncp); // 46.08 is 1.5 * 30.72, times 2 for I/Q
+ if (prach_sequence_length == 0) {
+ AssertFatal(fp->N_RB_UL <= 107,"cannot do 108..136 PRBs with 3/4 sampling\n");
+ if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
+ dftlen=36864;
+ dft(DFT_36864,prach2,rxsigF[aa],1);
reps++;
}
- }
- if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) {
- dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1);
- dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1);
- reps+=2;
- }
- if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) {
- dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1);
- dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1);
- reps+=2;
- }
- if (prach_fmt == 0xc2) {
- for (int i=6;i<11;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1);
- reps+=6;
- }
- }
- }
+ if (prachFormat == 1 || prachFormat == 2) {
+ dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1);
+ reps++;
+ }
+ if (prachFormat == 2) {
+ dft(DFT_36864,prach2+(73728*2),rxsigF[aa]+(73728*2),1);
+ dft(DFT_36864,prach2+(73728*3),rxsigF[aa]+(73728*3),1);
+ reps+=2;
+ }
+ if (prachFormat == 3) {
+ dftlen=9216;
+ for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1);
+ reps=4;
+ }
+ } else {
+ if ((mu==0 &&
+ (prachStartSymbol == 0 || prachStartSymbol == 7)) ||
+ (mu==1 && prachStartSymbol == 0)) prach2+=48; // 24 samples @ 46.08 Ms/s in first symbol of each half subframe (15/30 kHz only)
+ if (mu==0) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==1) {
+ dftlen=1536;
+ dft(DFT_1536,prach2,rxsigF[aa],1);
+ if (prachFormat != 7) {
+ dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1);
+ reps++;
+ }
+
+ if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) {
+ dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1);
+ dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1);
+ reps+=2;
+ }
+ if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) {
+ dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1);
+ dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1);
+ reps+=2;
+ }
+ if (prachFormat == 6) {
+ for (int i=6;i<12;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1);
+ reps+=6;
+ }
+ }// mu==1
+ else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n");
+ } // short format
+ } // 3/4 sampling
+ } // <=50 MHz BW
else if (fp->N_RB_UL <= 273) {
if (fp->threequarter_fs==0) {
prach2 = prach[aa] + (Ncp<<3);
- dftlen=98304;
- //80,90,100 MHz @ 61.44 Ms/s
- if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2)
- dft(DFT_98304,prach2,rxsigF[aa],1);
- if (prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1);
- reps++;
- }
- if (prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1);
- dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1);
- reps+=2;
- }
- if (prach_fmt == 3) {
- dft(DFT_24576,prach2+(2*49152),rxsigF[aa]+(2*49152),1);
- reps=4;
- dftlen=24576;
- }
- if (prach_fmt >3) {
- dftlen=4096;
- dft(DFT_4096,prach2,rxsigF[aa],1);
- if (prach_fmt != 0xc0) {
- dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1);
+ //80,90,100 MHz @ 122.88 Ms/s
+
+ if (prach_sequence_length == 0) {
+ if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
+ dftlen=98304;
+ dft(DFT_98304,prach2,rxsigF[aa],1);
+ }
+ if (prachFormat == 1 || prachFormat == 2) {
+ dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1);
reps++;
}
- }
- if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) {
- dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1);
- dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1);
- reps+=2;
- }
- if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) {
- dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1);
- dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1);
- reps+=2;
- }
- if (prach_fmt == 0xc2) {
- for (int i=6;i<11;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1);
- reps+=6;
+ if (prachFormat == 2) {
+ dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1);
+ dft(DFT_98304,prach2+(196608*3),rxsigF[aa]+(196608*3),1);
+ reps+=2;
+ }
+ if (prachFormat == 3) {
+ dftlen=24576;
+ for (int i=0;i<4;i++) dft(DFT_24576,prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1);
+ reps=4;
+ }
+ }
+ else {
+ if ((mu==0 &&
+ (prachStartSymbol == 0 || prachStartSymbol == 7)) ||
+ (mu==1 && prachStartSymbol == 0)) prach2+=128; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only)
+
+ if (mu==0) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==1) {
+ dftlen=4096;
+ dft(DFT_4096,prach2,rxsigF[aa],1);
+ if (prachFormat != 7) { //!=C0
+ dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1);
+ reps++;
+ }
+
+ if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) {
+ dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1);
+ dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1);
+ reps+=2;
+ }
+ if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) {
+ dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1);
+ dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1);
+ reps+=2;
+ }
+ if (prachFormat == 6) {
+ for (int i=6;i<12;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1);
+ reps+=6;
+ }
+ }
+ else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n");
}
} else {
AssertFatal(fp->N_RB_UL <= 217,"cannot do more than 217 PRBs with 3/4 sampling\n");
prach2 = prach[aa] + (6*Ncp);
- // 80 MHz @ 46.08 Ms/s
- dftlen=73728;
- if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_73728,prach2,rxsigF[aa],1);
- reps++;
- }
- if (prach_fmt == 1 || prach_fmt == 2) {
- dft(DFT_73728,prach2+(2*73728),rxsigF[aa]+(2*73728),1);
- reps++;
- }
- if (prach_fmt == 3) {
- dft(DFT_73728,prach2+(4*73728),rxsigF[aa]+(4*73728),1);
- reps=4;
- dftlen=18432;
- }
-
- if (prach_fmt >3) {
- dftlen=3072;
- dft(DFT_3072,prach2,rxsigF[aa],1);
- if (prach_fmt != 0xc0) {
- dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1);
+ // 80 MHz @ 92.16 Ms/s
+ if (prach_sequence_length == 0) {
+ if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
+ dftlen=73728;
+ dft(DFT_73728,prach2,rxsigF[aa],1);
+ reps++;
+ }
+ if (prachFormat == 1 || prachFormat == 2) {
+ dft(DFT_73728,prach2+(2*73728),rxsigF[aa]+(2*73728),1);
reps++;
}
- }
- if (prach_fmt == 0xa2 || prach_fmt == 0xa3 || prach_fmt == 0xb2 || prach_fmt == 0xb3 || prach_fmt == 0xb4 || prach_fmt == 0xc2) {
- dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1);
- dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1);
- reps+=2;
- }
- if (prach_fmt == 0xa3 || prach_fmt == 0xb3 || prach_fmt == 0xc2) {
- dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1);
- dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1);
- reps+=2;
- }
- if (prach_fmt == 0xc2) {
- for (int i=6;i<11;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1);
- reps+=6;
+ if (prachFormat == 3) {
+ dftlen=18432;
+ for (int i=0;i<4;i++) dft(DFT_18432,prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1);
+ reps=4;
+ }
+ } else {
+ if ((mu==0 &&
+ (prachStartSymbol == 0 || prachStartSymbol == 7)) ||
+ (mu==1 && prachStartSymbol == 0)) prach2+=96; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only)
+
+ if (mu==0) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==1) {
+ dftlen=3072;
+ dft(DFT_3072,prach2,rxsigF[aa],1);
+ if (prachFormat != 7) { //!=C0
+ dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1);
+ reps++;
+ }
+
+ if (prachFormat == 1 || prachFormat == 2 || prachFormat == 4 || prachFormat == 5 || prachFormat == 6 || prachFormat == 8) {
+ dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1);
+ dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1);
+ reps+=2;
+ }
+ if (prachFormat == 2 || prachFormat == 5 || prachFormat == 6) {
+ dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1);
+ dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1);
+ reps+=2;
+ }
+ if (prachFormat == 6) {
+ for (int i=6;i<12;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1);
+ reps+=6;
+ }
+ }
+ else if (mu==2) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==3) AssertFatal(1==0,"Shouldn't get here\n");
+ else if (mu==4) AssertFatal(1==0,"Shouldn't get here\n");
}
}
}
//Coherent combining of PRACH repetitions (assumes channel does not change, to be revisted for "long" PRACH)
+ LOG_D(PHY,"Doing PRACH combining of %d reptitions N_ZC %d\n",reps,N_ZC);
int16_t rxsigF_tmp[N_ZC<<1];
// if (k+N_ZC > dftlen) { // PRACH signal is split around DC
int16_t *rxsigF2=rxsigF[aa];
@@ -350,7 +512,7 @@ void rx_nr_prach_ru(RU_t *ru,
for (int j=0;j<N_ZC<<1;j++,k2++) {
if (k2==(dftlen<<1)) k2=0;
rxsigF_tmp[j] = rxsigF2[k2];
- for (int i=1;i<reps;i++) rxsigF_tmp[j] += rxsigF2[k2+(i*N_ZC<<1)];
+ for (int i=1;i<reps;i++) rxsigF_tmp[j] += rxsigF2[k2+(i*dftlen<<1)];
}
memcpy((void*)rxsigF2,(void *)rxsigF_tmp,N_ZC<<2);
@@ -359,6 +521,7 @@ void rx_nr_prach_ru(RU_t *ru,
}
void rx_nr_prach(PHY_VARS_gNB *gNB,
+ nfapi_nr_prach_pdu_t *prach_pdu,
int frame,
int subframe,
uint16_t *max_preamble,
@@ -366,16 +529,17 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
uint16_t *max_preamble_delay
)
{
+ AssertFatal(gNB!=NULL,"Can only be called from gNB\n");
int i;
+ nfapi_nr_prach_config_t *cfg=&gNB->gNB_config.prach_config;
NR_DL_FRAME_PARMS *fp;
- lte_frame_type_t frame_type;
+
uint16_t rootSequenceIndex;
- uint8_t prach_ConfigIndex;
- uint8_t Ncs_config;
+ int numrootSequenceIndex;
uint8_t restricted_set;
- uint8_t n_ra_prb;
+ uint8_t n_ra_prb=0xFF;
int16_t *prachF=NULL;
int nb_rx;
@@ -403,63 +567,35 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
int16_t prach_ifft_tmp[2048*2] __attribute__((aligned(32)));
int32_t *prach_ifft=(int32_t*)NULL;
- nr_frequency_range_e freq_range;
+ fp = &gNB->frame_parms;
- AssertFatal(gNB!=NULL,"Can only be called from gNB\n");
- fp = &gNB->frame_parms;
- nb_rx = fp->nb_antennas_rx;
+ nb_rx = gNB->gNB_config.carrier_config.num_rx_ant.value;
- frame_type = fp->frame_type;
- freq_range = fp->freq_range;
- rootSequenceIndex = fp->prach_config_common.rootSequenceIndex;
- prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
- Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig;
- restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag;
-
+ rootSequenceIndex = cfg->num_prach_fd_occasions_list[0].prach_root_sequence_index.value;
+ numrootSequenceIndex = cfg->num_prach_fd_occasions_list[0].num_root_sequences.value;
+ NCS = prach_pdu->num_cs;//cfg->num_prach_fd_occasions_list[0].prach_zero_corr_conf.value;
+ int prach_sequence_length = cfg->prach_sequence_length.value;
- uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,freq_range);
- uint16_t N_ZC = (prach_fmt <4)?839:139;
+ int msg1_frequencystart = cfg->num_prach_fd_occasions_list[0].k1.value;
+ // int num_unused_root_sequences = cfg->num_prach_fd_occasions_list[0].num_unused_root_sequences.value;
+ // cfg->num_prach_fd_occasions_list[0].unused_root_sequences_list
- AssertFatal(gNB!=NULL,"gNB is null\n");
+ restricted_set = cfg->restricted_set_config.value;
+
+ uint8_t prach_fmt = prach_pdu->prach_format;
+ uint16_t N_ZC = (prach_sequence_length==0)?839:139;
+
+ LOG_D(PHY,"L1 PRACH RX: rooSequenceIndex %d, numRootSeqeuences %d, NCS %d, N_ZC %d \n", rootSequenceIndex,numrootSequenceIndex,NCS,N_ZC);
prach_ifft = gNB->prach_vars.prach_ifft;
prachF = gNB->prach_vars.prachF;
if (LOG_DEBUGFLAG(PRACH)){
- if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, prach_ConfigIndex %d , rootSequenceIndex %d\n", subframe,fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart,prach_ConfigIndex,rootSequenceIndex);
- }
-
-
-
-
-
-
- int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME
- if (prach_fmt<3){
- if (restricted_set == 0) {
- NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config];
- } else {
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME
- }
+ if ((frame&1023) < 20) LOG_D(PHY,"PRACH (gNB) : running rx_prach for subframe %d, msg1_frequencystart %d, rootSequenceIndex %d\n", subframe,msg1_frequencystart,rootSequenceIndex);
}
- if (prach_fmt==3){
- if (restricted_set == 0) {
- NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config];
- } else {
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME
- }
- }
- if (prach_fmt>3){
- NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config];
- }
-
- AssertFatal(NCS!=99,"NCS has not been set\n");
- if (gNB) start_meas(&gNB->rx_prach);
+ start_meas(&gNB->rx_prach);
-
- prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc;
+ prach_root_sequence_map = (cfg->prach_sequence_length.value==0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc;
// PDP is oversampled, e.g. 1024 sample instead of 839
// Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839
@@ -472,16 +608,19 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
*max_preamble_energy=0;
+ *max_preamble_delay=0;
+ *max_preamble=0;
+
for (preamble_index=0 ; preamble_index<64 ; preamble_index++) {
if (LOG_DEBUGFLAG(PRACH)){
int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],(N_ZC==839) ? 840: 140));
- if (en>60) LOG_I(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index);
+ if (en>60) LOG_D(PHY,"frame %d, subframe %d : Trying preamble %d \n",frame,subframe,preamble_index);
}
if (restricted_set == 0) {
// This is the relative offset in the root sequence table (5.7.2-4 from 36.211) for the given preamble index
preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS)));
-
+
if (preamble_offset != preamble_offset_old) {
preamble_offset_old = preamble_offset;
new_dft = 1;
@@ -511,13 +650,6 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
// current root depending on rootSequenceIndex
int index = (rootSequenceIndex + preamble_offset) % N_ZC;
- if (prach_fmt<4) {
- // prach_root_sequence_map points to prach_root_sequence_map0_3
- DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) );
- } else {
- // prach_root_sequence_map points to prach_root_sequence_map4
- DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) );
- }
u = prach_root_sequence_map[index];
uint16_t n_group_ra = 0;
@@ -562,14 +694,21 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
// Compute DFT of RX signal (conjugate input, results in conjugate output) for each new rootSequenceIndex
if (LOG_DEBUGFLAG(PRACH)) {
int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840));
- if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, NCS_config %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n",
- frame,subframe,preamble_index,NCS,Ncs_config,N_ZC/NCS,preamble_offset,preamble_shift,en);
+ if (en>60) LOG_I(PHY,"frame %d, subframe %d : preamble index %d, NCS %d, N_ZC/NCS %d: offset %d, preamble shift %d , en %d)\n",
+ frame,subframe,preamble_index,NCS,N_ZC/NCS,preamble_offset,preamble_shift,en);
}
+ LOG_D(PHY,"PRACH RX preamble_index %d, preamble_offset %d\n",preamble_index,preamble_offset);
+
+
if (new_dft == 1) {
new_dft = 0;
Xu=(int16_t*)gNB->X_u[preamble_offset-first_nonzero_root_idx];
+
+ LOG_D(PHY,"PRACH RX new dft preamble_offset-first_nonzero_root_idx %d\n",preamble_offset-first_nonzero_root_idx);
+
+
memset(prach_ifft,0,((N_ZC==839) ? 2048 : 256)*sizeof(int32_t));
@@ -593,32 +732,31 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
idft(IDFT_1024,prachF,prach_ifft_tmp,1);
// compute energy and accumulate over receive antennas
for (i=0;i<2048;i++)
- prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[i<<1] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10;
+ prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[i<<1] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10;
} else {
idft(IDFT_256,prachF,prach_ifft_tmp,1);
log2_ifft_size = 8;
// compute energy and accumulate over receive antennas and repetitions for BR
for (i=0;i<256;i++)
- prach_ifft[i] += (prach_ifft_tmp[i<<1]*prach_ifft_tmp[(i<<1)] + prach_ifft_tmp[1+(i<<1)]*prach_ifft_tmp[1+(i<<1)])>>10;
+ prach_ifft[i] += ((int32_t)prach_ifft_tmp[i<<1]*(int32_t)prach_ifft_tmp[(i<<1)] + (int32_t)prach_ifft_tmp[1+(i<<1)]*(int32_t)prach_ifft_tmp[1+(i<<1)])>>10;
}
- if (LOG_DUMPFLAG(PRACH)) {
+ if (LOG_DUMPFLAG(PRACH)) {
if (aa==0) LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1);
if (aa==1) LOG_M("prach_rxF_comp1.m","prach_rxF_comp1",prachF,1024,1,1);
- }
+ }
}// antennas_rx
} // new dft
// check energy in nth time shift, for
preamble_shift2 = ((preamble_shift==0) ? 0 : ((preamble_shift<<log2_ifft_size)/N_ZC));
-
-
+
for (i=0; i<NCS2; i++) {
lev = (int32_t)prach_ifft[(preamble_shift2+i)];
levdB = dB_fixed_times10(lev);
-
if (levdB>*max_preamble_energy) {
+ LOG_D(PHY,"preamble_index %d, delay %d en %d dB > %d dB\n",preamble_index,i,levdB,*max_preamble_energy);
*max_preamble_energy = levdB;
*max_preamble_delay = i; // Note: This has to be normalized to the 30.72 Ms/s sampling rate
*max_preamble = preamble_index;
@@ -626,9 +764,34 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
}
}// preamble_index
+
+ // The conversion from *max_preamble_delay from TA value is done here.
+ // It is normalized to the 30.72 Ms/s, considering the numerology, N_RB and the sampling rate
+ // See table 6.3.3.1 -1 and -2 in 38211.
+
+ // Format 0, 1, 2: 24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s
+ // By solving:
+ // max_preamble_delay * ( (24576*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc
+
+ // Format 3: 6144 samples @ 30.72 Ms/s, 24576 samples @ 122.88 Ms/s
+ // By solving:
+ // max_preamble_delay * ( (6144*(fs/30.72M)) / 1024 ) / fs = TA * 16 * 64 / 2^mu * Tc
+
+ // Format >3: 2048/2^mu samples @ 30.72 Ms/s, 2048/2^mu * 4 samples @ 122.88 Ms/s
+ // By solving:
+ // max_preamble_delay * ( (2048/2^mu*(fs/30.72M)) / 256 ) / fs = TA * 16 * 64 / 2^mu * Tc
+ uint16_t *TA = max_preamble_delay;
+ int mu = fp->numerology_index;
+ if (cfg->prach_sequence_length.value==0) {
+ if (prach_fmt == 0 || prach_fmt == 1 || prach_fmt == 2) *TA = *TA*3*(1<<mu)/2;
+ else if (prach_fmt == 3) *TA = *TA*3*(1<<mu)/8;
+ }
+ else *TA = *TA/2;
+
+
if (LOG_DUMPFLAG(PRACH)) {
- int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840));
- if (en>60) {
+ //int en = dB_fixed(signal_energy((int32_t*)&rxsigF[0][0],840));
+ // if (en>60) {
int k = (12*n_ra_prb) - 6*fp->N_RB_UL;
if (k<0) k+=fp->ofdm_symbol_size;
@@ -642,9 +805,9 @@ void rx_nr_prach(PHY_VARS_gNB *gNB,
LOG_M("prach_rxF_comp0.m","prach_rxF_comp0",prachF,1024,1,1);
LOG_M("Xu.m","xu",Xu,N_ZC,1,1);
LOG_M("prach_ifft0.m","prach_t0",prach_ifft,1024,1,1);
- }
+ // }
} /* LOG_DUMPFLAG(PRACH) */
- if (gNB) stop_meas(&gNB->rx_prach);
+ stop_meas(&gNB->rx_prach);
}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach.h b/openair1/PHY/NR_TRANSPORT/nr_prach.h
index 1e2b7580358a66a22f27fe08baa6d94e045ccf2d..d158e04c794b54efacf6ae1577e32c241748e036 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_prach.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_prach.h
@@ -37,18 +37,6 @@ uint16_t nr_du[838];
/*************************************
* The following tables defined for NR
**************************************/
-// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz
-uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419};
-uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A
-uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B
-
-// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz
-uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419};
-uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A
-uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B
-
-// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3}
-uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69};
//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839
uint16_t prach_root_sequence_map_0_3[838] = {
@@ -105,787 +93,3 @@ uint16_t prach_root_sequence_map_abc[138] = {
51, 88 , 52, 87 , 53, 86 , 54, 85 , 55, 84 , 56, 83 , 57, 82 , 58, 81 , 59, 80 , 60, 79 ,
61, 78 , 62, 77 , 63, 76 , 64, 75 , 65, 74 , 66, 73 , 67, 72 , 68, 71 , 69, 70
};
-
-// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink
-// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent.
-// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9.
-// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6
-int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = {
-//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
-{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
-{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
-{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
-{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
-{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
-{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
-{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
-{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9
-{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8
-{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9
-{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
-{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
-{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
-{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
-{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
-{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
-{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
-{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9
-{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5
-{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5
-{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
-{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
-{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
-{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
-{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
-{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
-{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
-{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
-{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
-{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
-{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
-{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
-{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9
-{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8
-{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9
-{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4
-{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4
-{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4
-{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1
-{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4
-{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7
-{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4
-{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6
-{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
-{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1
-{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7
-{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7
-{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7
-{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8
-{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9
-{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
-{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
-{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
-{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
-{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
-{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
-{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
-{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4
-{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
-{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4
-{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
-{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
-{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
-{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
-{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
-{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
-{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4
-{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6
-{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9
-{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
-{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
-{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7
-{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7
-{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8
-{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9
-{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
-{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
-{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4
-{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6
-{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9
-{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
-{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
-{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7
-{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8
-{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
-{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
-{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
-{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
-{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
-{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
-{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
-{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7
-{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
-{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
-{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9
-{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
-{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
-{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
-{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
-{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
-{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
-{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
-{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
-{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
-{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
-{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
-{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
-{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
-{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7
-{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
-{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
-{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9
-{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4
-{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4
-{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
-{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1
-{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
-{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7
-{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1
-{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
-{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7
-{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6
-{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7
-{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
-{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7
-{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8
-{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9
-{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
-{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
-{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
-{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
-{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
-{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
-{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
-{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
-{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7
-{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
-{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
-{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9
-{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
-{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
-{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
-{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
-{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
-{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
-{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
-{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
-{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
-{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7
-{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
-{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
-{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
-{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9
-};
-// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum
-int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = {
-//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
-{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
-{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4)
-{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
-{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8)
-{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
-{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6)
-{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5)
-{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
-{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3)
-{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2)
-{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6)
-{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6)
-{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9)
-{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8)
-{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7)
-{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9)
-{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9)
-{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9)
-{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9)
-{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9)
-{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9)
-{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9)
-{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9)
-{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
-{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
-{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
-{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
-{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
-{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
-{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
-{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
-{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
-{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6)
-{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6)
-{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6)
-{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
-{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4)
-{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
-{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8)
-{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
-{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6)
-{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5)
-{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
-{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3)
-{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2)
-{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6)
-{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6)
-{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9)
-{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8)
-{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7)
-{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9)
-{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9)
-{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9)
-{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9)
-{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9)
-{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9)
-{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9)
-{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9)
-{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9)
-{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9)
-{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9)
-{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9)
-{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9)
-{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9)
-{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9)
-{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9)
-{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9)
-{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9)
-{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9)
-{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9)
-{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9)
-{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9)
-{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9)
-{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9)
-{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9)
-{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9)
-{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9)
-{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9)
-{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
-{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9)
-{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9)
-{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9)
-{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9)
-{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9)
-{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9)
-{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2)
-{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7)
-{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
-{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9)
-{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9)
-{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9)
-{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7)
-{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9)
-{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9)
-{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9)
-{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9)
-{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9)
-{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9)
-{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9)
-{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9)
-{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
-{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9)
-{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9)
-{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9)
-{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9)
-{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9)
-{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9)
-{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2)
-{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7)
-{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
-{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9)
-{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9)
-{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9)
-{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7)
-{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9)
-{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9)
-{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9)
-{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9)
-{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9)
-{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9)
-{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
-{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
-{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
-{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
-{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
-{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
-{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
-{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
-{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
-{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9)
-{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9)
-{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9)
-{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9)
-{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9)
-{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9)
-{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9)
-{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9)
-{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9)
-{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9)
-{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1)
-{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2)
-{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4)
-{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7)
-{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9)
-{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9)
-{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9)
-{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9)
-{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9)
-{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9)
-{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9)
-{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9)
-{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9)
-{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9)
-{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9)
-{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
-{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9)
-{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
-{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
-{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9)
-{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
-{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
-{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
-{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
-{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
-{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9)
-{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9)
-{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
-{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9)
-{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9)
-{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9)
-{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9)
-{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9)
-{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9)
-{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9)
-{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9)
-{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9)
-{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9)
-{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9)
-{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9)
-{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9)
-{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9)
-{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9)
-{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9)
-{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9)
-{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9)
-{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9)
-{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9)
-{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9)
-{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
-{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9)
-{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
-{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
-{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9)
-{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
-{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
-{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
-{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
-{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
-{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
-{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9)
-{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
-{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
-{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9)
-{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9)
-{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9)
-{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9)
-{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9)
-{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9)
-{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9)
-{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9)
-{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9)
-{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9)
-{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9)
-{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9)
-{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9)
-{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
-{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
-{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9)
-{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9)
-{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9)
-{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9)
-{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9)
-{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9)
-{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9)
-{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9)
-{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9)
-{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9)
-{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9)
-{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9)
-{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9)
-{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9)
-};
-// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum
-int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = {
-//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
-{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39)
-{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39)
-{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39)
-{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7)
-{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39)
-{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39)
-{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39)
-{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39)
-{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
-{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39)
-{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39)
-{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39)
-{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
-{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39)
-{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39)
-{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39)
-{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39)
-{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7)
-{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39)
-{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39)
-{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39)
-{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39)
-{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39)
-{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39)
-{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39)
-{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13)
-{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13)
-{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39)
-{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39)
-{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
-{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39)
-{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7)
-{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13)
-{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39)
-{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39)
-{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39)
-{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
-{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39)
-{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39)
-{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39)
-{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13)
-{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13)
-{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39)
-{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39)
-{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
-{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
-{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7)
-{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39)
-{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39)
-{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39)
-{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
-{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39)
-{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
-{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39)
-{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
-{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
-{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39)
-{0xb4, -1, 16, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 16, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 8, 1, 2, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 8, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39)
-{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 4, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 4, 1, 2, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39)
-{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39)
-{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39)
-{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39)
-{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39)
-{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39)
-{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39)
-{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39)
-{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39)
-{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39)
-{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19)
-{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13)
-{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 1, 0, -1, 586406201480, 2, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25)
-{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25)
-{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39)
-{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39)
-{0xc0, -1, 16, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 16, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 8, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 8, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 8, 1, 2, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39)
-{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 4, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 4, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39)
-{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
-{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7)
-{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39)
-{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39)
-{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39)
-{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39)
-{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
-{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39)
-{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39)
-{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
-{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39)
-{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39)
-{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
-{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39)
-{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39)
-{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7)
-{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39)
-{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39)
-{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39)
-{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39)
-{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39)
-{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13)
-{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39)
-{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39)
-{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39)
-{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39)
-{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39)
-{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
-{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39)
-{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39)
-{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
-{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
-{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39)
-{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39)
-{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa1, 0xb1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
-{0xa2, 0xb2, 16, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39)
-{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39)
-{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39)
-{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39)
-{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39)
-{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39)
-{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39)
-{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39)
-{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39)
-{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39)
-{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39)
-{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39)
-{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39)
-{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39)
-{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39)
-{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
-{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
-{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39)
-};
diff --git a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c
index e1b80a87a2f16e0d279997e3d512c4caa92366db..a95c519d439290449bd82792465632cbf63c0df8 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_prach_common.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_prach_common.c
@@ -34,15 +34,15 @@
#include "PHY/impl_defs_nr.h"
#include "PHY/defs_nr_UE.h"
#include "PHY/NR_TRANSPORT/nr_prach.h"
-#include "PHY/NR_TRANSPORT/nr_transport_proto_common.h"
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
-
+#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h"
#include "T.h"
-void init_nr_prach_tables(int N_ZC);
-void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) {
+
+/*void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) {
FILE *fd;
@@ -76,23 +76,13 @@ void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe) {
fprintf(fd,"prach_config: n_ra_prboffset = %d\n",frame_parms->prach_config_common.prach_ConfigInfo.msg1_frequencystart);
fclose(fd);
-}
+}*/
// This function computes the du
-void nr_fill_du(uint8_t prach_fmt)
+void nr_fill_du(uint16_t N_ZC,uint16_t *prach_root_sequence_map)
{
uint16_t iu,u,p;
- uint16_t N_ZC;
- uint16_t *prach_root_sequence_map;
-
- if (prach_fmt<4) {
- N_ZC = 839;
- prach_root_sequence_map = prach_root_sequence_map_0_3;
- } else {
- N_ZC = 139;
- prach_root_sequence_map = prach_root_sequence_map_abc;
- }
for (iu=0; iu<(N_ZC-1); iu++) {
@@ -107,214 +97,49 @@ void nr_fill_du(uint8_t prach_fmt)
}
-int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame, uint8_t subframe) {
-
- uint8_t prach_ConfigIndex = frame_parms->prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
- /*
- // For FR1 paired
- if (((frame%table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][3]) &&
- ((table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][4]&(1<<subframe)) == 1)) {
- // using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink
- return(1);
- } else {
- return(0);
- }
- */
- // For FR1 unpaired
- if (((frame%table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][3]) &&
- ((table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4]&(1<<subframe)) == 1)) {
- // using table 6.3.3.2-2: Random access configurations for FR1 and unpaired
- return(1);
- } else {
- return(0);
- }
- /*
- // For FR2: FIXME
- if ((((frame%table_6_3_3_2_4_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_4_prachConfig_Index[prach_ConfigIndex][3]) ||
- ((frame%table_6_3_3_2_4_prachConfig_Index[prach_ConfigIndex][2]) == table_6_3_3_2_4_prachConfig_Index[prach_ConfigIndex][4]))
- &&
- ((table_6_3_3_2_4_prachConfig_Index[prach_ConfigIndex][5]&(1<<subframe)) == 1)) {
- // using table 6.3.3.2-2: Random access configurations for FR1 and unpaired
- return(1);
- } else {
- return(0);
- }
- */
-}
-
-
-int do_prach_rx(NR_DL_FRAME_PARMS *fp,int frame,int slot) {
-
- int subframe = slot / fp->slots_per_subframe;
- // when were in the last slot of the subframe and this is a PRACH subframe ,return 1
- if (((slot%fp->slots_per_subframe) == fp->slots_per_subframe-1)&&
- (is_nr_prach_subframe(fp,frame,subframe))) return (1);
- else return(0);
-}
-
-uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr)
-{
-
- if (frame_type==FDD) return (table_6_3_3_2_2_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink
- else if (fr==nr_FR1) return (table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][0]); // if using table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum
- else AssertFatal(1==0,"FR2 prach configuration not supported yet\n");
- // For FR2 not implemented. FIXME
-}
-
-void compute_nr_prach_seq(uint16_t rootSequenceIndex,
- uint8_t prach_ConfigIndex,
- uint8_t zeroCorrelationZoneConfig,
- uint8_t highSpeedFlag,
- lte_frame_type_t frame_type,
- nr_frequency_range_e fr,
- uint32_t X_u[64][839])
-{
+void compute_nr_prach_seq(uint8_t short_sequence,
+ uint8_t num_sequences,
+ uint8_t rootSequenceIndex,
+ uint32_t X_u[64][839]){
// Compute DFT of x_u => X_u[k] = x_u(inv(u)*k)^* X_u[k] = exp(j\pi u*inv(u)*k*(inv(u)*k+1)/N_ZC)
- unsigned int k,inv_u,i,NCS=0,num_preambles;
+ unsigned int k,inv_u,i;
int N_ZC;
- uint8_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,frame_type,fr);
+
uint16_t *prach_root_sequence_map;
- uint16_t u, preamble_offset;
- uint16_t n_shift_ra,n_shift_ra_bar, d_start,numshift;
- uint8_t not_found;
+ uint16_t u;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_FUNCTION_IN);
-#ifdef NR_PRACH_DEBUG
- LOG_I(PHY,"compute_prach_seq: NCS_config %d, prach_fmt %x\n",zeroCorrelationZoneConfig, prach_fmt);
-#endif
-
+ LOG_D(PHY,"compute_prach_seq: prach short sequence %x, num_sequences %d, rootSequenceIndex %d\n", short_sequence, num_sequences, rootSequenceIndex);
- N_ZC = (prach_fmt < 4) ? 839 : 139;
+ N_ZC = (short_sequence) ? 139 : 839;
//init_prach_tables(N_ZC); //moved to phy_init_lte_ue/eNB, since it takes to long in real-time
init_nr_prach_tables(N_ZC);
- if (prach_fmt < 4) {
- prach_root_sequence_map = prach_root_sequence_map_0_3;
- } else {
+ if (short_sequence) {
// FIXME cannot be reached
prach_root_sequence_map = prach_root_sequence_map_abc;
- }
-
-
-#ifdef PRACH_DEBUG
- LOG_I( PHY, "compute_prach_seq: done init prach_tables\n" );
-#endif
-
-
-
-
- int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME
-
- if (highSpeedFlag== 0) {
-
-#ifdef PRACH_DEBUG
- LOG_I(PHY,"Low speed prach : NCS_config %d\n",zeroCorrelationZoneConfig);
-#endif
-
- AssertFatal(zeroCorrelationZoneConfig<=15,
- "FATAL, Illegal Ncs_config for unrestricted format %"PRIu8"\n", zeroCorrelationZoneConfig );
- if (prach_fmt<3) NCS = NCS_unrestricted_delta_f_RA_125[zeroCorrelationZoneConfig];
- if (prach_fmt==3) NCS = NCS_unrestricted_delta_f_RA_5[zeroCorrelationZoneConfig];
- if (prach_fmt>3) NCS = NCS_unrestricted_delta_f_RA_15[zeroCorrelationZoneConfig];
-
- num_preambles = (NCS==0) ? 64 : ((64*NCS)/N_ZC);
-
- if (NCS>0) num_preambles++;
-
- preamble_offset = 0;
} else {
-
-#ifdef PRACH_DEBUG
- LOG_I( PHY, "high speed prach : NCS_config %"PRIu8"\n", zeroCorrelationZoneConfig );
-#endif
-
- AssertFatal(zeroCorrelationZoneConfig<=14,
- "FATAL, Illegal Ncs_config for restricted format %"PRIu8"\n", zeroCorrelationZoneConfig );
- if (prach_fmt<3){
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME
- }
- if (prach_fmt==3){
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[zeroCorrelationZoneConfig]; // for TypeB, this is hardcoded. FIXME
- }
- if (prach_fmt>3){
-
- }
-
- nr_fill_du(prach_fmt);
-
- num_preambles = 64; // compute ZC sequence for 64 possible roots
- // find first non-zero shift root (stored in preamble_offset)
- not_found = 1;
- preamble_offset = 0;
-
- while (not_found == 1) {
- // current root depending on rootSequenceIndex
- int index = (rootSequenceIndex + preamble_offset) % N_ZC;
-
- if (prach_fmt<4) {
- // prach_root_sequence_map points to prach_root_sequence_map0_3
- DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) );
- } else {
- // prach_root_sequence_map points to prach_root_sequence_map4
- DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) );
- }
-
- u = prach_root_sequence_map[index];
-
- uint16_t n_group_ra = 0;
-
- if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) {
- n_shift_ra = nr_du[u]/NCS;
- d_start = (nr_du[u]<<1) + (n_shift_ra * NCS);
- n_group_ra = N_ZC/d_start;
- n_shift_ra_bar = max(0,(N_ZC-(nr_du[u]<<1)-(n_group_ra*d_start))/N_ZC);
- } else if ( (nr_du[u]>=(N_ZC/3)) && (nr_du[u]<=((N_ZC - NCS)>>1)) ) {
- n_shift_ra = (N_ZC - (nr_du[u]<<1))/NCS;
- d_start = N_ZC - (nr_du[u]<<1) + (n_shift_ra * NCS);
- n_group_ra = nr_du[u]/d_start;
- n_shift_ra_bar = min(n_shift_ra,max(0,(nr_du[u]- (n_group_ra*d_start))/NCS));
- } else {
- n_shift_ra = 0;
- n_shift_ra_bar = 0;
- }
-
- // This is the number of cyclic shifts for the current root u
- numshift = (n_shift_ra*n_group_ra) + n_shift_ra_bar;
-
- // skip to next root and recompute parameters if numshift==0
- if (numshift>0)
- not_found = 0;
- else
- preamble_offset++;
- }
+ prach_root_sequence_map = prach_root_sequence_map_0_3;
}
-#ifdef PRACH_DEBUG
-
- if (NCS>0)
- LOG_I( PHY, "Initializing %u preambles for PRACH (NCS_config %"PRIu8", NCS %u, N_ZC/NCS %u)\n",
- num_preambles, zeroCorrelationZoneConfig, NCS, N_ZC/NCS );
+ LOG_D( PHY, "compute_prach_seq: done init prach_tables\n" );
-#endif
-
- for (i=0; i<num_preambles; i++) {
- int index = (rootSequenceIndex+i+preamble_offset) % N_ZC;
+ for (i=0; i<num_sequences; i++) {
+ int index = (rootSequenceIndex+i) % (N_ZC-1);
- if (prach_fmt<4) {
- // prach_root_sequence_map points to prach_root_sequence_map0_3
- DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) );
- } else {
+ if (short_sequence) {
// prach_root_sequence_map points to prach_root_sequence_map4
DevAssert( index < sizeof(prach_root_sequence_map_abc) / sizeof(prach_root_sequence_map_abc[0]) );
+ } else {
+ // prach_root_sequence_map points to prach_root_sequence_map0_3
+ DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) );
}
u = prach_root_sequence_map[index];
-
+ LOG_D(PHY,"prach index %d => u=%d\n",index,u);
inv_u = nr_ZC_inv[u]; // multiplicative inverse of u
@@ -322,8 +147,8 @@ void compute_nr_prach_seq(uint16_t rootSequenceIndex,
// for the unrestricted case X_u[0] is the first root indicated by the rootSequenceIndex
for (k=0; k<N_ZC; k++) {
- // 420 is the multiplicative inverse of 2 (required since ru is exp[j 2\pi n])
- X_u[i][k] = ((uint32_t*)nr_ru)[(((k*(1+(inv_u*k)))%N_ZC)*420)%N_ZC];
+ // multiply by inverse of 2 (required since ru is exp[j 2\pi n])
+ X_u[i][k] = ((uint32_t*)nr_ru)[(((k*(1+(inv_u*k)))%N_ZC)*nr_ZC_inv[2])%N_ZC];
}
}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_pss.c b/openair1/PHY/NR_TRANSPORT/nr_pss.c
index be9e011e60cb6fcba7c7cf7ef8a7edb29312d916..535ce991438c9ed3220cd7a94eb851ef019e39aa 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_pss.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_pss.c
@@ -20,7 +20,7 @@
*/
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
//#define NR_PSS_DEBUG
diff --git a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h
index 2b25464b84928cdee2005f4eae6e650d420b037d..491e24658e46b747edfbeac88a73068a3036c932 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_sch_dmrs.h
@@ -50,4 +50,4 @@ uint16_t get_dmrs_freq_idx(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t d
uint8_t get_l0(uint16_t dlDmrsSymbPos);
-#endif
\ No newline at end of file
+#endif
diff --git a/openair1/PHY/NR_TRANSPORT/nr_sss.c b/openair1/PHY/NR_TRANSPORT/nr_sss.c
index 7d8b551d7ca087f49035a18d90f56e176df7b827..de92237f6caf2b45cb325da09b0b550a08c83b81 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_sss.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_sss.c
@@ -19,7 +19,7 @@
* contact@openairinterface.org
*/
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
//#define NR_SSS_DEBUG
diff --git a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c
index ea8e39488e36e8d04236631b9756ef24cc89674f..e535286084fb954aabd6d90c23e73efd83455063 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_tbs_tools.c
@@ -32,7 +32,7 @@
#include "nr_transport_common_proto.h"
#include "PHY/CODING/coding_defs.h"
-
+#include "PHY/defs_nr_common.h"
uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) {
uint32_t G;
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport.h b/openair1/PHY/NR_TRANSPORT/nr_transport.h
deleted file mode 100644
index be738750588aaf124ab191631368aece7d301dbb..0000000000000000000000000000000000000000
--- a/openair1/PHY/NR_TRANSPORT/nr_transport.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.
- * The OpenAirInterface Software Alliance licenses this file to You under
- * the OAI Public License, Version 1.1 (the "License"); you may not use this file
- * except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.openairinterface.org/?page_id=698
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *-------------------------------------------------------------------------------
- * For more information about the OpenAirInterface (OAI) Software Alliance:
- * contact@openairinterface.org
- */
-
-#ifndef __NR_TRANSPORT__H__
-#define __NR_TRANSPORT__H__
-
-#include "PHY/defs_gNB.h"
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
-
-#define NR_PBCH_PDU_BITS 24
-
-/*!
-\fn int nr_generate_pss
-\brief Generation of the NR PSS
-@param
-@returns 0 on success
- */
-int nr_generate_pss( int16_t *d_pss,
- int32_t *txdataF,
- int16_t amp,
- uint8_t ssb_start_symbol,
- nfapi_nr_config_request_scf_t *config,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/*!
-\fn int nr_generate_sss
-\brief Generation of the NR SSS
-@param
-@returns 0 on success
- */
-int nr_generate_sss( int16_t *d_sss,
- int32_t *txdataF,
- int16_t amp,
- uint8_t ssb_start_symbol,
- nfapi_nr_config_request_scf_t *config,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/*!
-\fn int nr_generate_pbch_dmrs
-\brief Generation of the DMRS for the PBCH
-@param
-@returns 0 on success
- */
-int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs,
- int32_t *txdataF,
- int16_t amp,
- uint8_t ssb_start_symbol,
- nfapi_nr_config_request_scf_t *config,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/*!
-\fn int nr_pbch_scrambling
-\brief PBCH scrambling function
-@param
- */
-void nr_pbch_scrambling(NR_gNB_PBCH *pbch,
- uint32_t Nid,
- uint8_t nushift,
- uint16_t M,
- uint16_t length,
- uint8_t encoded,
- uint32_t unscrambling_mask);
-
-/*!
-\fn int nr_generate_pbch
-\brief Generation of the PBCH
-@param
-@returns 0 on success
- */
-int nr_generate_pbch(NR_gNB_PBCH *pbch,
- nfapi_nr_dl_tti_ssb_pdu *ssb_pdu,
- uint8_t *interleaver,
- int32_t *txdataF,
- int16_t amp,
- uint8_t ssb_start_symbol,
- uint8_t n_hf,
- int sfn,
- nfapi_nr_config_request_scf_t *config,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/*!
-\fn int nr_generate_pbch
-\brief PBCH interleaving function
-@param bit index i of the input payload
-@returns the bit index of the output
- */
-void nr_init_pbch_interleaver(uint8_t *interleaver);
-
-NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms,
- unsigned char Kmimo,
- unsigned char Mdlharq,
- uint32_t Nsoft,
- uint8_t abstraction_flag,
- uint16_t N_RB);
-
-void rx_nr_prach(PHY_VARS_gNB *gNB,
- int frame,
- int subframe,
- uint16_t *max_preamble,
- uint16_t *max_preamble_energy,
- uint16_t *max_preamble_delay
- );
-
-void rx_nr_prach_ru(RU_t *ru,
- int frame,
- int subframe);
-
-#endif /*__NR_TRANSPORT__H__*/
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
index 762346048f94f9e62e7733ecdbb4010ffa107dd1..a30c52945986d597739193a5619deee0c1d0296c 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
@@ -31,22 +31,51 @@
* \warning
*/
+/** @addtogroup _PHY_TRANSPORT_
+ * @{
+ */
+
#ifndef __NR_TRANSPORT_COMMON_PROTO__H__
#define __NR_TRANSPORT_COMMON_PROTO__H__
#include "PHY/defs_nr_common.h"
-#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1
-#define NR_PUSCH_y 3 // UCI placeholder bit
-
-
-
+void nr_group_sequence_hopping(pucch_GroupHopping_t PUCCH_GroupHopping,
+ uint32_t n_id,
+ uint8_t n_hop,
+ int nr_tti_tx,
+ uint8_t *u,
+ uint8_t *v);
+double nr_cyclic_shift_hopping(uint32_t n_id,
+ uint8_t m0,
+ uint8_t mcs,
+ uint8_t lnormal,
+ uint8_t lprime,
+ int nr_tti_tx);
/** \brief Computes available bits G. */
uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch, uint8_t nb_re_dmrs, uint16_t length_dmrs, uint8_t Qm, uint8_t Nl);
uint32_t nr_get_E(uint32_t G, uint8_t C, uint8_t Qm, uint8_t Nl, uint8_t r);
+uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
+
+uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
+
+uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
+
+uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
+
+void compute_nr_prach_seq(uint8_t short_sequence,
+ uint8_t num_sequences,
+ uint8_t rootSequenceIndex,
+ uint32_t X_u[64][839]);
+
+void init_nr_prach_tables(int N_ZC);
+
+/**@}*/
+
+void init_pucch2_luts(void);
#endif
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h
index 9ce56421fc47004154bc26d55d5284da4bb6eab3..e33532fa657f25792cf84c75342c38941ff29011 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h
+++ b/openair1/PHY/NR_TRANSPORT/nr_transport_proto.h
@@ -30,7 +30,98 @@
* \warning
*/
+#ifndef __NR_TRANSPORT__H__
+#define __NR_TRANSPORT__H__
+
#include "PHY/defs_nr_common.h"
+#include "PHY/defs_gNB.h"
+#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+
+#define NR_PBCH_PDU_BITS 24
+
+/*!
+\fn int nr_generate_pss
+\brief Generation of the NR PSS
+@param
+@returns 0 on success
+ */
+int nr_generate_pss(int16_t *d_pss,
+ int32_t *txdataF,
+ int16_t amp,
+ uint8_t ssb_start_symbol,
+ nfapi_nr_config_request_scf_t *config,
+ NR_DL_FRAME_PARMS *frame_parms);
+
+/*!
+\fn int nr_generate_sss
+\brief Generation of the NR SSS
+@param
+@returns 0 on success
+ */
+int nr_generate_sss(int16_t *d_sss,
+ int32_t *txdataF,
+ int16_t amp,
+ uint8_t ssb_start_symbol,
+ nfapi_nr_config_request_scf_t *config,
+ NR_DL_FRAME_PARMS *frame_parms);
+
+/*!
+\fn int nr_generate_pbch_dmrs
+\brief Generation of the DMRS for the PBCH
+@param
+@returns 0 on success
+ */
+int nr_generate_pbch_dmrs(uint32_t *gold_pbch_dmrs,
+ int32_t *txdataF,
+ int16_t amp,
+ uint8_t ssb_start_symbol,
+ nfapi_nr_config_request_scf_t *config,
+ NR_DL_FRAME_PARMS *frame_parms);
+
+/*!
+\fn int nr_pbch_scrambling
+\brief PBCH scrambling function
+@param
+ */
+void nr_pbch_scrambling(NR_gNB_PBCH *pbch,
+ uint32_t Nid,
+ uint8_t nushift,
+ uint16_t M,
+ uint16_t length,
+ uint8_t encoded,
+ uint32_t unscrambling_mask);
+
+/*!
+\fn int nr_generate_pbch
+\brief Generation of the PBCH
+@param
+@returns 0 on success
+ */
+int nr_generate_pbch(NR_gNB_PBCH *pbch,
+ nfapi_nr_dl_tti_ssb_pdu *ssb_pdu,
+ uint8_t *interleaver,
+ int32_t *txdataF,
+ int16_t amp,
+ uint8_t ssb_start_symbol,
+ uint8_t n_hf,
+ int sfn,
+ nfapi_nr_config_request_scf_t *config,
+ NR_DL_FRAME_PARMS *frame_parms);
+
+/*!
+\fn int nr_generate_pbch
+\brief PBCH interleaving function
+@param bit index i of the input payload
+@returns the bit index of the output
+ */
+void nr_init_pbch_interleaver(uint8_t *interleaver);
+
+NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms,
+ unsigned char Kmimo,
+ unsigned char Mdlharq,
+ uint32_t Nsoft,
+ uint8_t abstraction_flag,
+ uint16_t N_RB);
/** \brief This function is the top-level entry point to PUSCH demodulation, after frequency-domain transformation and channel estimation. It performs
- RB extraction (signal and channel estimates)
@@ -46,13 +137,12 @@
@param symbol Symbol on which to act (within-in nr_TTI_rx)
@param harq_pid HARQ process ID
*/
-void nr_rx_pusch(PHY_VARS_gNB *gNB,
- uint8_t UE_id,
- uint32_t frame,
- uint8_t nr_tti_rx,
- unsigned char symbol,
- unsigned char harq_pid);
-
+int nr_rx_pusch(PHY_VARS_gNB *gNB,
+ uint8_t UE_id,
+ uint32_t frame,
+ uint8_t nr_tti_rx,
+ unsigned char symbol,
+ unsigned char harq_pid);
/** \brief This function performs RB extraction (signal and channel estimates) (currently signal only until channel estimation and compensation are implemented)
@param rxdataF pointer to the received frequency domain signal
@@ -62,8 +152,6 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
@param start_rb The starting RB in the RB allocation (used for Resource Allocation Type 1 in NR)
@param nb_rb_pusch The number of RBs allocated (used for Resource Allocation Type 1 in NR)
@param frame_parms, Pointer to frame descriptor structure
- @param is_dmrs_symbol, flag to indicate wether this OFDM symbol contains DMRS symbols or not.
-
*/
void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
NR_gNB_PUSCH *pusch_vars,
@@ -80,7 +168,6 @@ void nr_ulsch_scale_channel(int32_t **ul_ch_estimates_ext,
uint16_t nb_rb,
pusch_dmrs_type_t pusch_dmrs_type);
-
/** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal
@param ul_ch_estimates_ext Channel estimates in allocated RBs
@param frame_parms Pointer to frame descriptor
@@ -95,7 +182,6 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext,
uint32_t len,
unsigned short nb_rb);
-
/** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation)
@param rxdataF_ext Frequency-domain received signal in RBs to be demodulated
@param ul_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated
@@ -195,20 +281,71 @@ void nr_fill_ulsch(PHY_VARS_gNB *gNB,
int slot,
nfapi_nr_pusch_pdu_t *ulsch_pdu);
-uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
+void nr_fill_prach(PHY_VARS_gNB *gNB,
+ int SFN,
+ int Slot,
+ nfapi_nr_prach_pdu_t *prach_pdu);
-uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
+void rx_nr_prach(PHY_VARS_gNB *gNB,
+ nfapi_nr_prach_pdu_t *prach_pdu,
+ int frame,
+ int subframe,
+ uint16_t *max_preamble,
+ uint16_t *max_preamble_energy,
+ uint16_t *max_preamble_delay);
-uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
+void rx_nr_prach_ru(RU_t *ru,
+ int prach_fmt,
+ int numRA,
+ int prachStartSymbol,
+ int frame,
+ int subframe);
-uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
+void nr_fill_prach_ru(RU_t *ru,
+ int SFN,
+ int Slot,
+ nfapi_nr_prach_pdu_t *prach_pdu);
-uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
+int16_t find_nr_prach(PHY_VARS_gNB *gNB,int frame,int slot, int numRA, find_type_t type);
+int16_t find_nr_prach_ru(RU_t *ru,int frame,int slot, find_type_t type);
-void rx_nr_prach(PHY_VARS_gNB *gNB,
- int frame,
- int subframe,
- uint16_t *max_preamble,
- uint16_t *max_preamble_energy,
- uint16_t *max_preamble_delay
- );
+NR_gNB_PUCCH_t *new_gNB_pucch(void);
+
+void nr_fill_pucch(PHY_VARS_gNB *gNB,
+ int frame,
+ int slot,
+ nfapi_nr_pucch_pdu_t *pucch_pdu);
+
+int nr_find_pucch(uint16_t rnti,
+ int frame,
+ int slot,
+ PHY_VARS_gNB *gNB);
+
+
+void init_prach_list(PHY_VARS_gNB *gNB);
+void init_prach_ru_list(RU_t *ru);
+void free_nr_ru_prach_entry(RU_t *ru, int prach_id);
+
+
+void nr_decode_pucch1(int32_t **rxdataF,
+ pucch_GroupHopping_t pucch_GroupHopping,
+ uint32_t n_id, // hoppingID higher layer parameter
+ uint64_t *payload,
+ NR_DL_FRAME_PARMS *frame_parms,
+ int16_t amp,
+ int nr_tti_tx,
+ uint8_t m0,
+ uint8_t nrofSymbols,
+ uint8_t startingSymbolIndex,
+ uint16_t startingPRB,
+ uint16_t startingPRB_intraSlotHopping,
+ uint8_t timeDomainOCC,
+ uint8_t nr_bit);
+
+void nr_decode_pucch0(PHY_VARS_gNB *gNB,
+ int slot,
+ nfapi_nr_uci_pucch_pdu_format_0_1_t* uci_pdu,
+ nfapi_nr_pucch_pdu_t* pucch_pdu);
+
+
+#endif /*__NR_TRANSPORT__H__*/
diff --git a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h b/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
deleted file mode 100644
index dd37455e2629898363ed1184151f7959200da1cd..0000000000000000000000000000000000000000
--- a/openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
+++ /dev/null
@@ -1,1760 +0,0 @@
-/*
- * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.
- * The OpenAirInterface Software Alliance licenses this file to You under
- * the OAI Public License, Version 1.1 (the "License"); you may not use this file
- * except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.openairinterface.org/?page_id=698
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *-------------------------------------------------------------------------------
- * For more information about the OpenAirInterface (OAI) Software Alliance:
- * contact@openairinterface.org
- */
-
-/*! \file PHY/NR_UE_TRANSPORT/transport_proto_ue.h
- * \brief Function prototypes for PHY physical/transport channel processing and generation V8.6 2009-03
- * \author R. Knopp, F. Kaltenberger
- * \date 2011
- * \version 0.1
- * \company Eurecom
- * \email: knopp@eurecom.fr
- * \note
- * \warning
- */
-#ifndef __NR_TRANSPORT_PROTO_UE__H__
-#define __NR_TRANSPORT_PROTO_UE__H__
-#include "PHY/defs_nr_UE.h"
-#include "SCHED_NR_UE/defs.h"
-//#include "PHY/LTE_TRANSPORT/transport_common_proto.h"
-#include <math.h>
-#include "nfapi_interface.h"
-
-// Functions below implement 36-211 and 36-212
-
-/** @addtogroup _PHY_TRANSPORT_
- * @{
- */
-
-/** \fn free_ue_dlsch(NR_UE_DLSCH_t *dlsch)
- \brief This function frees memory allocated for a particular DLSCH at UE
- @param dlsch Pointer to DLSCH to be removed
-*/
-void free_nr_ue_dlsch(NR_UE_DLSCH_t *dlsch);
-
-/** \fn new_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t abstraction_flag)
- \brief This function allocates structures for a particular DLSCH at UE
- @returns Pointer to DLSCH to be removed
- @param Kmimo Kmimo factor from 36-212/36-213
- @param Mdlharq Maximum number of HARQ rounds (36-212/36-213)
- @param Nsoft Soft-LLR buffer size from UE-Category
- @params N_RB_DL total number of resource blocks (determine the operating BW)
- @param abstraction_flag Flag to indicate abstracted interface
-*/
-NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint8_t max_turbo_iterations,uint8_t N_RB_DL, uint8_t abstraction_flag);
-
-
-void free_nr_ue_ulsch(NR_UE_ULSCH_t *ulsch);
-
-
-NR_UE_ULSCH_t *new_nr_ue_ulsch(unsigned char N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag);
-
-void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id);
-
-int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue,
- unsigned char eNB_id,
- uint8_t subframe,
- unsigned char symbol);
-
-/** \brief Dump OCTAVE/MATLAB files for PMCH debugging
- @param phy_vars_ue Pointer to UE variables
- @param eNB_id index of eNB in ue variables
- @param coded_bits_per_codeword G from 36.211
- @param subframe Index of subframe
- @returns 0 on success
-*/
-void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe);
-
-
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qpsk_qpsk(int16_t *stream0_in,
- int16_t *stream1_in,
- int16_t *stream0_out,
- int16_t *rho01,
- int32_t length);
-
-/** \brief This function perform LLR computation for dual-stream (QPSK/QPSK) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr128p pointer to pointer to symbol in dlsch_llr*/
-int32_t nr_dlsch_qpsk_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- int32_t **rho_i,
- int16_t *dlsch_llr,
- uint8_t symbol,
- uint32_t len,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- uint16_t pbch_pss_sss_adj,
- int16_t **llr128p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/16QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qpsk_qam16(int16_t *stream0_in,
- int16_t *stream1_in,
- short *ch_mag_i,
- int16_t *stream0_out,
- int16_t *rho01,
- int32_t length);
-
-/** \brief This function perform LLR computation for dual-stream (QPSK/16QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr128p pointer to pointer to symbol in dlsch_llr*/
-int32_t nr_dlsch_qpsk_16qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10})
- int32_t **rho_i,
- int16_t *dlsch_llr,
- uint8_t symbol,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- uint16_t pbch_pss_sss_adj,
- int16_t **llr128p);
-
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/64QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qpsk_qam64(int16_t *stream0_in,
- int16_t *stream1_in,
- short *ch_mag_i,
- int16_t *stream0_out,
- int16_t *rho01,
- int32_t length);
-
-/** \brief This function perform LLR computation for dual-stream (QPSK/64QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr128p pointer to pointer to symbol in dlsch_llr*/
-int32_t nr_dlsch_qpsk_64qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10})
- int32_t **rho_i,
- int16_t *dlsch_llr,
- uint8_t symbol,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- uint16_t pbch_pss_sss_adj,
- int16_t **llr128p);
-
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/QPSK reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam16_qpsk(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *stream0_out,
- short *rho01,
- int length);
-/** \brief This function perform LLR computation for dual-stream (16QAM/QPSK) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_16qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag, //|h_0|^2*(2/sqrt{10})
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- short **llr16p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/16QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam16_qam16(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *ch_mag_i,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function perform LLR computation for dual-stream (16QAM/16QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_16qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag, //|h_0|^2*(2/sqrt{10})
- int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10})
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- uint32_t len,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- short **llr16p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 16QAM/64QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam16_qam64(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *ch_mag_i,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function perform LLR computation for dual-stream (16QAM/64QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_16qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag, //|h_0|^2*(2/sqrt{10})
- int **dl_ch_mag_i, //|h_1|^2*(2/sqrt{10})
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- short **llr16p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam64_qpsk(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_64qam_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag,
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- short **llr16p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam64_qam16(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *ch_mag_i,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/16QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam64_qam16_avx2(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *ch_mag_i,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function perform LLR computation for dual-stream (64QAM/16QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_64qam_16qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag,
- int **dl_ch_mag_i,
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- short **llr16p);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam64_qam64(short *stream0_in,
- short *stream1_in,
- short *ch_mag,
- short *ch_mag_i,
- short *stream0_out,
- short *rho01,
- int length);
-
-/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream 64QAM/64QAM reception.
- @param stream0_in Input from channel compensated (MR combined) stream 0
- @param stream1_in Input from channel compensated (MR combined) stream 1
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param stream0_out Output from LLR unit for stream0
- @param rho01 Cross-correlation between channels (MR combined)
- @param length in complex channel outputs*/
-void qam64_qam64_avx2(int32_t *stream0_in,
- int32_t *stream1_in,
- int32_t *ch_mag,
- int32_t *ch_mag_i,
- int16_t *stream0_out,
- int32_t *rho01,
- int length);
-
-/** \brief This function perform LLR computation for dual-stream (64QAM/64QAM) transmission.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param ch_mag Input from scaled channel magnitude square of h0'*g0
- @param ch_mag_i Input from scaled channel magnitude square of h0'*g1
- @param rho_i Correlation between channel of signal and inteference
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag flag to indicate this is the first symbol of the dlsch
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr16p pointer to pointer to symbol in dlsch_llr*/
-int nr_dlsch_64qam_64qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **dl_ch_mag,
- int **dl_ch_mag_i,
- int **rho_i,
- short *dlsch_llr,
- unsigned char symbol,
- uint32_t len,
- unsigned char first_symbol_flag,
- unsigned short nb_rb,
- uint16_t pbch_pss_sss_adjust,
- //short **llr16p,
- uint32_t llr_offset);
-
-
-/** \brief This function generates log-likelihood ratios (decoder input) for single-stream QPSK received waveforms.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param dlsch_llr llr output
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adj Number of channel bits taken by PBCH/PSS/SSS
- @param llr128p pointer to pointer to symbol in dlsch_llr
- @param beamforming_mode beamforming mode
-*/
-int32_t nr_dlsch_qpsk_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int16_t *dlsch_llr,
- uint8_t symbol,
- uint32_t len,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- uint8_t beamforming_mode);
-
-/**
- \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param dlsch_llr llr output
- @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation and weighted for mid-point in 16QAM constellation
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adjust Adjustment factor in RE for PBCH/PSS/SSS allocations
- @param llr128p pointer to pointer to symbol in dlsch_llr
- @param beamforming_mode beamforming mode
-*/
-
-int32_t nr_dlsch_qpsk_llr_SIC(NR_DL_FRAME_PARMS *frame_parms,
- int **rxdataF_comp,
- int32_t **sic_buffer,
- int **rho_i,
- short *dlsch_llr,
- uint8_t num_pdcch_symbols,
- uint16_t nb_rb,
- uint8_t subframe,
- uint16_t mod_order_0,
- uint32_t rb_alloc);
-
-void nr_dlsch_16qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int16_t *dlsch_llr,
- int32_t **dl_ch_mag,
- uint8_t symbol,
- uint32_t len,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- int16_t **llr32p,
- uint8_t beamforming_mode);
-/**
- \brief This function generates log-likelihood ratios (decoder input) for single-stream 16QAM received waveforms
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param dlsch_llr llr output
- @param dl_ch_mag Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by first mid-point of 64-QAM constellation
- @param dl_ch_magb Squared-magnitude of channel in each resource element position corresponding to allocation, weighted by second mid-point of 64-QAM constellation
- @param symbol OFDM symbol index in sub-frame
- @param first_symbol_flag
- @param nb_rb number of RBs for this allocation
- @param pbch_pss_sss_adjust PBCH/PSS/SSS RE adjustment (in REs)
- @param beamforming_mode beamforming mode
-*/
-void nr_dlsch_16qam_llr_SIC (NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **sic_buffer, //Q15
- int32_t **rho_i,
- int16_t *dlsch_llr,
- uint8_t num_pdcch_symbols,
- int32_t **dl_ch_mag,
- uint16_t nb_rb,
- uint8_t subframe,
- uint16_t mod_order_0,
- uint32_t rb_alloc);
-
-void dlsch_64qam_llr_SIC(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **sic_buffer, //Q15
- int32_t **rho_i,
- int16_t *dlsch_llr,
- uint8_t num_pdcch_symbols,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint16_t nb_rb,
- uint8_t subframe,
- uint16_t mod_order_0,
- uint32_t rb_alloc);
-
-void nr_dlsch_64qam_llr(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int16_t *dlsch_llr,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint32_t len,
- uint8_t first_symbol_flag,
- uint16_t nb_rb,
- uint32_t llr_offset,
- uint8_t beamforming_mode);
-
-
-/** \fn dlsch_siso(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- uint8_t l,
- uint16_t nb_rb)
- \brief This function does the first stage of llr computation for SISO, by just extracting the pilots, PBCH and primary/secondary synchronization sequences.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param l symbol in sub-frame
- @param nb_rb Number of RBs in this allocation
-*/
-
-void dlsch_siso(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- uint8_t l,
- uint16_t nb_rb);
-
-/** \fn dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint16_t nb_rb)
- \brief This function does Alamouti combining on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param symbol Symbol in sub-frame
- @param nb_rb Number of RBs in this allocation
-*/
-void dlsch_alamouti(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint16_t nb_rb);
-
-/** \fn dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint16_t nb_rb)
- \brief This function does antenna selection (based on antenna cycling pattern) on RX and prepares LLR inputs by skipping pilots, PBCH and primary/secondary synchronization signals. Note that this is not LTE, it is just included for comparison purposes.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param symbol Symbol in sub-frame
- @param nb_rb Number of RBs in this allocation
-*/
-void dlsch_antcyc(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint16_t nb_rb);
-
-/** \fn dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- int32_t **rho,
- int32_t **rho_i,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- uint8_t symbol,
- uint16_t nb_rb,
- uint8_t dual_stream_UE)
-
- \brief This function does maximal-ratio combining for dual-antenna receivers.
- @param frame_parms Frame descriptor structure
- @param rxdataF_comp Compensated channel output
- @param rxdataF_comp_i Compensated channel output for interference
- @param rho Cross correlation between spatial channels
- @param rho_i Cross correlation between signal and inteference channels
- @param dl_ch_mag First squared-magnitude of channel (16QAM and 64QAM) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param dl_ch_magb Second squared-magnitude of channel (64QAM only) for LLR computation. Alamouti combining should be performed on this as well. Result is stored in first antenna position
- @param symbol Symbol in sub-frame
- @param nb_rb Number of RBs in this allocation
- @param dual_stream_UE Flag to indicate dual-stream detection
-*/
-void dlsch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms,
- int32_t **rxdataF_comp,
- int32_t **rxdataF_comp_i,
- int32_t **rho,
- int32_t **rho_i,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- int32_t **dl_ch_mag_i,
- int32_t **dl_ch_magb_i,
- uint8_t symbol,
- uint16_t nb_rb,
- uint8_t dual_stream_UE);
-
-void dlsch_detection_mrc_TM34(NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_PDSCH *lte_ue_pdsch_vars,
- int harq_pid,
- int round,
- unsigned char symbol,
- unsigned short nb_rb,
- unsigned char dual_stream_UE);
-
-/** \fn dlsch_extract_rbs_single(int32_t **rxdataF,
- int32_t **dl_ch_estimates,
- int32_t **rxdataF_ext,
- int32_t **dl_ch_estimates_ext,
- uint16_t pmi,
- uint8_t *pmi_ext,
- uint32_t *rb_alloc,
- uint8_t symbol,
- uint8_t subframe,
- NR_DL_FRAME_PARMS *frame_parms)
- \brief This function extracts the received resource blocks, both channel estimates and data symbols,
- for the current allocation and for single antenna eNB transmission.
- @param rxdataF Raw FFT output of received signal
- @param dl_ch_estimates Channel estimates of current slot
- @param rxdataF_ext FFT output for RBs in this allocation
- @param dl_ch_estimates_ext Channel estimates for RBs in this allocation
- @param pmi subband Precoding matrix indicator
- @param pmi_ext Extracted PMI for chosen RBs
- @param rb_alloc RB allocation vector
- @param symbol Symbol to extract
- @param subframe Subframe number
- @param vrb_type Flag to indicate distributed VRB type
- @param high_speed_flag
- @param frame_parms Pointer to frame descriptor
-*/
-/*uint16_t nr_dlsch_extract_rbs_single(int32_t **rxdataF,
- int32_t **dl_ch_estimates,
- int32_t **rxdataF_ext,
- int32_t **dl_ch_estimates_ext,
- uint16_t pmi,
- uint8_t *pmi_ext,
- uint32_t *rb_alloc,
- uint8_t symbol,
- uint8_t subframe,
- uint32_t high_speed_flag,
- NR_DL_FRAME_PARMS *frame_parms);*/
-
-unsigned short nr_dlsch_extract_rbs_single(int **rxdataF,
- int **dl_ch_estimates,
- int **rxdataF_ext,
- int **dl_ch_estimates_ext,
- unsigned short pmi,
- unsigned char *pmi_ext,
- unsigned char symbol,
- uint8_t pilots,
- unsigned short start_rb,
- unsigned short nb_pdsch_rb,
- unsigned char nr_tti_rx,
- uint32_t high_speed_flag,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/** \fn dlsch_extract_rbs_dual(int32_t **rxdataF,
- int32_t **dl_ch_estimates,
- int32_t **rxdataF_ext,
- int32_t **dl_ch_estimates_ext,
- uint16_t pmi,
- uint8_t *pmi_ext,
- uint32_t *rb_alloc,
- uint8_t symbol,
- NR_DL_FRAME_PARMS *frame_parms)
- \brief This function extracts the received resource blocks, both channel estimates and data symbols,
- for the current allocation and for dual antenna eNB transmission.
- @param rxdataF Raw FFT output of received signal
- @param dl_ch_estimates Channel estimates of current slot
- @param rxdataF_ext FFT output for RBs in this allocation
- @param dl_ch_estimates_ext Channel estimates for RBs in this allocation
- @param pmi subband Precoding matrix indicator
- @param pmi_ext Extracted PMI for chosen RBs
- @param rb_alloc RB allocation vector
- @param symbol Symbol to extract
- @param subframe Subframe index
- @param high_speed_flag
- @param frame_parms Pointer to frame descriptor
-*/
-unsigned short nr_dlsch_extract_rbs_dual(int **rxdataF,
- int **dl_ch_estimates,
- int **rxdataF_ext,
- int **dl_ch_estimates_ext,
- unsigned short pmi,
- unsigned char *pmi_ext,
- unsigned char symbol,
- uint8_t pilots,
- unsigned short start_rb,
- unsigned short nb_rb_pdsch,
- unsigned char nr_tti_rx,
- uint32_t high_speed_flag,
- NR_DL_FRAME_PARMS *frame_parms,
- MIMO_mode_t mimo_mode);
-
-/** \fn dlsch_extract_rbs_TM7(int32_t **rxdataF,
- int32_t **dl_bf_ch_estimates,
- int32_t **rxdataF_ext,
- int32_t **dl_bf_ch_estimates_ext,
- uint32_t *rb_alloc,
- uint8_t symbol,
- uint8_t subframe,
- uint32_t high_speed_flag,
- NR_DL_FRAME_PARMS *frame_parms)
- \brief This function extracts the received resource blocks, both channel estimates and data symbols,
- for the current allocation and for single antenna eNB transmission.
- @param rxdataF Raw FFT output of received signal
- @param dl_bf_ch_estimates Beamforming channel estimates of current slot
- @param rxdataF_ext FFT output for RBs in this allocation
- @param dl_bf_ch_estimates_ext Beamforming channel estimates for RBs in this allocation
- @param rb_alloc RB allocation vector
- @param symbol Symbol to extract
- @param subframe Subframe number
- @param high_speed_flag
- @param frame_parms Pointer to frame descriptor
-*/
-uint16_t dlsch_extract_rbs_TM7(int32_t **rxdataF,
- int32_t **dl_bf_ch_estimates,
- int32_t **rxdataF_ext,
- int32_t **dl_bf_ch_estimates_ext,
- uint32_t *rb_alloc,
- uint8_t symbol,
- uint8_t subframe,
- uint32_t high_speed_flag,
- NR_DL_FRAME_PARMS *frame_parms);
-
-/** \brief This function performs channel compensation (matched filtering) on the received RBs for this allocation. In addition, it computes the squared-magnitude of the channel with weightings for 16QAM/64QAM detection as well as dual-stream detection (cross-correlation)
- @param rxdataF_ext Frequency-domain received signal in RBs to be demodulated
- @param dl_ch_estimates_ext Frequency-domain channel estimates in RBs to be demodulated
- @param dl_ch_mag First Channel magnitudes (16QAM/64QAM)
- @param dl_ch_magb Second weighted Channel magnitudes (64QAM)
- @param rxdataF_comp Compensated received waveform
- @param rho Cross-correlation between two spatial channels on each RX antenna
- @param frame_parms Pointer to frame descriptor
- @param symbol Symbol on which to operate
- @param first_symbol_flag set to 1 on first DLSCH symbol
- @param mod_order Modulation order of allocation
- @param nb_rb Number of RBs in allocation
- @param output_shift Rescaling for compensated output (should be energy-normalizing)
- @param phy_measurements Pointer to UE PHY measurements
-*/
-void nr_dlsch_channel_compensation(int32_t **rxdataF_ext,
- int32_t **dl_ch_estimates_ext,
- int32_t **dl_ch_mag,
- int32_t **dl_ch_magb,
- int32_t **rxdataF_comp,
- int32_t **rho,
- NR_DL_FRAME_PARMS *frame_parms,
- uint8_t symbol,
- uint8_t start_symbol,
- uint8_t first_symbol_flag,
- uint8_t mod_order,
- uint16_t nb_rb,
- uint8_t output_shift,
- PHY_NR_MEASUREMENTS *phy_measurements);
-
-void nr_dlsch_channel_compensation_core(int **rxdataF_ext,
- int **dl_ch_estimates_ext,
- int **dl_ch_mag,
- int **dl_ch_magb,
- int **rxdataF_comp,
- int **rho,
- unsigned char n_tx,
- unsigned char n_rx,
- unsigned char mod_order,
- unsigned char output_shift,
- int length,
- int start_point);
-
-void nr_dlsch_deinterleaving(uint8_t symbol,
- uint8_t start_symbol,
- uint16_t L,
- uint16_t *llr,
- uint16_t *llr_deint,
- uint16_t nb_rb_pdsch);
-
-void dlsch_dual_stream_correlation(NR_DL_FRAME_PARMS *frame_parms,
- unsigned char symbol,
- unsigned short nb_rb,
- int **dl_ch_estimates_ext,
- int **dl_ch_estimates_ext_i,
- int **dl_ch_rho_ext,
- unsigned char output_shift);
-
-void dlsch_dual_stream_correlationTM34(NR_DL_FRAME_PARMS *frame_parms,
- unsigned char symbol,
- unsigned short nb_rb,
- int **dl_ch_estimates_ext,
- int **dl_ch_estimates_ext_i,
- int **dl_ch_rho_ext,
- unsigned char output_shift0,
- unsigned char output_shift1);
-//This function is used to compute multiplications in Hhermitian * H matrix
-void conjch0_mult_ch1(int *ch0,
- int *ch1,
- int32_t *ch0conj_ch1,
- unsigned short nb_rb,
- unsigned char output_shift0);
-
-void construct_HhH_elements(int *ch0conj_ch0,
- int *ch1conj_ch1,
- int *ch2conj_ch2,
- int *ch3conj_ch3,
- int *ch0conj_ch1,
- int *ch1conj_ch0,
- int *ch2conj_ch3,
- int *ch3conj_ch2,
- int32_t *after_mf_00,
- int32_t *after_mf_01,
- int32_t *after_mf_10,
- int32_t *after_mf_11,
- unsigned short nb_rb);
-
-void squared_matrix_element(int32_t *Hh_h_00,
- int32_t *Hh_h_00_sq,
- unsigned short nb_rb);
-
-void dlsch_channel_level_TM34_meas(int *ch00,
- int *ch01,
- int *ch10,
- int *ch11,
- int *avg_0,
- int *avg_1,
- unsigned short nb_rb);
-
-void nr_dlsch_channel_level_median(int **dl_ch_estimates_ext,
- int32_t *median,
- int n_tx,
- int n_rx,
- int length,
- int start_point);
-
-void nr_dlsch_detection_mrc_core(int **rxdataF_comp,
- int **rxdataF_comp_i,
- int **rho,
- int **rho_i,
- int **dl_ch_mag,
- int **dl_ch_magb,
- int **dl_ch_mag_i,
- int **dl_ch_magb_i,
- unsigned char n_tx,
- unsigned char n_rx,
- int length,
- int start_point);
-
-void det_HhH(int32_t *after_mf_00,
- int32_t *after_mf_01,
- int32_t *after_mf_10,
- int32_t *after_mf_11,
- int32_t *det_fin_128,
- unsigned short nb_rb);
-
-void numer(int32_t *Hh_h_00_sq,
- int32_t *Hh_h_01_sq,
- int32_t *Hh_h_10_sq,
- int32_t *Hh_h_11_sq,
- int32_t *num_fin,
- unsigned short nb_rb);
-
-uint8_t rank_estimation_tm3_tm4(int *dl_ch_estimates_00,
- int *dl_ch_estimates_01,
- int *dl_ch_estimates_10,
- int *dl_ch_estimates_11,
- unsigned short nb_rb);
-
-void dlsch_channel_compensation_TM56(int **rxdataF_ext,
- int **dl_ch_estimates_ext,
- int **dl_ch_mag,
- int **dl_ch_magb,
- int **rxdataF_comp,
- unsigned char *pmi_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- PHY_NR_MEASUREMENTS *phy_measurements,
- int eNB_id,
- unsigned char symbol,
- unsigned char mod_order,
- unsigned short nb_rb,
- unsigned char output_shift,
- unsigned char dl_power_off);
-
-
-void dlsch_channel_compensation_TM34(NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_PDSCH *lte_ue_pdsch_vars,
- PHY_NR_MEASUREMENTS *phy_measurements,
- int eNB_id,
- unsigned char symbol,
- unsigned char mod_order0,
- unsigned char mod_order1,
- int harq_pid,
- int round,
- MIMO_mode_t mimo_mode,
- unsigned short nb_rb,
- unsigned char output_shift0,
- unsigned char output_shift1);
-
-
-/** \brief This function computes the average channel level over all allocated RBs and antennas (TX/RX) in order to compute output shift for compensated signal
- @param dl_ch_estimates_ext Channel estimates in allocated RBs
- @param frame_parms Pointer to frame descriptor
- @param avg Pointer to average signal strength
- @param pilots_flag Flag to indicate pilots in symbol
- @param nb_rb Number of allocated RBs
-*/
-void nr_dlsch_channel_level(int **dl_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- int32_t *avg,
- uint8_t symbol,
- uint32_t len,
- unsigned short nb_rb);
-
-
-void dlsch_channel_level_TM34(int **dl_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- unsigned char *pmi_ext,
- int *avg_0,
- int *avg_1,
- uint8_t symbol,
- unsigned short nb_rb,
- MIMO_mode_t mimo_mode);
-
-
-void dlsch_channel_level_TM56(int32_t **dl_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- unsigned char *pmi_ext,
- int32_t *avg,
- uint8_t symbol_mod,
- uint16_t nb_rb);
-
-void dlsch_channel_level_TM7(int32_t **dl_bf_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- int32_t *avg,
- uint8_t pilots_flag,
- uint16_t nb_rb);
-
-void nr_dlsch_scale_channel(int32_t **dl_ch_estimates_ext,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t **dlsch_ue,
- uint8_t symbol,
- uint8_t start_symbol,
- uint16_t nb_rb);
-
-/** \brief This is the top-level entry point for DLSCH decoding in UE. It should be replicated on several
- threads (on multi-core machines) corresponding to different HARQ processes. The routine first
- computes the segmentation information, followed by rate dematching and sub-block deinterleaving the of the
- received LLRs computed by dlsch_demodulation for each transport block segment. It then calls the
- turbo-decoding algorithm for each segment and stops after either after unsuccesful decoding of at least
- one segment or correct decoding of all segments. Only the segment CRCs are check for the moment, the
- overall CRC is ignored. Finally transport block reassembly is performed.
- @param phy_vars_ue Pointer to ue variables
- @param dlsch_llr Pointer to LLR values computed by dlsch_demodulation
- @param lte_frame_parms Pointer to frame descriptor
- @param dlsch Pointer to DLSCH descriptor
- @param frame Frame number
- @param subframe Subframe number
- @param num_pdcch_symbols Number of PDCCH symbols
- @param is_crnti indicates if PDSCH belongs to a CRNTI (necessary for parallelizing decoding threads)
- @param llr8_flag If 1, indicate that the 8-bit turbo decoder should be used
- @returns 0 on success, 1 on unsuccessful decoding
-*/
-
-uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
- short *dlsch_llr,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t *dlsch,
- NR_DL_UE_HARQ_t *harq_process,
- uint32_t frame,
- uint16_t nb_symb_sch,
- uint8_t nr_tti_rx,
- uint8_t harq_pid,
- uint8_t is_crnti,
- uint8_t llr8_flag);
-
-int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
- NR_DL_FRAME_PARMS* frame_parms,
- uint8_t harq_pid);
-
-/*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1
- @param[in] in Pointer to input bits
- @param[in] size of input bits
- @param[in] Nid cell id
- @param[in] n_RNTI CRNTI
- @param[out] out the scrambled bits
-*/
-
-void nr_pusch_codeword_scrambling(uint8_t *in,
- uint16_t size,
- uint32_t Nid,
- uint32_t n_RNTI,
- uint32_t* out);
-
-
-uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
- UE_nr_rxtx_proc_t *proc,
- int eNB_id,
- short *dlsch_llr,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t *dlsch,
- NR_DL_UE_HARQ_t *harq_process,
- uint32_t frame,
- uint16_t nb_symb_sch,
- uint8_t nr_tti_rx,
- uint8_t harq_pid,
- uint8_t is_crnti,
- uint8_t llr8_flag);
-
-void *nr_dlsch_decoding_2thread0(void *arg);
-
-void *nr_dlsch_decoding_2thread1(void *arg);
-
-void nr_dlsch_unscrambling(int16_t* llr,
- uint32_t size,
- uint8_t q,
- uint32_t Nid,
- uint32_t n_RNTI);
-
-uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue,
- uint8_t subframe,
- PDSCH_t dlsch_id,
- uint8_t eNB_id);
-
-/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs
- - RB extraction (signal and channel estimates)
- - channel compensation (matched filtering)
- - RE extraction (pilot, PBCH, synch. signals)
- - antenna combining (MRC, Alamouti, cycling)
- - LLR computation
- This function supports TM1, 2, 3, 5, and 6.
- @param PHY_VARS_NR_UE Pointer to PHY variables
- @param type Type of PDSCH (SI_PDSCH,RA_PDSCH,PDSCH,PMCH)
- @param eNB_id eNb index (Nid1) 0,1,2
- @param eNB_id_i Interfering eNB index (Nid1) 0,1,2, or 3 in case of MU-MIMO IC receiver
- @param subframe Subframe number
- @param symbol Symbol on which to act (within sub-frame)
- @param first_symbol_flag set to 1 on first DLSCH symbol
- @param rx_type. rx_type=RX_IC_single_stream will enable interference cancellation of a second stream when decoding the first stream. In case of TM1, 2, 5, and this can cancel interference from a neighbouring cell given by eNB_id_i. In case of TM5, eNB_id_i should be set to n_connected_eNB to perform multi-user interference cancellation. In case of TM3, eNB_id_i should be set to eNB_id to perform co-channel interference cancellation; this option should be used together with an interference cancellation step [...]. In case of TM3, if rx_type=RX_IC_dual_stream, both streams will be decoded by applying the IC single stream receiver twice.
- @param i_mod Modulation order of the interfering stream
-*/
-int32_t nr_rx_pdsch(PHY_VARS_NR_UE *phy_vars_ue,
- PDSCH_t type,
- uint8_t eNB_id,
- uint8_t eNB_id_i,
- uint32_t frame,
- uint8_t subframe,
- uint8_t symbol,
- uint8_t first_symbol_flag,
- RX_type_t rx_type,
- uint8_t i_mod,
- uint8_t harq_pid);
-
-int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
- uint32_t frame,
- uint8_t nr_tti_rx,
- uint8_t eNB_id,
- MIMO_mode_t mimo_mode,
- uint32_t high_speed_flag,
- uint8_t is_secondary_ue,
- int nb_coreset_active,
- uint16_t symbol_mon,
- NR_SEARCHSPACE_TYPE_t searchSpaceType);
-
-/*! \brief Extract PSS and SSS resource elements
- @param phy_vars_ue Pointer to UE variables
- @param[out] pss_ext contain the PSS signals after the extraction
- @param[out] sss_ext contain the SSS signals after the extraction
- @returns 0 on success
-*/
-int pss_sss_extract(PHY_VARS_NR_UE *phy_vars_ue,
- int32_t pss_ext[4][72],
- int32_t sss_ext[4][72],
- uint8_t subframe);
-
-/*! \brief Extract only PSS resource elements
- @param phy_vars_ue Pointer to UE variables
- @param[out] pss_ext contain the PSS signals after the extraction
- @returns 0 on success
-*/
-int pss_only_extract(PHY_VARS_NR_UE *phy_vars_ue,
- int32_t pss_ext[4][72],
- uint8_t subframe);
-
-/*! \brief Extract only SSS resource elements
- @param phy_vars_ue Pointer to UE variables
- @param[out] sss_ext contain the SSS signals after the extraction
- @returns 0 on success
-*/
-int sss_only_extract(PHY_VARS_NR_UE *phy_vars_ue,
- int32_t sss_ext[4][72],
- uint8_t subframe);
-
-/*! \brief Performs detection of SSS to find cell ID and other framing parameters (FDD/TDD, normal/extended prefix)
- @param phy_vars_ue Pointer to UE variables
- @param tot_metric Pointer to variable containing maximum metric under framing hypothesis (to be compared to other hypotheses
- @param flip_max Pointer to variable indicating if start of frame is in second have of RX buffer (i.e. PSS/SSS is flipped)
- @param phase_max Pointer to variable (0 ... 6) containing rought phase offset between PSS and SSS (can be used for carrier
- frequency adjustment. 0 means -pi/3, 6 means pi/3.
- @returns 0 on success
-*/
-int rx_sss(PHY_VARS_NR_UE *phy_vars_ue,int32_t *tot_metric,uint8_t *flip_max,uint8_t *phase_max);
-
-/*! \brief receiver for the PBCH
- \returns number of tx antennas or -1 if error
-*/
-int nr_rx_pbch( PHY_VARS_NR_UE *ue,
- UE_nr_rxtx_proc_t *proc,
- NR_UE_PBCH *nr_ue_pbch_vars,
- NR_DL_FRAME_PARMS *frame_parms,
- uint8_t eNB_id,
- uint8_t i_ssb,
- MIMO_mode_t mimo_mode,
- uint32_t high_speed_flag);
-
-int nr_pbch_detection(UE_nr_rxtx_proc_t *proc,
- PHY_VARS_NR_UE *ue,
- int pbch_initial_symbol,
- runmode_t mode);
-
-uint16_t rx_pbch_emul(PHY_VARS_NR_UE *phy_vars_ue,
- uint8_t eNB_id,
- uint8_t pbch_phase);
-
-
-/*! \brief PBCH unscrambling
- This is similar to pbch_scrabling with the difference that inputs are signed s16s (llr values) and instead of flipping bits we change signs.
- \param frame_parms Pointer to frame descriptor
- \param llr Output of the demodulator
- \param length Length of the sequence
- \param frame_mod4 Frame number modulo 4*/
-void pbch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
- int8_t* llr,
- uint32_t length,
- uint8_t frame_mod4);
-
-
-void generate_64qam_table(void);
-void generate_16qam_table(void);
-void generate_qpsk_table(void);
-
-uint16_t extract_crc(uint8_t *dci,uint8_t DCI_LENGTH);
-
-/*! \brief LLR from two streams. This function takes two streams (qpsk modulated) and calculates the LLR, considering one stream as interference.
- \param stream0_in pointer to first stream0
- \param stream1_in pointer to first stream1
- \param stream0_out pointer to output stream
- \param rho01 pointer to correlation matrix
- \param length*/
-void qpsk_qpsk_TM3456(short *stream0_in,
- short *stream1_in,
- short *stream0_out,
- short *rho01,
- int length
- );
-
-/** \brief Attempt decoding of a particular DCI with given length and format.
- @param DCI_LENGTH length of DCI in bits
- @param DCI_FMT Format of DCI
- @param e e-sequence (soft bits)
- @param decoded_output Output of Viterbi decoder
-*/
-void dci_decoding(uint8_t DCI_LENGTH,
- uint8_t DCI_FMT,
- int8_t *e,
- uint8_t *decoded_output);
-
-/** \brief Do 36.213 DCI decoding procedure by searching different RNTI options and aggregation levels. Currently does
- not employ the complexity reducing procedure based on RNTI.
- @param phy_vars_ue UE variables
- @param dci_alloc Pointer to DCI_ALLOC_t array to store results for DLSCH/ULSCH programming
- @param do_common If 1 perform search in common search-space else ue-specific search-space
- @param eNB_id eNB Index on which to act
- @param subframe Index of subframe
- @returns bitmap of occupied CCE positions (i.e. those detected)
-*/
-uint16_t dci_decoding_procedure(PHY_VARS_NR_UE *phy_vars_ue,
- DCI_ALLOC_t *dci_alloc,
- int do_common,
- int16_t eNB_id,
- uint8_t subframe);
-
-uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_NR_UE *ue,
- DCI_ALLOC_t *dci_alloc,
- uint8_t DCIFormat,
- uint8_t agregationLevel,
- int16_t eNB_id,
- uint8_t subframe);
-
-uint16_t dci_decoding_procedure_emul(NR_UE_PDCCH **lte_ue_pdcch_vars,
- uint8_t num_ue_spec_dci,
- uint8_t num_common_dci,
- DCI_ALLOC_t *dci_alloc_tx,
- DCI_ALLOC_t *dci_alloc_rx,
- int16_t eNB_id);
-
-/** \brief Compute Q (modulation order) based on I_MCS PDSCH. Implements table 7.1.7.1-1 from 36.213.
- @param I_MCS */
-uint8_t get_Qm(uint8_t I_MCS);
-
-/** \brief Compute Q (modulation order) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213.
- @param I_MCS */
-uint8_t get_Qm_ul(uint8_t I_MCS);
-
-/** \brief Compute I_TBS (transport-block size) based on I_MCS for PDSCH. Implements table 7.1.7.1-1 from 36.213.
- @param I_MCS */
-uint8_t get_I_TBS(uint8_t I_MCS);
-
-/** \brief Compute I_TBS (transport-block size) based on I_MCS for PUSCH. Implements table 8.6.1-1 from 36.213.
- @param I_MCS */
-unsigned char get_I_TBS_UL(unsigned char I_MCS);
-
-/** \brief Compute Q (modulation order) based on downlink I_MCS. Implements table 7.1.7.1-1 from 36.213.
- @param I_MCS
- @param nb_rb
- @return Transport block size */
-uint32_t get_TBS_DL(uint8_t mcs, uint16_t nb_rb);
-
-/** \brief Compute Q (modulation order) based on uplink I_MCS. Implements table 7.1.7.1-1 from 36.213.
- @param I_MCS
- @param nb_rb
- @return Transport block size */
-uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb);
-
-/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type
- @param N_RB_DL number of PRB on DL
- @param indicator for even/odd slot
- @param vrb vrb index
- @param Ngap Gap indicator
-*/
-uint32_t get_prb(int N_RB_DL,int odd_slot,int vrb,int Ngap);
-
-/* \brief Return prb for a given vrb index
- @param vrb_type VRB type (0=localized,1=distributed)
- @param rb_alloc_dci rballoc field from DCI
-*/
-uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci);
-
-
-/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type
- @returns Transmission mode (1-7)
-*/
-uint8_t get_transmission_mode(module_id_t Mod_id, uint8_t CC_id, rnti_t rnti);
-
-
-/* \brief
- @param ra_header Header of resource allocation (0,1) (See sections 7.1.6.1/7.1.6.2 of 36.213 Rel8.6)
- @param rb_alloc Bitmap allocation from DCI (format 1,2)
- @returns number of physical resource blocks
-*/
-uint32_t conv_nprb(uint8_t ra_header,uint32_t rb_alloc,int N_RB_DL);
-
-int get_G(NR_DL_FRAME_PARMS *frame_parms,uint16_t nb_rb,uint32_t *rb_alloc,uint8_t mod_order,uint8_t Nl,uint8_t num_pdcch_symbols,int frame,uint8_t subframe, uint8_t beamforming_mode);
-
-int adjust_G(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe);
-int adjust_G2(NR_DL_FRAME_PARMS *frame_parms,uint32_t *rb_alloc,uint8_t mod_order,uint8_t subframe,uint8_t symbol);
-
-
-#ifndef modOrder
-#define modOrder(I_MCS,I_TBS) ((I_MCS-I_TBS)*2+2) // Find modulation order from I_TBS and I_MCS
-#endif
-
-/** \fn uint8_t I_TBS2I_MCS(uint8_t I_TBS);
- \brief This function maps I_tbs to I_mcs according to Table 7.1.7.1-1 in 3GPP TS 36.213 V8.6.0. Where there is two supported modulation orders for the same I_TBS then either high or low modulation is chosen by changing the equality of the two first comparisons in the if-else statement.
- \param I_TBS Index of Transport Block Size
- \return I_MCS given I_TBS
-*/
-uint8_t I_TBS2I_MCS(uint8_t I_TBS);
-
-/** \fn uint8_t SE2I_TBS(float SE,
- uint8_t N_PRB,
- uint8_t symbPerRB);
- \brief This function maps a requested throughput in number of bits to I_tbs. The throughput is calculated as a function of modulation order, RB allocation and number of symbols per RB. The mapping orginates in the "Transport block size table" (Table 7.1.7.2.1-1 in 3GPP TS 36.213 V8.6.0)
- \param SE Spectral Efficiency (before casting to integer, multiply by 1024, remember to divide result by 1024!)
- \param N_PRB Number of PhysicalResourceBlocks allocated \sa lte_frame_parms->N_RB_DL
- \param symbPerRB Number of symbols per resource block allocated to this channel
- \return I_TBS given an SE and an N_PRB
-*/
-uint8_t SE2I_TBS(float SE,
- uint8_t N_PRB,
- uint8_t symbPerRB);
-/** \brief This function generates the sounding reference symbol (SRS) for the uplink according to 36.211 v8.6.0. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence.
- @param frame_parms LTE DL Frame Parameters
- @param soundingrs_ul_config_dedicated Dynamic configuration from RRC during Connection Establishment
- @param txdataF pointer to the frequency domain TX signal
- @returns 0 on success*/
-int generate_srs(NR_DL_FRAME_PARMS *frame_parms,
- SOUNDINGRS_UL_CONFIG_DEDICATED *soundingrs_ul_config_dedicated,
- int *txdataF,
- int16_t amp,
- uint32_t subframe);
-
-
-/*!
- \brief This function is similar to generate_srs_tx but generates a conjugate sequence for channel estimation. If IFFT_FPGA is defined, the SRS is quantized to a QPSK sequence.
- @param phy_vars_ue Pointer to PHY_VARS structure
- @param eNB_id Index of destination eNB for this SRS
- @param amp Linear amplitude of SRS
- @param subframe Index of subframe on which to act
- @returns 0 on success, -1 on error with message
-*/
-
-int32_t generate_srs_tx(PHY_VARS_NR_UE *phy_vars_ue,
- uint8_t eNB_id,
- int16_t amp,
- uint32_t subframe);
-
-/*!
- \brief This function generates the downlink reference signal for the PUSCH according to 36.211 v8.6.0. The DRS occuies the RS defined by rb_alloc and the symbols 2 and 8 for extended CP and 3 and 10 for normal CP.
-*/
-
-int32_t generate_drs_pusch(PHY_VARS_NR_UE *phy_vars_ue,
- UE_nr_rxtx_proc_t *proc,
- uint8_t eNB_id,
- int16_t amp,
- uint32_t subframe,
- uint32_t first_rb,
- uint32_t nb_rb,
- uint8_t ant);
-
-/*!
- \brief This function initializes the Group Hopping, Sequence Hopping and nPRS sequences for PUCCH/PUSCH according to 36.211 v8.6.0. It should be called after configuration of UE (reception of SIB2/3) and initial configuration of eNB (or after reconfiguration of cell-specific parameters).
- @param frame_parms Pointer to a NR_DL_FRAME_PARMS structure (eNB or UE)*/
-void init_ul_hopping(NR_DL_FRAME_PARMS *frame_parms);
-
-
-/*!
- \brief This function implements the initialization of paging parameters for UE (See Section 7, 36.304).It must be called after setting IMSImod1024 during UE startup and after receiving SIB2
- @param ue Pointer to UE context
- @param defaultPagingCycle T from 36.304 (0=32,1=64,2=128,3=256)
- @param nB nB from 36.304 (0=4T,1=2T,2=T,3=T/2,4=T/4,5=T/8,6=T/16,7=T/32*/
-int init_ue_paging_info(PHY_VARS_NR_UE *ue, long defaultPagingCycle, long nB);
-
-int32_t compareints (const void * a, const void * b);
-
-
-void ulsch_modulation(int32_t **txdataF,
- int16_t amp,
- frame_t frame,
- uint32_t subframe,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_ULSCH_t *ulsch);
-
-
-
-
-
-
-int generate_ue_dlsch_params_from_dci(int frame,
- uint8_t subframe,
- void *dci_pdu,
- rnti_t rnti,
- DCI_format_t dci_format,
- NR_UE_PDCCH *pdcch_vars,
- NR_UE_PDSCH *pdsch_vars,
- NR_UE_DLSCH_t **dlsch,
- NR_DL_FRAME_PARMS *frame_parms,
- PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- uint16_t si_rnti,
- uint16_t ra_rnti,
- uint16_t p_rnti,
- uint8_t beamforming_mode,
- uint16_t tc_rnti);
-
-
-int generate_ue_ulsch_params_from_dci(void *dci_pdu,
- rnti_t rnti,
- uint8_t subframe,
- DCI_format_t dci_format,
- PHY_VARS_NR_UE *phy_vars_ue,
- UE_nr_rxtx_proc_t *proc,
- uint16_t si_rnti,
- uint16_t ra_rnti,
- uint16_t p_rnti,
- uint16_t cba_rnti,
- uint8_t eNB_id,
- uint8_t use_srs);
-
-int32_t generate_ue_ulsch_params_from_rar(PHY_VARS_NR_UE *phy_vars_ue,
- UE_nr_rxtx_proc_t *proc,
- uint8_t eNB_id);
-double sinr_eff_cqi_calc(PHY_VARS_NR_UE *phy_vars_ue,
- uint8_t eNB_id,
- uint8_t subframe);
-
-uint8_t sinr2cqi(double sinr,uint8_t trans_mode);
-
-
-int dump_dci(NR_DL_FRAME_PARMS *frame_parms, DCI_ALLOC_t *dci);
-
-int dump_ue_stats(PHY_VARS_NR_UE *phy_vars_ue, UE_nr_rxtx_proc_t *proc, char* buffer, int length, runmode_t mode, int input_level_dBm);
-
-void init_transport_channels(uint8_t);
-
-void generate_RIV_tables(void);
-
-/*!
- \brief This function performs the initial cell search procedure - PSS detection, SSS detection and PBCH detection. At the
- end, the basic frame parameters are known (Frame configuration - TDD/FDD and cyclic prefix length,
- N_RB_DL, PHICH_CONFIG and Nid_cell) and the UE can begin decoding PDCCH and DLSCH SI to retrieve the rest. Once these
- parameters are know, the routine calls some basic initialization routines (cell-specific reference signals, etc.)
- @param phy_vars_ue Pointer to UE variables
- @param mode current running mode
-*/
-int nr_initial_sync(UE_nr_rxtx_proc_t *proc,
- PHY_VARS_NR_UE *phy_vars_ue, runmode_t mode);
-
-
-/*!
- \brief Encoding of PUSCH/ACK/RI/ACK from 36-212.
- @param a Pointer to ulsch SDU
- @param frame_parms Pointer to Frame parameters
- @param ulsch Pointer to ulsch descriptor
- @param harq_pid HARQ process ID
- @param tmode Transmission mode (1-7)
- @param control_only_flag Generate PUSCH with control information only
- @param Nbundled Parameter for ACK/NAK bundling (36.213 Section 7.3)
-*/
-uint32_t ulsch_encoding(uint8_t *a,
- PHY_VARS_NR_UE *phy_vars_ue,
- uint8_t harq_pid,
- uint8_t eNB_id,
- uint8_t subframe_rx,
- uint8_t tmode,
- uint8_t control_only_flag,
- uint8_t Nbundled);
-
-void print_CQI(void *o,UCI_format_t uci_format,uint8_t eNB_id,int N_RB_DL);
-
-void fill_CQI(NR_UE_ULSCH_t *ulsch,PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id, uint8_t harq_pid,int N_RB_DL, rnti_t rnti, uint8_t trans_mode,double sinr_eff);
-
-void reset_cba_uci(void *o);
-
-/** \brief This routine computes the subband PMI bitmap based on measurements (0,1,2,3 for rank 0 and 0,1 for rank 1) in the format needed for UCI
- @param meas pointer to measurements
- @param eNB_id eNB_id
- @param nb_subbands number of subbands
- @returns subband PMI bitmap
-*/
-uint16_t quantize_subband_pmi(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,int nb_subbands);
-
-int32_t pmi_convert_rank1_from_rank2(uint16_t pmi_alloc, int tpmi, int nb_rb);
-
-uint16_t quantize_subband_pmi2(PHY_NR_MEASUREMENTS *meas,uint8_t eNB_id,uint8_t a_id,int nb_subbands);
-
-
-
-uint64_t cqi2hex(uint32_t cqi);
-
-uint16_t computeRIV(uint16_t N_RB_DL,uint16_t RBstart,uint16_t Lcrbs);
-
-
-/** \brief This routine extracts a single subband PMI from a bitmap coming from UCI or the pmi_extend function
- @param N_RB_DL number of resource blocks
- @param mimo_mode
- @param pmi_alloc subband PMI bitmap
- @param rb resource block for which to extract PMI
- @returns subband PMI
-*/
-uint8_t get_pmi(uint8_t N_RB_DL,MIMO_mode_t mode, uint32_t pmi_alloc,uint16_t rb);
-
-int get_nCCE_offset_l1(int *CCE_table,
- const unsigned char L,
- const int nCCE,
- const int common_dci,
- const unsigned short rnti,
- const unsigned char subframe);
-
-uint16_t get_nCCE(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi);
-
-uint16_t get_nquad(uint8_t num_pdcch_symbols,NR_DL_FRAME_PARMS *frame_parms,uint8_t mi);
-
-uint8_t get_mi(NR_DL_FRAME_PARMS *frame,uint8_t subframe);
-
-uint16_t get_nCCE_mac(uint8_t Mod_id,uint8_t CC_id,int num_pdcch_symbols,int subframe);
-
-uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
-
-void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi);
-
-void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
- uint8_t subframe,
- int8_t* llr,
- uint32_t length);
-
-
-
-void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
- int mbsfn_flag,
- NR_UE_DLSCH_t *dlsch,
- int G,
- int16_t* llr,
- uint8_t q,
- uint8_t Ns);
-
-void init_ncs_cell(NR_DL_FRAME_PARMS *frame_parms,uint8_t ncs_cell[20][7]);
-
-void generate_pucch1x(int32_t **txdataF,
- NR_DL_FRAME_PARMS *frame_parms,
- uint8_t ncs_cell[20][7],
- PUCCH_FMT_t fmt,
- PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
- uint16_t n1_pucch,
- uint8_t shortened_format,
- uint8_t *payload,
- int16_t amp,
- uint8_t subframe);
-
-void generate_pucch2x(int32_t **txdataF,
- NR_DL_FRAME_PARMS *fp,
- uint8_t ncs_cell[20][7],
- PUCCH_FMT_t fmt,
- PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
- uint16_t n2_pucch,
- uint8_t *payload,
- int A,
- int B2,
- int16_t amp,
- uint8_t subframe,
- uint16_t rnti);
-
-void generate_pucch3x(int32_t **txdataF,
- NR_DL_FRAME_PARMS *frame_parms,
- uint8_t ncs_cell[20][7],
- PUCCH_FMT_t fmt,
- PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
- uint16_t n3_pucch,
- uint8_t shortened_format,
- uint8_t *payload,
- int16_t amp,
- uint8_t subframe,
- uint16_t rnti);
-
-
-void init_ulsch_power_LUT(void);
-
-/*!
- \brief Check for PRACH TXop in subframe
- @param frame_parms Pointer to NR_DL_FRAME_PARMS
- @param frame frame index to check
- @param subframe subframe index to check
- @returns 0 on success
-*/
-int is_prach_subframe(NR_DL_FRAME_PARMS *frame_parms,frame_t frame, uint8_t subframe);
-
-/*!
- \brief Generate PRACH waveform
- @param phy_vars_ue Pointer to ue top-level descriptor
- @param eNB_id Index of destination eNB
- @param subframe subframe index to operate on
- @param index of preamble (0-63)
- @param Nf System frame number
- @returns 0 on success
-
-*/
-int32_t generate_prach(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint8_t subframe,uint16_t Nf);
-
-
-/*!
- \brief Helper for MAC, returns number of available PRACH in TDD for a particular configuration index
- @param frame_parms Pointer to NR_DL_FRAME_PARMS structure
- @returns 0-5 depending on number of available prach
-*/
-uint8_t get_num_prach_tdd(module_id_t Mod_id);
-
-/*!
- \brief Return the PRACH format as a function of the Configuration Index and Frame type.
- @param prach_ConfigIndex PRACH Configuration Index
- @param frame_type 0-FDD, 1-TDD
- @returns 0-1 accordingly
-*/
-uint8_t get_prach_fmt(uint8_t prach_ConfigIndex,lte_frame_type_t frame_type);
-
-uint16_t get_nr_prach_fmt(int prach_ConfigIndex,lte_frame_type_t frame_type, nr_frequency_range_e fr);
-
-/*!
- \brief Helper for MAC, returns frequency index of PRACH resource in TDD for a particular configuration index
- @param frame_parms Pointer to NR_DL_FRAME_PARMS structure
- @returns 0-5 depending on number of available prach
-*/
-uint8_t get_fid_prach_tdd(module_id_t Mod_id,uint8_t tdd_map_index);
-
-/*!
- \brief Comp ute DFT of PRACH ZC sequences. Used for generation of prach in UE and reception of PRACH in eNB.
- @param rootSequenceIndex PRACH root sequence
- #param prach_ConfigIndex PRACH Configuration Index
- @param zeroCorrelationZoneConfig PRACH ncs_config
- @param highSpeedFlat PRACH High-Speed Flag
- @param frame_type TDD/FDD flag
- @param Xu DFT output
-*/
-void compute_prach_seq(uint16_t rootSequenceIndex,
- uint8_t prach_ConfigIndex,
- uint8_t zeroCorrelationZoneConfig,
- uint8_t highSpeedFlag,
- lte_frame_type_t frame_type,
- uint32_t X_u[64][839]);
-
-
-void init_prach_tables(int N_ZC);
-
-void init_unscrambling_lut(void);
-void init_scrambling_lut(void);
-
-/*!
- \brief Return the status of MBSFN in this frame/subframe
- @param frame Frame index
- @param subframe Subframe index
- @param frame_parms Pointer to frame parameters
- @returns 1 if subframe is for MBSFN
-*/
-int is_pmch_subframe(frame_t frame, int subframe, NR_DL_FRAME_PARMS *frame_parms);
-
-uint8_t is_not_pilot(uint8_t pilots, uint8_t re, uint8_t nushift, uint8_t use2ndpilots);
-
-uint8_t is_not_UEspecRS(int8_t lprime, uint8_t re, uint8_t nushift, uint8_t Ncp, uint8_t beamforming_mode);
-
-uint32_t dlsch_decoding_abstraction(double *dlsch_MIPB,
- NR_DL_FRAME_PARMS *lte_frame_parms,
- NR_UE_DLSCH_t *dlsch,
- uint8_t subframe,
- uint8_t num_pdcch_symbols);
-
-// DL power control functions
-double get_pa_dB(uint8_t pa);
-
-
-double computeRhoA_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- NR_UE_DLSCH_t *dlsch_ue,
- uint8_t dl_power_off,
- uint8_t n_antenna_port);
-
-double computeRhoB_UE(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- PDSCH_CONFIG_COMMON *pdsch_config_common,
- uint8_t n_antenna_port,
- NR_UE_DLSCH_t *dlsch_ue,
- uint8_t dl_power_off);
-
-/*void compute_sqrt_RhoAoRhoB(PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
- PDSCH_CONFIG_COMMON *pdsch_config_common,
- uint8_t n_antenna_port,
- NR_UE_DLSCH_t *dlsch_ue);
-*/
-
-uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms,
- uint8_t prach_ConfigIndex,
- uint8_t n_ra_prboffset,
- uint8_t tdd_mapindex, uint16_t Nf);
-
-void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx,
- int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common);
-
-
-uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset);
-
-int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
- PDSCH_t type,
- unsigned char eNB_id,
- unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference
- uint32_t frame,
- uint8_t nr_tti_rx,
- unsigned char symbol,
- unsigned char first_symbol_flag,
- RX_type_t rx_type,
- unsigned char i_mod,
- unsigned char harq_pid);
-
-uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch,uint8_t nb_re_dmrs,uint16_t length_dmrs, uint8_t Qm, uint8_t Nl) ;
-
-uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
- short *dlsch_llr,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t *dlsch,
- NR_DL_UE_HARQ_t *harq_process,
- uint32_t frame,
- uint16_t nb_symb_sch,
- uint8_t nr_tti_rx,
- uint8_t harq_pid,
- uint8_t is_crnti,
- uint8_t llr8_flag);
-
-/**@}*/
-#endif
diff --git a/openair1/PHY/NR_TRANSPORT/nr_uci_tools_common.c b/openair1/PHY/NR_TRANSPORT/nr_uci_tools_common.c
new file mode 100644
index 0000000000000000000000000000000000000000..2b0cbe72b3a91c8757c12d3ccbf194d5d08f740c
--- /dev/null
+++ b/openair1/PHY/NR_TRANSPORT/nr_uci_tools_common.c
@@ -0,0 +1,167 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file PHY/NR_TRANSPORT/nr_dci_tools_common.c
+ * \brief
+ * \author
+ * \date 2020
+ * \version 0.1
+ * \company Eurecom
+ * \email:
+ * \note
+ * \warning
+ */
+
+#include "nr_dci.h"
+
+void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping,
+ uint32_t n_id,
+ uint8_t n_hop,
+ int nr_tti_tx,
+ uint8_t *u,
+ uint8_t *v) {
+ /*
+ * Implements TS 38.211 subclause 6.3.2.2.1 Group and sequence hopping
+ * The following variables are set by higher layers:
+ * - PUCCH_GroupHopping:
+ * - n_id: higher-layer parameter hoppingId
+ * - n_hop: frequency hopping index
+ * if intra-slot frequency hopping is disabled by the higher-layer parameter PUCCH-frequency-hopping
+ * n_hop=0
+ * if frequency hopping is enabled by the higher-layer parameter PUCCH-frequency-hopping
+ * n_hop=0 for the first hop
+ * n_hop=1 for the second hop
+ */
+ // depending on the value of the PUCCH_GroupHopping, we will obtain different values for u,v
+ //pucch_GroupHopping_t PUCCH_GroupHopping = ue->pucch_config_common_nr->pucch_GroupHopping; // from higher layers FIXME!!!
+ // n_id defined as per TS 38.211 subclause 6.3.2.2.1 (is given by the higher-layer parameter hoppingId)
+ // it is hoppingId from PUCCH-ConfigCommon:
+ // Cell-Specific scrambling ID for group hoppping and sequence hopping if enabled
+ // Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2) BIT STRING (SIZE (10))
+ //uint16_t n_id = ue->pucch_config_common_nr->hoppingId; // from higher layers FIXME!!!
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("\t\t [nr_group_sequence_hopping] PUCCH_GroupHopping=%u, n_id=%u \n",PUCCH_GroupHopping,n_id);
+#endif
+ uint8_t f_ss=0,f_gh=0;
+ *u=0;
+ *v=0;
+ uint32_t c_init = 0;
+ uint32_t x1,s; // TS 38.211 Subclause 5.2.1
+ int l = 32, minShift = ((2*nr_tti_tx+n_hop)<<3);
+ int tmpShift =0;
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("\t\t [nr_group_sequence_hopping] calculating u,v -> ");
+#endif
+
+ if (PUCCH_GroupHopping == neither) { // PUCCH_GroupHopping 'neither'
+ f_ss = n_id%30;
+ }
+
+ if (PUCCH_GroupHopping == enable) { // PUCCH_GroupHopping 'enabled'
+ c_init = floor(n_id/30); // we initialize c_init to calculate u,v according to 6.3.2.2.1 of 38.211
+ s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
+ for (int m=0; m<8; m++) {
+ while(minShift >= l) {
+ s = lte_gold_generic(&x1, &c_init, 0);
+ l = l+32;
+ }
+
+ tmpShift = (minShift&((1<<5)-1)); //minShift%32;
+ f_gh = f_gh + ((1<<m)*((uint8_t)((s>>tmpShift)&1)));
+ minShift ++;
+ }
+
+ f_gh = f_gh%30;
+ f_ss = n_id%30;
+ /* for (int m=0; m<8; m++){
+ f_gh = f_gh + ((1<<m)*((uint8_t)((s>>(8*(2*nr_tti_tx+n_hop)+m))&1))); // Not sure we have to use nr_tti_tx FIXME!!!
+ }
+ f_gh = f_gh%30;
+ f_ss = n_id%30;*/
+ }
+
+ if (PUCCH_GroupHopping == disable) { // PUCCH_GroupHopping 'disabled'
+ c_init = (1<<5)*floor(n_id/30)+(n_id%30); // we initialize c_init to calculate u,v
+ s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
+ f_ss = n_id%30;
+ l = 32, minShift = (2*nr_tti_tx+n_hop);
+
+ while(minShift >= l) {
+ s = lte_gold_generic(&x1, &c_init, 0);
+ l = l+32;
+ }
+
+ tmpShift = (minShift&((1<<5)-1)); //minShift%32;
+ *v = (uint8_t)((s>>tmpShift)&1);
+ // *v = (uint8_t)((s>>(2*nr_tti_tx+n_hop))&1); // Not sure we have to use nr_tti_tx FIXME!!!
+ }
+
+ *u = (f_gh+f_ss)%30;
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("%d,%d\n",*u,*v);
+#endif
+}
+
+double nr_cyclic_shift_hopping(uint32_t n_id,
+ uint8_t m0,
+ uint8_t mcs,
+ uint8_t lnormal,
+ uint8_t lprime,
+ int nr_tti_tx) {
+ /*
+ * Implements TS 38.211 subclause 6.3.2.2.2 Cyclic shift hopping
+ * - n_id: higher-layer parameter hoppingId
+ * - m0: provided by higher layer parameter PUCCH-F0-F1-initial-cyclic-shift of PUCCH-F0-resource-config
+ * - mcs: mcs=0 except for PUCCH format 0 when it depends on information to be transmitted according to TS 38.213 subclause 9.2
+ * - lnormal: lnormal is the OFDM symbol number in the PUCCH transmission where l=0 corresponds to the first OFDM symbol of the PUCCH transmission
+ * - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213]
+ */
+ // alpha_init initialized to 2*PI/12=0.5235987756
+ double alpha = 0.5235987756;
+ uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs
+
+ uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
+ uint8_t n_cs=0;
+ int l = 32, minShift = (14*8*nr_tti_tx )+ 8*(lnormal+lprime);
+ int tmpShift =0;
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("\t\t [nr_cyclic_shift_hopping] calculating alpha (cyclic shift) using c_init=%u -> \n",c_init);
+#endif
+
+ for (int m=0; m<8; m++) {
+ while(minShift >= l) {
+ s = lte_gold_generic(&x1, &c_init, 0);
+ l = l+32;
+ }
+
+ tmpShift = (minShift&((1<<5)-1)); //minShift%32;
+ minShift ++;
+ n_cs = n_cs+((1<<m)*((uint8_t)((s>>tmpShift)&1)));
+ // calculating n_cs (Not sure we have to use nr_tti_tx FIXME!!!)
+ // n_cs = n_cs+((1<<m)*((uint8_t)((s>>((14*8*nr_tti_tx) + 8*(lnormal+lprime) + m))&1)));
+ }
+
+ alpha = (alpha * (double)((m0+mcs+n_cs)%12));
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("n_cs=%d -> %lf\n",n_cs,alpha);
+#endif
+ return(alpha);
+}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c
index 2bc623a66c2db7aa152983aab7b5af6621e5740a..3622e61b615772bb037b9285aee5e72deaf49748 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_ulsch.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch.c
@@ -35,12 +35,59 @@
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/LTE_REFSIG/lte_refsig.h"
+int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type) {
+
+ uint16_t i;
+ int16_t first_free_index=-1;
+
+ AssertFatal(gNB!=NULL,"gNB is null\n");
+ for (i=0; i<NUMBER_OF_NR_ULSCH_MAX; i++) {
+ AssertFatal(gNB->ulsch[i]!=NULL,"gNB->ulsch[%d] is null\n",i);
+ AssertFatal(gNB->ulsch[i][0]!=NULL,"gNB->ulsch[%d][0] is null\n",i);
+ LOG_D(PHY,"searching for rnti %x : ulsch_index %d=> harq_mask %x, rnti %x, first_free_index %d\n", rnti,i,gNB->ulsch[i][0]->harq_mask,gNB->ulsch[i][0]->rnti,first_free_index);
+ if ((gNB->ulsch[i][0]->harq_mask >0) &&
+ (gNB->ulsch[i][0]->rnti==rnti)) return i;
+ else if ((gNB->ulsch[i][0]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
+ }
+ if (type == SEARCH_EXIST) return -1;
+ if (first_free_index != -1)
+ gNB->ulsch[first_free_index][0]->rnti = 0;
+ return first_free_index;
+}
+
+void nr_fill_ulsch(PHY_VARS_gNB *gNB,
+ int frame,
+ int slot,
+ nfapi_nr_pusch_pdu_t *ulsch_pdu) {
+
+
+ int ulsch_id = find_nr_ulsch(ulsch_pdu->rnti,gNB,SEARCH_EXIST_OR_FREE);
+ AssertFatal( (ulsch_id>=0) && (ulsch_id<NUMBER_OF_NR_ULSCH_MAX),
+ "illegal or no ulsch_id found!!! rnti %04x ulsch_id %d\n",ulsch_pdu->rnti,ulsch_id);
+
+ NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ulsch_id][0];
+ int harq_pid = ulsch_pdu->pusch_data.harq_process_id;
+ ulsch->rnti = ulsch_pdu->rnti;
+ //ulsch->rnti_type;
+ ulsch->harq_mask |= 1<<harq_pid;
+ ulsch->harq_process_id[slot] = harq_pid;
+
+ ulsch->harq_processes[harq_pid]->frame=frame;
+ ulsch->harq_processes[harq_pid]->slot=slot;
+ ulsch->harq_processes[harq_pid]->handled= 0;
+ ulsch->harq_processes[harq_pid]->status= NR_ACTIVE;
+ memcpy((void*)&ulsch->harq_processes[harq_pid]->ulsch_pdu, (void*)ulsch_pdu, sizeof(nfapi_nr_pusch_pdu_t));
+
+ LOG_D(PHY,"Initializing nFAPI for ULSCH, UE %d, harq_pid %d\n",ulsch_id,harq_pid);
+
+}
+
void nr_ulsch_unscrambling(int16_t* llr,
- uint32_t size,
- uint8_t q,
- uint32_t Nid,
- uint32_t n_RNTI)
-{
+ uint32_t size,
+ uint8_t q,
+ uint32_t Nid,
+ uint32_t n_RNTI) {
+
uint8_t reset;
uint32_t x1, x2, s=0;
diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
index 050c2302128fd5965fd78df090e1daf4342fd356..8ca3071e061d4ba36e9028a21876edebf3be474a 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
@@ -70,13 +70,12 @@ void free_gNB_ulsch(NR_gNB_ULSCH_t **ulschptr,uint8_t N_RB_UL)
a_segments = a_segments/273;
}
- uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment
for (i=0; i<NR_MAX_ULSCH_HARQ_PROCESSES; i++) {
if (ulsch->harq_processes[i]) {
if (ulsch->harq_processes[i]->b) {
- free16(ulsch->harq_processes[i]->b,ulsch_bytes);
+ free16(ulsch->harq_processes[i]->b,a_segments*1056);
ulsch->harq_processes[i]->b = NULL;
}
for (r=0; r<a_segments; r++) {
@@ -219,13 +218,13 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch)
/// Nfapi ULSCH PDU
//nfapi_nr_ul_config_ulsch_pdu ulsch_pdu;
ulsch->harq_processes[i]->frame=0;
- ulsch->harq_processes[i]->subframe=0;
+ ulsch->harq_processes[i]->slot=0;
ulsch->harq_processes[i]->round=0;
ulsch->harq_processes[i]->TPC=0;
ulsch->harq_processes[i]->mimo_mode=0;
ulsch->harq_processes[i]->dci_alloc=0;
ulsch->harq_processes[i]->rar_alloc=0;
- ulsch->harq_processes[i]->status=0;
+ ulsch->harq_processes[i]->status=NR_SCH_IDLE;
ulsch->harq_processes[i]->subframe_scheduling_flag=0;
ulsch->harq_processes[i]->subframe_cba_scheduling_flag=0;
ulsch->harq_processes[i]->phich_active=0;
@@ -358,6 +357,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
}
// harq_process->trials[nfapi_ulsch_pdu_rel15->round]++;
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,1);
harq_process->TBS = pusch_pdu->pusch_data.tb_size;
A = (harq_process->TBS)<<3;
@@ -421,7 +422,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
#ifdef DEBUG_ULSCH_DECODING
printf("ulsch decoding nr segmentation Z %d\n", harq_process->Z);
if (!frame%100)
- printf("K %d C %d Z %d\n", harq_process->K, harq_process->C, harq_process->Z);
+ printf("K %d C %d Z %d \n", harq_process->K, harq_process->C, harq_process->Z);
#endif
}
p_decParams->Z = harq_process->Z;
@@ -528,7 +529,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
#ifdef DEBUG_ULSCH_DECODING
if (r==0) {
write_output("decoder_llr.m","decllr",ulsch_llr,G,1,0);
- write_output("decoder_in.m","dec",&harq_process->d[0][0],(3*8*Kr_bytes)+12,1,0);
+ write_output("decoder_in.m","dec",&harq_process->d[0][0],E,1,0);
}
printf("decoder input(segment %u) :", r);
@@ -609,7 +610,6 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
#endif
ret = ulsch->max_ldpc_iterations + 1;
}
-
nb_total_decod++;
if (no_iteration_ldpc > ulsch->max_ldpc_iterations){
@@ -667,8 +667,8 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
ulsch->harq_mask &= ~(1 << harq_pid);
}
- // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
- // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS);
+ // LOG_D(PHY,"[gNB %d] ULSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
+ // phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,ulsch->Mlimit,harq_process->TBS);
harq_process->handled = 1;
ret = ulsch->max_ldpc_iterations + 1;
@@ -690,6 +690,7 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
// LOG_D(PHY,"[gNB %d] ULSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_gNB->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
+
// Reassembly of Transport block here
offset = 0;
Kr = harq_process->K;
@@ -713,15 +714,15 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
}
#ifdef DEBUG_ULSCH_DECODING
- LOG_I(PHY, "Decoder output (payload): \n");
- for (i = 0; i < harq_process->TBS / 8; i++) {
+ LOG_I(PHY, "Decoder output (payload) at SFN/SF: %d/%d \n", frame, nr_tti_rx);
+ for (i = 0; i < harq_process->TBS ; i++) {
//harq_process_ul_ue->a[i] = (unsigned char) rand();
//printf("a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]);
- printf("0x%02x",harq_process->b[i]);
+ printf("%02x ",harq_process->b[i]);
}
#endif
ulsch->last_iteration_cnt = ret;
-
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_ULSCH_DECODING,0);
return(ret);
}
diff --git a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
index d22a013c049cf346a7cb9f09c49aec6ccc102a38..a966db5844ad6de4170175655c6dffec5e05ae21 100644
--- a/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
+++ b/openair1/PHY/NR_TRANSPORT/nr_ulsch_demodulation.c
@@ -222,7 +222,6 @@ void nr_idft(uint32_t *z, uint32_t Msc_PUSCH)
}
-
void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
NR_gNB_PUSCH *pusch_vars,
unsigned char symbol,
@@ -230,9 +229,10 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
nfapi_nr_pusch_pdu_t *pusch_pdu,
NR_DL_FRAME_PARMS *frame_parms)
{
+
unsigned short start_re, re, nb_re_pusch;
unsigned char aarx;
- uint8_t K_ptrs;
+ uint8_t K_ptrs = 0;
uint32_t rxF_ext_index = 0;
uint32_t ul_ch0_ext_index = 0;
uint32_t ul_ch0_index = 0;
@@ -259,8 +259,6 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
is_ptrs_symbol_flag = 0;
num_ptrs_symbols = 0;
- K_ptrs = (pusch_pdu->pusch_ptrs.ptrs_freq_density)?4:2;
-
for (aarx = 0; aarx < frame_parms->nb_antennas_rx; aarx++) {
rxF = (int16_t *)&rxdataF[aarx][symbol * frame_parms->ofdm_symbol_size];
@@ -284,19 +282,18 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
else
is_dmrs_re = 0;
- if ( ((pusch_pdu->pdu_bit_map)>>2)& 0x01 ) {
- is_ptrs_symbol_flag = is_ptrs_symbol(symbol,
- (start_re + re)%frame_parms->ofdm_symbol_size,
- n_rnti,
- pusch_pdu->rb_size,
- pusch_pdu->nr_of_symbols,
- aarx,
- K_ptrs,
- pusch_vars->ptrs_symbols,
- start_re,
- frame_parms->ofdm_symbol_size,
- pusch_pdu->dmrs_config_type,
- pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset);
+ if (pusch_pdu->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) {
+ K_ptrs = (pusch_pdu->pusch_ptrs.ptrs_freq_density)?4:2;
+ if(is_ptrs_symbol(symbol, pusch_vars->ptrs_symbols))
+ is_ptrs_symbol_flag = is_ptrs_subcarrier((start_re + re) % frame_parms->ofdm_symbol_size,
+ n_rnti,
+ aarx,
+ pusch_pdu->dmrs_config_type,
+ K_ptrs,
+ pusch_pdu->rb_size,
+ pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset,
+ start_re,
+ frame_parms->ofdm_symbol_size);
if (is_ptrs_symbol_flag == 1)
num_ptrs_symbols++;
@@ -304,7 +301,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
}
#ifdef DEBUG_RB_EXT
- printf("re = %d, is_dmrs_symbol_flag = %d, symbol = %d\n", re, is_dmrs_symbol_flag, symbol);
+ printf("re = %d, is_ptrs_symbol_flag = %d, symbol = %d\n", re, is_ptrs_symbol_flag, symbol);
#endif
if ( is_dmrs_re == 0 && is_ptrs_symbol_flag == 0) {
@@ -315,8 +312,7 @@ void nr_ulsch_extract_rbs_single(int32_t **rxdataF,
ul_ch0_ptrs_ext[ul_ch0_ptrs_ext_index] = ul_ch0_ptrs[ul_ch0_ptrs_index];
#ifdef DEBUG_RB_EXT
- printf("rxF_ext[%d] = %d\n", rxF_ext_index, rxF_ext[rxF_ext_index]);
- printf("rxF_ext[%d] = %d\n", rxF_ext_index+1, rxF_ext[rxF_ext_index+1]);
+ printf("rxF_ext[%d] = (%d,%d)\n", rxF_ext_index>>1, rxF_ext[rxF_ext_index],rxF_ext[rxF_ext_index+1]);
#endif
ul_ch0_ext_index++;
@@ -372,7 +368,6 @@ void nr_ulsch_scale_channel(int **ul_ch_estimates_ext,
nb_rb = (2*nb_rb)/3;
}
-
for (rb=0;rb<nb_rb;rb++) {
ul_ch128[0] = _mm_mulhi_epi16(ul_ch128[0], ch_amp128);
@@ -446,7 +441,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext,
symbol_mod = (symbol>=(7-frame_parms->Ncp)) ? symbol-(7-frame_parms->Ncp) : symbol;
- for (aatx=0; aatx<frame_parms->nb_antenna_ports_gNB; aatx++)
+ for (aatx=0; aatx<frame_parms->nb_antenna_ports_gNB; aatx++) {
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
//clear average level
avg128U = vdupq_n_s32(0);
@@ -489,8 +484,7 @@ void nr_ulsch_channel_level(int **ul_ch_estimates_ext,
((int32_t*)&avg128U)[2] +
((int32_t*)&avg128U)[3] ) / (nb_rb*nre);
}
-
-
+ }
#endif
}
@@ -516,12 +510,12 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
ul_ch = (int16_t *)&ul_ch_estimates_ext[0][symbol*nb_rb*12];
printf("--------------------symbol = %d, mod_order = %d, output_shift = %d-----------------------\n", symbol, mod_order, output_shift);
- printf("----------------Before compansation------------------\n");
+ printf("----------------Before compensation------------------\n");
- for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx++){
+ for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx+=2){
- printf("rxF[%d] = %d\n", prnt_idx, rxF[prnt_idx]);
- printf("ul_ch[%d] = %d\n", prnt_idx, ul_ch[prnt_idx]);
+ printf("rxF[%d] = (%d,%d)\n", prnt_idx>>1, rxF[prnt_idx],rxF[prnt_idx+1]);
+ printf("ul_ch[%d] = (%d,%d)\n", prnt_idx>>1, ul_ch[prnt_idx],ul_ch[prnt_idx+1]);
}
@@ -709,7 +703,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
if (rho) {
-
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
rho128 = (__m128i *)&rho[aarx][symbol*frame_parms->N_RB_UL*12];
ul_ch128 = (__m128i *)&ul_ch_estimates_ext[aarx][symbol*frame_parms->N_RB_UL*12];
@@ -791,7 +784,6 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
#elif defined(__arm__)
-
unsigned short rb;
unsigned char aatx,aarx,symbol_mod,is_dmrs_symbol=0;
@@ -993,9 +985,9 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
printf("----------------After compansation------------------\n");
- for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx++){
+ for (prnt_idx=0;prnt_idx<12*nb_rb*2;prnt_idx+=2){
- printf("rxF[%d] = %d\n", prnt_idx, rxF[prnt_idx]);
+ printf("rxF[%d] = (%d,%d)\n", prnt_idx>>1, rxF[prnt_idx],rxF[prnt_idx+1]);
}
@@ -1008,9 +1000,9 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
printf("----------------After computation------------------\n");
- for (print_idx=0;print_idx<12*nb_rb*2;print_idx++){
+ for (print_idx=0;print_idx<12*nb_rb*2;print_idx+=2){
- printf("ch_mag[%d] = %d\n", print_idx, ch_mag[print_idx]);
+ printf("ch_mag[%d] = (%d,%d)\n", print_idx>>1, ch_mag[print_idx],ch_mag[print_idx+1]);
}
@@ -1018,44 +1010,39 @@ void nr_ulsch_channel_compensation(int **rxdataF_ext,
}
-void nr_rx_pusch(PHY_VARS_gNB *gNB,
- uint8_t UE_id,
- uint32_t frame,
- uint8_t nr_tti_rx,
- unsigned char symbol,
- unsigned char harq_pid)
+int nr_rx_pusch(PHY_VARS_gNB *gNB,
+ uint8_t ulsch_id,
+ uint32_t frame,
+ uint8_t nr_tti_rx,
+ unsigned char symbol,
+ unsigned char harq_pid)
{
- uint8_t first_symbol_flag, aarx, aatx, dmrs_symbol_flag, ptrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol
+ uint8_t aarx, aatx, dmrs_symbol_flag; // dmrs_symbol_flag, a flag to indicate DMRS REs in current symbol
uint32_t nb_re_pusch, bwp_start_subcarrier;
uint8_t L_ptrs = 0; // PTRS parameter
int avgs;
int avg[4];
NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
- nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[UE_id][0]->harq_processes[harq_pid]->ulsch_pdu;
+ nfapi_nr_pusch_pdu_t *rel15_ul = &gNB->ulsch[ulsch_id][0]->harq_processes[harq_pid]->ulsch_pdu;
dmrs_symbol_flag = 0;
- ptrs_symbol_flag = 0;
- first_symbol_flag = 0;
- gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol = 0;
+ gNB->pusch_vars[ulsch_id]->ptrs_sc_per_ofdm_symbol = 0;
if(symbol == rel15_ul->start_symbol_index){
- gNB->pusch_vars[UE_id]->rxdataF_ext_offset = 0;
- gNB->pusch_vars[UE_id]->dmrs_symbol = 0;
- gNB->pusch_vars[UE_id]->cl_done = 0;
- gNB->pusch_vars[UE_id]->ptrs_symbols = 0;
- first_symbol_flag = 1;
+ gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = 0;
+ gNB->pusch_vars[ulsch_id]->dmrs_symbol = 0;
+ gNB->pusch_vars[ulsch_id]->cl_done = 0;
+ gNB->pusch_vars[ulsch_id]->ptrs_symbols = 0;
- if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu
+ if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu
L_ptrs = 1<<(rel15_ul->pusch_ptrs.ptrs_time_density);
- set_ptrs_symb_idx(&gNB->pusch_vars[UE_id]->ptrs_symbols,
+ set_ptrs_symb_idx(&gNB->pusch_vars[ulsch_id]->ptrs_symbols,
rel15_ul->nr_of_symbols,
rel15_ul->start_symbol_index,
- rel15_ul->dmrs_config_type,
L_ptrs,
- 1, // only dmrs of length 1 is currently supported
- frame_parms->ofdm_symbol_size);
+ rel15_ul->ul_dmrs_symb_pos);
}
}
@@ -1064,29 +1051,25 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
dmrs_symbol_flag = ((rel15_ul->ul_dmrs_symb_pos)>>symbol)&0x01;
if (dmrs_symbol_flag == 1){
- nb_re_pusch = rel15_ul->rb_size * ((rel15_ul->dmrs_config_type==pusch_dmrs_type1)?6:8);
- gNB->pusch_vars[UE_id]->dmrs_symbol = symbol;
+ if (((rel15_ul->ul_dmrs_symb_pos)>>((symbol+1)%frame_parms->symbols_per_slot))&0x01)
+ AssertFatal(1==0,"Double DMRS configuration is not yet supported\n");
+
+ if (rel15_ul->dmrs_config_type == 0) {
+ // if no data in dmrs cdm group is 1 only even REs have no data
+ // if no data in dmrs cdm group is 2 both odd and even REs have no data
+ nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*6));
+ }
+ else {
+ nb_re_pusch = rel15_ul->rb_size *(12 - (rel15_ul->num_dmrs_cdm_grps_no_data*4));
+ }
+ gNB->pusch_vars[ulsch_id]->dmrs_symbol = symbol;
} else {
nb_re_pusch = rel15_ul->rb_size * NR_NB_SC_PER_RB;
}
- if ( ((rel15_ul->pdu_bit_map)>>2)& 0x01 ) { // if there is ptrs pdu
- ptrs_symbol_flag = is_ptrs_symbol(symbol,
- 0,
- rel15_ul->rnti,
- rel15_ul->rb_size,
- rel15_ul->nr_of_symbols,
- 0,
- (rel15_ul->pusch_ptrs.ptrs_freq_density)?4:2,
- gNB->pusch_vars[UE_id]->ptrs_symbols,
- 0,
- frame_parms->ofdm_symbol_size,
- rel15_ul->dmrs_config_type,
- rel15_ul->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset);
- }
-
- if (ptrs_symbol_flag == 1){
- gNB->pusch_vars[UE_id]->ptrs_symbol_index = symbol;
+ if (rel15_ul->pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) { // if there is ptrs pdu
+ if(is_ptrs_symbol(symbol, gNB->pusch_vars[ulsch_id]->ptrs_symbols))
+ gNB->pusch_vars[ulsch_id]->ptrs_symbol_index = symbol;
}
@@ -1106,75 +1089,88 @@ void nr_rx_pusch(PHY_VARS_gNB *gNB,
//--------------------- RBs extraction ---------------------
//----------------------------------------------------------
- start_meas(&gNB->ulsch_rbs_extraction_stats);
- nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF,
- gNB->pusch_vars[UE_id],
- symbol,
- dmrs_symbol_flag,
- rel15_ul,
- frame_parms);
- stop_meas(&gNB->ulsch_rbs_extraction_stats);
-
- nr_ulsch_scale_channel(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext,
- frame_parms,
- gNB->ulsch[UE_id],
- symbol,
- dmrs_symbol_flag,
- rel15_ul->rb_size,
- rel15_ul->dmrs_config_type);
-
+ if (nb_re_pusch > 0) {
- if (first_symbol_flag==1) {
+ start_meas(&gNB->ulsch_rbs_extraction_stats);
+ nr_ulsch_extract_rbs_single(gNB->common_vars.rxdataF,
+ gNB->pusch_vars[ulsch_id],
+ symbol,
+ dmrs_symbol_flag,
+ rel15_ul,
+ frame_parms);
+ stop_meas(&gNB->ulsch_rbs_extraction_stats);
- nr_ulsch_channel_level(gNB->pusch_vars[UE_id]->ul_ch_estimates_ext,
+ nr_ulsch_scale_channel(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext,
frame_parms,
- avg,
+ gNB->ulsch[ulsch_id],
symbol,
- nb_re_pusch,
- rel15_ul->rb_size);
- avgs = 0;
+ dmrs_symbol_flag,
+ rel15_ul->rb_size,
+ rel15_ul->dmrs_config_type);
- for (aatx=0;aatx<frame_parms->nb_antennas_tx;aatx++)
- for (aarx=0;aarx<frame_parms->nb_antennas_rx;aarx++)
- avgs = cmax(avgs,avg[(aatx<<1)+aarx]);
- gNB->pusch_vars[UE_id]->log2_maxh = (log2_approx(avgs)/2)+1;
+ if (gNB->pusch_vars[ulsch_id]->cl_done==0) {
- }
+ nr_ulsch_channel_level(gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext,
+ frame_parms,
+ avg,
+ symbol,
+ nb_re_pusch,
+ rel15_ul->rb_size);
+
+ avgs = 0;
+
+ for (aatx=0;aatx<frame_parms->nb_antennas_tx;aatx++)
+ for (aarx=0;aarx<frame_parms->nb_antennas_rx;aarx++)
+ avgs = cmax(avgs,avg[(aatx<<1)+aarx]);
+
+ gNB->pusch_vars[ulsch_id]->log2_maxh = (log2_approx(avgs)/2)+1;
+ gNB->pusch_vars[ulsch_id]->cl_done = 1;
+ }
+
+ start_meas(&gNB->ulsch_channel_compensation_stats);
+ nr_ulsch_channel_compensation(gNB->pusch_vars[ulsch_id]->rxdataF_ext,
+ gNB->pusch_vars[ulsch_id]->ul_ch_estimates_ext,
+ gNB->pusch_vars[ulsch_id]->ul_ch_mag0,
+ gNB->pusch_vars[ulsch_id]->ul_ch_magb0,
+ gNB->pusch_vars[ulsch_id]->rxdataF_comp,
+ (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[ulsch_id]->rho : NULL,
+ frame_parms,
+ symbol,
+ dmrs_symbol_flag,
+ rel15_ul->qam_mod_order,
+ rel15_ul->rb_size,
+ gNB->pusch_vars[ulsch_id]->log2_maxh);
+ stop_meas(&gNB->ulsch_channel_compensation_stats);
- start_meas(&gNB->ulsch_channel_compensation_stats);
- nr_ulsch_channel_compensation(gNB->pusch_vars[UE_id]->rxdataF_ext,
- gNB->pusch_vars[UE_id]->ul_ch_estimates_ext,
- gNB->pusch_vars[UE_id]->ul_ch_mag0,
- gNB->pusch_vars[UE_id]->ul_ch_magb0,
- gNB->pusch_vars[UE_id]->rxdataF_comp,
- (frame_parms->nb_antennas_tx>1) ? gNB->pusch_vars[UE_id]->rho : NULL,
- frame_parms,
- symbol,
- dmrs_symbol_flag,
- rel15_ul->qam_mod_order,
- rel15_ul->rb_size,
- gNB->pusch_vars[UE_id]->log2_maxh);
- stop_meas(&gNB->ulsch_channel_compensation_stats);
+
+ int rxsig = signal_energy(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][(symbol*rel15_ul->rb_size*12)],
+ rel15_ul->rb_size*12);
+
+ if (rxsig==1) return (rxsig);
#ifdef NR_SC_FDMA
- nr_idft(&((uint32_t*)gNB->pusch_vars[UE_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch);
+ nr_idft(&((uint32_t*)gNB->pusch_vars[ulsch_id]->rxdataF_ext[0])[symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB], nb_re_pusch);
#endif
//----------------------------------------------------------
//-------------------- LLRs computation --------------------
//----------------------------------------------------------
- start_meas(&gNB->ulsch_llr_stats);
- nr_ulsch_compute_llr(&gNB->pusch_vars[UE_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB],
- gNB->pusch_vars[UE_id]->ul_ch_mag0,
- gNB->pusch_vars[UE_id]->ul_ch_magb0,
- &gNB->pusch_vars[UE_id]->llr[gNB->pusch_vars[UE_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order],
- rel15_ul->rb_size,
- nb_re_pusch,
- symbol,
- rel15_ul->qam_mod_order);
- stop_meas(&gNB->ulsch_llr_stats);
-
- gNB->pusch_vars[UE_id]->rxdataF_ext_offset = gNB->pusch_vars[UE_id]->rxdataF_ext_offset + nb_re_pusch - gNB->pusch_vars[UE_id]->ptrs_sc_per_ofdm_symbol;
-
+ start_meas(&gNB->ulsch_llr_stats);
+ AssertFatal(gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order+nb_re_pusch*rel15_ul->qam_mod_order < (8*((3*8*6144)+12)) , "Mysterious llr buffer size check");
+ nr_ulsch_compute_llr(&gNB->pusch_vars[ulsch_id]->rxdataF_comp[0][symbol * rel15_ul->rb_size * NR_NB_SC_PER_RB],
+ gNB->pusch_vars[ulsch_id]->ul_ch_mag0,
+ gNB->pusch_vars[ulsch_id]->ul_ch_magb0,
+ &gNB->pusch_vars[ulsch_id]->llr[gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset * rel15_ul->qam_mod_order],
+ rel15_ul->rb_size,
+ nb_re_pusch,
+ symbol,
+ rel15_ul->qam_mod_order);
+ stop_meas(&gNB->ulsch_llr_stats);
+
+ }
+
+ gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset = gNB->pusch_vars[ulsch_id]->rxdataF_ext_offset + nb_re_pusch;
+ return (0);
+
}
diff --git a/openair1/PHY/NR_TRANSPORT/pucch_rx.c b/openair1/PHY/NR_TRANSPORT/pucch_rx.c
index b74b078dfd6ffcd63faa97b59314335405e0f546..501df8bb357b1d665ea55ff34952091a9cda56f2 100644
--- a/openair1/PHY/NR_TRANSPORT/pucch_rx.c
+++ b/openair1/PHY/NR_TRANSPORT/pucch_rx.c
@@ -1,3 +1,34 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file PHY/NR_TRANSPORT/pucch_rx.c
+ * \brief Top-level routines for decoding the PUCCH physical channel
+ * \author A. Mico Pereperez, Padarthi Naga Prasanth, Francesco Mani, Raymond Knopp
+ * \date 2020
+ * \version 0.2
+ * \company Eurecom
+ * \email:
+ * \note
+ * \warning
+ */
#include<stdio.h>
#include <string.h>
#include <math.h>
@@ -8,38 +39,160 @@
#include "PHY/impl_defs_nr.h"
#include "PHY/defs_nr_common.h"
-#include "PHY/defs_nr_UE.h"
+#include "PHY/defs_gNB.h"
+#include "PHY/sse_intrin.h"
#include "PHY/NR_UE_TRANSPORT/pucch_nr.h"
-#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
-
+#include <openair1/PHY/CODING/nrSmallBlock/nr_small_block_defs.h>
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
+#include "PHY/NR_REFSIG/nr_refsig.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "T.h"
+//#define DEBUG_NR_PUCCH_RX 1
+
+NR_gNB_PUCCH_t *new_gNB_pucch(void){
+ NR_gNB_PUCCH_t *pucch;
+ pucch = (NR_gNB_PUCCH_t *)malloc16(sizeof(NR_gNB_PUCCH_t));
+ pucch->active = 0;
+ return (pucch);
+}
+
+int nr_find_pucch(uint16_t rnti,
+ int frame,
+ int slot,
+ PHY_VARS_gNB *gNB) {
+
+ AssertFatal(gNB!=NULL,"gNB is null\n");
+ int index = -1;
+
+ for (int i=0; i<NUMBER_OF_NR_ULSCH_MAX; i++) {
+ AssertFatal(gNB->pucch[i]!=NULL,"gNB->pucch[%d] is null\n",i);
+ if ((gNB->pucch[i]->active >0) &&
+ (gNB->pucch[i]->pucch_pdu.rnti==rnti) &&
+ (gNB->pucch[i]->frame==frame) &&
+ (gNB->pucch[i]->slot==slot)) return(i);
+ else if ((gNB->pucch[i]->active == 0) && (index==-1)) index=i;
+ }
+
+ if (index==-1)
+ LOG_E(MAC,"PUCCH list is full\n");
+
+ return(index);
+}
+
+void nr_fill_pucch(PHY_VARS_gNB *gNB,
+ int frame,
+ int slot,
+ nfapi_nr_pucch_pdu_t *pucch_pdu) {
+
+ int id = nr_find_pucch(pucch_pdu->rnti,frame,slot,gNB);
+ AssertFatal( (id>=0) && (id<NUMBER_OF_NR_PUCCH_MAX),
+ "invalid id found for pucch !!! rnti %04x id %d\n",pucch_pdu->rnti,id);
+
+ NR_gNB_PUCCH_t *pucch = gNB->pucch[id];
+ pucch->frame = frame;
+ pucch->slot = slot;
+ pucch->active = 1;
+ memcpy((void*)&pucch->pucch_pdu, (void*)pucch_pdu, sizeof(nfapi_nr_pucch_pdu_t));
+
+}
+
+
+int get_pucch0_cs_lut_index(PHY_VARS_gNB *gNB,nfapi_nr_pucch_pdu_t* pucch_pdu) {
+
+ int i=0;
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("getting index for LUT with %d entries, Nid %d\n",gNB->pucch0_lut.nb_id, pucch_pdu->hopping_id);
+#endif
+
+ for (i=0;i<gNB->pucch0_lut.nb_id;i++) {
+ if (gNB->pucch0_lut.Nid[i] == pucch_pdu->hopping_id) break;
+ }
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("found index %d\n",i);
+#endif
+ if (i<gNB->pucch0_lut.nb_id) return(i);
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Initializing PUCCH0 LUT index %i with Nid %d\n",i, pucch_pdu->hopping_id);
+#endif
+ // initialize
+ gNB->pucch0_lut.Nid[gNB->pucch0_lut.nb_id]=pucch_pdu->hopping_id;
+ for (int slot=0;slot<10<<pucch_pdu->subcarrier_spacing;slot++)
+ for (int symbol=0;symbol<14;symbol++)
+ gNB->pucch0_lut.lut[gNB->pucch0_lut.nb_id][slot][symbol] = (int)floor(nr_cyclic_shift_hopping(pucch_pdu->hopping_id,0,0,symbol,0,slot)/0.5235987756);
+ gNB->pucch0_lut.nb_id++;
+ return(gNB->pucch0_lut.nb_id-1);
+}
+
+
+
+int16_t idft12_re[12][12] = {
+ {23170,23170,23170,23170,23170,23170,23170,23170,23170,23170,23170,23170},
+ {23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585,0,11585,20066},
+ {23170,11585,-11585,-23170,-11585,11585,23170,11585,-11585,-23170,-11585,11585},
+ {23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170,0},
+ {23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585},
+ {23170,-20066,11585,0,-11585,20066,-23170,20066,-11585,0,11585,-20066},
+ {23170,-23170,23170,-23170,23170,-23170,23170,-23170,23170,-23170,23170,-23170},
+ {23170,-20066,11585,0,-11585,20066,-23170,20066,-11585,0,11585,-20066},
+ {23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585,23170,-11585,-11585},
+ {23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170,0},
+ {23170,11585,-11585,-23170,-11585,11585,23170,11585,-11585,-23170,-11585,11585},
+ {23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585,0,11585,20066}
+};
+
+int16_t idft12_im[12][12] = {
+ {0,0,0,0,0,0,0,0,0,0,0,0},
+ {0,11585,20066,23170,20066,11585,0,-11585,-20066,-23170,-20066,-11585},
+ {0,20066,20066,0,-20066,-20066,0,20066,20066,0,-20066,-20066},
+ {0,23170,0,-23170,0,23170,0,-23170,0,23170,0,-23170},
+ {0,20066,-20066,0,20066,-20066,0,20066,-20066,0,20066,-20066},
+ {0,11585,-20066,23170,-20066,11585,0,-11585,20066,-23170,20066,-11585},
+ {0,0,0,0,0,0,0,0,0,0,0,0},
+ {0,-11585,20066,-23170,20066,-11585,0,11585,-20066,23170,-20066,11585},
+ {0,-20066,20066,0,-20066,20066,0,-20066,20066,0,-20066,20066},
+ {0,-23170,0,23170,0,-23170,0,23170,0,-23170,0,23170},
+ {0,-20066,-20066,0,20066,20066,0,-20066,-20066,0,20066,20066},
+ {0,-11585,-20066,-23170,-20066,-11585,0,11585,20066,23170,20066,11585}
+};
+
+
+void nr_decode_pucch0(PHY_VARS_gNB *gNB,
+ int slot,
+ nfapi_nr_uci_pucch_pdu_format_0_1_t* uci_pdu,
+ nfapi_nr_pucch_pdu_t* pucch_pdu) {
+
+
+ int32_t **rxdataF = gNB->common_vars.rxdataF;
+ NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
-void nr_decode_pucch0( int32_t **rxdataF,
- pucch_GroupHopping_t pucch_GroupHopping,
- uint32_t n_id, // hoppingID higher layer parameter
- uint64_t *payload,
- NR_DL_FRAME_PARMS *frame_parms,
- int16_t amp,
- int nr_tti_tx,
- uint8_t m0, // should come from resource set
- uint8_t nrofSymbols, // should come from resource set
- uint8_t startingSymbolIndex, // should come from resource set
- uint16_t startingPRB, // should come from resource set
- uint8_t nr_bit) { // is number of UCI bits to be decoded
int nr_sequences;
const uint8_t *mcs;
- if(nr_bit==1){
+
+ pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1);
+
+ AssertFatal(pucch_pdu->bit_len_harq > 0 || pucch_pdu->sr_flag > 0,
+ "Either bit_len_harq (%d) or sr_flag (%d) must be > 0\n",
+ pucch_pdu->bit_len_harq,pucch_pdu->sr_flag);
+
+ if(pucch_pdu->bit_len_harq==0){
+ mcs=table1_mcs;
+ nr_sequences=1;
+ }
+ else if(pucch_pdu->bit_len_harq==1){
mcs=table1_mcs;
- nr_sequences=4;
+ nr_sequences=4>>(1-pucch_pdu->sr_flag);
}
else{
mcs=table2_mcs;
- nr_sequences=8;
+ nr_sequences=8>>(1-pucch_pdu->sr_flag);
}
+
+ int cs_ind = get_pucch0_cs_lut_index(gNB,pucch_pdu);
/*
* Implement TS 38.211 Subclause 6.3.2.3.1 Sequence generation
*
@@ -48,13 +201,11 @@ void nr_decode_pucch0( int32_t **rxdataF,
* Defining cyclic shift hopping TS 38.211 Subclause 6.3.2.2.2
*/
// alpha is cyclic shift
- double alpha;
+ //double alpha;
// lnormal is the OFDM symbol number in the PUCCH transmission where l=0 corresponds to the first OFDM symbol of the PUCCH transmission
//uint8_t lnormal;
// lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213]
//uint8_t lprime;
- // mcs is provided by TC 38.213 subclauses 9.2.3, 9.2.4, 9.2.5 FIXME!
- //uint8_t mcs;
/*
* in TS 38.213 Subclause 9.2.1 it is said that:
@@ -73,76 +224,76 @@ void nr_decode_pucch0( int32_t **rxdataF,
// if frequency hopping is enabled by the higher-layer parameter PUCCH-frequency-hopping
// n_hop = 0 for first hop
// n_hop = 1 for second hop
- uint8_t n_hop = 0;
- //uint8_t PUCCH_Frequency_Hopping; // from higher layers FIXME!!
+ uint8_t n_hop = 0; // Frequnecy hopping not implemented FIXME!!
// x_n contains the sequence r_u_v_alpha_delta(n)
- int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24];
+
int n,i,l;
+ nr_group_sequence_hopping(pucch_GroupHopping,pucch_pdu->hopping_id,n_hop,slot,&u,&v); // calculating u and v value
+
+ uint32_t re_offset=0;
+ uint8_t l2;
+
+#ifdef OLD_IMPL
+ int16_t x_n_re[nr_sequences][24],x_n_im[nr_sequences][24];
+
for(i=0;i<nr_sequences;i++){
- // we proceed to calculate alpha according to TS 38.211 Subclause 6.3.2.2.2
- for (l=0; l<nrofSymbols; l++){
- // if frequency hopping is enabled n_hop = 1 for second hop. Not sure frequency hopping concerns format 0. FIXME!!!
- // if ((PUCCH_Frequency_Hopping == 1)&&(l == (nrofSymbols-1))) n_hop = 1;
- nr_group_sequence_hopping(pucch_GroupHopping,n_id,n_hop,nr_tti_tx,&u,&v); // calculating u and v value
- alpha = nr_cyclic_shift_hopping(n_id,m0,mcs[i],l,startingSymbolIndex,nr_tti_tx);
- #ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d)\n",u,v,alpha,l);
- #endif
+ // we proceed to calculate alpha according to TS 38.211 Subclause 6.3.2.2.2
+ for (l=0; l<pucch_pdu->nr_of_symbols; l++){
+ double alpha = nr_cyclic_shift_hopping(pucch_pdu->hopping_id,pucch_pdu->initial_cyclic_shift,mcs[i],l,pucch_pdu->start_symbol_index,slot);
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d/%d,mcs %d)\n",u,v,alpha,l,l+pucch_pdu->start_symbol_index,mcs[i]);
+ printf("lut output %d\n",gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index]);
+#endif
+ alpha=0.0;
for (n=0; n<12; n++){
- x_n_re[i][(12*l)+n] = (int16_t)((int32_t)(amp)*(int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)
- - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))>>15); // Re part of base sequence shifted by alpha
- x_n_im[i][(12*l)+n] =(int16_t)((int32_t)(amp)* (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)
- + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))>>15); // Im part of base sequence shifted by alpha
- #ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d)\n",
- u,v,alpha,l,n,x_n_re[(12*l)+n],x_n_im[(12*l)+n]);
- #endif
+ x_n_re[i][(12*l)+n] = (int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)
+ - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)))); // Re part of base sequence shifted by alpha
+ x_n_im[i][(12*l)+n] =(int16_t)((int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)
+ + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)))); // Im part of base sequence shifted by alpha
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \tx_n(l=%d,n=%d)=(%d,%d) %d,%d\n",
+ u,v,alpha,l,n,x_n_re[i][(12*l)+n],x_n_im[i][(12*l)+n],
+ (int32_t)(round(32767*cos(alpha*n))),
+ (int32_t)(round(32767*sin(alpha*n))));
+#endif
}
}
}
- int16_t r_re[24],r_im[24];
/*
- * Implementing TS 38.211 Subclause 6.3.2.3.2 Mapping to physical resources FIXME!
+ * Implementing TS 38.211 Subclause 6.3.2.3.2 Mapping to physical resources
*/
- uint32_t re_offset=0;
- for (l=0; l<nrofSymbols; l++) {
- if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
- if ((startingPRB >= (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is upper band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1)));
- }
- if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is lower band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
- if ((startingPRB > (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is upper band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))) + 6;
- }
- if ((startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB contains DC
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
+
+ int16_t r_re[24],r_im[24];
+
+ for (l=0; l<pucch_pdu->nr_of_symbols; l++) {
+
+ l2 = l+pucch_pdu->start_symbol_index;
+ re_offset = (12*pucch_pdu->prb_start) + (12*pucch_pdu->bwp_start) + frame_parms->first_carrier_offset;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
+
for (n=0; n<12; n++){
- if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) {
- // if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB)
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size);
- }
- r_re[(12*l)+n]=((int16_t *)&rxdataF[0][re_offset])[0];
- r_im[(12*l)+n]=((int16_t *)&rxdataF[0][re_offset])[1];
- #ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch0] mapping to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n",
- amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,re_offset,
- l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]);
- #endif
+
+ r_re[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0];
+ r_im[(12*l)+n]=((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1];
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("\t [nr_generate_pucch0] mapping to RE \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n",
+ frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size)+re_offset,
+ l,n,((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[0],
+ ((int16_t *)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size)+re_offset])[1]);
+#endif
re_offset++;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
}
- }
+ }
double corr[nr_sequences],corr_re[nr_sequences],corr_im[nr_sequences];
memset(corr,0,nr_sequences*sizeof(double));
memset(corr_re,0,nr_sequences*sizeof(double));
memset(corr_im,0,nr_sequences*sizeof(double));
for(i=0;i<nr_sequences;i++){
- for(l=0;l<nrofSymbols;l++){
+ for(l=0;l<pucch_pdu->nr_of_symbols;l++){
for(n=0;n<12;n++){
corr_re[i]+= (double)(r_re[12*l+n])/32767*(double)(x_n_re[i][12*l+n])/32767+(double)(r_im[12*l+n])/32767*(double)(x_n_im[i][12*l+n])/32767;
corr_im[i]+= (double)(r_re[12*l+n])/32767*(double)(x_n_im[i][12*l+n])/32767-(double)(r_im[12*l+n])/32767*(double)(x_n_re[i][12*l+n])/32767;
@@ -151,14 +302,122 @@ void nr_decode_pucch0( int32_t **rxdataF,
corr[i]=corr_re[i]*corr_re[i]+corr_im[i]*corr_im[i];
}
float max_corr=corr[0];
- int index=0;
+ uint8_t index=0;
for(i=1;i<nr_sequences;i++){
if(corr[i]>max_corr){
index= i;
max_corr=corr[i];
}
}
- *payload=(uint64_t)index; // payload bits 00..b3b2b0, b0 is the SR bit and b3b2 are HARQ bits
+#else
+
+ const int16_t *x_re = table_5_2_2_2_2_Re[u],*x_im = table_5_2_2_2_2_Im[u];
+ int16_t xr[24] __attribute__((aligned(32)));
+ //int16_t xrt[24] __attribute__((aligned(32)));
+ int32_t xrtmag=0;
+ int maxpos=0;
+ int n2=0;
+ uint8_t index=0;
+ memset((void*)xr,0,24*sizeof(int16_t));
+
+ for (l=0; l<pucch_pdu->nr_of_symbols; l++) {
+
+ l2 = l+pucch_pdu->start_symbol_index;
+ re_offset = (12*pucch_pdu->prb_start) + frame_parms->first_carrier_offset;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
+
+ AssertFatal(re_offset+12 < frame_parms->ofdm_symbol_size,"pucch straddles DC carrier, handle this!\n");
+
+ int16_t *r=(int16_t*)&rxdataF[0][(l2*frame_parms->ofdm_symbol_size+re_offset)];
+ for (n=0;n<12;n++,n2+=2) {
+ xr[n2] =(int16_t)(((int32_t)x_re[n]*r[n2]+(int32_t)x_im[n]*r[n2+1])>>15);
+ xr[n2+1]=(int16_t)(((int32_t)x_re[n]*r[n2+1]-(int32_t)x_im[n]*r[n2])>>15);
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("x (%d,%d), r (%d,%d), xr (%d,%d)\n",
+ x_re[n],x_im[n],r[n2],r[n2+1],xr[n2],xr[n2+1]);
+#endif
+ }
+ }
+ int32_t corr_re,corr_im,temp;
+ int seq_index;
+
+ for(i=0;i<nr_sequences;i++){
+ corr_re=0;corr_im=0;
+ n2=0;
+ for (l=0;l<pucch_pdu->nr_of_symbols;l++) {
+
+ seq_index = (pucch_pdu->initial_cyclic_shift+
+ mcs[i]+
+ gNB->pucch0_lut.lut[cs_ind][slot][l+pucch_pdu->start_symbol_index])%12;
+ for (n=0;n<12;n++,n2+=2) {
+ corr_re+=(xr[n2]*idft12_re[seq_index][n]+xr[n2+1]*idft12_im[seq_index][n])>>15;
+ corr_im+=(xr[n2]*idft12_im[seq_index][n]-xr[n2+1]*idft12_re[seq_index][n])>>15;
+ }
+ }
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("PUCCH IDFT[%d/%d] = (%d,%d)=>%f\n",mcs[i],seq_index,corr_re,corr_im,10*log10(corr_re*corr_re + corr_im*corr_im));
+#endif
+ if ((temp=corr_re*corr_re + corr_im*corr_im)>xrtmag) {
+ xrtmag=temp;
+ maxpos=i;
+ }
+ }
+
+ uint8_t xrtmag_dB = dB_fixed(xrtmag);
+
+//#ifdef DEBUG_NR_PUCCH_RX
+ printf("PUCCH 0 : maxpos %d\n",maxpos);
+//#endif
+
+ index=maxpos;
+#endif
+ // first bit of bitmap for sr presence and second bit for acknack presence
+ uci_pdu->pduBitmap = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1);
+ uci_pdu->pucch_format = 0; // format 0
+ uci_pdu->ul_cqi = 0xff; // currently not valid
+ uci_pdu->timing_advance = 0xffff; // currently not valid
+ uci_pdu->rssi = 0xffff; // currently not valid
+
+ if (pucch_pdu->bit_len_harq==0) {
+ uci_pdu->harq = NULL;
+ uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr));
+ if (xrtmag_dB>(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres)) {
+ uci_pdu->sr->sr_indication = 1;
+ uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres);
+ } else {
+ uci_pdu->sr->sr_indication = 0;
+ uci_pdu->sr->sr_confidence_level = (gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres)-xrtmag_dB;
+ }
+ }
+ else if (pucch_pdu->bit_len_harq==1) {
+ uci_pdu->harq = calloc(1,sizeof(*uci_pdu->harq));
+ uci_pdu->harq->num_harq = 1;
+ uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres);
+ uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(1);
+ uci_pdu->harq->harq_list[0].harq_value = index&0x01;
+ if (pucch_pdu->sr_flag == 1) {
+ uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr));
+ uci_pdu->sr->sr_indication = (index>1) ? 1 : 0;
+ uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres);
+ }
+ }
+ else {
+ uci_pdu->harq = calloc(1,sizeof(*uci_pdu->harq));
+ uci_pdu->harq->num_harq = 2;
+ uci_pdu->harq->harq_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres);
+ uci_pdu->harq->harq_list = (nfapi_nr_harq_t*)malloc(2);
+
+ uci_pdu->harq->harq_list[1].harq_value = index&0x01;
+ uci_pdu->harq->harq_list[0].harq_value = (index>>1)&0x01;
+
+ if (pucch_pdu->sr_flag == 1) {
+ uci_pdu->sr = calloc(1,sizeof(*uci_pdu->sr));
+ uci_pdu->sr->sr_indication = (index>3) ? 1 : 0;
+ uci_pdu->sr->sr_confidence_level = xrtmag_dB-(gNB->measurements.n0_subband_power_tot_dB[pucch_pdu->prb_start]+gNB->pucch0_thres);
+ }
+ }
}
@@ -180,7 +439,7 @@ void nr_decode_pucch1( int32_t **rxdataF,
uint8_t timeDomainOCC,
uint8_t nr_bit) {
#ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch1] start function at slot(nr_tti_tx)=%d payload=%d m0=%d nrofSymbols=%d startingSymbolIndex=%d startingPRB=%d startingPRB_intraSlotHopping=%d timeDomainOCC=%d nr_bit=%d\n",
+ printf("\t [nr_generate_pucch1] start function at slot(nr_tti_tx)=%d payload=%lp m0=%d nrofSymbols=%d startingSymbolIndex=%d startingPRB=%d startingPRB_intraSlotHopping=%d timeDomainOCC=%d nr_bit=%d\n",
nr_tti_tx,payload,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit);
#endif
/*
@@ -190,7 +449,7 @@ void nr_decode_pucch1( int32_t **rxdataF,
// complex-valued symbol d_re, d_im containing complex-valued symbol d(0):
int16_t d_re=0, d_im=0,d1_re=0,d1_im=0;
#ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch1] sequence modulation: payload=%x \tde_re=%d \tde_im=%d\n",payload,d_re,d_im);
+ printf("\t [nr_generate_pucch1] sequence modulation: payload=%lp \tde_re=%d \tde_im=%d\n",payload,d_re,d_im);
#endif
/*
* Defining cyclic shift hopping TS 38.211 Subclause 6.3.2.2.2
@@ -274,7 +533,6 @@ void nr_decode_pucch1( int32_t **rxdataF,
re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
}
- //txptr = &txdataF[0][re_offset];
for (int n=0; n<12; n++) {
if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) {
// if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB)
@@ -285,22 +543,22 @@ void nr_decode_pucch1( int32_t **rxdataF,
z_re_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[0];
z_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1];
#ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch1] mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n",
+ printf("\t [nr_generate_pucch1] mapping PUCCH to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_pucch[%d]=txptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n",
amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset,
- l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]);
+ l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]);
#endif
}
if (l%2 == 0) { // mapping DM-RS signal according to TS38.211 subclause 6.4.1.3.1
z_dmrs_re_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[0];
z_dmrs_im_rx[i+n] = ((int16_t *)&rxdataF[0][re_offset])[1];
-// printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]);
+ // printf("%d\t%d\t%d\n",l,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]);
#ifdef DEBUG_NR_PUCCH_RX
- printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%d)=(x_n(l=%d,n=%d)=(%d,%d))\n",
+ printf("\t [nr_generate_pucch1] mapping DM-RS to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \tz_dm-rs[%d]=txptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n",
amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,i+n,re_offset,
- l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]);
+ l,n,((int16_t *)&rxdataF[0][re_offset])[0],((int16_t *)&rxdataF[0][re_offset])[1]);
#endif
-// printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]);
+ // printf("l=%d\ti=%d\tre_offset=%d\treceived dmrs re=%d\tim=%d\n",l,i,re_offset,z_dmrs_re_rx[i+n],z_dmrs_im_rx[i+n]);
}
re_offset++;
@@ -319,7 +577,7 @@ void nr_decode_pucch1( int32_t **rxdataF,
l,lprime);
#endif
// y_n contains the complex value d multiplied by the sequence r_u_v
- if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop
+ if ((intraSlotFrequencyHopping == 1) && (l >= (int)floor(nrofSymbols/2))) n_hop = 1; // n_hop = 1 for second hop
#ifdef DEBUG_NR_PUCCH_RX
printf("\t [nr_generate_pucch1] entering function nr_group_sequence_hopping with n_hop=%d, nr_tti_tx=%d\n",
@@ -337,18 +595,18 @@ void nr_decode_pucch1( int32_t **rxdataF,
}
else{
r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15)
- - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha
+ - (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15))); // Re part of DMRS base sequence shifted by alpha
r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((((int32_t)(round(32767*cos(alpha*n))) * table_5_2_2_2_2_Im[u][n])>>15)
- + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha
+ + (((int32_t)(round(32767*sin(alpha*n))) * table_5_2_2_2_2_Re[u][n])>>15))); // Im part of DMRS base sequence shifted by alpha
r_u_v_alpha_delta_dmrs_re[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_re[n]))>>15);
r_u_v_alpha_delta_dmrs_im[n] = (int16_t)(((int32_t)(amp*r_u_v_alpha_delta_dmrs_im[n]))>>15);
}
-// printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]);
+ // printf("symbol=%d\tr_u_rx_re=%d\tr_u_rx_im=%d\n",l,r_u_v_alpha_delta_dmrs_re[n], r_u_v_alpha_delta_dmrs_im[n]);
// PUCCH sequence = DM-RS sequence multiplied by d(0)
-/* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15)
- - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n)
- y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15)
- + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */
+ /* y_n_re[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_re)>>15)
+ - (((int32_t)(r_u_v_alpha_delta_im[n])*d_im)>>15))); // Re part of y(n)
+ y_n_im[n] = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*d_im)>>15)
+ + (((int32_t)(r_u_v_alpha_delta_im[n])*d_re)>>15))); // Im part of y(n) */
#ifdef DEBUG_NR_PUCCH_RX
printf("\t [nr_generate_pucch1] sequence generation \tu=%d \tv=%d \talpha=%lf \tr_u_v_alpha_delta[n=%d]=(%d,%d) \ty_n[n=%d]=(%d,%d)\n",
u,v,alpha,n,r_u_v_alpha_delta_re[n],r_u_v_alpha_delta_im[n],n,y_n_re[n],y_n_im[n]);
@@ -398,30 +656,30 @@ void nr_decode_pucch1( int32_t **rxdataF,
if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){
for (int n=0; n<12 ; n++) {
z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_re_temp;
z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]=z_im_temp;
-// printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ // printf("symbol=%d\tz_re_rx=%d\tz_im_rx=%d\t",l,(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#ifdef DEBUG_NR_PUCCH_RX
printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n",
mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n,
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],
- z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#endif
// multiplying with conjugate of low papr sequence
z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp;
z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp;
-/* if(z_re_temp<0){
- printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15));
- }
- printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */
+ /* if(z_re_temp<0){
+ printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_re[n],z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15));
+ }
+ printf("z1_re_rx=%d\tz1_im_rx=%d\n",(int)z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]); */
}
}
}
@@ -432,32 +690,32 @@ void nr_decode_pucch1( int32_t **rxdataF,
if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){
for (int n=0; n<12 ; n++) {
z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp;
z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp;
-// printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ // printf("symbol=%d\tz_dmrs_re_rx=%d\tz_dmrs_im_rx=%d\t",l,(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#ifdef DEBUG_NR_PUCCH_RX
printf("\t [nr_generate_pucch1] block-wise spread with wi(m) (mprime=%d, m=%d, n=%d) z[%d] = ((%d * %d - %d * %d), (%d * %d + %d * %d)) = (%d,%d)\n",
mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n,
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],
- z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#endif
//finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays
z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
-/* if(z_dmrs_re_temp<0){
- printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15));
- }*/
+ - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ /* if(z_dmrs_re_temp<0){
+ printf("\nBug detection %d\t%d\t%d\t%d\n",r_u_v_alpha_delta_dmrs_re[n],z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15),(((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15));
+ }*/
z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp;
z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp;
-// printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
- /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n];
- z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */
+ // printf("z1_dmrs_re_rx=%d\tz1_dmrs_im_rx=%d\n",(int)z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],(int)z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n];
+ z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */
}
}
}
@@ -484,9 +742,9 @@ void nr_decode_pucch1( int32_t **rxdataF,
if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)){
for (int n=0; n<12 ; n++) {
z_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp;
z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp;
#ifdef DEBUG_NR_PUCCH_RX
@@ -494,12 +752,12 @@ void nr_decode_pucch1( int32_t **rxdataF,
mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n,
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],y_n_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],y_n_re[n],
- z_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#endif
z_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(r_u_v_alpha_delta_im[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_re[n])*z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15)
- - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(r_u_v_alpha_delta_im[n])*z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n])>>15))>>1);
z_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_re_temp;
z_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n] = z_im_temp;
}
@@ -512,9 +770,9 @@ void nr_decode_pucch1( int32_t **rxdataF,
if(floor(l/2)*12==(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)){
for (int n=0; n<12 ; n++) {
z_dmrs_re_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_im_temp = (int16_t)(((((int32_t)(table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_DMRS_1][w_index][m])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp;
z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp;
#ifdef DEBUG_NR_PUCCH_RX
@@ -522,18 +780,18 @@ void nr_decode_pucch1( int32_t **rxdataF,
mprime, m, n, (mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n,
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],
table_6_3_2_4_1_2_Wi_Re[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_im[n],table_6_3_2_4_1_2_Wi_Im[N_SF_mprime_PUCCH_1][w_index][m],r_u_v_alpha_delta_dmrs_re[n],
- z_dmrs_re[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
+ z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n],z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_1)+(m*12)+n]);
#endif
//finding channel coeffcients by dividing received dmrs with actual dmrs and storing them in z_dmrs_re_rx and z_dmrs_im_rx arrays
z_dmrs_re_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ + (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_im_temp = (int16_t)(((((int32_t)(r_u_v_alpha_delta_dmrs_re[n])*z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15)
- - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
+ - (((int32_t)(r_u_v_alpha_delta_dmrs_im[n])*z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n])>>15))>>1);
z_dmrs_re_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_re_temp;
z_dmrs_im_rx[(mprime*12*N_SF_mprime0_PUCCH_DMRS_1)+(m*12)+n] = z_dmrs_im_temp;
- /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n];
- z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */
+ /* z_dmrs_re_rx[(int)(l/2)*12+n]=z_dmrs_re_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_re[n];
+ z_dmrs_im_rx[(int)(l/2)*12+n]=z_dmrs_im_rx[(int)(l/2)*12+n]/r_u_v_alpha_delta_dmrs_im[n]; */
}
}
}
@@ -585,8 +843,8 @@ void nr_decode_pucch1( int32_t **rxdataF,
for(int n=0;n<12;n++){
y_n_re[n]=round(z_re_rx[l*12+n]/floor(nrofSymbols/4))+y_n_re[n];
y_n_im[n]=round(z_im_rx[l*12+n]/floor(nrofSymbols/4))+y_n_im[n];
- }
- }
+ }
+ }
else{
for(int n=0;n<12;n++){
y1_n_re[n]=round(z_re_rx[l*12+n]/round(nrofSymbols/4))+y1_n_re[n];
@@ -618,12 +876,12 @@ void nr_decode_pucch1( int32_t **rxdataF,
}
//Decoding QPSK or BPSK symbols to obtain payload bits
if(nr_bit==1){
- if((d_re+d_im)>0){
- *payload=0;
- }
- else{
- *payload=1;
- }
+ if((d_re+d_im)>0){
+ *payload=0;
+ }
+ else{
+ *payload=1;
+ }
}
else if(nr_bit==2){
if((d_re>0)&&(d_im>0)){
@@ -641,3 +899,761 @@ void nr_decode_pucch1( int32_t **rxdataF,
}
}
+__m256i pucch2_3bit[8*2];
+__m256i pucch2_4bit[16*2];
+__m256i pucch2_5bit[32*2];
+__m256i pucch2_6bit[64*2];
+__m256i pucch2_7bit[128*2];
+__m256i pucch2_8bit[256*2];
+__m256i pucch2_9bit[512*2];
+__m256i pucch2_10bit[1024*2];
+__m256i pucch2_11bit[2048*2];
+
+__m256i *pucch2_lut[9]={pucch2_3bit,
+ pucch2_4bit,
+ pucch2_5bit,
+ pucch2_6bit,
+ pucch2_7bit,
+ pucch2_8bit,
+ pucch2_9bit,
+ pucch2_10bit,
+ pucch2_11bit};
+
+__m64 pucch2_polar_4bit[16];
+__m128i pucch2_polar_llr_num_lut[256],pucch2_polar_llr_den_lut[256];
+
+void init_pucch2_luts() {
+
+ uint32_t out;
+ int8_t bit;
+
+ for (int b=3;b<12;b++) {
+ for (uint16_t i=0;i<(1<<b);i++) {
+ out=encodeSmallBlock(&i,b);
+#ifdef DEBUG_NR_PUCCH_RX
+ if (b==3) printf("in %d, out %x\n",i,out);
+#endif
+ __m256i *lut_i=&pucch2_lut[b-3][i<<1];
+ __m256i *lut_ip1=&pucch2_lut[b-3][1+(i<<1)];
+ bit = (out&0x1) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,0);
+ bit = (out&0x2) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,0);
+ bit = (out&0x4) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,1);
+ bit = (out&0x8) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,1);
+ bit = (out&0x10) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,2);
+ bit = (out&0x20) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,2);
+ bit = (out&0x40) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,3);
+ bit = (out&0x80) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,3);
+ bit = (out&0x100) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,4);
+ bit = (out&0x200) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,4);
+ bit = (out&0x400) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,5);
+ bit = (out&0x800) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,5);
+ bit = (out&0x1000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,6);
+ bit = (out&0x2000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,6);
+ bit = (out&0x4000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,7);
+ bit = (out&0x8000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,7);
+ bit = (out&0x10000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,8);
+ bit = (out&0x20000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,8);
+ bit = (out&0x40000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,9);
+ bit = (out&0x80000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,9);
+ bit = (out&0x100000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,10);
+ bit = (out&0x200000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,10);
+ bit = (out&0x400000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,11);
+ bit = (out&0x800000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,11);
+ bit = (out&0x1000000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,12);
+ bit = (out&0x2000000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,12);
+ bit = (out&0x4000000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,13);
+ bit = (out&0x8000000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,13);
+ bit = (out&0x10000000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,14);
+ bit = (out&0x20000000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,14);
+ bit = (out&0x40000000) > 0 ? -1 : 1;
+ *lut_i = _mm256_insert_epi16(*lut_i,bit,15);
+ bit = (out&0x80000000) > 0 ? -1 : 1;
+ *lut_ip1 = _mm256_insert_epi16(*lut_ip1,bit,15);
+ }
+ }
+ for (uint16_t i=0;i<16;i++) {
+ __m64 *lut_i=&pucch2_polar_4bit[i];
+
+ bit = (i&0x1) > 0 ? -1 : 1;
+ *lut_i = _mm_insert_pi16(*lut_i,bit,0);
+ bit = (i&0x2) > 0 ? -1 : 1;
+ *lut_i = _mm_insert_pi16(*lut_i,bit,1);
+ bit = (i&0x4) > 0 ? -1 : 1;
+ *lut_i = _mm_insert_pi16(*lut_i,bit,2);
+ bit = (i&0x8) > 0 ? -1 : 1;
+ *lut_i = _mm_insert_pi16(*lut_i,bit,3);
+ }
+ for (int i=0;i<256;i++) {
+ __m128i *lut_num_i=&pucch2_polar_llr_num_lut[i];
+ __m128i *lut_den_i=&pucch2_polar_llr_den_lut[i];
+ bit = (i&0x1) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,0);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,0);
+
+ bit = (i&0x10) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,1);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,1);
+
+ bit = (i&0x2) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,2);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,2);
+
+ bit = (i&0x20) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,3);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,3);
+
+ bit = (i&0x4) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,4);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,4);
+
+ bit = (i&0x40) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,5);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,5);
+
+ bit = (i&0x8) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,6);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,6);
+
+ bit = (i&0x80) > 0 ? 0 : 1;
+ *lut_num_i = _mm_insert_epi16(*lut_num_i,bit,7);
+ *lut_den_i = _mm_insert_epi16(*lut_den_i,1-bit,7);
+ printf("i %d, lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",i,
+ ((int16_t *)lut_num_i)[0],
+ ((int16_t *)lut_num_i)[1],
+ ((int16_t *)lut_num_i)[2],
+ ((int16_t *)lut_num_i)[3],
+ ((int16_t *)lut_num_i)[4],
+ ((int16_t *)lut_num_i)[5],
+ ((int16_t *)lut_num_i)[6],
+ ((int16_t *)lut_num_i)[7]);
+ }
+}
+
+
+void nr_decode_pucch2(PHY_VARS_gNB *gNB,
+ int slot,
+ nfapi_nr_uci_pucch_pdu_format_2_3_4_t* uci_pdu,
+ nfapi_nr_pucch_pdu_t* pucch_pdu) {
+
+ int32_t **rxdataF = gNB->common_vars.rxdataF;
+ NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
+ //pucch_GroupHopping_t pucch_GroupHopping = pucch_pdu->group_hop_flag + (pucch_pdu->sequence_hop_flag<<1);
+
+
+
+ AssertFatal(pucch_pdu->nr_of_symbols==1 || pucch_pdu->nr_of_symbols==2,
+ "Illegal number of symbols for PUCCH 2 %d\n",pucch_pdu->nr_of_symbols);
+
+
+ //extract pucch and dmrs first
+
+ int l2=pucch_pdu->start_symbol_index;
+ int re_offset = (12*pucch_pdu->prb_start) + (12*pucch_pdu->bwp_start) + frame_parms->first_carrier_offset;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
+
+ AssertFatal(pucch_pdu->prb_size*pucch_pdu->nr_of_symbols > 1,"number of PRB*SYMB (%d,%d)< 2",
+ pucch_pdu->prb_size,pucch_pdu->nr_of_symbols);
+
+ int Prx = gNB->gNB_config.carrier_config.num_rx_ant.value;
+ int Prx2 = (Prx==1)?2:Prx;
+ // use 2 for Nb antennas in case of single antenna to allow the following allocations
+ int16_t r_re_ext[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t r_im_ext[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t r_re_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t r_im_ext2[Prx2][8*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t rd_re_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t rd_im_ext[Prx2][4*pucch_pdu->nr_of_symbols*pucch_pdu->prb_size] __attribute__((aligned(32)));
+ int16_t *r_re_ext_p,*r_im_ext_p,*rd_re_ext_p,*rd_im_ext_p;
+
+ int16_t *rp[Prx2];
+ __m64 dmrs_re,dmrs_im;
+
+ for (int aa=0;aa<Prx;aa++) rp[aa] = ((int16_t *)&rxdataF[aa][(l2*frame_parms->ofdm_symbol_size)+re_offset]);
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Decoding pucch2 for %d symbols, %d PRB\n",pucch_pdu->nr_of_symbols,pucch_pdu->prb_size);
+#endif
+
+ int nc_group_size=1; // 2 PRB
+ int ngroup = pucch_pdu->prb_size/nc_group_size/2;
+ int32_t corr32_re[ngroup][Prx2],corr32_im[ngroup][Prx2];
+ for (int aa=0;aa<Prx;aa++) for (int group=0;group<ngroup;group++) { corr32_re[group][aa]=0; corr32_im[group][aa]=0;}
+
+ if (pucch_pdu->nr_of_symbols == 1) {
+ AssertFatal((pucch_pdu->prb_size&1) == 0,"prb_size %d is not a multiple of 2\n",pucch_pdu->prb_size);
+ // 24 PRBs contains 48x16-bit, so 6x8x16-bit
+ for (int prb=0;prb<pucch_pdu->prb_size;prb+=2) {
+ for (int aa=0;aa<Prx;aa++) {
+ r_re_ext_p=&r_re_ext[aa][8*prb];
+ r_im_ext_p=&r_im_ext[aa][8*prb];
+ rd_re_ext_p=&rd_re_ext[aa][4*prb];
+ rd_im_ext_p=&rd_im_ext[aa][4*prb];
+
+ r_re_ext_p[0]=rp[aa][0];
+ r_im_ext_p[0]=rp[aa][1];
+ rd_re_ext_p[0]=rp[aa][2];
+ rd_im_ext_p[0]=rp[aa][3];
+ r_re_ext_p[1]=rp[aa][4];
+ r_im_ext_p[1]=rp[aa][5];
+
+ r_re_ext_p[2]=rp[aa][6];
+ r_im_ext_p[2]=rp[aa][7];
+ rd_re_ext_p[1]=rp[aa][8];
+ rd_im_ext_p[1]=rp[aa][9];
+ r_re_ext_p[3]=rp[aa][10];
+ r_im_ext_p[3]=rp[aa][11];
+
+ r_re_ext_p[4]=rp[aa][12];
+ r_im_ext_p[4]=rp[aa][13];
+ rd_re_ext_p[2]=rp[aa][14];
+ rd_im_ext_p[2]=rp[aa][15];
+ r_re_ext_p[5]=rp[aa][16];
+ r_im_ext_p[5]=rp[aa][17];
+
+ r_re_ext_p[6]=rp[aa][18];
+ r_im_ext_p[6]=rp[aa][19];
+ rd_re_ext_p[3]=rp[aa][20];
+ rd_im_ext_p[3]=rp[aa][21];
+ r_re_ext_p[7]=rp[aa][22];
+ r_im_ext_p[7]=rp[aa][23];
+
+ r_re_ext_p[8]=rp[aa][24];
+ r_im_ext_p[8]=rp[aa][25];
+ rd_re_ext_p[4]=rp[aa][26];
+ rd_im_ext_p[4]=rp[aa][27];
+ r_re_ext_p[9]=rp[aa][28];
+ r_im_ext_p[9]=rp[aa][29];
+
+ r_re_ext_p[10]=rp[aa][30];
+ r_im_ext_p[10]=rp[aa][31];
+ rd_re_ext_p[5]=rp[aa][32];
+ rd_im_ext_p[5]=rp[aa][33];
+ r_re_ext_p[11]=rp[aa][34];
+ r_im_ext_p[11]=rp[aa][35];
+
+ r_re_ext_p[12]=rp[aa][36];
+ r_im_ext_p[12]=rp[aa][37];
+ rd_re_ext_p[6]=rp[aa][38];
+ rd_im_ext_p[6]=rp[aa][39];
+ r_re_ext_p[13]=rp[aa][40];
+ r_im_ext_p[13]=rp[aa][41];
+
+ r_re_ext_p[14]=rp[aa][42];
+ r_im_ext_p[14]=rp[aa][43];
+ rd_re_ext_p[7]=rp[aa][44];
+ rd_im_ext_p[7]=rp[aa][45];
+ r_re_ext_p[15]=rp[aa][46];
+ r_im_ext_p[15]=rp[aa][47];
+
+#ifdef DEBUG_NR_PUCCH_RX
+ for (int i=0;i<8;i++) printf("Ant %d PRB %d dmrs[%d] -> (%d,%d)\n",aa,prb+(i>>2),i,rd_re_ext_p[i],rd_im_ext_p[i]);
+ for (int i=0;i<16;i++) printf("Ant %d PRB %d data[%d] -> (%d,%d)\n",aa,prb+(i>>3),i,r_re_ext_p[i],r_im_ext_p[i]);
+#endif
+ rp[aa]+=48;
+ } // aa
+ } // prb
+
+
+ // first compute DMRS component
+ uint32_t x1, x2, s=0;
+ x2 = (((1<<17)*((14*slot) + (pucch_pdu->start_symbol_index) + 1)*((2*pucch_pdu->dmrs_scrambling_id) + 1)) + (2*pucch_pdu->dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("slot %d, start_symbol_index %d, dmrs_scrambling_id %d\n",
+ slot,pucch_pdu->start_symbol_index,pucch_pdu->dmrs_scrambling_id);
+#endif
+ s = lte_gold_generic(&x1, &x2, 1);
+
+ for (int group=0;group<ngroup;group++) {
+ // each group has 8*nc_group_size elements, compute 1 complex correlation with DMRS per group
+ // non-coherent combining across groups
+ dmrs_re = byte2m64_re[((uint8_t*)&s)[(group&1)<<1]];
+ dmrs_im = byte2m64_im[((uint8_t*)&s)[(group&1)<<1]];
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Group %d: s %x x2 %x ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ group,
+ ((uint16_t*)&s)[0],x2,
+ ((int16_t*)&dmrs_re)[0],((int16_t*)&dmrs_im)[0],
+ ((int16_t*)&dmrs_re)[1],((int16_t*)&dmrs_im)[1],
+ ((int16_t*)&dmrs_re)[2],((int16_t*)&dmrs_im)[2],
+ ((int16_t*)&dmrs_re)[3],((int16_t*)&dmrs_im)[3]);
+#endif
+ for (int aa=0;aa<Prx;aa++) {
+ rd_re_ext_p=&rd_re_ext[aa][8*group];
+ rd_im_ext_p=&rd_im_ext[aa][8*group];
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Group %d: rd ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ group,
+ rd_re_ext_p[0],rd_im_ext_p[0],
+ rd_re_ext_p[1],rd_im_ext_p[1],
+ rd_re_ext_p[2],rd_im_ext_p[2],
+ rd_re_ext_p[3],rd_im_ext_p[3]);
+#endif
+ corr32_re[group][aa]+=(rd_re_ext_p[0]*((int16_t*)&dmrs_re)[0] + rd_im_ext_p[0]*((int16_t*)&dmrs_im)[0]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[0]*((int16_t*)&dmrs_im)[0] + rd_im_ext_p[0]*((int16_t*)&dmrs_re)[0]);
+ corr32_re[group][aa]+=(rd_re_ext_p[1]*((int16_t*)&dmrs_re)[1] + rd_im_ext_p[1]*((int16_t*)&dmrs_im)[1]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[1]*((int16_t*)&dmrs_im)[1] + rd_im_ext_p[1]*((int16_t*)&dmrs_re)[1]);
+ corr32_re[group][aa]+=(rd_re_ext_p[2]*((int16_t*)&dmrs_re)[2] + rd_im_ext_p[2]*((int16_t*)&dmrs_im)[2]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[2]*((int16_t*)&dmrs_im)[2] + rd_im_ext_p[2]*((int16_t*)&dmrs_re)[2]);
+ corr32_re[group][aa]+=(rd_re_ext_p[3]*((int16_t*)&dmrs_re)[3] + rd_im_ext_p[3]*((int16_t*)&dmrs_im)[3]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[3]*((int16_t*)&dmrs_im)[3] + rd_im_ext_p[3]*((int16_t*)&dmrs_re)[3]);
+ }
+ dmrs_re = byte2m64_re[((uint8_t*)&s)[1+((group&1)<<1)]];
+ dmrs_im = byte2m64_im[((uint8_t*)&s)[1+((group&1)<<1)]];
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Group %d: s %x ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ group,
+ ((uint16_t*)&s)[1],
+ ((int16_t*)&dmrs_re)[0],((int16_t*)&dmrs_im)[0],
+ ((int16_t*)&dmrs_re)[1],((int16_t*)&dmrs_im)[1],
+ ((int16_t*)&dmrs_re)[2],((int16_t*)&dmrs_im)[2],
+ ((int16_t*)&dmrs_re)[3],((int16_t*)&dmrs_im)[3]);
+#endif
+ for (int aa=0;aa<Prx;aa++) {
+ rd_re_ext_p=&rd_re_ext[aa][8*group];
+ rd_im_ext_p=&rd_im_ext[aa][8*group];
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Group %d: rd ((%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ group,
+ rd_re_ext_p[4],rd_im_ext_p[4],
+ rd_re_ext_p[5],rd_im_ext_p[5],
+ rd_re_ext_p[6],rd_im_ext_p[6],
+ rd_re_ext_p[7],rd_im_ext_p[7]);
+#endif
+ corr32_re[group][aa]+=(rd_re_ext_p[4]*((int16_t*)&dmrs_re)[0] + rd_im_ext_p[4]*((int16_t*)&dmrs_im)[0]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[4]*((int16_t*)&dmrs_im)[0] + rd_im_ext_p[4]*((int16_t*)&dmrs_re)[0]);
+ corr32_re[group][aa]+=(rd_re_ext_p[5]*((int16_t*)&dmrs_re)[1] + rd_im_ext_p[5]*((int16_t*)&dmrs_im)[1]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[5]*((int16_t*)&dmrs_im)[1] + rd_im_ext_p[5]*((int16_t*)&dmrs_re)[1]);
+ corr32_re[group][aa]+=(rd_re_ext_p[6]*((int16_t*)&dmrs_re)[2] + rd_im_ext_p[6]*((int16_t*)&dmrs_im)[2]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[6]*((int16_t*)&dmrs_im)[2] + rd_im_ext_p[6]*((int16_t*)&dmrs_re)[2]);
+ corr32_re[group][aa]+=(rd_re_ext_p[7]*((int16_t*)&dmrs_re)[3] + rd_im_ext_p[7]*((int16_t*)&dmrs_im)[3]);
+ corr32_im[group][aa]+=(-rd_re_ext_p[7]*((int16_t*)&dmrs_im)[3] + rd_im_ext_p[7]*((int16_t*)&dmrs_re)[3]);
+ corr32_re[group][aa]>>=5;
+ corr32_im[group][aa]>>=5;
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("Group %d: corr32 (%d,%d)\n",group,corr32_re[group][aa],corr32_im[group][aa]);
+#endif
+ } //aa
+
+ if ((group&1) == 1) s = lte_gold_generic(&x1, &x2, 0);
+ } // group
+ }
+ else { // 2 symbol case
+ AssertFatal(1==0, "Fill in 2 symbol PUCCH2 case\n");
+ }
+
+ uint32_t x1, x2, s=0;
+ // unscrambling
+ x2 = ((pucch_pdu->rnti)<<15)+pucch_pdu->data_scrambling_id;
+ s = lte_gold_generic(&x1, &x2, 1);
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("x2 %x, s %x\n",x2,s);
+#endif
+ __m64 c_re0,c_im0,c_re1,c_im1,c_re2,c_im2,c_re3,c_im3;
+ re_offset=0;
+ for (int prb=0;prb<pucch_pdu->prb_size;prb+=2,re_offset+=16) {
+ c_re0 = byte2m64_re[((uint8_t*)&s)[0]];
+ c_im0 = byte2m64_im[((uint8_t*)&s)[0]];
+ c_re1 = byte2m64_re[((uint8_t*)&s)[1]];
+ c_im1 = byte2m64_im[((uint8_t*)&s)[1]];
+ c_re2 = byte2m64_re[((uint8_t*)&s)[2]];
+ c_im2 = byte2m64_im[((uint8_t*)&s)[2]];
+ c_re3 = byte2m64_re[((uint8_t*)&s)[3]];
+ c_im3 = byte2m64_im[((uint8_t*)&s)[3]];
+
+ for (int aa=0;aa<Prx;aa++) {
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("prb %d: rd ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb,
+ r_re_ext[aa][re_offset],r_im_ext[aa][re_offset],
+ r_re_ext[aa][re_offset+1],r_im_ext[aa][re_offset+1],
+ r_re_ext[aa][re_offset+2],r_im_ext[aa][re_offset+2],
+ r_re_ext[aa][re_offset+3],r_im_ext[aa][re_offset+3],
+ r_re_ext[aa][re_offset+4],r_im_ext[aa][re_offset+4],
+ r_re_ext[aa][re_offset+5],r_im_ext[aa][re_offset+5],
+ r_re_ext[aa][re_offset+6],r_im_ext[aa][re_offset+6],
+ r_re_ext[aa][re_offset+7],r_im_ext[aa][re_offset+7]);
+ printf("prb %d (%x): c ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb,s,
+ ((int16_t*)&c_re0)[0],((int16_t*)&c_im0)[0],
+ ((int16_t*)&c_re0)[1],((int16_t*)&c_im0)[1],
+ ((int16_t*)&c_re0)[2],((int16_t*)&c_im0)[2],
+ ((int16_t*)&c_re0)[3],((int16_t*)&c_im0)[3],
+ ((int16_t*)&c_re1)[0],((int16_t*)&c_im1)[0],
+ ((int16_t*)&c_re1)[1],((int16_t*)&c_im1)[1],
+ ((int16_t*)&c_re1)[2],((int16_t*)&c_im1)[2],
+ ((int16_t*)&c_re1)[3],((int16_t*)&c_im1)[3]
+ );
+ printf("prb %d: rd ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb+1,
+ r_re_ext[aa][re_offset+8],r_im_ext[aa][re_offset+8],
+ r_re_ext[aa][re_offset+9],r_im_ext[aa][re_offset+9],
+ r_re_ext[aa][re_offset+10],r_im_ext[aa][re_offset+10],
+ r_re_ext[aa][re_offset+11],r_im_ext[aa][re_offset+11],
+ r_re_ext[aa][re_offset+12],r_im_ext[aa][re_offset+12],
+ r_re_ext[aa][re_offset+13],r_im_ext[aa][re_offset+13],
+ r_re_ext[aa][re_offset+14],r_im_ext[aa][re_offset+14],
+ r_re_ext[aa][re_offset+15],r_im_ext[aa][re_offset+15]);
+ printf("prb %d (%x): c ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb+1,s,
+ ((int16_t*)&c_re2)[0],((int16_t*)&c_im2)[0],
+ ((int16_t*)&c_re2)[1],((int16_t*)&c_im2)[1],
+ ((int16_t*)&c_re2)[2],((int16_t*)&c_im2)[2],
+ ((int16_t*)&c_re2)[3],((int16_t*)&c_im2)[3],
+ ((int16_t*)&c_re3)[0],((int16_t*)&c_im3)[0],
+ ((int16_t*)&c_re3)[1],((int16_t*)&c_im3)[1],
+ ((int16_t*)&c_re3)[2],((int16_t*)&c_im3)[2],
+ ((int16_t*)&c_re3)[3],((int16_t*)&c_im3)[3]
+ );
+#endif
+
+ ((__m64*)&r_re_ext2[aa][re_offset])[0] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[0],c_im0);
+ ((__m64*)&r_re_ext[aa][re_offset])[0] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[0],c_re0);
+ ((__m64*)&r_im_ext2[aa][re_offset])[0] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[0],c_re0);
+ ((__m64*)&r_im_ext[aa][re_offset])[0] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[0],c_im0);
+
+ ((__m64*)&r_re_ext2[aa][re_offset])[1] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[1],c_im1);
+ ((__m64*)&r_re_ext[aa][re_offset])[1] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[1],c_re1);
+ ((__m64*)&r_im_ext2[aa][re_offset])[1] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[1],c_re1);
+ ((__m64*)&r_im_ext[aa][re_offset])[1] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[1],c_im1);
+
+ ((__m64*)&r_re_ext2[aa][re_offset])[2] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[2],c_im2);
+ ((__m64*)&r_re_ext[aa][re_offset])[2] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[2],c_re2);
+ ((__m64*)&r_im_ext2[aa][re_offset])[2] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[2],c_re2);
+ ((__m64*)&r_im_ext[aa][re_offset])[2] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[2],c_im2);
+
+ ((__m64*)&r_re_ext2[aa][re_offset])[3] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[3],c_im3);
+ ((__m64*)&r_re_ext[aa][re_offset])[3] = _mm_mullo_pi16(((__m64*)&r_re_ext[aa][re_offset])[3],c_re3);
+ ((__m64*)&r_im_ext2[aa][re_offset])[3] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[3],c_re3);
+ ((__m64*)&r_im_ext[aa][re_offset])[3] = _mm_mullo_pi16(((__m64*)&r_im_ext[aa][re_offset])[3],c_im3);
+
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("prb %d: r ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb,
+ r_re_ext[aa][re_offset],r_im_ext[aa][re_offset],
+ r_re_ext[aa][re_offset+1],r_im_ext[aa][re_offset+1],
+ r_re_ext[aa][re_offset+2],r_im_ext[aa][re_offset+2],
+ r_re_ext[aa][re_offset+3],r_im_ext[aa][re_offset+3],
+ r_re_ext[aa][re_offset+4],r_im_ext[aa][re_offset+4],
+ r_re_ext[aa][re_offset+5],r_im_ext[aa][re_offset+5],
+ r_re_ext[aa][re_offset+6],r_im_ext[aa][re_offset+6],
+ r_re_ext[aa][re_offset+7],r_im_ext[aa][re_offset+7]);
+ printf("prb %d: r ((%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d),(%d,%d))\n",
+ prb+1,
+ r_re_ext[aa][re_offset+8],r_im_ext[aa][re_offset+8],
+ r_re_ext[aa][re_offset+9],r_im_ext[aa][re_offset+9],
+ r_re_ext[aa][re_offset+10],r_im_ext[aa][re_offset+10],
+ r_re_ext[aa][re_offset+11],r_im_ext[aa][re_offset+11],
+ r_re_ext[aa][re_offset+12],r_im_ext[aa][re_offset+12],
+ r_re_ext[aa][re_offset+13],r_im_ext[aa][re_offset+13],
+ r_re_ext[aa][re_offset+14],r_im_ext[aa][re_offset+14],
+ r_re_ext[aa][re_offset+15],r_im_ext[aa][re_offset+15]);
+#endif
+ }
+ s = lte_gold_generic(&x1, &x2, 0);
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("\n");
+#endif
+ }
+ int nb_bit = pucch_pdu->bit_len_harq+pucch_pdu->sr_flag+pucch_pdu->bit_len_csi_part1+pucch_pdu->bit_len_csi_part2;
+ AssertFatal(nb_bit > 2 && nb_bit< 65,"illegal length (%d : %d,%d,%d,%d)\n",nb_bit,pucch_pdu->bit_len_harq,pucch_pdu->sr_flag,pucch_pdu->bit_len_csi_part1,pucch_pdu->bit_len_csi_part2);
+
+ uint64_t decodedPayload[2];
+ uint8_t corr_dB;
+ int decoderState=2;
+ if (nb_bit < 12) { // short blocklength case
+ __m256i *rp_re[Prx2];
+ __m256i *rp2_re[Prx2];
+ __m256i *rp_im[Prx2];
+ __m256i *rp2_im[Prx2];
+ for (int aa=0;aa<Prx;aa++) {
+ rp_re[aa] = (__m256i*)r_re_ext[aa];
+ rp_im[aa] = (__m256i*)r_im_ext[aa];
+ rp2_re[aa] = (__m256i*)r_re_ext2[aa];
+ rp2_im[aa] = (__m256i*)r_im_ext2[aa];
+ }
+ __m256i prod_re[Prx2],prod_im[Prx2];
+ int64_t corr=0;
+ int cw_ML=0;
+
+
+ for (int cw=0;cw<1<<nb_bit;cw++) {
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("cw %d:",cw);
+ for (int i=0;i<32;i+=2) {
+ printf("%d,%d,",
+ ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[i>>1],
+ ((int16_t*)&pucch2_lut[nb_bit-3][cw<<1])[1+(i>>1)]);
+ }
+ printf("\n");
+#endif
+ // do complex correlation
+ for (int aa=0;aa<Prx;aa++) {
+ prod_re[aa] = _mm256_srai_epi16(_mm256_adds_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp_re[aa][0]),
+ _mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp_im[aa][0])),5);
+ prod_im[aa] = _mm256_srai_epi16(_mm256_subs_epi16(_mm256_mullo_epi16(pucch2_lut[nb_bit-3][cw<<1],rp2_im[aa][0]),
+ _mm256_mullo_epi16(pucch2_lut[nb_bit-3][(cw<<1)+1],rp2_re[aa][0])),5);
+#ifdef DEBUG_NR_PUCCH_RX
+ printf("prod_re[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa,
+ ((int16_t*)&prod_re[aa])[0],((int16_t*)&prod_re[aa])[1],((int16_t*)&prod_re[aa])[2],((int16_t*)&prod_re[aa])[3],
+ ((int16_t*)&prod_re[aa])[4],((int16_t*)&prod_re[aa])[5],((int16_t*)&prod_re[aa])[6],((int16_t*)&prod_re[aa])[7],
+ ((int16_t*)&prod_re[aa])[8],((int16_t*)&prod_re[aa])[9],((int16_t*)&prod_re[aa])[10],((int16_t*)&prod_re[aa])[11],
+ ((int16_t*)&prod_re[aa])[12],((int16_t*)&prod_re[aa])[13],((int16_t*)&prod_re[aa])[14],((int16_t*)&prod_re[aa])[15]);
+ printf("prod_im[%d] => (%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d)",aa,
+ ((int16_t*)&prod_im[aa])[0],((int16_t*)&prod_im[aa])[1],((int16_t*)&prod_im[aa])[2],((int16_t*)&prod_im[aa])[3],
+ ((int16_t*)&prod_im[aa])[4],((int16_t*)&prod_im[aa])[5],((int16_t*)&prod_im[aa])[6],((int16_t*)&prod_im[aa])[7],
+ ((int16_t*)&prod_im[aa])[8],((int16_t*)&prod_im[aa])[9],((int16_t*)&prod_im[aa])[10],((int16_t*)&prod_im[aa])[11],
+ ((int16_t*)&prod_im[aa])[12],((int16_t*)&prod_im[aa])[13],((int16_t*)&prod_im[aa])[14],((int16_t*)&prod_im[aa])[15]);
+
+#endif
+ prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1
+ prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]);
+ prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3
+ prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]);
+ prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3+4+5+6+7
+ prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]);
+ prod_re[aa] = _mm256_hadds_epi16(prod_re[aa],prod_re[aa]);// 0+1+2+3+4+5+6+7+8+9+10+11+12+13+14+15
+ prod_im[aa] = _mm256_hadds_epi16(prod_im[aa],prod_im[aa]);
+ }
+ int64_t corr_re=0,corr_im=0;
+
+ int64_t corr_tmp = 0;
+ for (int aa=0;aa<Prx;aa++) {
+ LOG_D(PHY,"pucch2 cw %d aa %d: (%d,%d)+(%d,%d) = (%d,%d)\n",cw,aa,
+ corr32_re[0][aa],corr32_im[0][aa],
+ ((int16_t*)(&prod_re[aa]))[0],
+ ((int16_t*)(&prod_im[aa]))[0],
+ corr32_re[0][aa]+((int16_t*)(&prod_re[0]))[0],
+ corr32_im[0][aa]+((int16_t*)(&prod_im[0]))[0]);
+
+ corr_re = ( corr32_re[0][aa]+((int16_t*)(&prod_re[0]))[0]);
+ corr_im = ( corr32_im[0][aa]+((int16_t*)(&prod_im[0]))[0]);
+
+ corr_tmp += corr_re*corr_re + corr_im*corr_im;
+ }
+
+ if (corr_tmp > corr) {
+ corr = corr_tmp;
+ cw_ML=cw;
+ }
+ }
+ corr_dB = dB_fixed64((uint64_t)corr);
+ LOG_D(PHY,"cw_ML %d, metric %d dB\n",cw_ML,corr_dB);
+ decodedPayload[0]=(uint64_t)cw_ML;
+ }
+ else { // polar coded case
+
+ t_nrPolar_params *currentPtr = nr_polar_params(2,nb_bit,pucch_pdu->prb_size,1,&gNB->uci_polarParams);
+ __m64 *rp_re[Prx2];
+ __m64 *rp2_re[Prx2];
+ __m64 *rp_im[Prx2];
+ __m64 *rp2_im[Prx2];
+ __m128i llrs[pucch_pdu->prb_size*2];
+
+ for (int aa=0;aa<Prx;aa++) {
+ rp_re[aa] = (__m64*)r_re_ext[aa];
+ rp_im[aa] = (__m64*)r_im_ext[aa];
+ rp2_re[aa] = (__m64*)r_re_ext2[aa];
+ rp2_im[aa] = (__m64*)r_im_ext2[aa];
+ }
+ __m64 prod_re[Prx2],prod_im[Prx2];
+
+#ifdef DEBUG_NR_PUCCH_RX
+ for (int cw=0;cw<16;cw++) {
+
+ printf("cw %d:",cw);
+ for (int i=0;i<4;i++) {
+ printf("%d,",
+ ((int16_t*)&pucch2_polar_4bit[cw])[i>>1]);
+ }
+ printf("\n");
+ }
+#endif
+
+ // non-coherent LLR computation on groups of 4 REs (half-PRBs)
+ int32_t corr_re,corr_im,corr_tmp;
+ __m128i corr16,llr_num,llr_den;
+ uint64_t corr = 0;
+
+ for (int half_prb=0;half_prb<(2*pucch_pdu->prb_size);half_prb++) {
+ llr_num=_mm_set1_epi16(0);llr_den=_mm_set1_epi16(0);
+ for (int cw=0;cw<256;cw++) {
+ corr_tmp=0;
+ for (int aa=0;aa<Prx;aa++) {
+ prod_re[aa] = _mm_srai_pi16(_mm_adds_pi16(_mm_mullo_pi16(pucch2_polar_4bit[cw&15],rp_re[aa][half_prb]),
+ _mm_mullo_pi16(pucch2_polar_4bit[cw>>4],rp_im[aa][half_prb])),5);
+ prod_im[aa] = _mm_srai_pi16(_mm_subs_pi16(_mm_mullo_pi16(pucch2_polar_4bit[cw&15],rp2_im[aa][half_prb]),
+ _mm_mullo_pi16(pucch2_polar_4bit[cw>>4],rp2_re[aa][half_prb])),5);
+ prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1
+ prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]);
+ prod_re[aa] = _mm_hadds_pi16(prod_re[aa],prod_re[aa]);// 0+1+2+3
+ prod_im[aa] = _mm_hadds_pi16(prod_im[aa],prod_im[aa]);
+
+ // this is for UL CQI measurement
+ if (cw==0) corr += ((int64_t)corr32_re[half_prb>>2][aa]*corr32_re[half_prb>>2][aa])+
+ ((int64_t)corr32_im[half_prb>>2][aa]*corr32_im[half_prb>>2][aa]);
+
+
+ corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]);
+ corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]);
+ corr_tmp += corr_re*corr_re + corr_im*corr_im;
+ /*
+ LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n",
+ half_prb,cw,cw&15,cw>>4,aa,
+ ((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0],
+ ((int16_t*)&pucch2_polar_4bit[cw&15])[1],((int16_t*)&pucch2_polar_4bit[cw>>4])[1],
+ ((int16_t*)&pucch2_polar_4bit[cw&15])[2],((int16_t*)&pucch2_polar_4bit[cw>>4])[2],
+ ((int16_t*)&pucch2_polar_4bit[cw&15])[3],((int16_t*)&pucch2_polar_4bit[cw>>4])[3],
+ ((int16_t*)&rp_re[aa][half_prb])[0],((int16_t*)&rp_im[aa][half_prb])[0],
+ ((int16_t*)&rp_re[aa][half_prb])[1],((int16_t*)&rp_im[aa][half_prb])[1],
+ ((int16_t*)&rp_re[aa][half_prb])[2],((int16_t*)&rp_im[aa][half_prb])[2],
+ ((int16_t*)&rp_re[aa][half_prb])[3],((int16_t*)&rp_im[aa][half_prb])[3],
+ corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2),corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2),
+ ((int16_t*)(&prod_re[aa]))[0],
+ ((int16_t*)(&prod_im[aa]))[0],
+ corr_re,
+ corr_im,
+ corr_tmp);
+ */
+ }
+ corr16 = _mm_set1_epi16((int16_t)(corr_tmp>>8));
+ /*
+ LOG_D(PHY,"half_prb %d cw %d corr16 %d\n",half_prb,cw,corr_tmp>>8);
+ */
+ llr_num = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_num_lut[cw]),llr_num);
+ llr_den = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_den_lut[cw]),llr_den);
+ /*
+ LOG_D(PHY,"lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[0],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[1],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[2],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[3],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[4],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[5],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[6],
+ ((int16_t*)&pucch2_polar_llr_num_lut[cw])[7]);
+
+ LOG_D(PHY,"llr_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",
+ ((int16_t*)&llr_num)[0],
+ ((int16_t*)&llr_num)[1],
+ ((int16_t*)&llr_num)[2],
+ ((int16_t*)&llr_num)[3],
+ ((int16_t*)&llr_num)[4],
+ ((int16_t*)&llr_num)[5],
+ ((int16_t*)&llr_num)[6],
+ ((int16_t*)&llr_num)[7]);
+ LOG_D(PHY,"llr_den (%d,%d,%d,%d,%d,%d,%d,%d)\n",
+ ((int16_t*)&llr_den)[0],
+ ((int16_t*)&llr_den)[1],
+ ((int16_t*)&llr_den)[2],
+ ((int16_t*)&llr_den)[3],
+ ((int16_t*)&llr_den)[4],
+ ((int16_t*)&llr_den)[5],
+ ((int16_t*)&llr_den)[6],
+ ((int16_t*)&llr_den)[7]);
+ */
+ }
+ // compute llrs
+ llrs[half_prb] = _mm_subs_epi16(llr_num,llr_den);
+ LOG_D(PHY,"llrs[%d] : (%d,%d,%d,%d,%d,%d,%d,%d)\n",
+ half_prb,
+ ((int16_t*)&llrs[half_prb])[0],
+ ((int16_t*)&llrs[half_prb])[1],
+ ((int16_t*)&llrs[half_prb])[2],
+ ((int16_t*)&llrs[half_prb])[3],
+ ((int16_t*)&llrs[half_prb])[4],
+ ((int16_t*)&llrs[half_prb])[5],
+ ((int16_t*)&llrs[half_prb])[6],
+ ((int16_t*)&llrs[half_prb])[7]);
+ } // half_prb
+ // run polar decoder on llrs
+ decoderState = polar_decoder_int16((int16_t*)llrs, decodedPayload, 0, currentPtr);
+ LOG_D(PHY,"UCI decoderState %d, payload[0] %llux\n",decoderState,(unsigned long long)decodedPayload[0]);
+ if (decoderState>0) decoderState=1;
+ corr_dB = dB_fixed64(corr);
+ LOG_D(PHY,"metric %d dB\n",corr_dB);
+ }
+ uci_pdu->harq.harq_bit_len = pucch_pdu->bit_len_harq;
+ uci_pdu->pduBitmap=0;
+ uci_pdu->rnti=pucch_pdu->rnti;
+ uci_pdu->handle=pucch_pdu->handle;
+ uci_pdu->pucch_format=0;
+ uci_pdu->ul_cqi=corr_dB;
+ // need to fill these field!
+ uci_pdu->timing_advance=31;
+ uci_pdu->rssi=0;
+ if (pucch_pdu->bit_len_harq>0) {
+ int harq_bytes=pucch_pdu->bit_len_harq>>3;
+ if ((pucch_pdu->bit_len_harq&7) > 0) harq_bytes++;
+ uci_pdu->pduBitmap|=1;
+ uci_pdu->harq.harq_payload = (uint8_t*)malloc(harq_bytes);
+ uci_pdu->harq.harq_crc = decoderState > 0 ? 1 : 0;
+ int i=0;
+ for (;i<harq_bytes-1;i++) {
+ uci_pdu->harq.harq_payload[i] = decodedPayload[0] & 255;
+ decodedPayload[0]>>=8;
+ }
+ uci_pdu->harq.harq_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_harq&7))-1);
+ decodedPayload[0] >>= pucch_pdu->bit_len_harq;
+ }
+
+ if (pucch_pdu->sr_flag == 1) {
+ uci_pdu->pduBitmap|=2;
+ uci_pdu->sr.sr_bit_len = 1;
+ uci_pdu->sr.sr_payload = malloc(1);
+ uci_pdu->sr.sr_payload[0] = decodedPayload[0]&1;
+ decodedPayload[0] = decodedPayload[0]>>1;
+ }
+ // csi
+ if (pucch_pdu->bit_len_csi_part1>0) {
+ uci_pdu->pduBitmap|=4;
+ int csi_part1_bytes=pucch_pdu->bit_len_csi_part1>>3;
+ if ((pucch_pdu->bit_len_csi_part1&7) > 0) csi_part1_bytes++;
+ uci_pdu->csi_part1.csi_part1_payload = (uint8_t*)malloc(csi_part1_bytes);
+ uci_pdu->csi_part1.csi_part1_crc = decoderState > 0 ? 1 : 0;
+ int i=0;
+ for (;i<csi_part1_bytes-1;i++) {
+ uci_pdu->csi_part1.csi_part1_payload[i] = decodedPayload[0] & 255;
+ decodedPayload[0]>>=8;
+ }
+ uci_pdu->csi_part1.csi_part1_payload[i] = decodedPayload[0] & ((1<<(pucch_pdu->bit_len_csi_part1&7))-1);
+ decodedPayload[0] >>= pucch_pdu->bit_len_csi_part1;
+ }
+
+ if (pucch_pdu->bit_len_csi_part2>0) {
+ uci_pdu->pduBitmap|=8;
+ }
+
+}
+
diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c
index 7f5872e8858fa69c873c220757415c4bb6597c01..b49443c03c8652e251f4d654ecddc04dbc0a05f1 100644
--- a/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c
+++ b/openair1/PHY/NR_UE_ESTIMATION/nr_adjust_synch_ue.c
@@ -34,8 +34,9 @@
void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms,
PHY_VARS_NR_UE *ue,
- module_id_t eNB_id,
- uint8_t subframe,
+ module_id_t gNB_id,
+ uint8_t frame,
+ uint8_t subframe,
unsigned char clear,
short coef)
{
@@ -59,8 +60,8 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms,
temp = 0;
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
- Re = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[(i<<1)];
- Im = ((int16_t*)ue->pbch_vars[eNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)];
+ Re = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[(i<<1)];
+ Im = ((int16_t*)ue->pbch_vars[gNB_id]->dl_ch_estimates_time[aa])[1+(i<<1)];
temp += (Re*Re/2) + (Im*Im/2);
}
@@ -104,17 +105,19 @@ void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms,
//mac_resynch();
//dl_phy_sync_success(ue->Mod_id,ue->proc.proc_rxtx[0].frame_rx,0,1);//ue->common_vars.eNb_id);
ue->UE_mode[0] = PRACH;
+ ue->prach_resources[gNB_id]->sync_frame = frame;
+ ue->prach_resources[gNB_id]->init_msg1 = 0;
}
else {
ue->UE_mode[0] = PUSCH;
}
}
- if ( ue->rx_offset < 0 )
- ue->rx_offset += frame_parms->samples_per_frame;
+ if (ue->rx_offset < 0)
+ ue->rx_offset += frame_parms->samples_per_frame;
- if ( ue->rx_offset >= frame_parms->samples_per_frame )
- ue->rx_offset -= frame_parms->samples_per_frame;
+ if (ue->rx_offset >= frame_parms->samples_per_frame)
+ ue->rx_offset -= frame_parms->samples_per_frame;
diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
index 19564bd8d08394d52cb417cb31ae3dee2fff2fde..71a5771f5be55947ee1eec2b38d6d1ac00a39135 100644
--- a/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
+++ b/openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
@@ -618,7 +618,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PDCCH
- printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
+ printf("pilot %u : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
#endif
multadd_real_vector_complex_scalar(fr,
diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h
index af06f9a98f3d69eea929221af3aac45852b4575b..18376643912e8fc4229bd9bc47f98562cf8f35e6 100644
--- a/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h
+++ b/openair1/PHY/NR_UE_ESTIMATION/nr_estimation.h
@@ -75,6 +75,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
void nr_adjust_synch_ue(NR_DL_FRAME_PARMS *frame_parms,
PHY_VARS_NR_UE *ue,
module_id_t eNB_id,
+ uint8_t frame,
uint8_t subframe,
unsigned char clear,
short coef);
@@ -90,6 +91,7 @@ void phy_adjust_gain_nr(PHY_VARS_NR_UE *ue,
uint32_t rx_power_fil_dB,
uint8_t eNB_id);
-int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index);
+int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index);
+
#endif
diff --git a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c
index aa1e2b5ade0f15bf74bd9770dfd98b1172b69cd0..860ca11d8cbccd2fd9a5851708c459f9daa1c296 100644
--- a/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c
+++ b/openair1/PHY/NR_UE_ESTIMATION/nr_ue_measurements.c
@@ -55,8 +55,9 @@ void print_ints(char *s,int *x)
}
#endif
-int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index)
-{
+int16_t get_nr_PL(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index){
+
+ PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id];
/*
if (ue->frame_parms.mode1_flag == 1)
@@ -75,9 +76,6 @@ int16_t get_nr_PL(PHY_VARS_NR_UE *ue,uint8_t gNB_index)
//(ue->frame_parms.pdsch_config_common.referenceSignalPower*10))/10));
}
-
-
-
void nr_ue_measurements(PHY_VARS_NR_UE *ue,
unsigned int subframe_offset,
unsigned char N0_symbol,
diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
index ef22b61260b6ff5358e1b165714e05146c302588..7cde6e31c16b1f8edaad9b13691b7ad84b562efa 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
@@ -29,11 +29,15 @@
* \note
* \warning
*/
+
#ifdef USER_MODE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif
+
+#include "executables/softmodem-common.h"
+
#include "nr_transport_proto_ue.h"
#include "PHY/CODING/nrPolar_tools/nr_polar_dci_defs.h"
#include "PHY/phy_extern_nr_ue.h"
@@ -799,20 +803,22 @@ void pdcch_scrambling(NR_DL_FRAME_PARMS *frame_parms,
#ifdef NR_PDCCH_DCI_RUN
-void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
- int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id) {
+void nr_pdcch_unscrambling(int16_t *z,
+ uint16_t scrambling_RNTI,
+ uint32_t length,
+ uint16_t pdcch_DMRS_scrambling_id,
+ int16_t *z2) {
int i;
uint8_t reset;
uint32_t x1, x2, s = 0;
uint16_t n_id; //{0,1,...,65535}
- uint32_t n_rnti;
+ uint32_t rnti = (uint32_t) scrambling_RNTI;
reset = 1;
// x1 is set in first call to lte_gold_generic
- //do_common=1;
- n_id = pdcch_DMRS_scrambling_id;
- n_rnti = (uint32_t)crnti;
+ n_id = pdcch_DMRS_scrambling_id;
+ x2 = ((rnti<<16) + n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3
- x2 = (((1<<16)*n_rnti)+n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3
+ LOG_D(PHY,"PDCCH Unscrambling x2 %x : scrambling_RNTI %x\n", x2, rnti);
for (i = 0; i < length; i++) {
if ((i & 0x1f) == 0) {
@@ -840,38 +846,48 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
rel15 = &pdcch_vars->pdcch_config[i];
int dci_length = rel15->dci_length;
+ //int gNB_id = 0;
int16_t tmp_e[16*108];
+ rnti_t n_rnti;
for (int j=0;j<rel15->number_of_candidates;j++) {
- LOG_D(PHY,"Trying DCI candidate %d, CCE %d (%d), L %d\n",j,rel15->CCE[j],rel15->CCE[j]*9*6*2,rel15->L[j]);
int CCEind = rel15->CCE[j];
int L = rel15->L[j];
uint64_t dci_estimation[2]= {0};
- const t_nrPolar_params *currentPtrDCI=nr_polar_params(1, dci_length, L,1,&ue->polarList);
+ const t_nrPolar_params *currentPtrDCI = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, dci_length, L, 1, &ue->polarList);
- nr_pdcch_unscrambling(rel15->rnti,
- &ue->frame_parms,
- slot,
- &pdcch_vars->e_rx[CCEind*108],
- tmp_e,
- L*108,
- // get_nCCE(n_pdcch_symbols, frame_parms, mi) * 72,
- rel15->coreset.pdcch_dmrs_scrambling_id);
+ LOG_D(PHY, "Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d\n", j, rel15->number_of_candidates, CCEind, CCEind*9*6*2, L);
+
+ nr_pdcch_unscrambling(&pdcch_vars->e_rx[CCEind*108], rel15->coreset.scrambling_rnti, L*108, rel15->coreset.pdcch_dmrs_scrambling_id, tmp_e);
+
+ #ifdef DEBUG_DCI_DECODING
+ uint32_t * z = (uint32_t *) &pdcch_vars->e_rx[CCEind*108];
+ for (int index_z = 0; index_z < 96; index_z++){
+ for (int i=0; i<9; i++) {
+ LOG_D(PHY,"z[%d]=(%d,%d) \n", (9*index_z + i), *(int16_t *) &z[index_z + i],*(1 + (int16_t *) &z[index_z + i]));
+ }
+ }
+ #endif
uint16_t crc = polar_decoder_int16(tmp_e,
dci_estimation,
1,
currentPtrDCI);
- LOG_D(PHY,"Decoded crc %x\n",crc);
- if (crc == rel15->rnti) {
+
+ n_rnti = rel15->rnti;
+
+ if (crc == n_rnti) {
+ LOG_D(PHY,"Decoded crc %x matches rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format);
dci_ind->SFN = frame;
dci_ind->slot = slot;
- dci_ind->dci_list[dci_ind->number_of_dcis].rnti = rel15->rnti;
+ dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti;
dci_ind->dci_list[dci_ind->number_of_dcis].n_CCE = CCEind;
dci_ind->dci_list[dci_ind->number_of_dcis].dci_format = rel15->dci_format;
dci_ind->dci_list[dci_ind->number_of_dcis].payloadSize = dci_length;
memcpy((void*)dci_ind->dci_list[dci_ind->number_of_dcis].payloadBits,(void*)dci_estimation,8);
dci_ind->number_of_dcis++;
+ } else {
+ LOG_D(PHY,"Decoded crc %x does not match rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format);
}
}
}
diff --git a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h
index 95b6cfd2e2f4945eddfcf8705622fd73aa1740da..5f1321dd321bfda863e20b1e0a38ddc1c82d59f3 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/dci_nr.h
@@ -29,6 +29,10 @@
* \note
* \warning
*/
+
+#ifndef __PHY_NR_UE_TRANSPORT_DCI_NR__H__
+#define __PHY_NR_UE_TRANSPORT_DCI_NR__H__
+
#ifndef USER_MODE
#include "PHY/types.h"
#else
@@ -118,4 +122,5 @@ typedef struct NR_DCI_INFO_EXTRACTED NR_DCI_INFO_EXTRACTED_t;
#endif
+#endif
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
index 00167507ce5bc53b553fb63369974456787e857a..3a2cb3f4361c257252168c4fafbda56f91cbe6ee 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
@@ -32,6 +32,7 @@
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "PHY/defs_nr_UE.h"
+#include "SCHED_NR_UE/harq_nr.h"
#include "PHY/phy_extern_nr_ue.h"
#include "PHY/CODING/coding_extern.h"
#include "PHY/CODING/coding_defs.h"
@@ -42,6 +43,7 @@
#include "SIMULATION/TOOLS/sim.h"
#include "executables/nr-uesoftmodem.h"
#include "PHY/CODING/nrLDPC_extern.h"
+#include "LAYER2/NR_MAC_gNB/mac_proto.h"
//#define DEBUG_DLSCH_DECODING
//#define ENABLE_PHY_PAYLOAD_DEBUG 1
@@ -69,12 +71,11 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr,uint8_t N_RB_DL)
a_segments = a_segments/273;
}
- uint16_t dlsch_bytes = a_segments*1056; // allocated bytes per segment
for (i=0; i<dlsch->Mdlharq; i++) {
if (dlsch->harq_processes[i]) {
if (dlsch->harq_processes[i]->b) {
- free16(dlsch->harq_processes[i]->b,dlsch_bytes);
+ free16(dlsch->harq_processes[i]->b,a_segments*1056);
dlsch->harq_processes[i]->b = NULL;
}
@@ -133,6 +134,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint
memset(dlsch,0,sizeof(NR_UE_DLSCH_t));
dlsch->Kmimo = Kmimo;
dlsch->Mdlharq = Mdlharq;
+ dlsch->number_harq_processes_for_pdsch = Mdlharq;
dlsch->Nsoft = Nsoft;
dlsch->Mlimit = 4;
dlsch->max_ldpc_iterations = max_ldpc_iterations;
@@ -143,6 +145,7 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint
if (dlsch->harq_processes[i]) {
memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t));
+ init_downlink_harq_status(dlsch->harq_processes[i]);
dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (uint8_t*)malloc16(dlsch_bytes);
@@ -215,16 +218,16 @@ void nr_dlsch_unscrambling(int16_t* llr,
}
uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
- short *dlsch_llr,
- NR_DL_FRAME_PARMS *frame_parms,
- NR_UE_DLSCH_t *dlsch,
- NR_DL_UE_HARQ_t *harq_process,
- uint32_t frame,
- uint16_t nb_symb_sch,
- uint8_t nr_tti_rx,
- uint8_t harq_pid,
- uint8_t is_crnti,
- uint8_t llr8_flag)
+ short *dlsch_llr,
+ NR_DL_FRAME_PARMS *frame_parms,
+ NR_UE_DLSCH_t *dlsch,
+ NR_DL_UE_HARQ_t *harq_process,
+ uint32_t frame,
+ uint16_t nb_symb_sch,
+ uint8_t nr_tti_rx,
+ uint8_t harq_pid,
+ uint8_t is_crnti,
+ uint8_t llr8_flag)
{
#if UE_TIMING_TRACE
@@ -263,8 +266,14 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
double Coderate;// = 0.0;
uint8_t dmrs_Type = harq_process->dmrsConfigType;
- AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type);
- uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4;
+ AssertFatal(dmrs_Type == 0 || dmrs_Type == 1, "Illegal dmrs_type %d\n", dmrs_Type);
+ uint8_t nb_re_dmrs;
+ if (dmrs_Type==NFAPI_NR_DMRS_TYPE1) {
+ nb_re_dmrs = 6*harq_process->n_dmrs_cdm_groups;
+ }
+ else {
+ nb_re_dmrs = 4*harq_process->n_dmrs_cdm_groups;
+ }
uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos);
AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length);
@@ -318,7 +327,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
- harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, harq_process->Nl);
+ harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, 0, harq_process->Nl);
A = harq_process->TBS;
ret = dlsch->max_ldpc_iterations + 1;
@@ -327,7 +336,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
- LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d nb_re_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, nb_re_dmrs,harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
+ LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d (%d) G %d nb_re_dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,A/8,G, nb_re_dmrs,harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
if ((harq_process->R)<1024)
Coderate = (float) (harq_process->R) /(float) 1024;
@@ -406,7 +415,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if (nb_rb != 273) {
a_segments = a_segments*nb_rb;
- a_segments = a_segments/273;
+ a_segments = (a_segments + 272) / 273;
}
if (harq_process->C > a_segments) {
@@ -802,8 +811,13 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
//nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config;
//uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value;
- uint8_t nb_re_dmrs = (dmrs_type==1)?6:4;
- uint16_t length_dmrs = get_num_dmrs(harq_process->dlDmrsSymbPos);
+ uint8_t nb_re_dmrs;
+ if (dmrs_Type == NFAPI_NR_DMRS_TYPE1)
+ nb_re_dmrs = 6*harq_process->n_dmrs_cdm_groups;
+ else
+ nb_re_dmrs = 4*harq_process->n_dmrs_cdm_groups;
+
+ uint16_t length_dmrs = get_num_dmrs(dl_config_pdu->dlDmrsSymbPos);
uint32_t i,j;
// int nbDlProcessing =0;
@@ -855,7 +869,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
- harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl);
+ harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl);
A = harq_process->TBS;
@@ -1432,7 +1446,7 @@ void nr_dlsch_decoding_process(void *arg)
uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
- harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, harq_process->Nl);
+ harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*length_dmrs, nb_rb_oh, 0, harq_process->Nl);
A = harq_process->TBS; //2072 for QPSK 1/3
@@ -1698,10 +1712,10 @@ void nr_dlsch_decoding_process(void *arg)
}
no_iteration_ldpc = nrLDPC_decoder(p_decParams,
- (int8_t*)&pl[0],
- llrProcBuf,
- p_nrLDPC_procBuf,
- p_procTime);
+ (int8_t*)&pl[0],
+ llrProcBuf,
+ p_nrLDPC_procBuf,
+ p_procTime);
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
index c704efdb1fd09b929874b4421e462c3a7be6b86f..ab3cf4ae90f7cdfe12b75baf484167e3460e27ee 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
@@ -30,6 +30,7 @@
*/
#include "PHY/defs_nr_UE.h"
#include "PHY/phy_extern_nr_ue.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "nr_transport_proto_ue.h"
//#include "SCHED/defs.h"
//#include "PHY/defs.h"
@@ -131,9 +132,9 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
unsigned short nb_rb = 0, round;
int avgs = 0;// rb;
- NR_DL_UE_HARQ_t *dlsch0_harq,*dlsch1_harq = 0;
+ NR_DL_UE_HARQ_t *dlsch0_harq, *dlsch1_harq = NULL;
- uint8_t beamforming_mode;
+ uint8_t beamforming_mode = 0;
int32_t **rxdataF_comp_ptr;
int32_t **dl_ch_mag_ptr;
@@ -155,82 +156,104 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
uint16_t n_tx=1, n_rx=1;
int32_t median[16];
uint32_t len;
-
+
switch (type) {
case SI_PDSCH:
- pdsch_vars = &ue->pdsch_vars_SI[eNB_id];
+ pdsch_vars = ue->pdsch_vars_SI;
dlsch = &ue->dlsch_SI[eNB_id];
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
- beamforming_mode = 0;
+
break;
case RA_PDSCH:
- pdsch_vars = &ue->pdsch_vars_ra[eNB_id];
+ pdsch_vars = ue->pdsch_vars_ra;
dlsch = &ue->dlsch_ra[eNB_id];
dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
- beamforming_mode = 0;
+
+ // WIP TBR Hotfix
+ memcpy((void*)&pdsch_vars[eNB_id]->dl_ch_estimates[0][ue->frame_parms.ofdm_symbol_size*2], (void*)&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][0]->dl_ch_estimates[0][ue->frame_parms.ofdm_symbol_size*2], ue->frame_parms.ofdm_symbol_size*sizeof(int32_t));
+
break;
case PDSCH:
pdsch_vars = ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]];
dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id];
+ dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
+ dlsch1_harq = dlsch[1]->harq_processes[harq_pid];
+ beamforming_mode = ue->transmission_mode[eNB_id] < 7 ? 0 :ue->transmission_mode[eNB_id];
+ break;
+ default:
+ LOG_E(PHY, "[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n", nr_tti_rx, type);
+ return -1;
+ break;
+ }
- dlsch[0]->harq_processes[harq_pid]->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
- dlsch[0]->harq_processes[harq_pid]->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
-
- //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status);
- LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n",
- frame,nr_tti_rx,symbol,harq_pid,
- dlsch[0]->harq_processes[harq_pid]->status,
- dlsch[1]->harq_processes[harq_pid]->status);
-
- if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) &&
- (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE)){
- codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword;
- codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword;
+ if (dlsch1_harq){
+
+ //printf("status TB0 = %d, status TB1 = %d \n", dlsch[0]->harq_processes[harq_pid]->status, dlsch[1]->harq_processes[harq_pid]->status);
+ LOG_D(PHY,"AbsSubframe %d.%d / Sym %d harq_pid %d, harq status %d.%d \n", frame, nr_tti_rx, symbol, harq_pid, dlsch0_harq->status, dlsch1_harq->status);
+
+ if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status == ACTIVE)){
+ codeword_TB0 = dlsch0_harq->codeword;
+ codeword_TB1 = dlsch1_harq->codeword;
dlsch0_harq = dlsch[codeword_TB0]->harq_processes[harq_pid];
dlsch1_harq = dlsch[codeword_TB1]->harq_processes[harq_pid];
-#ifdef DEBUG_HARQ
- printf("[DEMOD] I am assuming both TBs are active\n");
-#endif
- }
- else if ((dlsch[0]->harq_processes[harq_pid]->status == ACTIVE) &&
- (dlsch[1]->harq_processes[harq_pid]->status != ACTIVE) ) {
- codeword_TB0 = dlsch[0]->harq_processes[harq_pid]->codeword;
- dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
+
+ #ifdef DEBUG_HARQ
+ printf("[DEMOD] I am assuming both TBs are active, in cw0 %d and cw1 %d \n", codeword_TB0, codeword_TB1);
+ #endif
+
+ } else if ((dlsch0_harq->status == ACTIVE) && (dlsch1_harq->status != ACTIVE) ) {
+ codeword_TB0 = dlsch0_harq->codeword;
+ dlsch0_harq = dlsch[codeword_TB0]->harq_processes[harq_pid];
dlsch1_harq = NULL;
- codeword_TB1 = -1;
-#ifdef DEBUG_HARQ
- printf("[DEMOD] I am assuming only TB0 is active\n");
-#endif
- }
- else if ((dlsch[0]->harq_processes[harq_pid]->status != ACTIVE) &&
- (dlsch[1]->harq_processes[harq_pid]->status == ACTIVE) ){
- codeword_TB1 = dlsch[1]->harq_processes[harq_pid]->codeword;
- dlsch0_harq = dlsch[1]->harq_processes[harq_pid];
- dlsch1_harq = NULL;
- codeword_TB0 = -1;
-#ifdef DEBUG_HARQ
- printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", dlsch0_harq->codeword);
-#endif
- }
- else {
- LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n",nr_tti_rx);
+
+ #ifdef DEBUG_HARQ
+ printf("[DEMOD] I am assuming only TB0 is active, in cw %d \n", codeword_TB0);
+ #endif
+
+ } else if ((dlsch0_harq->status != ACTIVE) && (dlsch1_harq->status == ACTIVE)){
+ codeword_TB1 = dlsch1_harq->codeword;
+ dlsch0_harq = NULL;
+ dlsch1_harq = dlsch[codeword_TB1]->harq_processes[harq_pid];
+
+ #ifdef DEBUG_HARQ
+ printf("[DEMOD] I am assuming only TB1 is active, it is in cw %d\n", codeword_TB1);
+ #endif
+
+ LOG_E(PHY, "[UE][FATAL] DLSCH: TB0 not active and TB1 active case is not supported\n");
+ return -1;
+
+ } else {
+ LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx);
return(-1);
}
- beamforming_mode = ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id];
- break;
+ } else if (dlsch0_harq) {
+ if (dlsch0_harq->status == ACTIVE)
+ codeword_TB0 = dlsch0_harq->codeword;
+ dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
- default:
- LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: Unknown PDSCH format %d\n",nr_tti_rx,type);
- return(-1);
- break;
+ #ifdef DEBUG_HARQ
+ printf("[DEMOD] I am assuming only TB0 is active\n");
+ #endif
+ } else {
+ LOG_E(PHY,"[UE][FATAL] nr_tti_rx %d: no active DLSCH\n", nr_tti_rx);
+ return (-1);
}
-#ifdef DEBUG_HARQ
- printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode);
- printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1);
-#endif
+
+ if (dlsch0_harq == NULL) {
+ LOG_E(PHY, "Done\n");
+ return -1;
+ }
+
+ dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
+ dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
+
+ #ifdef DEBUG_HARQ
+ printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode);
+ printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1);
+ #endif
start_rb = dlsch0_harq->start_rb;
nb_rb_pdsch = dlsch0_harq->nb_rb;
@@ -269,7 +292,6 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
return(-1);
}
-
if (dlsch0_harq->mimo_mode==NR_DUALSTREAM) {
DevAssert(dlsch1_harq);
}
@@ -363,7 +385,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
nr_tti_rx,
ue->high_speed_flag,
frame_parms);
-
+
} /*else if(beamforming_mode>7) {
LOG_W(PHY,"dlsch_demodulation: beamforming mode not supported yet.\n");
}*/
@@ -624,7 +646,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
write_output("rho2_mrc.m","rho2_0",&pdsch_vars[eNB_id]->dl_ch_rho2_ext[0][symbol*frame_parms->N_RB_DL*12],frame_parms->N_RB_DL*12,1,1);//should be almost 0
} */
}
- }
+ }
//printf("start compute LLR\n");
if (dlsch0_harq->mimo_mode == NR_DUALSTREAM) {
@@ -655,19 +677,19 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
// -> // compute @pointer where llrs should filled for this ofdm-symbol
if (first_symbol_flag==1) pdsch_vars[eNB_id]->llr_offset[symbol-1] = 0;
- llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1];
- //pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0];
- //pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1];
- pllr_symbol_layer0 = pdsch_vars[eNB_id]->layer_llr[0];
- pllr_symbol_layer1 = pdsch_vars[eNB_id]->layer_llr[1];
- pllr_symbol_layer0 += llr_offset_symbol;
- pllr_symbol_layer1 += llr_offset_symbol;
- pllr_symbol_cw0 = pdsch_vars[eNB_id]->llr[0];
- pllr_symbol_cw1 = pdsch_vars[eNB_id]->llr[1];
- pllr_symbol_cw0 += llr_offset_symbol;
- pllr_symbol_cw1 += llr_offset_symbol;
-
- pdsch_vars[eNB_id]->llr_offset[symbol] = len*dlsch0_harq->Qm + llr_offset_symbol;
+ llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1];
+ //pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0];
+ //pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1];
+ pllr_symbol_layer0 = pdsch_vars[eNB_id]->layer_llr[0];
+ pllr_symbol_layer1 = pdsch_vars[eNB_id]->layer_llr[1];
+ pllr_symbol_layer0 += llr_offset_symbol;
+ pllr_symbol_layer1 += llr_offset_symbol;
+ pllr_symbol_cw0 = pdsch_vars[eNB_id]->llr[0];
+ pllr_symbol_cw1 = pdsch_vars[eNB_id]->llr[1];
+ pllr_symbol_cw0 += llr_offset_symbol;
+ pllr_symbol_cw1 += llr_offset_symbol;
+
+ pdsch_vars[eNB_id]->llr_offset[symbol] = len*dlsch0_harq->Qm + llr_offset_symbol;
/*LOG_I(PHY,"compute LLRs [symbol %d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %x @LLR Buff(symb) %x\n",
symbol,
@@ -689,13 +711,13 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
case 2 :
if ((rx_type==rx_standard) || (codeword_TB1 == -1)) {
nr_dlsch_qpsk_llr(frame_parms,
- pdsch_vars[eNB_id]->rxdataF_comp0,
- pllr_symbol_cw0,
- symbol,
- len,
- first_symbol_flag,
- nb_rb,
- beamforming_mode);
+ pdsch_vars[eNB_id]->rxdataF_comp0,
+ pllr_symbol_cw0,
+ symbol,
+ len,
+ first_symbol_flag,
+ nb_rb,
+ beamforming_mode);
} else if (codeword_TB0 == -1){
@@ -964,46 +986,47 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
return(-1);
break;
}
+
if (dlsch1_harq) {
- switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) {
- case 2 :
- if (rx_type==rx_standard) {
- nr_dlsch_qpsk_llr(frame_parms,
- pdsch_vars[eNB_id]->rxdataF_comp0,
- pllr_symbol_cw0,
- symbol,len,first_symbol_flag,nb_rb,
- beamforming_mode);
- }
- break;
- case 4:
- if (rx_type==rx_standard) {
- nr_dlsch_16qam_llr(frame_parms,
- pdsch_vars[eNB_id]->rxdataF_comp0,
- pdsch_vars[eNB_id]->llr[0],
- pdsch_vars[eNB_id]->dl_ch_mag0,
- symbol,len,first_symbol_flag,nb_rb,
- pdsch_vars[eNB_id]->llr128,
- beamforming_mode);
+ switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) {
+ case 2 :
+ if (rx_type==rx_standard) {
+ nr_dlsch_qpsk_llr(frame_parms,
+ pdsch_vars[eNB_id]->rxdataF_comp0,
+ pllr_symbol_cw0,
+ symbol,len,first_symbol_flag,nb_rb,
+ beamforming_mode);
+ }
+ break;
+ case 4:
+ if (rx_type==rx_standard) {
+ nr_dlsch_16qam_llr(frame_parms,
+ pdsch_vars[eNB_id]->rxdataF_comp0,
+ pdsch_vars[eNB_id]->llr[0],
+ pdsch_vars[eNB_id]->dl_ch_mag0,
+ symbol,len,first_symbol_flag,nb_rb,
+ pdsch_vars[eNB_id]->llr128,
+ beamforming_mode);
+ }
+ break;
+ case 6 :
+ if (rx_type==rx_standard) {
+ nr_dlsch_64qam_llr(frame_parms,
+ pdsch_vars[eNB_id]->rxdataF_comp0,
+ pllr_symbol_cw0,
+ pdsch_vars[eNB_id]->dl_ch_mag0,
+ pdsch_vars[eNB_id]->dl_ch_magb0,
+ symbol,len,first_symbol_flag,nb_rb,
+ pdsch_vars[eNB_id]->llr_offset[symbol],
+ beamforming_mode);
+ }
+ break;
+ default:
+ LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n");
+ return(-1);
+ break;
}
- break;
- case 6 :
- if (rx_type==rx_standard) {
- nr_dlsch_64qam_llr(frame_parms,
- pdsch_vars[eNB_id]->rxdataF_comp0,
- pllr_symbol_cw0,
- pdsch_vars[eNB_id]->dl_ch_mag0,
- pdsch_vars[eNB_id]->dl_ch_magb0,
- symbol,len,first_symbol_flag,nb_rb,
- pdsch_vars[eNB_id]->llr_offset[symbol],
- beamforming_mode);
- }
- break;
- default:
- LOG_W(PHY,"rx_dlsch.c : Unknown mod_order!!!!\n");
- return(-1);
- break;
- }
- }
+ }
//nr_dlsch_deinterleaving(symbol,bundle_L,(int16_t*)pllr_symbol_cw0,(int16_t*)pllr_symbol_cw0_deint, nb_rb_pdsch);
@@ -2368,7 +2391,7 @@ unsigned short nr_dlsch_extract_rbs_single(int **rxdataF,
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
- k = frame_parms->first_carrier_offset + 12*start_rb;
+ k = frame_parms->first_carrier_offset + NR_NB_SC_PER_RB*start_rb;
if (high_speed_flag == 1)
dl_ch0 = &dl_ch_estimates[aarx][(2*(frame_parms->ofdm_symbol_size))];
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c
index 61748a8e562c2f63e3d3850d23e5297b634cd0f1..5c480d6646e3b695e54374f889f5ca80af850ec5 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_initial_sync.c
@@ -38,6 +38,7 @@
#include "PHY/NR_UE_ESTIMATION/nr_estimation.h"
//#include "SCHED/defs.h"
//#include "SCHED/extern.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
#include "common_lib.h"
#include <math.h>
@@ -135,7 +136,7 @@ int nr_pbch_detection(UE_nr_rxtx_proc_t * proc, PHY_VARS_NR_UE *ue, int pbch_ini
stop_meas(&ue->dlsch_channel_estimation_stats);
#endif
- current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im+current_ssb->c_re;
+ current_ssb->metric = current_ssb->c_re*current_ssb->c_re + current_ssb->c_im*current_ssb->c_im;
// generate a list of SSB structures
if (best_ssb == NULL)
@@ -213,6 +214,9 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode,
NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
int ret=-1;
int rx_power=0; //aarx,
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_IN);
+
LOG_D(PHY,"nr_initial sync ue RB_DL %d\n", fp->N_RB_DL);
@@ -477,6 +481,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc, PHY_VARS_NR_UE *ue, runmode_t mode,
}
// exit_fun("debug exit");
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_OUT);
return ret;
}
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
index 60306d8e53b32b046cfcdceee16041a505cba7b3..612dc6283dbe97c5f5071f023b41af76af8285cf 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
@@ -505,7 +505,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
return(-1);
}
*/
- if (symbol==1) {
+ if (symbol==2) {
nr_pbch_quantize(pbch_e_rx,
(short *)&(nr_ue_pbch_vars->rxdataF_comp[0][symbol*240]),
144);
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
index adef4a759277c8371e089239310394e79ad8640d..e4cab0b9a660245ba882d11079ae88763223e059 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
@@ -19,13 +19,13 @@
* contact@openairinterface.org
*/
-/*! \file PHY/LTE_TRANSPORT/prach_common.c
- * \brief Common routines for UE/eNB PRACH physical channel V8.6 2009-03
- * \author R. Knopp
- * \date 2011
- * \version 0.1
- * \company Eurecom
- * \email: knopp@eurecom.fr
+/*! \file PHY/NR_TRANSPORT/nr_prach.c
+ * \brief Routines for UE PRACH physical channel
+ * \author R. Knopp, G. Casati
+ * \date 2019
+ * \version 0.2
+ * \company Eurecom, Fraunhofer IIS
+ * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de
* \note
* \warning
*/
@@ -35,100 +35,90 @@
#include "PHY/impl_defs_nr.h"
#include "PHY/defs_nr_UE.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "T.h"
+//#define NR_PRACH_DEBUG 1
-
-
-extern uint16_t NCS_unrestricted_delta_f_RA_125[16];
-extern uint16_t NCS_restricted_TypeA_delta_f_RA_125[15];
-extern uint16_t NCS_restricted_TypeB_delta_f_RA_125[13];
-extern uint16_t NCS_unrestricted_delta_f_RA_5[16];
-extern uint16_t NCS_restricted_TypeA_delta_f_RA_5[16];
-extern uint16_t NCS_restricted_TypeB_delta_f_RA_5[14];
-extern uint16_t NCS_unrestricted_delta_f_RA_15[16];
extern uint16_t prach_root_sequence_map_0_3[838];
extern uint16_t prach_root_sequence_map_abc[138];
-extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9];
-extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9];
-extern int64_t table_6_3_3_2_4_prachConfig_Index [256][10];
extern uint16_t nr_du[838];
extern int16_t nr_ru[2*839];
+extern const char *prachfmt[9];
+extern const char *prachfmt03[4];
+
+// Note:
+// - prach_fmt_id is an ID used to map to the corresponding PRACH format value in prachfmt
+// WIP todo:
+// - take prach start symbol into account
+// - idft for short sequence assumes we are transmitting starting in symbol 0 of a PRACH slot
+// - Assumes that PRACH SCS is same as PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below
+// - Preamble index different from 0 is not detected by gNB
+int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t slot){
-
-
-
-
-
-
-
-int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf )
-{
-
- //lte_frame_type_t frame_type = ue->frame_parms.frame_type;
- //uint8_t tdd_config = ue->frame_parms.tdd_config;
NR_DL_FRAME_PARMS *fp=&ue->frame_parms;
- uint16_t rootSequenceIndex = fp->prach_config_common.rootSequenceIndex;
- uint8_t prach_ConfigIndex = fp->prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
- uint8_t Ncs_config = fp->prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig;
- uint8_t restricted_set = fp->prach_config_common.prach_ConfigInfo.highSpeedFlag;
- uint8_t preamble_index = ue->prach_resources[eNB_id]->ra_PreambleIndex;
- //uint8_t tdd_mapindex = ue->prach_resources[eNB_id]->ra_TDD_map_index;
- int16_t *prachF = ue->prach_vars[eNB_id]->prachF;
- int16_t prach_tmp[98304*2*4] __attribute__((aligned(32)));
- int16_t *prach = prach_tmp;
- int16_t *prach2;
- int16_t amp = ue->prach_vars[eNB_id]->amp;
- int16_t Ncp;
- uint16_t NCS=0;
- uint16_t *prach_root_sequence_map;
- uint16_t preamble_offset,preamble_shift;
- uint16_t preamble_index0,n_shift_ra,n_shift_ra_bar;
- uint16_t d_start=-1,numshift;
-
- uint16_t prach_fmt = get_nr_prach_fmt(prach_ConfigIndex,fp->frame_type,fp->freq_range);
- //uint8_t Nsp=2;
- //uint8_t f_ra,t1_ra;
- uint16_t N_ZC = (prach_fmt<4)?839:139;
- uint8_t not_found;
- int16_t *Xu;
- uint16_t u;
- int32_t Xu_re,Xu_im;
- uint16_t offset,offset2;
- int prach_start;
- int i, prach_len=0;
- uint16_t first_nonzero_root_idx=0;
-
-#if defined(OAI_USRP)
- prach_start = (ue->rx_offset+subframe*fp->samples_per_subframe-ue->hw_timing_advance-ue->N_TA_offset);
-#ifdef NR_PRACH_DEBUG
- LOG_I(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id,
- prach_start,
- ue->rx_offset,
- ue->hw_timing_advance,
- ue->N_TA_offset);
-#endif
-
- if (prach_start<0)
- prach_start+=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME);
+ fapi_nr_config_request_t *nrUE_config = &ue->nrUE_config;
+ NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_id];
+ fapi_nr_ul_config_prach_pdu *prach_pdu = &ue->prach_vars[gNB_id]->prach_pdu;
- if (prach_start>=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME))
- prach_start-=(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME);
+ uint8_t Mod_id, fd_occasion, preamble_index, restricted_set, not_found;
+ uint16_t rootSequenceIndex, prach_fmt_id, NCS, *prach_root_sequence_map, preamble_offset = 0;
+ uint16_t preamble_shift = 0, preamble_index0, n_shift_ra, n_shift_ra_bar, d_start, numshift, N_ZC, u, offset, offset2, first_nonzero_root_idx;
+ int16_t prach_tmp[98304*2*4] __attribute__((aligned(32)));
-#else //normal case (simulation)
- prach_start = subframe*fp->samples_per_subframe-ue->N_TA_offset;
- LOG_D(PHY,"[UE %d] prach_start %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", ue->Mod_id,
- prach_start,
- ue->rx_offset,
- ue->hw_timing_advance,
- ue->N_TA_offset);
+ int16_t Ncp = 0, amp, *prach, *prach2, *prachF, *Xu;
+ int32_t Xu_re, Xu_im, samp_count;
+ int prach_start, prach_sequence_length, i, prach_len, dftlen, mu, kbar, K, n_ra_prb, k;
+ //int restricted_Type;
+
+ prach = prach_tmp;
+ prachF = ue->prach_vars[gNB_id]->prachF;
+ amp = ue->prach_vars[gNB_id]->amp;
+ Mod_id = ue->Mod_id;
+ prach_sequence_length = nrUE_config->prach_config.prach_sequence_length;
+ N_ZC = (prach_sequence_length == 0) ? 839:139;
+ mu = nrUE_config->prach_config.prach_sub_c_spacing;
+ restricted_set = prach_pdu->restricted_set;
+ rootSequenceIndex = prach_pdu->root_seq_id;
+ n_ra_prb = prach_pdu->freq_msg1;
+ NCS = prach_pdu->num_cs;
+ prach_fmt_id = prach_pdu->prach_format;
+ preamble_index = prach_resources->ra_PreambleIndex;
+ fd_occasion = 0;
+ prach_len = 0;
+ dftlen = 0;
+ first_nonzero_root_idx = 0;
+ kbar = 1;
+ K = 24;
+ k = 12*n_ra_prb - 6*fp->N_RB_UL;
+ //prachStartSymbol = prach_config_pdu->prach_start_symbol
+ //restricted_Type = 0;
+
+ compute_nr_prach_seq(nrUE_config->prach_config.prach_sequence_length,
+ nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].num_root_sequences,
+ nrUE_config->prach_config.num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index,
+ ue->X_u);
+
+ if (mu == 0)
+ samp_count = fp->samples_per_subframe;
+ else
+ samp_count = (slot%(fp->slots_per_subframe/2)) ? fp->samples_per_slotN0 : fp->samples_per_slot0;
+
+ #ifdef OAI_USRP
+ prach_start = (ue->rx_offset + slot*samp_count - ue->hw_timing_advance - ue->N_TA_offset);
+ #else //normal case (simulation)
+ prach_start = slot*samp_count - ue->N_TA_offset;
+ #endif
-#endif
+ if (prach_start<0)
+ prach_start += (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME);
+ if (prach_start >= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME))
+ prach_start -= (fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME);
// First compute physical root sequence
/************************************************************************
@@ -138,41 +128,19 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
* NOTE: Restricted set type B is not implemented
*************************************************************************/
- int restricted_Type = 0; //this is hardcoded ('0' for restricted_TypeA; and '1' for restricted_TypeB). FIXME
- if (prach_fmt<3){
- if (restricted_set == 0) {
- NCS = NCS_unrestricted_delta_f_RA_125[Ncs_config];
- } else {
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_125[Ncs_config]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_125[Ncs_config]; // for TypeB, this is hardcoded. FIXME
- }
- }
- if (prach_fmt==3){
- if (restricted_set == 0) {
- NCS = NCS_unrestricted_delta_f_RA_5[Ncs_config];
- } else {
- if (restricted_Type == 0) NCS = NCS_restricted_TypeA_delta_f_RA_5[Ncs_config]; // for TypeA, this is hardcoded. FIXME
- if (restricted_Type == 1) NCS = NCS_restricted_TypeB_delta_f_RA_5[Ncs_config]; // for TypeB, this is hardcoded. FIXME
- }
- }
- if (prach_fmt>3){
- NCS = NCS_unrestricted_delta_f_RA_15[Ncs_config];
- }
-
- prach_root_sequence_map = (prach_fmt<4) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc;
-
- // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index
- preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS)));
+ prach_root_sequence_map = (prach_sequence_length == 0) ? prach_root_sequence_map_0_3 : prach_root_sequence_map_abc;
if (restricted_set == 0) {
+ // This is the relative offset (for unrestricted case) in the root sequence table (5.7.2-4 from 36.211) for the given preamble index
+ preamble_offset = ((NCS==0)? preamble_index : (preamble_index/(N_ZC/NCS)));
// This is the \nu corresponding to the preamble index
preamble_shift = (NCS==0)? 0 : (preamble_index % (N_ZC/NCS));
preamble_shift *= NCS;
} else { // This is the high-speed case
-#ifdef NR_PRACH_DEBUG
- LOG_I(PHY,"[UE %d] High-speed mode, NCS_config %d\n",ue->Mod_id,Ncs_config);
-#endif
+ #ifdef NR_PRACH_DEBUG
+ LOG_I(PHY, "PRACH [UE %d] High-speed mode, NCS %d\n", Mod_id, NCS);
+ #endif
not_found = 1;
preamble_index0 = preamble_index;
@@ -183,8 +151,9 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
while (not_found == 1) {
// current root depending on rootSequenceIndex and preamble_offset
int index = (rootSequenceIndex + preamble_offset) % N_ZC;
+ uint16_t n_group_ra = 0;
- if (prach_fmt<4) {
+ if (prach_fmt_id<4) {
// prach_root_sequence_map points to prach_root_sequence_map0_3
DevAssert( index < sizeof(prach_root_sequence_map_0_3) / sizeof(prach_root_sequence_map_0_3[0]) );
} else {
@@ -194,8 +163,6 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
u = prach_root_sequence_map[index];
- uint16_t n_group_ra = 0;
-
if ( (nr_du[u]<(N_ZC/3)) && (nr_du[u]>=NCS) ) {
n_shift_ra = nr_du[u]/NCS;
d_start = (nr_du[u]<<1) + (n_shift_ra * NCS);
@@ -229,43 +196,52 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
}
// now generate PRACH signal
-#ifdef NR_PRACH_DEBUG
-
- if (NCS>0)
- LOG_D(PHY,"Generate PRACH for RootSeqIndex %d, Preamble Index %d, PRACH Format %x, prach_ConfigIndex %d, NCS %d (NCS_config %d, N_ZC/NCS %d): Preamble_offset %d, Preamble_shift %d\n",
- rootSequenceIndex,preamble_index,prach_fmt,prach_ConfigIndex,NCS,Ncs_config,N_ZC/NCS,
- preamble_offset,preamble_shift);
-
-#endif
+ #ifdef NR_PRACH_DEBUG
+ if (NCS>0)
+ LOG_I(PHY, "PRACH [UE %d] generate PRACH in slot %d for RootSeqIndex %d, Preamble Index %d, PRACH Format %s, NCS %d (N_ZC %d): Preamble_offset %d, Preamble_shift %d msg1 frequency start %d\n",
+ Mod_id,
+ slot,
+ rootSequenceIndex,
+ preamble_index,
+ prach_sequence_length == 0 ? prachfmt03[prach_fmt_id] : prachfmt[prach_fmt_id],
+ NCS,
+ N_ZC,
+ preamble_offset,
+ preamble_shift,
+ n_ra_prb);
+ #endif
// nsymb = (frame_parms->Ncp==0) ? 14:12;
- // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*subframe*nsymb;
- int kbar = 1;
- int K = 24;
- if (prach_fmt == 3) {
- K=4;
- kbar=10;
- }
- else if (prach_fmt > 3) {
- // Note: Assumes that PRACH SCS is same as PUSCH SCS
- K=1;
- kbar=2;
+ // subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*slot*nsymb;
+
+ if (prach_sequence_length == 0 && prach_fmt_id == 3) {
+ K = 4;
+ kbar = 10;
+ } else if (prach_sequence_length == 1) {
+ K = 1;
+ kbar = 2;
}
- int n_ra_prb = fp->prach_config_common.prach_ConfigInfo.msg1_frequencystart;
- int k = (12*n_ra_prb) - 6*fp->N_RB_UL;
- k = (12*n_ra_prb) - 6*fp->N_RB_UL;
+ if (k<0)
+ k += fp->ofdm_symbol_size;
- if (k<0) k+=fp->ofdm_symbol_size;
+ k *= K;
+ k += kbar;
+ k *= 2;
- k*=K;
- k+=kbar;
-
- LOG_D(PHY,"placing prach in position %d\n",k);
- k*=2;
+ LOG_I(PHY, "PRACH [UE %d] in slot %d, placing PRACH in position %d, msg1 frequency start %d, preamble_offset %d, first_nonzero_root_idx %d\n", Mod_id,
+ slot,
+ k,
+ n_ra_prb,
+ preamble_offset,
+ first_nonzero_root_idx);
Xu = (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx];
+ #if defined (PRACH_WRITE_OUTPUT_DEBUG)
+ LOG_M("X_u.m", "X_u", (int16_t*)ue->X_u[preamble_offset-first_nonzero_root_idx], N_ZC, 1, 1);
+ #endif
+
/********************************************************
*
* In function init_prach_tables:
@@ -280,10 +256,86 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
*
*********************************************************/
- AssertFatal(prach_fmt>3,"prach_fmt<=3: Fix this for other formats\n");
- int dftlen=2048;
- if (fp->N_RB_UL >= 137) dftlen=4096;
- if (fp->threequarter_fs==1) dftlen=(3*dftlen)/4;
+ if (fp->N_RB_UL <= 100)
+ AssertFatal(1 == 0, "N_RB_UL %d not support for NR PRACH yet\n", fp->N_RB_UL);
+ else if (fp->N_RB_UL < 137) {
+ if (fp->threequarter_fs == 0) {
+ //40 MHz @ 61.44 Ms/s
+ //50 MHz @ 61.44 Ms/s
+ if (prach_sequence_length == 0) {
+ if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2)
+ dftlen = 49152;
+ if (prach_fmt_id == 3)
+ dftlen = 12288;
+ } // 839 sequence
+ else {
+ switch (mu){
+ case 1:
+ dftlen = 2048;
+ break;
+ default:
+ AssertFatal(1 == 0, "Shouldn't get here\n");
+ break;
+ }
+ }
+ } else { // threequarter sampling
+ // 40 MHz @ 46.08 Ms/s
+ if (prach_sequence_length == 0) {
+ AssertFatal(fp->N_RB_UL <= 107, "cannot do 108..136 PRBs with 3/4 sampling\n");
+ if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2)
+ dftlen = 36864;
+ if (prach_fmt_id == 3)
+ dftlen = 9216;
+ } else {
+ switch (mu){
+ case 1:
+ dftlen = 1536;
+ break;
+ default:
+ AssertFatal(1 == 0, "Shouldn't get here\n");
+ break;
+ }
+ } // short format
+ } // 3/4 sampling
+ } // <=50 MHz BW
+ else if (fp->N_RB_UL <= 273) {
+ if (fp->threequarter_fs == 0) {
+ //80,90,100 MHz @ 122.88 Ms/s
+ if (prach_sequence_length == 0) {
+ if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2)
+ dftlen = 98304;
+ if (prach_fmt_id == 3)
+ dftlen = 24576;
+ }
+ } else { // threequarter sampling
+ switch (mu){
+ case 1:
+ dftlen = 4096;
+ break;
+ default:
+ AssertFatal(1 == 0, "Shouldn't get here\n");
+ break;
+ }
+ }
+ } else {
+ AssertFatal(fp->N_RB_UL <= 217, "cannot do more than 217 PRBs with 3/4 sampling\n");
+ // 80 MHz @ 92.16 Ms/s
+ if (prach_sequence_length == 0) {
+ if (prach_fmt_id == 0 || prach_fmt_id == 1 || prach_fmt_id == 2)
+ dftlen = 73728;
+ if (prach_fmt_id == 3)
+ dftlen = 18432;
+ } else {
+ switch (mu){
+ case 1:
+ dftlen = 3072;
+ break;
+ default:
+ AssertFatal(1 == 0, "Shouldn't get here\n");
+ break;
+ }
+ }
+ }
for (offset=0,offset2=0; offset<N_ZC; offset++,offset2+=preamble_shift) {
@@ -294,536 +346,502 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
Xu_im = (((int32_t)Xu[1+(offset<<1)]*amp)>>15);
prachF[k++]= ((Xu_re*nr_ru[offset2<<1]) - (Xu_im*nr_ru[1+(offset2<<1)]))>>15;
prachF[k++]= ((Xu_im*nr_ru[offset2<<1]) + (Xu_re*nr_ru[1+(offset2<<1)]))>>15;
+
if (k==dftlen) k=0;
}
- switch (fp->N_RB_UL) {
- case 6:
- memset((void*)prachF,0,4*1536);
- break;
-
- case 15:
- memset((void*)prachF,0,4*3072);
- break;
-
- case 25:
- memset((void*)prachF,0,4*6144);
- break;
-
- case 50:
- memset((void*)prachF,0,4*12288);
- break;
-
- case 75:
- memset((void*)prachF,0,4*18432);
- break;
-
- case 100:
- if (fp->threequarter_fs == 0)
- memset((void*)prachF,0,4*24576);
- else
- memset((void*)prachF,0,4*18432);
- break;
-
- case 106:
- memset((void*)prachF,0,4*24576);
- break;
-}
-
- int mu = 1; // numerology is hardcoded. FIXME!!!
- switch (prach_fmt) {
- case 0:
- Ncp = 3168;
- break;
-
- case 1:
- Ncp = 2*21024;
- break;
-
- case 2:
- Ncp = 4688;
- break;
-
- case 3:
- Ncp = 3168;
- break;
-
- case 0xa1:
- Ncp = 288/(1<<mu);
- break;
-
- case 0xa2:
- Ncp = 576/(1<<mu);
- break;
-
- case 0xa3:
- Ncp = 864/(1<<mu);
- break;
-
- case 0xb1:
- Ncp = 216/(1<<mu);
- break;
-
- case 0xb2:
- Ncp = 360/(1<<mu);
- break;
-
- case 0xb3:
- Ncp = 504/(1<<mu);
- break;
-
- case 0xb4:
- Ncp = 936/(1<<mu);
- break;
-
- case 0xc0:
- Ncp = 1240/(1<<mu);
- break;
-
- case 0xc2:
- Ncp = 2048/(1<<mu);
- break;
+ #if defined (PRACH_WRITE_OUTPUT_DEBUG)
+ LOG_M("prachF.m", "prachF", &prachF[1804], 1024, 1, 1);
+ LOG_M("Xu.m", "Xu", Xu, N_ZC, 1, 1);
+ #endif
+
+ if (prach_sequence_length == 0) {
+
+ AssertFatal(prach_fmt_id < 4, "Illegal PRACH format %d for sequence length 839\n", prach_fmt_id);
+
+ switch (prach_fmt_id) {
+ case 0:
+ Ncp = 3168;
+ break;
+ case 1:
+ Ncp = 21024;
+ break;
+ case 2:
+ Ncp = 4688;
+ break;
+ case 3:
+ Ncp = 3168;
+ break;
+ }
- default:
- Ncp = 3168;
+ } else {
+
+ switch (prach_fmt_id) {
+ case 0: //A1
+ Ncp = 288/(1<<mu);
+ break;
+ case 1: //A2
+ Ncp = 576/(1<<mu);
+ break;
+ case 2: //A3
+ Ncp = 864/(1<<mu);
+ break;
+ case 3: //B1
+ Ncp = 216/(1<<mu);
break;
+ case 4: //B2
+ Ncp = 360/(1<<mu);
+ break;
+ case 5: //B3
+ Ncp = 504/(1<<mu);
+ break;
+ case 6: //B4
+ Ncp = 936/(1<<mu);
+ break;
+ case 7: //C0
+ Ncp = 1240/(1<<mu);
+ break;
+ case 8: //C2
+ Ncp = 2048/(1<<mu);
+ break;
+ default:
+ AssertFatal(1==0,"Unknown PRACH format ID %d\n", prach_fmt_id);
+ break;
+ }
}
+ #ifdef NR_PRACH_DEBUG
+ LOG_D(PHY, "PRACH [UE %d] Ncp %d, dftlen %d \n", Mod_id, Ncp, dftlen);
+ #endif
if (fp->N_RB_UL <= 100)
AssertFatal(1==0,"N_RB_UL %d not supported for NR PRACH yet\n",fp->N_RB_UL);
else if (fp->N_RB_UL < 137) { // 46.08 or 61.44 Ms/s
- if (fp->threequarter_fs==0) { //61.44 Ms/s
+ if (fp->threequarter_fs == 0) { // full sampling @ 61.44 Ms/s
Ncp<<=1;
// This is after cyclic prefix (Ncp<<1 samples for 30.72 Ms/s, Ncp<<2 samples for 61.44 Ms/s
prach2 = prach+(Ncp<<1);
- if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
- idft(IDFT_49152,prachF,prach2,1);
- // here we have |empty | Prach49152|
- memmove(prach,prach+(49152<<1),(Ncp<<3));
- // here we have |Prefix | Prach49152|
- prach_len = 49152+Ncp;
- dftlen=49152;
- }
- else if (prach_fmt == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
- idft(IDFT_49152,prachF,prach2,1);
- memmove(prach2+(49152<<1),prach2,(49152<<2));
- // here we have |empty | Prach49152 | Prach49152|
- memmove(prach,prach+(49152<<2),(Ncp<<3));
- // here we have |Prefix | Prach49152 | Prach49152|
- prach_len = (49152*2)+Ncp;
- dftlen=49152;
- }
- else if (prach_fmt == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
- idft(IDFT_49152,prachF,prach2,1);
- memmove(prach2+(49152<<1),prach2,(49152<<2));
- // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152
- memmove(prach2+(49152<<2),prach2,(49152<<3));
- // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152
- memmove(prach,prach+(49152<<3),(Ncp<<3));
- // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152
- prach_len = (49152*4)+Ncp;
- dftlen=49152;
- }
- else if (prach_fmt == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s
- idft(IDFT_12288,prachF,prach2,1);
- memmove(prach2+(12288<<1),prach2,(12288<<2));
- // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288
- memmove(prach2+(12288<<2),prach2,(12288<<3));
- // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288
- memmove(prach,prach+(12288<<3),(Ncp<<3));
- // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288
- prach_len = (12288*4)+Ncp;
- dftlen=12288;
- }
- else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) {
- prach2 = prach+(Ncp<<1);
- idft(IDFT_2048,prachF,prach2,1);
- dftlen=2048;
- // here we have |empty | Prach2048 |
- if (prach_fmt != 0xc0) {
- memmove(prach2+(2048<<1),prach2,(2048<<2));
- prach_len = (2048*2)+Ncp;
- }
- else prach_len = (2048*1)+Ncp;
- memmove(prach,prach+(2048<<1),(Ncp<<2));
- // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) |
- }
- else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x2048
- idft(IDFT_2048,prachF,prach2,1);
- dftlen=2048;
- // here we have |empty | Prach2048 |
- memmove(prach2+(2048<<1),prach2,(2048<<2));
- // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 |
- memmove(prach2+(2048<<2),prach2,(2048<<3));
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 |
- memmove(prach,prach+(2048<<1),(Ncp<<2));
- // here we have |Prefix | Prach2048 |
- prach_len = (2048*4)+Ncp;
- }
- else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x2048
- prach2 = prach+(Ncp<<1);
- idft(IDFT_2048,prachF,prach2,1);
- dftlen=2048;
- // here we have |empty | Prach2048 |
- memmove(prach2+(2048<<1),prach2,(2048<<2));
- // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048
- memmove(prach2+(2048<<2),prach2,(2048<<3));
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048
- memmove(prach2+((2048<<1)*3),prach2,(2048<<3));
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048
- memmove(prach,prach+(2048<<1),(Ncp<<2));
- // here we have |Prefix | Prach2048 |
- prach_len = (2048*6)+Ncp;
- }
- else if (prach_fmt == 0xb4) { // 12x2048
- idft(IDFT_2048,prachF,prach2,1);
- dftlen=2048;
- // here we have |empty | Prach2048 |
- memmove(prach2+(2048<<1),prach2,(2048<<2));
- // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048
- memmove(prach2+(2048<<2),prach2,(2048<<3));
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048
- memmove(prach2+(2048<<3),prach2,(2048<<3));
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048
- memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6);
- // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048|
- memmove(prach,prach+(2048<<1),(Ncp<<2));
- // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048|
- prach_len = (2048*12)+Ncp;
- }
-
- }
- else { // 46.08 Ms/s
+ if (prach_sequence_length == 0){
+ if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
+ idft(IDFT_49152,prachF,prach2,1);
+ // here we have |empty | Prach49152|
+ memmove(prach,prach+(49152<<1),(Ncp<<2));
+ // here we have |Prefix | Prach49152|
+ prach_len = 49152+Ncp;
+ } else if (prach_fmt_id == 1) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
+ idft(IDFT_49152,prachF,prach2,1);
+ memmove(prach2+(49152<<1),prach2,(49152<<2));
+ // here we have |empty | Prach49152 | Prach49152|
+ memmove(prach,prach+(49152<<2),(Ncp<<2));
+ // here we have |Prefix | Prach49152 | Prach49152|
+ prach_len = (49152*2)+Ncp;
+ } else if (prach_fmt_id == 2) { //24576 samples @ 30.72 Ms/s, 49152 samples @ 61.44 Ms/s
+ idft(IDFT_49152,prachF,prach2,1);
+ memmove(prach2+(49152<<1),prach2,(49152<<2));
+ // here we have |empty | Prach49152 | Prach49152| empty49152 | empty49152
+ memmove(prach2+(49152<<2),prach2,(49152<<3));
+ // here we have |empty | Prach49152 | Prach49152| Prach49152 | Prach49152
+ memmove(prach,prach+(49152<<3),(Ncp<<2));
+ // here we have |Prefix | Prach49152 | Prach49152| Prach49152 | Prach49152
+ prach_len = (49152*4)+Ncp;
+ } else if (prach_fmt_id == 3) { // //6144 samples @ 30.72 Ms/s, 12288 samples @ 61.44 Ms/s
+ idft(IDFT_12288,prachF,prach2,1);
+ memmove(prach2+(12288<<1),prach2,(12288<<2));
+ // here we have |empty | Prach12288 | Prach12288| empty12288 | empty12288
+ memmove(prach2+(12288<<2),prach2,(12288<<3));
+ // here we have |empty | Prach12288 | Prach12288| Prach12288 | Prach12288
+ memmove(prach,prach+(12288<<3),(Ncp<<2));
+ // here we have |Prefix | Prach12288 | Prach12288| Prach12288 | Prach12288
+ prach_len = (12288*4)+Ncp;
+ }
+ } else { // short PRACH sequence
+ if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) {
+ Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_2048,prachF,prach2,1);
+ // here we have |empty | Prach2048 |
+ if (prach_fmt_id != 7) {
+ memmove(prach2+(2048<<1),prach2,(2048<<2));
+ prach_len = (2048*2)+Ncp;
+ }
+ else prach_len = (2048*1)+Ncp;
+ memmove(prach,prach+(2048<<1),(Ncp<<2));
+ // here we have |Prefix | Prach2048 | Prach2048 (if ! 0xc0) |
+ } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x2048
+ Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_2048,prachF,prach2,1);
+ // here we have |empty | Prach2048 |
+ memmove(prach2+(2048<<1),prach2,(2048<<2));
+ // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 |
+ memmove(prach2+(2048<<2),prach2,(2048<<3));
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 |
+ memmove(prach,prach+(2048<<1),(Ncp<<2));
+ // here we have |Prefix | Prach2048 |
+ prach_len = (2048*4)+Ncp;
+ } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x2048
+ Ncp+=32;
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_2048,prachF,prach2,1);
+ // here we have |empty | Prach2048 |
+ memmove(prach2+(2048<<1),prach2,(2048<<2));
+ // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048
+ memmove(prach2+(2048<<2),prach2,(2048<<3));
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048
+ memmove(prach2+(2048<<3),prach2,(2048<<3));
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048
+ memmove(prach,prach+(2048<<1),(Ncp<<2));
+ // here we have |Prefix | Prach2048 |
+ prach_len = (2048*6)+Ncp;
+ } else if (prach_fmt_id == 6) { // 12x2048
+ Ncp+=32; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_2048,prachF,prach2,1);
+ // here we have |empty | Prach2048 |
+ memmove(prach2+(2048<<1),prach2,(2048<<2));
+ // here we have |empty | Prach2048 | Prach2048| empty2048 | empty2048 | empty2048 | empty2048
+ memmove(prach2+(2048<<2),prach2,(2048<<3));
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | empty2048 | empty2048
+ memmove(prach2+(2048<<3),prach2,(2048<<3));
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048
+ memmove(prach2+(2048<<1)*6,prach2,(2048<<2)*6);
+ // here we have |empty | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048|
+ memmove(prach,prach+(2048<<1),(Ncp<<2));
+ // here we have |Prefix | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048 | Prach2048| Prach2048 | Prach2048 | Prach2048 | Prach2048|
+ prach_len = (2048*12)+Ncp;
+ }
+ }
+ } else { // threequarter sampling @ 46.08 Ms/s
Ncp = (Ncp*3)/2;
prach2 = prach+(Ncp<<1);
- if (prach_fmt == 0) {
- idft(IDFT_36864,prachF,prach2,1);
- dftlen=36864;
- // here we have |empty | Prach73728|
- memmove(prach,prach+(36864<<1),(Ncp<<2));
- // here we have |Prefix | Prach73728|
- prach_len = (36864*1)+Ncp;
- }
- else if (prach_fmt == 1) {
- idft(IDFT_36864,prachF,prach2,1);
- dftlen=36864;
- memmove(prach2+(36864<<1),prach2,(36864<<2));
- // here we have |empty | Prach73728 | Prach73728|
- memmove(prach,prach+(36864<<2),(Ncp<<2));
- // here we have |Prefix | Prach73728 | Prach73728|
- prach_len = (36864*2)+Ncp;
- }
- if (prach_fmt == 2) {
- idft(IDFT_36864,prachF,prach2,1);
- dftlen=36864;
- memmove(prach2+(36864<<1),prach2,(36864<<2));
- // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728
- memmove(prach2+(36864<<2),prach2,(36864<<3));
- // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728
- memmove(prach,prach+(36864<<3),(Ncp<<2));
- // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728
- prach_len = (36864*4)+Ncp;
- }
- else if (prach_fmt == 3) {
- idft(IDFT_9216,prachF,prach2,1);
- dftlen=36864;
- memmove(prach2+(9216<<1),prach2,(9216<<2));
- // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216
- memmove(prach2+(9216<<2),prach2,(9216<<3));
- // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216
- memmove(prach,prach+(9216<<3),(Ncp<<2));
- // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216
- prach_len = (9216*4)+Ncp;
- }
- else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) {
- idft(IDFT_1536,prachF,prach2,1);
- dftlen=1536;
- // here we have |empty | Prach1536 |
- if (prach_fmt != 0xc0)
- memmove(prach2+(1536<<1),prach2,(1536<<2));
- memmove(prach,prach+(1536<<1),(Ncp<<2));
- // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) |
- prach_len = (1536*2)+Ncp;
+ if (prach_sequence_length == 0){
+ if (prach_fmt_id == 0) {
+ idft(IDFT_36864,prachF,prach2,1);
+ // here we have |empty | Prach73728|
+ memmove(prach,prach+(36864<<1),(Ncp<<2));
+ // here we have |Prefix | Prach73728|
+ prach_len = (36864*1)+Ncp;
+ } else if (prach_fmt_id == 1) {
+ idft(IDFT_36864,prachF,prach2,1);
+ memmove(prach2+(36864<<1),prach2,(36864<<2));
+ // here we have |empty | Prach73728 | Prach73728|
+ memmove(prach,prach+(36864<<2),(Ncp<<2));
+ // here we have |Prefix | Prach73728 | Prach73728|
+ prach_len = (36864*2)+Ncp;
+ } else if (prach_fmt_id == 2) {
+ idft(IDFT_36864,prachF,prach2,1);
+ memmove(prach2+(36864<<1),prach2,(36864<<2));
+ // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728
+ memmove(prach2+(36864<<2),prach2,(36864<<3));
+ // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728
+ memmove(prach,prach+(36864<<3),(Ncp<<2));
+ // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728
+ prach_len = (36864*4)+Ncp;
+ } else if (prach_fmt_id == 3) {
+ idft(IDFT_9216,prachF,prach2,1);
+ memmove(prach2+(9216<<1),prach2,(9216<<2));
+ // here we have |empty | Prach9216 | Prach9216| empty9216 | empty9216
+ memmove(prach2+(9216<<2),prach2,(9216<<3));
+ // here we have |empty | Prach9216 | Prach9216| Prach9216 | Prach9216
+ memmove(prach,prach+(9216<<3),(Ncp<<2));
+ // here we have |Prefix | Prach9216 | Prach9216| Prach9216 | Prach9216
+ prach_len = (9216*4)+Ncp;
+ }
+ } else { // short sequence
+ if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) {
+ Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_1536,prachF,prach2,1);
+ // here we have |empty | Prach1536 |
+ if (prach_fmt_id != 7) {
+ memmove(prach2+(1536<<1),prach2,(1536<<2));
+ prach_len = (1536*2)+Ncp;
+ } else prach_len = (1536*1)+Ncp;
+
+ memmove(prach,prach+(1536<<1),(Ncp<<2));
+ // here we have |Prefix | Prach1536 | Prach1536 (if ! 0xc0) |
+
+ } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 6x1536
+
+ Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_1536,prachF,prach2,1);
+ // here we have |empty | Prach1536 |
+ memmove(prach2+(1536<<1),prach2,(1536<<2));
+ // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 |
+ memmove(prach2+(1536<<2),prach2,(1536<<3));
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 |
+ memmove(prach,prach+(1536<<1),(Ncp<<2));
+ // here we have |Prefix | Prach1536 |
+ prach_len = (1536*4)+Ncp;
+ } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x1536
+ Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_1536,prachF,prach2,1);
+ // here we have |empty | Prach1536 |
+ memmove(prach2+(1536<<1),prach2,(1536<<2));
+ // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536
+ memmove(prach2+(1536<<2),prach2,(1536<<3));
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536
+ memmove(prach2+(1536<<3),prach2,(1536<<3));
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536
+ memmove(prach,prach+(1536<<1),(Ncp<<2));
+ // here we have |Prefix | Prach1536 |
+ prach_len = (1536*6)+Ncp;
+ } else if (prach_fmt_id == 6) { // 12x1536
+ Ncp+=24; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_1536,prachF,prach2,1);
+ // here we have |empty | Prach1536 |
+ memmove(prach2+(1536<<1),prach2,(1536<<2));
+ // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536
+ memmove(prach2+(1536<<2),prach2,(1536<<3));
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536
+ memmove(prach2+(1536<<3),prach2,(1536<<3));
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536
+ memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6);
+ // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536|
+ memmove(prach,prach+(1536<<1),(Ncp<<2));
+ // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536|
+ prach_len = (1536*12)+Ncp;
+ }
}
- else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 6x1536
- idft(IDFT_1536,prachF,prach2,1);
- dftlen=1536;
- // here we have |empty | Prach1536 |
- memmove(prach2+(1536<<1),prach2,(1536<<2));
- // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 |
- memmove(prach2+(1536<<2),prach2,(1536<<3));
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 |
- memmove(prach,prach+(1536<<1),(Ncp<<2));
- // here we have |Prefix | Prach1536 |
- prach_len = (1536*4)+Ncp;
- }
- else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x1536
- idft(IDFT_1536,prachF,prach2,1);
- dftlen=1536;
- // here we have |empty | Prach1536 |
- memmove(prach2+(1536<<1),prach2,(1536<<2));
- // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536
- memmove(prach2+(1536<<2),prach2,(1536<<3));
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536
- memmove(prach2+((1536<<1)*3),prach2,(1536<<3));
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536
- memmove(prach,prach+(1536<<1),(Ncp<<2));
- // here we have |Prefix | Prach1536 |
- prach_len = (1536*6)+Ncp;
- }
- else if (prach_fmt == 0xb4) { // 12x1536
- idft(IDFT_1536,prachF,prach2,1);
- dftlen=1536;
- // here we have |empty | Prach1536 |
- memmove(prach2+(1536<<1),prach2,(1536<<2));
- // here we have |empty | Prach1536 | Prach1536| empty1536 | empty1536 | empty1536 | empty1536
- memmove(prach2+(1536<<2),prach2,(1536<<3));
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | empty1536 | empty1536
- memmove(prach2+(1536<<3),prach2,(1536<<3));
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536
- memmove(prach2+(1536<<1)*6,prach2,(1536<<2)*6);
- // here we have |empty | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536|
- memmove(prach,prach+(1536<<1),(Ncp<<2));
- // here we have |Prefix | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536 | Prach1536| Prach1536 | Prach1536 | Prach1536 | Prach1536|
- prach_len = (1536*12)+Ncp;
- }
}
- }
- else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s
- if (fp->threequarter_fs==0) { //122.88 Ms/s
+ } else if (fp->N_RB_UL <= 273) {// 92.16 or 122.88 Ms/s
+ if (fp->threequarter_fs == 0) { // full sampling @ 122.88 Ms/s
Ncp<<=2;
prach2 = prach+(Ncp<<1);
- if (prach_fmt == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s
- idft(IDFT_98304,prachF,prach2,1);
- dftlen=98304;
- // here we have |empty | Prach98304|
- memmove(prach,prach+(98304<<1),(Ncp<<2));
- // here we have |Prefix | Prach98304|
- prach_len = (98304*1)+Ncp;
- }
- else if (prach_fmt == 1) {
- idft(IDFT_98304,prachF,prach2,1);
- dftlen=98304;
- memmove(prach2+(98304<<1),prach2,(98304<<2));
- // here we have |empty | Prach98304 | Prach98304|
- memmove(prach,prach+(98304<<2),(Ncp<<2));
- // here we have |Prefix | Prach98304 | Prach98304|
- prach_len = (98304*2)+Ncp;
- }
- else if (prach_fmt == 2) {
- idft(IDFT_98304,prachF,prach2,1);
- dftlen=98304;
- memmove(prach2+(98304<<1),prach2,(98304<<2));
- // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304
- memmove(prach2+(98304<<2),prach2,(98304<<3));
- // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304
- memmove(prach,prach+(98304<<3),(Ncp<<2));
- // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304
- prach_len = (98304*4)+Ncp;
- }
- else if (prach_fmt == 3) { // 4x6144, Ncp 3168
- idft(IDFT_24576,prachF,prach2,1);
- dftlen=24576;
- memmove(prach2+(24576<<1),prach2,(24576<<2));
- // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576
- memmove(prach2+(24576<<2),prach2,(24576<<3));
- // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576
- memmove(prach,prach+(24576<<3),(Ncp<<2));
- // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576
- prach_len = (24576*4)+(Ncp<<1);
- }
- else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) {
- idft(IDFT_4096,prachF,prach2,1);
- dftlen=4096;
- // here we have |empty | Prach4096 |
- if (prach_fmt != 0xc0) {
- memmove(prach2+(4096<<1),prach2,(4096<<2));
- prach_len = (4096*2)+Ncp;
- }
- else prach_len = (4096*1)+Ncp;
- memmove(prach,prach+(4096<<1),(Ncp<<2));
- // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) |
-
- }
- else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x4096
- idft(IDFT_4096,prachF,prach2,1);
- dftlen=4096;
- // here we have |empty | Prach4096 |
- memmove(prach2+(4096<<1),prach2,(4096<<2));
- // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 |
- memmove(prach2+(4096<<2),prach2,(4096<<3));
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 |
- memmove(prach,prach+(4096<<1),(Ncp<<2));
- // here we have |Prefix | Prach4096 |
- prach_len = (4096*4)+Ncp;
- }
- else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x4096
- idft(IDFT_4096,prachF,prach2,1);
- dftlen=4096;
- // here we have |empty | Prach4096 |
- memmove(prach2+(4096<<1),prach2,(4096<<2));
- // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096
- memmove(prach2+(4096<<2),prach2,(4096<<3));
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096
- memmove(prach2+((4096<<1)*3),prach2,(4096<<3));
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096
- memmove(prach,prach+(4096<<1),(Ncp<<2));
- // here we have |Prefix | Prach4096 |
- prach_len = (4096*6)+Ncp;
- }
- else if (prach_fmt == 0xb4) { // 12x4096
- idft(IDFT_4096,prachF,prach2,1);
- dftlen=4096;
- // here we have |empty | Prach4096 |
- memmove(prach2+(4096<<1),prach2,(4096<<2));
- // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096
- memmove(prach2+(4096<<2),prach2,(4096<<3));
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096
- memmove(prach2+(4096<<3),prach2,(4096<<3));
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096
- memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6);
- // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096|
- memmove(prach,prach+(4096<<1),(Ncp<<2));
- // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096|
- prach_len = (4096*12)+Ncp;
- }
- }
- else { // 92.16 Ms/s
+ if (prach_sequence_length == 0){
+ if (prach_fmt_id == 0) { //24576 samples @ 30.72 Ms/s, 98304 samples @ 122.88 Ms/s
+ idft(IDFT_98304,prachF,prach2,1);
+ // here we have |empty | Prach98304|
+ memmove(prach,prach+(98304<<1),(Ncp<<2));
+ // here we have |Prefix | Prach98304|
+ prach_len = (98304*1)+Ncp;
+ } else if (prach_fmt_id == 1) {
+ idft(IDFT_98304,prachF,prach2,1);
+ memmove(prach2+(98304<<1),prach2,(98304<<2));
+ // here we have |empty | Prach98304 | Prach98304|
+ memmove(prach,prach+(98304<<2),(Ncp<<2));
+ // here we have |Prefix | Prach98304 | Prach98304|
+ prach_len = (98304*2)+Ncp;
+ } else if (prach_fmt_id == 2) {
+ idft(IDFT_98304,prachF,prach2,1);
+ memmove(prach2+(98304<<1),prach2,(98304<<2));
+ // here we have |empty | Prach98304 | Prach98304| empty98304 | empty98304
+ memmove(prach2+(98304<<2),prach2,(98304<<3));
+ // here we have |empty | Prach98304 | Prach98304| Prach98304 | Prach98304
+ memmove(prach,prach+(98304<<3),(Ncp<<2));
+ // here we have |Prefix | Prach98304 | Prach98304| Prach98304 | Prach98304
+ prach_len = (98304*4)+Ncp;
+ } else if (prach_fmt_id == 3) { // 4x6144, Ncp 3168
+ idft(IDFT_24576,prachF,prach2,1);
+ memmove(prach2+(24576<<1),prach2,(24576<<2));
+ // here we have |empty | Prach24576 | Prach24576| empty24576 | empty24576
+ memmove(prach2+(24576<<2),prach2,(24576<<3));
+ // here we have |empty | Prach24576 | Prach24576| Prach24576 | Prach24576
+ memmove(prach,prach+(24576<<3),(Ncp<<2));
+ // here we have |Prefix | Prach24576 | Prach24576| Prach24576 | Prach24576
+ prach_len = (24576*4)+Ncp;
+ }
+ } else { // short sequence
+ if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) {
+ Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_4096,prachF,prach2,1);
+ // here we have |empty | Prach4096 |
+ if (prach_fmt_id != 7) {
+ memmove(prach2+(4096<<1),prach2,(4096<<2));
+ prach_len = (4096*2)+Ncp;
+ } else prach_len = (4096*1)+Ncp;
+ memmove(prach,prach+(4096<<1),(Ncp<<2));
+ // here we have |Prefix | Prach4096 | Prach4096 (if ! 0xc0) |
+ } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x4096
+ Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_4096,prachF,prach2,1);
+ // here we have |empty | Prach4096 |
+ memmove(prach2+(4096<<1),prach2,(4096<<2));
+ // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 |
+ memmove(prach2+(4096<<2),prach2,(4096<<3));
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 |
+ memmove(prach,prach+(4096<<1),(Ncp<<2));
+ // here we have |Prefix | Prach4096 |
+ prach_len = (4096*4)+Ncp;
+ } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x4096
+ Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_4096,prachF,prach2,1);
+ // here we have |empty | Prach4096 |
+ memmove(prach2+(4096<<1),prach2,(4096<<2));
+ // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096
+ memmove(prach2+(4096<<2),prach2,(4096<<3));
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096
+ memmove(prach2+(4096<<3),prach2,(4096<<3));
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096
+ memmove(prach,prach+(4096<<1),(Ncp<<2));
+ // here we have |Prefix | Prach4096 |
+ prach_len = (4096*6)+Ncp;
+ } else if (prach_fmt_id == 6) { // 12x4096
+ Ncp+=64; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_4096,prachF,prach2,1);
+ // here we have |empty | Prach4096 |
+ memmove(prach2+(4096<<1),prach2,(4096<<2));
+ // here we have |empty | Prach4096 | Prach4096| empty4096 | empty4096 | empty4096 | empty4096
+ memmove(prach2+(4096<<2),prach2,(4096<<3));
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | empty4096 | empty4096
+ memmove(prach2+(4096<<3),prach2,(4096<<3));
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096
+ memmove(prach2+(4096<<1)*6,prach2,(4096<<2)*6);
+ // here we have |empty | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096|
+ memmove(prach,prach+(4096<<1),(Ncp<<2));
+ // here we have |Prefix | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096 | Prach4096| Prach4096 | Prach4096 | Prach4096 | Prach4096|
+ prach_len = (4096*12)+Ncp;
+ }
+ }
+ } else { // three quarter sampling @ 92.16 Ms/s
Ncp = (Ncp*3);
prach2 = prach+(Ncp<<1);
- if (prach_fmt == 0) {
- idft(IDFT_73728,prachF,prach2,1);
- dftlen=73728;
- // here we have |empty | Prach73728|
- memmove(prach,prach+(73728<<1),(Ncp<<4));
- // here we have |Prefix | Prach73728|
- prach_len = (73728*1)+Ncp;
- }
- else if (prach_fmt == 1) {
- idft(IDFT_73728,prachF,prach2,1);
- dftlen=73728;
- memmove(prach2+(73728<<1),prach2,(73728<<2));
- // here we have |empty | Prach73728 | Prach73728|
- memmove(prach,prach+(73728<<2),(Ncp<<4));
- // here we have |Prefix | Prach73728 | Prach73728|
- prach_len = (73728*2)+Ncp;
- }
- if (prach_fmt == 2) {
- idft(IDFT_73728,prachF,prach2,1);
- dftlen=73728;
- memmove(prach2+(73728<<1),prach2,(73728<<2));
- // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728
- memmove(prach2+(73728<<2),prach2,(73728<<3));
- // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728
- memmove(prach,prach+(73728<<3),(Ncp<<4));
- // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728
- prach_len = (73728*4)+Ncp;
- }
- else if (prach_fmt == 3) {
- idft(IDFT_18432,prachF,prach2,1);
- dftlen=18432;
- memmove(prach2+(18432<<1),prach2,(18432<<2));
- // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432
- memmove(prach2+(18432<<2),prach2,(18432<<3));
- // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432
- memmove(prach,prach+(18432<<3),(Ncp<<4));
- // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432
- prach_len = (18432*4)+Ncp;
- }
- else if (prach_fmt == 0xa1 || prach_fmt == 0xb1 || prach_fmt == 0xc0) {
- idft(IDFT_3072,prachF,prach2,1);
- dftlen=3072;
- // here we have |empty | Prach3072 |
- if (prach_fmt != 0xc0) {
- memmove(prach2+(3072<<1),prach2,(3072<<2));
- prach_len = (3072*2)+Ncp;
- }
- else prach_len = (3072*1)+Ncp;
- memmove(prach,prach+(3072<<1),(Ncp<<2));
- // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) |
- }
- else if (prach_fmt == 0xa3 || prach_fmt == 0xb3) { // 6x3072
- idft(IDFT_3072,prachF,prach2,1);
- dftlen=3072;
- // here we have |empty | Prach3072 |
- memmove(prach2+(3072<<1),prach2,(3072<<2));
- // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072
- memmove(prach2+(3072<<2),prach2,(3072<<3));
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072
- memmove(prach2+((3072<<1)*3),prach2,(3072<<3));
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072
- memmove(prach,prach+(3072<<1),(Ncp<<2));
- // here we have |Prefix | Prach3072 |
- prach_len = (3072*6)+Ncp;
- }
- else if (prach_fmt == 0xa2 || prach_fmt == 0xb2) { // 4x3072
- idft(IDFT_3072,prachF,prach2,1);
- dftlen=3072;
- // here we have |empty | Prach3072 |
- memmove(prach2+(3072<<1),prach2,(3072<<2));
- // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 |
- memmove(prach2+(3072<<2),prach2,(3072<<3));
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 |
- memmove(prach,prach+(3072<<1),(Ncp<<2));
- // here we have |Prefix | Prach3072 |
- prach_len = (3072*4)+Ncp;
- }
- else if (prach_fmt == 0xb4) { // 12x3072
- idft(IDFT_3072,prachF,prach2,1);
- dftlen=3072;
- // here we have |empty | Prach3072 |
- memmove(prach2+(3072<<1),prach2,(3072<<2));
- // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072
- memmove(prach2+(3072<<2),prach2,(3072<<3));
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072
- memmove(prach2+(3072<<3),prach2,(3072<<3));
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072
- memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6);
- // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072|
- memmove(prach,prach+(3072<<1),(Ncp<<2));
- // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072|
- prach_len = (3072*12)+Ncp;
+ if (prach_sequence_length == 0){
+ if (prach_fmt_id == 0) {
+ idft(IDFT_73728,prachF,prach2,1);
+ // here we have |empty | Prach73728|
+ memmove(prach,prach+(73728<<1),(Ncp<<2));
+ // here we have |Prefix | Prach73728|
+ prach_len = (73728*1)+Ncp;
+ } else if (prach_fmt_id == 1) {
+ idft(IDFT_73728,prachF,prach2,1);
+ memmove(prach2+(73728<<1),prach2,(73728<<2));
+ // here we have |empty | Prach73728 | Prach73728|
+ memmove(prach,prach+(73728<<2),(Ncp<<2));
+ // here we have |Prefix | Prach73728 | Prach73728|
+ prach_len = (73728*2)+Ncp;
+ } if (prach_fmt_id == 2) {
+ idft(IDFT_73728,prachF,prach2,1);
+ memmove(prach2+(73728<<1),prach2,(73728<<2));
+ // here we have |empty | Prach73728 | Prach73728| empty73728 | empty73728
+ memmove(prach2+(73728<<2),prach2,(73728<<3));
+ // here we have |empty | Prach73728 | Prach73728| Prach73728 | Prach73728
+ memmove(prach,prach+(73728<<3),(Ncp<<2));
+ // here we have |Prefix | Prach73728 | Prach73728| Prach73728 | Prach73728
+ prach_len = (73728*4)+Ncp;
+ } else if (prach_fmt_id == 3) {
+ idft(IDFT_18432,prachF,prach2,1);
+ memmove(prach2+(18432<<1),prach2,(18432<<2));
+ // here we have |empty | Prach18432 | Prach18432| empty18432 | empty18432
+ memmove(prach2+(18432<<2),prach2,(18432<<3));
+ // here we have |empty | Prach18432 | Prach18432| Prach18432 | Prach18432
+ memmove(prach,prach+(18432<<3),(Ncp<<2));
+ // here we have |Prefix | Prach18432 | Prach18432| Prach18432 | Prach18432
+ prach_len = (18432*4)+Ncp;
+ }
+ } else { // short sequence
+ if (prach_fmt_id == 0 || prach_fmt_id == 3 || prach_fmt_id == 7) {
+ Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_3072,prachF,prach2,1);
+ // here we have |empty | Prach3072 |
+ if (prach_fmt_id != 7) {
+ memmove(prach2+(3072<<1),prach2,(3072<<2));
+ prach_len = (3072*2)+Ncp;
+ } else prach_len = (3072*1)+Ncp;
+ memmove(prach,prach+(3072<<1),(Ncp<<2));
+ // here we have |Prefix | Prach3072 | Prach3072 (if ! 0xc0) |
+ } else if (prach_fmt_id == 2 || prach_fmt_id == 5) { // 6x3072
+ Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_3072,prachF,prach2,1);
+ // here we have |empty | Prach3072 |
+ memmove(prach2+(3072<<1),prach2,(3072<<2));
+ // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072
+ memmove(prach2+(3072<<2),prach2,(3072<<3));
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072
+ memmove(prach2+(3072<<3),prach2,(3072<<3));
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072
+ memmove(prach,prach+(3072<<1),(Ncp<<2));
+ // here we have |Prefix | Prach3072 |
+ prach_len = (3072*6)+Ncp;
+ } else if (prach_fmt_id == 1 || prach_fmt_id == 4) { // 4x3072
+ Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_3072,prachF,prach2,1);
+ // here we have |empty | Prach3072 |
+ memmove(prach2+(3072<<1),prach2,(3072<<2));
+ // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 |
+ memmove(prach2+(3072<<2),prach2,(3072<<3));
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 |
+ memmove(prach,prach+(3072<<1),(Ncp<<2));
+ // here we have |Prefix | Prach3072 |
+ prach_len = (3072*4)+Ncp;
+ } else if (prach_fmt_id == 6) { // 12x3072
+ Ncp+=48; // This assumes we are transmitting starting in symbol 0 of a PRACH slot, 30 kHz, full sampling
+ prach2 = prach+(Ncp<<1);
+ idft(IDFT_3072,prachF,prach2,1);
+ // here we have |empty | Prach3072 |
+ memmove(prach2+(3072<<1),prach2,(3072<<2));
+ // here we have |empty | Prach3072 | Prach3072| empty3072 | empty3072 | empty3072 | empty3072
+ memmove(prach2+(3072<<2),prach2,(3072<<3));
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | empty3072 | empty3072
+ memmove(prach2+(3072<<3),prach2,(3072<<3));
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072
+ memmove(prach2+(3072<<1)*6,prach2,(3072<<2)*6);
+ // here we have |empty | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072|
+ memmove(prach,prach+(3072<<1),(Ncp<<2));
+ // here we have |Prefix | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072 | Prach3072| Prach3072 | Prach3072 | Prach3072 | Prach3072|
+ prach_len = (3072*12)+Ncp;
+ }
}
}
- }
-
-
-
-
-#if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
- int j;
- int overflow = prach_start + prach_len - LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe;
- LOG_D( PHY, "prach_start=%d, overflow=%d\n", prach_start, overflow );
-
- for (i=prach_start,j=0; i<min(fp->samples_per_subframe*LTE_NUMBER_OF_SUBFRAMES_PER_FRAME,prach_start+prach_len); i++,j++) {
- ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j];
- ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1];
- }
-
- for (i=0; i<overflow; i++,j++) {
- ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j];
- ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1];
}
-#else
-
- LOG_D( PHY, "prach_start=%d\n", prach_start);
- for (i=0; i<prach_len; i++) {
- ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i] = prach[2*i];
- ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1];
- }
-#endif
+ #ifdef NR_PRACH_DEBUG
+ LOG_I(PHY, "PRACH [UE %d] N_RB_UL %d prach_start %d, prach_len %d, rx_offset %d, hw_timing_advance %d, N_TA_offset %d\n", Mod_id,
+ fp->N_RB_UL,
+ prach_start,
+ prach_len,
+ ue->rx_offset,
+ ue->hw_timing_advance,
+ ue->N_TA_offset);
+ #endif
+
+ #if defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR)
+ int j, overflow = prach_start + prach_len - NR_NUMBER_OF_SUBFRAMES_PER_FRAME*fp->samples_per_subframe;
+
+ #ifdef NR_PRACH_DEBUG
+ LOG_I( PHY, "PRACH [UE %d] overflow = %d\n", Mod_id, overflow);
+ #endif
+
+ // prach_start=414.730, overflow=-39470 prach_len=6600 fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME 460.800 prach_start+prach_len 421.330 fp->samples_per_subframe 46080
+
+ // from prach_start=414.730 to prach_start+prach_len 421.330
+ for (i = prach_start, j = 0; i < min(fp->samples_per_subframe*NR_NUMBER_OF_SUBFRAMES_PER_FRAME, prach_start + prach_len); i++, j++) {
+ ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j];
+ ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1];
+ }
+ for (i = 0; i < overflow; i++,j++) {
+ ((int16_t*)ue->common_vars.txdata[0])[2*i] = prach[2*j];
+ ((int16_t*)ue->common_vars.txdata[0])[2*i+1] = prach[2*j+1];
+ }
+ #else // simulators
+ for (i=0; i<prach_len; i++) {
+ ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i] = prach[2*i];
+ ((int16_t*)(&ue->common_vars.txdata[0][prach_start]))[2*i+1] = prach[2*i+1];
+ }
+ #endif
+ //printf("----------------------\n");
+ //for(int ii = prach_start; ii<2*(prach_start + prach_len); ii++){
+ // printf("PRACH rx data[%d] = %d\n", ii, ue->common_vars.txdata[0][ii]);
+ //}
+ //printf(" \n");
-#if defined(PRACH_WRITE_OUTPUT_DEBUG)
- LOG_M("prach_txF0.m","prachtxF0",prachF,prach_len-Ncp,1,1);
- LOG_M("prach_tx0.m","prachtx0",prach+(Ncp<<1),prach_len-Ncp,1,1);
- LOG_M("txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]),fp->samples_per_subframe,1,1);
- exit(-1);
-#endif
+ #ifdef PRACH_WRITE_OUTPUT_DEBUG
+ LOG_M("prach_tx0.m", "prachtx0", prach+(Ncp<<1), prach_len-Ncp, 1, 1);
+ LOG_M("Prach_txsig.m","txs",(int16_t*)(&ue->common_vars.txdata[0][prach_start]), 2*(prach_start+prach_len), 1, 1)
+ #endif
- return signal_energy( (int*)prach, 256 );
+ return signal_energy((int*)prach, 256);
}
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
index 35fe8bc8992e6ab507c6e43cf83dfac1b691ccd8..ee957965cdb814a066a9ac1d1a8d7426d869d992 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
@@ -37,6 +37,9 @@
#include <math.h>
#include "nfapi_interface.h"
+#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1
+#define NR_PUSCH_y 3 // UCI placeholder bit
+
// Functions below implement 36-211 and 36-212
/** @addtogroup _PHY_TRANSPORT_
@@ -66,24 +69,6 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulsch,unsigned char N_RB_UL);
NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL, int number_of_harq_pids, uint8_t abstraction_flag);
-void fill_UE_dlsch_MCH(PHY_VARS_NR_UE *ue,int mcs,int ndi,int rvidx,int eNB_id);
-
-int rx_pmch(PHY_VARS_NR_UE *phy_vars_ue,
- unsigned char eNB_id,
- uint8_t subframe,
- unsigned char symbol);
-
-/** \brief Dump OCTAVE/MATLAB files for PMCH debugging
- @param phy_vars_ue Pointer to UE variables
- @param eNB_id index of eNB in ue variables
- @param coded_bits_per_codeword G from 36.211
- @param subframe Index of subframe
- @returns 0 on success
-*/
-void dump_mch(PHY_VARS_NR_UE *phy_vars_ue,uint8_t eNB_id,uint16_t coded_bits_per_codeword,int subframe);
-
-
-
/** \brief This function computes the LLRs for ML (max-logsum approximation) dual-stream QPSK/QPSK reception.
@param stream0_in Input from channel compensated (MR combined) stream 0
@param stream1_in Input from channel compensated (MR combined) stream 1
@@ -1053,7 +1038,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
NR_DL_FRAME_PARMS* frame_parms,
- uint8_t harq_pid);
+ uint8_t harq_pid,
+ unsigned int G);
/*! \brief Perform PUSCH scrambling. TS 38.211 V15.4.0 subclause 6.3.1.1
@param[in] in, Pointer to input bits
@@ -1078,7 +1064,7 @@ void nr_pusch_codeword_scrambling(uint8_t *in,
void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
unsigned char harq_pid,
- uint8_t frame,
+ uint32_t frame,
uint8_t slot,
uint8_t thread_id,
int gNB_id);
@@ -1401,8 +1387,10 @@ void ulsch_modulation(int32_t **txdataF,
NR_UE_ULSCH_t *ulsch);
-
-
+uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k,
+ uint16_t start_sc,
+ uint8_t numDmrsCdmGrpsNoData,
+ uint8_t dmrs_type);
int generate_ue_dlsch_params_from_dci(int frame,
@@ -1539,11 +1527,11 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME
void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi);
-void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
- int16_t *z, int16_t *z2,uint32_t length, uint16_t pdcch_DMRS_scrambling_id);
-
-
-
+void nr_pdcch_unscrambling(int16_t *z,
+ uint16_t scrambling_RNTI,
+ uint32_t length,
+ uint16_t pdcch_DMRS_scrambling_id,
+ int16_t *z2);
void dlsch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
int mbsfn_flag,
@@ -1756,9 +1744,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t is_crnti,
uint8_t llr8_flag);
-
-
-int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf );
+int32_t generate_nr_prach(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint8_t subframe);
void *dlsch_thread(void *arg);
/**@}*/
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
index fb560f229d26db49060f9065892d574a5915d453..d1dd0f785b9c20378a35c1e9ecd7aec09eebc0da 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
@@ -42,9 +42,8 @@
#include "UTIL/LISTS/list.h"
#endif
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h"
-//#include "../LTE_TRANSPORT/transport_common.h"
// structures below implement 36-211 and 36-212
@@ -86,40 +85,26 @@ typedef struct {
#endif
typedef struct {
+ /// NDAPI struct for UE
+ nfapi_nr_ue_pusch_pdu_t pusch_pdu;
/// Indicator of first transmission
uint8_t first_tx;
- /// Last Ndi received for this process on DCI (used for C-RNTI only)
- uint8_t DCINdi;
/// HARQ tx status
harq_result_t tx_status;
- /// Flag indicating that this ULSCH has a new packet (start of new round)
- // uint8_t Ndi;
/// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
uint8_t subframe_scheduling_flag;
/// Subframe cba scheduling indicator (i.e. Transmission opportunity indicator)
uint8_t subframe_cba_scheduling_flag;
- /// First Allocated RB
- uint16_t first_rb;
- /// Current Number of RBs
- uint16_t nb_rb;
- /// number of layers
- uint8_t Nl;
/// Last TPC command
uint8_t TPC;
- /// Transport block size
- uint32_t TBS;
/// The payload + CRC size in bits, "B" from 36-212
uint32_t B;
/// Length of ACK information (bits)
uint8_t O_ACK;
/// Index of current HARQ round for this ULSCH
uint8_t round;
- /// MCS format of this ULSCH
- uint8_t mcs;
- /// Redundancy-version of the current sub-frame
- uint8_t rvidx;
/// pointer to pdu from MAC interface (TS 36.212 V15.4.0, Sec 5.1 p. 8)
unsigned char *a;
/// Pointer to the payload + CRC
@@ -152,19 +137,11 @@ typedef struct {
uint32_t G;
// Number of modulated symbols carrying data
uint32_t num_of_mod_symbols;
- // This is "L" in TS 38.214 V15.4.0 subclause 6.1.2.1
- uint8_t number_of_symbols;
- // This is "S" in TS 38.214 V15.4.0 subclause 6.1.2.1
- uint8_t start_symbol;
// decode phich
uint8_t decode_phich;
} NR_UL_UE_HARQ_t;
typedef struct {
- /// number of DMRS resource elements
- uint8_t nb_re_dmrs;
- /// DMRS length
- uint8_t length_dmrs;
/// SRS active flag
uint8_t srs_active;
//#if defined(UPGRADE_RAT_NR)
@@ -200,7 +177,7 @@ typedef struct {
/// Scrambled "b"-sequences (for definition see 36-211 V8.6 2009-03, p.14)
uint8_t b_tilde[MAX_NUM_NR_CHANNEL_BITS];
/// Modulated "d"-sequences (for definition see 36-211 V8.6 2009-03, p.14)
- uint32_t d_mod[MAX_NUM_NR_RE];
+ uint32_t d_mod[MAX_NUM_NR_RE] __attribute__ ((aligned(16)));
/// Transform-coded "y"-sequences (for definition see 38-211 V15.3.0 2018-09, subsection 6.3.1.4)
uint32_t y[MAX_NUM_NR_RE] __attribute__ ((aligned(16)));
/*
@@ -226,8 +203,6 @@ typedef struct {
uint8_t power_offset;
// for cooperative communication
uint8_t cooperation_flag;
- /// RNTI attributed to this ULSCH
- uint16_t rnti;
/// RNTI type
uint8_t rnti_type;
/// Cell ID
@@ -317,6 +292,8 @@ typedef struct {
uint16_t dlDmrsSymbPos;
/// DMRS Configuration Type
uint8_t dmrsConfigType;
+ // Number of DMRS CDM groups with no data
+ uint8_t n_dmrs_cdm_groups;
/// Starting Symbol number
uint16_t start_symbol;
/// Current subband PMI allocation
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c
index 00627ac3ae33559b40acf8736de42104a4b9f2f5..4b36f91e69af639f81d32444956bed823412f82e 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c
@@ -60,17 +60,16 @@ void free_nr_ue_ulsch(NR_UE_ULSCH_t **ulschptr,unsigned char N_RB_UL)
a_segments = a_segments/273;
}
- uint16_t ulsch_bytes = a_segments*1056; // allocated bytes per segment
for (i=0; i<NR_MAX_ULSCH_HARQ_PROCESSES; i++) {
if (ulsch->harq_processes[i]) {
if (ulsch->harq_processes[i]->a) {
- free16(ulsch->harq_processes[i]->a,ulsch_bytes);
+ free16(ulsch->harq_processes[i]->a,a_segments*1056);
ulsch->harq_processes[i]->a = NULL;
}
if (ulsch->harq_processes[i]->b) {
- free16(ulsch->harq_processes[i]->b,ulsch_bytes);
+ free16(ulsch->harq_processes[i]->b,a_segments*1056);
ulsch->harq_processes[i]->b = NULL;
}
if (ulsch->harq_processes[i]->e) {
@@ -217,15 +216,15 @@ NR_UE_ULSCH_t *new_nr_ue_ulsch(uint16_t N_RB_UL,
int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
NR_DL_FRAME_PARMS* frame_parms,
- uint8_t harq_pid)
+ uint8_t harq_pid,
+ unsigned int G)
{
/////////////////////////parameters and variables declaration/////////////////////////
///////////
- unsigned int G,crc;
+ unsigned int crc;
NR_UL_UE_HARQ_t *harq_process;
uint16_t nb_rb ;
- uint8_t nb_symb_sch ;
uint32_t A, Z, F;
uint32_t *pz;
uint8_t mod_order;
@@ -235,8 +234,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
uint32_t E,Kb;
uint8_t Ilbrm;
uint32_t Tbslbrm;
- uint8_t nb_re_dmrs;
- uint16_t length_dmrs;
uint16_t R;
float Coderate;
@@ -249,32 +246,25 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
crc = 1;
harq_process = ulsch->harq_processes[harq_pid];
- nb_rb = harq_process->nb_rb;
- nb_symb_sch = harq_process->number_of_symbols;
- A = harq_process->TBS;
+ nb_rb = harq_process->pusch_pdu.rb_size;
+ A = harq_process->pusch_pdu.pusch_data.tb_size;
pz = &Z;
- mod_order = nr_get_Qm_ul(harq_process->mcs,0);
- R = nr_get_code_rate_ul(harq_process->mcs, 0);
+ mod_order = nr_get_Qm_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table);
+ R = nr_get_code_rate_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table);
Kr=0;
r_offset=0;
BG = 1;
F=0;
Ilbrm = 0;
Tbslbrm = 950984; //max tbs
- nb_re_dmrs = ulsch->nb_re_dmrs;
- length_dmrs = ulsch->length_dmrs;
Coderate = 0.0;
///////////
/////////////////////////////////////////////////////////////////////////////////////////
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_IN);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_IN);
-
- LOG_D(PHY,"ulsch coding nb_rb %d nb_symb_sch %d nb_re_dmrs %d, length_dmrs %d, harq_process->Nl = %d\n", nb_rb,nb_symb_sch, nb_re_dmrs,length_dmrs, harq_process->Nl);
-
-
- G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs,mod_order,harq_process->Nl);
+ LOG_D(PHY,"ulsch coding nb_rb %d, Nl = %d\n", nb_rb, harq_process->pusch_pdu.nrOfLayers);
LOG_D(PHY,"ulsch coding A %d G %d mod_order %d\n", A,G, mod_order);
// if (harq_process->Ndi == 1) { // this is a new packet
@@ -292,6 +282,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
printf("%02x.",a[i]);
printf("\n");
*/
+
if (A > 3824) {
// Add 24-bit crc (polynomial A) to payload
crc = crc24a(harq_process->a,A)>>8;
@@ -321,7 +312,6 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
memcpy(harq_process->b,harq_process->a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc
}
-
///////////
///////////////////////////////////////////////////////////////////////////
@@ -340,6 +330,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
BG = 1;
}
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_IN);
Kb=nr_segmentation(harq_process->b,
harq_process->c,
harq_process->B,
@@ -348,6 +339,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
pz,
&harq_process->F,
BG);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_SEGMENTATION, VCD_FUNCTION_OUT);
F = harq_process->F;
Kr = harq_process->K;
@@ -398,7 +390,11 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
impp.n_segments=harq_process->C;
impp.macro_num=0;
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_IN);
+
nrLDPC_encoder(harq_process->c,harq_process->d,*pz,Kb,Kr,BG,&impp);
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_LDPC_ENCODER_OPTIM, VCD_FUNCTION_OUT);
//stop_meas(te_stats);
//printf("end ldpc encoder -- output\n");
@@ -434,16 +430,17 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
//start_meas(rm_stats);
#ifdef DEBUG_DLSCH_CODING
- printf("rvidx in encoding = %d\n", harq_process->rvidx);
+ printf("rvidx in encoding = %d\n", harq_process->pusch_pdu.pusch_data.rv_index);
#endif
///////////////////////// d---->| Rate matching bit selection |---->e /////////////////////////
///////////
- E = nr_get_E(G, harq_process->C, mod_order, harq_process->Nl, r);
+ E = nr_get_E(G, harq_process->C, mod_order, harq_process->pusch_pdu.nrOfLayers, r);
- Tbslbrm = nr_compute_tbslbrm(0,nb_rb,harq_process->Nl,harq_process->C);
+ Tbslbrm = nr_compute_tbslbrm(0,nb_rb,harq_process->pusch_pdu.nrOfLayers,harq_process->C);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_IN);
nr_rate_matching_ldpc(Ilbrm,
Tbslbrm,
BG,
@@ -453,8 +450,9 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
harq_process->C,
F,
Kr-F-2*(*pz),
- harq_process->rvidx,
+ harq_process->pusch_pdu.pusch_data.rv_index,
E);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RATE_MATCHING_LDPC, VCD_FUNCTION_OUT);
@@ -473,10 +471,14 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
//stop_meas(rm_stats);
//start_meas(i_stats);
- nr_interleaving_ldpc(E,
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_IN);
+
+ nr_interleaving_ldpc(E,
mod_order,
harq_process->e+r_offset,
harq_process->f+r_offset);
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INTERLEAVING_LDPC, VCD_FUNCTION_OUT);
//stop_meas(i_stats);
@@ -497,7 +499,7 @@ int nr_ulsch_encoding(NR_UE_ULSCH_t *ulsch,
memcpy(ulsch->g,harq_process->f,G); // g is the concatenated code block
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING, VCD_FUNCTION_OUT);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_OUT);
return(0);
}
diff --git a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
index a15851bf4910a0476f657cbb75de0b2b516179cf..34cd6e92af48b9c044cc4e2d0e1af4b79c0714e3 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
@@ -93,11 +93,13 @@ void nr_pusch_codeword_scrambling(uint8_t *in,
void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
unsigned char harq_pid,
- uint8_t frame,
+ uint32_t frame,
uint8_t slot,
uint8_t thread_id,
int gNB_id) {
+ LOG_D(PHY,"nr_ue_ulsch_procedures hard_id %d %d.%d\n",harq_pid,frame,slot);
+
uint32_t available_bits;
uint8_t mod_order, cwd_index, num_of_codewords, l;
uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5];
@@ -106,12 +108,11 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
int32_t **txdataF;
uint16_t start_sc, start_rb;
int8_t Wf[2], Wt[2], l_prime[2], delta;
- uint16_t n_dmrs, code_rate, number_dmrs_symbols, k;
- uint8_t dmrs_type;
+ uint16_t rnti, n_dmrs, code_rate, number_dmrs_symbols, nb_rb, k;
+ uint8_t dmrs_type, nb_dmrs_re_per_rb, number_of_symbols, mcs, Nl;
int ap, start_symbol, Nid_cell, i;
int sample_offsetF, N_RE_prime, N_PRB_oh;
- uint16_t n_rnti;
- uint8_t data_existing =0;
+ uint16_t ul_dmrs_symb_pos;
uint8_t L_ptrs, K_ptrs; // PTRS parameters
uint16_t beta_ptrs; // PTRS parameter related to power control
@@ -119,107 +120,61 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
NR_UL_UE_HARQ_t *harq_process_ul_ue=NULL;
NR_DL_FRAME_PARMS *frame_parms = &UE->frame_parms;
NR_UE_PUSCH *pusch_ue = UE->pusch_vars[thread_id][gNB_id];
- uint8_t ulsch_input_buffer[MAX_ULSCH_PAYLOAD_BYTES];
- ptrs_UplinkConfig_t *ptrs_Uplink_Config = &UE->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig;
+ // ptrs_UplinkConfig_t *ptrs_Uplink_Config = &UE->pusch_config.dmrs_UplinkConfig.ptrs_UplinkConfig;
num_of_codewords = 1; // tmp assumption
- n_rnti = 0x1234;
Nid_cell = 0;
N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig
number_dmrs_symbols = 0;
- uint8_t mapping_type = UE->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType;
for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) {
ulsch_ue = UE->ulsch[thread_id][gNB_id][cwd_index];
harq_process_ul_ue = ulsch_ue->harq_processes[harq_pid];
- start_symbol = harq_process_ul_ue->start_symbol;
-
- for (i = start_symbol; i < start_symbol + harq_process_ul_ue->number_of_symbols; i++)
- number_dmrs_symbols += is_dmrs_symbol((mapping_type)?i-start_symbol:i,
- 0,
- 0,
- 0,
- 0,
- 0,
- harq_process_ul_ue->number_of_symbols,
- UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type,
- frame_parms->ofdm_symbol_size);
-
- ulsch_ue->length_dmrs = number_dmrs_symbols; // pusch.MaxLenght is redundant here as number_dmrs_symbols
- // contains all dmrs symbols even for double symbol dmrs
- ulsch_ue->rnti = n_rnti;
+ start_symbol = harq_process_ul_ue->pusch_pdu.start_symbol_index;
+ ul_dmrs_symb_pos = harq_process_ul_ue->pusch_pdu.ul_dmrs_symb_pos;
+ number_of_symbols = harq_process_ul_ue->pusch_pdu.nr_of_symbols;
+ dmrs_type = harq_process_ul_ue->pusch_pdu.dmrs_config_type;
+
+ for (i = start_symbol; i < start_symbol + number_of_symbols; i++) {
+
+ if((ul_dmrs_symb_pos >> i) & 0x01)
+ number_dmrs_symbols += 1;
+
+ }
+
+ rnti = harq_process_ul_ue->pusch_pdu.rnti;
ulsch_ue->Nid_cell = Nid_cell;
- ulsch_ue->nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1)?6:4);
- N_RE_prime = NR_NB_SC_PER_RB*harq_process_ul_ue->number_of_symbols - ulsch_ue->nb_re_dmrs*number_dmrs_symbols - N_PRB_oh;
+ nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4)*harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data;
+
+ N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh;
- harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*harq_process_ul_ue->nb_rb*num_of_codewords;
+ nb_rb = harq_process_ul_ue->pusch_pdu.rb_size;
- mod_order = nr_get_Qm_ul(harq_process_ul_ue->mcs, 0);
- code_rate = nr_get_code_rate_ul(harq_process_ul_ue->mcs, 0);
+ harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*num_of_codewords;
- harq_process_ul_ue->TBS = nr_compute_tbs(mod_order,
+ mcs = harq_process_ul_ue->pusch_pdu.mcs_index;
+ Nl = harq_process_ul_ue->pusch_pdu.nrOfLayers;
+ mod_order = nr_get_Qm_ul(mcs, 0);
+ code_rate = nr_get_code_rate_ul(mcs, 0);
+
+ harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = nr_compute_tbs(mod_order,
code_rate,
- harq_process_ul_ue->nb_rb,
- harq_process_ul_ue->number_of_symbols,
- ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs,
+ nb_rb,
+ number_of_symbols,
+ nb_dmrs_re_per_rb*number_dmrs_symbols,
0,
- harq_process_ul_ue->Nl);
-
- uint8_t access_mode = SCHEDULED_ACCESS;
-
- //-----------------------------------------------------//
- // to be removed later when MAC is ready
-
- if (harq_process_ul_ue != NULL){
- data_existing = 0;
-
- if (IS_SOFTMODEM_NOS1){
- data_existing = nr_ue_get_sdu(UE->Mod_id, UE->CC_id, frame,
- slot, 0, ulsch_input_buffer, harq_process_ul_ue->TBS/8, &access_mode);
- //IP traffic to be transmitted
- if(data_existing){
- //harq_process_ul_ue->a = (unsigned char*)calloc(harq_process_ul_ue->TBS/8, sizeof(unsigned char));
- memcpy(harq_process_ul_ue->a, ulsch_input_buffer, harq_process_ul_ue->TBS/8);
-
- #ifdef DEBUG_MAC_PDU
- LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", harq_process_ul_ue->TBS/8);
- for (i = 0; i < harq_process_ul_ue->TBS / 8; i++) {
- printf("0x%02x",harq_process_ul_ue->a[i]);
- }
- printf("\n");
- #endif
- }
- }
- //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity
- if (!IS_SOFTMODEM_NOS1 || !data_existing) {
- //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid
- //and block this traffic from being forwarded to the upper layers at the gNB
- uint16_t payload_offset = 5;
- LOG_D(PHY, "Random data to be tranmsitted: \n");
- //Give the header bytes some dummy value in order to block the random packet at the MAC layer of the receiver
- for (i = 0; i<payload_offset; i++)
- harq_process_ul_ue->a[i] = 0;
-
- for (i = payload_offset; i < harq_process_ul_ue->TBS / 8; i++) {
- harq_process_ul_ue->a[i] = (unsigned char) rand();
- //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]);
- }
- }
- } else {
- LOG_E(PHY, "[phy_procedures_nrUE_TX] harq_process_ul_ue is NULL !!\n");
- return;
- }
-
- //-----------------------------------------------------//
+ 0,
+ harq_process_ul_ue->pusch_pdu.nrOfLayers);
/////////////////////////ULSCH coding/////////////////////////
///////////
-
- nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid);
+ unsigned int G = nr_get_G(nb_rb, number_of_symbols,
+ nb_dmrs_re_per_rb, number_dmrs_symbols, mod_order, Nl);
+ nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G);
///////////
////////////////////////////////////////////////////////////////////
@@ -227,21 +182,14 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
/////////////////////////ULSCH scrambling/////////////////////////
///////////
- mod_order = nr_get_Qm_ul(harq_process_ul_ue->mcs, 0);
-
- available_bits = nr_get_G(harq_process_ul_ue->nb_rb,
- harq_process_ul_ue->number_of_symbols,
- ulsch_ue->nb_re_dmrs,
- ulsch_ue->length_dmrs,
- mod_order,
- 1);
+ available_bits = G;
memset(scrambled_output[cwd_index], 0, ((available_bits>>5)+1)*sizeof(uint32_t));
nr_pusch_codeword_scrambling(ulsch_ue->g,
available_bits,
ulsch_ue->Nid_cell,
- ulsch_ue->rnti,
+ rnti,
scrambled_output[cwd_index]); // assume one codeword for the moment
@@ -269,9 +217,8 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
/////////////////////////DMRS Modulation/////////////////////////
///////////
pusch_dmrs = UE->nr_gold_pusch_dmrs[slot];
- n_dmrs = (harq_process_ul_ue->nb_rb*ulsch_ue->nb_re_dmrs*ulsch_ue->length_dmrs);
- int16_t mod_dmrs[n_dmrs<<1];
- dmrs_type = UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type;
+ n_dmrs = (nb_rb*((dmrs_type == pusch_dmrs_type1) ? 6:4)*number_dmrs_symbols);
+ int16_t mod_dmrs[n_dmrs<<1] __attribute((aligned(16)));
///////////
////////////////////////////////////////////////////////////////////////
@@ -279,26 +226,23 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
/////////////////////////PTRS parameters' initialization/////////////////////////
///////////
- int16_t mod_ptrs[(harq_process_ul_ue->nb_rb/2)*(NR_SYMBOLS_PER_SLOT-1)*2]; // assume maximum number of PTRS per pusch allocation
+ int16_t mod_ptrs[(nb_rb/2)*(NR_SYMBOLS_PER_SLOT-1)*2]; // assume maximum number of PTRS per pusch allocation
K_ptrs = 0; // just to avoid a warning
- if (UE->ptrs_configured == 1) {
+ if (harq_process_ul_ue->pusch_pdu.pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS) {
- K_ptrs = get_K_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->nb_rb);
-
- L_ptrs = get_L_ptrs(ptrs_Uplink_Config, harq_process_ul_ue->mcs);
+ K_ptrs = (harq_process_ul_ue->pusch_pdu.pusch_ptrs.ptrs_freq_density)?4:2;
+ L_ptrs = 1<<harq_process_ul_ue->pusch_pdu.pusch_ptrs.ptrs_time_density;
beta_ptrs = 1; // temp value until power control is implemented
ulsch_ue->ptrs_symbols = 0;
set_ptrs_symb_idx(&ulsch_ue->ptrs_symbols,
- harq_process_ul_ue->number_of_symbols,
+ number_of_symbols,
start_symbol,
- dmrs_type,
L_ptrs,
- ulsch_ue->length_dmrs,
- frame_parms->ofdm_symbol_size);
+ ul_dmrs_symb_pos);
}
///////////
@@ -310,9 +254,9 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
tx_layers = (int16_t **)pusch_ue->txdataF_layers;
nr_ue_layer_mapping(UE->ulsch[thread_id][gNB_id],
- harq_process_ul_ue->Nl,
- available_bits/mod_order,
- tx_layers);
+ Nl,
+ available_bits/mod_order,
+ tx_layers);
///////////
////////////////////////////////////////////////////////////////////////
@@ -327,24 +271,19 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
uint32_t nb_re_pusch, nb_re_dmrs_per_rb;
uint32_t y_offset = 0;
- for (l = start_symbol; l < start_symbol + harq_process_ul_ue->number_of_symbols; l++) {
+ for (l = start_symbol; l < start_symbol + number_of_symbols; l++) {
- is_dmrs = is_dmrs_symbol((mapping_type)?l-start_symbol:l,
- 0,
- 0,
- 0,
- 0,
- 0,
- harq_process_ul_ue->number_of_symbols,
- dmrs_type,
- frame_parms->ofdm_symbol_size);
+ if((ul_dmrs_symb_pos >> l) & 0x01)
+ is_dmrs = 1;
+ else
+ is_dmrs = 0;
if (is_dmrs == 1)
- nb_re_dmrs_per_rb = ulsch_ue->nb_re_dmrs;
+ nb_re_dmrs_per_rb = nb_dmrs_re_per_rb;
else
nb_re_dmrs_per_rb = 0;
- nb_re_pusch = harq_process_ul_ue->nb_rb * (NR_NB_SC_PER_RB - nb_re_dmrs_per_rb);
+ nb_re_pusch = nb_rb * (NR_NB_SC_PER_RB - nb_re_dmrs_per_rb);
nr_dft(&ulsch_ue->y[y_offset], &((int32_t*)tx_layers[0])[y_offset], nb_re_pusch);
@@ -364,13 +303,13 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
txdataF = UE->common_vars.txdataF;
- start_rb = harq_process_ul_ue->first_rb;
+ start_rb = harq_process_ul_ue->pusch_pdu.rb_start;
start_sc = frame_parms->first_carrier_offset + start_rb*NR_NB_SC_PER_RB;
if (start_sc >= frame_parms->ofdm_symbol_size)
start_sc -= frame_parms->ofdm_symbol_size;
- for (ap=0; ap<harq_process_ul_ue->Nl; ap++) {
+ for (ap=0; ap< Nl; ap++) {
// DMRS params for this ap
get_Wt(Wt, ap, dmrs_type);
@@ -379,47 +318,41 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
uint8_t k_prime=0;
- uint8_t is_dmrs, is_ptrs;
- uint8_t l_ref;
+ uint8_t is_dmrs, is_ptrs, is_dmrs_symbol;
uint16_t m=0, n=0, dmrs_idx=0, ptrs_idx = 0;
- for (l=start_symbol; l<start_symbol+harq_process_ul_ue->number_of_symbols; l++) {
+ for (l=start_symbol; l<start_symbol+number_of_symbols; l++) {
k = start_sc;
n = 0;
dmrs_idx = 0;
- l_ref = (mapping_type) ? l-start_symbol : l;
- for (i=0; i<harq_process_ul_ue->nb_rb*NR_NB_SC_PER_RB; i++) {
+ for (i=0; i< nb_rb*NR_NB_SC_PER_RB; i++) {
sample_offsetF = l*frame_parms->ofdm_symbol_size + k;
is_dmrs = 0;
is_ptrs = 0;
+ is_dmrs_symbol = 0;
- is_dmrs = is_dmrs_symbol(l_ref,
- k,
- start_sc,
- k_prime,
- n,
- delta,
- harq_process_ul_ue->number_of_symbols,
- dmrs_type,
- frame_parms->ofdm_symbol_size);
-
- if (UE->ptrs_configured == 1){
- is_ptrs = is_ptrs_symbol(l,
- k,
- ulsch_ue->rnti,
- harq_process_ul_ue->nb_rb,
- harq_process_ul_ue->number_of_symbols,
- ap,
- K_ptrs,
- ulsch_ue->ptrs_symbols,
- start_sc,
- frame_parms->ofdm_symbol_size,
- UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type,
- ptrs_Uplink_Config->resourceElementOffset);
+ if((ul_dmrs_symb_pos >> l) & 0x01) {
+ is_dmrs_symbol = 1;
+ if (k == ((start_sc+get_dmrs_freq_idx_ul(n, k_prime, delta, dmrs_type))%frame_parms->ofdm_symbol_size))
+ is_dmrs = 1;
+ }
+
+ if (harq_process_ul_ue->pusch_pdu.pdu_bit_map & PUSCH_PDU_BITMAP_PUSCH_PTRS){
+
+ if(is_ptrs_symbol(l, ulsch_ue->ptrs_symbols))
+ is_ptrs = is_ptrs_subcarrier(k,
+ rnti,
+ ap,
+ dmrs_type,
+ K_ptrs,
+ nb_rb,
+ harq_process_ul_ue->pusch_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset,
+ start_sc,
+ frame_parms->ofdm_symbol_size);
}
if (is_dmrs == 1) {
@@ -446,7 +379,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
} else if (is_ptrs == 1) {
if (k == start_sc){
- nr_modulation(pusch_dmrs[l][0], harq_process_ul_ue->nb_rb/2, DMRS_MOD_ORDER, mod_ptrs);
+ nr_modulation(pusch_dmrs[l][0], nb_rb, DMRS_MOD_ORDER, mod_ptrs);
}
((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = (beta_ptrs*AMP*mod_ptrs[ptrs_idx<<1]) >> 15;
@@ -454,18 +387,24 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
ptrs_idx++;
- } else {
+ } else if (!is_dmrs_symbol || allowed_xlsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) {
((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1];
((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1];
- #ifdef DEBUG_PUSCH_MAPPING
- printf("m %d\t l %d \t k %d \t txdataF: %d %d\n",
- m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1],
- ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]);
- #endif
+ #ifdef DEBUG_PUSCH_MAPPING
+ printf("m %d\t l %d \t k %d \t txdataF: %d %d\n",
+ m, l, k, ((int16_t*)txdataF[ap])[(sample_offsetF)<<1],
+ ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1]);
+ #endif
m++;
+
+ } else {
+
+ ((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = 0;
+ ((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = 0;
+
}
if (++k >= frame_parms->ofdm_symbol_size)
@@ -475,11 +414,13 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
}
//}
+ NR_UL_UE_HARQ_t *harq_process_ulsch=NULL;
+ harq_process_ulsch = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid];
+ harq_process_ulsch->status = SCH_IDLE;
///////////
////////////////////////////////////////////////////////////////////////
- LOG_D(PHY, "Is data existing ?: %d \n", data_existing);
}
@@ -494,7 +435,7 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE,
int32_t **txdata;
int32_t **txdataF;
int timing_advance;
- uint8_t Nl = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->Nl; // cw 0
+ uint8_t Nl = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->pusch_pdu.nrOfLayers; // cw 0
/////////////////////////IFFT///////////////////////
///////////
@@ -520,21 +461,51 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE,
txdata = UE->common_vars.txdata;
txdataF = UE->common_vars.txdataF;
- for (ap = 0; ap < Nl; ap++) {
+ if(UE->N_TA_offset > tx_offset) {
+ int32_t *tmp_idft_out = (int32_t*)malloc16(frame_parms->get_samples_per_slot(slot, frame_parms) * sizeof(int32_t));
+
+ for(ap = 0; ap < Nl; ap++) {
if (frame_parms->Ncp == 1) { // extended cyclic prefix
- PHY_ofdm_mod(txdataF[ap],
- &txdata[ap][tx_offset],
- frame_parms->ofdm_symbol_size,
- 12,
- frame_parms->nb_prefix_samples,
- CYCLIC_PREFIX);
+ PHY_ofdm_mod(txdataF[ap],
+ tmp_idft_out,
+ frame_parms->ofdm_symbol_size,
+ 12,
+ frame_parms->nb_prefix_samples,
+ CYCLIC_PREFIX);
} else { // normal cyclic prefix
- nr_normal_prefix_mod(txdataF[ap],
- &txdata[ap][tx_offset],
- 14,
- frame_parms);
+ nr_normal_prefix_mod(txdataF[ap],
+ tmp_idft_out,
+ 14,
+ frame_parms);
+ }
+
+ memcpy((void *) &txdata[ap][frame_parms->samples_per_frame - UE->N_TA_offset + tx_offset],
+ (void *) tmp_idft_out,
+ (UE->N_TA_offset - tx_offset) * sizeof(int32_t));
+
+ memcpy((void *) &txdata[ap][0],
+ (void *) &tmp_idft_out[UE->N_TA_offset - tx_offset],
+ (frame_parms->get_samples_per_slot(slot, frame_parms) - UE->N_TA_offset + tx_offset) * sizeof(int32_t));
+ }
+
+ free(tmp_idft_out);
+ } else { // UE->N_TA_offset <= tx_offset
+ for (ap = 0; ap < Nl; ap++) {
+ if (frame_parms->Ncp == 1) { // extended cyclic prefix
+ PHY_ofdm_mod(txdataF[ap],
+ &txdata[ap][tx_offset-UE->N_TA_offset],
+ frame_parms->ofdm_symbol_size,
+ 12,
+ frame_parms->nb_prefix_samples,
+ CYCLIC_PREFIX);
+ } else { // normal cyclic prefix
+ nr_normal_prefix_mod(txdataF[ap],
+ &txdata[ap][tx_offset-UE->N_TA_offset],
+ 14,
+ frame_parms);
}
}
+ }
///////////
////////////////////////////////////////////////////
diff --git a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c
index baf34ade92a2a67fe51aae93498af971993c674f..c977118df3188bd8cee268e1c935aab183f03aab 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/pss_nr.c
@@ -38,6 +38,7 @@
#include "PHY/defs_nr_UE.h"
#include "PHY/NR_REFSIG/ss_pbch_nr.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
#define DEFINE_VARIABLES_PSS_NR_H
#include "PHY/NR_REFSIG/pss_nr.h"
@@ -672,6 +673,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change)
int **rxdata = NULL;
int fo_flag = PHY_vars_UE->UE_fo_compensation; // flag to enable freq offset estimation and compensation
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_IN);
#ifdef DBG_PSS_NR
LOG_M("rxdata0_rand.m","rxd0_rand", &PHY_vars_UE->common_vars.rxdata[0][0], frame_parms->samples_per_frame, 1, 1);
@@ -710,6 +712,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change)
#endif
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_IN);
synchro_position = pss_search_time_nr(rxdata,
frame_parms,
fo_flag,
@@ -717,6 +720,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change)
(int *)&PHY_vars_UE->common_vars.eNb_id,
(int *)&PHY_vars_UE->common_vars.freq_offset);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SEARCH_TIME_NR, VCD_FUNCTION_OUT);
#if TEST_SYNCHRO_TIMING_PSS
@@ -749,6 +753,7 @@ int pss_synchro_nr(PHY_VARS_NR_UE *PHY_vars_UE, int is, int rate_change)
}
#endif
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PSS_SYNCHRO_NR, VCD_FUNCTION_OUT);
return synchro_position;
}
diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
index 351c4ea22a5126ef2e26dd447594210dd6f00d90..65bb2edaca82b274ac12949df3531980e2df0176 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
+++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.c
@@ -37,161 +37,25 @@
//#include "LAYER2/MAC/extern.h"
#include "PHY/NR_UE_TRANSPORT/pucch_nr.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
-
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
+#include <openair1/PHY/CODING/nrSmallBlock/nr_small_block_defs.h>
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "T.h"
+//#define NR_UNIT_TEST 1
#ifdef NR_UNIT_TEST
#define DEBUG_PUCCH_TX
#define DEBUG_NR_PUCCH_TX
#endif
-//#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2)
-
-void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping,
- uint32_t n_id,
- uint8_t n_hop,
- int nr_tti_tx,
- uint8_t *u,
- uint8_t *v) {
- /*
- * Implements TS 38.211 subclause 6.3.2.2.1 Group and sequence hopping
- * The following variables are set by higher layers:
- * - PUCCH_GroupHopping:
- * - n_id: higher-layer parameter hoppingId
- * - n_hop: frequency hopping index
- * if intra-slot frequency hopping is disabled by the higher-layer parameter PUCCH-frequency-hopping
- * n_hop=0
- * if frequency hopping is enabled by the higher-layer parameter PUCCH-frequency-hopping
- * n_hop=0 for the first hop
- * n_hop=1 for the second hop
- */
- // depending on the value of the PUCCH_GroupHopping, we will obtain different values for u,v
- //pucch_GroupHopping_t PUCCH_GroupHopping = ue->pucch_config_common_nr->pucch_GroupHopping; // from higher layers FIXME!!!
- // n_id defined as per TS 38.211 subclause 6.3.2.2.1 (is given by the higher-layer parameter hoppingId)
- // it is hoppingId from PUCCH-ConfigCommon:
- // Cell-Specific scrambling ID for group hoppping and sequence hopping if enabled
- // Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2) BIT STRING (SIZE (10))
- //uint16_t n_id = ue->pucch_config_common_nr->hoppingId; // from higher layers FIXME!!!
-#ifdef DEBUG_NR_PUCCH_TX
- // initialization to be removed
- PUCCH_GroupHopping=neither;
- n_id=10;
- printf("\t\t [nr_group_sequence_hopping] initialization PUCCH_GroupHopping=%u, n_id=%u -> variable initializations TO BE REMOVED\n",PUCCH_GroupHopping,n_id);
-#endif
- uint8_t f_ss=0,f_gh=0;
- *u=0;
- *v=0;
- uint32_t c_init = 0;
- uint32_t x1,s; // TS 38.211 Subclause 5.2.1
- int l = 32, minShift = ((2*nr_tti_tx+n_hop)<<3);
- int tmpShift =0;
-#ifdef DEBUG_NR_PUCCH_TX
- printf("\t\t [nr_group_sequence_hopping] calculating u,v -> ");
-#endif
-
- if (PUCCH_GroupHopping == neither) { // PUCCH_GroupHopping 'neither'
- f_ss = n_id%30;
- }
-
- if (PUCCH_GroupHopping == enable) { // PUCCH_GroupHopping 'enabled'
- c_init = floor(n_id/30); // we initialize c_init to calculate u,v according to 6.3.2.2.1 of 38.211
- s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
- for (int m=0; m<8; m++) {
- while(minShift >= l) {
- s = lte_gold_generic(&x1, &c_init, 0);
- l = l+32;
- }
-
- tmpShift = (minShift&((1<<5)-1)); //minShift%32;
- f_gh = f_gh + ((1<<m)*((uint8_t)((s>>tmpShift)&1)));
- minShift ++;
- }
-
- f_gh = f_gh%30;
- f_ss = n_id%30;
- /* for (int m=0; m<8; m++){
- f_gh = f_gh + ((1<<m)*((uint8_t)((s>>(8*(2*nr_tti_tx+n_hop)+m))&1))); // Not sure we have to use nr_tti_tx FIXME!!!
- }
- f_gh = f_gh%30;
- f_ss = n_id%30;*/
- }
-
- if (PUCCH_GroupHopping == disable) { // PUCCH_GroupHopping 'disabled'
- c_init = (1<<5)*floor(n_id/30)+(n_id%30); // we initialize c_init to calculate u,v
- s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
- f_ss = n_id%30;
- l = 32, minShift = (2*nr_tti_tx+n_hop);
-
- while(minShift >= l) {
- s = lte_gold_generic(&x1, &c_init, 0);
- l = l+32;
- }
-
- tmpShift = (minShift&((1<<5)-1)); //minShift%32;
- *v = (uint8_t)((s>>tmpShift)&1);
- // *v = (uint8_t)((s>>(2*nr_tti_tx+n_hop))&1); // Not sure we have to use nr_tti_tx FIXME!!!
- }
- *u = (f_gh+f_ss)%30;
-#ifdef DEBUG_NR_PUCCH_TX
- printf("%d,%d\n",*u,*v);
-#endif
-}
-
-double nr_cyclic_shift_hopping(uint32_t n_id,
- uint8_t m0,
- uint8_t mcs,
- uint8_t lnormal,
- uint8_t lprime,
- int nr_tti_tx) {
- /*
- * Implements TS 38.211 subclause 6.3.2.2.2 Cyclic shift hopping
- * - n_id: higher-layer parameter hoppingId
- * - m0: provided by higher layer parameter PUCCH-F0-F1-initial-cyclic-shift of PUCCH-F0-resource-config
- * - mcs: mcs=0 except for PUCCH format 0 when it depends on information to be transmitted according to TS 38.213 subclause 9.2
- * - lnormal: lnormal is the OFDM symbol number in the PUCCH transmission where l=0 corresponds to the first OFDM symbol of the PUCCH transmission
- * - lprime: lprime is the index of the OFDM symbol in the slot that corresponds to the first OFDM symbol of the PUCCH transmission in the slot given by [5, TS 38.213]
- */
- // alpha_init initialized to 2*PI/12=0.5235987756
- double alpha = 0.5235987756;
- uint32_t c_init = n_id; // we initialize c_init again to calculate n_cs
-#ifdef DEBUG_NR_PUCCH_TX
- // initialization to be remo.ved
- c_init=10;
- printf("\t\t [nr_cyclic_shift_hopping] initialization c_init=%u -> variable initialization TO BE REMOVED\n",c_init);
-#endif
- uint32_t x1,s = lte_gold_generic(&x1, &c_init, 1); // TS 38.211 Subclause 5.2.1
- uint8_t n_cs=0;
- int l = 32, minShift = (14*8*nr_tti_tx )+ 8*(lnormal+lprime);
- int tmpShift =0;
-#ifdef DEBUG_NR_PUCCH_TX
- printf("\t\t [nr_cyclic_shift_hopping] calculating alpha (cyclic shift) using c_init=%u -> \n",c_init);
-#endif
-
- for (int m=0; m<8; m++) {
- while(minShift >= l) {
- s = lte_gold_generic(&x1, &c_init, 0);
- l = l+32;
- }
-
- tmpShift = (minShift&((1<<5)-1)); //minShift%32;
- minShift ++;
- n_cs = n_cs+((1<<m)*((uint8_t)((s>>tmpShift)&1)));
- // calculating n_cs (Not sure we have to use nr_tti_tx FIXME!!!)
- // n_cs = n_cs+((1<<m)*((uint8_t)((s>>((14*8*nr_tti_tx) + 8*(lnormal+lprime) + m))&1)));
- }
+//#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2)
- alpha = (alpha * (double)((m0+mcs+n_cs)%12));
-#ifdef DEBUG_NR_PUCCH_TX
- printf("n_cs=%d -> %lf\n",n_cs,alpha);
-#endif
- return(alpha);
-}
void nr_generate_pucch0(PHY_VARS_NR_UE *ue,
int32_t **txdataF,
NR_DL_FRAME_PARMS *frame_parms,
- PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
+ long pucch_GroupHopping,
+ long hoppingId,
int16_t amp,
int nr_tti_tx,
uint8_t m0,
@@ -248,7 +112,7 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue,
for (int l=0; l<nrofSymbols; l++) {
// if frequency hopping is enabled n_hop = 1 for second hop. Not sure frequency hopping concerns format 0. FIXME!!!
// if ((PUCCH_Frequency_Hopping == 1)&&(l == (nrofSymbols-1))) n_hop = 1;
- nr_group_sequence_hopping(ue->pucch_config_common_nr->pucch_GroupHopping,ue->pucch_config_common_nr->hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value
+ nr_group_sequence_hopping(pucch_GroupHopping,hoppingId,n_hop,nr_tti_tx,&u,&v); // calculating u and v value
alpha = nr_cyclic_shift_hopping(ue->pucch_config_common_nr->hoppingId,m0,mcs,l,startingSymbolIndex,nr_tti_tx);
#ifdef DEBUG_NR_PUCCH_TX
printf("\t [nr_generate_pucch0] sequence generation \tu=%d \tv=%d \talpha=%lf \t(for symbol l=%d)\n",u,v,alpha,l);
@@ -271,46 +135,31 @@ void nr_generate_pucch0(PHY_VARS_NR_UE *ue,
*/
//int32_t *txptr;
uint32_t re_offset=0;
+ uint8_t l2;
for (int l=0; l<nrofSymbols; l++) {
- if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
-
- if ((startingPRB >= (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is upper band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1)));
- }
-
- if ((startingPRB < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is lower band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
-
- if ((startingPRB > (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB is upper band
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*(startingPRB-(frame_parms->N_RB_DL>>1))) + 6;
- }
-
- if ((startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) { // if number RBs in bandwidth is odd and current PRB contains DC
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size) + (12*startingPRB) + frame_parms->first_carrier_offset;
- }
+ l2=l+startingSymbolIndex;
+ re_offset = (12*startingPRB) + frame_parms->first_carrier_offset;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
//txptr = &txdataF[0][re_offset];
for (int n=0; n<12; n++) {
- if ((n==6) && (startingPRB == (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 1)) {
- // if number RBs in bandwidth is odd and current PRB contains DC, we need to recalculate the offset when n=6 (for second half PRB)
- re_offset = ((l+startingSymbolIndex)*frame_parms->ofdm_symbol_size);
- }
- ((int16_t *)&txdataF[0][re_offset])[0] = (int16_t)(((int32_t)(amp) * x_n_re[(12*l)+n])>>15);
- ((int16_t *)&txdataF[0][re_offset])[1] = (int16_t)(((int32_t)(amp) * x_n_im[(12*l)+n])>>15);
+ ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[0] = (int16_t)(((int32_t)(amp) * x_n_re[(12*l)+n])>>15);
+ ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[1] = (int16_t)(((int32_t)(amp) * x_n_im[(12*l)+n])>>15);
//((int16_t *)txptr[0][re_offset])[0] = (int16_t)((int32_t)amp * x_n_re[(12*l)+n])>>15;
//((int16_t *)txptr[0][re_offset])[1] = (int16_t)((int32_t)amp * x_n_im[(12*l)+n])>>15;
//txptr[re_offset] = (x_n_re[(12*l)+n]<<16) + x_n_im[(12*l)+n];
#ifdef DEBUG_NR_PUCCH_TX
printf("\t [nr_generate_pucch0] mapping to RE \t amp=%d \tofdm_symbol_size=%d \tN_RB_DL=%d \tfirst_carrier_offset=%d \ttxptr(%u)=(x_n(l=%d,n=%d)=(%d,%d))\n",
- amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,re_offset,
- l,n,((int16_t *)&txdataF[0][re_offset])[0],((int16_t *)&txdataF[0][re_offset])[1]);
+ amp,frame_parms->ofdm_symbol_size,frame_parms->N_RB_DL,frame_parms->first_carrier_offset,(l2*frame_parms->ofdm_symbol_size) + re_offset,
+ l2,n,((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[0],
+ ((int16_t *)&txdataF[0][(l2*frame_parms->ofdm_symbol_size) + re_offset])[1]);
#endif
re_offset++;
+ if (re_offset>= frame_parms->ofdm_symbol_size)
+ re_offset-=frame_parms->ofdm_symbol_size;
}
}
}
@@ -951,27 +800,47 @@ void nr_generate_pucch1_old(PHY_VARS_NR_UE *ue,
}
#endif //0
-inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) __attribute__((always_inline));
-inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint32_t B,uint8_t *btilde) {
+inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) __attribute__((always_inline));
+inline void nr_pucch2_3_4_scrambling(uint16_t M_bit,uint16_t rnti,uint16_t n_id,uint64_t *B64,uint8_t *btilde) {
uint32_t x1, x2, s=0;
int i;
uint8_t c;
// c_init=nRNTI*2^15+n_id according to TS 38.211 Subclause 6.3.2.6.1
//x2 = (rnti) + ((uint32_t)(1+nr_tti_tx)<<16)*(1+(fp->Nid_cell<<1));
x2 = ((rnti)<<15)+n_id;
- s = lte_gold_generic(&x1, &x2, 1);
#ifdef DEBUG_NR_PUCCH_TX
- printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x\n",s);
-#endif
-
- for (i=0; i<M_bit; i++) {
- c = (uint8_t)((s>>i)&1);
- btilde[i] = (((B>>i)&1) ^ c);
-#ifdef DEBUG_NR_PUCCH_TX
- //printf("\t\t\t btilde[%d]=%lx from scrambled bit %d\n",i,btilde[i],((B>>i)&1));
+ printf("\t\t [nr_pucch2_3_4_scrambling] gold sequence s=%x, M_bit %d\n",s,M_bit);
+#endif
+
+ uint8_t *btildep=btilde;
+ int M_bit2=M_bit > 31 ? 32 : (M_bit&31), M_bit3=M_bit;
+ uint32_t B;
+ for (int iprime=0;iprime<=(M_bit>>5);iprime++,btildep+=32) {
+ s = lte_gold_generic(&x1, &x2, (iprime==0) ? 1 : 0);
+ B=((uint32_t*)B64)[iprime];
+ for (int n=0;n<M_bit2;n+=8)
+ LOG_D(PHY,"PUCCH2 encoded %d : %d,%d,%d,%d,%d,%d,%d,%d\n",n,
+ (B>>n)&1,
+ (B>>(n+1))&1,
+ (B>>(n+2))&1,
+ (B>>(n+3))&1,
+ (B>>(n+4))&1,
+ (B>>(n+5))&1,
+ (B>>(n+6))&1,
+ (B>>(n+7))&1
+ );
+ for (i=0; i<M_bit2; i++) {
+ c = (uint8_t)((s>>i)&1);
+ btildep[i] = (((B>>i)&1) ^ c);
+#ifdef DEBUG_NR_PUCCH_TX
+ printf("\t\t\t btilde[%d]=%lx from unscrambled bit %d and scrambling %d (%x)\n",i+(iprime<<5),btilde[i],((B>>i)&1),c,s>>i);
#endif
+ }
+ M_bit3-=32;
+ M_bit2=M_bit3 > 31 ? 32 : (M_bit3&31);
}
+
#ifdef DEBUG_NR_PUCCH_TX
printf("\t\t [nr_pucch2_3_4_scrambling] scrambling M_bit=%d bits\n", M_bit);
#endif
@@ -1059,29 +928,23 @@ void nr_uci_encoding(uint64_t payload,
if (A<=11) {
// procedure in subclause 6.3.1.2.2 (UCI encoded by channel coding of small block lengths -> subclause 6.3.1.3.2)
// CRC bits are not attached, and coding small block lengths (subclause 5.3.3)
+ b[0] = encodeSmallBlock((uint16_t*)&payload,A);
} else if (A>=12) {
- // procedure in subclause 6.3.1.2.1 (UCI encoded by Polar code -> subclause 6.3.1.3.1)
- /*if ((A>=360 && E>=1088)||(A>=1013)) {
- I_seg = 1;
- } else {
- I_seg = 0;
- }*/
-
- /*if (A>=20) {
- // parity bits (subclause 5.2.1) computed by setting L=11 and using generator polynomial gCRC11(D) (subclause 5.1)
- L=11;
- } else if (A<=19) {
- // parity bits (subclause 5.2.1) computed by setting L=6 and using generator polynomial gCRC6(D) (subclause 5.1)
- L=6;
- }*/
-
- // code block segmentation and CRC attachment is performed according to subclause 5.2.1
- // polar coding subclause 5.3.1
+ AssertFatal(A<65,"Polar encoding not supported yet for UCI with more than 64 bits\n");
+ t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_UCI_PUCCH_MESSAGE_TYPE,
+ A,
+ nrofPRB,
+ 1,
+ NULL);
+ polar_encoder_fast(&payload, b, 0,0,currentPtr);
}
+
}
//#if 0
void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
uint16_t crnti,
+ uint32_t dmrs_scrambling_id,
+ uint32_t data_scrambling_id,
int32_t **txdataF,
NR_DL_FRAME_PARMS *frame_parms,
PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
@@ -1097,10 +960,10 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
printf("\t [nr_generate_pucch2] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n",nr_tti_tx, payload, nr_bit);
#endif
// b is the block of bits transmitted on the physical channel after payload coding
- uint64_t b;
+ uint64_t b[16]; // limit to 1024-bit encoded length
// M_bit is the number of bits of block b (payload after encoding)
uint16_t M_bit;
- nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,&b,&M_bit);
+ nr_uci_encoding(payload,nr_bit,pucch_format2_nr,0,nrofSymbols,nrofPRB,1,0,0,&b[0],&M_bit);
/*
* Implementing TS 38.211
* Subclauses 6.3.2.5.1 Scrambling (PUCCH format 2)
@@ -1115,14 +978,14 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
*/
uint8_t *btilde = malloc(sizeof(int8_t)*M_bit);
// rnti is given by the C-RNTI
- uint16_t rnti=crnti, n_id=0;
+ uint16_t rnti=crnti;
#ifdef DEBUG_NR_PUCCH_TX
printf("\t [nr_generate_pucch2] rnti = %d ,\n",rnti);
#endif
/*
* Implementing TS 38.211 Subclause 6.3.2.5.1 scrambling format 2
*/
- nr_pucch2_3_4_scrambling(M_bit,rnti,n_id,b,btilde);
+ nr_pucch2_3_4_scrambling(M_bit,rnti,data_scrambling_id,&b[0],btilde);
/*
* Implementing TS 38.211 Subclause 6.3.2.5.2 modulation format 2
* btilde shall be modulated as described in subclause 5.1 using QPSK
@@ -1170,10 +1033,10 @@ void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
int m=0;
for (int l=0; l<nrofSymbols; l++) {
- x2 = (((1<<17)*((14*nr_tti_tx) + (l+startingSymbolIndex) + 1)*((2*n_id) + 1)) + (2*n_id))%(1U<<31); // c_init calculation according to TS38.211 subclause
+ x2 = (((1<<17)*((14*nr_tti_tx) + (l+startingSymbolIndex) + 1)*((2*dmrs_scrambling_id) + 1)) + (2*dmrs_scrambling_id))%(1U<<31); // c_init calculation according to TS38.211 subclause
+
s = lte_gold_generic(&x1, &x2, 1);
m = 0;
-
for (int rb=0; rb<nrofPRB; rb++) {
//startingPRB = startingPRB + rb;
if (((rb+startingPRB) < (frame_parms->N_RB_DL>>1)) && ((frame_parms->N_RB_DL & 1) == 0)) { // if number RBs in bandwidth is even and current PRB is lower band
@@ -1266,7 +1129,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
printf("\t [nr_generate_pucch3_4] start function at slot(nr_tti_tx)=%d with payload=%lu and nr_bit=%d\n", nr_tti_tx, payload, nr_bit);
#endif
// b is the block of bits transmitted on the physical channel after payload coding
- uint64_t b;
+ uint64_t b[16];
// M_bit is the number of bits of block b (payload after encoding)
uint16_t M_bit;
// parameter PUCCH-F4-preDFT-OCC-length set of {2,4} -> to use table -1 or -2
@@ -1291,7 +1154,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
//nrofPRB = 2; // only for test purposes
if (fmt == pucch_format4_nr) nrofPRB = 1;
- nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,&b,&M_bit);
+ nr_uci_encoding(payload,nr_bit,fmt,is_pi_over_2_bpsk_enabled,nrofSymbols,nrofPRB,n_SF_PUCCH_s,intraSlotFrequencyHopping,add_dmrs,&b[0],&M_bit);
/*
* Implementing TS 38.211
* Subclauses 6.3.2.6.1 Scrambling (PUCCH formats 3 and 4)
@@ -1313,7 +1176,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
/*
* Implementing TS 38.211 Subclause 6.3.2.6.1 scrambling formats 3 and 4
*/
- nr_pucch2_3_4_scrambling(M_bit,rnti,n_id,b,btilde);
+ nr_pucch2_3_4_scrambling(M_bit,rnti,n_id,&b[0],btilde);
/*
* Implementing TS 38.211 Subclause 6.3.2.6.2 modulation formats 3 and 4
*
diff --git a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
index e8cd147526be502ba16ab3e0e88e9c490e1c43b9..0e81045d660996f6a80938d81d01cde5a285e2fb 100644
--- a/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
+++ b/openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h
@@ -20,7 +20,7 @@
*/
/*! \file PHY/NR_UE_TRANSPORT/pucch_nr.c
-* \brief Top-level routines for generating and decoding the PUCCH physical channel
+* \brief Top-level routines for generating the PUCCH physical channel
* \author A. Mico Pereperez
* \date 2018
* \version 0.1
@@ -29,6 +29,9 @@
* \note
* \warning
*/
+#ifndef __PUCCH_NR__H__
+#define __PUCCH_NR__H__
+
//#include "PHY/defs.h"
#include "PHY/impl_defs_nr.h"
#include "PHY/defs_nr_common.h"
@@ -42,50 +45,12 @@
#include "T.h"
#define ONE_OVER_SQRT2 23170 // 32767/sqrt(2) = 23170 (ONE_OVER_SQRT2)
-void nr_decode_pucch1( int32_t **rxdataF,
- pucch_GroupHopping_t pucch_GroupHopping,
- uint32_t n_id, // hoppingID higher layer parameter
- uint64_t *payload,
- NR_DL_FRAME_PARMS *frame_parms,
- int16_t amp,
- int nr_tti_tx,
- uint8_t m0,
- uint8_t nrofSymbols,
- uint8_t startingSymbolIndex,
- uint16_t startingPRB,
- uint16_t startingPRB_intraSlotHopping,
- uint8_t timeDomainOCC,
- uint8_t nr_bit);
-
-void nr_decode_pucch0( int32_t **rxdataF,
- pucch_GroupHopping_t PUCCH_GroupHopping,
- uint32_t n_id, //PHY_VARS_gNB *gNB, generally rxdataf is in gNB->common_vars
- uint64_t *payload,
- NR_DL_FRAME_PARMS *frame_parms,
- int16_t amp,
- int nr_tti_tx,
- uint8_t m0, // should come from resource set
- uint8_t nrofSymbols, // should come from resource set
- uint8_t startingSymbolIndex, // should come from resource set
- uint16_t startingPRB, // should come from resource set
- uint8_t nr_bit);
-void nr_group_sequence_hopping (pucch_GroupHopping_t PUCCH_GroupHopping,
- uint32_t n_id,
- uint8_t n_hop,
- int nr_tti_tx,
- uint8_t *u,
- uint8_t *v);
-double nr_cyclic_shift_hopping(uint32_t n_id,
- uint8_t m0,
- uint8_t mcs,
- uint8_t lnormal,
- uint8_t lprime,
- int nr_tti_tx);
void nr_generate_pucch0(PHY_VARS_NR_UE *ue,
int32_t **txdataF,
NR_DL_FRAME_PARMS *frame_parms,
- PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
+ long pucch_GroupHopping,
+ long hoppingId,
int16_t amp,
int nr_tti_tx,
uint8_t m0,
@@ -109,6 +74,8 @@ void nr_generate_pucch1(PHY_VARS_NR_UE *ue,
uint8_t nr_bit);
void nr_generate_pucch2(PHY_VARS_NR_UE *ue,
uint16_t crnti,
+ uint32_t dmrs_scrambling_id,
+ uint32_t data_scrambling_id,
int32_t **txdataF,
NR_DL_FRAME_PARMS *frame_parms,
PUCCH_CONFIG_DEDICATED *pucch_config_dedicated,
@@ -139,8 +106,8 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
uint8_t occ_index_format4);
// tables for mcs values for different payloads
- static const uint8_t table1_mcs[]={0,3,6,9};
- static const uint8_t table2_mcs[]={0,1,3,4,6,7,9,10};
+ static const uint8_t table1_mcs[]={0,6,3,9};
+ static const uint8_t table2_mcs[]={0,3,9,6,1,4,10,7};
/*
* The following tables implement TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (rows->u {0,1,..,29} / columns->n {0,1,...,M_ZC-1)
@@ -454,3 +421,4 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
73, 79, 83, 89, 97, 101,103,107,109,113,
127,131,137,139,149,151,157,163,167,173,
179,181,191,193,197,199};
+#endif
diff --git a/openair1/PHY/TOOLS/Makefile b/openair1/PHY/TOOLS/Makefile
index c71717dc8787cb6cfd29671228591d494af582ae..a59700bb7c058bc159cfda8befbb62e3c9370c9f 100644
--- a/openair1/PHY/TOOLS/Makefile
+++ b/openair1/PHY/TOOLS/Makefile
@@ -1,16 +1,16 @@
-lte_dfts_sse4: lte_dfts.c
- gcc-7 -O3 -std=gnu99 -msse4.1 -o lte_dfts_sse4 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
+oai_dfts_sse4: oai_dfts.c
+ gcc-7 -O3 -std=gnu99 -msse4.1 -o oai_dfts_sse4 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
-lte_dfts_avx2: lte_dfts.c
- gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o lte_dfts_avx2 lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
+oai_dfts_avx2: oai_dfts.c
+ gcc -O2 -std=gnu99 -mavx2 -g -ggdb -o oai_dfts_avx2 oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
-lte_dfts_avx2.s: lte_dfts.c
- gcc -O2 -std=gnu99 -mavx2 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
+oai_dfts_avx2.s: oai_dfts.c
+ gcc -O2 -std=gnu99 -mavx2 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
-lte_dfts_sse4.s: lte_dfts.c
- gcc -O2 -std=gnu99 -msse4.1 -S lte_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
+oai_dfts_sse4.s: oai_dfts.c
+ gcc -O2 -std=gnu99 -msse4.1 -S oai_dfts.c time_meas.c ../../SIMULATION/TOOLS/taus.c $$OPENAIR_HOME/common/utils/backtrace.c -I$$OPENAIR_HOME -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR_TARGETS/COMMON -I$$OPENAIR_TARGETS/ARCH/COMMON -I$$OPENAIR2_DIR -I$$OPENAIR2_DIR/COMMON -I$$OPENAIR_HOME/common/utils -I$$OPENAIR_HOME/common/utils/T -I$$OPENAIR_HOME/common/utils/msc -I$$OPENAIR_HOME/nfapi/open-nFAPI/nfapi/public_inc -DMR_MAIN -DNB_ANTENNAS_RX=1 -lm -lpthread # -DD256STATS #-DD64STATS
-dft_cycles_avx2: lte_dfts_avx2
- ./lte_dfts_avx2 | egrep cycles
+dft_cycles_avx2: oai_dfts_avx2
+ ./oai_dfts_avx2 | egrep cycles
diff --git a/openair1/PHY/TOOLS/nr_phy_scope.c b/openair1/PHY/TOOLS/nr_phy_scope.c
index 4682a890299786dd491c30e3e9500a9749468b45..44d7b93ae209ae8a27e26207355097b9268dbe29 100644
--- a/openair1/PHY/TOOLS/nr_phy_scope.c
+++ b/openair1/PHY/TOOLS/nr_phy_scope.c
@@ -9,6 +9,8 @@
*
* http://www.openairinterface.org/?page_id=698
*
+ * Author and copyright: Laurent Thomas, open-cells.com
+ *
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -24,8 +26,11 @@
#include <stdlib.h>
#include "nr_phy_scope.h"
#include "executables/nr-softmodem-common.h"
+#include "executables/softmodem-common.h"
+#include <forms.h>
#define TPUT_WINDOW_LENGTH 100
+#define localBuff(NaMe,SiZe) float NaMe[SiZe]; memset(NaMe,0,sizeof(NaMe));
int otg_enabled;
FL_COLOR rx_antenna_colors[4] = {FL_RED,FL_BLUE,FL_GREEN,FL_YELLOW};
@@ -36,24 +41,47 @@ float tput_time_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}};
float tput_ue[NUMBER_OF_UE_MAX][TPUT_WINDOW_LENGTH] = {{0}};
float tput_ue_max[NUMBER_OF_UE_MAX] = {0};
+typedef struct {
+ int16_t r;
+ int16_t i;
+} scopeSample_t;
+#define SquaredNorm(VaR) ((VaR).r*(VaR).r+(VaR).i*(VaR).i)
+
+typedef struct OAIgraph {
+ FL_OBJECT *graph;
+ float maxX;
+ float maxY;
+ float minX;
+ float minY;
+ int iteration;
+ void (*gNBfunct) (struct OAIgraph *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id);
+ void (*nrUEfunct)(struct OAIgraph *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id);
+} OAIgraph_t;
+
+/* Forms and Objects */
+typedef struct {
+ FL_FORM *phy_scope;
+ OAIgraph_t graph[20];
+ FL_OBJECT *button_0;
+} OAI_phy_scope_t;
-static void ia_receiver_on_off( FL_OBJECT *button, long arg)
-{
+typedef struct {
+ FL_FORM *stats_form;
+ void *vdata;
+ char *cdata;
+ long ldata;
+ FL_OBJECT *stats_text;
+ FL_OBJECT *stats_button;
+} FD_stats_form;
- if (fl_get_button(button)) {
- fl_set_object_label(button, "IA Receiver ON");
- // PHY_vars_UE_g[0][0]->use_ia_receiver = 1;
- fl_set_object_color(button, FL_GREEN, FL_GREEN);
- } else {
- fl_set_object_label(button, "IA Receiver OFF");
- // PHY_vars_UE_g[0][0]->use_ia_receiver = 0;
- fl_set_object_color(button, FL_RED, FL_RED);
- }
+static void drawsymbol(FL_OBJECT *obj, int id,
+ FL_POINT *p, int n, int w, int h) {
+ fl_points( p, n, FL_YELLOW);
}
-static void dl_traffic_on_off( FL_OBJECT *button, long arg)
-{
-
+// button callback example
+#if 0
+static void dl_traffic_on_off( FL_OBJECT *button, long arg) {
if (fl_get_button(button)) {
fl_set_object_label(button, "DL Traffic ON");
otg_enabled = 1;
@@ -64,765 +92,544 @@ static void dl_traffic_on_off( FL_OBJECT *button, long arg)
fl_set_object_color(button, FL_RED, FL_RED);
}
}
+#endif
-FD_phy_scope_gnb *create_phy_scope_gnb( void )
-{
-
- FL_OBJECT *obj;
- FD_phy_scope_gnb *fdui = fl_malloc( sizeof *fdui );
-
- // Define form
- fdui->phy_scope_gnb = fl_bgn_form( FL_NO_BOX, 800, 800 );
-
- // This the whole UI box
- obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" );
- fl_set_object_color( obj, FL_BLACK, FL_BLACK );
-
- // Received signal
- fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" );
- fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color
- fl_set_xyplot_ybounds(fdui->rxsig_t,10,70);
-
- // Time-domain channel response
- fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "SRS Frequency Response (samples, abs)" );
- fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color
-
- // Frequency-domain channel response
- fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" );
- fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color
- fl_set_xyplot_ybounds( fdui->chest_f,30,70);
+static FL_OBJECT *commonGraph( int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) {
+ FL_OBJECT *graph;
+ graph=fl_add_xyplot(type, x, y, w, h, label);
+ fl_set_object_lcolor(graph, FL_WHITE ); // Label color
+ fl_set_object_color(graph, FL_BLACK, pointColor);
+ fl_set_xyplot_symbol(graph, -1, drawsymbol);
+ return graph;
+}
- // LLR of PUSCH
- fdui->pusch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 200, "PUSCH Log-Likelihood Ratios (LLR, mag)" );
- fl_set_object_boxtype( fdui->pusch_llr, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pusch_llr, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pusch_llr, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pusch_llr,2);
+static OAIgraph_t gNBcommonGraph( void (*funct) (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int UE_id),
+ int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) {
+ OAIgraph_t graph;
+ graph.graph=commonGraph(type, x, y, w, h, label, pointColor);
+ graph.gNBfunct=funct;
+ graph.nrUEfunct=NULL;
+ graph.maxX=0;
+ graph.maxY=0;
+ graph.minX=0;
+ graph.minY=0;
+ return graph;
+}
- // I/Q PUSCH comp
- fdui->pusch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 200, "PUSCH I/Q of MF Output" );
- fl_set_object_boxtype( fdui->pusch_comp, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pusch_comp, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pusch_comp, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pusch_comp,2);
- fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR);
+static OAIgraph_t nrUEcommonGraph( void (*funct) (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id),
+ int type, FL_Coord x, FL_Coord y, FL_Coord w, FL_Coord h, const char *label, FL_COLOR pointColor) {
+ OAIgraph_t graph;
+ graph.graph=commonGraph(type, x, y, w, h, label, pointColor);
+ graph.gNBfunct=NULL;
+ graph.nrUEfunct=funct;
+ graph.maxX=0;
+ graph.maxY=0;
+ graph.minX=0;
+ graph.minY=0;
+ return graph;
+}
- // I/Q PUCCH comp (format 1)
- fdui->pucch_comp1 = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 480, 240, 100, "PUCCH1 Energy (SR)" );
- fl_set_object_boxtype( fdui->pucch_comp1, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pucch_comp1, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pucch_comp1, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pucch_comp1,2);
- // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR);
+static void setRange(OAIgraph_t *graph, float minX, float maxX, float minY, float maxY) {
+ if ( maxX > graph->maxX || maxY > graph->maxY || minX < graph->minX || minY < graph->minY ) {
+ graph->maxX=max(graph->maxX,maxX);
+ graph->minX=min(graph->minX,minX);
+ graph->maxY=max(graph->maxY,maxY);
+ graph->minY=min(graph->minY,minY);
+ fl_set_xyplot_ybounds(graph->graph, graph->minY, graph->maxY);
+ fl_set_xyplot_xbounds(graph->graph, graph->minX, graph->maxX);
+ }
+}
- // I/Q PUCCH comp (fromat 1a/b)
- fdui->pucch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 600, 240, 100, "PUCCH I/Q of MF Output" );
- fl_set_object_boxtype( fdui->pucch_comp, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pucch_comp, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pucch_comp, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pucch_comp,2);
- // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR);
+static void oai_xygraph(OAIgraph_t *graph, float *x, float *y, int len, int layer, int NoAutoScale) {
+ if (layer==0)
+ fl_set_xyplot_data(graph->graph,x,y,len,"","","");
+ else
+ fl_add_xyplot_overlay(graph->graph,layer,x,y,len,rx_antenna_colors[layer]);
- // Throughput on PUSCH
- fdui->pusch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 480, 500, 100, "PUSCH Throughput [frame]/[kbit/s]" );
- fl_set_object_boxtype( fdui->pusch_tput, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pusch_tput, FL_BLACK, FL_WHITE );
- fl_set_object_lcolor( fdui->pusch_tput, FL_WHITE ); // Label color
+ if ( NoAutoScale && graph->iteration%NoAutoScale == 0) {
+ float maxX=0, maxY=0, minX=0, minY=0;
- // Generic eNB Button
- fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 20, 600, 240, 40, "" );
- fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER );
- fl_set_button(fdui->button_0,0);
- otg_enabled = 0;
- fl_set_object_label(fdui->button_0, "DL Traffic OFF");
- fl_set_object_color(fdui->button_0, FL_RED, FL_RED);
- fl_set_object_callback(fdui->button_0, dl_traffic_on_off, 0 );
+ for (int k=0; k<len; k++) {
+ maxX=max(maxX,x[k]);
+ minX=min(minX,x[k]);
+ maxY=max(maxY,y[k]);
+ minY=min(minY,y[k]);
+ }
- fl_end_form( );
- fdui->phy_scope_gnb->fdui = fdui;
+ setRange(graph,minX,maxX, minY, maxY);
+ }
- return fdui;
+ graph->iteration++;
}
-void phy_scope_gNB(FD_phy_scope_gnb *form,
- PHY_VARS_gNB *phy_vars_gnb,
- RU_t *phy_vars_ru,
- int UE_id)
-{
- int i, arx; //int i,i2,arx,atx,ind,k;
- NR_DL_FRAME_PARMS *frame_parms = &phy_vars_gnb->frame_parms;
- int nsymb_ce = 12*frame_parms->N_RB_UL*frame_parms->symbols_per_tti;
- uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx;
- uint8_t nb_antennas_tx = 1; // frame_parms->nb_antennas_tx; // in LTE Rel. 8 and 9 only a single transmit antenna is assumed at the UE
- int16_t **rxsig_t, **rxsig_f;
- // int16_t **chest_t=NULL;
- // int16_t **chest_f=NULL;
- // int16_t *pusch_llr=NULL;
- // int32_t *pusch_comp=NULL;
- // int32_t *pucch1_comp=NULL;
- // int32_t *pucch1_thres=NULL;
- // int32_t *pucch1ab_comp=NULL;
- // float Re,Im,ymax;
- float *llr, *bit;
- // float I[nsymb_ce*2], Q[nsymb_ce*2];
- // float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240];
- float *rxsig_t_dB[nb_antennas_rx];
- float *rxsig_f_dB[nb_antennas_rx];
- float time[frame_parms->samples_per_frame];
- // float freq[nsymb_ce*nb_antennas_rx*nb_antennas_tx];
- // uint32_t total_dlsch_bitrate = phy_vars_gnb->total_dlsch_bitrate;
- int coded_bits_per_codeword = 0;
- // uint8_t harq_pid; // in TDD config 3 it is sf-2, i.e., can be 0,1,2
- int Qm = 2;
-
- /*
- if (!RC.nrmac[0]->UE_info.active[UE_id])
- return;
-
- // choose max MCS to compute coded_bits_per_codeword
- if (phy_vars_gnb->ulsch[UE_id][0]!=NULL) {
- for (harq_pid=0; harq_pid<3; harq_pid++) {
- //Qm = cmax(phy_vars_gnb->ulsch[UE_id][0]->harq_processes->Qm,Qm);
- }
- }
- */
- coded_bits_per_codeword = frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti;
+static void genericLogPowerPerAntena(OAIgraph_t *graph, const int nb_ant, const scopeSample_t **data, const int len) {
+ float *values=malloc(len*sizeof(*values));
+ float *time=malloc(len*sizeof(*time));
- for (arx=0; arx<nb_antennas_rx; arx++) {
- rxsig_t_dB[arx] = (float*) calloc(frame_parms->samples_per_frame,sizeof(float));
- rxsig_f_dB[arx] = (float*) calloc(frame_parms->samples_per_slot_wCP,sizeof(float));
- }
- llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero
- bit = malloc(coded_bits_per_codeword*sizeof(float));
-
- rxsig_t = (int16_t**) phy_vars_ru->common.rxdata;
- rxsig_f = (int16_t**) phy_vars_ru->common.rxdataF;
- //chest_t = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates_time[eNB_id];
- /* chest_t = (int16_t**) phy_vars_gnb->srs_vars[UE_id].srs_ch_estimates;
- chest_f = (int16_t**) phy_vars_gnb->pusch_vars[UE_id]->drs_ch_estimates;
- pusch_llr = (int16_t*) phy_vars_gnb->pusch_vars[UE_id]->llr;
- pusch_comp = (int32_t*) phy_vars_gnb->pusch_vars[UE_id]->rxdataF_comp;
- pucch1_comp = (int32_t*) phy_vars_gnb->pucch1_stats[UE_id];
- pucch1_thres = (int32_t*) phy_vars_gnb->pucch1_stats_thres[UE_id];
- pucch1ab_comp = (int32_t*) phy_vars_gnb->pucch1ab_stats[UE_id];
- */
+ for (int ant=0; ant<nb_ant; ant++) {
+ if (data[ant] != NULL) {
+ for (int i=0; i<len; i+=8) {
+ float *vals=values+i;
+ float *tim=time+i;
+ const scopeSample_t *in=&(data[ant][i]);
- // Received signal in time domain of receive antenna 0
- if (rxsig_t != NULL) {
- if (rxsig_t[0] != NULL) {
- for (i=0; i<frame_parms->samples_per_frame; i++) {
- rxsig_t_dB[0][i] = 10*log10(1.0+(float) ((rxsig_t[0][2*i])*(rxsig_t[0][2*i])+(rxsig_t[0][2*i+1])*(rxsig_t[0][2*i+1])));
- time[i] = (float) i;
+ for (int k=0; k<8; k++ ) {
+ vals[k] = 10*log10(1.0+SquaredNorm(in[k]));
+ tim[k] = i+k;
+ }
}
- fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],frame_parms->samples_per_frame,"","","");
+ oai_xygraph(graph,time,values, len, ant, 10);
}
+ }
- for (arx=1; arx<nb_antennas_rx; arx++) {
- if (rxsig_t[arx] != NULL) {
- for (i=0; i<frame_parms->samples_per_frame; i++) {
- rxsig_t_dB[arx][i] = 10*log10(1.0+(float) ((rxsig_t[arx][2*i])*(rxsig_t[arx][2*i])+(rxsig_t[arx][2*i+1])*(rxsig_t[arx][2*i+1])));
- }
+ free(values);
+ free(time);
+}
- fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],frame_parms->samples_per_frame,rx_antenna_colors[arx]);
- }
- }
- }
+static void genericPowerPerAntena(OAIgraph_t *graph, const int nb_ant, const scopeSample_t **data, const int len) {
+ float values[len];
+ float time[len];
- /*
- // Channel Impulse Response
- if (chest_t != NULL) {
- ymax = 0;
-
- if (chest_t[0] !=NULL) {
- for (i=0; i<(frame_parms->ofdm_symbol_size); i++) {
- //i2 = (i+(frame_parms->ofdm_symbol_size>>1))%frame_parms->ofdm_symbol_size;
- i2=i;
- //time2[i] = (float)(i-(frame_parms->ofdm_symbol_size>>1));
- time2[i] = (float)i;
- chest_t_abs[0][i] = 10*log10((float) (1+chest_t[0][2*i2]*chest_t[0][2*i2]+chest_t[0][2*i2+1]*chest_t[0][2*i2+1]));
-
- if (chest_t_abs[0][i] > ymax)
- ymax = chest_t_abs[0][i];
+ for (int ant=0; ant<nb_ant; ant++) {
+ if (data[ant] != NULL) {
+ for (int i=0; i<len; i++) {
+ values[i] = SquaredNorm(data[ant][i]);
+ time[i] = i;
}
- fl_set_xyplot_data(form->chest_t,time2,chest_t_abs[0],(frame_parms->ofdm_symbol_size),"","","");
+ oai_xygraph(graph,time,values, len, ant, 10);
}
+ }
+}
- for (arx=1; arx<nb_antennas_rx; arx++) {
- if (chest_t[arx] !=NULL) {
- for (i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) {
- chest_t_abs[arx][i] = 10*log10((float) (1+chest_t[arx][2*i]*chest_t[arx][2*i]+chest_t[arx][2*i+1]*chest_t[arx][2*i+1]));
+static void timeSignal (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, const int nb_UEs) {
+ // Received signal in time domain of receive antenna 0
+ if (!phy_vars_ru->common.rxdata)
+ return;
- if (chest_t_abs[arx][i] > ymax)
- ymax = chest_t_abs[arx][i];
- }
+ NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms;
+ genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx,
+ (const scopeSample_t **)phy_vars_ru->common.rxdata,
+ frame_parms->samples_per_frame);
+}
- fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]);
- fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT);
- }
- }
+static void timeResponse (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
+ const int len=2*phy_vars_gnb->frame_parms.ofdm_symbol_size;
+ float values[len];
+ float time[len];
+ const int ant=0; // display antenna 0 for each UE
- // Avoid flickering effect
- // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax);
- fl_set_xyplot_ybounds(form->chest_t,0,ymax);
- }
- */
-
- // Channel Frequency Response
- if (rxsig_f != NULL) {
- if (rxsig_f[0] != NULL) {
- for (i=0; i<frame_parms->samples_per_slot_wCP; i++) {
- rxsig_f_dB[0][i] = 10*log10(1.0+(float) ((rxsig_f[0][2*i])*(rxsig_f[0][2*i])+(rxsig_f[0][2*i+1])*(rxsig_f[0][2*i+1])));
- time[i] = (float) i;
+ for (int ue=0; ue<nb_UEs; ue++) {
+ scopeSample_t *data= (scopeSample_t *)phy_vars_gnb->pusch_vars[ue]->ul_ch_estimates_time[ant];
+
+ if (data != NULL) {
+ for (int i=0; i<len; i++) {
+ values[i] = SquaredNorm(data[i]);
+ time[i] = i;
}
- fl_set_xyplot_data(form->chest_t,time,rxsig_f_dB[0],frame_parms->samples_per_slot_wCP,"","","");
+ oai_xygraph(graph,time,values, len, ue, 10);
}
}
-
- /*
-
- for (arx=0; arx<nb_antennas_rx; arx++) {
- if (chest_f[(atx<<1)+arx] != NULL) {
- for (k=0; k<nsymb_ce; k++) {
- freq[ind] = (float)ind;
- Re = (float)(chest_f[(atx<<1)+arx][(2*k)]);
- Im = (float)(chest_f[(atx<<1)+arx][(2*k)+1]);
+}
- chest_f_abs[ind] = (short)10*log10(1.0+((double)Re*Re + (double)Im*Im));
- ind++;
- }
- }
- }
- }
+static void frequencyResponse (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
+ NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms;
+ genericLogPowerPerAntena(graph, frame_parms->nb_antennas_rx,
+ (const scopeSample_t **)phy_vars_ru->common.rxdataF,
+ frame_parms->samples_per_slot_wCP);
+}
- // tx antenna 0
- fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce);
- fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,3);
- fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR);
- fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,nsymb_ce,"","","");
+static void puschLLR (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
+ //int Qm = 2;
+ int coded_bits_per_codeword =3*8*6144+12; // (8*((3*8*6144)+12)); // frame_parms->N_RB_UL*12*Qm*frame_parms->symbols_per_tti;
+ float llr[coded_bits_per_codeword];
+ float bit[coded_bits_per_codeword];
- for (arx=1; arx<nb_antennas_rx; arx++) {
- fl_add_xyplot_overlay(form->chest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
- }
+ for (int ue=0; ue<nb_UEs; ue++) {
+ int16_t *pusch_llr = (int16_t *)phy_vars_gnb->pusch_vars[ue]->llr;
- // other tx antennas
- if (nb_antennas_tx > 1) {
- if (nb_antennas_rx > 1) {
- for (atx=1; atx<nb_antennas_tx; atx++) {
- for (arx=0; arx<nb_antennas_rx; arx++) {
- fl_add_xyplot_overlay(form->chest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
- }
- }
- } else { // 1 rx antenna
- atx=1;
- arx=0;
- fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
+ if (pusch_llr) {
+ for (int i=0; i<coded_bits_per_codeword; i++) {
+ llr[i] = (float) pusch_llr[i];
+ bit[i] = (float) i;
}
+
+ oai_xygraph(graph,bit,llr,coded_bits_per_codeword,ue,10);
}
}
+}
- // PUSCH LLRs
- if (pusch_llr != NULL) {
- for (i=0; i<coded_bits_per_codeword; i++) {
- llr[i] = (float) pusch_llr[i];
- bit[i] = (float) i;
- }
+static void puschIQ (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
+ NR_DL_FRAME_PARMS *frame_parms=&phy_vars_gnb->frame_parms;
+ int sz=frame_parms->N_RB_UL*12*frame_parms->symbols_per_slot;
+ float I[sz], Q[sz];
- fl_set_xyplot_data(form->pusch_llr,bit,llr,coded_bits_per_codeword,"","","");
- }
+ for (int ue=0; ue<nb_UEs; ue++) {
+ scopeSample_t *pusch_comp = (scopeSample_t *) phy_vars_gnb->pusch_vars[ue]->rxdataF_comp[0];
- // PUSCH I/Q of MF Output
- if (pusch_comp!=NULL) {
- ind=0;
-
- for (k=0; k<frame_parms->symbols_per_tti; k++) {
- for (i=0; i<12*frame_parms->N_RB_UL; i++) {
- I[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i];
- Q[ind] = pusch_comp[(2*frame_parms->N_RB_UL*12*k)+2*i+1];
- ind++;
+ if (pusch_comp) {
+ for (int k=0; k<sz; k++ ) {
+ I[k] = pusch_comp[k].r;
+ Q[k] = pusch_comp[k].i;
}
- }
- fl_set_xyplot_data(form->pusch_comp,I,Q,ind,"","","");
+ oai_xygraph(graph,I,Q,sz,ue,10);
+ }
}
+}
+static void pucchEnergy (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
// PUSCH I/Q of MF Output
- if (pucch1ab_comp!=NULL) {
- for (ind=0; ind<10240; ind++) {
+ /*
+ int32_t *pucch1ab_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1ab_stats[UE_id];
+ int32_t *pucch1_comp = (int32_t *) NULL; //phy_vars_gnb->pucch1_stats[UE_id];
+ float I_pucch[10240],Q_pucch[10240],A_pucch[10240],B_pucch[10240],C_pucch[10240];
+ for (int ind=0; ind<10240; ind++) {
I_pucch[ind] = (float)pucch1ab_comp[2*(ind)];
Q_pucch[ind] = (float)pucch1ab_comp[2*(ind)+1];
A_pucch[ind] = pucch1_comp?(10*log10(pucch1_comp[ind])):0;
B_pucch[ind] = ind;
+ int32_t *pucch1_thres = (int32_t *) NULL; // phy_vars_gnb->pucch1_stats_thres[UE_id];
C_pucch[ind] = pucch1_thres?(float)pucch1_thres[ind]:0;
}
- fl_set_xyplot_data(form->pucch_comp,I_pucch,Q_pucch,10240,"","","");
- fl_set_xyplot_data(form->pucch_comp1,B_pucch,A_pucch,1024,"","","");
- fl_add_xyplot_overlay(form->pucch_comp1,1,B_pucch,C_pucch,1024,FL_RED);
- fl_set_xyplot_ybounds(form->pucch_comp,-5000,5000);
- fl_set_xyplot_xbounds(form->pucch_comp,-5000,5000);
- fl_set_xyplot_ybounds(form->pucch_comp1,0,80);
+ fl_set_xyplot_data(graph,I_pucch,Q_pucch,10240,"","","");
+ fl_set_xyplot_data(graph,B_pucch,A_pucch,1024,"","","");
+ fl_add_xyplot_overlay(graph,1,B_pucch,C_pucch,1024,FL_RED);
+ fl_set_xyplot_ybounds(graph,-5000,5000);
+ fl_set_xyplot_xbounds(graph,-5000,5000);
+ fl_set_xyplot_ybounds(graph,0,80);
}
+ */
+}
+static void pucchIQ (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
+}
+static void puschThroughtput (OAIgraph_t *graph, PHY_VARS_gNB *phy_vars_gnb, RU_t *phy_vars_ru, int nb_UEs) {
// PUSCH Throughput
+ /*
memmove( tput_time_enb[UE_id], &tput_time_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) );
memmove( tput_enb[UE_id], &tput_enb[UE_id][1], (TPUT_WINDOW_LENGTH-1)*sizeof(float) );
-
tput_time_enb[UE_id][TPUT_WINDOW_LENGTH-1] = (float) 0;
-// tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0;
-
- fl_set_xyplot_data(form->pusch_tput,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","","");
-
+ // tput_enb[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0;
+ fl_set_xyplot_data(graph,tput_time_enb[UE_id],tput_enb[UE_id],TPUT_WINDOW_LENGTH,"","","");
// fl_get_xyplot_ybounds(form->pusch_tput,&ymin,&ymax);
// fl_set_xyplot_ybounds(form->pusch_tput,0,ymax);
-
*/
-
- fl_check_forms();
-
- free(llr);
- free(bit);
}
-FD_phy_scope_nrue *create_phy_scope_nrue( void )
-{
-
+static OAI_phy_scope_t *create_phy_scope_gnb(void) {
FL_OBJECT *obj;
- FD_phy_scope_nrue *fdui = fl_malloc( sizeof *fdui );
-
+ OAI_phy_scope_t *fdui = calloc(( sizeof *fdui ),1);
// Define form
- fdui->phy_scope_nrue = fl_bgn_form( FL_NO_BOX, 800, 900 );
-
+ fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 800 );
// This the whole UI box
- obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" );
- fl_set_object_color( obj, FL_BLACK, FL_BLACK );
-
+ obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 800, "" );
+ fl_set_object_color( obj, FL_BLACK, FL_WHITE );
+ int curY=0,x,y,w,h;
// Received signal
- fdui->rxsig_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 20, 370, 100, "Received Signal (Time-Domain, dB)" );
- fl_set_object_boxtype( fdui->rxsig_t, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->rxsig_t, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->rxsig_t, FL_WHITE ); // Label color
- fl_set_xyplot_ybounds(fdui->rxsig_t,10,70);
-
+ fdui->graph[0] = gNBcommonGraph( timeSignal, FL_NORMAL_XYPLOT, 0, curY, 400, 100,
+ "Received Signal (Time-Domain, dB)", FL_RED );
// Time-domain channel response
- fdui->chest_t = fl_add_xyplot( FL_NORMAL_XYPLOT, 410, 20, 370, 100, "Channel Impulse Response (samples, abs)" );
- fl_set_object_boxtype( fdui->chest_t, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->chest_t, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->chest_t, FL_WHITE ); // Label color
-
+ fdui->graph[1] = gNBcommonGraph( timeResponse, FL_NORMAL_XYPLOT, 410, curY, 400, 100,
+ "SRS Frequency Response (samples, abs)", FL_RED );
+ fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h);
+ curY+=h;
// Frequency-domain channel response
- fdui->chest_f = fl_add_xyplot( FL_IMPULSE_XYPLOT, 20, 140, 760, 100, "Channel Frequency Response (RE, dB)" );
- fl_set_object_boxtype( fdui->chest_f, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->chest_f, FL_BLACK, FL_RED );
- fl_set_object_lcolor( fdui->chest_f, FL_WHITE ); // Label color
- fl_set_xyplot_ybounds( fdui->chest_f,30,70);
-
- // LLR of PBCH
- fdui->pbch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 260, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)" );
- fl_set_object_boxtype( fdui->pbch_llr, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pbch_llr, FL_BLACK, FL_GREEN );
- fl_set_object_lcolor( fdui->pbch_llr, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pbch_llr,2);
- fl_set_xyplot_xgrid( fdui->pbch_llr,FL_GRID_MAJOR);
- //fl_set_xyplot_xbounds( fdui->pbch_llr,0,1920);
+ fdui->graph[2] = gNBcommonGraph( frequencyResponse, FL_NORMAL_XYPLOT, 0, curY, 800, 100,
+ "Channel Frequency Response (RE, dB)", FL_RED );
+ fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h);
+ curY+=h;
+ // LLR of PUSCH
+ fdui->graph[3] = gNBcommonGraph( puschLLR, FL_POINTS_XYPLOT, 0, curY, 500, 200,
+ "PUSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW );
+ // I/Q PUSCH comp
+ fdui->graph[4] = gNBcommonGraph( puschIQ, FL_POINTS_XYPLOT, 500, curY, 300, 200,
+ "PUSCH I/Q of MF Output", FL_YELLOW );
+ fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h);
+ curY+=h;
+ // I/Q PUCCH comp (format 1)
+ fdui->graph[5] = gNBcommonGraph( pucchEnergy, FL_POINTS_XYPLOT, 0, curY, 300, 100,
+ "PUCCH1 Energy (SR)", FL_YELLOW );
+ // fl_set_xyplot_xgrid( fdui->pusch_llr,FL_GRID_MAJOR);
+ // I/Q PUCCH comp (fromat 1a/b)
+ fdui->graph[6] = gNBcommonGraph( pucchIQ, FL_POINTS_XYPLOT, 500, curY, 300, 100,
+ "PUCCH I/Q of MF Output", FL_YELLOW );
+ fl_get_object_bbox(fdui->graph[6].graph,&x, &y,&w, &h);
+ curY+=h;
+ // Throughput on PUSCH
+ fdui->graph[7] = gNBcommonGraph( puschThroughtput, FL_NORMAL_XYPLOT, 0, curY, 500, 100,
+ "PUSCH Throughput [frame]/[kbit/s]", FL_WHITE );
+ fdui->graph[8].graph=NULL;
+ fl_end_form( );
+ fdui->phy_scope->fdui = fdui;
+ fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, "LTE UL SCOPE gNB");
+ return fdui;
+}
- // I/Q PBCH comp
- fdui->pbch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 260, 240, 100, "PBCH I/Q of MF Output" );
- fl_set_object_boxtype( fdui->pbch_comp, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pbch_comp, FL_BLACK, FL_GREEN );
- fl_set_object_lcolor( fdui->pbch_comp, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pbch_comp,2);
- // fl_set_xyplot_xbounds( fdui->pbch_comp,-100,100);
- // fl_set_xyplot_ybounds( fdui->pbch_comp,-100,100);
+static const int scope_enb_num_ue = 1;
+void phy_scope_gNB(OAI_phy_scope_t *form,
+ PHY_VARS_gNB *phy_vars_gnb,
+ RU_t *phy_vars_ru,
+ int UE_id) {
+ static OAI_phy_scope_t *remeberForm=NULL;
- // LLR of PDCCH
- fdui->pdcch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 380, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)" );
- fl_set_object_boxtype( fdui->pdcch_llr, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pdcch_llr, FL_BLACK, FL_CYAN );
- fl_set_object_lcolor( fdui->pdcch_llr, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pdcch_llr,2);
+ if (form==NULL)
+ form=remeberForm;
+ else
+ remeberForm=form;
- // I/Q PDCCH comp
- fdui->pdcch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 380, 240, 100, "PDCCH I/Q of MF Output" );
- fl_set_object_boxtype( fdui->pdcch_comp, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pdcch_comp, FL_BLACK, FL_CYAN );
- fl_set_object_lcolor( fdui->pdcch_comp, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pdcch_comp,2);
- fl_set_xyplot_xgrid( fdui->pdcch_llr,FL_GRID_MAJOR);
+ if (form==NULL) return;
- // LLR of PDSCH
- fdui->pdsch_llr = fl_add_xyplot( FL_POINTS_XYPLOT, 20, 500, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)" );
- fl_set_object_boxtype( fdui->pdsch_llr, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pdsch_llr, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pdsch_llr, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pdsch_llr,2);
- fl_set_xyplot_xgrid( fdui->pdsch_llr,FL_GRID_MAJOR);
+ int i=0;
- // I/Q PDSCH comp
- fdui->pdsch_comp = fl_add_xyplot( FL_POINTS_XYPLOT, 540, 500, 240, 200, "PDSCH I/Q of MF Output" );
- fl_set_object_boxtype( fdui->pdsch_comp, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pdsch_comp, FL_BLACK, FL_YELLOW );
- fl_set_object_lcolor( fdui->pdsch_comp, FL_WHITE ); // Label color
- fl_set_xyplot_symbolsize( fdui->pdsch_comp,2);
+ while (form->graph[i].graph) {
+ form->graph[i].gNBfunct(form->graph+i, phy_vars_gnb, phy_vars_ru, UE_id);
+ i++;
+ }
- // Throughput on PDSCH
- fdui->pdsch_tput = fl_add_xyplot( FL_NORMAL_XYPLOT, 20, 720, 500, 100, "PDSCH Throughput [frame]/[kbit/s]" );
- fl_set_object_boxtype( fdui->pdsch_tput, FL_EMBOSSED_BOX );
- fl_set_object_color( fdui->pdsch_tput, FL_BLACK, FL_WHITE );
- fl_set_object_lcolor( fdui->pdsch_tput, FL_WHITE ); // Label color
+ fl_check_forms();
+}
- // Generic UE Button
- fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" );
- fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER );
- //openair_daq_vars.use_ia_receiver = 0;
- fl_set_button(fdui->button_0,0);
- fl_set_object_label(fdui->button_0, "IA Receiver OFF");
- fl_set_object_color(fdui->button_0, FL_RED, FL_RED);
- fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 );
- fl_hide_object(fdui->button_0);
+static void *scope_thread_gNB(void *arg) {
+ scopeParms_t *p=(scopeParms_t *) arg;
+ //# ifdef ENABLE_XFORMS_WRITE_STATS
+ // FILE *gNB_stats = fopen("gNB_stats.txt", "w");
+ //#endif
+ size_t stksize=0;
+ pthread_attr_t atr;
+ pthread_attr_init(&atr);
+ pthread_attr_getstacksize(&atr, &stksize);
+ pthread_attr_setstacksize(&atr,32*1024*1024 );
+ sleep(3); // no clean interthread barriers
+ fl_initialize (p->argc, p->argv, NULL, 0, 0);
+ int nb_ue=min(NUMBER_OF_UE_MAX, scope_enb_num_ue);
+ OAI_phy_scope_t *form_gnb = create_phy_scope_gnb();
- fl_end_form( );
- fdui->phy_scope_nrue->fdui = fdui;
+ while (!oai_exit) {
+ phy_scope_gNB(form_gnb, p->gNB, p->ru, nb_ue);
+ usleep(99*1000);
+ }
- return fdui;
+ return NULL;
}
-void phy_scope_nrUE(FD_phy_scope_nrue *form,
- PHY_VARS_NR_UE *phy_vars_ue,
- int eNB_id,
- int UE_id,
- uint8_t subframe)
-{
- int i,arx,atx,ind,k;
- NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms;
- //int nsymb_ce = frame_parms->ofdm_symbol_size;//*frame_parms->symbols_per_tti;
- int samples_per_frame = frame_parms->samples_per_frame;
- uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx;
- uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB;
- int16_t **rxsig_t;
- float **rxsig_t_dB;
- float *time;
- float *corr;
- int16_t **chest_t;
- int16_t **chest_f;
- int16_t *pdsch_llr;
- int16_t *pdsch_comp;
- //int16_t *pdsch_mag;
- int8_t *pdcch_llr;
- int16_t *pdcch_comp;
- int16_t *pbch_llr;
- int16_t *pbch_comp;
- float llr_pbch[1920], bit_pbch[1920];
- float *llr, *bit;
- float *llr_pdcch, *bit_pdcch;
- float *I, *Q;
- int num_pdcch_symbols=2;
- int num_re = 4500;
- int Qm = 2;
- int coded_bits_per_codeword = num_re*Qm;
- int symbol, first_symbol=2,nb_re;
- int nb_rb_pdsch=50,nb_symb_sch=9;
- float ymax=1;
- float **chest_t_abs;
- float Re,Im;
- float *chest_f_abs;
- float *freq;
- static int overlay = 0;
- /*
- int frame = phy_vars_ue->proc.proc_rxtx[0].frame_rx;
- int mcs = 0;
- unsigned char harq_pid = 0;
- */
+void gNBinitScope(scopeParms_t *p) {
+ static scopeParms_t parms;
+ memcpy(&parms,p,sizeof(parms));
+ pthread_t forms_thread;
+ threadCreate(&forms_thread, scope_thread_gNB, &parms, "scope", -1, OAI_PRIORITY_RT_LOW);
+}
- /*
- if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) {
- harq_pid = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->current_harq_pid;
+static void ueTimeResponse (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // Received signal in time domain of receive antenna 0
+ genericLogPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx,
+ (const scopeSample_t **) phy_vars_ue->common_vars.rxdata,
+ phy_vars_ue->frame_parms.samples_per_frame);
+}
- if (harq_pid>=8)
- return;
+static void ueChannelResponse (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // Channel Impulse Response
+ genericPowerPerAntena(graph, phy_vars_ue->frame_parms.nb_antennas_rx,
+ (const scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time,
+ phy_vars_ue->frame_parms.ofdm_symbol_size>>3);
+}
- mcs = phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->mcs;
+static void uePbchFrequencyResp (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // Channel Frequency Response (includes 5 complex sample for filter)
+ if (!phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates)
+ return;
- // Button 0
- if(!phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->dl_power_off) {
- // we are in TM5
- fl_show_object(form->button_0);
+ NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms;
+ uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx;
+ uint8_t nb_antennas_tx = frame_parms->nb_antenna_ports_gNB;
+ scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates;
+ int ind = 0;
+ float chest_f_abs[frame_parms->ofdm_symbol_size];
+ float freq[frame_parms->ofdm_symbol_size];
+
+ for (int atx=0; atx<nb_antennas_tx; atx++) {
+ for (int arx=0; arx<nb_antennas_rx; arx++) {
+ if (chest_f[(atx<<1)+arx] != NULL) {
+ for (int k=0; k<frame_parms->ofdm_symbol_size; k++) {
+ freq[ind] = (float)ind;
+ chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k]));
+ ind++;
+ }
+ }
}
}
- if (phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]!=NULL) {
- num_pdcch_symbols = phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->num_pdcch_symbols;
- }
+ // tx antenna 0
+ //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce);
+ //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2);
+ // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2);
+ //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR);
+ oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10);
+}
- // coded_bits_per_codeword = frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti);
- if (phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]!=NULL) {
- coded_bits_per_codeword = get_G(frame_parms,
- phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->nb_rb,
- phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->rb_alloc_even,
- get_Qm(mcs),
- phy_vars_ue->dlsch[phy_vars_ue->current_thread_id[subframe]][eNB_id][0]->harq_processes[harq_pid]->Nl,
- num_pdcch_symbols,
- frame,
- subframe,
- beamforming_mode);
- } else {
- coded_bits_per_codeword = 0; //frame_parms->N_RB_DL*12*get_Qm(mcs)*(frame_parms->symbols_per_tti);
- }
- */
- I = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float));
- Q = (float*) calloc(frame_parms->ofdm_symbol_size*frame_parms->symbols_per_slot*2,sizeof(float));
+static void uePbchLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PBCH LLRs
+ if ( !phy_vars_ue->pbch_vars[eNB_id]->llr)
+ return;
- chest_t_abs = (float**) malloc(nb_antennas_rx*sizeof(float*));
+ int16_t *pbch_llr = (int16_t *) phy_vars_ue->pbch_vars[eNB_id]->llr;
+ float llr_pbch[864], bit_pbch[864];
- for (arx=0; arx<nb_antennas_rx; arx++) {
- chest_t_abs[arx] = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float));
+ for (int i=0; i<864; i++) {
+ llr_pbch[i] = (float) pbch_llr[i];
+ bit_pbch[i] = (float) i;
}
- chest_f_abs = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float));
- freq = (float*) calloc(frame_parms->ofdm_symbol_size,sizeof(float));
+ oai_xygraph(graph,bit_pbch,llr_pbch,864,0,10);
+}
- llr = (float*) calloc(coded_bits_per_codeword,sizeof(float)); // init to zero
- bit = malloc(coded_bits_per_codeword*sizeof(float));
+static void uePbchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PBCH I/Q of MF Output
+ if (!phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0])
+ return;
- llr_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float)); // init to zero
- bit_pdcch = (float*) calloc(12*frame_parms->N_RB_DL*num_pdcch_symbols*2,sizeof(float));
+ scopeSample_t *pbch_comp = (scopeSample_t *) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0];
+ localBuff(I,180*3);
+ localBuff(Q,180*3);
+ int first_symbol=1;
+ int base=0;
- rxsig_t = (int16_t**) phy_vars_ue->common_vars.rxdata;
- rxsig_t_dB = calloc(nb_antennas_rx,sizeof(float*));
- for (arx=0; arx<nb_antennas_rx; arx++) {
- rxsig_t_dB[arx] = (float*) calloc(samples_per_frame,sizeof(float));
- }
- time = calloc(samples_per_frame,sizeof(float));
- corr = calloc(samples_per_frame,sizeof(float));
+ for (int symbol=first_symbol; symbol<(first_symbol+3); symbol++) {
+ int nb_re;
- chest_t = (int16_t**) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates_time;
- chest_f = (int16_t**) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates;
+ if (symbol == 2 || symbol == 6)
+ nb_re = 72;
+ else
+ nb_re = 180;
- pbch_llr = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->llr;
- pbch_comp = (int16_t*) phy_vars_ue->pbch_vars[eNB_id]->rxdataF_comp[0];
+ AssertFatal(base+nb_re<180*3,"");
- pdcch_llr = (int8_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr;
- pdcch_comp = (int16_t*) phy_vars_ue->pdcch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp[0];
- pdsch_llr = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->llr[0]; // stream 0
- // pdsch_llr = (int16_t*) phy_vars_ue->lte_ue_pdsch_vars_SI[eNB_id]->llr[0]; // stream 0
- pdsch_comp = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->rxdataF_comp0[0];
- //pdsch_mag = (int16_t*) phy_vars_ue->pdsch_vars[phy_vars_ue->current_thread_id[subframe]][eNB_id]->dl_ch_mag0[0];
+ for (int i=0; i<nb_re; i++) {
+ I[base+i] = pbch_comp[symbol*20*12+i].r;
+ Q[base+i] = pbch_comp[symbol*20*12+i].i;
+ }
- // Received signal in time domain of receive antenna 0
- if (rxsig_t != NULL) {
- if (rxsig_t[0] != NULL) {
- for (i=0; i<samples_per_frame; i++) {
- rxsig_t_dB[0][i] = 10*log10(1.0+(float) ((rxsig_t[0][2*i])*(rxsig_t[0][2*i])+(rxsig_t[0][2*i+1])*(rxsig_t[0][2*i+1])));
- time[i] = (float) i;
- }
+ base+=nb_re;
+ }
- fl_set_xyplot_data(form->rxsig_t,time,rxsig_t_dB[0],samples_per_frame,"","","");
- }
+ oai_xygraph(graph,I,Q,base,0,10);
+}
- /*
- for (arx=1; arx<nb_antennas_rx; arx++) {
- if (rxsig_t[arx] != NULL) {
- for (i=0; i<FRAME_LENGTH_COMPLEX_SAMPLES; i++) {
- rxsig_t_dB[arx][i] = 10*log10(1.0+(float) ((rxsig_t[arx][2*i])*(rxsig_t[arx][2*i])+(rxsig_t[arx][2*i+1])*(rxsig_t[arx][2*i+1])));
- }
+static void uePcchLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PDCCH LLRs
+ if (!phy_vars_ue->pdcch_vars[0][eNB_id]->llr)
+ return;
- fl_add_xyplot_overlay(form->rxsig_t,arx,time,rxsig_t_dB[arx],FRAME_LENGTH_COMPLEX_SAMPLES,rx_antenna_colors[arx]);
+ NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms;
+ uint8_t nb_antennas_rx = frame_parms->nb_antennas_rx;
+ uint8_t nb_antennas_tx = frame_parms->nb_antennas_tx;
+ scopeSample_t **chest_f = (scopeSample_t **) phy_vars_ue->pbch_vars[eNB_id]->dl_ch_estimates;
+ int ind = 0;
+ float chest_f_abs[frame_parms->ofdm_symbol_size];
+ float freq[frame_parms->ofdm_symbol_size];
+
+ for (int atx=0; atx<nb_antennas_tx; atx++) {
+ for (int arx=0; arx<nb_antennas_rx; arx++) {
+ if (chest_f[(atx<<1)+arx] != NULL) {
+ for (int k=0; k<frame_parms->ofdm_symbol_size; k++) {
+ freq[ind] = (float)ind;
+ chest_f_abs[ind] = (short)10*log10(1.0+SquaredNorm(chest_f[(atx<<1)+arx][6144+k]));
+ ind++;
+ }
}
}
- */
}
- if (phy_vars_ue->is_synchronized==0) {
- for (ind=0;ind<3;ind++) {
- /*
- if (pss_corr_ue[ind]) {
- for (i=0; i<samples_per_frame; i++) {
- corr[i] = (float) pss_corr_ue[ind][i];
- time[i] = (float) i;
- }
-
- if (ind==0)
- fl_set_xyplot_data(form->chest_t,time,corr,samples_per_frame,"","","");
- else
- fl_add_xyplot_overlay(form->chest_t,ind,time,corr,samples_per_frame,rx_antenna_colors[ind]);
-
- overlay = 1;
- }
- */
- }
- }
- else {
-
- if (overlay) { //there was a previous overlay
- fl_clear_xyplot(form->chest_t);
- overlay = 0;
- }
+ // tx antenna 0
+ //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce);
+ //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2);
+ // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2);
+ //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR);
+ oai_xygraph(graph,freq,chest_f_abs,frame_parms->ofdm_symbol_size,0,10);
+}
- // Channel Impulse Response
- if (chest_t != NULL) {
- ymax = 0;
+static void uePcchIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PDCCH I/Q of MF Output
+ if (!phy_vars_ue->pdcch_vars[0][eNB_id]->rxdataF_comp[0])
+ return;
- if (chest_t[0] !=NULL) {
- for (i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) {
- chest_t_abs[0][i] = (float) (chest_t[0][2*i]*chest_t[0][2*i]+chest_t[0][2*i+1]*chest_t[0][2*i+1]);
- time[i] = (float) i;
+ int nb=4*273*12; // 12*frame_parms->N_RB_DL*num_pdcch_symbols
+ localBuff(I,nb*RX_NB_TH_MAX);
+ localBuff(Q,nb*RX_NB_TH_MAX);
+ int base=0;
- if (chest_t_abs[0][i] > ymax)
- ymax = chest_t_abs[0][i];
- }
+ for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) {
+ scopeSample_t *pdcch_comp = (scopeSample_t *) phy_vars_ue->pdcch_vars[thr][eNB_id]->rxdataF_comp[0];
- fl_set_xyplot_data(form->chest_t,time,chest_t_abs[0],(frame_parms->ofdm_symbol_size>>3),"","","");
+ for (int i=0; i< nb; i++) {
+ I[base+i] = pdcch_comp[i].r;
+ Q[base+i] = pdcch_comp[i].i;
}
- /*
- for (arx=1; arx<nb_antennas_rx; arx++) {
- if (chest_t[arx] !=NULL) {
- for (i=0; i<(frame_parms->ofdm_symbol_size>>3); i++) {
- chest_t_abs[arx][i] = (float) (chest_t[arx][4*i]*chest_t[arx][4*i]+chest_t[arx][4*i+1]*chest_t[arx][4*i+1]);
-
- if (chest_t_abs[arx][i] > ymax)
- ymax = chest_t_abs[arx][i];
- }
- fl_add_xyplot_overlay(form->chest_t,arx,time,chest_t_abs[arx],(frame_parms->ofdm_symbol_size>>3),rx_antenna_colors[arx]);
- fl_set_xyplot_overlay_type(form->chest_t,arx,FL_DASHED_XYPLOT);
- }
- }
- */
- // Avoid flickering effect
- // fl_get_xyplot_ybounds(form->chest_t,&ymin,&ymax); // Does not always work...
- fl_set_xyplot_ybounds(form->chest_t,0,(double) ymax);
- }
+ base+=nb;
}
- // Channel Frequency Response (includes 5 complex sample for filter)
- if (chest_f != NULL) {
- ind = 0;
-
- for (atx=0; atx<nb_antennas_tx; atx++) {
- for (arx=0; arx<nb_antennas_rx; arx++) {
- if (chest_f[(atx<<1)+arx] != NULL) {
- for (k=0; k<frame_parms->ofdm_symbol_size; k++) {
- freq[ind] = (float)ind;
- Re = (float)(chest_f[(atx<<1)+arx][6144+(2*k)]);
- Im = (float)(chest_f[(atx<<1)+arx][6144+(2*k)+1]);
-
- chest_f_abs[ind] = (short)10*log10(1.0+((double)Re*Re + (double)Im*Im));
- ind++;
- }
- }
- }
- }
+ oai_xygraph(graph,I,Q,base,0,10);
+}
- // tx antenna 0
- //fl_set_xyplot_xbounds(form->chest_f,0,nb_antennas_rx*nb_antennas_tx*nsymb_ce);
- //fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*frame_parms->symbols_per_tti,2);
- // fl_set_xyplot_xtics(form->chest_f,nb_antennas_rx*nb_antennas_tx*2,2);
- //fl_set_xyplot_xgrid(form->chest_f,FL_GRID_MAJOR);
- fl_set_xyplot_data(form->chest_f,freq,chest_f_abs,frame_parms->ofdm_symbol_size,"","","");
+static void uePdschLLR (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PDSCH LLRs
+ if (!phy_vars_ue->pdsch_vars[0][eNB_id]->llr[0])
+ return;
- /*
- for (arx=1; arx<nb_antennas_rx; arx++) {
- fl_add_xyplot_overlay(form->chest_f,1,&freq[arx*nsymb_ce],&chest_f_abs[arx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
- }
+ int num_re = 4500;
+ int Qm = 2;
+ int coded_bits_per_codeword = num_re*Qm;
+ localBuff(llr,coded_bits_per_codeword*RX_NB_TH_MAX);
+ localBuff(bit,coded_bits_per_codeword*RX_NB_TH_MAX);
+ int base=0;
- // other tx antennas
- if (nb_antennas_tx > 1) {
- if (nb_antennas_rx > 1) {
- for (atx=1; atx<nb_antennas_tx; atx++) {
- for (arx=0; arx<nb_antennas_rx; arx++) {
- fl_add_xyplot_overlay(form->chest_f,(atx<<1)+arx,&freq[((atx<<1)+arx)*nsymb_ce],&chest_f_abs[((atx<<1)+arx)*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
- }
- }
- } else { // 1 rx antenna
- atx=1;
- arx=0;
- fl_add_xyplot_overlay(form->chest_f,atx,&freq[atx*nsymb_ce],&chest_f_abs[atx*nsymb_ce],nsymb_ce,rx_antenna_colors[arx]);
- }
- }
- */
- }
-
- // PBCH LLRs
- if (pbch_llr != NULL) {
- for (i=0; i<864; i++) {
- llr_pbch[i] = (float) pbch_llr[i];
- bit_pbch[i] = (float) i;
+ for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) {
+ int16_t *pdsch_llr = (int16_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->llr[0]; // stream 0
+
+ for (int i=0; i<coded_bits_per_codeword; i++) {
+ llr[base+i] = (float) pdsch_llr[i];
+ bit[base+i] = (float) base+i;
}
- fl_set_xyplot_data(form->pbch_llr,bit_pbch,llr_pbch,864,"","","");
+ base+=coded_bits_per_codeword;
}
- first_symbol=1;
-
- // PBCH I/Q of MF Output
- if (pbch_comp!=NULL) {
- for (symbol=first_symbol; symbol<(first_symbol+3); symbol++) {
- if (symbol == 2 || symbol == 6)
- nb_re = 72;
- else
- nb_re = 180;
- for (i=0; i<nb_re; i++) {
- I[i] = pbch_comp[2*symbol*20*12+2*i];
- Q[i] = pbch_comp[2*symbol*20*12+2*i+1];
- }
- }
- fl_set_xyplot_data(form->pbch_comp,I,Q,432,"","","");
- }
+ //fl_set_xyplot_xbounds(form->pdsch_llr,0,coded_bits_per_codeword);
+ oai_xygraph(graph,bit,llr,base,0,10);
+}
- // PDCCH LLRs
- if (pdcch_llr != NULL) {
- for (i=0; i<100; i++) { //12*frame_parms->N_RB_DL*2*num_pdcch_symbols
- llr_pdcch[i] = (float) pdcch_llr[2*24*9 +i];
- bit_pdcch[i] = (float) i;
- }
+static void uePdschIQ (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
+ // PDSCH I/Q of MF Output
+ if (!phy_vars_ue->pdsch_vars[0][eNB_id]->rxdataF_comp0[0])
+ return;
- fl_set_xyplot_data(form->pdcch_llr,bit_pdcch,llr_pdcch,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","","");
- }
+ NR_DL_FRAME_PARMS *frame_parms = &phy_vars_ue->frame_parms;
+ int sz=7*2*frame_parms->N_RB_DL*12; // size of the malloced buffer
+ localBuff(I,sz*RX_NB_TH_MAX);
+ localBuff(Q,sz*RX_NB_TH_MAX);
+ int base=0;
- // PDCCH I/Q of MF Output
- if (pdcch_comp!=NULL) {
- for (i=0; i<100; i++) {
- I[i] = pdcch_comp[2*50*12+2*i];
- Q[i] = pdcch_comp[2*50*12+2*i+1];
- }
- fl_set_xyplot_data(form->pdcch_comp,I,Q,12*frame_parms->N_RB_DL*num_pdcch_symbols,"","","");
- }
+ for (int thr=0 ; thr < RX_NB_TH_MAX ; thr ++ ) {
+ scopeSample_t *pdsch_comp = (scopeSample_t *) phy_vars_ue->pdsch_vars[thr][eNB_id]->rxdataF_comp0[0];
- // PDSCH LLRs
- if (pdsch_llr != NULL) {
- for (i=0; i<coded_bits_per_codeword; i++) {
- llr[i] = (float) pdsch_llr[i];
- bit[i] = (float) i;
+ for (int s=0; s<sz; s++) {
+ I[s+base] += pdsch_comp[s].r;
+ Q[s+base] += pdsch_comp[s].i;
}
- //fl_set_xyplot_xbounds(form->pdsch_llr,0,coded_bits_per_codeword);
- fl_set_xyplot_data(form->pdsch_llr,bit,llr,coded_bits_per_codeword,"","","");
+ base+=sz;
}
- first_symbol = 2;
- ind = 0;
- // PDSCH I/Q of MF Output
- if (pdsch_comp!=NULL) {
- for (symbol=0;symbol<nb_symb_sch;symbol++) {
- for (i=0; i<nb_rb_pdsch*12; i++) {
- I[ind] = pdsch_comp[2*((first_symbol+symbol)*frame_parms->N_RB_DL*12+i) ];
- Q[ind] = pdsch_comp[2*((first_symbol+symbol)*frame_parms->N_RB_DL*12+i)+1];
- ind++;
- }
- }
-
- fl_set_xyplot_data(form->pdsch_comp,I,Q,nb_symb_sch*nb_rb_pdsch*12,"","","");
- }
+ oai_xygraph(graph,I,Q,base,0,10);
+}
+
+static void uePdschThroughput (OAIgraph_t *graph, PHY_VARS_NR_UE *phy_vars_ue, int eNB_id, int UE_id) {
/*
// PDSCH Throughput
@@ -833,122 +640,177 @@ void phy_scope_nrUE(FD_phy_scope_nrue *form,
tput_ue[UE_id][TPUT_WINDOW_LENGTH-1] = ((float) total_dlsch_bitrate)/1000.0;
if (tput_ue[UE_id][TPUT_WINDOW_LENGTH-1] > tput_ue_max[UE_id]) {
- tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1];
+ tput_ue_max[UE_id] = tput_ue[UE_id][TPUT_WINDOW_LENGTH-1];
}
fl_set_xyplot_data(form->pdsch_tput,tput_time_ue[UE_id],tput_ue[UE_id],TPUT_WINDOW_LENGTH,"","","");
fl_set_xyplot_ybounds(form->pdsch_tput,0,tput_ue_max[UE_id]);
*/
+}
- fl_check_forms();
+static OAI_phy_scope_t *create_phy_scope_nrue( int ID ) {
+ FL_OBJECT *obj;
+ OAI_phy_scope_t *fdui = calloc(( sizeof *fdui ),1);
+ // Define form
+ fdui->phy_scope = fl_bgn_form( FL_NO_BOX, 800, 900 );
+ // This the whole UI box
+ obj = fl_add_box( FL_BORDER_BOX, 0, 0, 800, 900, "" );
+ fl_set_object_color( obj, FL_BLACK, FL_BLACK );
+ int curY=0,x,y,w,h;
+ // Received signal
+ fdui->graph[0] = nrUEcommonGraph(ueTimeResponse,
+ FL_NORMAL_XYPLOT, 0, curY, 400, 100, "Received Signal (Time-Domain, dB)", FL_RED );
+ // Time-domain channel response
+ fdui->graph[1] = nrUEcommonGraph(ueChannelResponse,
+ FL_NORMAL_XYPLOT, 400, curY, 400, 100, "Channel Impulse Response (samples, abs)", FL_RED );
+ fl_get_object_bbox(fdui->graph[0].graph,&x, &y,&w, &h);
+ curY+=h;
+ // Frequency-domain channel response
+ fdui->graph[2] = nrUEcommonGraph(uePbchFrequencyResp,
+ FL_IMPULSE_XYPLOT, 0, curY, 800, 100, "Channel Frequency data (RE, dB)", FL_RED );
+ fl_get_object_bbox(fdui->graph[2].graph,&x, &y,&w, &h);
+ curY+=h;
+ // LLR of PBCH
+ fdui->graph[3] = nrUEcommonGraph(uePbchLLR,
+ FL_POINTS_XYPLOT, 0, curY, 500, 100, "PBCH Log-Likelihood Ratios (LLR, mag)", FL_GREEN );
+ fl_set_xyplot_xgrid(fdui->graph[3].graph,FL_GRID_MAJOR);
+ // I/Q PBCH comp
+ fdui->graph[4] = nrUEcommonGraph(uePbchIQ,
+ FL_POINTS_XYPLOT, 500, curY, 300, 100, "PBCH I/Q of MF Output", FL_GREEN );
+ fl_get_object_bbox(fdui->graph[3].graph,&x, &y,&w, &h);
+ curY+=h;
+ // LLR of PDCCH
+ fdui->graph[5] = nrUEcommonGraph(uePcchLLR,
+ FL_POINTS_XYPLOT, 0, curY, 500, 100, "PDCCH Log-Likelihood Ratios (LLR, mag)", FL_CYAN );
+ // I/Q PDCCH comp
+ fdui->graph[6] = nrUEcommonGraph(uePcchIQ,
+ FL_POINTS_XYPLOT, 500, curY, 300, 100, "PDCCH I/Q of MF Output", FL_CYAN );
+ fl_get_object_bbox(fdui->graph[5].graph,&x, &y,&w, &h);
+ curY+=h;
+ // LLR of PDSCH
+ fdui->graph[7] = nrUEcommonGraph(uePdschLLR,
+ FL_POINTS_XYPLOT, 0, curY, 500, 200, "PDSCH Log-Likelihood Ratios (LLR, mag)", FL_YELLOW );
+ // I/Q PDSCH comp
+ fdui->graph[8] = nrUEcommonGraph(uePdschIQ,
+ FL_POINTS_XYPLOT, 500, curY, 300, 200, "PDSCH I/Q of MF Output", FL_YELLOW );
+ fl_get_object_bbox(fdui->graph[8].graph,&x, &y,&w, &h);
+ curY+=h;
+ // Throughput on PDSCH
+ fdui->graph[9] = nrUEcommonGraph(uePdschThroughput,
+ FL_NORMAL_XYPLOT, 0, curY, 500, 100, "PDSCH Throughput [frame]/[kbit/s]", FL_WHITE );
+ fdui->graph[10].graph=NULL;
+ // Generic UE Button
+#if 0
+ fdui->button_0 = fl_add_button( FL_PUSH_BUTTON, 540, 720, 240, 40, "" );
+ fl_set_object_lalign(fdui->button_0, FL_ALIGN_CENTER );
+ //openair_daq_vars.use_ia_receiver = 0;
+ fl_set_button(fdui->button_0,0);
+ fl_set_object_label(fdui->button_0, "IA Receiver OFF");
+ fl_set_object_color(fdui->button_0, FL_RED, FL_RED);
+ fl_set_object_callback(fdui->button_0, ia_receiver_on_off, 0 );
+ fl_hide_object(fdui->button_0);
+#endif
+ fl_end_form( );
+ fdui->phy_scope->fdui = fdui;
+ char buf[100];
+ sprintf(buf,"NR DL SCOPE UE %d", ID);
+ fl_show_form (fdui->phy_scope, FL_PLACE_HOTSPOT, FL_FULLBORDER, buf);
+ return fdui;
+}
- free(time);
- free(corr);
- for (arx=0; arx<nb_antennas_rx; arx++) {
- free(rxsig_t_dB[arx]);
- }
- free(rxsig_t_dB);
-
- free(I);
- free(Q);
- free(llr);
- free(bit);
- free(bit_pdcch);
- free(llr_pdcch);
- free(chest_t_abs);
- /*
- free(chest_f_abs);
- for (arx=0; arx<nb_antennas_rx; arx++) {
- free(chest_t_abs[arx]);
+void phy_scope_nrUE(OAI_phy_scope_t *form,
+ PHY_VARS_NR_UE *phy_vars_ue,
+ int eNB_id,
+ int UE_id) {
+ static OAI_phy_scope_t *remeberForm=NULL;
+
+ if (form==NULL)
+ form=remeberForm;
+ else
+ remeberForm=form;
+
+ if (form==NULL)
+ return;
+
+ int i=0;
+
+ while (form->graph[i].graph) {
+ form->graph[i].nrUEfunct(form->graph+i, phy_vars_ue, eNB_id, UE_id);
+ i++;
}
- free(chest_t_abs);
- */
+
+ fl_check_forms();
}
-typedef struct {
- FL_FORM *stats_form;
- void *vdata;
- char *cdata;
- long ldata;
- FL_OBJECT *stats_text;
- FL_OBJECT *stats_button;
-} FD_stats_form;
+static void *nrUEscopeThread(void *arg) {
+ PHY_VARS_NR_UE *ue=(PHY_VARS_NR_UE *)arg;
+ size_t stksize;
+ pthread_attr_t atr;
+ pthread_attr_getstacksize(&atr, &stksize);
+ pthread_attr_setstacksize(&atr,32*1024*1024 );
+ int fl_argc=1;
+ char *name="5G-UE-scope";
+ fl_initialize (&fl_argc, &name, NULL, 0, 0);
+ OAI_phy_scope_t *form_nrue=create_phy_scope_nrue(0);
+
+ while (!oai_exit) {
+ phy_scope_nrUE(form_nrue,
+ ue,
+ 0,0);
+ usleep(99*1000);
+ }
+
+ pthread_exit((void *)arg);
+}
+
+void nrUEinitScope(PHY_VARS_NR_UE *ue) {
+ pthread_t forms_thread;
+ threadCreate(&forms_thread, nrUEscopeThread, ue, "scope", -1, OAI_PRIORITY_RT_LOW);
+}
-// current status is that every UE has a DL scope for a SINGLE eNB (gnb_id=0)
-// at eNB 0, an UL scope for every UE
-FD_phy_scope_gnb *form_gnb[NUMBER_OF_UE_MAX];
+void nrscope_autoinit(void *dataptr) {
+ AssertFatal( (IS_SOFTMODEM_GNB_BIT||IS_SOFTMODEM_5GUE_BIT),"Scope cannot find NRUE or GNB context");
+
+ if (IS_SOFTMODEM_GNB_BIT)
+ gNBinitScope(dataptr);
+ else
+ nrUEinitScope(dataptr);
+}
+// Kept to put back the functionality soon
+#if 0
//FD_stats_form *form_stats=NULL,*form_stats_l2=NULL;
//char title[255];
-unsigned char scope_enb_num_ue = 1;
//static pthread_t forms_thread; //xforms
-
-
-void reset_stats_gNB(FL_OBJECT *button,
- long arg)
-{
+static void reset_stats_gNB(FL_OBJECT *button,
+ long arg) {
int i,k;
//PHY_VARS_gNB *phy_vars_gNB = RC.gNB[0][0];
for (i=0; i<NUMBER_OF_UE_MAX; i++) {
for (k=0; k<8; k++) { //harq_processes
/* for (j=0; j<phy_vars_gNB->dlsch[i][0]->Mlimit; j++) {
- phy_vars_gNB->UE_stats[i].dlsch_NAK[k][j]=0;
- phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0;
- phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0;
- }
- phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0;
- phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0;
- phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0;
- phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0;
- phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0;
- phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/
- }
- }
-}
-
-
-static void *scope_thread_gNB(void *arg) {
- int UE_id;
- int ue_cnt=0;
-//# ifdef ENABLE_XFORMS_WRITE_STATS
-// FILE *gNB_stats = fopen("gNB_stats.txt", "w");
-//#endif
-
- while (!oai_exit) {
- ue_cnt=0;
-
- for(UE_id=0; UE_id<NUMBER_OF_UE_MAX; UE_id++) {
- if ((ue_cnt<scope_enb_num_ue)) {
- //this function needs to be written
- phy_scope_gNB(form_gnb[ue_cnt], RC.gNB[0], RC.ru[0], UE_id);
- ue_cnt++;
+ phy_vars_gNB->UE_stats[i].dlsch_NAK[k][j]=0;
+ phy_vars_gNB->UE_stats[i].dlsch_ACK[k][j]=0;
+ phy_vars_gNB->UE_stats[i].dlsch_trials[k][j]=0;
}
+ phy_vars_gNB->UE_stats[i].dlsch_l2_errors[k]=0;
+ phy_vars_gNB->UE_stats[i].ulsch_errors[k]=0;
+ phy_vars_gNB->UE_stats[i].ulsch_consecutive_errors=0;
+ phy_vars_gNB->UE_stats[i].dlsch_sliding_cnt=0;
+ phy_vars_gNB->UE_stats[i].dlsch_NAK_round0=0;
+ phy_vars_gNB->UE_stats[i].dlsch_mcs_offset=0;*/
}
- sleep(1);
}
+}
-// printf("%s",stats_buffer);
-/*#ifdef ENABLE_XFORMS_WRITE_STATS
- if (eNB_stats) {
- rewind (gNB_stats);
- fwrite (stats_buffer, 1, len, gNB_stats);
- fclose (gNB_stats);
- }
-#endif
- pthread_exit((void *)arg);
-}*/
-
- return NULL;
-}
-
-FD_stats_form * create_form_stats_form( void ) {
+static FD_stats_form *create_form_stats_form(int ID) {
FL_OBJECT *obj;
- FD_stats_form *fdui = fl_malloc( sizeof *fdui );
+ FD_stats_form *fdui = calloc(( sizeof *fdui ),1);
fdui->vdata = fdui->cdata = NULL;
fdui->ldata = 0;
fdui->stats_form = fl_bgn_form( FL_NO_BOX, 1115, 900 );
@@ -964,24 +826,8 @@ FD_stats_form * create_form_stats_form( void ) {
fdui->stats_form->fdui = fdui;
return fdui;
}
+#endif
+
+
-void startScope(scopeParms_t * p) {
- FD_stats_form *form_stats=NULL,*form_stats_l2=NULL;
- char title[255];
- fl_initialize (p->argc, p->argv, NULL, 0, 0);
- /*
- form_stats_l2 = create_form_stats_form();
- fl_show_form (form_stats_l2->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "l2 stats");
- form_stats = create_form_stats_form();
- fl_show_form (form_stats->stats_form, FL_PLACE_HOTSPOT, FL_FULLBORDER, "stats");
- */
-
- for(int UE_id=0; UE_id<scope_enb_num_ue; UE_id++) {
- form_gnb[UE_id] = create_phy_scope_gnb();
- sprintf (title, "LTE UL SCOPE eNB for UE %d",UE_id);
- fl_show_form (form_gnb[UE_id]->phy_scope_gnb, FL_PLACE_HOTSPOT, FL_FULLBORDER, title);
- } // UE_id
- pthread_t forms_thread;
- threadCreate(&forms_thread, scope_thread_gNB, NULL, "scope", -1, OAI_PRIORITY_RT_LOW);
-}
diff --git a/openair1/PHY/TOOLS/nr_phy_scope.h b/openair1/PHY/TOOLS/nr_phy_scope.h
index aaee08a554bf9fe27c8ce5742531f3d4c29e1bd6..84b9e66908bec48d048e3cee9f345ae5726cc1fd 100644
--- a/openair1/PHY/TOOLS/nr_phy_scope.h
+++ b/openair1/PHY/TOOLS/nr_phy_scope.h
@@ -26,71 +26,20 @@
#include <simple_executable.h>
#include <common/utils/system.h>
#include <openairinterface5g_limits.h>
-#include <openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h>
#include "common/ran_context.h"
#include <openair1/PHY/defs_gNB.h>
-#include <forms.h>
#include "PHY/defs_gNB.h"
//#include "PHY/defs_nrUE.h"
//#include "PHY/impl_defs_top.h"
#include "PHY/defs_nr_UE.h"
-/* Forms and Objects */
-typedef struct {
- FL_FORM * phy_scope_gnb;
- FL_OBJECT * rxsig_t;
- FL_OBJECT * chest_f;
- FL_OBJECT * chest_t;
- FL_OBJECT * pusch_comp;
- FL_OBJECT * pucch_comp;
- FL_OBJECT * pucch_comp1;
- FL_OBJECT * pusch_llr;
- FL_OBJECT * pusch_tput;
- FL_OBJECT * button_0;
-} FD_phy_scope_gnb;
-
-typedef struct {
- FL_FORM * phy_scope_nrue;
- FL_OBJECT * rxsig_t;
- FL_OBJECT * chest_f;
- FL_OBJECT * chest_t;
- FL_OBJECT * pbch_comp;
- FL_OBJECT * pbch_llr;
- FL_OBJECT * pdcch_comp;
- FL_OBJECT * pdcch_llr;
- FL_OBJECT * pdsch_comp;
- FL_OBJECT * pdsch_llr;
- FL_OBJECT * pdsch_comp1;
- FL_OBJECT * pdsch_llr1;
- FL_OBJECT * pdsch_tput;
- FL_OBJECT * button_0;
-} FD_phy_scope_nrue;
-
typedef struct {
int *argc;
char **argv;
+ RU_t *ru;
+ PHY_VARS_gNB *gNB;
} scopeParms_t;
-extern unsigned char scope_enb_num_ue;
-FD_phy_scope_gnb * create_phy_scope_gnb( void );
-FD_phy_scope_nrue * create_phy_scope_nrue( void );
-
-
-void phy_scope_gNB(FD_phy_scope_gnb *form,
- PHY_VARS_gNB *phy_vars_gnb,
- RU_t *phy_vars_ru,
- int UE_id);
-
-
-void phy_scope_nrUE(FD_phy_scope_nrue *form,
- PHY_VARS_NR_UE *phy_vars_ue,
- int eNB_id,
- int UE_id,
- uint8_t subframe);
-
-
-void startScope(scopeParms_t * p);
-
extern RAN_CONTEXT_t RC;
#endif
diff --git a/openair1/PHY/TOOLS/oai_dfts.c b/openair1/PHY/TOOLS/oai_dfts.c
index d0b39184bb63aed51bb91623bd4fcd233e91ecf5..25244eeff530732ae75a32f94c95f90126df53b4 100644
--- a/openair1/PHY/TOOLS/oai_dfts.c
+++ b/openair1/PHY/TOOLS/oai_dfts.c
@@ -2439,6 +2439,10 @@ static inline void idft16(int16_t *x,int16_t *y)
#endif
}
+void idft16f(int16_t *x,int16_t *y) {
+ idft16(x,y);
+}
+
#if defined(__x86_64__) || defined(__i386__)
#ifdef __AVX2__
// Does two 16-point IDFTS (x[0 .. 15] is 128 LSBs of input vector, x[16..31] is in 128 MSBs)
@@ -5349,54 +5353,58 @@ void idft8192(int16_t *x,int16_t *y,unsigned char scale)
#endif
-int16_t twa1536[1024],twb1536[1024];
+int16_t tw16384[3*2*4096];
-// 512 x 3
-void idft1536(int16_t *input, int16_t *output, unsigned char scale)
+#ifndef __AVX2__
+void dft16384(int16_t *x,int16_t *y,unsigned char scale)
{
- int i,i2,j;
- uint32_t tmp[3][512 ]__attribute__((aligned(32)));
- uint32_t tmpo[3][512] __attribute__((aligned(32)));
- simd_q15_t *y128p=(simd_q15_t*)output;
- simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<512; i++) {
- tmp[0][i] = ((uint32_t *)input)[j++];
- tmp[1][i] = ((uint32_t *)input)[j++];
- tmp[2][i] = ((uint32_t *)input)[j++];
+ simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y;
+ simd_q15_t *ytmpp = &ytmp[0];
+ int i,j;
+
+ for (i=0,j=0; i<4096; i+=4,j++) {
+ transpose16_ooff(x128+i,xtmp+j,1024);
}
- idft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- idft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- idft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<1024; i+=8,i2+=4) {
- ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i),
- (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i));
+ dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1);
+ dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1);
+ dft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1);
+ dft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1);
+
+ for (i=0; i<1024; i++) {
+ bfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072,
+ y128p,y128p+1024,y128p+2048,y128p+3072,
+ tw16384_128p,tw16384_128p+1024,tw16384_128p+2048);
+ tw16384_128p++;
+ y128p++;
+ ytmpp++;
}
+ if (scale>0) {
- if (scale==1) {
- for (i=0; i<24; i++) {
- y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
- y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
- y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
- y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
- y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
- y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
- y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
- y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
- y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
- y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
- y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
- y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
- y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
- y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
- y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
- y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
- y128p+=16;
+ for (i=0; i<256; i++) {
+ y128[0] = shiftright_int16(y128[0],1);
+ y128[1] = shiftright_int16(y128[1],1);
+ y128[2] = shiftright_int16(y128[2],1);
+ y128[3] = shiftright_int16(y128[3],1);
+ y128[4] = shiftright_int16(y128[4],1);
+ y128[5] = shiftright_int16(y128[5],1);
+ y128[6] = shiftright_int16(y128[6],1);
+ y128[7] = shiftright_int16(y128[7],1);
+ y128[8] = shiftright_int16(y128[8],1);
+ y128[9] = shiftright_int16(y128[9],1);
+ y128[10] = shiftright_int16(y128[10],1);
+ y128[11] = shiftright_int16(y128[11],1);
+ y128[12] = shiftright_int16(y128[12],1);
+ y128[13] = shiftright_int16(y128[13],1);
+ y128[14] = shiftright_int16(y128[14],1);
+ y128[15] = shiftright_int16(y128[15],1);
+
+ y128+=16;
}
+
}
_mm_empty();
@@ -5404,61 +5412,57 @@ void idft1536(int16_t *input, int16_t *output, unsigned char scale)
}
-void dft1536(int16_t *input, int16_t *output, unsigned char scale)
+
+
+void idft16384(int16_t *x,int16_t *y,unsigned char scale)
{
- int i,i2,j;
- uint32_t tmp[3][512] __attribute__((aligned(32)));
- uint32_t tmpo[3][512] __attribute__((aligned(32)));
- simd_q15_t *y128p=(simd_q15_t*)output;
- simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<512; i++) {
- tmp[0][i] = ((uint32_t *)input)[j++];
- tmp[1][i] = ((uint32_t *)input)[j++];
- tmp[2][i] = ((uint32_t *)input)[j++];
+ simd_q15_t xtmp[4096],ytmp[4096],*tw16384_128p=(simd_q15_t *)tw16384,*x128=(simd_q15_t *)x,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y;
+ simd_q15_t *ytmpp = &ytmp[0];
+ int i,j;
+
+ for (i=0,j=0; i<4096; i+=4,j++) {
+ transpose16_ooff(x128+i,xtmp+j,1024);
}
- dft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- dft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- dft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- /*
- for (i=1; i<512; i++) {
- tmpo[0][i] = tmpo[0][i<<1];
- tmpo[1][i] = tmpo[1][i<<1];
- tmpo[2][i] = tmpo[2][i<<1];
- }*/
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("dft1536out0.m","o0",tmpo[0],2048,1,1);
- LOG_M("dft1536out1.m","o1",tmpo[1],2048,1,1);
- LOG_M("dft1536out2.m","o2",tmpo[2],2048,1,1);
- }
- for (i=0,i2=0; i<1024; i+=8,i2+=4) {
- bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i),
- (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i));
+ idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1);
+ idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1);
+ idft4096((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1);
+ idft4096((int16_t*)(xtmp+3072),(int16_t*)(ytmp+3072),1);
+
+ for (i=0; i<1024; i++) {
+ ibfly4(ytmpp,ytmpp+1024,ytmpp+2048,ytmpp+3072,
+ y128p,y128p+1024,y128p+2048,y128p+3072,
+ tw16384_128p,tw16384_128p+1024,tw16384_128p+2048);
+ tw16384_128p++;
+ y128p++;
+ ytmpp++;
}
- if (scale==1) {
- for (i=0; i<24; i++) {
- y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
- y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
- y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
- y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
- y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
- y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
- y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
- y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
- y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
- y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
- y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
- y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
- y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
- y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
- y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
- y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
- y128p+=16;
+ if (scale>0) {
+
+ for (i=0; i<256; i++) {
+ y128[0] = shiftright_int16(y128[0],scale);
+ y128[1] = shiftright_int16(y128[1],scale);
+ y128[2] = shiftright_int16(y128[2],scale);
+ y128[3] = shiftright_int16(y128[3],scale);
+ y128[4] = shiftright_int16(y128[4],scale);
+ y128[5] = shiftright_int16(y128[5],scale);
+ y128[6] = shiftright_int16(y128[6],scale);
+ y128[7] = shiftright_int16(y128[7],scale);
+ y128[8] = shiftright_int16(y128[8],scale);
+ y128[9] = shiftright_int16(y128[9],scale);
+ y128[10] = shiftright_int16(y128[10],scale);
+ y128[11] = shiftright_int16(y128[11],scale);
+ y128[12] = shiftright_int16(y128[12],scale);
+ y128[13] = shiftright_int16(y128[13],scale);
+ y128[14] = shiftright_int16(y128[14],scale);
+ y128[15] = shiftright_int16(y128[15],scale);
+
+ y128+=16;
}
+
}
_mm_empty();
@@ -5466,96 +5470,957 @@ void dft1536(int16_t *input, int16_t *output, unsigned char scale)
}
-int16_t twa3072[2048] __attribute__((aligned(32)));
-int16_t twb3072[2048] __attribute__((aligned(32)));
-// 1024 x 3
-void dft3072(int16_t *input, int16_t *output,unsigned char scale)
+#else //__AVX2__
+void dft16384(int16_t *x,int16_t *y,unsigned char scale)
{
- int i,i2,j;
- uint32_t tmp[3][1024] __attribute__((aligned(32)));
- uint32_t tmpo[3][1024] __attribute__((aligned(32)));
- simd_q15_t *y128p=(simd_q15_t*)output;
- simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<1024; i++) {
- tmp[0][i] = ((uint32_t *)input)[j++];
- tmp[1][i] = ((uint32_t *)input)[j++];
- tmp[2][i] = ((uint32_t *)input)[j++];
+ simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y;
+ simd256_q15_t *ytmpp = &ytmp[0];
+ int i,j;
+
+ for (i=0,j=0; i<2048; i+=4,j++) {
+ transpose16_ooff_simd256(x256+i,xtmp+j,512);
}
- dft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- dft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- dft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<2048; i+=8,i2+=4) {
- bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i),
- (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i));
+ dft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1);
+ dft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1);
+ dft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1);
+ dft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1);
+
+ for (i=0; i<512; i++) {
+ bfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536,
+ y256p,y256p+512,y256p+1024,y256p+1536,
+ tw16384_256p,tw16384_256p+512,tw16384_256p+1024);
+ tw16384_256p++;
+ y256p++;
+ ytmpp++;
}
- if (scale==1) {
- for (i=0; i<48; i++) {
- y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
- y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
- y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
- y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
- y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
- y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
- y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
- y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
- y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
- y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
- y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
- y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
- y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
- y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
- y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
- y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
- y128p+=16;
+ if (scale>0) {
+
+ for (i=0; i<128; i++) {
+ y256[0] = shiftright_int16_simd256(y256[0],1);
+ y256[1] = shiftright_int16_simd256(y256[1],1);
+ y256[2] = shiftright_int16_simd256(y256[2],1);
+ y256[3] = shiftright_int16_simd256(y256[3],1);
+ y256[4] = shiftright_int16_simd256(y256[4],1);
+ y256[5] = shiftright_int16_simd256(y256[5],1);
+ y256[6] = shiftright_int16_simd256(y256[6],1);
+ y256[7] = shiftright_int16_simd256(y256[7],1);
+ y256[8] = shiftright_int16_simd256(y256[8],1);
+ y256[9] = shiftright_int16_simd256(y256[9],1);
+ y256[10] = shiftright_int16_simd256(y256[10],1);
+ y256[11] = shiftright_int16_simd256(y256[11],1);
+ y256[12] = shiftright_int16_simd256(y256[12],1);
+ y256[13] = shiftright_int16_simd256(y256[13],1);
+ y256[14] = shiftright_int16_simd256(y256[14],1);
+ y256[15] = shiftright_int16_simd256(y256[15],1);
+
+ y256+=16;
}
+
}
_mm_empty();
_m_empty();
+
}
-void idft3072(int16_t *input, int16_t *output,unsigned char scale)
+void idft16384(int16_t *x,int16_t *y,unsigned char scale)
{
- int i,i2,j;
- uint32_t tmp[3][1024]__attribute__((aligned(32)));
- uint32_t tmpo[3][1024] __attribute__((aligned(32)));
- simd_q15_t *y128p=(simd_q15_t*)output;
- simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<1024; i++) {
- tmp[0][i] = ((uint32_t *)input)[j++];
- tmp[1][i] = ((uint32_t *)input)[j++];
- tmp[2][i] = ((uint32_t *)input)[j++];
+ simd256_q15_t xtmp[2048],ytmp[2048],*tw16384_256p=(simd256_q15_t *)tw16384,*x256=(simd256_q15_t *)x,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y;
+ simd256_q15_t *ytmpp = &ytmp[0];
+ int i,j;
+
+ for (i=0,j=0; i<2048; i+=4,j++) {
+ transpose16_ooff_simd256(x256+i,xtmp+j,512);
}
- idft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- idft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- idft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<2048; i+=8,i2+=4) {
- ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i),
- (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i));
+
+ idft4096((int16_t*)(xtmp),(int16_t*)(ytmp),1);
+ idft4096((int16_t*)(xtmp+512),(int16_t*)(ytmp+512),1);
+ idft4096((int16_t*)(xtmp+1024),(int16_t*)(ytmp+1024),1);
+ idft4096((int16_t*)(xtmp+1536),(int16_t*)(ytmp+1536),1);
+
+ for (i=0; i<512; i++) {
+ ibfly4_256(ytmpp,ytmpp+512,ytmpp+1024,ytmpp+1536,
+ y256p,y256p+512,y256p+1024,y256p+1536,
+ tw16384_256p,tw16384_256p+512,tw16384_256p+1024);
+ tw16384_256p++;
+ y256p++;
+ ytmpp++;
}
+ if (scale>0) {
- if (scale==1) {
- for (i=0; i<48; i++) {
- y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
- y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
- y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
- y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
- y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
- y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
- y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
- y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
- y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
- y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
- y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ for (i=0; i<128; i++) {
+ y256[0] = shiftright_int16_simd256(y256[0],1);
+ y256[1] = shiftright_int16_simd256(y256[1],1);
+ y256[2] = shiftright_int16_simd256(y256[2],1);
+ y256[3] = shiftright_int16_simd256(y256[3],1);
+ y256[4] = shiftright_int16_simd256(y256[4],1);
+ y256[5] = shiftright_int16_simd256(y256[5],1);
+ y256[6] = shiftright_int16_simd256(y256[6],1);
+ y256[7] = shiftright_int16_simd256(y256[7],1);
+ y256[8] = shiftright_int16_simd256(y256[8],1);
+ y256[9] = shiftright_int16_simd256(y256[9],1);
+ y256[10] = shiftright_int16_simd256(y256[10],1);
+ y256[11] = shiftright_int16_simd256(y256[11],1);
+ y256[12] = shiftright_int16_simd256(y256[12],1);
+ y256[13] = shiftright_int16_simd256(y256[13],1);
+ y256[14] = shiftright_int16_simd256(y256[14],1);
+ y256[15] = shiftright_int16_simd256(y256[15],1);
+
+ y256+=16;
+ }
+
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+#endif //__AVX2__
+
+int16_t tw32768[2*16384] __attribute__((aligned(32)));
+
+#ifndef __AVX2__
+void dft32768(int16_t *x,int16_t *y,unsigned char scale)
+{
+
+ simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x;
+ simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y;
+ simd_q15_t *ytmpp = &ytmp[0];
+ int i;
+ simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15);
+
+ xtmpp = xtmp;
+
+ for (i=0; i<256; i++) {
+ transpose4_ooff(x64 ,xtmpp,8192);
+ transpose4_ooff(x64+2,xtmpp+1,8192);
+ transpose4_ooff(x64+4,xtmpp+2,8192);
+ transpose4_ooff(x64+6,xtmpp+3,8192);
+ transpose4_ooff(x64+8,xtmpp+4,8192);
+ transpose4_ooff(x64+10,xtmpp+5,8192);
+ transpose4_ooff(x64+12,xtmpp+6,8192);
+ transpose4_ooff(x64+14,xtmpp+7,8192);
+ transpose4_ooff(x64+16,xtmpp+8,8192);
+ transpose4_ooff(x64+18,xtmpp+9,8192);
+ transpose4_ooff(x64+20,xtmpp+10,8192);
+ transpose4_ooff(x64+22,xtmpp+11,8192);
+ transpose4_ooff(x64+24,xtmpp+12,8192);
+ transpose4_ooff(x64+26,xtmpp+13,8192);
+ transpose4_ooff(x64+28,xtmpp+14,8192);
+ transpose4_ooff(x64+30,xtmpp+15,8192);
+ transpose4_ooff(x64+32,xtmpp+16,8192);
+ transpose4_ooff(x64+34,xtmpp+17,8192);
+ transpose4_ooff(x64+36,xtmpp+18,8192);
+ transpose4_ooff(x64+38,xtmpp+19,8192);
+ transpose4_ooff(x64+40,xtmpp+20,8192);
+ transpose4_ooff(x64+42,xtmpp+21,8192);
+ transpose4_ooff(x64+44,xtmpp+22,8192);
+ transpose4_ooff(x64+46,xtmpp+23,8192);
+ transpose4_ooff(x64+48,xtmpp+24,8192);
+ transpose4_ooff(x64+50,xtmpp+25,8192);
+ transpose4_ooff(x64+52,xtmpp+26,8192);
+ transpose4_ooff(x64+54,xtmpp+27,8192);
+ transpose4_ooff(x64+56,xtmpp+28,8192);
+ transpose4_ooff(x64+58,xtmpp+29,8192);
+ transpose4_ooff(x64+60,xtmpp+30,8192);
+ transpose4_ooff(x64+62,xtmpp+31,8192);
+ x64+=64;
+ xtmpp+=32;
+ }
+
+ dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1);
+ dft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1);
+
+
+ for (i=0; i<4096; i++) {
+ bfly2(ytmpp,ytmpp+4096,
+ y128p,y128p+4096,
+ tw32768_128p);
+ tw32768_128p++;
+ y128p++;
+ ytmpp++;
+ }
+
+ if (scale>0) {
+ y128p = y128;
+
+ for (i=0; i<512; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+void idft32768(int16_t *x,int16_t *y,unsigned char scale)
+{
+
+ simdshort_q15_t xtmp[16384],*xtmpp,*x64 = (simdshort_q15_t *)x;
+ simd_q15_t ytmp[8192],*tw32768_128p=(simd_q15_t *)tw32768,*y128=(simd_q15_t *)y,*y128p=(simd_q15_t *)y;
+ simd_q15_t *ytmpp = &ytmp[0];
+ int i;
+ simd_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16(ONE_OVER_SQRT2_Q15);
+
+ xtmpp = xtmp;
+
+ for (i=0; i<256; i++) {
+ transpose4_ooff(x64 ,xtmpp,8192);
+ transpose4_ooff(x64+2,xtmpp+1,8192);
+ transpose4_ooff(x64+4,xtmpp+2,8192);
+ transpose4_ooff(x64+6,xtmpp+3,8192);
+ transpose4_ooff(x64+8,xtmpp+4,8192);
+ transpose4_ooff(x64+10,xtmpp+5,8192);
+ transpose4_ooff(x64+12,xtmpp+6,8192);
+ transpose4_ooff(x64+14,xtmpp+7,8192);
+ transpose4_ooff(x64+16,xtmpp+8,8192);
+ transpose4_ooff(x64+18,xtmpp+9,8192);
+ transpose4_ooff(x64+20,xtmpp+10,8192);
+ transpose4_ooff(x64+22,xtmpp+11,8192);
+ transpose4_ooff(x64+24,xtmpp+12,8192);
+ transpose4_ooff(x64+26,xtmpp+13,8192);
+ transpose4_ooff(x64+28,xtmpp+14,8192);
+ transpose4_ooff(x64+30,xtmpp+15,8192);
+ transpose4_ooff(x64+32,xtmpp+16,8192);
+ transpose4_ooff(x64+34,xtmpp+17,8192);
+ transpose4_ooff(x64+36,xtmpp+18,8192);
+ transpose4_ooff(x64+38,xtmpp+19,8192);
+ transpose4_ooff(x64+40,xtmpp+20,8192);
+ transpose4_ooff(x64+42,xtmpp+21,8192);
+ transpose4_ooff(x64+44,xtmpp+22,8192);
+ transpose4_ooff(x64+46,xtmpp+23,8192);
+ transpose4_ooff(x64+48,xtmpp+24,8192);
+ transpose4_ooff(x64+50,xtmpp+25,8192);
+ transpose4_ooff(x64+52,xtmpp+26,8192);
+ transpose4_ooff(x64+54,xtmpp+27,8192);
+ transpose4_ooff(x64+56,xtmpp+28,8192);
+ transpose4_ooff(x64+58,xtmpp+29,8192);
+ transpose4_ooff(x64+60,xtmpp+30,8192);
+ transpose4_ooff(x64+62,xtmpp+31,8192);
+ x64+=64;
+ xtmpp+=32;
+ }
+
+ idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1);
+ idft16384((int16_t*)(xtmp+8192),(int16_t*)(ytmp+4096),1);
+
+
+ for (i=0; i<4096; i++) {
+ ibfly2(ytmpp,ytmpp+4096,
+ y128p,y128p+4096,
+ tw32768_128p);
+ tw32768_128p++;
+ y128p++;
+ ytmpp++;
+ }
+
+ if (scale>0) {
+ y128p = y128;
+
+ for (i=0; i<512; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT2_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT2_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT2_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT2_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT2_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT2_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT2_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT2_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT2_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT2_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT2_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT2_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT2_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT2_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT2_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT2_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+#else // __AVX2__
+void dft32768(int16_t *x,int16_t *y,unsigned char scale)
+{
+
+ simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x;
+ simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y;
+
+ simd256_q15_t *ytmpp = &ytmp[0];
+ int i;
+ simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15);
+
+ xtmpp = xtmp;
+
+ for (i=0; i<256; i++) {
+ transpose4_ooff_simd256(x256 ,xtmpp,2048);
+ transpose4_ooff_simd256(x256+2,xtmpp+1,2048);
+ transpose4_ooff_simd256(x256+4,xtmpp+2,2048);
+ transpose4_ooff_simd256(x256+6,xtmpp+3,2048);
+ transpose4_ooff_simd256(x256+8,xtmpp+4,2048);
+ transpose4_ooff_simd256(x256+10,xtmpp+5,2048);
+ transpose4_ooff_simd256(x256+12,xtmpp+6,2048);
+ transpose4_ooff_simd256(x256+14,xtmpp+7,2048);
+ transpose4_ooff_simd256(x256+16,xtmpp+8,2048);
+ transpose4_ooff_simd256(x256+18,xtmpp+9,2048);
+ transpose4_ooff_simd256(x256+20,xtmpp+10,2048);
+ transpose4_ooff_simd256(x256+22,xtmpp+11,2048);
+ transpose4_ooff_simd256(x256+24,xtmpp+12,2048);
+ transpose4_ooff_simd256(x256+26,xtmpp+13,2048);
+ transpose4_ooff_simd256(x256+28,xtmpp+14,2048);
+ transpose4_ooff_simd256(x256+30,xtmpp+15,2048);
+ transpose4_ooff_simd256(x256+32,xtmpp+16,2048);
+ transpose4_ooff_simd256(x256+34,xtmpp+17,2048);
+ transpose4_ooff_simd256(x256+36,xtmpp+18,2048);
+ transpose4_ooff_simd256(x256+38,xtmpp+19,2048);
+ transpose4_ooff_simd256(x256+40,xtmpp+20,2048);
+ transpose4_ooff_simd256(x256+42,xtmpp+21,2048);
+ transpose4_ooff_simd256(x256+44,xtmpp+22,2048);
+ transpose4_ooff_simd256(x256+46,xtmpp+23,2048);
+ transpose4_ooff_simd256(x256+48,xtmpp+24,2048);
+ transpose4_ooff_simd256(x256+50,xtmpp+25,2048);
+ transpose4_ooff_simd256(x256+52,xtmpp+26,2048);
+ transpose4_ooff_simd256(x256+54,xtmpp+27,2048);
+ transpose4_ooff_simd256(x256+56,xtmpp+28,2048);
+ transpose4_ooff_simd256(x256+58,xtmpp+29,2048);
+ transpose4_ooff_simd256(x256+60,xtmpp+30,2048);
+ transpose4_ooff_simd256(x256+62,xtmpp+31,2048);
+ x256+=64;
+ xtmpp+=32;
+ }
+
+ dft16384((int16_t*)(xtmp),(int16_t*)ytmp,1);
+ dft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1);
+
+
+ for (i=0; i<2048; i++) {
+ bfly2_256(ytmpp,ytmpp+2048,
+ y256p,y256p+2048,
+ tw32768_256p);
+ tw32768_256p++;
+ y256p++;
+ ytmpp++;
+ }
+
+ if (scale>0) {
+ y256p = y256;
+
+ for (i=0; i<64; i++) {
+ y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128);
+ y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128);
+ y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128);
+ y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128);
+ y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128);
+ y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128);
+ y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128);
+ y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128);
+ y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128);
+ y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128);
+ y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128);
+ y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128);
+ y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128);
+ y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128);
+ y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128);
+ y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128);
+ y256p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+void idft32768(int16_t *x,int16_t *y,unsigned char scale)
+{
+
+ simd256_q15_t xtmp[4096],*xtmpp,*x256 = (simd256_q15_t *)x;
+ simd256_q15_t ytmp[4096],*tw32768_256p=(simd256_q15_t *)tw32768,*y256=(simd256_q15_t *)y,*y256p=(simd256_q15_t *)y;
+ simd256_q15_t *ytmpp = &ytmp[0];
+ int i;
+ simd256_q15_t ONE_OVER_SQRT2_Q15_128 = set1_int16_simd256(ONE_OVER_SQRT2_Q15);
+
+ xtmpp = xtmp;
+
+ for (i=0; i<64; i++) {
+ transpose4_ooff_simd256(x256 ,xtmpp,2048);
+ transpose4_ooff_simd256(x256+2,xtmpp+1,2048);
+ transpose4_ooff_simd256(x256+4,xtmpp+2,2048);
+ transpose4_ooff_simd256(x256+6,xtmpp+3,2048);
+ transpose4_ooff_simd256(x256+8,xtmpp+4,2048);
+ transpose4_ooff_simd256(x256+10,xtmpp+5,2048);
+ transpose4_ooff_simd256(x256+12,xtmpp+6,2048);
+ transpose4_ooff_simd256(x256+14,xtmpp+7,2048);
+ transpose4_ooff_simd256(x256+16,xtmpp+8,2048);
+ transpose4_ooff_simd256(x256+18,xtmpp+9,2048);
+ transpose4_ooff_simd256(x256+20,xtmpp+10,2048);
+ transpose4_ooff_simd256(x256+22,xtmpp+11,2048);
+ transpose4_ooff_simd256(x256+24,xtmpp+12,2048);
+ transpose4_ooff_simd256(x256+26,xtmpp+13,2048);
+ transpose4_ooff_simd256(x256+28,xtmpp+14,2048);
+ transpose4_ooff_simd256(x256+30,xtmpp+15,2048);
+ transpose4_ooff_simd256(x256+32,xtmpp+16,2048);
+ transpose4_ooff_simd256(x256+34,xtmpp+17,2048);
+ transpose4_ooff_simd256(x256+36,xtmpp+18,2048);
+ transpose4_ooff_simd256(x256+38,xtmpp+19,2048);
+ transpose4_ooff_simd256(x256+40,xtmpp+20,2048);
+ transpose4_ooff_simd256(x256+42,xtmpp+21,2048);
+ transpose4_ooff_simd256(x256+44,xtmpp+22,2048);
+ transpose4_ooff_simd256(x256+46,xtmpp+23,2048);
+ transpose4_ooff_simd256(x256+48,xtmpp+24,2048);
+ transpose4_ooff_simd256(x256+50,xtmpp+25,2048);
+ transpose4_ooff_simd256(x256+52,xtmpp+26,2048);
+ transpose4_ooff_simd256(x256+54,xtmpp+27,2048);
+ transpose4_ooff_simd256(x256+56,xtmpp+28,2048);
+ transpose4_ooff_simd256(x256+58,xtmpp+29,2048);
+ transpose4_ooff_simd256(x256+60,xtmpp+30,2048);
+ transpose4_ooff_simd256(x256+62,xtmpp+31,2048);
+ x256+=64;
+ xtmpp+=32;
+ }
+
+ idft16384((int16_t*)(xtmp),(int16_t*)ytmp,1);
+ idft16384((int16_t*)(xtmp+2048),(int16_t*)(ytmp+2048),1);
+
+
+ for (i=0; i<2048; i++) {
+ ibfly2_256(ytmpp,ytmpp+2048,
+ y256p,y256p+2048,
+ tw32768_256p);
+ tw32768_256p++;
+ y256p++;
+ ytmpp++;
+ }
+
+ if (scale>0) {
+ y256p = y256;
+
+ for (i=0; i<256; i++) {
+ y256p[0] = mulhi_int16_simd256(y256p[0],ONE_OVER_SQRT2_Q15_128);
+ y256p[1] = mulhi_int16_simd256(y256p[1],ONE_OVER_SQRT2_Q15_128);
+ y256p[2] = mulhi_int16_simd256(y256p[2],ONE_OVER_SQRT2_Q15_128);
+ y256p[3] = mulhi_int16_simd256(y256p[3],ONE_OVER_SQRT2_Q15_128);
+ y256p[4] = mulhi_int16_simd256(y256p[4],ONE_OVER_SQRT2_Q15_128);
+ y256p[5] = mulhi_int16_simd256(y256p[5],ONE_OVER_SQRT2_Q15_128);
+ y256p[6] = mulhi_int16_simd256(y256p[6],ONE_OVER_SQRT2_Q15_128);
+ y256p[7] = mulhi_int16_simd256(y256p[7],ONE_OVER_SQRT2_Q15_128);
+ y256p[8] = mulhi_int16_simd256(y256p[8],ONE_OVER_SQRT2_Q15_128);
+ y256p[9] = mulhi_int16_simd256(y256p[9],ONE_OVER_SQRT2_Q15_128);
+ y256p[10] = mulhi_int16_simd256(y256p[10],ONE_OVER_SQRT2_Q15_128);
+ y256p[11] = mulhi_int16_simd256(y256p[11],ONE_OVER_SQRT2_Q15_128);
+ y256p[12] = mulhi_int16_simd256(y256p[12],ONE_OVER_SQRT2_Q15_128);
+ y256p[13] = mulhi_int16_simd256(y256p[13],ONE_OVER_SQRT2_Q15_128);
+ y256p[14] = mulhi_int16_simd256(y256p[14],ONE_OVER_SQRT2_Q15_128);
+ y256p[15] = mulhi_int16_simd256(y256p[15],ONE_OVER_SQRT2_Q15_128);
+ y256p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+
+#endif
+
+
+int16_t twa1536[1024],twb1536[1024];
+
+// 512 x 3
+void idft1536(int16_t *input, int16_t *output, unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][512 ]__attribute__((aligned(32)));
+ uint32_t tmpo[3][512] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<512; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ idft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ for (i=0,i2=0; i<1024; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i),
+ (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i));
+ }
+
+
+ if (scale==1) {
+ for (i=0; i<24; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+void dft1536(int16_t *input, int16_t *output, unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][512] __attribute__((aligned(32)));
+ uint32_t tmpo[3][512] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<512; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ dft512((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft512((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft512((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ /*
+ for (i=1; i<512; i++) {
+ tmpo[0][i] = tmpo[0][i<<1];
+ tmpo[1][i] = tmpo[1][i<<1];
+ tmpo[2][i] = tmpo[2][i<<1];
+ }*/
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("dft1536out0.m","o0",tmpo[0],2048,1,1);
+ LOG_M("dft1536out1.m","o1",tmpo[1],2048,1,1);
+ LOG_M("dft1536out2.m","o2",tmpo[2],2048,1,1);
+ }
+ for (i=0,i2=0; i<1024; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+1024+i),(simd_q15_t*)(output+2048+i),
+ (simd_q15_t*)(twa1536+i),(simd_q15_t*)(twb1536+i));
+ }
+
+ if (scale==1) {
+ for (i=0; i<24; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+int16_t twa3072[2048] __attribute__((aligned(32)));
+int16_t twb3072[2048] __attribute__((aligned(32)));
+// 1024 x 3
+void dft3072(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][1024] __attribute__((aligned(32)));
+ uint32_t tmpo[3][1024] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<1024; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ dft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ for (i=0,i2=0; i<2048; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i),
+ (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i));
+ }
+
+ if (scale==1) {
+ for (i=0; i<48; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+}
+
+void idft3072(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][1024]__attribute__((aligned(32)));
+ uint32_t tmpo[3][1024] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<1024; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+ idft1024((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft1024((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft1024((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ for (i=0,i2=0; i<2048; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+2048+i),(simd_q15_t*)(output+4096+i),
+ (simd_q15_t*)(twa3072+i),(simd_q15_t*)(twb3072+i));
+ }
+
+
+ if (scale==1) {
+ for (i=0; i<48; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+}
+
+
+int16_t twa6144[4096] __attribute__((aligned(32)));
+int16_t twb6144[4096] __attribute__((aligned(32)));
+
+void idft6144(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][2048] __attribute__((aligned(32)));
+ uint32_t tmpo[3][2048] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<2048; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ idft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("idft6144in.m","in",input,6144,1,1);
+ LOG_M("idft6144out0.m","o0",tmpo[0],2048,1,1);
+ LOG_M("idft6144out1.m","o1",tmpo[1],2048,1,1);
+ LOG_M("idft6144out2.m","o2",tmpo[2],2048,1,1);
+ }
+
+ for (i=0,i2=0; i<4096; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i),
+ (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i));
+ }
+
+
+ if (scale==1) {
+ for (i=0; i<96; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+
+ _mm_empty();
+ _m_empty();
+
+}
+
+
+void dft6144(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][2048] __attribute__((aligned(32)));
+ uint32_t tmpo[3][2048] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<2048; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ dft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ /*
+ for (i=1; i<2048; i++) {
+ tmpo[0][i] = tmpo[0][i<<1];
+ tmpo[1][i] = tmpo[1][i<<1];
+ tmpo[2][i] = tmpo[2][i<<1];
+ }*/
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("ft6144out0.m","o0",tmpo[0],2048,1,1);
+ LOG_M("ft6144out1.m","o1",tmpo[1],2048,1,1);
+ LOG_M("ft6144out2.m","o2",tmpo[2],2048,1,1);
+ }
+ for (i=0,i2=0; i<4096; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i),
+ (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i));
+ }
+
+ if (scale==1) {
+ for (i=0; i<96; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+ _mm_empty();
+ _m_empty();
+
+}
+
+int16_t twa9216[6144] __attribute__((aligned(32)));
+int16_t twb9216[6144] __attribute__((aligned(32)));
+// 3072 x 3
+void dft9216(int16_t *input, int16_t *output,uint8_t scale) {
+
+ AssertFatal(1==0,"Need to do this ..\n");
+}
+
+void idft9216(int16_t *input, int16_t *output,uint8_t scale) {
+
+ AssertFatal(1==0,"Need to do this ..\n");
+}
+
+int16_t twa12288[8192] __attribute__((aligned(32)));
+int16_t twb12288[8192] __attribute__((aligned(32)));
+// 4096 x 3
+void dft12288(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][4096] __attribute__((aligned(32)));
+ uint32_t tmpo[3][4096] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<4096; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+ dft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
+ dft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
+ dft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
+ /*
+ for (i=1; i<4096; i++) {
+ tmpo[0][i] = tmpo[0][i<<1];
+ tmpo[1][i] = tmpo[1][i<<1];
+ tmpo[2][i] = tmpo[2][i<<1];
+ }*/
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("dft12288out0.m","o0",tmpo[0],4096,1,1);
+ LOG_M("dft12288out1.m","o1",tmpo[1],4096,1,1);
+ LOG_M("dft12288out2.m","o2",tmpo[2],4096,1,1);
+ }
+ for (i=0,i2=0; i<8192; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i),
+ (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i));
+ }
+
+ if (scale==1) {
+ for (i=0; i<192; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+ _mm_empty();
+ _m_empty();
+
+}
+
+void idft12288(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][4096] __attribute__((aligned(32)));
+ uint32_t tmpo[3][4096] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<4096; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
+
+
+
+ idft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
+ idft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
+ idft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
+
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("idft12288in.m","in",input,12288,1,1);
+ LOG_M("idft12288out0.m","o0",tmpo[0],4096,1,1);
+ LOG_M("idft12288out1.m","o1",tmpo[1],4096,1,1);
+ LOG_M("idft12288out2.m","o2",tmpo[2],4096,1,1);
+ }
+
+ for (i=0,i2=0; i<8192; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i),
+ (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i));
+ }
+
+ if (scale==1) {
+ for (i=0; i<192; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
@@ -5564,49 +6429,89 @@ void idft3072(int16_t *input, int16_t *output,unsigned char scale)
y128p+=16;
}
}
-
_mm_empty();
_m_empty();
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("idft12288out.m","out",output,6144,1,1);
+ }
}
+int16_t twa18432[12288] __attribute__((aligned(32)));
+int16_t twb18432[12288] __attribute__((aligned(32)));
+// 6144 x 3
+void dft18432(int16_t *input, int16_t *output,unsigned char scale) {
-int16_t twa6144[4096] __attribute__((aligned(32)));
-int16_t twb6144[4096] __attribute__((aligned(32)));
-
-void idft6144(int16_t *input, int16_t *output,unsigned char scale)
-{
int i,i2,j;
- uint32_t tmp[3][2048] __attribute__((aligned(32)));
- uint32_t tmpo[3][2048] __attribute__((aligned(32)));
+ uint32_t tmp[3][6144] __attribute__((aligned(32)));
+ uint32_t tmpo[3][6144] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<2048; i++) {
+ for (i=0,j=0; i<6144; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- idft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- idft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- idft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+ dft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
+ dft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
+ dft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("idft6144in.m","in",input,6144,1,1);
- LOG_M("idft6144out0.m","o0",tmpo[0],2048,1,1);
- LOG_M("idft6144out1.m","o1",tmpo[1],2048,1,1);
- LOG_M("idft6144out2.m","o2",tmpo[2],2048,1,1);
+ for (i=0,i2=0; i<12288; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i),
+ (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i));
+ }
+ if (scale==1) {
+ for (i=0; i<288; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
}
+ _mm_empty();
+ _m_empty();
+}
- for (i=0,i2=0; i<4096; i+=8,i2+=4) {
- ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i),
- (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i));
+void idft18432(int16_t *input, int16_t *output,unsigned char scale) {
+
+ int i,i2,j;
+ uint32_t tmp[3][6144] __attribute__((aligned(32)));
+ uint32_t tmpo[3][6144] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
+
+ for (i=0,j=0; i<6144; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
}
+ idft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
+ idft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
+ idft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
+ for (i=0,i2=0; i<12288; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i),
+ (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i));
+ }
if (scale==1) {
- for (i=0; i<96; i++) {
+ for (i=0; i<288; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5626,50 +6531,51 @@ void idft6144(int16_t *input, int16_t *output,unsigned char scale)
y128p+=16;
}
}
-
_mm_empty();
_m_empty();
-
}
-void dft6144(int16_t *input, int16_t *output,unsigned char scale)
+int16_t twa24576[16384] __attribute__((aligned(32)));
+int16_t twb24576[16384] __attribute__((aligned(32)));
+// 8192 x 3
+void dft24576(int16_t *input, int16_t *output,unsigned char scale)
{
int i,i2,j;
- uint32_t tmp[3][2048] __attribute__((aligned(32)));
- uint32_t tmpo[3][2048] __attribute__((aligned(32)));
+ uint32_t tmp[3][8192] __attribute__((aligned(32)));
+ uint32_t tmpo[3][8192] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<2048; i++) {
+ for (i=0,j=0; i<8192; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- dft2048((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- dft2048((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- dft2048((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
-
+ dft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
/*
- for (i=1; i<2048; i++) {
+ for (i=1; i<8192; i++) {
tmpo[0][i] = tmpo[0][i<<1];
tmpo[1][i] = tmpo[1][i<<1];
tmpo[2][i] = tmpo[2][i<<1];
}*/
if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("ft6144out0.m","o0",tmpo[0],2048,1,1);
- LOG_M("ft6144out1.m","o1",tmpo[1],2048,1,1);
- LOG_M("ft6144out2.m","o2",tmpo[2],2048,1,1);
+ LOG_M("dft24576out0.m","o0",tmpo[0],8192,1,1);
+ LOG_M("dft24576out1.m","o1",tmpo[1],8192,1,1);
+ LOG_M("dft24576out2.m","o2",tmpo[2],8192,1,1);
}
- for (i=0,i2=0; i<4096; i+=8,i2+=4) {
+ for (i=0,i2=0; i<16384; i+=8,i2+=4) {
bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+4096+i),(simd_q15_t*)(output+8192+i),
- (simd_q15_t*)(twa6144+i),(simd_q15_t*)(twb6144+i));
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i),
+ (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i));
}
+
if (scale==1) {
- for (i=0; i<96; i++) {
+ for (i=0; i<384; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5691,61 +6597,106 @@ void dft6144(int16_t *input, int16_t *output,unsigned char scale)
}
_mm_empty();
_m_empty();
-
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("out.m","out",output,24576,1,1);
+ }
}
-int16_t twa9216[6144] __attribute__((aligned(32)));
-int16_t twb9216[6144] __attribute__((aligned(32)));
-// 3072 x 3
-void dft9216(int16_t *input, int16_t *output,uint8_t scale) {
+void idft24576(int16_t *input, int16_t *output,unsigned char scale)
+{
+ int i,i2,j;
+ uint32_t tmp[3][8192] __attribute__((aligned(32)));
+ uint32_t tmpo[3][8192] __attribute__((aligned(32)));
+ simd_q15_t *y128p=(simd_q15_t*)output;
+ simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- AssertFatal(1==0,"Need to do this ..\n");
-}
+ for (i=0,j=0; i<8192; i++) {
+ tmp[0][i] = ((uint32_t *)input)[j++];
+ tmp[1][i] = ((uint32_t *)input)[j++];
+ tmp[2][i] = ((uint32_t *)input)[j++];
+ }
-void idft9216(int16_t *input, int16_t *output,uint8_t scale) {
+ idft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("idft24576in.m","in",input,24576,1,1);
+ LOG_M("idft24576out0.m","o0",tmpo[0],8192,1,1);
+ LOG_M("idft24576out1.m","o1",tmpo[1],8192,1,1);
+ LOG_M("idft24576out2.m","o2",tmpo[2],8192,1,1);
+ }
- AssertFatal(1==0,"Need to do this ..\n");
+ for (i=0,i2=0; i<16384; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i),
+ (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i));
+ }
+ if (scale==1) {
+ for (i=0; i<384; i++) {
+ y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
+ y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
+ y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
+ y128p[3] = mulhi_int16(y128p[3],ONE_OVER_SQRT3_Q15_128);
+ y128p[4] = mulhi_int16(y128p[4],ONE_OVER_SQRT3_Q15_128);
+ y128p[5] = mulhi_int16(y128p[5],ONE_OVER_SQRT3_Q15_128);
+ y128p[6] = mulhi_int16(y128p[6],ONE_OVER_SQRT3_Q15_128);
+ y128p[7] = mulhi_int16(y128p[7],ONE_OVER_SQRT3_Q15_128);
+ y128p[8] = mulhi_int16(y128p[8],ONE_OVER_SQRT3_Q15_128);
+ y128p[9] = mulhi_int16(y128p[9],ONE_OVER_SQRT3_Q15_128);
+ y128p[10] = mulhi_int16(y128p[10],ONE_OVER_SQRT3_Q15_128);
+ y128p[11] = mulhi_int16(y128p[11],ONE_OVER_SQRT3_Q15_128);
+ y128p[12] = mulhi_int16(y128p[12],ONE_OVER_SQRT3_Q15_128);
+ y128p[13] = mulhi_int16(y128p[13],ONE_OVER_SQRT3_Q15_128);
+ y128p[14] = mulhi_int16(y128p[14],ONE_OVER_SQRT3_Q15_128);
+ y128p[15] = mulhi_int16(y128p[15],ONE_OVER_SQRT3_Q15_128);
+ y128p+=16;
+ }
+ }
+ _mm_empty();
+ _m_empty();
+
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("idft24576out.m","out",output,24576,1,1);
+ }
}
-int16_t twa12288[8192] __attribute__((aligned(32)));
-int16_t twb12288[8192] __attribute__((aligned(32)));
-// 4096 x 3
-void dft12288(int16_t *input, int16_t *output,unsigned char scale)
-{
+int16_t twa36864[24576] __attribute__((aligned(32)));
+int16_t twb36864[24576] __attribute__((aligned(32)));
+
+// 12288 x 3
+void dft36864(int16_t *input, int16_t *output,uint8_t scale) {
+
int i,i2,j;
- uint32_t tmp[3][4096] __attribute__((aligned(32)));
- uint32_t tmpo[3][4096] __attribute__((aligned(32)));
+ uint32_t tmp[3][12288] __attribute__((aligned(32)));
+ uint32_t tmpo[3][12288] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<4096; i++) {
+ for (i=0,j=0; i<12288; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- dft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
- dft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
- dft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
- /*
- for (i=1; i<4096; i++) {
- tmpo[0][i] = tmpo[0][i<<1];
- tmpo[1][i] = tmpo[1][i<<1];
- tmpo[2][i] = tmpo[2][i<<1];
- }*/
+ dft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+
if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("dft12288out0.m","o0",tmpo[0],4096,1,1);
- LOG_M("dft12288out1.m","o1",tmpo[1],4096,1,1);
- LOG_M("dft12288out2.m","o2",tmpo[2],4096,1,1);
+ LOG_M("dft36864out0.m","o0",tmpo[0],12288,1,1);
+ LOG_M("dft36864out1.m","o1",tmpo[1],12288,1,1);
+ LOG_M("dft36864out2.m","o2",tmpo[2],12288,1,1);
}
- for (i=0,i2=0; i<8192; i+=8,i2+=4) {
+
+ for (i=0,i2=0; i<24576; i+=8,i2+=4) {
bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i),
- (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i));
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i),
+ (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i));
}
if (scale==1) {
- for (i=0; i<192; i++) {
+ for (i=0; i<576; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5767,44 +6718,36 @@ void dft12288(int16_t *input, int16_t *output,unsigned char scale)
}
_mm_empty();
_m_empty();
-
+ if (LOG_DUMPFLAG(DEBUG_DFT)) {
+ LOG_M("out.m","out",output,36864,1,1);
+ }
}
-void idft12288(int16_t *input, int16_t *output,unsigned char scale)
-{
+void idft36864(int16_t *input, int16_t *output,uint8_t scale) {
+
int i,i2,j;
- uint32_t tmp[3][4096] __attribute__((aligned(32)));
- uint32_t tmpo[3][4096] __attribute__((aligned(32)));
+ uint32_t tmp[3][12288] __attribute__((aligned(32)));
+ uint32_t tmpo[3][12288] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<4096; i++) {
+ for (i=0,j=0; i<12288; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
+ idft12288((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft12288((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft12288((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
-
- idft4096((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
- idft4096((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
- idft4096((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
-
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("idft12288in.m","in",input,12288,1,1);
- LOG_M("idft12288out0.m","o0",tmpo[0],4096,1,1);
- LOG_M("idft12288out1.m","o1",tmpo[1],4096,1,1);
- LOG_M("idft12288out2.m","o2",tmpo[2],4096,1,1);
- }
-
- for (i=0,i2=0; i<8192; i+=8,i2+=4) {
+ for (i=0,i2=0; i<24576; i+=8,i2+=4) {
ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+8192+i),(simd_q15_t*)(output+16384+i),
- (simd_q15_t*)(twa12288+i),(simd_q15_t*)(twb12288+i));
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+24576+i),(simd_q15_t*)(output+49152+i),
+ (simd_q15_t*)(twa36864+i),(simd_q15_t*)(twb36864+i));
}
-
if (scale==1) {
- for (i=0; i<192; i++) {
+ for (i=0; i<576; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5826,39 +6769,37 @@ void idft12288(int16_t *input, int16_t *output,unsigned char scale)
}
_mm_empty();
_m_empty();
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("idft12288out.m","out",output,6144,1,1);
- }
}
-int16_t twa18432[12288] __attribute__((aligned(32)));
-int16_t twb18432[12288] __attribute__((aligned(32)));
-// 6144 x 3
-void dft18432(int16_t *input, int16_t *output,unsigned char scale) {
+int16_t twa49152[32768] __attribute__((aligned(32)));
+int16_t twb49152[32768] __attribute__((aligned(32)));
+
+// 16384 x 3
+void dft49152(int16_t *input, int16_t *output,uint8_t scale) {
int i,i2,j;
- uint32_t tmp[3][6144] __attribute__((aligned(32)));
- uint32_t tmpo[3][6144] __attribute__((aligned(32)));
+ uint32_t tmp[3][16384] __attribute__((aligned(32)));
+ uint32_t tmpo[3][16384] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<6144; i++) {
+ for (i=0,j=0; i<16384; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- dft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
- dft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
- dft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
+ dft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<12288; i+=8,i2+=4) {
- bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i),
- (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i));
+ for (i=0,i2=0; i<32768; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i),
+ (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i));
}
if (scale==1) {
- for (i=0; i<288; i++) {
+ for (i=0; i<768; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5880,33 +6821,34 @@ void dft18432(int16_t *input, int16_t *output,unsigned char scale) {
}
_mm_empty();
_m_empty();
+
}
-void idft18432(int16_t *input, int16_t *output,unsigned char scale) {
+void idft49152(int16_t *input, int16_t *output,uint8_t scale) {
- int i,i2,j;
- uint32_t tmp[3][6144] __attribute__((aligned(32)));
- uint32_t tmpo[3][6144] __attribute__((aligned(32)));
+ int i,i2,j;
+ uint32_t tmp[3][16384] __attribute__((aligned(32)));
+ uint32_t tmpo[3][16384] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<6144; i++) {
+ for (i=0,j=0; i<16384; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- idft6144((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),scale);
- idft6144((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),scale);
- idft6144((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),scale);
+ idft16384((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft16384((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft16384((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<12288; i+=8,i2+=4) {
- ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+12288+i),(simd_q15_t*)(output+24576+i),
- (simd_q15_t*)(twa18432+i),(simd_q15_t*)(twb18432+i));
+ for (i=0,i2=0; i<32768; i+=8,i2+=4) {
+ ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+32768+i),(simd_q15_t*)(output+65536+i),
+ (simd_q15_t*)(twa49152+i),(simd_q15_t*)(twb49152+i));
}
if (scale==1) {
- for (i=0; i<288; i++) {
+ for (i=0; i<768; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5930,47 +6872,48 @@ void idft18432(int16_t *input, int16_t *output,unsigned char scale) {
_m_empty();
}
+int16_t twa73728[49152] __attribute__((aligned(32)));
+int16_t twb73728[49152] __attribute__((aligned(32)));
+// 24576 x 3
+void dft73728(int16_t *input, int16_t *output,uint8_t scale) {
+
+ AssertFatal(1==0,"Need to do this ..\n");
+}
+
+void idft73728(int16_t *input, int16_t *output,uint8_t scale) {
+
+ AssertFatal(1==0,"Need to do this ..\n");
+}
+
+
+int16_t twa98304[65536] __attribute__((aligned(32)));
+int16_t twb98304[65536] __attribute__((aligned(32)));
+// 32768 x 3
+void dft98304(int16_t *input, int16_t *output,uint8_t scale) {
-int16_t twa24576[16384] __attribute__((aligned(32)));
-int16_t twb24576[16384] __attribute__((aligned(32)));
-// 8192 x 3
-void dft24576(int16_t *input, int16_t *output,unsigned char scale)
-{
int i,i2,j;
- uint32_t tmp[3][8192] __attribute__((aligned(32)));
- uint32_t tmpo[3][8192] __attribute__((aligned(32)));
+ uint32_t tmp[3][32768] __attribute__((aligned(32)));
+ uint32_t tmpo[3][32768] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<8192; i++) {
+ for (i=0,j=0; i<32768; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- dft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- dft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- dft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- /*
- for (i=1; i<8192; i++) {
- tmpo[0][i] = tmpo[0][i<<1];
- tmpo[1][i] = tmpo[1][i<<1];
- tmpo[2][i] = tmpo[2][i<<1];
- }*/
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("dft24576out0.m","o0",tmpo[0],8192,1,1);
- LOG_M("dft24576out1.m","o1",tmpo[1],8192,1,1);
- LOG_M("dft24576out2.m","o2",tmpo[2],8192,1,1);
- }
- for (i=0,i2=0; i<16384; i+=8,i2+=4) {
- bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),(simd_q15_t*)(&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i),
- (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i));
- }
-
+ dft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ dft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ dft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
+ for (i=0,i2=0; i<65536; i+=8,i2+=4) {
+ bfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i),
+ (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i));
+ }
if (scale==1) {
- for (i=0; i<384; i++) {
+ for (i=0; i<1536; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -5992,43 +6935,34 @@ void dft24576(int16_t *input, int16_t *output,unsigned char scale)
}
_mm_empty();
_m_empty();
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("out.m","out",output,24576,1,1);
- }
+
}
-void idft24576(int16_t *input, int16_t *output,unsigned char scale)
-{
+void idft98304(int16_t *input, int16_t *output,uint8_t scale) {
+
int i,i2,j;
- uint32_t tmp[3][8192] __attribute__((aligned(32)));
- uint32_t tmpo[3][8192] __attribute__((aligned(32)));
+ uint32_t tmp[3][32768] __attribute__((aligned(32)));
+ uint32_t tmpo[3][32768] __attribute__((aligned(32)));
simd_q15_t *y128p=(simd_q15_t*)output;
simd_q15_t ONE_OVER_SQRT3_Q15_128 = set1_int16(ONE_OVER_SQRT3_Q15);
- for (i=0,j=0; i<8192; i++) {
+ for (i=0,j=0; i<32768; i++) {
tmp[0][i] = ((uint32_t *)input)[j++];
tmp[1][i] = ((uint32_t *)input)[j++];
tmp[2][i] = ((uint32_t *)input)[j++];
}
- idft8192((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
- idft8192((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
- idft8192((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
-
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("idft24576in.m","in",input,24576,1,1);
- LOG_M("idft24576out0.m","o0",tmpo[0],8192,1,1);
- LOG_M("idft24576out1.m","o1",tmpo[1],8192,1,1);
- LOG_M("idft24576out2.m","o2",tmpo[2],8192,1,1);
- }
+ idft32768((int16_t*)(tmp[0]),(int16_t*)(tmpo[0]),1);
+ idft32768((int16_t*)(tmp[1]),(int16_t*)(tmpo[1]),1);
+ idft32768((int16_t*)(tmp[2]),(int16_t*)(tmpo[2]),1);
- for (i=0,i2=0; i<16384; i+=8,i2+=4) {
+ for (i=0,i2=0; i<65536; i+=8,i2+=4) {
ibfly3((simd_q15_t*)(&tmpo[0][i2]),(simd_q15_t*)(&tmpo[1][i2]),((simd_q15_t*)&tmpo[2][i2]),
- (simd_q15_t*)(output+i),(simd_q15_t*)(output+16384+i),(simd_q15_t*)(output+32768+i),
- (simd_q15_t*)(twa24576+i),(simd_q15_t*)(twb24576+i));
+ (simd_q15_t*)(output+i),(simd_q15_t*)(output+65536+i),(simd_q15_t*)(output+131072+i),
+ (simd_q15_t*)(twa98304+i),(simd_q15_t*)(twb98304+i));
}
if (scale==1) {
- for (i=0; i<384; i++) {
+ for (i=0; i<1536; i++) {
y128p[0] = mulhi_int16(y128p[0],ONE_OVER_SQRT3_Q15_128);
y128p[1] = mulhi_int16(y128p[1],ONE_OVER_SQRT3_Q15_128);
y128p[2] = mulhi_int16(y128p[2],ONE_OVER_SQRT3_Q15_128);
@@ -6050,62 +6984,6 @@ void idft24576(int16_t *input, int16_t *output,unsigned char scale)
}
_mm_empty();
_m_empty();
-
- if (LOG_DUMPFLAG(DEBUG_DFT)) {
- LOG_M("idft24576out.m","out",output,24576,1,1);
- }
-}
-
-int16_t twa36864[24576] __attribute__((aligned(32)));
-int16_t twb36884[24576] __attribute__((aligned(32)));
-// 12288 x 3
-void dft36864(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-void idft36864(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-int16_t twa49152[32768] __attribute__((aligned(32)));
-int16_t twb49152[32768] __attribute__((aligned(32)));
-// 16384 x 3
-void dft49152(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-void idft49152(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-int16_t twa73728[49152] __attribute__((aligned(32)));
-int16_t twb73728[49152] __attribute__((aligned(32)));
-// 24576 x 3
-void dft73728(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-void idft73728(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-
-int16_t twa98304[49152] __attribute__((aligned(32)));
-int16_t twb98304[49152] __attribute__((aligned(32)));
-// 32768 x 3
-void dft98304(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
-}
-
-void idft98304(int16_t *input, int16_t *output,uint8_t scale) {
-
- AssertFatal(1==0,"Need to do this ..\n");
}
@@ -8720,6 +9598,8 @@ int dfts_autoinit(void)
init_rad2(2048,tw2048);
init_rad4(4096,tw4096);
init_rad2(8192,tw8192);
+ init_rad4(16384,tw16384);
+ init_rad2(32768,tw32768);
init_rad3(1536,twa1536,twb1536);
init_rad3(3072,twa3072,twb3072);
@@ -8727,6 +9607,10 @@ int dfts_autoinit(void)
init_rad3(12288,twa12288,twb12288);
init_rad3(18432,twa18432,twb18432);
init_rad3(24576,twa24576,twb24576);
+ init_rad3(36864,twa36864,twb36864);
+ init_rad3(49152,twa49152,twb49152);
+ init_rad3(98304,twa98304,twb98304);
+
init_rad2_rep(24,tw24);
init_rad3_rep(36,twa36,twb36);
@@ -8766,6 +9650,7 @@ int dfts_autoinit(void)
+#ifndef MR_MAIN
void dft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){
AssertFatal((sizeidx>=0 && sizeidx<(int)DFT_SIZE_IDXTABLESIZE),"Invalid dft size index %i\n",sizeidx);
@@ -8776,6 +9661,7 @@ void idft(uint8_t sizeidx, int16_t *sigF,int16_t *sig,unsigned char scale_flag){
AssertFatal((sizeidx>=0 && sizeidx<(int)IDFT_SIZE_IDXTABLESIZE),"Invalid idft size index %i\n",sizeidx);
idft_ftab[sizeidx](sigF,sig,scale_flag);
};
+#endif
/*---------------------------------------------------------------------------------------*/
@@ -8946,9 +9832,9 @@ int main(int argc, char**argv)
time_stats_t ts;
#ifdef __AVX2__
- simd256_q15_t x[4096],x2[4096],y[4096],tw0,tw1,tw2,tw3;
+ simd256_q15_t x[16384],x2[16384],y[16384],tw0,tw1,tw2,tw3;
#else
- simd_q15_t x[8192],y[8192],tw0,tw1,tw2,tw3;
+ simd_q15_t x[32768],y[32768],tw0,tw1,tw2,tw3;
#endif
int i;
simd_q15_t *x128=(simd_q15_t*)x,*y128=(simd_q15_t*)y;
@@ -9510,10 +10396,34 @@ int main(int argc, char**argv)
stop_meas(&ts);
}
- printf("\n\n1536-point(%f cycles)\n",(double)ts.diff/(double)ts.trials);
+ printf("\n\n8192-point(%f cycles)\n",(double)ts.diff/(double)ts.trials);
LOG_M("y8192.m","y8192",y,8192,1,1);
LOG_M("x8192.m","x8192",x,8192,1,1);
+ memset((void*)x,0,16384*sizeof(int32_t));
+ for (i=2;i<9602;i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ for (i=2*(16384-4800);i<32768;i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ reset_meas(&ts);
+ for (i=0; i<10000; i++) {
+ start_meas(&ts);
+ dft16384((int16_t *)x,(int16_t *)y,1);
+ stop_meas(&ts);
+ }
+
+ printf("\n\n16384-point(%f cycles)\n",(double)ts.diff/(double)ts.trials);
+ LOG_M("y16384.m","y16384",y,16384,1,1);
+ LOG_M("x16384.m","x16384",x,16384,1,1);
+
memset((void*)x,0,1536*sizeof(int32_t));
for (i=2;i<1202;i++) {
if ((taus() & 1)==0)
@@ -9662,6 +10572,56 @@ int main(int argc, char**argv)
LOG_M("y24576.m","y24576",y,24576,1,1);
LOG_M("x24576.m","x24576",x,24576,1,1);
+
+ memset((void*)x,0,2*18432*sizeof(int32_t));
+ for (i=2;i<(2*14402);i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ for (i=2*(36864-14400);i<(36864*2);i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ reset_meas(&ts);
+ for (i=0; i<10000; i++) {
+ start_meas(&ts);
+ dft36864((int16_t *)x,(int16_t *)y,1);
+ stop_meas(&ts);
+ }
+
+ printf("\n\n36864-point(%f cycles)\n",(double)ts.diff/(double)ts.trials);
+ LOG_M("y36864.m","y36864",y,36864,1,1);
+ LOG_M("x36864.m","x36864",x,36864,1,1);
+
+
+ memset((void*)x,0,49152*sizeof(int32_t));
+ for (i=2;i<28402;i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ for (i=2*(49152-14400);i<98304;i++) {
+ if ((taus() & 1)==0)
+ ((int16_t*)x)[i] = 364;
+ else
+ ((int16_t*)x)[i] = -364;
+ }
+ reset_meas(&ts);
+ for (i=0; i<10000; i++) {
+ start_meas(&ts);
+ idft49152((int16_t *)x,(int16_t *)y,1);
+ stop_meas(&ts);
+ }
+
+ printf("\n\n49152-point(%f cycles)\n",(double)ts.diff/(double)ts.trials);
+ LOG_M("y49152.m","y49152",y,49152,1,1);
+ LOG_M("x49152.m","x49152",x,49152,1,1);
+ /*
int dftsizes[33]={24,36,48,60,72,96,108,120,144,180,192,216,240,288,300,324,360,384,432,480,540,576,600,648,720,768,864,900,960,972,1080,1152,1200};
void (*dft)(int16_t *x,int16_t *y,uint8_t scale)[33] = {dft24,dft36,dft48,dft60,dft72,dft96,dft108,dft120,dft144,dft180,dft192,dft216,dft240,dft288,dft300,dft324,dft360,dft384,dft432,dft480,dft540,dft576,dft600,dft648,dft720,dft768,dft864,dft900,dft960,dft972,dft1080,dft1152,dft1200};
for (int n=0;n<33;n++) {
@@ -9694,7 +10654,7 @@ int main(int argc, char**argv)
LOG_M(ystr,ystr2,y,dftsizes[n]*4,1,1);
LOG_M(xstr,xstr2,x,dftsizes[n]*4,1,1);
}
-
+ */
return(0);
}
diff --git a/openair1/PHY/TOOLS/phy_scope_interface.c b/openair1/PHY/TOOLS/phy_scope_interface.c
index 835fb4ea7b2a028f4ddfb378c3c877b699b6bc27..af237b2325e8a3f2fc035478cff4df4f39974901 100644
--- a/openair1/PHY/TOOLS/phy_scope_interface.c
+++ b/openair1/PHY/TOOLS/phy_scope_interface.c
@@ -37,10 +37,10 @@
#define SOFTSCOPE_ENDFUNC_IDX 0
static loader_shlibfunc_t scope_fdesc[]= {{"end_forms",NULL}};
-int load_softscope(char *exectype) {
+int load_softscope(char *exectype, void *initarg) {
char libname[64];
sprintf(libname,"%.10sscope",exectype);
- return load_module_shlib(libname,scope_fdesc,1,NULL);
+ return load_module_shlib(libname,scope_fdesc,1,initarg);
}
int end_forms(void) {
diff --git a/openair1/PHY/TOOLS/phy_scope_interface.h b/openair1/PHY/TOOLS/phy_scope_interface.h
index 779a57a7202450327cc8d515066191f48e373613..adf04d5ea4a6a7f664e23eab35c8bff82d46121e 100644
--- a/openair1/PHY/TOOLS/phy_scope_interface.h
+++ b/openair1/PHY/TOOLS/phy_scope_interface.h
@@ -31,5 +31,5 @@
*/
-int load_softscope(char *exectype);
+int load_softscope(char *exectype, void *initarg);
int end_forms(void) ;
diff --git a/openair1/PHY/TOOLS/readme.md b/openair1/PHY/TOOLS/readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..f6671acc6df14e006c428e6b603d01eced07daa3
--- /dev/null
+++ b/openair1/PHY/TOOLS/readme.md
@@ -0,0 +1,12 @@
+
+To use the scope, run the xNB or the UE with option "-d"
+
+Usage in gdb
+In gdb, when you break, you can refresh immediatly the scope view by calling the display function.
+The first paramter is the graph context, nevertheless we keep the last value for a dirty call in gdb (so you can use '0')
+
+Example with no variable known
+phy_scope_nrUE(0, PHY_vars_UE_g[0][0], 0, 0, 0)
+
+or
+phy_scope_gNB(0, phy_vars_gnb, phy_vars_ru, UE_id)
diff --git a/openair1/PHY/TOOLS/smbv.h b/openair1/PHY/TOOLS/smbv.h
index ef40a9ed7d08e27817430e622ecc056e36b0c48a..f8fab67d0146cd55b5efbb45599ef08375b575ee 100644
--- a/openair1/PHY/TOOLS/smbv.h
+++ b/openair1/PHY/TOOLS/smbv.h
@@ -23,6 +23,8 @@
This library offers some functions to remotely program the R&S SMBV100A.
*/
+#ifndef __PHY_TOOLS_SMBV__H__
+#define __PHY_TOOLS_SMBV__H__
#include <string.h>
#include <stdio.h>
@@ -93,3 +95,4 @@ int smbv_configure_common_dci(const char* fname, uint8_t subframe, const char* t
// item is the row in the DCI table
int smbv_configure_ue_spec_dci(const char* fname, uint8_t subframe, uint8_t user, DCI_ALLOC_t *dci_alloc, uint8_t item);
#endif
+#endif
diff --git a/openair1/PHY/TOOLS/tools_defs.h b/openair1/PHY/TOOLS/tools_defs.h
index 86916cab21b4021cdb1e7e174b177992010d6053..9c9b8aa821c3fe1a795246686f04caff3f159738 100644
--- a/openair1/PHY/TOOLS/tools_defs.h
+++ b/openair1/PHY/TOOLS/tools_defs.h
@@ -183,11 +183,6 @@ This function performs optimized fixed-point radix-2 FFT/IFFT.
-
-
-
-
-
#ifdef OAIDFTS_MAIN
typedef void(*adftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag);
typedef void(*aidftfunc_t)(int16_t *sigF,int16_t *sig,unsigned char scale_flag);
diff --git a/openair1/PHY/defs_L1_NB_IoT.h b/openair1/PHY/defs_L1_NB_IoT.h
index f0fd7661c718f15df967e4ddddd482b3a016cacf..1f8c0b8eeec1cd73e7c51966c97eda05e8b807d4 100644
--- a/openair1/PHY/defs_L1_NB_IoT.h
+++ b/openair1/PHY/defs_L1_NB_IoT.h
@@ -148,11 +148,7 @@ static inline void* malloc16_clear( size_t size )
#define NB_BANDS_MAX_NB_IoT 8
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
typedef enum {normal_txrx_NB_IoT=0,rx_calib_ue_NB_IoT=1,rx_calib_ue_med_NB_IoT=2,rx_calib_ue_byp_NB_IoT=3,debug_prach_NB_IoT=4,no_L2_connect_NB_IoT=5,calib_prach_tx_NB_IoT=6,rx_dump_frame_NB_IoT=7,loop_through_memory_NB_IoT=8} runmode_NB_IoT_t;
-#endif
/*
enum transmission_access_mode {
NO_ACCESS=0,
diff --git a/openair1/PHY/defs_RU.h b/openair1/PHY/defs_RU.h
index 2fd4d0ea663d0c9fc6045ab40598ea1e6b56383a..b8083b5ecfd566bf313f6cf76ae31ba21a017a27 100644
--- a/openair1/PHY/defs_RU.h
+++ b/openair1/PHY/defs_RU.h
@@ -38,16 +38,12 @@
#include "openairinterface5g_limits.h"
#include "PHY/TOOLS/time_meas.h"
#include "defs_common.h"
-#include <openair2/PHY_INTERFACE/IF_Module.h>
-
+#include "nfapi_nr_interface_scf.h"
#define MAX_BANDS_PER_RRU 4
#define MAX_RRU_CONFIG_SIZE 1024
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
typedef enum {
normal_txrx=0,
@@ -93,7 +89,6 @@ typedef enum {
synch_to_other, // synch to another source_(timer, other RU)
synch_to_mobipass_standalone // special case for mobipass in standalone mode
} node_timing_t;
-#endif
typedef struct {
@@ -190,6 +185,16 @@ typedef struct RU_feptx_t_s{
int index;
}RU_feptx_t;
+typedef struct {
+ int frame;
+ int slot;
+ int fmt;
+ int numRA;
+ int prachStartSymbol;
+} RU_PRACH_list_t;
+
+#define NUMBER_OF_NR_RU_PRACH_MAX 8
+
typedef struct RU_proc_t_s {
/// Pointer to associated RU descriptor
struct RU_t_s *ru;
@@ -481,6 +486,8 @@ typedef struct RU_t_s {
int att_tx;
/// flag to indicate precoding operation in RU
int do_precoding;
+ /// FAPI confiuration
+ nfapi_nr_config_request_scf_t config;
/// Frame parameters
struct LTE_DL_FRAME_PARMS *frame_parms;
struct NR_DL_FRAME_PARMS *nr_frame_parms;
@@ -541,6 +548,8 @@ typedef struct RU_t_s {
void (*wakeup_prach_gNB)(struct PHY_VARS_gNB_s *gNB, struct RU_t_s *ru, int frame, int subframe);
/// function pointer to wakeup routine in lte-enb.
void (*wakeup_prach_eNB_br)(struct PHY_VARS_eNB_s *eNB, struct RU_t_s *ru, int frame, int subframe);
+ /// function pointer to start a thread of tx write for USRP.
+ int (*start_write_thread)(struct RU_t_s *ru);
/// function pointer to NB entry routine
void (*eNB_top)(struct PHY_VARS_eNB_s *eNB, int frame_rx, int subframe_rx, char *string, struct RU_t_s *ru);
@@ -581,6 +590,10 @@ typedef struct RU_t_s {
int32_t *bw_list[NUMBER_OF_eNB_MAX+1];
/// beamforming weight vectors
int32_t **beam_weights[NUMBER_OF_eNB_MAX+1][15];
+ /// prach commands
+ RU_PRACH_list_t prach_list[NUMBER_OF_NR_RU_PRACH_MAX];
+ /// mutex for prach_list access
+ pthread_mutex_t prach_list_mutex;
/// received frequency-domain signal for PRACH (IF4p5 RRU)
int16_t **prach_rxsigF;
/// received frequency-domain signal for PRACH BR (IF4p5 RRU)
diff --git a/openair1/PHY/defs_common.h b/openair1/PHY/defs_common.h
index f52558b63203e2bbb337a71d07ef7ff199448000..75b2d54dc6933ffa507d3df7544f68f4ceb14b3b 100644
--- a/openair1/PHY/defs_common.h
+++ b/openair1/PHY/defs_common.h
@@ -99,9 +99,6 @@
#define NB_RX_ANTENNAS_MAX 64
-#ifdef OCP_FRAMEWORK
-#include "enums.h"
-#else
typedef enum {TDD=1,FDD=0} lte_frame_type_t;
@@ -122,7 +119,6 @@ typedef enum {
one=6,
two=12
} PHICH_RESOURCE_t;
-#endif
/// PHICH-Config from 36.331 RRC spec
typedef struct {
/// Parameter: PHICH-Duration, see TS 36.211 (Table 6.9.3-1).
@@ -250,12 +246,10 @@ typedef struct {
} UL_REFERENCE_SIGNALS_PUSCH_t;
/// Enumeration for parameter Hopping-mode \ref PUSCH_CONFIG_COMMON::hoppingMode.
-#ifndef OCP_FRAMEWORK
typedef enum {
interSubFrame=0,
intraAndInterSubFrame=1
} PUSCH_HOPPING_t;
-#endif
/// PUSCH-ConfigCommon from 36.331 RRC spec.
typedef struct {
@@ -434,7 +428,6 @@ typedef struct {
uint8_t filterCoefficient;
} UL_POWER_CONTROL_DEDICATED;
-#ifndef OCP_FRAMEWORK
/// Enumeration for parameter \f$\alpha\f$ \ref UL_POWER_CONTROL_CONFIG_COMMON::alpha.
typedef enum {
al0=0,
@@ -446,7 +439,6 @@ typedef enum {
al09=6,
al1=7
} PUSCH_alpha_t;
-#endif
/// \note UNUSED
typedef enum {
diff --git a/openair1/PHY/defs_gNB.h b/openair1/PHY/defs_gNB.h
index 7dbb2e796bb9b46eae2949d999e133890c62a3a1..e2cdebff3ad345c91d5e4144f316e03190694ace 100644
--- a/openair1/PHY/defs_gNB.h
+++ b/openair1/PHY/defs_gNB.h
@@ -43,7 +43,17 @@
#include "PHY/CODING/nrLDPC_extern.h"
#include "PHY/CODING/nrLDPC_decoder/nrLDPC_types.h"
+#include "nfapi_nr_interface_scf.h"
+
#define MAX_NUM_RU_PER_gNB MAX_NUM_RU_PER_eNB
+#define MAX_PUCCH0_NID 8
+
+typedef struct {
+ int nb_id;
+ int Nid[MAX_PUCCH0_NID];
+ int lut[MAX_PUCCH0_NID][160][14];
+} NR_gNB_PUCCH0_LUT_t;
+
typedef struct {
uint32_t pbch_a;
@@ -148,6 +158,14 @@ typedef struct {
int16_t sqrt_rho_b;
} NR_gNB_DLSCH_t;
+typedef struct {
+ int frame;
+ int slot;
+ nfapi_nr_prach_pdu_t pdu;
+} gNB_PRACH_list_t;
+
+#define NUMBER_OF_NR_PRACH_MAX 8
+
typedef struct {
/// \brief ?.
/// first index: ? [0..1023] (hard coded)
@@ -158,6 +176,7 @@ typedef struct {
int16_t **rxsigF;
/// \brief local buffer to compute prach_ifft
int32_t *prach_ifft;
+ gNB_PRACH_list_t list[NUMBER_OF_NR_PRACH_MAX];
} NR_gNB_PRACH;
typedef struct {
@@ -165,8 +184,8 @@ typedef struct {
nfapi_nr_pusch_pdu_t ulsch_pdu;
/// Frame where current HARQ round was sent
uint32_t frame;
- /// Subframe where current HARQ round was sent
- uint32_t subframe;
+ /// Slot where current HARQ round was sent
+ uint32_t slot;
/// Index of current HARQ round for this DLSCH
uint8_t round;
/// Last TPC command
@@ -321,6 +340,15 @@ typedef struct {
uint16_t cba_rnti[NUM_MAX_CBA_GROUP];
} NR_gNB_ULSCH_t;
+typedef struct {
+ uint8_t active;
+ /// Frame where current PUCCH pdu was sent
+ uint32_t frame;
+ /// Slot where current PUCCH pdu was sent
+ uint32_t slot;
+ /// ULSCH PDU
+ nfapi_nr_pucch_pdu_t pucch_pdu;
+} NR_gNB_PUCCH_t;
typedef struct {
/// \brief Pointers (dynamic) to the received data in the time domain.
@@ -561,13 +589,13 @@ typedef struct {
//! estimated avg noise power (dB)
short n0_power_tot_dBm;
//! estimated avg noise power per RB per RX ant (lin)
- unsigned short n0_subband_power[MAX_NUM_RU_PER_gNB][100];
+ unsigned short n0_subband_power[MAX_NUM_RU_PER_gNB][275];
//! estimated avg noise power per RB per RX ant (dB)
- unsigned short n0_subband_power_dB[MAX_NUM_RU_PER_gNB][100];
+ unsigned short n0_subband_power_dB[MAX_NUM_RU_PER_gNB][275];
//! estimated avg noise power per RB (dB)
- short n0_subband_power_tot_dB[100];
+ short n0_subband_power_tot_dB[275];
//! estimated avg noise power per RB (dBm)
- short n0_subband_power_tot_dBm[100];
+ short n0_subband_power_tot_dBm[275];
// gNB measurements (per user)
//! estimated received spatial signal power (linear)
unsigned int rx_spatial_power[NUMBER_OF_NR_DLSCH_MAX][2][2];
@@ -587,22 +615,22 @@ typedef struct {
/// Wideband CQI (sum of all RX antennas, in dB)
char wideband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX];
/// Subband CQI per RX antenna and RB (= SINR)
- int subband_cqi[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][100];
+ int subband_cqi[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][275];
/// Total Subband CQI and RB (= SINR)
- int subband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX][100];
+ int subband_cqi_tot[NUMBER_OF_NR_DLSCH_MAX][275];
/// Subband CQI in dB and RB (= SINR dB)
- int subband_cqi_dB[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][100];
+ int subband_cqi_dB[NUMBER_OF_NR_DLSCH_MAX][MAX_NUM_RU_PER_gNB][275];
/// Total Subband CQI and RB
- int subband_cqi_tot_dB[NUMBER_OF_NR_DLSCH_MAX][100];
+ int subband_cqi_tot_dB[NUMBER_OF_NR_DLSCH_MAX][275];
/// PRACH background noise level
int prach_I0;
} PHY_MEASUREMENTS_gNB;
#define MAX_NUM_NR_RX_RACH_PDUS 4
#define MAX_NUM_NR_RX_PRACH_PREAMBLES 4
-#define MAX_UL_PDUS_PER_SLOT 100
-#define MAX_NUM_NR_SRS_PDUS 100
-#define MAX_NUM_NR_UCI_PDUS 100
+#define MAX_UL_PDUS_PER_SLOT 8
+#define MAX_NUM_NR_SRS_PDUS 8
+#define MAX_NUM_NR_UCI_PDUS 8
/// Top-level PHY Data Structure for gNB
typedef struct PHY_VARS_gNB_s {
@@ -644,6 +672,7 @@ typedef struct PHY_VARS_gNB_s {
//Sched_Rsp_t Sched_INFO;
nfapi_nr_ul_tti_request_t UL_tti_req;
+ nfapi_nr_uci_indication_t uci_indication;
nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu;
nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu;
@@ -655,13 +684,18 @@ typedef struct PHY_VARS_gNB_s {
NR_gNB_COMMON common_vars;
NR_gNB_PRACH prach_vars;
NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX];
+ NR_gNB_PUCCH_t *pucch[NUMBER_OF_NR_PUCCH_MAX];
NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams
NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords]
NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p;
NR_gNB_DLSCH_t *dlsch_PCH;
+ t_nrPolar_params *uci_polarParams;
+
uint8_t pbch_configured;
char gNB_generate_rar;
+ // PUCCH0 Look-up table for cyclic-shifts
+ NR_gNB_PUCCH0_LUT_t pucch0_lut;
/// NR synchronization sequences
int16_t d_pss[NR_PSS_LENGTH];
int16_t d_sss[NR_SSS_LENGTH];
@@ -713,6 +747,7 @@ typedef struct PHY_VARS_gNB_s {
/// counter to average prach energh over first 100 prach opportunities
int prach_energy_counter;
+ int pucch0_thres;
/*
time_stats_t phy_proc;
*/
diff --git a/openair1/PHY/defs_nr_UE.h b/openair1/PHY/defs_nr_UE.h
index 6f6c5ac8e9a4696e5dd2103f269b4f59b8beb49a..9bdf892ceb41e3e95dccb7e21a358ef3345ebf2b 100644
--- a/openair1/PHY/defs_nr_UE.h
+++ b/openair1/PHY/defs_nr_UE.h
@@ -782,6 +782,8 @@ typedef struct {
int16_t amp;
int16_t *prachF;
int16_t *prach;
+ fapi_nr_ul_config_prach_pdu prach_pdu;
+ uint8_t prach_Config_enabled;
} NR_UE_PRACH;
// structure used for multiple SSB detection
@@ -882,8 +884,6 @@ typedef struct {
fapi_nr_config_request_t nrUE_config;
- uint16_t frame_gap;
-
// the following structures are not part of PHY_vars_UE anymore as it is not thread safe. They are now on the stack of the functions that actually need them
//nr_downlink_indication_t dl_indication;
@@ -930,7 +930,7 @@ typedef struct {
uint8_t pucch_sel[10];
uint8_t pucch_payload[22];
- UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_eNB_MAX];
+ UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX];
/// cell-specific reference symbols
uint32_t lte_gold_table[7][20][2][14];
@@ -954,9 +954,6 @@ typedef struct {
/// PUSCH DMRS sequence
uint32_t ****nr_gold_pusch_dmrs;
- /// flag to indicate if PTRS is configured
- uint8_t ptrs_configured;
-
uint32_t X_u[64][839];
uint32_t high_speed_flag;
@@ -968,12 +965,13 @@ typedef struct {
char ulsch_no_allocation_counter[NUMBER_OF_CONNECTED_eNB_MAX];
+ unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_gNB_MAX];
+ uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_gNB_MAX];
+ unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_gNB_MAX];
+ uint8_t Msg3_startSymbol[NUMBER_OF_CONNECTED_gNB_MAX];
+ uint8_t Msg3_Length[NUMBER_OF_CONNECTED_gNB_MAX];
-
- unsigned char ulsch_Msg3_active[NUMBER_OF_CONNECTED_eNB_MAX];
- uint32_t ulsch_Msg3_frame[NUMBER_OF_CONNECTED_eNB_MAX];
- unsigned char ulsch_Msg3_subframe[NUMBER_OF_CONNECTED_eNB_MAX];
- PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_eNB_MAX];
+ NR_PRACH_RESOURCES_t *prach_resources[NUMBER_OF_CONNECTED_gNB_MAX];
int turbo_iterations, turbo_cntl_iterations;
/// \brief ?.
/// - first index: eNB [0..NUMBER_OF_CONNECTED_eNB_MAX[ (hard coded)
@@ -1008,8 +1006,6 @@ typedef struct {
int dlsch_mtch_trials[MAX_MBSFN_AREA][NUMBER_OF_CONNECTED_eNB_MAX];
int current_dlsch_cqi[NUMBER_OF_CONNECTED_eNB_MAX];
unsigned char first_run_timing_advance[NUMBER_OF_CONNECTED_eNB_MAX];
- uint8_t generate_prach;
- uint8_t generate_nr_prach;
uint8_t prach_cnt;
uint8_t prach_PreambleIndex;
// uint8_t prach_timer;
diff --git a/openair1/PHY/defs_nr_common.h b/openair1/PHY/defs_nr_common.h
index ccc79b7d47a09312684d6a4fcc23ee1b55606e00..584962c55c6234486acd0d09d9318dc9a2faaf50 100644
--- a/openair1/PHY/defs_nr_common.h
+++ b/openair1/PHY/defs_nr_common.h
@@ -198,30 +198,34 @@ typedef struct {
nr_reg_t reg_list[NR_NB_REG_PER_CCE];
} nr_cce_t;
-
-/// PRACH-ConfigInfo from 38.331 RRC spec
-typedef struct {
- /// Parameter: prach-ConfigurationIndex, see TS 38.211 (6.3.3.2).
- uint8_t prach_ConfigIndex;
- /// Parameter: High-speed-flag, see TS 38.211 (6.3.3.1). 1 corresponds to Restricted set and 0 to Unrestricted set.
- uint8_t highSpeedFlag;
- /// Restricted Set Config (type A=0 , type B=1) TS 38.211 (6.3.3.1)
- uint8_t restrictedSetConfig;
- /// 38.211 (NCS 38.211 6.3.3.1).
- uint8_t zeroCorrelationZoneConfig;
- /// see TS 38.211 (6.3.3.2).
- uint8_t msg1_frequencystart;
-} NR_PRACH_CONFIG_INFO;
-
-/// PRACH-ConfigSIB or PRACH-Config
typedef struct {
- /// Parameter: prach-rootSequenceIndex, see TS 38.211 (6.3.3.2).
- uint16_t rootSequenceIndex;
- /// prach_Config_enabled=1 means enabled.}
- uint8_t prach_Config_enabled;
- /// PRACH Configuration Information
- NR_PRACH_CONFIG_INFO prach_ConfigInfo;
-} NR_PRACH_CONFIG_COMMON;
+ /// PRACH format retrieved from prach_ConfigIndex
+ uint16_t prach_format;
+ /// Preamble index for PRACH (0-63)
+ uint8_t ra_PreambleIndex;
+ /// RACH MaskIndex
+ uint8_t ra_RACH_MaskIndex;
+ /// Target received power at gNB. Baseline is range -202..-60 dBm. Depends on delta preamble, power ramping counter and step.
+ int ra_PREAMBLE_RECEIVED_TARGET_POWER;
+ /// PRACH index for TDD (0 ... 6) depending on TDD configuration and prachConfigIndex
+ uint8_t ra_TDD_map_index;
+ /// RA Preamble Power Ramping Step in dB
+ uint32_t RA_PREAMBLE_POWER_RAMPING_STEP;
+ ///
+ uint8_t RA_PREAMBLE_BACKOFF;
+ ///
+ uint8_t RA_SCALING_FACTOR_BI;
+ ///
+ uint8_t RA_PCMAX;
+ /// Corresponding RA-RNTI for UL-grant
+ uint16_t ra_RNTI;
+ /// Pointer to Msg3 payload for UL-grant
+ uint8_t *Msg3;
+ /// Frame of last completed synch
+ uint8_t sync_frame;
+ /// Flag to indicate that prach is ready to start: it is enabled with an initial delay after the sync
+ uint8_t init_msg1;
+} NR_PRACH_RESOURCES_t;
typedef struct NR_DL_FRAME_PARMS NR_DL_FRAME_PARMS;
@@ -313,8 +317,6 @@ struct NR_DL_FRAME_PARMS {
uint8_t nb_antennas_rx;
/// Number of common transmit antenna ports in eNodeB (1 or 2)
uint8_t nb_antenna_ports_gNB;
- /// PRACH_CONFIG
- NR_PRACH_CONFIG_COMMON prach_config_common;
/// Cyclic Prefix for DL (0=Normal CP, 1=Extended CP)
lte_prefix_type_t Ncp;
/// shift of pilot position in one RB
@@ -350,9 +352,10 @@ struct NR_DL_FRAME_PARMS {
uint8_t ssb_index;
/// PBCH polar encoder params
t_nrPolar_params pbch_polar_params;
-
};
+
+
#define KHz (1000UL)
#define MHz (1000*KHz)
diff --git a/openair1/PHY/impl_defs_nr.h b/openair1/PHY/impl_defs_nr.h
index 44f2e314ea653ce8464f4389e23f6d65d142128f..3e09f3f593e2bebc905bdb77311a83ad70243507 100644
--- a/openair1/PHY/impl_defs_nr.h
+++ b/openair1/PHY/impl_defs_nr.h
@@ -757,11 +757,11 @@ typedef struct {
#define MAX_NR_OF_SPATIAL_RELATION_INFOS (8)
typedef enum {
- pucch_format0_nr = 0,
- pucch_format1_nr = 1,
- pucch_format2_nr = 2,
- pucch_format3_nr = 3,
- pucch_format4_nr = 4,
+ pucch_format0_nr = 1,
+ pucch_format1_nr = 2,
+ pucch_format2_nr = 3,
+ pucch_format3_nr = 4,
+ pucch_format4_nr = 5
} pucch_format_nr_t;
typedef enum {
diff --git a/openair1/PHY/impl_defs_top.h b/openair1/PHY/impl_defs_top.h
index a4607d31067ab92725c3b15cc0ce887aff2f9821..6c3d97838d7b9337021b801143c0462de235462a 100644
--- a/openair1/PHY/impl_defs_top.h
+++ b/openair1/PHY/impl_defs_top.h
@@ -265,7 +265,7 @@
#define NB_NUMEROLOGIES_NR (5)
#define TDD_CONFIG_NB_FRAMES (2)
#define NR_MAX_SLOTS_PER_FRAME (160) /* number of slots per frame */
-#define NR_UE_CAPABILITY_SLOT_RX_TO_TX (4) /* FFS_NR_TODO it defines ue capability which is the number of slots */
+#define NR_UE_CAPABILITY_SLOT_RX_TO_TX (6) /* FFS_NR_TODO it defines ue capability which is the number of slots */
/* - between reception of pdsch and tarnsmission of its acknowlegment */
/* - between reception of un uplink grant and its related transmission */
diff --git a/openair1/PHY/phy_extern.h b/openair1/PHY/phy_extern.h
index deb7087c8cf4cc4c969629ce50a2c3949839c8f7..165ed961b30f0a40a3723c2ca275a88152fef815 100644
--- a/openair1/PHY/phy_extern.h
+++ b/openair1/PHY/phy_extern.h
@@ -38,7 +38,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX];
extern unsigned int DAQ_MBOX;
extern int number_of_cards;
-extern short conjugate[8],conjugate2[8];
+extern const short conjugate[8],conjugate2[8];
extern RAN_CONTEXT_t RC;
@@ -73,8 +73,8 @@ extern int flag_LA;
extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX];
extern double sinr_bler_map_up[MCS_COUNT][2][16];
extern int table_length[MCS_COUNT];
-extern double sinr_to_cqi[4][16];
-extern int cqi_to_mcs[16];
+extern const double sinr_to_cqi[4][16];
+extern const int cqi_to_mcs[16];
//for MU-MIMO abstraction using MIESM
//this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively
@@ -82,23 +82,22 @@ extern double MI_map_4qam[3][162];
extern double MI_map_16qam[3][197];
extern double MI_map_64qam[3][227];
-extern double beta1_dlsch_MI[6][MCS_COUNT];
-extern double beta2_dlsch_MI[6][MCS_COUNT];
+extern const double beta1_dlsch_MI[6][MCS_COUNT];
+extern const double beta2_dlsch_MI[6][MCS_COUNT];
-extern double q_qpsk[8];
-extern double q_qam16[8];
-extern double q_qam64[8];
+extern const double q_qpsk[8];
+extern const double q_qam16[8];
+extern const double q_qam64[8];
+extern const double p_qpsk[8];
+extern const double p_qam16[8];
+extern const double p_qam64[8];
-extern double p_qpsk[8];
-extern double p_qam16[8];
-extern double p_qam64[8];
+extern const double beta1_dlsch[6][MCS_COUNT];
+extern const double beta2_dlsch[6][MCS_COUNT];
-extern double beta1_dlsch[6][MCS_COUNT];
-extern double beta2_dlsch[6][MCS_COUNT];
-
-extern char NB_functions[7][20];
-extern char NB_timing[2][20];
-extern char ru_if_types[MAX_RU_IF_TYPES][20];
+extern const char NB_functions[7][20];
+extern const char NB_timing[2][20];
+extern const char ru_if_types[MAX_RU_IF_TYPES][20];
extern int16_t unscrambling_lut[65536*16];
extern uint8_t scrambling_lut[65536*16];
diff --git a/openair1/PHY/phy_extern_nr_ue.h b/openair1/PHY/phy_extern_nr_ue.h
index 569bec68515e3fe71525493ef33617e3ad5e6d07..2f2a0427f41484531b043887c89a14e4d3e10e95 100644
--- a/openair1/PHY/phy_extern_nr_ue.h
+++ b/openair1/PHY/phy_extern_nr_ue.h
@@ -34,7 +34,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX];
//#include "PHY/LTE_TRANSPORT/transport_extern.h"
-extern short conjugate[8],conjugate2[8];
+extern const short conjugate[8],conjugate2[8];
extern int number_of_cards;
@@ -70,8 +70,8 @@ extern int flag_LA;
extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX];
extern double sinr_bler_map_up[MCS_COUNT][2][16];
extern int table_length[MCS_COUNT];
-extern double sinr_to_cqi[4][16];
-extern int cqi_to_mcs[16];
+extern const double sinr_to_cqi[4][16];
+extern const int cqi_to_mcs[16];
//for MU-MIMO abstraction using MIESM
//this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively
@@ -79,23 +79,19 @@ extern double MI_map_4qam[3][162];
extern double MI_map_16qam[3][197];
extern double MI_map_64qam[3][227];
-extern double beta1_dlsch_MI[6][MCS_COUNT];
-extern double beta2_dlsch_MI[6][MCS_COUNT];
+extern const double beta1_dlsch_MI[6][MCS_COUNT];
+extern const double beta2_dlsch_MI[6][MCS_COUNT];
-extern double q_qpsk[8];
-extern double q_qam16[8];
-extern double q_qam64[8];
+extern const double q_qpsk[8];
+extern const double q_qam16[8];
+extern const double q_qam64[8];
-extern double p_qpsk[8];
-extern double p_qam16[8];
-extern double p_qam64[8];
+extern const double beta1_dlsch[6][MCS_COUNT];
+extern const double beta2_dlsch[6][MCS_COUNT];
-extern double beta1_dlsch[6][MCS_COUNT];
-extern double beta2_dlsch[6][MCS_COUNT];
-
-extern char NB_functions[7][20];
-extern char NB_timing[2][20];
-extern char ru_if_types[MAX_RU_IF_TYPES][20];
+extern const char NB_functions[7][20];
+extern const char NB_timing[2][20];
+extern const char ru_if_types[MAX_RU_IF_TYPES][20];
extern int16_t unscrambling_lut[65536*16];
extern uint8_t scrambling_lut[65536*16];
diff --git a/openair1/PHY/phy_extern_ue.h b/openair1/PHY/phy_extern_ue.h
index 4f9ed0f26bec1ebd0983797d495b741d1b38ced9..622551c2fe9891ad7a77df04ef2de7ed9e0d5953 100644
--- a/openair1/PHY/phy_extern_ue.h
+++ b/openair1/PHY/phy_extern_ue.h
@@ -36,7 +36,7 @@ extern unsigned int TX_DMA_BUFFER[4][NB_ANTENNAS_TX];
extern int number_of_cards;
-extern short conjugate[8],conjugate2[8];
+extern const short conjugate[8],conjugate2[8];
extern PHY_VARS_UE ***PHY_vars_UE_g;
@@ -70,8 +70,8 @@ extern int flag_LA;
extern double sinr_bler_map[MCS_COUNT][2][MCS_TABLE_LENGTH_MAX];
extern double sinr_bler_map_up[MCS_COUNT][2][16];
extern int table_length[MCS_COUNT];
-extern double sinr_to_cqi[4][16];
-extern int cqi_to_mcs[16];
+extern const double sinr_to_cqi[4][16];
+extern const int cqi_to_mcs[16];
//for MU-MIMO abstraction using MIESM
//this 2D arrarays contains SINR, MI and RBIR in rows 1, 2, and 3 respectively
@@ -79,23 +79,23 @@ extern double MI_map_4qam[3][162];
extern double MI_map_16qam[3][197];
extern double MI_map_64qam[3][227];
-extern double beta1_dlsch_MI[6][MCS_COUNT];
-extern double beta2_dlsch_MI[6][MCS_COUNT];
+extern const double beta1_dlsch_MI[6][MCS_COUNT];
+extern const double beta2_dlsch_MI[6][MCS_COUNT];
-extern double q_qpsk[8];
-extern double q_qam16[8];
-extern double q_qam64[8];
+extern const double q_qpsk[8];
+extern const double q_qam16[8];
+extern const double q_qam64[8];
-extern double p_qpsk[8];
-extern double p_qam16[8];
-extern double p_qam64[8];
+extern const double p_qpsk[8];
+extern const double p_qam16[8];
+extern const double p_qam64[8];
-extern double beta1_dlsch[6][MCS_COUNT];
-extern double beta2_dlsch[6][MCS_COUNT];
+extern const double beta1_dlsch[6][MCS_COUNT];
+extern const double beta2_dlsch[6][MCS_COUNT];
-extern char NB_functions[7][20];
-extern char NB_timing[2][20];
-extern char ru_if_types[MAX_RU_IF_TYPES][20];
+extern const char NB_functions[7][20];
+extern const char NB_timing[2][20];
+extern const char ru_if_types[MAX_RU_IF_TYPES][20];
extern int16_t unscrambling_lut[65536*16];
extern uint8_t scrambling_lut[65536*16];
diff --git a/openair1/PHY/phy_vars.h b/openair1/PHY/phy_vars.h
index 26540f6fc885ee3b6424cf1cc3bc1f4f52068bc0..5e2be8bd8f76181ff7f660da8902ab2d1bf88415 100644
--- a/openair1/PHY/phy_vars.h
+++ b/openair1/PHY/phy_vars.h
@@ -50,8 +50,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024];
unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192];
-short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
-short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
+const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
+const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
#include "SIMULATION/ETH_TRANSPORT/vars.h"
@@ -59,10 +59,10 @@ short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
unsigned char NB_RU=0;
#ifndef OPENAIR2
-unsigned char NB_eNB_INST=0;
-uint16_t NB_UE_INST=0;
-unsigned char NB_RN_INST=0;
-unsigned char NB_INST=0;
+//unsigned char NB_eNB_INST=0;
+//uint16_t NB_UE_INST=0;
+//unsigned char NB_RN_INST=0;
+//unsigned char NB_INST=0;
#endif
int number_of_cards;
@@ -84,29 +84,29 @@ double MI_map_16qam[3][197];
double MI_map_64qam[3][227];
// here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs
-double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
+const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
{-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572},
{-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392},
{ -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545}
};
//int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27};
-int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
+const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
//for SNR to MI conversion 7 th order Polynomial coeff
-double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
-double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
-double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
+const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
+const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
+const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
//for MI to SNR conversion 7 th order Polynomial coeff
-double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
-double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
-double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
+const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
+const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
+const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
// ideal CE MIESM
-double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
-double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
+const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
+const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
//real CE MIESM
/*
@@ -116,8 +116,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8
//ideal channel estimation values
//double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
//double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
-double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
-double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
+const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
+const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
//real channel estimation valus
/*
@@ -126,13 +126,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682
*/
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
-char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
-char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
-char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
-#endif
+const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
+const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
+const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
/// lookup table for unscrambling in RX
int16_t unscrambling_lut[65536*16] __attribute__((aligned(32)));
diff --git a/openair1/PHY/phy_vars_nr_ue.h b/openair1/PHY/phy_vars_nr_ue.h
index bd077b5b0c77997a1fb547648d84b0702a626f6c..baa64561f0e4bc5fc8b3dd0f2bc67788e3a10b78 100644
--- a/openair1/PHY/phy_vars_nr_ue.h
+++ b/openair1/PHY/phy_vars_nr_ue.h
@@ -49,8 +49,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024];
unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192];
-short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
-short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
+const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
+const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
#include "SIMULATION/ETH_TRANSPORT/vars.h"
@@ -84,29 +84,29 @@ double MI_map_16qam[3][197];
double MI_map_64qam[3][227];
// here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs
-double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
+const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
{-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572},
{-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392},
{ -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545}
};
//int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27};
-int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
+const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
//for SNR to MI conversion 7 th order Polynomial coeff
-double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
-double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
-double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
+const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
+const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
+const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
//for MI to SNR conversion 7 th order Polynomial coeff
-double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
-double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
-double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
+const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
+const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
+const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
// ideal CE MIESM
-double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
-double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
+const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
+const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
//real CE MIESM
/*
@@ -116,8 +116,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8
//ideal channel estimation values
//double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
//double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
-double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
-double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
+const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
+const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
//real channel estimation valus
/*
@@ -126,13 +126,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682
*/
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
-char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
-char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
-char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
-#endif
+const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
+const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
+const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
/// lookup table for unscrambling in RX
int16_t unscrambling_lut[65536*16] __attribute__((aligned(32)));
@@ -142,4 +138,4 @@ uint8_t scrambling_lut[65536*16] __attribute__((aligned(32)));
uint8_t max_ldpc_iterations=4;
uint8_t max_turbo_iterations=4;
-#endif /*__PHY_VARS_H__ */
+#endif
diff --git a/openair1/PHY/phy_vars_ue.h b/openair1/PHY/phy_vars_ue.h
index 05f2e1b8f1960718fe9687e39699db305ca1ca48..e90c2641aa7f852ff4e5cf5a855db0d6ecf0a2d5 100644
--- a/openair1/PHY/phy_vars_ue.h
+++ b/openair1/PHY/phy_vars_ue.h
@@ -19,8 +19,8 @@
* contact@openairinterface.org
*/
-#ifndef __PHY_VARS_H__
-#define __PHY_VARS_H__
+#ifndef __PHY_VARS_UE__H__
+#define __PHY_VARS_UE__H__
#include "PHY/types.h"
#include "PHY/defs_UE.h"
@@ -43,8 +43,8 @@ unsigned short rev[2048],rev_times4[8192],rev_half[1024];
unsigned short rev256[256],rev512[512],rev1024[1024],rev4096[4096],rev2048[2048],rev8192[8192];
-short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
-short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
+const short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
+const short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
#include "SIMULATION/ETH_TRANSPORT/vars.h"
@@ -77,29 +77,29 @@ double MI_map_16qam[3][197];
double MI_map_64qam[3][227];
// here the first index is for transmission mode 1, 2, 5 and 6 whereas the second index is for the 16 sinr vaues corresponding to 16 CQIs
-double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
+const double sinr_to_cqi[4][16]= { {-2.5051, -2.5051, -1.7451, -0.3655, 1.0812, 2.4012, 3.6849, 6.6754, 8.3885, 8.7970, 12.0437, 14.4709, 15.7281, 17.2424, 17.2424, 17.2424},
{-2.2360, -2.2360, -1.3919, -0.0218, 1.5319, 2.9574, 4.3234, 6.3387, 8.9879, 9.5096, 12.6609, 14.0116, 16.4984, 18.1572, 18.1572, 18.1572},
{-1, -1.0000, -0.4198, -0.0140, 1.0362, 2.3520, 3.5793, 6.1136, 8.4836, 9.0858, 12.4723, 13.9128, 16.2054, 17.7392, 17.7392, 17.7392},
{ -4.1057, -4.1057, -3.3768, -2.2916, -1.1392, 0.1236, 1.2849, 3.1933, 5.9298, 6.4052, 9.6245, 10.9414, 13.5166, 14.9545, 14.9545, 14.9545}
};
//int cqi_to_mcs[16]={0, 0, 1, 3, 5, 7, 9, 13, 15, 16, 20, 23, 25, 27, 27, 27};
-int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
+const int cqi_to_mcs[16]= {0, 0, 1, 2, 4, 6, 8, 11, 13, 16, 18, 20, 23, 25, 27, 28};
//for SNR to MI conversion 7 th order Polynomial coeff
-double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
-double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
-double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
+const double q_qam16[8]= {3.21151853033897e-10,5.55435952230651e-09,-2.30760065362117e-07,-6.25587743817859e-06,4.62251036452795e-06,0.00224150813158937,0.0393723140344367,0.245486379182639};
+const double q_qpsk[8]= {1.94491167814437e-09,8.40494123817774e-08,4.75527131198034e-07,-2.48946285301621e-05,-0.000347614016158364,0.00209252225437100,0.0742986115462510,0.488297879889425};
+const double q_qam64[8]= {2.25934026232206e-11,-1.45992206328306e-10,-3.70861183071900e-08,-1.22206071019319e-06,6.49115500399637e-06,0.00129828997837433,0.0259669554914859,0.166602901214898};
//for MI to SNR conversion 7 th order Polynomial coeff
-double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
-double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
-double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
+const double p_qpsk[8]= {5982.42405670359,-21568.1135917693,31293.9987036905,-23394.6795043871,9608.34750585489,-2158.15802349899,267.731968719036,-20.6145324295965};
+const double p_qam16[8]= {7862.12690694170,-28510.3207048338,41542.2150287122,-31088.3036957379,12690.1982361016,-2785.66604739984,326.595462489375,-18.9911849872089};
+const double p_qam64[8]= {8832.57933013696,-32119.1802555952,46914.2578990397,-35163.8150557183,14343.7419388853,-3126.61025510092,360.954930562237,-18.0358548533343};
// ideal CE MIESM
-double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
-double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
+const double beta1_dlsch_MI[6][MCS_COUNT] = { {1.1188, 0.3720, 0.3755, 0.9453, 0.5799, 0.5256, 0.5485, 0.5340, 0.5165, 0.5300, 0.6594, 0.5962, 0.4884, 0.4927, 0.3687, 0.4614, 0.4081, 0.2639,0.2935,0.2520,0.3709,0.2906,0.2612,0.2390}, {0.7138, 0.5533, 0.5533, 0.4828, 0.4998, 0.4843, 0.4942, 0.5323, 0.5142, 0.4756, 0.5792, 0.4167, 0.4445, 0.3942, 0.3789, 0.2756, 0.4456, 0.1650, 0.2254, 0.2353, 0.2097,0.2517,0.3242,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1},{1.808065416202085, 1.754544945430673,1.902272019362616, 1.790054645392961, 1.563204092967629, 1.585258289348813, 1.579349443720310, 1.570650121437345, 1.545055626608596, 1.362229442426877, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33, 1,1,1,1,1,1,1},{0.7146, 0.4789, 0.5392, 0.5556, 0.4975, 0.4847, 0.4691, 0.5261, 0.5278, 0.4962, 0.4468, 0.4113, 0.4622, 0.4609, 0.3946, 0.3991, 0.3532, 0.2439, 0.1898, 0.2929, 0.2712, 0.3367, 0.3591, 0.2571}};
+const double beta2_dlsch_MI[6][MCS_COUNT] = { {1.1293, 0.3707, 0.3722, 0.9310, 0.5808, 0.5265, 0.5404, 0.5279, 0.5210, 0.5226, 0.6438, 0.5827, 0.4804, 0.4830, 0.3638, 0.4506, 0.4107, 0.2547, 0.2797, 0.2413, 0.3351, 0.2750, 0.2568, 0.2273}, {0.7028, 0.5503, 0.5503, 0.4815, 0.5006, 0.4764, 0.4810, 0.5124, 0.4964, 0.4485, 0.5497, 0.3971, 0.4239, 0.3701, 0.3494, 0.2630, 0.4053, 0.1505, 0.2001,0.2024,0.1788,0.2124,0.2668,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1,1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1},{1.079518113138858, 1.105622953570353, 1.031337449900606, 1.073342032668810, 1.242636589110353, 1.255054927783647, 1.291463834317768, 1.317048698347491, 1.354485054187984, 0.338534029291017, 1.85, 1.79, 1.65, 1.54, 1.46, 1.39, 1.33,1, 1,1,1,1,1,1},{0.6980, 0.4694, 0.5379, 0.5483, 0.4982, 0.4737, 0.4611, 0.5051, 0.5020, 0.4672, 0.4357, 0.3957, 0.4389, 0.4344, 0.3645, 0.3661, 0.3301, 0.2179, 0.1730, 0.2536, 0.2389,0.2884,0.2936,0.2226}};
//real CE MIESM
/*
@@ -109,8 +109,8 @@ double beta2_dlsch_MI[6][MCS_COUNT] = { {1.36875, 0.59304, 0.53870, 0.98239, 0.8
//ideal channel estimation values
//double beta1_dlsch[6][MCS_COUNT] = { {2.3814, 0.4956, 0.5273, 1.1708, 0.8014, 0.7889, 0.8111, 0.8139, 0.8124, 0.8479, 1.9280, 1.9664, 2.3857, 2.5147, 2.4511, 3.0158, 2.8643, 5.3013, 5.8594, 6.5372, 7.8073, 7.8030, 7.5295, 7.1320}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
//double beta2_dlsch[6][MCS_COUNT] = { {2.3639, 0.4952, 0.5207, 1.1572, 0.8026, 0.7864, 0.7996, 0.8034, 0.8200, 0.8367, 1.8701, 1.9212, 2.2947, 2.4472, 2.4091, 2.9479, 2.8973, 5.0591, 5.5134, 6.1483, 7.2166, 7.5177, 7.5704, 7.2248}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
-double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
-double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
+const double beta1_dlsch[6][MCS_COUNT] = { {1.199175, 1.085656, 0.983872, 0.843789, 0.816093, 0.853078, 0.899236, 0.919665, 0.888673, 0.924181, 0.814176, 0.794108, 0.770653, 0.826266, 0.982043, 0.979621, 0.985176, 0.901741, 0.870311, 0.911303, 0.898923, 1.003359, 0.988535, 1.030639, 1.151038, 1.116939, 1.214118, 1.219148}, {0.5146, 0.5549, 0.7405, 0.6913, 0.7349, 0.7000, 0.7539, 0.7955, 0.8074, 0.7760, 1.8150, 1.6561, 1.9280, 2.3563, 2.6699, 2.3086, 3.1601, 4.5316, 5.2870, 6.0983, 6.5635, 7.7024, 9.9592, 6.6173}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {1.79358, 1.17908, 2.02600, 1.72040, 1.58618, 1.59039, 1.68111, 1.67062, 1.64911, 1.33274, 4.87800, 3.58797, 3.72338, 5.35700, 2.81752, 1.93472, 2.23259, 1,1,1,1,1,1,1}, {0.4445, 0.5918, 0.7118, 0.7115, 0.7284, 0.7202, 0.7117, 0.8111, 0.8239, 0.7907, 1.8456, 1.8144, 2.3830, 2.6634, 2.6129, 2.8127, 2.7372, 4.9424, 4.8763, 6.8413, 7.1493, 9.4180, 10.1230, 8.9613}};
+const double beta2_dlsch[6][MCS_COUNT] = { {0.534622, 0.596561, 0.500838, 0.471721, 0.548218, 0.547974, 0.924245, 0.836484, 0.776917, 0.879691, 0.875722, 0.666933, 0.666393, 0.755377, 1.074985, 1.080290, 1.010914, 0.790892, 0.793435, 0.860249, 0.901508, 0.967060, 0.951372, 1.011493, 1.106151, 1.117076, 1.209397, 1.227790}, {0.5113, 0.5600, 0.7359, 0.6860, 0.7344, 0.6902, 0.7315, 0.7660, 0.7817, 0.7315, 1.7268, 1.5912, 1.8519, 2.2115, 2.4580, 2.1879, 2.9015, 4.1543, 4.6986, 5.3193, 5.6319, 6.5640, 8.2421, 5.6393}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1,1}, {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1,1,1,1,1}, {0.79479, 0.52872, 0.90005, 0.77170, 0.73220, 0.72060, 0.75433, 0.75451, 0.75989, 0.67655, 1.68525, 1.31100, 1.46573, 1.99843, 1.57293, 1.62852, 2.10636, 1,1,1,1,1,1,1}, {0.4398, 0.5823, 0.7094, 0.7043, 0.7282, 0.7041, 0.6979, 0.7762, 0.7871, 0.7469, 1.7752, 1.7443, 2.2266, 2.4767, 2.4146, 2.6040, 2.5708, 4.4488, 4.4944, 5.9630, 6.3740, 8.1097, 8.4210, 7.8027}};
//real channel estimation valus
/*
@@ -119,13 +119,9 @@ double beta2_dlsch[6][MCS_COUNT] = { {2.52163, 0.83231, 0.77472, 1.36536, 1.1682
*/
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
-char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
-char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
-char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
-#endif
+const char NB_functions[7][20]={"eNodeB_3GPP","eNodeB_3GPP_BBU","NGFI_RAU_IF4p5","NGFI_RRU_IF5","NGFI_RRU_IF4p5","gNodeB_3GPP",};
+const char NB_timing[2][20]={"synch_to_ext_device","synch_to_other"};
+const char ru_if_types[MAX_RU_IF_TYPES][20]={"local RF","IF5 RRU","IF5 Mobipass","IF4p5 RRU","IF1pp RRU"};
/// lookup table for unscrambling in RX
int16_t unscrambling_lut[65536*16] __attribute__((aligned(32)));
@@ -133,4 +129,4 @@ int16_t unscrambling_lut[65536*16] __attribute__((aligned(32)));
uint8_t scrambling_lut[65536*16] __attribute__((aligned(32)));
uint8_t max_turbo_iterations=4;
-#endif /*__PHY_VARS_H__ */
+#endif /* __PHY_VARS_UE__H__ */
diff --git a/openair1/SCHED/phy_procedures_lte_eNb.c b/openair1/SCHED/phy_procedures_lte_eNb.c
index ba03e79e624178cb781e930d6126fab06a317e99..b3e3ab8c4e969f14422bce4c831adddc80692f24 100644
--- a/openair1/SCHED/phy_procedures_lte_eNb.c
+++ b/openair1/SCHED/phy_procedures_lte_eNb.c
@@ -20,12 +20,12 @@
*/
/*! \file phy_procedures_lte_eNB.c
- * \brief Implementation of eNB procedures from 36.213 LTE specifications
- * \author R. Knopp, F. Kaltenberger, N. Nikaein, X. Foukas
+ * \brief Implementation of eNB procedures from 36.213 LTE specifications / FeMBMS 36.231 LTE procedures v14.2
+ * \author R. Knopp, F. Kaltenberger, N. Nikaein, X. Foukas, J. Morgade
* \date 2011
* \version 0.1
* \company Eurecom
- * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr,navid.nikaein@eurecom.fr, x.foukas@sms.ed.ac.uk
+ * \email: knopp@eurecom.fr,florian.kaltenberger@eurecom.fr,navid.nikaein@eurecom.fr, x.foukas@sms.ed.ac.uk, javier.morgade@ieee.org
* \note
* \warning
*/
@@ -122,12 +122,32 @@ lte_subframe_t get_subframe_direction(uint8_t Mod_id,uint8_t CC_id,uint8_t subfr
}
#ifdef MBMS_NFAPI_SCHEDULER
-void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) {
+void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc, int fembms_flag) {
int subframe = proc->subframe_tx;
// This is DL-Cell spec pilots in Control region
- generate_pilots_slot (eNB, eNB->common_vars.txdataF, AMP, subframe << 1, 1);
- if(eNB->dlsch_MCH->active==1)
- generate_mch (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/);
+ if(!fembms_flag){
+ generate_pilots_slot (eNB, eNB->common_vars.txdataF, AMP, subframe << 1, 1);
+ generate_mbsfn_pilot(eNB,proc,
+ eNB->common_vars.txdataF,
+ AMP);
+ }else
+ generate_mbsfn_pilot_khz_1dot25(eNB,proc,
+ eNB->common_vars.txdataF,
+ AMP);
+
+ if(eNB->dlsch_MCH->active==1){
+ if(!fembms_flag){
+ generate_mch (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/);
+ }
+ else{
+ generate_mch_khz_1dot25 (eNB, proc,NULL/*, eNB->dlsch_MCH->harq_processes[0]->pdu*/);
+ }
+
+ LOG_D(PHY,"[eNB%"PRIu8"] Frame %d subframe %d : Got MCH pdu for MBSFN (TBS %d) fembms %d \n",
+ eNB->Mod_id,proc->frame_tx,subframe,
+ eNB->dlsch_MCH->harq_processes[0]->TBS>>3,fembms_flag);
+
+ }
eNB->dlsch_MCH->active = 0;
}
#else
@@ -171,6 +191,80 @@ void pmch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) {
}
#endif
+void common_signal_procedures_fembms (PHY_VARS_eNB *eNB,int frame, int subframe) {
+ LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
+ int **txdataF = eNB->common_vars.txdataF;
+ uint8_t *pbch_pdu=&eNB->pbch_pdu[0];
+
+ if((frame&3)!=0 /*&& subframe != 0*/)
+ return;
+
+ LOG_I(PHY,"common_signal_procedures: frame %d, subframe %d fdd:%s dir:%s index:%d\n",frame,subframe,fp->frame_type == FDD?"FDD":"TDD", subframe_select(fp,subframe) == SF_DL?"DL":"UL?",(frame&15)/4);
+ // generate Cell-Specific Reference Signals for both slots
+ //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_RS_TX,1);
+
+
+ if(subframe_select(fp,subframe) == SF_S)
+ generate_pilots_slot(eNB,
+ txdataF,
+ AMP,
+ subframe<<1,1);
+ else
+ generate_pilots_slot(eNB,
+ txdataF,
+ AMP,
+ subframe<<1,0);
+
+ // check that 2nd slot is for DL
+ if (subframe_select (fp, subframe) == SF_DL)
+ generate_pilots_slot (eNB, txdataF, AMP, (subframe << 1) + 1, 0);
+
+ //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME (VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_RS_TX, 0);
+
+ // First half of PSS/SSS (FDD, slot 0)
+ if (subframe == 0) {
+ //if (fp->frame_type == FDD) {
+ generate_pss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 0);
+ generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 5 : 4, 0);
+ //}
+
+ /// First half of SSS (TDD, slot 1)
+
+ //if (fp->frame_type == TDD) {
+ generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 1);
+ //}
+
+ // generate PBCH (Physical Broadcast CHannel) info
+
+ /// generate PBCH
+ if ((frame&15)==0) {
+ //AssertFatal(eNB->pbch_configured==1,"PBCH was not configured by MAC\n");
+ if (eNB->pbch_configured!=1) return;
+
+ eNB->pbch_configured=0;
+ }
+
+ T(T_ENB_PHY_MIB, T_INT(eNB->Mod_id), T_INT(frame), T_INT(subframe),
+ T_BUFFER(pbch_pdu, 3));
+ generate_pbch_fembms (&eNB->pbch, txdataF, AMP, fp, pbch_pdu, (frame & 15)/4);
+ } //else if ((subframe == 1) && (fp->frame_type == TDD)) {
+ //generate_pss (txdataF, AMP, fp, 2, 2);
+ // }
+ // Second half of PSS/SSS (FDD, slot 10)
+ else if ((subframe == 5) && (fp->frame_type == FDD) && is_fembms_nonMBSFN_subframe(frame,subframe,fp)) {
+ generate_pss (txdataF, AMP, &eNB->frame_parms, (fp->Ncp == NORMAL) ? 6 : 5, 10);
+ generate_sss (txdataF, AMP, &eNB->frame_parms, (fp->Ncp == NORMAL) ? 5 : 4, 10);
+ }
+ // Second-half of SSS (TDD, slot 11)
+ // else if ((subframe == 5) && (fp->frame_type == TDD)) {
+ // generate_sss (txdataF, AMP, fp, (fp->Ncp == NORMAL) ? 6 : 5, 11);
+ // }
+ // Second half of PSS (TDD, slot 12)
+ // else if ((subframe == 6) && (fp->frame_type == TDD)) {
+ // generate_pss (txdataF, AMP, fp, 2, 12);
+ // }
+}
+
void common_signal_procedures (PHY_VARS_eNB *eNB,int frame, int subframe) {
LTE_DL_FRAME_PARMS *fp=&eNB->frame_parms;
int **txdataF = eNB->common_vars.txdataF;
@@ -417,12 +511,30 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
}
if (NFAPI_MODE==NFAPI_MONOLITHIC || NFAPI_MODE==NFAPI_MODE_PNF) {
+ if (is_fembms_pmch_subframe(frame,subframe,fp)) {
+#ifdef MBMS_NFAPI_SCHEDULER
+ pmch_procedures(eNB,proc,1);
+ LOG_D(MAC,"frame %d, subframe %d -> PMCH\n",frame,subframe);
+ return;
+#endif
+ }else if(is_fembms_cas_subframe(frame,subframe,fp) || is_fembms_nonMBSFN_subframe(frame,subframe,fp)){
+ LOG_D(MAC,"frame %d, subframe %d -> CAS\n",frame,subframe);
+ common_signal_procedures_fembms(eNB,proc->frame_tx, proc->subframe_tx);
+ //return;
+ }
+
+ if((!is_fembms_cas_subframe(frame,subframe,fp)) && (!is_fembms_nonMBSFN_subframe(frame,subframe,fp))){
if (is_pmch_subframe(frame,subframe,fp)) {
+#ifdef MBMS_NFAPI_SCHEDULER
+ pmch_procedures(eNB,proc,0);
+#else
pmch_procedures(eNB,proc);
+#endif
} else {
// this is not a pmch subframe, so generate PSS/SSS/PBCH
common_signal_procedures(eNB,proc->frame_tx, proc->subframe_tx);
}
+ }
}
// clear existing ulsch dci allocations before applying info from MAC (this is table
@@ -508,6 +620,18 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
if (do_meas==1) start_meas(&eNB->dlsch_ue_specific);
+ if (NFAPI_MODE==NFAPI_MONOLITHIC || NFAPI_MODE==NFAPI_MODE_PNF) {
+ if (is_fembms_pmch_subframe(frame,subframe,fp)) {
+#ifdef MBMS_NFAPI_SCHEDULER
+ pmch_procedures(eNB,proc,1);
+ return;
+#endif
+ }else if(is_fembms_cas_subframe(frame,subframe,fp)){
+ common_signal_procedures_fembms(eNB,proc->frame_tx, proc->subframe_tx);
+ }
+ }
+
+
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1);
// Now scan UE specific DLSCH
@@ -1211,6 +1335,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) {
}
if (!decodeSucess) {
+ T(T_ENB_PHY_ULSCH_UE_NACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti),
+ T_INT(rdata->harq_pid));
fill_crc_indication(eNB,i,rdata->frame,rdata->subframe,1); // indicate NAK to MAC
fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d UE %d Error receiving ULSCH, round %d/%d (ACK %d,%d)\n",
@@ -1239,6 +1365,8 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) {
fill_rx_indication(eNB,i,rdata->frame,rdata->subframe); // indicate SDU to MAC
ulsch_harq->status = SCH_IDLE;
ulsch->harq_mask &= ~(1 << rdata->harq_pid);
+ T (T_ENB_PHY_ULSCH_UE_ACK, T_INT(eNB->Mod_id), T_INT(rdata->frame), T_INT(rdata->subframe), T_INT(ulsch->rnti),
+ T_INT(rdata->harq_pid));
} // ulsch not in error
if (ulsch_harq->O_ACK>0)
@@ -1419,7 +1547,7 @@ void fill_rx_indication(PHY_VARS_eNB *eNB,
pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation
pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->decodedBytes;
// estimate timing advance for MAC
- sync_pos = lte_est_timing_advance_pusch(eNB,UE_id);
+ sync_pos = lte_est_timing_advance_pusch(&eNB->frame_parms, eNB->pusch_vars[UE_id]->drs_ch_estimates_time);
timing_advance_update = sync_pos; // - eNB->frame_parms.nb_prefix_samples/4; //to check
// if (timing_advance_update > 10) { dump_ulsch(eNB,frame,subframe,UE_id); exit(-1);}
diff --git a/openair1/SCHED/ru_procedures.c b/openair1/SCHED/ru_procedures.c
index 8846b77af9f9b756bbc308012bf8494792012ac6..e472d64db44c4b8fc7ea5234bb95ecff4125f5a9 100644
--- a/openair1/SCHED/ru_procedures.c
+++ b/openair1/SCHED/ru_procedures.c
@@ -41,6 +41,17 @@
* \warning
*/
+/*! \function feptx0
+ * \brief Implementation of ofdm encoding for FeMBMS profile in one eNB
+ * \author J. Morgade
+ * \date 2020
+ * \version 0.1
+ * \email: javier.morgade@ieee.org
+ * \note
+ * \warning
+ */
+
+
#include "PHY/defs_eNB.h"
#include "PHY/phy_extern.h"
@@ -76,7 +87,7 @@ void feptx0(RU_t *ru,
int slot_sizeF = (fp->ofdm_symbol_size) * ((fp->Ncp==1) ? 6 : 7);
int subframe = ru->proc.tti_tx;
- //VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+slot , 1 );
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPTX_OFDM+(slot&1) , 1 );
slot_offset = slot*(fp->samples_per_tti>>1); //slot_offset = subframe*fp->samples_per_tti + (slot*(fp->samples_per_tti>>1));
@@ -91,7 +102,17 @@ void feptx0(RU_t *ru,
fp->nb_prefix_samples,
CYCLIC_PREFIX);
} else {
- if(is_pmch_subframe(ru->proc.frame_tx,subframe,fp)){
+ if(is_fembms_pmch_subframe(ru->proc.frame_tx,subframe,fp)){
+ if((slot&1)==0){//just use one slot chance
+ PHY_ofdm_mod(&ru->common.txdataF_BF[aa][(slot&1)*slot_sizeF],
+ (int*)&ru->common.txdata[aa][slot_offset],
+ fp->ofdm_symbol_size_khz_1dot25,
+ 1,
+ fp->ofdm_symbol_size_khz_1dot25>>2,
+ CYCLIC_PREFIX);
+ LOG_D(HW,"Generating PMCH FeMBMS TX subframe %d %d\n",subframe,fp->ofdm_symbol_size_khz_1dot25);
+ }
+ } else if(is_pmch_subframe(ru->proc.frame_tx,subframe,fp)){
if ((slot&1) == 0) {//just use one slot chance
normal_prefix_mod(&ru->common.txdataF_BF[aa][(slot&1)*slot_sizeF],
(int*)&ru->common.txdata[aa][slot_offset],
@@ -693,12 +714,6 @@ void ru_fep_full_2thread(RU_t *ru,
3/(fp->symbols_per_tti/2),// Ns = slot number
fp);
- /*lte_ul_channel_estimation((PHY_VARS_eNB *)NULL,
- proc,
- ru->idx,
- 3%(fp->symbols_per_tti/2),
- 3/(fp->symbols_per_tti/2));
- */
lte_ul_channel_estimation_RRU(fp,
calibration->drs_ch_estimates,
calibration->drs_ch_estimates_time,
@@ -713,7 +728,7 @@ void ru_fep_full_2thread(RU_t *ru,
0,//interpolate,
0 /*eNB->ulsch[ru->idx]->rnti rnti or ru->ulsch[eNB_id]->rnti*/);
- check_sync_pos = lte_est_timing_advance_pusch((PHY_VARS_eNB *)NULL, ru->idx);
+ check_sync_pos = lte_est_timing_advance_pusch(ru->frame_parms, ru->calibration.drs_ch_estimates_time);
if (ru->state == RU_CHECK_SYNC) {
if ((check_sync_pos >= 0 && check_sync_pos<8) || (check_sync_pos < 0 && check_sync_pos>-8)) {
LOG_I(PHY,"~~~~~~~~~~~ check_sync_pos %d, frame %d, cnt %d\n",check_sync_pos,proc->frame_rx,ru->wait_check);
diff --git a/openair1/SCHED_NR/fapi_nr_l1.c b/openair1/SCHED_NR/fapi_nr_l1.c
index 5c145a32302575038f71d269950e8a2f2685a90d..2870f1d42e0594bbe198afa0e9e91861886dc938 100644
--- a/openair1/SCHED_NR/fapi_nr_l1.c
+++ b/openair1/SCHED_NR/fapi_nr_l1.c
@@ -44,7 +44,7 @@ void handle_nr_nfapi_ssb_pdu(PHY_VARS_gNB *gNB,int frame,int slot,
AssertFatal(dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag== 1, "bchPayloadFlat %d != 1\n",
dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayloadFlag);
- LOG_I(PHY,"%d.%d : pbch_pdu: %x\n",frame,slot,dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload);
+ LOG_D(PHY,"%d.%d : pbch_pdu: %x\n",frame,slot,dl_tti_pdu->ssb_pdu.ssb_pdu_rel15.bchPayload);
memcpy((void*)&gNB->ssb_pdu,&dl_tti_pdu->ssb_pdu,sizeof(dl_tti_pdu->ssb_pdu));
}
@@ -113,8 +113,6 @@ void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB,
nr_fill_ul_dci(gNB,frame,slot);
-
-
}
void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot,
@@ -144,20 +142,25 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
gNB = RC.gNB[Mod_id];
- uint8_t number_dl_pdu = DL_req->dl_tti_request_body.nPDUs;
- // uint8_t number_ul_pdu = 0;
+ uint8_t number_dl_pdu = (DL_req==NULL) ? 0 : DL_req->dl_tti_request_body.nPDUs;
uint8_t number_ul_dci_pdu = (UL_dci_req==NULL) ? 0 : UL_dci_req->numPdus;
+ uint8_t number_ul_tti_pdu = (UL_tti_req==NULL) ? 0 : UL_tti_req->n_pdus;
- // if (UL_tti_req != NULL) number_ul_pdu = UL_tti_req->n_pdus;
-
- LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d%d DL_req:SFN/SLO:%04d%d:dl_pdu:%d tx_req:SFN/SLOT:%04d%d:pdus:%d;\n",
- frame,slot,
- DL_req->SFN,DL_req->Slot,number_dl_pdu,
- TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs);
+ if (DL_req != NULL && TX_req!=NULL)
+ LOG_D(PHY,"NFAPI: Sched_INFO:SFN/SLOT:%04d/%d DL_req:SFN/SLO:%04d/%d:dl_pdu:%d tx_req:SFN/SLOT:%04d/%d:pdus:%d;ul_dci %d ul_tti %d\n",
+ frame,slot,
+ DL_req->SFN,DL_req->Slot,number_dl_pdu,
+ TX_req->SFN,TX_req->Slot,TX_req->Number_of_PDUs,
+ number_ul_dci_pdu,number_ul_tti_pdu);
int pdcch_received=0;
gNB->num_pdsch_rnti=0;
+ for (int i=0; i<NUMBER_OF_NR_DLSCH_MAX; i++) {
+ gNB->dlsch[i][0]->rnti=0;
+ gNB->dlsch[i][0]->harq_mask=0;
+ }
gNB->pdcch_pdu = NULL;
+ gNB->ul_dci_pdu = NULL;
gNB->pbch_configured=0;
for (int i=0;i<number_dl_pdu;i++) {
@@ -174,6 +177,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE:
AssertFatal(pdcch_received == 0, "pdcch_received is not 0, we can only handle one PDCCH PDU per slot\n");
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot);
handle_nfapi_nr_pdcch_pdu(gNB,
frame, slot,
&dl_tti_pdu->pdcch_pdu);
@@ -184,6 +188,7 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE:
{
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot);
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15;
uint16_t pduIndex = pdsch_pdu_rel15->pduIndex;
AssertFatal(TX_req->pdu_list[pduIndex].num_TLV == 1, "TX_req->pdu_list[%d].num_TLV %d != 1\n",
@@ -194,13 +199,28 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
}
}
- if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t));
+ // if (UL_tti_req!=NULL) memcpy(&gNB->UL_tti_req,UL_tti_req,sizeof(nfapi_nr_ul_tti_request_t));
for (int i=0;i<number_ul_dci_pdu;i++) {
- handle_nfapi_nr_ul_dci_pdu(gNB,
- frame, slot,
- &UL_dci_req->ul_dci_pdu_list[i]);
+ handle_nfapi_nr_ul_dci_pdu(gNB, frame, slot, &UL_dci_req->ul_dci_pdu_list[i]);
}
-
+ for (int i = 0; i < number_ul_tti_pdu; i++) {
+ switch (UL_tti_req->pdus_list[i].pdu_type) {
+ case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUSCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot);
+ nr_fill_ulsch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pusch_pdu);
+ break;
+ case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE:
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PUCCH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot);
+ nr_fill_pucch(gNB,UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pucch_pdu);
+ break;
+ case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE:
+ LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_TTI_PRACH_PDU_TYPE for %d.%d\n", frame, slot, UL_tti_req->SFN, UL_tti_req->Slot);
+ nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu;
+ nr_fill_prach(gNB, UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu);
+ nr_fill_prach_ru(gNB->RU_list[0], UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu);
+ break;
+ }
+ }
}
diff --git a/openair1/SCHED_NR/nr_prach_procedures.c b/openair1/SCHED_NR/nr_prach_procedures.c
index 1ed8f28b49e21661d5d08c3d132b3b209329b3e7..a5d459a7c67a4c6e6b99179d19e0ed0bb968de97 100644
--- a/openair1/SCHED_NR/nr_prach_procedures.c
+++ b/openair1/SCHED_NR/nr_prach_procedures.c
@@ -32,7 +32,7 @@
#include "PHY/defs_gNB.h"
#include "PHY/phy_extern.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "nfapi_nr_interface_scf.h"
#include "fapi_nr_l1.h"
#include "nfapi_pnf.h"
@@ -55,7 +55,7 @@ extern int oai_nfapi_nr_rach_ind(nfapi_rach_indication_t *rach_ind);
void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot,
nfapi_nr_prach_pdu_t *prach_pdu) {
- uint16_t max_preamble[4],max_preamble_energy[4],max_preamble_delay[4];
+ uint16_t max_preamble[4]={0},max_preamble_energy[4]={0},max_preamble_delay[4]={0};
uint16_t i;
@@ -77,15 +77,14 @@ void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot,
}
}
-
- /* rx_nr_prach(gNB,
+ rx_nr_prach(gNB,
prach_pdu,
frame,
slot,
&max_preamble[0],
&max_preamble_energy[0],
&max_preamble_delay[0]
- );*/
+ );
LOG_D(PHY,"[RAPROC] Frame %d, slot %d : Most likely preamble %d, energy %d dB delay %d (prach_energy counter %d)\n",
frame,slot,
diff --git a/openair1/SCHED_NR/nr_ru_procedures.c b/openair1/SCHED_NR/nr_ru_procedures.c
index aefeec43e2d55d0cf4f181fe4fa806346bbd920b..560f47059afb29c7f2e7ce7daff6d6494f07fb39 100644
--- a/openair1/SCHED_NR/nr_ru_procedures.c
+++ b/openair1/SCHED_NR/nr_ru_procedures.c
@@ -520,7 +520,7 @@ void nr_fep0(RU_t *ru, int first_half) {
ru->common.rxdataF[aa],
l,
proc->tti_rx,
- 0,
+ ru->N_TA_offset,
0);
}
}
@@ -642,6 +642,8 @@ void nr_fep_full(RU_t *ru, int slot) {
// if ((fp->frame_type == TDD) &&
// (subframe_select(fp,proc->tti_rx) != NR_UPLINK_SLOT)) return;
+ LOG_D(PHY,"In fep_full for slot = %d\n", proc->tti_rx);
+
start_meas(&ru->ofdm_demod_stats);
if (ru->idx == 0) VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_RU_FEPRX, 1 );
@@ -655,7 +657,7 @@ void nr_fep_full(RU_t *ru, int slot) {
ru->common.rxdataF[aa],
l,
proc->tti_rx,
- 0,
+ ru->N_TA_offset,
0);
}
}
diff --git a/openair1/SCHED_NR/phy_frame_config_nr.c b/openair1/SCHED_NR/phy_frame_config_nr.c
index a36cebd6aeed3b8c7c26007384bf805396a8ca16..9d34f496b3fcd6e454ed5520ac9a2a065bee562f 100644
--- a/openair1/SCHED_NR/phy_frame_config_nr.c
+++ b/openair1/SCHED_NR/phy_frame_config_nr.c
@@ -29,11 +29,9 @@
*
************************************************************************/
-#include "SCHED_NR_UE/defs.h"
+#include "PHY/defs_nr_common.h"
#include "PHY/defs_nr_UE.h"
-#include "SCHED_NR_UE/phy_frame_config_nr.h"
-#include "PHY/impl_defs_nr.h"
-#include "PHY/impl_defs_top.h"
+#include "SCHED_NR/phy_frame_config_nr.h"
/*******************************************************************
*
diff --git a/openair1/SCHED_NR/phy_frame_config_nr.h b/openair1/SCHED_NR/phy_frame_config_nr.h
index d1ec5c80d8ba20103340c5b4f92b6409685936e2..ee4b500280a92b8470c61c52cf6853d3f44edf5f 100644
--- a/openair1/SCHED_NR/phy_frame_config_nr.h
+++ b/openair1/SCHED_NR/phy_frame_config_nr.h
@@ -76,9 +76,9 @@ int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms);
* @param frame_parms NR DL Frame parameters
* @param nr_frame : frame number
* @param nr_tti : slot number
- @returns nr_slot_t : downlink or uplink */
+ @returns int : downlink, uplink or mixed slot type*/
-nr_slot_t nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti);
+int nr_slot_select(nfapi_nr_config_request_scf_t *cfg, int nr_frame, int nr_tti);
/** \brief This function frees tdd configuration for nr
* @param frame_parms NR DL Frame parameters
diff --git a/openair1/SCHED_NR/phy_procedures_nr_gNB.c b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
index be8ad0470f98c0d963aef49a7d9260bfe74156c0..94e356951aa916e105fe39f04a291a134d2425dc 100644
--- a/openair1/SCHED_NR/phy_procedures_nr_gNB.c
+++ b/openair1/SCHED_NR/phy_procedures_nr_gNB.c
@@ -23,11 +23,11 @@
#include "PHY/defs_gNB.h"
#include "sched_nr.h"
#include "PHY/NR_REFSIG/dmrs_nr.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/NR_ESTIMATION/nr_ul_estimation.h"
+#include "PHY/NR_UE_TRANSPORT/pucch_nr.h"
#include "SCHED/sched_eNB.h"
#include "sched_nr.h"
#include "SCHED/sched_common_extern.h"
@@ -49,6 +49,8 @@
#include "intertask_interface.h"
+//#define DEBUG_RXDATA
+
uint8_t SSB_Table[38]={0,2,4,6,8,10,12,14,254,254,16,18,20,22,24,26,28,30,254,254,32,34,36,38,40,42,44,46,254,254,48,50,52,54,56,58,60,62};
extern uint8_t nfapi_mode;
@@ -142,7 +144,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
if ((cfg->cell_config.frame_duplex_type.value == TDD) &&
(nr_slot_select(cfg,frame,slot) == NR_UPLINK_SLOT)) return;
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,1);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX+offset,1);
if (do_meas==1) start_meas(&gNB->phy_proc_tx);
@@ -151,12 +153,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
memset(&gNB->common_vars.txdataF[aa][txdataF_offset],0,fp->samples_per_slot_wCP*sizeof(int32_t));
}
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,1);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,1);
if (nfapi_mode == 0 || nfapi_mode == 1) {
if ((!(frame%ssb_frame_periodicity))) // generate SSB only for given frames according to SSB periodicity
nr_common_signal_procedures(gNB,frame, slot);
}
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_COMMON_TX,0);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,0);
if (gNB->pdcch_pdu || gNB->ul_dci_pdu) {
@@ -165,7 +167,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
gNB->ul_dci_pdu==NULL?0:gNB->ul_dci_pdu->pdcch_pdu.pdcch_pdu_rel15.numDlDci,
gNB->pdcch_pdu==NULL?0:gNB->pdcch_pdu->pdcch_pdu_rel15.numDlDci);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,1);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,1);
nr_generate_dci_top(gNB->pdcch_pdu,
gNB->ul_dci_pdu,
@@ -173,12 +175,12 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
&gNB->common_vars.txdataF[0][txdataF_offset],
AMP, *fp);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PDCCH_TX,0);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,0);
}
- LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti);
for (int i=0; i<gNB->num_pdsch_rnti; i++) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1);
+ LOG_D(PHY, "PDSCH generation started (%d)\n", gNB->num_pdsch_rnti);
nr_generate_pdsch(gNB->dlsch[i][0],
gNB->nr_gold_pdsch_dmrs[slot],
gNB->common_vars.txdataF,
@@ -196,7 +198,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
}
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,0);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_TX+offset,0);
}
@@ -208,8 +210,6 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
// VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_RX,1);
-
- if (do_prach_rx(fp,frame,slot)) L1_nr_prach_procedures(gNB,frame,slot/fp->slots_per_subframe);
*/
void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH_id, uint8_t harq_pid)
@@ -226,9 +226,12 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
number_symbols = pusch_pdu->nr_of_symbols;
for (l = start_symbol; l < start_symbol + number_symbols; l++)
- number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01;
+ number_dmrs_symbols += ((pusch_pdu->ul_dmrs_symb_pos)>>l)&0x01;
- nb_re_dmrs = ((pusch_pdu->dmrs_config_type == pusch_dmrs_type1)?6:4);
+ if (pusch_pdu->dmrs_config_type==pusch_dmrs_type1)
+ nb_re_dmrs = 6*pusch_pdu->num_dmrs_cdm_grps_no_data;
+ else
+ nb_re_dmrs = 4*pusch_pdu->num_dmrs_cdm_grps_no_data;
G = nr_get_G(pusch_pdu->rb_size,
number_symbols,
@@ -237,11 +240,9 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
pusch_pdu->qam_mod_order,
pusch_pdu->nrOfLayers);
-
//----------------------------------------------------------
//------------------- ULSCH unscrambling -------------------
//----------------------------------------------------------
-
start_meas(&gNB->ulsch_unscrambling_stats);
nr_ulsch_unscrambling(gNB->pusch_vars[ULSCH_id]->llr,
G,
@@ -265,6 +266,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
G);
stop_meas(&gNB->ulsch_decoding_stats);
+
if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){
LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id);
nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1);
@@ -364,6 +366,7 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
for(symbol = 0; symbol < NR_SYMBOLS_PER_SLOT; symbol++) {
// nr_slot_fep_ul(gNB, symbol, proc->slot_rx, 0, 0);
+
for (aa = 0; aa < gNB->frame_parms.nb_antennas_rx; aa++) {
nr_slot_fep_ul(&gNB->frame_parms,
gNB->common_vars.rxdata[aa],
@@ -379,34 +382,91 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) {
- nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req;
- int num_pusch_pdu = UL_tti_req->n_pdus;
-
- LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu);
-
- gNB->UL_INFO.rx_ind.number_of_pdus = 0;
- gNB->UL_INFO.crc_ind.number_crcs = 0;
-
- for (int i = 0; i < num_pusch_pdu; i++) {
- switch (UL_tti_req->pdus_list[i].pdu_type) {
- case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:{
- LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx);
-
- nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
- nr_fill_ulsch(gNB,frame_rx,slot_rx,pusch_pdu);
-
- uint8_t ULSCH_id = find_nr_ulsch(pusch_pdu->rnti,gNB,SEARCH_EXIST);
- uint8_t harq_pid = pusch_pdu->pusch_data.harq_process_id;
- uint8_t symbol_start = pusch_pdu->start_symbol_index;
- uint8_t symbol_end = symbol_start + pusch_pdu->nr_of_symbols;
-
- for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) {
- nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,1);
+ LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d\n",frame_rx,slot_rx);
+
+ for (int i=0;i<NUMBER_OF_NR_PUCCH_MAX;i++){
+ NR_gNB_PUCCH_t *pucch = gNB->pucch[i];
+ if (pucch) {
+ if ((pucch->active == 1) &&
+ (pucch->frame == frame_rx) &&
+ (pucch->slot == slot_rx) ) {
+
+ nfapi_nr_pucch_pdu_t *pucch_pdu = &pucch[i].pucch_pdu;
+ uint16_t num_ucis;
+
+ switch (pucch_pdu->format_type) {
+ case 0:
+
+ num_ucis = gNB->UL_INFO.uci_ind.num_ucis;
+ gNB->UL_INFO.uci_ind.uci_list = &gNB->uci_pdu_list[0];
+ gNB->UL_INFO.uci_ind.sfn = frame_rx;
+ gNB->UL_INFO.uci_ind.slot = slot_rx;
+ gNB->uci_pdu_list[num_ucis].pdu_type = NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE;
+ gNB->uci_pdu_list[num_ucis].pdu_size = sizeof(nfapi_nr_uci_pucch_pdu_format_0_1_t);
+ nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu_format0 = &gNB->uci_pdu_list[num_ucis].pucch_pdu_format_0_1;
+
+ nr_decode_pucch0(gNB,
+ slot_rx,
+ uci_pdu_format0,
+ pucch_pdu);
+
+ gNB->UL_INFO.uci_ind.num_ucis += 1;
+ pucch->active = 0;
+ break;
+ default:
+ AssertFatal(1==0,"Only PUCCH format 0 is currently supported\n");
+ }
}
- //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1);
- //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1);
- nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid);
+ }
+ }
+
+ for (int ULSCH_id=0;ULSCH_id<NUMBER_OF_NR_ULSCH_MAX;ULSCH_id++) {
+ NR_gNB_ULSCH_t *ulsch = gNB->ulsch[ULSCH_id][0];
+ int harq_pid;
+ //int no_sig;
+ NR_UL_gNB_HARQ_t *ulsch_harq;
+
+ if ((ulsch) &&
+ (ulsch->rnti > 0)) {
+ // for for an active HARQ process
+ for (harq_pid=0;harq_pid<NR_MAX_ULSCH_HARQ_PROCESSES;harq_pid++) {
+ ulsch_harq = ulsch->harq_processes[harq_pid];
+ AssertFatal(ulsch_harq!=NULL,"harq_pid %d is not allocated\n",harq_pid);
+ if ((ulsch_harq->status == NR_ACTIVE) &&
+ (ulsch_harq->frame == frame_rx) &&
+ (ulsch_harq->slot == slot_rx) &&
+ (ulsch_harq->handled == 0)){
+
+#ifdef DEBUG_RXDATA
+ NR_DL_FRAME_PARMS *frame_parms = &gNB->frame_parms;
+ RU_t *ru = gNB->RU_list[0];
+ int slot_offset = frame_parms->get_samples_slot_timestamp(slot_rx,frame_parms,0);
+ slot_offset -= ru->N_TA_offset;
+ char name[128];
+ FILE *f;
+ sprintf(name, "rxdata.%d.%d.raw", frame_rx,slot_rx);
+ f = fopen(name, "w"); if (f == NULL) exit(1);
+ fwrite(&ru->common.rxdata[0][slot_offset],2,frame_parms->get_samples_per_slot(slot_rx,frame_parms)*2, f);
+ fclose(f);
+#endif
+
+ uint8_t symbol_start = ulsch_harq->ulsch_pdu.start_symbol_index;
+ uint8_t symbol_end = symbol_start + ulsch_harq->ulsch_pdu.nr_of_symbols;
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,1);
+ for(uint8_t symbol = symbol_start; symbol < symbol_end; symbol++) {
+ nr_rx_pusch(gNB, ULSCH_id, frame_rx, slot_rx, symbol, harq_pid);
+ }
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_RX_PUSCH,0);
+ //LOG_M("rxdataF_comp.m","rxF_comp",gNB->pusch_vars[0]->rxdataF_comp[0],6900,1,1);
+ //LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,1);
+ nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_ULSCH_PROCEDURES_RX,0);
+ break;
+ }
}
}
}
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,0);
}
diff --git a/openair1/SCHED_NR/sched_nr.h b/openair1/SCHED_NR/sched_nr.h
index 5f54539b7175e6134bc5f350f0be68ef74c991a0..b393e9566e7a744dfbe609f952653f8c79ac07c1 100644
--- a/openair1/SCHED_NR/sched_nr.h
+++ b/openair1/SCHED_NR/sched_nr.h
@@ -39,6 +39,7 @@ void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME
void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, int frame_tx, int slot_tx, int do_meas);
void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx);
void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx);
+void L1_nr_prach_procedures(PHY_VARS_gNB *gNB,int frame,int slot,nfapi_nr_prach_pdu_t *prach_pdu);
void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame, int slot);
void nr_feptx_ofdm(RU_t *ru,int frame_tx,int tti_tx);
void nr_feptx_ofdm_2thread(RU_t *ru,int frame_tx,int tti_tx);
diff --git a/openair1/SCHED_NR_UE/defs.h b/openair1/SCHED_NR_UE/defs.h
index e34ce2b6debc06071e09fc363ce3ea274160c45b..c6aea2ec08d317645a51d379d86a5494acbf0d8c 100644
--- a/openair1/SCHED_NR_UE/defs.h
+++ b/openair1/SCHED_NR_UE/defs.h
@@ -218,6 +218,15 @@ void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
*/
void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+/*! \brief UE PRACH procedures.
+ @param
+ @param
+ @param
+ */
+void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t mode);
+
+int is_nr_prach_subframe(NR_DL_FRAME_PARMS *frame_parms, uint32_t frame, uint8_t subframe);
+
#if 0
/*! \brief Compute ACK/NACK information for PUSCH/PUCCH for UE transmission in subframe n. This function implements table 10.1-1 of 36.213, p. 69.
@param frame_parms Pointer to DL frame parameter descriptor
@@ -322,13 +331,14 @@ uint16_t nr_get_n1_pucch(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t SR);
#endif
+
/*! \brief This function retrieves the PHY UE mode. It is used as a helper function for the UE MAC.
@param Mod_id Local UE index on which to act
@param CC_id Component Carrier Index
- @param eNB_index ID of eNB
+ @param gNB_index ID of gNB
@returns UE mode
*/
-UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index);
+UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_index);
/*! \brief This function implements the power control mechanism for PUCCH from 36.213.
@param phy_vars_ue PHY variables
diff --git a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
index 69876159d6317e48ca27882f77d4b7ccc9bcf767..ea73f2feccdc486bc33311d9a0a67a400af0c37c 100644
--- a/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+++ b/openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
@@ -34,30 +34,30 @@
#include "fapi_nr_ue_interface.h"
#include "fapi_nr_ue_l1.h"
+#include "harq_nr.h"
//#include "PHY/phy_vars_nr_ue.h"
#include "PHY/defs_nr_UE.h"
#include "PHY/impl_defs_nr.h"
-extern PHY_VARS_NR_UE ***PHY_vars_UE_g;
-int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
-{
+extern PHY_VARS_NR_UE ***PHY_vars_UE_g;
+int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
if(scheduled_response != NULL){
- /// module id
- module_id_t module_id = scheduled_response->module_id;
- /// component carrier id
- uint8_t cc_id = scheduled_response->CC_id;
+
+ module_id_t module_id = scheduled_response->module_id;
+ uint8_t cc_id = scheduled_response->CC_id, thread_id;
uint32_t i;
- int slot = scheduled_response->slot;
+ int slot = scheduled_response->slot;
+
// Note: we have to handle the thread IDs for this. To be revisited completely.
- uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
+ thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
+ NR_UE_DLSCH_t *dlsch0 = NULL;
NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
- NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0];
- //NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms;
- PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0];
+ NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms;
+ //PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0];
// PUCCH_ConfigCommon_nr_t *pucch_config_common = PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0];
// PUCCH_Config_t *pucch_config_dedicated = PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0];
@@ -67,136 +67,189 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus);
pdcch_vars->nb_search_space = 0;
- for(i=0; i<dl_config->number_pdus; ++i){
- if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){
- fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
- memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config));
- pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1;
- LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space);
- }else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
- // dlsch config pdu
-
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15;
- uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr;
- dlsch0->current_harq_pid = current_harq_pid;
- dlsch0->active = 1;
- dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti;
-
- //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs;
-
- NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid];
-
- dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart;
- dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize;
- dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs;
- dlsch0_harq->start_rb = dlsch_config_pdu->start_rb;
- dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols;
- dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol;
- dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos;
- dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType;
- dlsch0_harq->mcs = dlsch_config_pdu->mcs;
- dlsch0_harq->DCINdi = dlsch_config_pdu->ndi;
- dlsch0_harq->rvidx = dlsch_config_pdu->rv;
- dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH;
- dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id;
- dlsch0_harq->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind;
- dlsch0_harq->Nl=1;
- dlsch0_harq->mcs_table=0;
- dlsch0_harq->status = ACTIVE;
- LOG_D(MAC,">>>> \tdlsch0->g_pucch=%d\tdlsch0_harq.mcs=%d\n",dlsch0->g_pucch,dlsch0_harq->mcs);
-
- }
+
+ for (i = 0; i < dl_config->number_pdus; ++i){
+
+ if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI) {
+
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
+ memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config));
+ pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1;
+ LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space);
+
+ } else {
+
+ if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DLSCH){
+ dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
+ }
+ else if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH){
+ dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_ra[0];
+ }
+
+ fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15;
+ uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr;
+ NR_DL_UE_HARQ_t *dlsch0_harq;
+
+ dlsch0->current_harq_pid = current_harq_pid;
+ dlsch0->active = 1;
+ dlsch0->rnti = dl_config->dl_config_list[i].dlsch_config_pdu.rnti;
+ //dlsch0->harq_processes[0]->mcs = &dlsch_config_pdu->mcs;
+ dlsch0_harq = dlsch0->harq_processes[current_harq_pid];
+
+ if (dlsch0_harq){
+
+ dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart;
+ dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize;
+ dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs;
+ dlsch0_harq->start_rb = dlsch_config_pdu->start_rb;
+ dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols;
+ dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol;
+ dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos;
+ dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType;
+ dlsch0_harq->n_dmrs_cdm_groups = dlsch_config_pdu->n_dmrs_cdm_groups;
+ dlsch0_harq->mcs = dlsch_config_pdu->mcs;
+ dlsch0_harq->rvidx = dlsch_config_pdu->rv;
+ dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH;
+ dlsch0_harq->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id;
+ dlsch0_harq->harq_ack.slot_for_feedback_ack = (slot+dlsch_config_pdu->pdsch_to_harq_feedback_time_ind)%frame_parms.slots_per_frame;
+ dlsch0_harq->Nl=1;
+ dlsch0_harq->mcs_table=0;
+ dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type);
+ dlsch0_harq->harq_ack.vDAI_DL = dlsch_config_pdu->dai;
+ LOG_D(MAC, ">>>> \tdlsch0->g_pucch = %d\tdlsch0_harq.mcs = %d\n", dlsch0->g_pucch, dlsch0_harq->mcs);
+ }
+ }
}
- }else{
+ } else {
pdcch_vars->nb_search_space = 0;
}
- if(scheduled_response->ul_config != NULL){
+ if (scheduled_response->ul_config != NULL){
+
fapi_nr_ul_config_request_t *ul_config = scheduled_response->ul_config;
- for(i=0; i<ul_config->number_pdus; ++i){
- if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH){
- // pusch config pdu
- fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15;
- uint8_t current_harq_pid = pusch_config_pdu->harq_process_nbr;
- ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs;
- ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb;
- ulsch0->harq_processes[current_harq_pid]->number_of_symbols = pusch_config_pdu->number_symbols;
- ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol;
- ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs;
- ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi;
- ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv;
- ulsch0->harq_processes[current_harq_pid]->Nl = pusch_config_pdu->n_layers;
- ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
- }
- if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){
- // pucch config pdu
- fapi_nr_ul_config_pucch_pdu *pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu;
- uint8_t pucch_resource_id = 0; //FIXME!!!
- uint8_t format = 1; // FIXME!!!
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0].formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].hoppingId = pucch_config_pdu->hoppingId;
- PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0].p0_nominal = pucch_config_pdu->p0_nominal;
- /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping;
- pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used
- pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used
- pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK;
- pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping;
- pucch_config_common->hoppingId = pucch_config_pdu->hoppingId;
- pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/
- }
- if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PRACH){
- // prach config pdu
- fapi_nr_ul_config_prach_pdu *prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu;
- /*frame_parms.prach_config_common.rootSequenceIndex = prach_config_pdu->root_sequence_index;
- frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex = prach_config_pdu->prach_configuration_index;
- frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig = prach_config_pdu->zero_correlation_zone_config;
- frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag = prach_config_pdu->restrictedset_config;
- frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset = prach_config_pdu->prach_freq_offset;*/
- prach_resources->ra_PreambleIndex = prach_config_pdu->preamble_index;
- }
- }
- }else{
-
- }
- if(scheduled_response->tx_request != NULL){
+ for (i = 0; i < ul_config->number_pdus; ++i){
+
+ uint8_t pdu_type = ul_config->ul_config_list[i].pdu_type, pucch_resource_id, current_harq_pid, format, gNB_id = 0;
+ /* PRACH */
+ //NR_PRACH_RESOURCES_t *prach_resources;
+ fapi_nr_ul_config_prach_pdu *prach_config_pdu;
+ /* PUSCH */
+ nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu;
+ /* PUCCH */
+ fapi_nr_ul_config_pucch_pdu *pucch_config_pdu;
+ PUCCH_ConfigCommon_nr_t *pucch_config_common_nr;
+ PUCCH_Config_t *pucch_config_dedicated_nr;
+ PUCCH_format_t *format_params;
+
+ switch (pdu_type){
+
+ case (FAPI_NR_UL_CONFIG_TYPE_PUSCH):
+ // pusch config pdu
+ pusch_config_pdu = &ul_config->ul_config_list[i].pusch_config_pdu;
+ current_harq_pid = pusch_config_pdu->pusch_data.harq_process_id;
+ NR_UL_UE_HARQ_t *harq_process_ul_ue = ulsch0->harq_processes[current_harq_pid];
+
+ if (harq_process_ul_ue){
+
+ nfapi_nr_ue_pusch_pdu_t *pusch_pdu = &harq_process_ul_ue->pusch_pdu;
- }else{
-
+ memcpy(pusch_pdu, pusch_config_pdu, sizeof(nfapi_nr_ue_pusch_pdu_t));
+
+ ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
+
+ if (scheduled_response->tx_request){
+ fapi_nr_tx_request_body_t *tx_req_body = scheduled_response->tx_request->tx_request_body;
+
+ //harq_process_ul_ue->a = (unsigned char*)calloc(TBS/8, sizeof(unsigned char));
+ memcpy(harq_process_ul_ue->a, tx_req_body->pdu, tx_req_body->pdu_length);
+
+ harq_process_ul_ue->status = ACTIVE;
+ }
+
+ } else {
+
+ LOG_E(PHY, "[phy_procedures_nrUE_TX] harq_process_ul_ue is NULL !!\n");
+ return -1;
+
+ }
+
+ break;
+
+ case (FAPI_NR_UL_CONFIG_TYPE_PUCCH):
+ // pucch config pdu
+ pucch_config_pdu = &ul_config->ul_config_list[i].pucch_config_pdu;
+ pucch_resource_id = 0; //FIXME!!!
+ format = 1; // FIXME!!!
+ pucch_config_common_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_common_nr[0];
+ pucch_config_dedicated_nr = &PHY_vars_UE_g[module_id][cc_id]->pucch_config_dedicated_nr[0];
+ format_params = &pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->format_parameters;
+
+ format_params->initialCyclicShift = pucch_config_pdu->initialCyclicShift;
+ format_params->nrofSymbols = pucch_config_pdu->nrofSymbols;
+ format_params->startingSymbolIndex = pucch_config_pdu->startingSymbolIndex;
+ format_params->nrofPRBs = pucch_config_pdu->nrofPRBs;
+ format_params->timeDomainOCC = pucch_config_pdu->timeDomainOCC;
+ format_params->occ_length = pucch_config_pdu->occ_length;
+ format_params->occ_Index = pucch_config_pdu->occ_Index;
+
+ pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB;
+ pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping;
+ pucch_config_dedicated_nr->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used
+ pucch_config_dedicated_nr->formatConfig[format - 1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used
+ pucch_config_dedicated_nr->formatConfig[format - 1]->pi2PBSK = pucch_config_pdu->pi2PBSK;
+
+ pucch_config_common_nr->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping;
+ pucch_config_common_nr->hoppingId = pucch_config_pdu->hoppingId;
+ pucch_config_common_nr->p0_nominal = pucch_config_pdu->p0_nominal;
+
+ /* pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift = pucch_config_pdu->initialCyclicShift;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols = pucch_config_pdu->nrofSymbols;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex = pucch_config_pdu->startingSymbolIndex;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs = pucch_config_pdu->nrofPRBs;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->startingPRB = pucch_config_pdu->startingPRB;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC = pucch_config_pdu->timeDomainOCC;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length = pucch_config_pdu->occ_length;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index = pucch_config_pdu->occ_Index;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping = pucch_config_pdu->intraSlotFrequencyHopping;
+ pucch_config_dedicated->PUCCH_Resource[pucch_resource_id]->secondHopPRB = pucch_config_pdu->secondHopPRB; // Not sure this parameter is used
+ pucch_config_dedicated->formatConfig[format-1]->additionalDMRS = pucch_config_pdu->additionalDMRS; // At this point we need to know which format is going to be used
+ pucch_config_dedicated->formatConfig[format-1]->pi2PBSK = pucch_config_pdu->pi2PBSK;
+ pucch_config_common->pucch_GroupHopping = pucch_config_pdu->pucch_GroupHopping;
+ pucch_config_common->hoppingId = pucch_config_pdu->hoppingId;
+ pucch_config_common->p0_nominal = pucch_config_pdu->p0_nominal;*/
+ break;
+
+ case (FAPI_NR_UL_CONFIG_TYPE_PRACH):
+ // prach config pdu
+ //prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[gNB_id];
+ prach_config_pdu = &ul_config->ul_config_list[i].prach_config_pdu;
+ memcpy((void*)&(PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_pdu), (void*)prach_config_pdu, sizeof(fapi_nr_ul_config_prach_pdu));
+ PHY_vars_UE_g[module_id][cc_id]->prach_vars[gNB_id]->prach_Config_enabled = 1;
+ break;
+
+ default:
+ break;
+ }
+ }
+ } else {
}
+
}
return 0;
}
+
+
int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){
fapi_nr_config_request_t *nrUE_config = &PHY_vars_UE_g[phy_config->Mod_id][phy_config->CC_id]->nrUE_config;
-
+
if(phy_config != NULL)
memcpy(nrUE_config,&phy_config->config_req,sizeof(fapi_nr_config_request_t));
-
+
return 0;
}
diff --git a/openair1/SCHED_NR_UE/harq_nr.c b/openair1/SCHED_NR_UE/harq_nr.c
index 31dcfcacbe913f90a9326a9f533b5dd4b214d3fa..3c3017d658735efce65477680d2cb5f930173975 100644
--- a/openair1/SCHED_NR_UE/harq_nr.c
+++ b/openair1/SCHED_NR_UE/harq_nr.c
@@ -296,7 +296,7 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u
/* 38.321 5.4.2.1 2> if the uplink grant was received on PDCCH for the C-RNTI and the HARQ buffer of the identified process is empty */
if ((ulsch->harq_processes[harq_pid]->first_tx == 1) && (rnti_type == _C_RNTI_)) { /* no transmission yet on this process so consider its harq buffer as empty */
ulsch->harq_processes[harq_pid]->first_tx = 0;
- ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* store first value of ndi */
+ ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* store first value of ndi */
ulsch->harq_processes[harq_pid]->round = 0;
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
@@ -306,8 +306,8 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u
}
/* 38.321 5.4.2.1 2> if the received grant was not addressed to a Temporary C-RNTI on PDCCH, and the NDI provided in the associated HARQ */
/* information has been toggled compared to the value in the previous transmission of this TB of this HARQ process */
- else if ((ulsch->harq_processes[harq_pid]->DCINdi != ndi) && (rnti_type != _TC_RNTI_)) { /* is ndi toogled so this is a new grant ? */
- ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* store first value of ndi */
+ else if ((ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator != ndi) && (rnti_type != _TC_RNTI_)) { /* is ndi toogled so this is a new grant ? */
+ ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* store first value of ndi */
ulsch->harq_processes[harq_pid]->round = 0;
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
@@ -317,7 +317,7 @@ harq_result_t uplink_harq_process(NR_UE_ULSCH_t *ulsch, int harq_pid, int ndi, u
}
/* 38.321 5.4.2.1 2> else (i.e. retransmission): */
else {
- ulsch->harq_processes[harq_pid]->DCINdi = ndi; /* ndi has not toggled si this is a retransmission */
+ ulsch->harq_processes[harq_pid]->pusch_pdu.pusch_data.new_data_indicator = ndi; /* ndi has not toggled si this is a retransmission */
ulsch->harq_processes[harq_pid]->round++; /* increment number of retransmission */
result_harq = RETRANSMISSION_HARQ;
diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr.h b/openair1/SCHED_NR_UE/phy_frame_config_nr.h
index a939584584b7c16a0041429f0894dfb04841eb2e..36692395787099c63d31b87eec604557e14467b0 100644
--- a/openair1/SCHED_NR_UE/phy_frame_config_nr.h
+++ b/openair1/SCHED_NR_UE/phy_frame_config_nr.h
@@ -29,8 +29,8 @@
*
************************************************************************/
-#ifndef PHY_FRAME_CONFIG_NR_H
-#define PHY_FRAME_CONFIG_NR_H
+#ifndef PHY_FRAME_CONFIG_NR_UE_H
+#define PHY_FRAME_CONFIG_NR_UE_H
/************** DEFINE ********************************************/
@@ -62,10 +62,18 @@ int set_tdd_configuration_dedicated_nr(NR_DL_FRAME_PARMS *frame_parms);
* @param frame_parms NR DL Frame parameters
* @param nr_frame : frame number
* @param nr_tti : slot number
- @returns nr_slot_t : downlink or uplink */
+ @returns int : downlink or uplink */
int slot_select_nr(NR_DL_FRAME_PARMS *frame_parms, int nr_frame, int nr_tti);
+/** \brief This function checks nr UE slot direction : downlink or uplink
+ * @param cfg : FAPI Config Request
+ * @param nr_frame : frame number
+ * @param nr_tti : slot number
+ @returns int : downlink, uplink or mixed slot type */
+
+int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti);
+
/** \brief This function frees tdd configuration for nr
* @param frame_parms NR DL Frame parameters
@returns none */
diff --git a/openair1/SCHED_NR_UE/phy_frame_config_nr_ue.c b/openair1/SCHED_NR_UE/phy_frame_config_nr_ue.c
new file mode 100644
index 0000000000000000000000000000000000000000..640ffb4ac361c572cf1275ca701bb51612e3ba28
--- /dev/null
+++ b/openair1/SCHED_NR_UE/phy_frame_config_nr_ue.c
@@ -0,0 +1,99 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/***********************************************************************
+*
+* FILENAME : phy_frame_configuration_nr_ue.c
+*
+* DESCRIPTION : functions related to FDD/TDD configuration for NR
+* see TS 38.213 11.1 Slot configuration
+* and TS 38.331 for RRC configuration
+*
+************************************************************************/
+
+#include "PHY/defs_nr_UE.h"
+
+/*******************************************************************
+*
+* NAME : nr_ue_slot_select
+*
+* DESCRIPTION : function for the UE equivalent to nr_slot_select
+*
+*********************************************************************/
+
+int nr_ue_slot_select(fapi_nr_config_request_t *cfg, int nr_frame, int nr_tti) {
+ /* for FFD all slot can be considered as an uplink */
+ int mu = cfg->ssb_config.scs_common, check_slot = 0;
+
+ if (cfg->cell_config.frame_duplex_type == FDD) {
+ return (NR_UPLINK_SLOT | NR_DOWNLINK_SLOT);
+ }
+
+ if (nr_frame%2 == 0) {
+ for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+ if (cfg->tdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) {
+ check_slot++;
+ }
+ }
+
+ if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+ return (NR_UPLINK_SLOT);
+ }
+
+ check_slot = 0;
+
+ for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+ if (cfg->tdd_table.max_tdd_periodicity_list[nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) {
+ check_slot++;
+ }
+ }
+
+ if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+ return (NR_DOWNLINK_SLOT);
+ } else {
+ return (NR_MIXED_SLOT);
+ }
+ } else {
+ for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+ if (cfg->tdd_table.max_tdd_periodicity_list[((1<<mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME) + nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 1) {
+ check_slot++;
+ }
+ }
+
+ if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+ return (NR_UPLINK_SLOT);
+ }
+
+ check_slot = 0;
+
+ for(int symbol_count=0; symbol_count<NR_NUMBER_OF_SYMBOLS_PER_SLOT; symbol_count++) {
+ if (cfg->tdd_table.max_tdd_periodicity_list[((1<<mu) * NR_NUMBER_OF_SUBFRAMES_PER_FRAME) + nr_tti].max_num_of_symbol_per_slot_list[symbol_count].slot_config == 0) {
+ check_slot++;
+ }
+ }
+
+ if(check_slot == NR_NUMBER_OF_SYMBOLS_PER_SLOT) {
+ return (NR_DOWNLINK_SLOT);
+ } else {
+ return (NR_MIXED_SLOT);
+ }
+ }
+}
diff --git a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
index 1f46408e48cdf83fa97aedc748e71a433a8151a4..68715e27a80babd3dc52455bfcd1b7fc1bf25801 100644
--- a/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+++ b/openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
@@ -44,6 +44,7 @@
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
//#include "PHY/extern.h"
#include "SCHED_NR_UE/defs.h"
+#include "SCHED_NR_UE/pucch_uci_ue_nr.h"
#include "SCHED_NR/extern.h"
#include "SCHED_NR_UE/phy_sch_processing_time.h"
//#include <sched.h>
@@ -53,7 +54,7 @@
#ifdef EMOS
#include "SCHED/phy_procedures_emos.h"
#endif
-
+#include "executables/softmodem-common.h"
//#define DEBUG_PHY_PROC
#define NR_PDCCH_SCHED
@@ -66,6 +67,7 @@
#endif
#include "LAYER2/NR_MAC_UE/mac_defs.h"
+#include "LAYER2/NR_MAC_UE/mac_proto.h"
#include "common/utils/LOG/log.h"
#ifdef EMOS
@@ -86,17 +88,6 @@ char nr_mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"};
extern double cpuf;
-
-
-int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
- uint32_t frame,
- uint32_t slot);
-
-uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
- int frame,
- int nr_tti_rx,
- fapi_nr_dci_indication_t *dci_ind);
-
/*
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
@@ -201,14 +192,13 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,
exit(-1);
}
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
-//unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162};
-/*
- unsigned int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL)
- {
+#endif
- int gain_dB = power_dBm - power_max_dBm;
- int amp_x_100;
+unsigned int gain_table[31] = {100,112,126,141,158,178,200,224,251,282,316,359,398,447,501,562,631,708,794,891,1000,1122,1258,1412,1585,1778,1995,2239,2512,2818,3162};
+
+int get_tx_amp_prach(int power_dBm, int power_max_dBm, int N_RB_UL){
+
+ int gain_dB = power_dBm - power_max_dBm, amp_x_100 = -1;
switch (N_RB_UL) {
case 6:
@@ -230,37 +220,21 @@ void nr_dump_dlsch_SI(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,
amp_x_100 = 408*AMP; // 408 = 100*sqrt(100/6)
break;
default:
- LOG_E(PHY,"Unknown PRB size %d\n",N_RB_UL);
- //mac_xface->macphy_exit("");
+ LOG_E(PHY, "Unknown PRB size %d\n", N_RB_UL);
+ return (amp_x_100);
break;
}
if (gain_dB < -30) {
- return(amp_x_100/3162);
- } else if (gain_dB>0)
- return(amp_x_100);
+ return (amp_x_100/3162);
+ } else if (gain_dB > 0)
+ return (amp_x_100);
else
- return(amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6)
- }
-*/
-
-unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb)
-{
-
- int gain_dB = power_dBm - power_max_dBm;
- double gain_lin;
+ return (amp_x_100/gain_table[-gain_dB]); // 245 corresponds to the factor sqrt(25/6)
- gain_lin = pow(10,.1*gain_dB);
- if ((nb_rb >0) && (nb_rb <= N_RB_UL)) {
- return((int)(AMP*sqrt(gain_lin*N_RB_UL/(double)nb_rb)));
- }
- else {
- LOG_E(PHY,"Illegal nb_rb/N_RB_UL combination (%d/%d)\n",nb_rb,N_RB_UL);
- //mac_xface->macphy_exit("");
- }
- return(0);
+ return (amp_x_100);
}
-#endif
+#if 0
void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t nr_tti_rx)
{
@@ -300,107 +274,6 @@ void nr_dump_dlsch_ra(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,
write_output("dlsch_mag2.m","dlschmag2",ue->pdsch_vars_ra[0]->dl_ch_magb0,300*nsymb,1,1);
}
-void phy_reset_ue(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index)
-{
-
- // This flushes ALL DLSCH and ULSCH harq buffers of ALL connected eNBs...add the eNB_index later
- // for more flexibility
-
- uint8_t i,j,k,s;
- PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id];
-
- //[NUMBER_OF_RX_THREAD=2][NUMBER_OF_CONNECTED_eNB_MAX][2];
- for(int l=0; l<RX_NB_TH; l++) {
- for(i=0; i<NUMBER_OF_CONNECTED_eNB_MAX; i++) {
- for(j=0; j<2; j++) {
- //DL HARQ
- if(ue->dlsch[l][i][j]) {
- for(k=0; k<NR_MAX_DLSCH_HARQ_PROCESSES && ue->dlsch[l][i][j]->harq_processes[k]; k++) {
- ue->dlsch[l][i][j]->harq_processes[k]->status = SCH_IDLE;
- for (s=0; s<10; s++) {
- // reset ACK/NACK bit to DTX for all nr_tti_rxs s = 0..9
- ue->dlsch[l][i][j]->harq_ack[s].ack = 2;
- ue->dlsch[l][i][j]->harq_ack[s].send_harq_status = 0;
- ue->dlsch[l][i][j]->harq_ack[s].vDAI_UL = 0xff;
- ue->dlsch[l][i][j]->harq_ack[s].vDAI_DL = 0xff;
- }
- }
- }
- }
-
- //UL HARQ
- if(ue->ulsch[i]) {
- for(k=0; k<NR_MAX_ULSCH_HARQ_PROCESSES && ue->ulsch[i]->harq_processes[k]; k++) {
- ue->ulsch[i]->harq_processes[k]->status = SCH_IDLE;
- //Set NDIs for all UL HARQs to 0
- // ue->ulsch[i]->harq_processes[k]->Ndi = 0;
-
- }
- }
-
- // flush Msg3 buffer
- ue->ulsch_Msg3_active[i] = 0;
-
- }
- }
-}
-
-void ra_failed(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index)
-{
-
- // if contention resolution fails, go back to PRACH
- PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PRACH;
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti = 0;
- LOG_E(PHY,"[UE %d] Random-access procedure fails, going back to PRACH, setting SIStatus = 0, discard temporary C-RNTI and State RRC_IDLE\n",Mod_id);
- //mac_xface->macphy_exit("");
-}
-
-void ra_succeeded(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index)
-{
-
- int i;
-
- LOG_I(PHY,"[UE %d][RAPROC] Random-access procedure succeeded. Set C-RNTI = Temporary C-RNTI\n",Mod_id);
-
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[0][eNB_index]->crnti_is_temporary = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->pdcch_vars[1][eNB_index]->crnti_is_temporary = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->ulsch_Msg3_active[eNB_index] = 0;
- PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index] = PUSCH;
-
- for (i=0; i<8; i++) {
- if (PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]) {
- PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->status=IDLE;
- PHY_vars_UE_g[Mod_id][CC_id]->dlsch[0][eNB_index][0]->harq_processes[i]->round=0;
- PHY_vars_UE_g[Mod_id][CC_id]->dlsch[1][eNB_index][0]->harq_processes[i]->round=0;
- PHY_vars_UE_g[Mod_id][CC_id]->ulsch[eNB_index]->harq_processes[i]->subframe_scheduling_flag=0;
- }
- }
-
-
-}
-
-UE_MODE_t get_ue_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t eNB_index)
-{
-
- return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[eNB_index]);
-
-}
-void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint16_t timing_advance) {
-
- ue->timing_advance = timing_advance*4;
-
-
-#ifdef DEBUG_PHY_PROC
- /* TODO: fix this log, what is 'HW timing advance'? */
- /*LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d, HW timing advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx_rx, ue->timing_advance);*/
- LOG_I(PHY,"[UE %d] AbsoluteSubFrame %d.%d, received (rar) timing_advance %d\n",ue->Mod_id,proc->frame_rx, proc->nr_tti_rx, ue->timing_advance);
-#endif
-
-}
-
uint8_t nr_is_SR_TXOp(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id)
{
@@ -1391,14 +1264,12 @@ void ulsch_common_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_
#endif
+UE_MODE_t get_nrUE_mode(uint8_t Mod_id,uint8_t CC_id,uint8_t gNB_id){
+ return(PHY_vars_UE_g[Mod_id][CC_id]->UE_mode[gNB_id]);
+}
-void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){
-
- // 3GPP TS 38.213 p4.2
- // scale by the scs numerology
- int factor_mu = 1 << mu;
+uint16_t get_bw_scaling(uint16_t bwp_ul_NB_RB){
uint16_t bw_scaling;
-
// scale the 16 factor in N_TA calculation in 38.213 section 4.2 according to the used FFT size
switch (bwp_ul_NB_RB) {
case 32: bw_scaling = 4; break;
@@ -1409,13 +1280,37 @@ void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_com
case 273: bw_scaling = 32; break;
default: abort();
}
+ return bw_scaling;
+}
+
+void nr_process_timing_advance(module_id_t Mod_id, uint8_t CC_id, uint8_t ta_command, uint8_t mu, uint16_t bwp_ul_NB_RB){
+
+ // 3GPP TS 38.213 p4.2
+ // scale by the scs numerology
+ int factor_mu = 1 << mu;
+ uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB);
PHY_vars_UE_g[Mod_id][CC_id]->timing_advance += (ta_command - 31) * bw_scaling / factor_mu;
- LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %u\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance);
+ LOG_D(PHY, "[UE %d] Got timing advance command %u from MAC, new value is %d\n", Mod_id, ta_command, PHY_vars_UE_g[Mod_id][CC_id]->timing_advance);
+}
+
+// WIP
+// - todo: handle TA application as per ch 4.2 TS 38.213
+void nr_process_timing_advance_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint16_t ta_command) {
+
+ int factor_mu = 1 << ue->frame_parms.numerology_index;
+ uint16_t bwp_ul_NB_RB = ue->frame_parms.N_RB_UL;
+ uint16_t bw_scaling = get_bw_scaling(bwp_ul_NB_RB);
+
+ // Transmission timing adjustment (TS 38.213 p4.2)
+ ue->timing_advance = bw_scaling / factor_mu;
+
+ LOG_D(PHY, "[UE %d] Frame %d Slot %d, Received (RAR) timing advance command %d new value is %u \n", ue->Mod_id, proc->frame_rx, proc->nr_tti_rx, ta_command, ue->timing_advance);
}
#if 0
+
void ue_ulsch_uespec_procedures(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
uint8_t eNB_id,
@@ -2323,28 +2218,26 @@ void ue_pucch_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_
void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
uint8_t gNB_id,
- uint8_t thread_id)
-{
+ uint8_t thread_id){
//int32_t ulsch_start=0;
int slot_tx = proc->nr_tti_tx;
int frame_tx = proc->frame_tx;
+ uint8_t harq_pid = 0;
+ runmode_t mode = normal_txrx;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX,VCD_FUNCTION_IN);
+ memset(ue->common_vars.txdataF[0], 0, sizeof(int)*14*ue->frame_parms.ofdm_symbol_size);
+
LOG_I(PHY,"****** start TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx);
#if UE_TIMING_TRACE
start_meas(&ue->phy_proc_tx);
#endif
- uint8_t harq_pid = 0; //temporary implementation
-
- nr_ue_ulsch_procedures(ue,
- harq_pid,
- frame_tx,
- slot_tx,
- thread_id,
- gNB_id);
+ if (ue->UE_mode[gNB_id] == PUSCH || get_softmodem_params()->phy_test == 1){
+ if (ue->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->status == ACTIVE)
+ nr_ue_ulsch_procedures(ue, harq_pid, frame_tx, slot_tx, thread_id, gNB_id);
/*
@@ -2356,33 +2249,30 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,
} // UE_mode==PUSCH
*/
- LOG_D(PHY, "Sending data \n");
- nr_ue_pusch_common_procedures(ue,
- harq_pid,
- slot_tx,
- thread_id,
- gNB_id,
- &ue->frame_parms);
-
+ if (get_softmodem_params()->usim_test==0) {
+ LOG_D(PHY, "Sending PUCCH\n");
+ pucch_procedures_ue_nr(ue,
+ gNB_id,
+ proc,
+ TRUE);
+ }
+
+ LOG_D(PHY, "Sending data \n");
+ nr_ue_pusch_common_procedures(ue,
+ harq_pid,
+ slot_tx,
+ thread_id,
+ gNB_id,
+ &ue->frame_parms);
+ }
//LOG_M("txdata.m","txs",ue->common_vars.txdata[0],1228800,1,1);
-
-/*
- if ((ue->UE_mode[eNB_id] == PRACH) &&
- (ue->frame_parms.prach_config_common.prach_Config_enabled==1)) {
-
- // check if we have PRACH opportunity
-
- if (is_prach_subframe(&ue->frame_parms,frame_tx,nr_tti_tx)) {
-
- ue_prach_procedures(ue,proc,eNB_id,abstraction_flag,mode);
+ /* RACH */
+ if (get_softmodem_params()->do_ra==1) {
+ if ((ue->UE_mode[gNB_id] < PUSCH) && (ue->prach_vars[gNB_id]->prach_Config_enabled == 1)) {
+ nr_ue_prach_procedures(ue, proc, gNB_id, mode);
}
- } // mode is PRACH
- else {
- ue->generate_prach=0;
}
-*/
-
LOG_I(PHY,"****** end TX-Chain for AbsSubframe %d.%d ******\n", frame_tx, slot_tx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX, VCD_FUNCTION_OUT);
@@ -2392,137 +2282,6 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,
}
-
-void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,runmode_t mode) {
-
- int frame_tx = proc->frame_tx;
- int nr_tti_tx = proc->nr_tti_tx;
- int prach_power;
- uint16_t preamble_tx=50;
- PRACH_RESOURCES_t prach_resources;
-
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN);
-
- ue->generate_nr_prach=0;
- if (ue->mac_enabled==0){
- ue->prach_resources[eNB_id] = &prach_resources;
- ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx;
- ue->prach_resources[eNB_id]->ra_TDD_map_index = 0;
- }
-
- if (ue->mac_enabled==1){
-
- // ask L2 for RACH transport
- if ((mode != rx_calib_ue) && (mode != rx_calib_ue_med) && (mode != rx_calib_ue_byp) && (mode != no_L2_connect) ) {
- LOG_D(PHY,"Getting PRACH resources\n");
- //ue->prach_resources[eNB_id] = mac_xface->ue_get_rach(ue->Mod_id,ue->CC_id,frame_tx,eNB_id,nr_tti_tx);
- // LOG_D(PHY,"Got prach_resources for eNB %d address %p, RRCCommon %p\n",eNB_id,ue->prach_resources[eNB_id],UE_mac_inst[ue->Mod_id].radioResourceConfigCommon);
- // LOG_D(PHY,"Prach resources %p\n",ue->prach_resources[eNB_id]);
- }
-}
-
-if (ue->prach_resources[eNB_id]!=NULL) {
-
- ue->generate_nr_prach=1;
- ue->prach_cnt=0;
-#ifdef SMBV
-ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx;
-#endif
-
-#ifdef OAI_EMU
- ue->prach_PreambleIndex=ue->prach_resources[eNB_id]->ra_PreambleIndex;
-#endif
-
- if (abstraction_flag == 0) {
-
- LOG_I(PHY,"mode %d\n",mode);
-
- if ((ue->mac_enabled==1) && (mode != calib_prach_tx)) {
-
- ue->tx_power_dBm[nr_tti_tx] = ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id);
- }
- else {
- ue->tx_power_dBm[nr_tti_tx] = ue->tx_power_max_dBm;
- ue->prach_resources[eNB_id]->ra_PreambleIndex = preamble_tx;
- }
-
- LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : Generating PRACH, preamble %d,PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, PRACH TDD Resource index %d, RA-RNTI %d\n",
- ue->Mod_id,
- frame_tx,
- nr_tti_tx,
- ue->prach_resources[eNB_id]->ra_PreambleIndex,
- get_nr_PL(ue,eNB_id),
- ue->tx_power_dBm[nr_tti_tx],
- ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER,
- ue->prach_resources[eNB_id]->ra_TDD_map_index,
- ue->prach_resources[eNB_id]->ra_RNTI);
-
- ue->tx_total_RE[nr_tti_tx] = 96;
-
-#if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
- ue->prach_vars[eNB_id]->amp = nr_get_tx_amp(ue->tx_power_dBm[nr_tti_tx],
- ue->tx_power_max_dBm,
- ue->frame_parms.N_RB_UL,
- 6);
-#else
- ue->prach_vars[eNB_id]->amp = AMP;
-#endif
- if ((mode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0))
- LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d : PRACH TX power %d dBm, amp %d\n",
- ue->Mod_id,
- proc->frame_rx,
- proc->nr_tti_tx,
- ue->tx_power_dBm[nr_tti_tx],
- ue->prach_vars[eNB_id]->amp);
-
-
- // start_meas(&ue->tx_prach);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN);
-
-// prach_power = generate_nr_prach(ue,eNB_id,nr_tti_tx,frame_tx);
-prach_power = generate_nr_prach(ue,0,9,0); //subframe number hardcoded according to the simulator
-
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT);
- // stop_meas(&ue->tx_prach);
- LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n",
- ue->Mod_id,
- get_nr_PL(ue,eNB_id),
- ue->tx_power_dBm[nr_tti_tx],
- dB_fixed(prach_power),
- ue->prach_vars[eNB_id]->amp);
- }/* else {
- UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_flag=1;
- UE_transport_info[ue->Mod_id][ue->CC_id].cntl.prach_id=ue->prach_resources[eNB_id]->ra_PreambleIndex;
- }*/ // commented for compiling as abstraction flag is 0
-
- if (ue->mac_enabled==1){
- //mac_xface->Msg1_transmitted(ue->Mod_id,ue->CC_id,frame_tx,eNB_id);
- }
-
-LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_rx %d: Generating PRACH (eNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB), l3msg \n",
- ue->Mod_id,frame_tx,nr_tti_tx,eNB_id,
- ue->prach_resources[eNB_id]->ra_PreambleIndex,
- ue->prach_resources[eNB_id]->ra_PREAMBLE_RECEIVED_TARGET_POWER+get_nr_PL(ue,eNB_id),
- get_nr_PL(ue,eNB_id));
-
-}
-
-
-// if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue
-if (mode == calib_prach_tx)
- ue->prach_resources[eNB_id]=NULL;
-
-LOG_D(PHY,"[UE %d] frame %d nr_tti_rx %d : generate_nr_prach %d, prach_cnt %d\n",
- ue->Mod_id,frame_tx,nr_tti_tx,ue->generate_nr_prach,ue->prach_cnt);
-
-ue->prach_cnt++;
-
-if (ue->prach_cnt==3)
- ue->generate_nr_prach=0;
-
-VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT);
-}
-
/*
void phy_procedures_UE_S_TX(PHY_VARS_NR_UE *ue,uint8_t eNB_id,uint8_t abstraction_flag,relaying_type_t r_type)
{
@@ -2689,7 +2448,7 @@ void restart_phy(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc, uint8_t eNB_id,uint
}
#endif //(0)
-void nr_ue_pbch_procedures(uint8_t eNB_id,
+void nr_ue_pbch_procedures(uint8_t gNB_id,
PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
uint8_t abstraction_flag)
@@ -2708,20 +2467,26 @@ void nr_ue_pbch_procedures(uint8_t eNB_id,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_IN);
- //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, eNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,eNB_id);
+ //LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, gNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,gNB_id);
ret = nr_rx_pbch(ue, proc,
- ue->pbch_vars[eNB_id],
+ ue->pbch_vars[gNB_id],
&ue->frame_parms,
- eNB_id,
+ gNB_id,
(ue->frame_parms.ssb_index)&7,
SISO,
ue->high_speed_flag);
if (ret==0) {
- ue->pbch_vars[eNB_id]->pdu_errors_conseq = 0;
+ ue->pbch_vars[gNB_id]->pdu_errors_conseq = 0;
+ // Switch to PRACH state if it is first PBCH after initial synch and no timing correction is performed
+ if (ue->UE_mode[gNB_id] == NOT_SYNCHED && ue->no_timing_correction == 1){
+ ue->UE_mode[gNB_id] = PRACH;
+ ue->prach_resources[gNB_id]->sync_frame = frame_rx;
+ ue->prach_resources[gNB_id]->init_msg1 = 0;
+ }
#ifdef DEBUG_PHY_PROC
uint16_t frame_tx;
@@ -2751,25 +2516,25 @@ void nr_ue_pbch_procedures(uint8_t eNB_id,
exit(-1);
*/
- ue->pbch_vars[eNB_id]->pdu_errors_conseq++;
- ue->pbch_vars[eNB_id]->pdu_errors++;
+ ue->pbch_vars[gNB_id]->pdu_errors_conseq++;
+ ue->pbch_vars[gNB_id]->pdu_errors++;
- if (ue->pbch_vars[eNB_id]->pdu_errors_conseq>=100) {
+ if (ue->pbch_vars[gNB_id]->pdu_errors_conseq>=100) {
LOG_E(PHY,"More that 100 consecutive PBCH errors! Exiting!\n");
exit_fun("More that 100 consecutive PBCH errors! Exiting!\n");
}
}
if (frame_rx % 100 == 0) {
- ue->pbch_vars[eNB_id]->pdu_fer = ue->pbch_vars[eNB_id]->pdu_errors - ue->pbch_vars[eNB_id]->pdu_errors_last;
- ue->pbch_vars[eNB_id]->pdu_errors_last = ue->pbch_vars[eNB_id]->pdu_errors;
+ ue->pbch_vars[gNB_id]->pdu_fer = ue->pbch_vars[gNB_id]->pdu_errors - ue->pbch_vars[gNB_id]->pdu_errors_last;
+ ue->pbch_vars[gNB_id]->pdu_errors_last = ue->pbch_vars[gNB_id]->pdu_errors;
}
#ifdef DEBUG_PHY_PROC
LOG_D(PHY,"[UE %d] frame %d, slot %d, PBCH errors = %d, consecutive errors = %d!\n",
ue->Mod_id,frame_rx, nr_tti_rx,
- ue->pbch_vars[eNB_id]->pdu_errors,
- ue->pbch_vars[eNB_id]->pdu_errors_conseq);
+ ue->pbch_vars[gNB_id]->pdu_errors,
+ ue->pbch_vars[gNB_id]->pdu_errors_conseq);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_OUT);
}
@@ -3000,10 +2765,8 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id,
pdcch_vars->nb_search_space);
#endif
- fapi_nr_dci_indication_t dci_ind;
- nr_downlink_indication_t dl_indication;
- memset((void*)&dci_ind,0,sizeof(dci_ind));
- memset((void*)&dl_indication,0,sizeof(dl_indication));
+ fapi_nr_dci_indication_t dci_ind={0};
+ nr_downlink_indication_t dl_indication={0};
dci_cnt = nr_dci_decoding_procedure(ue,
proc->frame_rx,
nr_tti_rx,
@@ -3017,11 +2780,12 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id,
//LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
for (int i=0; i<dci_cnt; i++) {
- LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x : format %d\n",
- ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]],
- i,
- dci_ind.dci_list[i].rnti,
- dci_ind.dci_list[i].dci_format);
+ LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI %i of %d total DCIs found --> rnti %x : format %d\n",
+ ue->Mod_id,frame_rx%1024,nr_tti_rx,nr_mode_string[ue->UE_mode[gNB_id]],
+ i + 1,
+ dci_cnt,
+ dci_ind.dci_list[i].rnti,
+ dci_ind.dci_list[i].dci_format);
}
ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt;
@@ -3270,7 +3034,7 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
int first_symbol_flag=0;
if (!dlsch0)
- return;
+ return;
if (dlsch0->active == 0)
return;
@@ -3279,9 +3043,9 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart;
// uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize;
uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb;
- uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb;
- uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol;
- uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols;
+ uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb;
+ uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol;
+ uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols;
LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos);
@@ -3316,17 +3080,35 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
start_meas(&ue->dlsch_llr_stats_parallelization[ue->current_thread_id[nr_tti_rx]][slot]);
#endif
// process DLSCH received in first slot
- nr_rx_pdsch(ue,
- pdsch,
- eNB_id,
- eNB_id_i,
- proc->frame_rx,
- nr_tti_rx, // nr_tti_rx,
- m,
- first_symbol_flag,
- dual_stream_UE,
- i_mod,
- dlsch0->current_harq_pid);
+ // skip DMRS symbols (will have to check later if PDSCH/DMRS are multiplexed
+ if (((1<<m)&dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos) == 0)
+ nr_rx_pdsch(ue,
+ pdsch,
+ eNB_id,
+ eNB_id_i,
+ proc->frame_rx,
+ nr_tti_rx, // nr_tti_rx,
+ m,
+ first_symbol_flag,
+ dual_stream_UE,
+ i_mod,
+ dlsch0->current_harq_pid);
+ else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS)
+ if (pdsch == RA_PDSCH) ue->pdsch_vars_ra[eNB_id]->llr_offset[m]=ue->pdsch_vars_ra[eNB_id]->llr_offset[m-1];
+ else if (pdsch == PDSCH) nr_rx_pdsch(ue,
+ pdsch,
+ eNB_id,
+ eNB_id_i,
+ proc->frame_rx,
+ nr_tti_rx, // nr_tti_rx,
+ m,
+ first_symbol_flag,
+ dual_stream_UE,
+ i_mod,
+ dlsch0->current_harq_pid);
+ else AssertFatal(1==0,"not RA_PDSCH or PDSCH\n");
+ }
+ if (pdsch == PDSCH) LOG_D(PHY,"Done processing symbol %d : llr_offset %d\n",m,ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m]);
#if UE_TIMING_TRACE
stop_meas(&ue->dlsch_llr_stats_parallelization[ue->current_thread_id[nr_tti_rx]][slot]);
#if DISABLE_LOG_X
@@ -3343,103 +3125,153 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
} // CRNTI active
}
}
-#if 0
-void process_rar(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_id, runmode_t mode, int abstraction_flag) {
-
- int frame_rx = proc->frame_rx;
- int nr_tti_rx = proc->nr_tti_rx;
- int timing_advance;
- NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[eNB_id];
- int harq_pid = 0;
- uint8_t *rar;
- /*
- uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1);
- uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
- */
- LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Received RAR mode %d\n",
- ue->Mod_id,
- frame_rx,
- nr_tti_rx, ue->UE_mode[eNB_id]);
+// WIP fix:
+// - time domain indication hardcoded to 0 for k2 offset
+// - extend TS 38.213 ch 8.3 Msg3 PUSCH
+// - b buffer
+// - ulsch power offset
+// - UE_mode == PUSCH case (should be handled by TA updates)
+// - harq
+// - optimize: mu_pusch, j and table_6_1_2_1_1_2_time_dom_res_alloc_A are already defined in nr_ue_procedures
+void nr_process_rar(nr_downlink_indication_t *dl_info) {
+
+ module_id_t module_id = dl_info->module_id;
+ int cc_id = dl_info->cc_id, frame_rx = dl_info->proc->frame_rx, nr_tti_rx = dl_info->proc->nr_tti_rx, ta_command, k2, delta;
+ uint8_t gNB_index = dl_info->gNB_index; // *rar;
+ //fapi_nr_dci_indication_t *dci_ind = dl_info->dci_ind;
+ PHY_VARS_NR_UE *ue = PHY_vars_UE_g[module_id][cc_id];
+ NR_UE_DLSCH_t *dlsch0 = ue->dlsch_ra[gNB_index];
+ UE_MODE_t UE_mode = ue->UE_mode[gNB_index];
+ NR_PRACH_RESOURCES_t *prach_resources = ue->prach_resources[gNB_index];
+ uint16_t slots_per_frame = ue->frame_parms.slots_per_frame;
+ uint8_t mu_pusch = 1, sliv_S, sliv_L;
+ // definition table j Table 6.1.2.1.1-4
+ uint8_t j = (mu_pusch==3)?3:(mu_pusch==2)?2:1;
+ uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3]={ // for PUSCH from TS 38.214 subclause 6.1.2.1.1
+ {j, 0,14}, // row index 1
+ {j, 0,12}, // row index 2
+ {j, 0,10}, // row index 3
+ {j, 2,10}, // row index 4
+ {j, 4,10}, // row index 5
+ {j, 4,8}, // row index 6
+ {j, 4,6}, // row index 7
+ {j+1,0,14}, // row index 8
+ {j+1,0,12}, // row index 9
+ {j+1,0,10}, // row index 10
+ {j+2,0,14}, // row index 11
+ {j+2,0,12}, // row index 12
+ {j+2,0,10}, // row index 13
+ {j, 8,6}, // row index 14
+ {j+3,0,14}, // row index 15
+ {j+3,0,10} // row index 16
+ };
+
+ LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Received RAR mode %d\n", module_id, frame_rx, nr_tti_rx, UE_mode);
if (ue->mac_enabled == 1) {
- if ((ue->UE_mode[eNB_id] != PUSCH) &&
- (ue->prach_resources[eNB_id]->Msg3!=NULL)) {
- LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Invoking MAC for RAR (current preamble %d)\n",
- ue->Mod_id,frame_rx,
- nr_tti_rx,
- ue->prach_resources[eNB_id]->ra_PreambleIndex);
-
- /* timing_advance = mac_xface->ue_process_rar(ue->Mod_id,
- ue->CC_id,
- frame_rx,
- ue->prach_resources[eNB_id]->ra_RNTI,
- dlsch0->harq_processes[0]->b,
- &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti,
- ue->prach_resources[eNB_id]->ra_PreambleIndex,
- dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload
- */
- /*
- ue->pdcch_vars[next1_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti;
- ue->pdcch_vars[next2_thread_id][eNB_id]->crnti = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti;
- */
-
- if (timing_advance!=0xffff) {
-
- LOG_D(PHY,"[UE %d][RAPROC] Frame %d nr_tti_rx %d Got rnti %x and timing advance %d from RAR\n",
- ue->Mod_id,
- frame_rx,
- nr_tti_rx,
- ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti,
- timing_advance);
-
- // remember this c-rnti is still a tc-rnti
-
- ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti_is_temporary = 1;
-
- //timing_advance = 0;
- nr_process_timing_advance_rar(ue,proc,timing_advance);
-
- if (mode!=debug_prach) {
- ue->ulsch_Msg3_active[eNB_id]=1;
- nr_get_Msg3_alloc(&ue->frame_parms,
- nr_tti_rx,
- frame_rx,
- &ue->ulsch_Msg3_frame[eNB_id],
- &ue->ulsch_Msg3_subframe[eNB_id]);
-
- LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d nr_tti_rx %d: Msg3_frame %d, Msg3_subframe %d\n",
- ue->Mod_id,
- frame_rx,
- nr_tti_rx,
- ue->ulsch_Msg3_frame[eNB_id],
- ue->ulsch_Msg3_subframe[eNB_id]);
- harq_pid = nr_subframe2harq_pid(&ue->frame_parms,
- ue->ulsch_Msg3_frame[eNB_id],
- ue->ulsch_Msg3_subframe[eNB_id]);
- ue->ulsch[eNB_id]->harq_processes[harq_pid]->round = 0;
-
- ue->UE_mode[eNB_id] = RA_RESPONSE;
- // ue->Msg3_timer[eNB_id] = 10;
- ue->ulsch[eNB_id]->power_offset = 6;
- ue->ulsch_no_allocation_counter[eNB_id] = 0;
- }
- } else { // PRACH preamble doesn't match RAR
- LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n",
- ue->Mod_id,
- ue->prach_resources[eNB_id]->ra_PreambleIndex);
+ if ((UE_mode != PUSCH) && (prach_resources->Msg3 != NULL)) {
+
+ LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Invoking MAC for RAR (current preamble %d)\n", module_id, frame_rx, nr_tti_rx, prach_resources->ra_PreambleIndex);
+
+ ta_command = nr_ue_process_rar(ue->Mod_id,
+ cc_id,
+ frame_rx,
+ dlsch0->harq_processes[0]->b,
+ &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti,
+ prach_resources->ra_PreambleIndex,
+ dlsch0->harq_processes[0]->b); // alter the 'b' buffer so it contains only the selected RAR header and RAR payload
+
+ if (ta_command != 0xffff) {
+ LOG_D(PHY,"[UE %d][RAPROC] Frame %d subframe %d Got Temporary C-RNTI %x and timing advance %d from RAR\n",
+ ue->Mod_id,
+ frame_rx,
+ nr_tti_rx,
+ ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_index]->pdcch_config[0].rnti,
+ ta_command);
+
+ nr_process_timing_advance_rar(ue, dl_info->proc, ta_command);
+
+ if (ue->mode != debug_prach) {
+ ue->ulsch_Msg3_active[gNB_index] = 1;
+ // TS 38.213 ch 8.3 Msg3 PUSCH
+ // PUSCH time domain resource allocation A for normal CP
+ // TS 38.214 ch 6.1.2.1.1
+ k2 = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][0];
+ sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][1];
+ sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[0][2];
+
+ switch (mu_pusch) {
+ case 0:
+ delta = 2;
+ break;
+ case 1:
+ delta = 3;
+ break;
+ case 2:
+ delta = 4;
+ break;
+ case 3:
+ delta = 6;
+ break;
+ }
+
+ ue->Msg3_startSymbol[gNB_index] = sliv_S;
+ ue->Msg3_Length[gNB_index] = sliv_L;
+ ue->ulsch_Msg3_subframe[gNB_index] = (nr_tti_rx + k2 + delta) % slots_per_frame;
+ if (nr_tti_rx + k2 + delta > slots_per_frame){
+ ue->ulsch_Msg3_frame[gNB_index] = (frame_rx + 1) % 1024;
+ } else {
+ ue->ulsch_Msg3_frame[gNB_index] = frame_rx;
+ }
+
+ LOG_D(PHY,"[UE %d][RAPROC] Got Msg3_alloc Frame %d subframe %d: Msg3_frame %d, Msg3_subframe %d\n",
+ ue->Mod_id,
+ frame_rx,
+ nr_tti_rx,
+ ue->ulsch_Msg3_frame[gNB_index],
+ ue->ulsch_Msg3_subframe[gNB_index]);
+ // harq_pid = subframe2harq_pid(&ue->frame_parms,
+ // ue->ulsch_Msg3_frame[gNB_index],
+ // ue->ulsch_Msg3_subframe[gNB_index]);
+ // ue->ulsch[gNB_index]->harq_processes[harq_pid]->round = 0;
+ // ue->Msg3_timer[gNB_index] = 10;
+ // ue->ulsch[gNB_index].power_offset = 6;
+ // ue->ulsch_no_allocation_counter[gNB_index] = 0;
+ ue->UE_mode[gNB_index] = RA_RESPONSE;
+ }
+ } else {
+ LOG_W(PHY,"[UE %d][RAPROC] Received RAR preamble (%d) doesn't match !!!\n", ue->Mod_id, prach_resources->ra_PreambleIndex);
}
- } // mode != PUSCH
+ }
+ } else {
+ // rar = dlsch0->harq_processes[0]->b+1;
+ // ta_command = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4));
+ // nr_process_timing_advance_rar(ue, dl_info->proc, ta_command);
}
- else {
- rar = dlsch0->harq_processes[0]->b+1;
- timing_advance = ((((uint16_t)(rar[0]&0x7f))<<4) + (rar[1]>>4));
- nr_process_timing_advance_rar(ue,proc,timing_advance);
+}
+
+// if contention resolution fails, go back to UE mode PRACH
+void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index) {
+
+ PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id];
+ ue->UE_mode[gNB_index] = PRACH;
+
+ for (int i=0; i <RX_NB_TH_MAX; i++ ) {
+ ue->pdcch_vars[i][gNB_index]->pdcch_config[0].rnti = 0;
}
+ LOG_E(PHY,"[UE %d] [RAPROC] Random-access procedure fails, going back to PRACH\n", Mod_id);
+}
+void nr_ra_succeeded(uint8_t Mod_id,
+ uint8_t CC_id,
+ uint8_t gNB_index){
+ LOG_I(PHY,"[UE %d][RAPROC] RA procedure succeeded. UE set to PUSCH mode\n", Mod_id);
+ PHY_VARS_NR_UE *ue = PHY_vars_UE_g[Mod_id][CC_id];
+ ue->ulsch_Msg3_active[gNB_index] = 0;
+ ue->UE_mode[gNB_index] = PUSCH;
}
-#endif
void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
@@ -3450,17 +3282,15 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
int *dlsch_errors,
runmode_t mode) {
- int harq_pid;
+ int harq_pid = dlsch0->current_harq_pid;
int frame_rx = proc->frame_rx;
int nr_tti_rx = proc->nr_tti_rx;
int ret=0, ret1=0;
NR_UE_PDSCH *pdsch_vars;
uint8_t is_cw0_active = 0;
uint8_t is_cw1_active = 0;
- //nfapi_nr_config_request_t *cfg = &ue->nrUE_config;
- //uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value;
- uint8_t nb_re_dmrs = 6; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4;
- uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value;
+ uint8_t dmrs_type, nb_re_dmrs;
+ uint16_t length_dmrs = 1;
uint16_t nb_symb_sch = 9;
nr_downlink_indication_t dl_indication;
fapi_nr_rx_indication_t rx_ind;
@@ -3482,13 +3312,16 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
if (dlsch0==NULL)
AssertFatal(0,"dlsch0 should be defined at this level \n");
-
- harq_pid = dlsch0->current_harq_pid;
is_cw0_active = dlsch0->harq_processes[harq_pid]->status;
nb_symb_sch = dlsch0->harq_processes[harq_pid]->nb_symbols;
start_symbol = dlsch0->harq_processes[harq_pid]->start_symbol;
-
-
+ dmrs_type = dlsch0->harq_processes[harq_pid]->dmrsConfigType;
+ if (dmrs_type==NFAPI_NR_DMRS_TYPE1) {
+ nb_re_dmrs = 6*dlsch0->harq_processes[harq_pid]->n_dmrs_cdm_groups;
+ }
+ else {
+ nb_re_dmrs = 4*dlsch0->harq_processes[harq_pid]->n_dmrs_cdm_groups;
+ }
if(dlsch1)
is_cw1_active = dlsch1->harq_processes[harq_pid]->status;
@@ -3534,32 +3367,32 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
if (frame_rx < *dlsch_errors)
*dlsch_errors=0;
- if (pdsch==RA_PDSCH) {
+ if (pdsch == RA_PDSCH) {
if (ue->prach_resources[eNB_id]!=NULL)
- dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI;
+ dlsch0->rnti = ue->prach_resources[eNB_id]->ra_RNTI;
else {
- LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n",ue->Mod_id,frame_rx,nr_tti_rx);
- //mac_xface->macphy_exit("prach_resources is NULL");
- return;
+ LOG_E(PHY,"[UE %d] Frame %d, nr_tti_rx %d: FATAL, prach_resources is NULL\n", ue->Mod_id, frame_rx, nr_tti_rx);
+ //mac_xface->macphy_exit("prach_resources is NULL");
+ return;
}
}
- // start ldpc decode for CW 0
- dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb,
- nb_symb_sch,
- nb_re_dmrs,
- length_dmrs,
- dlsch0->harq_processes[harq_pid]->Qm,
- dlsch0->harq_processes[harq_pid]->Nl);
+ // start ldpc decode for CW 0
+ dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb,
+ nb_symb_sch,
+ nb_re_dmrs,
+ length_dmrs,
+ dlsch0->harq_processes[harq_pid]->Qm,
+ dlsch0->harq_processes[harq_pid]->Nl);
#if UE_TIMING_TRACE
start_meas(&ue->dlsch_unscrambling_stats);
#endif
nr_dlsch_unscrambling(pdsch_vars->llr[0],
- dlsch0->harq_processes[harq_pid]->G,
- 0,
- ue->frame_parms.Nid_cell,
- dlsch0->rnti);
+ dlsch0->harq_processes[harq_pid]->G,
+ 0,
+ ue->frame_parms.Nid_cell,
+ dlsch0->rnti);
#if UE_TIMING_TRACE
@@ -3640,10 +3473,10 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
start_meas(&ue->dlsch_unscrambling_stats);
#endif
nr_dlsch_unscrambling(pdsch_vars->llr[1],
- dlsch1->harq_processes[harq_pid]->G,
- 0,
- ue->frame_parms.Nid_cell,
- dlsch1->rnti);
+ dlsch1->harq_processes[harq_pid]->G,
+ 0,
+ ue->frame_parms.Nid_cell,
+ dlsch1->rnti);
#if UE_TIMING_TRACE
stop_meas(&ue->dlsch_unscrambling_stats);
#endif
@@ -3664,31 +3497,31 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
#ifdef UE_DLSCH_PARALLELISATION
ret1 = nr_dlsch_decoding_mthread(ue,
- proc,
- eNB_id,
- pdsch_vars->llr[1],
- &ue->frame_parms,
- dlsch1,
- dlsch1->harq_processes[harq_pid],
- frame_rx,
- nb_symb_sch,
- nr_tti_rx,
- harq_pid,
- pdsch==PDSCH?1:0,
- dlsch1->harq_processes[harq_pid]->TBS>256?1:0);
+ proc,
+ eNB_id,
+ pdsch_vars->llr[1],
+ &ue->frame_parms,
+ dlsch1,
+ dlsch1->harq_processes[harq_pid],
+ frame_rx,
+ nb_symb_sch,
+ nr_tti_rx,
+ harq_pid,
+ pdsch==PDSCH?1:0,
+ dlsch1->harq_processes[harq_pid]->TBS>256?1:0);
LOG_T(PHY,"UE_DLSCH_PARALLELISATION is defined, ret1 = %d\n", ret1);
#else
ret1 = nr_dlsch_decoding(ue,
- pdsch_vars->llr[1],
- &ue->frame_parms,
- dlsch1,
- dlsch1->harq_processes[harq_pid],
- frame_rx,
- nb_symb_sch,
- nr_tti_rx,
- harq_pid,
- pdsch==PDSCH?1:0,//proc->decoder_switch,
- dlsch1->harq_processes[harq_pid]->TBS>256?1:0);
+ pdsch_vars->llr[1],
+ &ue->frame_parms,
+ dlsch1,
+ dlsch1->harq_processes[harq_pid],
+ frame_rx,
+ nb_symb_sch,
+ nr_tti_rx,
+ harq_pid,
+ pdsch==PDSCH?1:0,//proc->decoder_switch,
+ dlsch1->harq_processes[harq_pid]->TBS>256?1:0);
LOG_T(PHY,"UE_DLSCH_PARALLELISATION is NOT defined, ret1 = %d\n", ret1);
printf("start cw1 dlsch decoding\n");
#endif
@@ -3710,35 +3543,46 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
#endif
LOG_I(PHY,"AbsSubframe %d.%d --> ldpc Decoding for CW1 %5.3f\n",
frame_rx%1024, nr_tti_rx,(ue->dlsch_decoding_stats[ue->current_thread_id[nr_tti_rx]].p_time)/(cpuf*1000.0));
+
+ LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch1->harq_processes[harq_pid]->TBS);
}
LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx);
-
- LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS);
+ LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS);
if(ret<dlsch0->max_ldpc_iterations+1){
- // fill dl_indication message
- dl_indication.module_id = ue->Mod_id;
- dl_indication.cc_id = ue->CC_id;
- dl_indication.gNB_index = eNB_id;
- dl_indication.frame = frame_rx;
- dl_indication.slot = nr_tti_rx;
-
- dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance
- dl_indication.proc=proc;
-
- //dl_indication.rx_ind->number_pdus
- rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH;
- rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b;
- rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3;
- LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length);
- rx_ind.number_pdus = 1;
-
- //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now
- dl_indication.dci_ind = NULL; //&ue->dci_ind;
- // send to mac
- if (ue->if_inst && ue->if_inst->dl_indication)
- ue->if_inst->dl_indication(&dl_indication, ul_time_alignment);
+
+ // fill dl_indication message
+ dl_indication.module_id = ue->Mod_id;
+ dl_indication.cc_id = ue->CC_id;
+ dl_indication.gNB_index = eNB_id;
+ dl_indication.frame = frame_rx;
+ dl_indication.slot = nr_tti_rx;
+ dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance
+ dl_indication.proc=proc;
+
+ //dl_indication.rx_ind->number_pdus
+ switch (pdsch) {
+ case RA_PDSCH:
+ rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_RAR;
+ break;
+ case PDSCH:
+ rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_DLSCH;
+ break;
+ default:
+ break;
+ }
+
+ rx_ind.rx_indication_body[0].pdsch_pdu.pdu = dlsch0->harq_processes[harq_pid]->b;
+ rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length = dlsch0->harq_processes[harq_pid]->TBS>>3;
+ LOG_D(PHY, "PDU length in bits: %d, in bytes: %d \n", dlsch0->harq_processes[harq_pid]->TBS, rx_ind.rx_indication_body[0].pdsch_pdu.pdu_length);
+ rx_ind.number_pdus = 1;
+
+ //ue->dl_indication.rx_ind = &dlsch1->harq_processes[harq_pid]->b; //no data, only dci for now
+ dl_indication.dci_ind = NULL; //&ue->dci_ind;
+ // send to mac
+ if (ue->if_inst && ue->if_inst->dl_indication)
+ ue->if_inst->dl_indication(&dl_indication, ul_time_alignment);
}
// TODO CRC check for CW0
@@ -4056,7 +3900,6 @@ void *UE_thread_slot1_dl_processing(void *arg) {
}
//printf("[slot1 dl processing] AbsSubframe %d.%d LLR Computation Start wait DCI %d\n",frame_rx,nr_tti_rx,wait);
-
/**** Pdsch Procedure Slot1 ****/
// start slot1 thread for Pdsch Procedure (slot1)
// do procedures for C-RNTI
@@ -4144,7 +3987,6 @@ void *UE_thread_slot1_dl_processing(void *arg) {
#endif
#endif
-
if (pthread_mutex_lock(&proc->mutex_slot1_dl_processing) != 0) {
LOG_E( PHY, "[SCHED][UE] error locking mutex for UE RXTX\n" );
exit_fun("noting to add");
@@ -4193,18 +4035,14 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
int nr_tti_rx = proc->nr_tti_rx;
int slot_pbch;
NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][0];
- NR_UE_DLSCH_t **dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id];
fapi_nr_config_request_t *cfg = &ue->nrUE_config;
- uint8_t harq_pid = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->current_harq_pid;
- NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
- uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
- uint16_t start_symb_sch = dlsch0_harq->start_symbol;
+
uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0;
uint8_t dci_cnt = 0;
NR_DL_FRAME_PARMS *fp = &ue->frame_parms;
-
+
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_RX, VCD_FUNCTION_IN);
-
+
LOG_D(PHY," ****** start RX-Chain for Frame.Slot %d.%d ****** \n", frame_rx%1024, nr_tti_rx);
/*
@@ -4212,7 +4050,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
*/
-
int coreset_nb_rb=0;
int coreset_start_rb=0;
if (pdcch_vars->nb_search_space > 0)
@@ -4247,11 +4084,12 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if (ue->no_timing_correction==0) {
LOG_I(PHY,"start adjust sync slot = %d no timing %d\n", nr_tti_rx, ue->no_timing_correction);
nr_adjust_synch_ue(fp,
- ue,
- eNB_id,
- nr_tti_rx,
- 0,
- 16384);
+ ue,
+ eNB_id,
+ frame_rx,
+ nr_tti_rx,
+ 0,
+ 16384);
}
}
@@ -4266,10 +4104,10 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_IN);
nr_slot_fep(ue,
- l,
- nr_tti_rx,
- 0,
- 0);
+ l,
+ nr_tti_rx,
+ 0,
+ 0);
// note: this only works if RBs for PDCCH are contigous!
LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n",
@@ -4296,40 +4134,41 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if (dci_cnt > 0) {
- LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt);
+ LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n", ue->Mod_id, frame_rx, nr_tti_rx, dci_cnt);
- } else {
- LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx);
- }
-#endif //NR_PDCCH_SCHED
+ NR_UE_DLSCH_t *dlsch = NULL;
+ if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1){
+ dlsch = ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0];
+ } else if (ue->dlsch_ra[0]->active == 1){
+ dlsch = ue->dlsch_ra[0];
+ }
+ AssertFatal(dlsch != NULL, "Unsupported mode\n");
+ uint8_t harq_pid = dlsch->current_harq_pid;
+ NR_DL_UE_HARQ_t *dlsch0_harq = dlsch->harq_processes[harq_pid];
+ uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
+ uint16_t start_symb_sch = dlsch0_harq->start_symbol;
+ int symb_dmrs = -1;
-
- if (dci_cnt > 0){
LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
//to update from pdsch config
- start_symb_sch = dlsch0_harq->start_symbol;
- int symb_dmrs=-1;
+
for (int i=0;i<4;i++) if (((1<<i)&dlsch0_harq->dlDmrsSymbPos) > 0) {symb_dmrs=i;break;}
AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n");
LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos);
nr_gold_pdsch(ue,symb_dmrs,0, 1);
-
- nb_symb_sch = dlsch0_harq->nb_symbols;
for (uint16_t m=start_symb_sch;m<(nb_symb_sch+start_symb_sch) ; m++){
nr_slot_fep(ue,
- m, //to be updated from higher layer
- nr_tti_rx,
- 0,
- 0);
-
-
+ m, //to be updated from higher layer
+ nr_tti_rx,
+ 0,
+ 0);
}
- //set active for testing, to be removed
- ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 1;
+ } else {
+ LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n", ue->Mod_id, frame_rx, nr_tti_rx);
}
- else
- ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0;
+
+#endif //NR_PDCCH_SCHED
#if UE_TIMING_TRACE
start_meas(&ue->generic_stat);
@@ -4343,7 +4182,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
PDSCH,
ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0],
NULL);
-
+
//printf("phy procedure pdsch start measurement\n");
nr_ue_measurement_procedures(2,ue,proc,eNB_id,nr_tti_rx,mode);
@@ -4355,7 +4194,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
write_output("rxF_comp.m","rxFc",&ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->rxdataF_comp0[0][0],fp->N_RB_DL*12*14,1,1);
write_output("rxF_llr.m","rxFllr",ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr[0],(nb_symb_sch-1)*50*12+50*6,1,0);
*/
-
+
//VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT);
}
@@ -4363,11 +4202,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if ((ue->dlsch_SI[eNB_id]) && (ue->dlsch_SI[eNB_id]->active == 1)) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_IN);
nr_ue_pdsch_procedures(ue,
- proc,
- eNB_id,
- SI_PDSCH,
- ue->dlsch_SI[eNB_id],
- NULL);
+ proc,
+ eNB_id,
+ SI_PDSCH,
+ ue->dlsch_SI[eNB_id],
+ NULL);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_SI, VCD_FUNCTION_OUT);
}
@@ -4376,11 +4215,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if ((ue->dlsch_p[eNB_id]) && (ue->dlsch_p[eNB_id]->active == 1)) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_IN);
nr_ue_pdsch_procedures(ue,
- proc,
- eNB_id,
- P_PDSCH,
- ue->dlsch_p[eNB_id],
- NULL);
+ proc,
+ eNB_id,
+ P_PDSCH,
+ ue->dlsch_p[eNB_id],
+ NULL);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_P, VCD_FUNCTION_OUT);
}
@@ -4389,18 +4228,42 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if ((ue->dlsch_ra[eNB_id]) && (ue->dlsch_ra[eNB_id]->active == 1)) {
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_IN);
nr_ue_pdsch_procedures(ue,
- proc,
- eNB_id,
- RA_PDSCH,
- ue->dlsch_ra[eNB_id],
- NULL);
+ proc,
+ eNB_id,
+ RA_PDSCH,
+ ue->dlsch_ra[eNB_id],
+ NULL);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT);
+ // #if UE_TIMING_TRACE
+ // start_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]);
+ // #endif
+
+ nr_ue_dlsch_procedures(ue,
+ proc,
+ eNB_id,
+ RA_PDSCH,
+ ue->dlsch_ra[eNB_id],
+ NULL,
+ &ue->dlsch_ra_errors[eNB_id],
+ mode);
+
+ // #if UE_TIMING_TRACE
+ // stop_meas(&ue->dlsch_procedures_stat[ue->current_thread_id[nr_tti_rx]]);
+ #if DISABLE_LOG_X
+ printf("[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[nr_tti_rx]].p_time/(cpuf*1000.0));
+ printf("[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0));
+ #else
+ LOG_D(PHY, "[SFN %d] Slot1: Pdsch Proc %5.2f\n", nr_tti_rx, ue->pdsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0));
+ LOG_D(PHY, "[SFN %d] Slot0 Slot1: Dlsch Proc %5.2f\n", nr_tti_rx, ue->dlsch_procedures_stat[ue->current_thread_id[ nr_tti_rx]].p_time/(cpuf*1000.0));
+ #endif
+ // #endif
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC_RA, VCD_FUNCTION_OUT);
}
// do procedures for C-RNTI
if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) {
-
+
LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN);
@@ -4430,6 +4293,9 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
#endif
+ // deactivate dlsch once dlsch proc is done
+ ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active = 0;
+
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_OUT);
}
@@ -4635,3 +4501,121 @@ uint8_t nr_is_ri_TXOp(PHY_VARS_NR_UE *ue,
return(0);
}
+// WIP
+// todo:
+// - set tx_total_RE
+// - power control as per 38.213 ch 7.4
+void nr_ue_prach_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t gNB_id, runmode_t runmode) {
+
+ int frame_tx = proc->frame_tx, nr_tti_tx = proc->nr_tti_tx, prach_power; // tx_amp
+ uint16_t /*preamble_tx = 50,*/ pathloss;
+ uint8_t mod_id = ue->Mod_id;
+ UE_MODE_t UE_mode = get_nrUE_mode(mod_id, ue->CC_id, gNB_id);
+ NR_PRACH_RESOURCES_t * prach_resources = ue->prach_resources[gNB_id];
+ uint8_t nr_prach = 0;
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_IN);
+
+ if (ue->mac_enabled == 0){
+ // prach_resources->ra_PreambleIndex = preamble_tx;
+ prach_resources->ra_TDD_map_index = 0;
+ prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = 10;
+ prach_resources->ra_RNTI = 0x1234;
+ nr_prach = 1;
+ } else {
+ // ask L2 for RACH transport
+ if ((runmode != rx_calib_ue) && (runmode != rx_calib_ue_med) && (runmode != rx_calib_ue_byp) && (runmode != no_L2_connect) ) {
+ LOG_D(PHY, "Getting PRACH resources. Frame %d Slot %d \n", frame_tx, nr_tti_tx);
+ // flush Msg3 Buffer
+ if (prach_resources->Msg3 == NULL){
+ for(int i = 0; i<NUMBER_OF_CONNECTED_gNB_MAX; i++) {
+ ue->ulsch_Msg3_active[i] = 0;
+ }
+ }
+ nr_prach = nr_ue_get_rach(ue->prach_resources[gNB_id], mod_id, ue->CC_id, UE_mode, frame_tx, gNB_id, nr_tti_tx);
+ }
+ }
+
+ if (!prach_resources->init_msg1 && (frame_tx > ue->prach_resources[gNB_id]->sync_frame + 150)){
+ ue->prach_cnt = 0;
+ prach_resources->init_msg1 = 1;
+ }
+
+ if (ue->prach_resources[gNB_id] != NULL && nr_prach == 1 && prach_resources->init_msg1) {
+
+ pathloss = get_nr_PL(mod_id, ue->CC_id, gNB_id);
+ LOG_D(PHY,"runmode %d\n",runmode);
+
+ if ((ue->mac_enabled == 1) && (runmode != calib_prach_tx)) {
+ ue->tx_power_dBm[nr_tti_tx] = prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER + pathloss;
+ }
+
+ LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : Generating PRACH, preamble %d, PL %d, P0_PRACH %d, TARGET_RECEIVED_POWER %d dBm, RA-RNTI %x\n",
+ ue->Mod_id,
+ frame_tx,
+ nr_tti_tx,
+ prach_resources->ra_PreambleIndex,
+ pathloss,
+ ue->tx_power_dBm[nr_tti_tx],
+ prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER,
+ prach_resources->ra_RNTI);
+
+ //ue->tx_total_RE[nr_tti_tx] = 96; // todo
+ ue->prach_vars[gNB_id]->amp = AMP;
+
+ /* #if defined(EXMIMO) || defined(OAI_USRP) || defined(OAI_BLADERF) || defined(OAI_LMSSDR) || defined(OAI_ADRV9371_ZC706)
+ tx_amp = get_tx_amp_prach(ue->tx_power_dBm[nr_tti_tx], ue->tx_power_max_dBm, ue->frame_parms.N_RB_UL);
+ if (tx_amp != -1)
+ ue->prach_vars[gNB_id]->amp = tx_amp;
+ #else
+ ue->prach_vars[gNB_id]->amp = AMP;
+ #endif */
+
+ if ((runmode == calib_prach_tx) && (((proc->frame_tx&0xfffe)%100)==0))
+ LOG_D(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d : PRACH TX power %d dBm, amp %d\n", ue->Mod_id,
+ proc->frame_rx,
+ proc->nr_tti_tx,
+ ue->tx_power_dBm[nr_tti_tx],
+ ue->prach_vars[gNB_id]->amp);
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_IN);
+
+ prach_power = generate_nr_prach(ue, gNB_id, nr_tti_tx);
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_GENERATE_PRACH, VCD_FUNCTION_OUT);
+
+ LOG_D(PHY,"[UE %d][RAPROC] PRACH PL %d dB, power %d dBm, digital power %d dB (amp %d)\n",
+ ue->Mod_id,
+ pathloss,
+ ue->tx_power_dBm[nr_tti_tx],
+ dB_fixed(prach_power),
+ ue->prach_vars[gNB_id]->amp);
+
+ if (ue->mac_enabled == 1)
+ nr_Msg1_transmitted(ue->Mod_id, ue->CC_id, frame_tx, gNB_id);
+
+ LOG_I(PHY,"[UE %d][RAPROC] Frame %d, nr_tti_tx %d: Generated PRACH Msg1 (gNB %d) preamble index %d for UL, TX power %d dBm (PL %d dB) \n",
+ ue->Mod_id,
+ frame_tx,
+ nr_tti_tx,
+ gNB_id,
+ prach_resources->ra_PreambleIndex,
+ ue->tx_power_dBm[nr_tti_tx],
+ pathloss);
+
+ LOG_D(PHY,"[UE %d] frame %d nr_tti_tx %d : prach_cnt %d\n", ue->Mod_id, frame_tx, nr_tti_tx, ue->prach_cnt);
+
+ ue->prach_cnt++;
+
+ if (ue->prach_cnt == 3)
+ ue->prach_cnt = 0;
+ } else if (nr_prach == 2) {
+ nr_ra_succeeded(mod_id, ue->CC_id, gNB_id);
+ }
+
+ // if we're calibrating the PRACH kill the pointer to its resources so that the RA protocol doesn't continue
+ if (runmode == calib_prach_tx)
+ ue->prach_resources[gNB_id] = NULL;
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_UE_TX_PRACH, VCD_FUNCTION_OUT);
+}
diff --git a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c
index 9632291e67108cc23e8ccfacd5452e3ff845909b..b51c8afbb0a19e38d8ee1b44cab4b512fbb4270c 100644
--- a/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c
+++ b/openair1/SCHED_NR_UE/pucch_power_control_ue_nr.c
@@ -104,7 +104,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue,
int P_O_PUCCH = P_O_NOMINAL_PUCCH + P_O_UE_PUCCH;
- int16_t PL = get_nr_PL(ue, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */
+ int16_t PL = get_nr_PL(ue->Mod_id, ue->CC_id, gNB_id); /* LTE function because NR path loss not yet implemented FFS TODO NR */
int16_t delta_F_PUCCH = power_config->deltaF_PUCCH_f[pucch_format];
diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
index 326c617dfb5413cffabd52a6b957a2c9574f1aa7..ccbe5021945d7cdd0fa7711b9effe5c69da73c7f 100644
--- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
+++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
@@ -37,7 +37,6 @@
#include "PHY/defs_nr_UE.h"
#include <openair1/SCHED/sched_common.h>
#include <openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h>
-#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h"
#ifndef NO_RAT_NR
@@ -162,6 +161,8 @@ void nr_generate_pucch3_4(int32_t **txdataF,
*
*********************************************************************/
+static int bwp_id = 1;
+
bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t *proc, bool reset_harq)
{
uint8_t sr_payload = 0;
@@ -187,9 +188,17 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
int pucch_resource_indicator = MAX_PUCCH_RESOURCE_INDICATOR;
int n_HARQ_ACK;
+ uint16_t crnti=0x1234;
+ int dmrs_scrambling_id=0,data_scrambling_id=0;
+
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(0);
+ NR_PUCCH_Resource_t *pucch_resource;
+ //NR_UE_MAC_INST_t *mac = get_mac_inst(0);
+
/* update current context */
- int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.ttis_per_subframe);
+ int subframe_number = (proc->nr_tti_rx)/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe);
nb_pucch_format_4_in_subframes[subframe_number] = 0; /* reset pucch format 4 counter at current rx position */
int dl_harq_pid = ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->current_harq_pid;
@@ -212,11 +221,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
/* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */
sr_payload = nr_ue_get_SR(Mod_id,
- CC_id,
- frame_tx,
- gNB_id,
- 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
- nr_tti_tx); // nr_tti_rx used for meas gap
+ CC_id,
+ frame_tx,
+ gNB_id,
+ 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
+ nr_tti_tx); // nr_tti_rx used for meas gap
}
else {
sr_payload = 1;
@@ -248,10 +257,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
}
else {
/* a resource set and a resource should be find according to payload size */
- pucch_resource_set = find_pucch_resource_set( ue, gNB_id, N_UCI);
+ pucch_resource_set = find_pucch_resource_set( mac, gNB_id, N_UCI);
if (pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) {
pucch_resource_indicator = 0;
- pucch_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set]->pucch_resource_id[pucch_resource_indicator]; /* get the first resource of the set */
+ pucch_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set]->resourceList.list.array[pucch_resource_indicator][0]; /* get the first resource of the set */
}
else {
LOG_W(PHY,"PUCCH no resource set found for CSI at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
@@ -297,7 +306,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
NR_UE_HARQ_STATUS_t *harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][0]->harq_processes[dl_harq_pid]->harq_ack;
- if (select_pucch_resource(ue, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set,
+ if (select_pucch_resource(ue, mac, gNB_id, N_UCI, pucch_resource_indicator, &initial_pucch_id, &pucch_resource_set,
&pucch_resource_id, harq_status) == TRUE) {
/* use of initial pucch configuration provided by system information 1 */
/***********************************************************************/
@@ -338,33 +347,43 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
/**********************************************/
else if ((pucch_resource_set != MAX_NB_OF_PUCCH_RESOURCE_SETS) && (pucch_resource_id != MAX_NB_OF_PUCCH_RESOURCES)) {
/* check that current configuration is supported */
- if ((ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH != FALSE)
- || (ue->cell_group_config.physicalCellGroupConfig.pdsch_HARQ_ACK_Codebook != dynamic)) {
+ if ((mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH != NULL)
+ || (mac->scg->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook != 1)) {
LOG_E(PHY,"PUCCH Unsupported cell group configuration : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
return(FALSE);
}
- else if (ue->PDSCH_ServingCellConfig.codeBlockGroupTransmission != NULL) {
+ else if (mac->scg->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) {
LOG_E(PHY,"PUCCH Unsupported code block group for serving cell config : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
return(FALSE);
}
- format = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.format;
- nb_symbols_total = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofSymbols;
- starting_symbol_index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.startingSymbolIndex;
- starting_prb = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->startingPRB;
+ pucch_resource = select_resource_by_id(pucch_resource_id, mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup);
+ format = pucch_resource->format.present;
+ nb_symbols_total = get_nb_symbols_pucch(pucch_resource, format);
+ starting_symbol_index = get_starting_symb_idx(pucch_resource, format);
+ starting_prb = pucch_resource->startingPRB;
second_hop = starting_prb;
- time_domain_occ = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.timeDomainOCC; /* format 1 only */
- occ_length = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_length; /* format 4 only */
- occ_Index = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.occ_Index; /* format 4 only */
+ if (format==pucch_format1_nr)
+ time_domain_occ = pucch_resource->format.choice.format1->timeDomainOCC;
+ if (format==pucch_format4_nr) {
+ occ_length = pucch_resource->format.choice.format4->occ_Length;
+ occ_Index = pucch_resource->format.choice.format4->occ_Index;
+ }
- if ((format == pucch_format0_nr) || (format == pucch_format1_nr)) {
- m_0 = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.initialCyclicShift;
+ m_0 = get_ics_pucch(pucch_resource, format);
+ AssertFatal(m_0 >= 0, "Invalid m_0\n");
+ if (format == pucch_format3_nr) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->additionalDMRS[0] == 1) {
+ index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS;
+ }
}
- else if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) {
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->additionalDMRS == enable_feature) {
+ else if (format == pucch_format4_nr) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->additionalDMRS[0] == 1) {
index_additional_dmrs = I_PUCCH_ADDITIONAL_DMRS;
}
+ }
- if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->intraSlotFrequencyHopping == feature_enabled) {
+ if ((format == pucch_format3_nr) || (format == pucch_format4_nr)) {
+ if (pucch_resource->intraSlotFrequencyHopping[0] == 1) {
index_hopping = I_PUCCH_HOPING;
}
}
@@ -383,6 +402,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
int O_CRC = 0;
nb_symbols = nb_symbols_total; /* by default, it can be reduced due to symbols reserved for dmrs */
+ pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[pucch_resource_id];
switch(format) {
case pucch_format0_nr:
@@ -399,14 +419,14 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
}
case pucch_format2_nr:
{
- nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs;
+ nb_of_prbs = pucch_resource->format.choice.format2->nrofPRBs;
N_sc_ctrl_RB = N_SC_RB - 4;
break;
}
case pucch_format3_nr:
{
- nb_of_prbs = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[pucch_resource_id]->format_parameters.nrofPRBs;
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) {
+ nb_of_prbs = pucch_resource->format.choice.format3->nrofPRBs;
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3->choice.setup->pi2BPSK[0] == 1) {
Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */
}
N_sc_ctrl_RB = N_SC_RB;
@@ -415,12 +435,12 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
}
case pucch_format4_nr:
{
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->pi2PBSK == feature_enabled) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4->choice.setup->pi2BPSK[0] == 1) {
Q_m = BITS_PER_SYMBOL_BPSK; /* set bpsk modulation type with 1 bit per modulation symbol */
}
nb_symbols = nb_symbols_excluding_dmrs[nb_symbols_total-4][index_additional_dmrs][index_hopping];
nb_of_prbs = 1;
- subframe_number = nr_tti_tx/(ue->frame_parms.ttis_per_subframe);
+ subframe_number = nr_tti_tx/(ue->frame_parms.slots_per_subframe);//ttis_per_subframe);
nb_pucch_format_4_in_subframes[subframe_number]++; /* increment number of transmit pucch 4 in current subframe */
NR_TST_PHY_PRINTF("PUCCH Number of pucch format 4 in subframe %d is %d \n", subframe_number, nb_pucch_format_4_in_subframes[subframe_number]);
N_sc_ctrl_RB = N_SC_RB/(nb_pucch_format_4_in_subframes[subframe_number]);
@@ -432,10 +452,10 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
/* drop CSI report if simultaneous HARQ-ACK/SR and periodic/semi-periodic CSI cannot be transmitted at the same time */
if (format != pucch_format0_nr) {
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1] != NULL) {
- max_code_rate = code_rate_r_time_100[ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->maxCodeRate]; /* it is code rate * 10 */
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) {
+ max_code_rate = code_rate_r_time_100[mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->maxCodeRate[0]]; /* it is code rate * 10 */
- if ((O_ACK != 0) && (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format-1]->simultaneousHARQ_ACK_CSI == disable_feature)) {
+ if ((O_ACK != 0) && (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->simultaneousHARQ_ACK_CSI[0] == 0)) {
N_UCI = N_UCI - O_CSI;
O_CSI = cqi_status = ri_status = 0;
csi_payload = 0; /* csi should be dropped in this case */
@@ -561,7 +581,8 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
{
nr_generate_pucch0(ue,ue->common_vars.txdataF,
&ue->frame_parms,
- &ue->pucch_config_dedicated[gNB_id],
+ mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping,
+ mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId[0],
tx_amp,
nr_tti_tx,
(uint8_t)m_0,
@@ -591,7 +612,9 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
case pucch_format2_nr:
{
nr_generate_pucch2(ue,
- 0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
+ crnti,
+ dmrs_scrambling_id,
+ data_scrambling_id,
ue->common_vars.txdataF,
&ue->frame_parms,
&ue->pucch_config_dedicated[gNB_id],
@@ -675,8 +698,11 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
int U_DAI_c = 0;
int N_m_c_rx = 0;
int V_DAI_m_DL = 0;
+ NR_UE_MAC_INST_t *mac = get_mac_inst(0);
+
+ if (mac->DLbwp[0] == NULL) return 0;
- if (ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI == nb_code_n2) {
+ if (mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0] == 2) {
two_transport_blocks = TRUE;
number_of_code_word = 2;
}
@@ -694,46 +720,49 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
for (int dl_harq_pid = 0; dl_harq_pid < number_pid_dl; dl_harq_pid++) {
- harq_status = &ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack;
+ for (int thread_idx = 0; thread_idx < RX_NB_TH; thread_idx++) {
- /* check if current tx slot should transmit downlink acknowlegment */
- if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) {
+ harq_status = &ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]->harq_ack;
- if (harq_status->ack == DL_ACKNACK_NO_SET) {
- LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
- return (0);
- }
- else if (harq_status->vDAI_DL == DL_DAI_NO_SET) {
- LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
- return (0);
- }
- else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) {
- LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
- return (0);
- }
- else if (harq_status->send_harq_status == 0) {
- LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
- return(0);
- }
- else {
+ /* check if current tx slot should transmit downlink acknowlegment */
+ if (harq_status->slot_for_feedback_ack == proc->nr_tti_tx) {
- dai_current = harq_status->vDAI_DL;
-
- if (dai_current == 0) {
- LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ if (harq_status->ack == DL_ACKNACK_NO_SET) {
+ LOG_E(PHY,"PUCCH Downlink acknowledgment has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ return (0);
+ }
+ else if (harq_status->vDAI_DL == DL_DAI_NO_SET) {
+ LOG_E(PHY,"PUCCH Downlink DAI has not been set : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ return (0);
+ }
+ else if (harq_status->vDAI_DL > NR_DL_MAX_DAI) {
+ LOG_E(PHY,"PUCCH Downlink DAI has an invalid value : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ return (0);
+ }
+ else if (harq_status->send_harq_status == 0) {
+ LOG_E(PHY,"PUCCH Downlink ack can not be transmitted : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
return(0);
- } else if (dai_current > dai_max) {
- dai_max = dai_current;
}
+ else {
- number_harq_feedback++;
- ack_data[code_word][dai_current - 1] = harq_status->ack;
- dai[code_word][dai_current - 1] = dai_current;
+ dai_current = harq_status->vDAI_DL+1; // DCI DAI to counter DAI conversion
+
+ if (dai_current == 0) {
+ LOG_E(PHY,"PUCCH Downlink dai is invalid : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ return(0);
+ } else if (dai_current > dai_max) {
+ dai_max = dai_current;
+ }
+
+ number_harq_feedback++;
+ ack_data[code_word][dai_current - 1] = harq_status->ack;
+ dai[code_word][dai_current - 1] = dai_current;
+ }
+ if (do_reset == TRUE) {
+ init_downlink_harq_status(ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]);
+ }
}
}
- if (do_reset == TRUE) {
- init_downlink_harq_status(ue->dlsch[ue->current_thread_id[proc->nr_tti_rx]][gNB_id][code_word]->harq_processes[dl_harq_pid]);
- }
}
}
@@ -752,8 +781,8 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
U_DAI_c = number_harq_feedback/number_of_code_word;
N_m_c_rx = number_harq_feedback;
int N_SPS_c = 0; /* FFS TODO_NR multicells and SPS are not supported at the moment */
- if (ue->cell_group_config.physicalCellGroupConfig.harq_ACK_SpatialBundlingPUCCH == FALSE) {
- int N_TB_max_DL = ue->PDSCH_Config.maxNrofCodeWordsScheduledByDCI;
+ if (mac->scg->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH == NULL) {
+ int N_TB_max_DL = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI[0];
*n_HARQ_ACK = (((V_DAI_m_DL - U_DAI_c)%4) * N_TB_max_DL) + N_m_c_rx + N_SPS_c;
NR_TST_PHY_PRINTF("PUCCH power n(%d) = ( V(%d) - U(%d) )mod4 * N_TB(%d) + N(%d) \n", *n_HARQ_ACK, V_DAI_m_DL, U_DAI_c, N_TB_max_DL, N_m_c_rx);
}
@@ -849,7 +878,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
*
*********************************************************************/
-boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator,
+boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator,
int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status)
{
boolean_t resource_set_found = FALSE;
@@ -857,18 +886,19 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
int current_resource_id = MAX_NB_OF_PUCCH_RESOURCES;
pucch_format_nr_t format_pucch;
int ready_pucch_resource_id = FALSE; /* in the case that it is already given */
+ NR_PUCCH_Resource_t *pucch_resource;
/* ini values to unset */
*initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE;
//*resource_set_id = MAX_NB_OF_PUCCH_RESOURCE_SETS;
//*resource_id = MAX_NB_OF_PUCCH_RESOURCES;
- if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[0] == NULL) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[0] == NULL) {
/* No resource set has been already configured so pucch_configCommon from Sib1 should be used in this case */
if (ue->UE_mode[gNB_id] != PUSCH) {
- *initial_pucch_id = ue->pucch_config_common_nr[gNB_id].pucch_ResourceCommon;
+ *initial_pucch_id = mac->ULbwp[bwp_id-1]->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_ResourceCommon[0];
if (*initial_pucch_id >= NB_INITIAL_PUCCH_RESOURCE) {
LOG_E(PHY,"PUCCH Invalid initial resource index : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
*initial_pucch_id = NB_INITIAL_PUCCH_RESOURCE;
@@ -893,7 +923,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
}
nb_symbols_for_tx = initial_pucch_resource[*initial_pucch_id].nrofSymbols;
format_pucch = initial_pucch_resource[*initial_pucch_id].format;
- if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) {
+ if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) {
return (TRUE);
}
else {
@@ -913,7 +943,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
-- This field can take integer values that are multiples of 4. Corresponds to L1 parameter 'N_2' or 'N_3' (see 38.213, section 9.2)
*/
/* look for the first resource set which supports uci_size number of bits for payload */
- pucch_resource_set_id = find_pucch_resource_set( ue, gNB_id, uci_size);
+ pucch_resource_set_id = find_pucch_resource_set(mac, gNB_id, uci_size);
if (pucch_resource_set_id != MAX_NB_OF_PUCCH_RESOURCE_SETS) {
resource_set_found = TRUE;
}
@@ -928,13 +958,13 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
if (resource_set_found == TRUE) {
if (pucch_resource_indicator < MAX_PUCCH_RESOURCE_INDICATOR) {
/* check if resource indexing by pucch_resource_indicator of this set is compatible */
- if ((ready_pucch_resource_id == TRUE) || (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator] != MAX_NB_OF_PUCCH_RESOURCES)) {
+ if ((ready_pucch_resource_id == TRUE) || (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0] != MAX_NB_OF_PUCCH_RESOURCES)) {
if (ready_pucch_resource_id == TRUE) {
current_resource_id = *resource_id;
}
else {
- int R_PUCCH = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->first_resources_set_R_PUCCH;
+ int R_PUCCH = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.count;
/* is it the first resource and its size exceeds 8 */
if ((pucch_resource_set_id == 0)
&& (R_PUCCH > MAX_NB_OF_PUCCH_RESOURCES_PER_SET_NOT_0)) {
@@ -956,15 +986,22 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
current_resource_id = r_PUCCH;
}
else {
- current_resource_id = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->pucch_resource_id[pucch_resource_indicator];
+ current_resource_id = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->resourceList.list.array[pucch_resource_indicator][0];
}
}
- if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id] != NULL) {
- nb_symbols_for_tx = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.nrofSymbols;
- format_pucch = ue->pucch_config_dedicated_nr[gNB_id].PUCCH_Resource[current_resource_id]->format_parameters.format;
+ /*uint8_t pucch_resource_count = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.count;
+ for (uint8_t i=0; i<pucch_resource_count; i++) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i]->pucch_ResourceId == current_resource_id)
+ pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList.list.array[i];
+ }*/
+
+ pucch_resource = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id];
+ if (pucch_resource != NULL) {
+ format_pucch = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceToAddModList->list.array[current_resource_id]->format.present;
+ nb_symbols_for_tx = get_nb_symbols_pucch(pucch_resource, format_pucch);
- if (check_pucch_format(ue, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) {
+ if (check_pucch_format(mac, gNB_id, format_pucch, nb_symbols_for_tx, uci_size) == TRUE) {
*resource_set_id = pucch_resource_set_id;
*resource_id = current_resource_id;
return (TRUE);
@@ -1010,9 +1047,10 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
*
*********************************************************************/
-int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size)
+int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size)
{
int pucch_resource_set_id = 0;
+ long *pucch_max_pl_bits = NULL;
/* from TS 38.331 field maxPayloadMinus1
-- Maximum number of payload bits minus 1 that the UE may transmit using this PUCCH resource set. In a PUCCH occurrence, the UE
@@ -1023,8 +1061,9 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size)
*/
/* look for the first resource set which supports uci_size number of bits for payload */
while (pucch_resource_set_id < MAX_NB_OF_PUCCH_RESOURCE_SETS) {
- if (ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id] != NULL) {
- if (uci_size <= ue->pucch_config_dedicated_nr[gNB_id].PUCCH_ResourceSet[pucch_resource_set_id]->maxPayloadMinus1 + 1) {
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id] != NULL) {
+ pucch_max_pl_bits = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->resourceSetToAddModList->list.array[pucch_resource_set_id]->maxPayloadMinus1;
+ if (uci_size <= (((pucch_max_pl_bits != NULL) ? *pucch_max_pl_bits : 1706) + 1)) {
NR_TST_PHY_PRINTF("PUCCH found resource set %d \n", pucch_resource_set_id);
return (pucch_resource_set_id);
break;
@@ -1053,18 +1092,40 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size)
*
*********************************************************************/
-boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size)
+boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx, int uci_size)
{
pucch_format_nr_t selected_pucch_format;
pucch_format_nr_t selected_pucch_format_second;
+ NR_SetupRelease_PUCCH_FormatConfig_t *identified_format = NULL;
- if (format_pucch != pucch_format0_nr) {
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1] != NULL) {
- if (ue->pucch_config_dedicated_nr[gNB_id].formatConfig[format_pucch-1]->nrofSlots != 1) {
- LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
- return (FALSE);
- }
- }
+ switch (format_pucch) {
+ case pucch_format1_nr:
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL)
+ identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1;
+ break;
+
+ case pucch_format2_nr:
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2 != NULL)
+ identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format2;
+ break;
+
+ case pucch_format3_nr:
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3 != NULL)
+ identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format3;
+ break;
+
+ case pucch_format4_nr:
+ if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4 != NULL)
+ identified_format = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format4;
+ break;
+
+ default:
+ break;
+ }
+
+ if ((identified_format != NULL) && (identified_format->choice.setup->nrofSlots[0] != 1)) {
+ LOG_E(PHY,"PUCCH not implemented multislots transmission : at line %d in function %s of file %s \n", LINE_FILE , __func__, FILE_NAME);
+ return (FALSE);
}
if (nb_symbols_for_tx <= 2) {
@@ -1156,7 +1217,7 @@ int trigger_periodic_scheduling_request(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_n
return (1); /* period is slot */
}
- int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.ttis_per_subframe;
+ int16_t N_slot_frame = NR_NUMBER_OF_SUBFRAMES_PER_FRAME * ue->frame_parms.slots_per_subframe;//ttis_per_subframe;
if (((proc->frame_tx * N_slot_frame) + proc->nr_tti_tx - SR_offset)%SR_periodicity == 0) {
return (1);
}
@@ -1215,4 +1276,74 @@ void set_csi_nr(int csi_status, uint32_t csi_payload)
}
}
+uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type)
+{
+ switch (format_type) {
+ case pucch_format0_nr:
+ return pucch_resource->format.choice.format0->nrofSymbols;
+
+ case pucch_format1_nr:
+ return pucch_resource->format.choice.format1->nrofSymbols;
+
+ case pucch_format2_nr:
+ return pucch_resource->format.choice.format2->nrofSymbols;
+
+ case pucch_format3_nr:
+ return pucch_resource->format.choice.format3->nrofSymbols;
+
+ case pucch_format4_nr:
+ return pucch_resource->format.choice.format4->nrofSymbols;
+ }
+ return 0;
+}
+
+uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type)
+{
+ switch (format_type) {
+ case pucch_format0_nr:
+ return pucch_resource->format.choice.format0->startingSymbolIndex;
+
+ case pucch_format1_nr:
+ return pucch_resource->format.choice.format1->startingSymbolIndex;
+
+ case pucch_format2_nr:
+ return pucch_resource->format.choice.format2->startingSymbolIndex;
+
+ case pucch_format3_nr:
+ return pucch_resource->format.choice.format3->startingSymbolIndex;
+
+ case pucch_format4_nr:
+ return pucch_resource->format.choice.format4->startingSymbolIndex;
+ }
+ return 0;
+}
+
+int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type)
+{
+ switch (format_type) {
+ case pucch_format0_nr:
+ return pucch_resource->format.choice.format0->initialCyclicShift;
+
+ case pucch_format1_nr:
+ return pucch_resource->format.choice.format1->initialCyclicShift;
+
+ default:
+ return -1;
+ }
+ return -1;
+}
+
+NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config)
+{
+ int n_list = pucch_config->resourceToAddModList->list.count;
+ NR_PUCCH_Resource_t *pucchres;
+ AssertFatal(n_list>0,"PUCCH resourceToAddModList is empty\n");
+
+ for (int i=0; i<n_list; i++) {
+ pucchres = pucch_config->resourceToAddModList->list.array[i];
+ if (pucchres->pucch_ResourceId == resource_id)
+ return pucchres;
+ }
+ return NULL;
+}
diff --git a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h
index 85cd969e2638d0478ce87077a36bde1a6bfec71c..089fae9f55cbb328617d4cef498477656713d433 100644
--- a/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h
+++ b/openair1/SCHED_NR_UE/pucch_uci_ue_nr.h
@@ -41,6 +41,9 @@
/************** INCLUDE *******************************************/
#include "PHY/defs_nr_UE.h"
+#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h"
+#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h"
+#include "RRC/NR_UE/rrc_proto.h"
#ifdef DEFINE_VARIABLES_PUCCH_UE_NR_H
#define EXTERN
@@ -187,7 +190,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
@param resource_id pucch resource id if any
@returns TRUE a pucch resource has been found FALSE no valid pucch resource */
-boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size, int pucch_resource_indicator,
+boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size, int pucch_resource_indicator,
int *initial_pucch_id, int *resource_set_id, int *resource_id, NR_UE_HARQ_STATUS_t *harq_status);
/** \brief This function select a pucch resource set
@@ -196,7 +199,7 @@ boolean_t select_pucch_resource(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size
@param uci size number of uci bits
@returns number of the pucch resource set */
-int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size);
+int find_pucch_resource_set(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, int uci_size);
/** \brief This function check pucch format
@param ue context
@@ -206,7 +209,7 @@ int find_pucch_resource_set(PHY_VARS_NR_UE *ue, uint8_t gNB_id, int uci_size);
@param uci size number of uci bits
@returns TRUE pucch format matched uci size and constraints, FALSE invalid pucch format */
-boolean_t check_pucch_format(PHY_VARS_NR_UE *ue, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx,
+boolean_t check_pucch_format(NR_UE_MAC_INST_t *mac, uint8_t gNB_id, pucch_format_nr_t format_pucch, int nb_symbols_for_tx,
int uci_size);
/** \brief This function selects a pucch resource
@@ -232,4 +235,11 @@ int get_csi_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, uint32_t *csi_payload);
void set_csi_nr(int csi_status, uint32_t csi_payload);
+uint8_t get_nb_symbols_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type);
+
+uint16_t get_starting_symb_idx(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type);
+
+int get_ics_pucch(NR_PUCCH_Resource_t *pucch_resource, pucch_format_nr_t format_type);
+
+NR_PUCCH_Resource_t *select_resource_by_id(int resource_id, NR_PUCCH_Config_t *pucch_config);
#endif /* PUCCH_UCI_UE_NR_H */
diff --git a/openair1/SCHED_UE/phy_procedures_lte_ue.c b/openair1/SCHED_UE/phy_procedures_lte_ue.c
index e0ea4ef2b28dc0144ac6c19e0ad7f336d36d0be2..3215718f8ec4805c5c9d4371e90c09a5086ad662 100644
--- a/openair1/SCHED_UE/phy_procedures_lte_ue.c
+++ b/openair1/SCHED_UE/phy_procedures_lte_ue.c
@@ -2383,10 +2383,12 @@ void ue_pbch_procedures(uint8_t eNB_id,
if (pbch_phase>=4)
pbch_phase=0;
+if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || first_run) {
+
for (pbch_trials=0; pbch_trials<4; pbch_trials++) {
//for (pbch_phase=0;pbch_phase<4;pbch_phase++) {
//LOG_I(PHY,"[UE %d] Frame %d, Trying PBCH %d (NidCell %d, eNB_id %d)\n",ue->Mod_id,frame_rx,pbch_phase,ue->frame_parms.Nid_cell,eNB_id);
- if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms)) {
+ if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || ue->frame_parms.FeMBMS_active) {
pbch_tx_ant = rx_pbch_fembms(&ue->common_vars,
ue->pbch_vars[eNB_id],
&ue->frame_parms,
@@ -2431,9 +2433,10 @@ void ue_pbch_procedures(uint8_t eNB_id,
ue->pbch_vars[eNB_id]->pdu_errors_conseq = 0;
- if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms)) {
+ if(is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || ue->frame_parms.FeMBMS_active) {
frame_tx = (int)((ue->pbch_vars[eNB_id]->decoded_output[2]&31)<<1);
frame_tx += ue->pbch_vars[eNB_id]->decoded_output[1]>>7;
+ frame_tx = frame_tx<<4;
frame_tx +=4*pbch_phase;
} else {
frame_tx = (((int)(ue->pbch_vars[eNB_id]->decoded_output[2]&0x03))<<8);
@@ -2490,7 +2493,7 @@ void ue_pbch_procedures(uint8_t eNB_id,
}
if (LOG_DEBUGFLAG(DEBUG_UE_PHYPROC)) {
- LOG_UI(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n",
+ LOG_D(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n",
ue->Mod_id,
frame_rx,
subframe_rx,
@@ -2501,6 +2504,17 @@ void ue_pbch_procedures(uint8_t eNB_id,
ue->frame_parms.phich_config_common.phich_duration,
ue->frame_parms.phich_config_common.phich_resource);
}
+ LOG_D(PHY,"[UE %d] frame %d, subframe %d, Received PBCH (MIB): nb_antenna_ports_eNB %d, tx_ant %d, frame_tx %d. N_RB_DL %d, phich_duration %d, phich_resource %d/6!\n",
+ ue->Mod_id,
+ frame_rx,
+ subframe_rx,
+ ue->frame_parms.nb_antenna_ports_eNB,
+ pbch_tx_ant,
+ frame_tx,
+ ue->frame_parms.N_RB_DL,
+ ue->frame_parms.phich_config_common.phich_duration,
+ ue->frame_parms.phich_config_common.phich_resource);
+
} else {
if (LOG_DUMPFLAG(DEBUG_UE_PHYPROC)) {
LOG_E(PHY,"[UE %d] frame %d, subframe %d, Error decoding PBCH!\n",
@@ -2533,6 +2547,8 @@ void ue_pbch_procedures(uint8_t eNB_id,
ue->pbch_vars[eNB_id]->pdu_errors_conseq);
}
+} //if((ue->frame_parms.FeMBMS_active == 0)|| is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || first_run)
+
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PBCH_PROCEDURES, VCD_FUNCTION_OUT);
}
@@ -2877,10 +2893,19 @@ void ue_pmch_procedures(PHY_VARS_UE *ue,
int l;
int ret=0;
- if (is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms)) {
+ if (is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms) || fembms_flag) {
// LOG_D(PHY,"ue calling pmch subframe ..\n ");
LOG_D(PHY,"[UE %d] Frame %d, subframe %d: Querying for PMCH demodulation\n",
ue->Mod_id,frame_rx,subframe_rx);
+ if(fembms_flag)
+ pmch_mcs = ue_query_mch_fembms(ue->Mod_id,
+ CC_id,
+ frame_rx,
+ subframe_rx,
+ eNB_id,
+ &sync_area,
+ &mcch_active);
+ else
pmch_mcs = ue_query_mch(ue->Mod_id,
CC_id,
frame_rx,
@@ -2960,6 +2985,7 @@ void ue_pmch_procedures(PHY_VARS_UE *ue,
LOG_D(PHY,"start turbo decode for MCH %d.%d --> Nl %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->harq_processes[0]->Nl);
LOG_D(PHY,"start turbo decode for MCH %d.%d --> G %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->harq_processes[0]->G);
LOG_D(PHY,"start turbo decode for MCH %d.%d --> Kmimo %d \n", frame_rx, subframe_rx, ue->dlsch_MCH[0]->Kmimo);
+
ret = dlsch_decoding(ue,
ue->pdsch_vars_MCH[ue->current_thread_id[subframe_rx]][0]->llr[0],
&ue->frame_parms,
@@ -3007,14 +3033,14 @@ void ue_pmch_procedures(PHY_VARS_UE *ue,
// if (subframe_rx==9)
// mac_xface->macphy_exit("Why are we exiting here?");
} else { // decoding successful
- LOG_D(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d)\n",
+ LOG_D(PHY,"[UE %d] Frame %d, subframe %d: PMCH OK (%d,%d), passing to L2 (TBS %d, iter %d,G %d) ret %d\n",
ue->Mod_id,
frame_rx,subframe_rx,
ue->dlsch_mcch_errors[sync_area][0],
ue->dlsch_mtch_errors[sync_area][0],
ue->dlsch_MCH[0]->harq_processes[0]->TBS>>3,
ue->dlsch_MCH[0]->max_turbo_iterations,
- ue->dlsch_MCH[0]->harq_processes[0]->G);
+ ue->dlsch_MCH[0]->harq_processes[0]->G,ret);
ue_send_mch_sdu(ue->Mod_id,
CC_id,
frame_rx,
@@ -3022,6 +3048,8 @@ void ue_pmch_procedures(PHY_VARS_UE *ue,
ue->dlsch_MCH[0]->harq_processes[0]->TBS>>3,
eNB_id,// not relevant in eMBMS context
sync_area);
+ //dump_mch(ue,0,ue->dlsch_MCH[0]->harq_processes[0]->G,subframe_rx);
+ //exit_fun("nothing to add");
if (mcch_active == 1)
ue->dlsch_mcch_received[sync_area][0]++;
@@ -4429,6 +4457,15 @@ int phy_procedures_UE_RX(PHY_VARS_UE *ue,
ue_pmch_procedures(ue,proc,eNB_id,abstraction_flag,1);
return 0;
} else { // this gets closed at end
+ if (is_fembms_cas_subframe(frame_rx,subframe_rx,&ue->frame_parms) || is_fembms_nonMBSFN_subframe(frame_rx,subframe_rx,&ue->frame_parms) ) {
+ l=0;
+ slot_fep(ue,
+ l,
+ subframe_rx<<1,
+ 0,
+ 0,
+ 0);
+ }
pmch_flag = is_pmch_subframe(frame_rx,subframe_rx,&ue->frame_parms) ? 1 : 0;
if (do_pdcch_flag) {
diff --git a/openair1/SIMULATION/ETH_TRANSPORT/socket.h b/openair1/SIMULATION/ETH_TRANSPORT/socket.h
index c7a2224375e8f9d797c0ad9c6bf515dc1f90f9e1..e9ca36bee2a13d7d4b1b1d9bcacad9f62c920d24 100644
--- a/openair1/SIMULATION/ETH_TRANSPORT/socket.h
+++ b/openair1/SIMULATION/ETH_TRANSPORT/socket.h
@@ -28,8 +28,9 @@
* \email: lionel.gauthier@eurecom.fr
*/
-#ifndef __SOCKET_H__
-# define __SOCKET_H__
+#ifndef __SIMULATION_ETH_TRANSPORT_SOCKET__H__
+#define __SIMULATION_ETH_TRANSPORT_SOCKET__H__
+
# ifdef SOCKET_C
# define private_socket(x) x
# define public_socket(x) x
diff --git a/openair1/SIMULATION/LTE_PHY/dummy_functions.c b/openair1/SIMULATION/LTE_PHY/dummy_functions.c
index 5ec0f6e6967cc2ae27bfe8b9b3b5d3d199b9525c..120e4845d92608ccc11c9f30080030fc70f8e103 100644
--- a/openair1/SIMULATION/LTE_PHY/dummy_functions.c
+++ b/openair1/SIMULATION/LTE_PHY/dummy_functions.c
@@ -67,6 +67,11 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
sub_frame_t subframe, uint8_t eNB_index,
uint8_t * sync_area, uint8_t * mcch_active){ return(0);}
+
+int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
+ sub_frame_t subframe, uint8_t eNB_index,
+ uint8_t * sync_area, uint8_t * mcch_active){ return(0);}
+
void dl_phy_sync_success(module_id_t module_idP,
frame_t frameP,
unsigned char eNB_index, uint8_t first_sync){}
diff --git a/openair1/SIMULATION/LTE_PHY/mbmssim.c b/openair1/SIMULATION/LTE_PHY/mbmssim.c
index 65415e7c68b97633eff7557dfe51ffba935f70f5..5073be24f5f3f73d8fc1667eb53342bcf7e13cba 100644
--- a/openair1/SIMULATION/LTE_PHY/mbmssim.c
+++ b/openair1/SIMULATION/LTE_PHY/mbmssim.c
@@ -19,204 +19,1048 @@
* contact@openairinterface.org
*/
+/*! \file mbmssim.c
+ \brief Top-level MBMS DL simulator
+ \authors R. Knopp, J. Morgade
+ \date 2011 - 2014 (Knopp) / 2020 (Morgade)
+ \version 0.1
+ \company Eurecom
+ \email: knopp@eurecom.fr, javier.morgade@ieee.org
+ \note
+ \warning
+*/
+
#include <string.h>
#include <math.h>
#include <unistd.h>
-#include <fcntl.h>
-#include <sys/ioctl.h>
-#include <sys/mman.h>
+#include <execinfo.h>
+#include <signal.h>
-#include "SIMULATION/TOOLS/defs.h"
-#include "SIMULATION/RF/defs.h"
+#include "SIMULATION/TOOLS/sim.h"
#include "PHY/types.h"
-#include "PHY/defs.h"
-#include "PHY/vars.h"
-#include "SCHED/defs.h"
-#include "SCHED/vars.h"
-#include "LAYER2/MAC/vars.h"
-
-#ifdef XFORMS
- #include "PHY/TOOLS/lte_phy_scope.h"
-#endif //XFORMS
+#include "PHY/defs_eNB.h"
+#include "PHY/defs_UE.h"
+#include "PHY/phy_vars.h"
+#include "SCHED/sched_eNB.h"
+#include "SCHED/sched_common_vars.h"
+#include "LAYER2/MAC/mac_vars.h"
#include "OCG_vars.h"
+#include "common/utils/LOG/log.h"
+#include "UTIL/LISTS/list.h"
+
#include "unitary_defs.h"
-PHY_VARS_eNB *eNB;
-PHY_VARS_UE *UE;
+#include "PHY/TOOLS/lte_phy_scope.h"
+
+#include "dummy_functions.c"
+
+#include "PHY/MODULATION/modulation_common.h"
+#include "PHY/MODULATION/modulation_eNB.h"
+#include "PHY/MODULATION/modulation_UE.h"
+#include "PHY/LTE_TRANSPORT/transport_proto.h"
+#include "PHY/LTE_UE_TRANSPORT/transport_proto_ue.h"
+#include "SCHED/sched_eNB.h"
+#include "SCHED_UE/sched_UE.h"
+#include "common/config/config_load_configmodule.h"
+#include "PHY/INIT/phy_init.h"
+#include "nfapi/oai_integration/vendor_ext.h"
+
+#define ENABLE_MBMS_SIM
+
+int enable_fembms=1;
+
+void feptx_ofdm(RU_t *ru);
+void feptx_prec(RU_t *ru);
double cpuf;
+#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0))
+//#define MCS_COUNT 23//added for PHY abstraction
+#include <openair1/SIMULATION/LTE_PHY/common_sim.h>
+
+int otg_enabled=0;
+/*the following parameters are used to control the processing times calculations*/
+double t_tx_max = -1000000000; /*!< \brief initial max process time for tx */
+double t_rx_max = -1000000000; /*!< \brief initial max process time for rx */
+double t_tx_min = 1000000000; /*!< \brief initial min process time for tx */
+double t_rx_min = 1000000000; /*!< \brief initial min process time for rx */
+int n_tx_dropped = 0; /*!< \brief initial max process time for tx */
+int n_rx_dropped = 0; /*!< \brief initial max process time for rx */
+
+THREAD_STRUCT thread_struct;
+
+int emulate_rf = 0;
+
+void handler(int sig) {
+ void *array[10];
+ size_t size;
+ // get void*'s for all entries on the stack
+ size = backtrace(array, 10);
+ // print out all the frames to stderr
+ fprintf(stderr, "Error: signal %d:\n", sig);
+ backtrace_symbols_fd(array, size, 2);
+ exit(1);
+}
+
+
+
+//DCI2_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu2_2A[2];
DCI1E_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu2_1E[2];
+uint64_t DLSCH_alloc_pdu_1[2];
+
#define UL_RB_ALLOC 0x1ff;
#define CCCH_RB_ALLOC computeRIV(eNB->frame_parms.N_RB_UL,0,2)
+//#define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13
+//#define DLSCH_RB_ALLOC 0x0001
+void do_OFDM_mod_l(int32_t **txdataF, int32_t **txdata, uint16_t next_slot, LTE_DL_FRAME_PARMS *frame_parms) {
+ int aa, slot_offset, slot_offset_F;
+ slot_offset_F = (next_slot)*(frame_parms->ofdm_symbol_size)*((frame_parms->Ncp==1) ? 6 : 7);
+ slot_offset = (next_slot)*(frame_parms->samples_per_tti>>1);
+
+ for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
+ // printf("Thread %d starting ... aa %d (%llu)\n",omp_get_thread_num(),aa,rdtsc());
+ if (frame_parms->Ncp == 1)
+ PHY_ofdm_mod(&txdataF[aa][slot_offset_F], // input
+ &txdata[aa][slot_offset], // output
+ frame_parms->ofdm_symbol_size,
+ 6, // number of symbols
+ frame_parms->nb_prefix_samples, // number of prefix samples
+ CYCLIC_PREFIX);
+ else {
+ normal_prefix_mod(&txdataF[aa][slot_offset_F],
+ &txdata[aa][slot_offset],
+ 7,
+ frame_parms);
+ }
+ }
+}
+
+void DL_channel(RU_t *ru,PHY_VARS_UE *UE,uint subframe,int awgn_flag,double SNR, int tx_lev,int hold_channel,int abstx, int num_rounds, int trials, int round, channel_desc_t *eNB2UE[4],
+ double *s_re[2],double *s_im[2],double *r_re[2],double *r_im[2],FILE *csv_fd) {
+ int i,u;
+ int aa,aarx,aatx;
+ double channelx,channely;
+ double sigma2_dB,sigma2;
+ double iqim=0.0;
+
+ // printf("Copying tx ..., nsymb %d (n_tx %d), awgn %d\n",nsymb,eNB->frame_parms.nb_antennas_tx,awgn_flag);
+ for (i=0; i<2*UE->frame_parms.samples_per_tti; i++) {
+ for (aa=0; aa<ru->frame_parms.nb_antennas_tx; aa++) {
+ if (awgn_flag == 0) {
+ s_re[aa][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) + (i<<1)]);
+ s_im[aa][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]);
+ } else {
+ for (aarx=0; aarx<UE->frame_parms.nb_antennas_rx; aarx++) {
+ if (aa==0) {
+ r_re[aarx][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)]);
+ r_im[aarx][i] = ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]);
+ } else {
+ r_re[aarx][i] += ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)]);
+ r_im[aarx][i] += ((double)(((short *)ru->common.txdata[aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]);
+ }
+ }
+ }
+ }
+ }
+
+ // Multipath channel
+ if (awgn_flag == 0) {
+ multipath_channel(eNB2UE[round],s_re,s_im,r_re,r_im,
+ 2*UE->frame_parms.samples_per_tti,hold_channel);
+
+ // printf("amc: ****************** eNB2UE[%d]->n_rx = %d,dd %d\n",round,eNB2UE[round]->nb_rx,eNB2UE[round]->channel_offset);
+ if(abstx==1 && num_rounds>1)
+ if(round==0 && hold_channel==0) {
+ random_channel(eNB2UE[1],0);
+ random_channel(eNB2UE[2],0);
+ random_channel(eNB2UE[3],0);
+ }
+
+ if (UE->perfect_ce==1) {
+ // fill in perfect channel estimates
+ freq_channel(eNB2UE[round],UE->frame_parms.N_RB_DL,12*UE->frame_parms.N_RB_DL + 1);
+ /*
+ LOG_M("channel.m","ch",eNB2UE[round]->ch[0],eNB2UE[round]->channel_length,1,8);
+ LOG_M("channelF.m","chF",eNB2UE[round]->chF[0],12*UE->frame_parms.N_RB_DL + 1,1,8);
+ */
+ }
+ }
+
+ if(abstx) {
+ if (trials==0 && round==0) {
+ // calculate freq domain representation to compute SINR
+ freq_channel(eNB2UE[0], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1);
+ // snr=pow(10.0,.1*SNR);
+ fprintf(csv_fd,"%f,",SNR);
+
+ for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) {
+ for (aarx=0; aarx<eNB2UE[0]->nb_rx; aarx++) {
+ for (aatx=0; aatx<eNB2UE[0]->nb_tx; aatx++) {
+ channelx = eNB2UE[0]->chF[aarx+(aatx*eNB2UE[0]->nb_rx)][u].x;
+ channely = eNB2UE[0]->chF[aarx+(aatx*eNB2UE[0]->nb_rx)][u].y;
+ fprintf(csv_fd,"%e+i*(%e),",channelx,channely);
+ }
+ }
+ }
+
+ if(num_rounds>1) {
+ freq_channel(eNB2UE[1], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1);
+
+ for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) {
+ for (aarx=0; aarx<eNB2UE[1]->nb_rx; aarx++) {
+ for (aatx=0; aatx<eNB2UE[1]->nb_tx; aatx++) {
+ channelx = eNB2UE[1]->chF[aarx+(aatx*eNB2UE[1]->nb_rx)][u].x;
+ channely = eNB2UE[1]->chF[aarx+(aatx*eNB2UE[1]->nb_rx)][u].y;
+ fprintf(csv_fd,"%e+i*(%e),",channelx,channely);
+ }
+ }
+ }
+
+ freq_channel(eNB2UE[2], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1);
+
+ for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) {
+ for (aarx=0; aarx<eNB2UE[2]->nb_rx; aarx++) {
+ for (aatx=0; aatx<eNB2UE[2]->nb_tx; aatx++) {
+ channelx = eNB2UE[2]->chF[aarx+(aatx*eNB2UE[2]->nb_rx)][u].x;
+ channely = eNB2UE[2]->chF[aarx+(aatx*eNB2UE[2]->nb_rx)][u].y;
+ fprintf(csv_fd,"%e+i*(%e),",channelx,channely);
+ }
+ }
+ }
+
+ freq_channel(eNB2UE[3], ru->frame_parms.N_RB_DL,2*ru->frame_parms.N_RB_DL + 1);
+
+ for (u=0; u<2*ru->frame_parms.N_RB_DL; u++) {
+ for (aarx=0; aarx<eNB2UE[3]->nb_rx; aarx++) {
+ for (aatx=0; aatx<eNB2UE[3]->nb_tx; aatx++) {
+ channelx = eNB2UE[3]->chF[aarx+(aatx*eNB2UE[3]->nb_rx)][u].x;
+ channely = eNB2UE[3]->chF[aarx+(aatx*eNB2UE[3]->nb_rx)][u].y;
+ fprintf(csv_fd,"%e+i*(%e),",channelx,channely);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ //AWGN
+ // tx_lev is the average energy over the whole subframe
+ // but SNR should be better defined wrt the energy in the reference symbols
+ sigma2_dB = 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR;
+ sigma2 = pow(10,sigma2_dB/10);
+
+ for (i=0; i<2*UE->frame_parms.samples_per_tti; i++) {
+ for (aa=0; aa<UE->frame_parms.nb_antennas_rx; aa++) {
+ //printf("s_re[0][%d]=> %f , r_re[0][%d]=> %f\n",i,s_re[aa][i],i,r_re[aa][i]);
+ ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i] =
+ (short) (r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0));
+ ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i+1] =
+ (short) (r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0));
+ }
+ }
+}
+
+uint16_t
+fill_tx_req(nfapi_tx_request_body_t *tx_req_body,
+ uint16_t absSF,
+ uint16_t pdu_length,
+ uint16_t pdu_index,
+ uint8_t *pdu) {
+ nfapi_tx_request_pdu_t *TX_req = &tx_req_body->tx_pdu_list[tx_req_body->number_of_pdus];
+ LOG_D(MAC, "Filling TX_req %d for pdu length %d\n",
+ tx_req_body->number_of_pdus, pdu_length);
+ TX_req->pdu_length = pdu_length;
+ TX_req->pdu_index = pdu_index;
+ TX_req->num_segments = 1;
+ TX_req->segments[0].segment_length = pdu_length;
+ TX_req->segments[0].segment_data = pdu;
+ tx_req_body->tl.tag = NFAPI_TX_REQUEST_BODY_TAG;
+ tx_req_body->number_of_pdus++;
+ return (((absSF / 10) << 4) + (absSF % 10));
+}
+
+void
+fill_mch_config(nfapi_dl_config_request_body_t *dl_req,
+ uint16_t length,
+ uint16_t pdu_index,
+ uint16_t rnti,
+ uint8_t resource_allocation_type,
+ uint16_t resource_block_coding,
+ uint8_t modulation,
+ uint16_t transmission_power,
+ uint8_t mbsfn_area_id){
+ nfapi_dl_config_request_pdu_t *dl_config_pdu =
+ &dl_req->dl_config_pdu_list[dl_req->number_pdu];
+ memset((void *) dl_config_pdu, 0,
+ sizeof(nfapi_dl_config_request_pdu_t));
+ dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_MCH_PDU_TYPE;
+ dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_mch_pdu));
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_MCH_PDU_REL8_TAG;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.length = length;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.pdu_index = pdu_index;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.rnti = rnti;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.resource_allocation_type = resource_allocation_type;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.resource_block_coding = resource_block_coding;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.modulation = modulation;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.transmission_power = transmission_power;
+ dl_config_pdu->mch_pdu.mch_pdu_rel8.mbsfn_area_id = mbsfn_area_id;
+ dl_req->number_pdu++;
+}
+
+void
+fill_dlsch_config(nfapi_dl_config_request_body_t *dl_req,
+ uint16_t length,
+ uint16_t pdu_index,
+ uint16_t rnti,
+ uint8_t resource_allocation_type,
+ uint8_t virtual_resource_block_assignment_flag,
+ uint16_t resource_block_coding,
+ uint8_t modulation,
+ uint8_t redundancy_version,
+ uint8_t transport_blocks,
+ uint8_t transport_block_to_codeword_swap_flag,
+ uint8_t transmission_scheme,
+ uint8_t number_of_layers,
+ uint8_t number_of_subbands,
+ // uint8_t codebook_index,
+ uint8_t ue_category_capacity,
+ uint8_t pa,
+ uint8_t delta_power_offset_index,
+ uint8_t ngap,
+ uint8_t nprb,
+ uint8_t transmission_mode,
+ uint8_t num_bf_prb_per_subband,
+ uint8_t num_bf_vector) {
+ nfapi_dl_config_request_pdu_t *dl_config_pdu =
+ &dl_req->dl_config_pdu_list[dl_req->number_pdu];
+ memset((void *) dl_config_pdu, 0,
+ sizeof(nfapi_dl_config_request_pdu_t));
+ dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DLSCH_PDU_TYPE;
+ dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dlsch_pdu));
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DLSCH_PDU_REL8_TAG;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.length = length;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pdu_index = pdu_index;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.rnti = rnti;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_allocation_type = resource_allocation_type;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.virtual_resource_block_assignment_flag = virtual_resource_block_assignment_flag;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.resource_block_coding = resource_block_coding;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.modulation = modulation;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.redundancy_version = redundancy_version;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_blocks = transport_blocks;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transport_block_to_codeword_swap_flag = transport_block_to_codeword_swap_flag;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_scheme = transmission_scheme;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_layers = number_of_layers;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.number_of_subbands = number_of_subbands;
+ // dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.codebook_index = codebook_index;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ue_category_capacity = ue_category_capacity;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.pa = pa;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.delta_power_offset_index = delta_power_offset_index;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.ngap = ngap;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.nprb = nprb;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.transmission_mode = transmission_mode;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_prb_per_subband = num_bf_prb_per_subband;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel8.num_bf_vector = num_bf_vector;
+ dl_config_pdu->dlsch_pdu.dlsch_pdu_rel13.initial_transmission_sf_io = 0xFFFF;
+ dl_req->number_pdu++;
+}
+
+void fill_MCH(PHY_VARS_eNB *eNB,
+ int frame,
+ int subframe,
+ Sched_Rsp_t *sched_resp,
+ uint8_t input_buffer[NUMBER_OF_UE_MAX][20000],
+ int n_rnti,
+ int common_flag,
+ int NB_RB,
+ int TPC,
+ int mcs1){
+
+ nfapi_dl_config_request_body_t *dl_req=&sched_resp->DL_req->dl_config_request_body;
+ nfapi_dl_config_request_pdu_t *dl_config_pdu;
+ nfapi_tx_request_body_t *TX_req=&sched_resp->TX_req->tx_request_body;
+ int NB_RB4TBS = common_flag == 0 ? NB_RB : (2+TPC);
+ dl_req->number_dci=0;
+ dl_req->number_pdu=0;
+ TX_req->number_of_pdus=0;
+ dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG;
+ fill_mch_config(
+ dl_req,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ 0,
+ 0xfffd,
+ 0,
+ get_Qm(mcs1),
+ mcs1,
+ 6000, //equal to RS power
+ 0 //mbsfn_area_id
+ );
+
+ fill_tx_req(TX_req,
+ (frame * 10) + subframe,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ 0,
+ input_buffer[0]);
+}
+
+void fill_DCI(PHY_VARS_eNB *eNB,
+ int frame,
+ int subframe,
+ Sched_Rsp_t *sched_resp,
+ uint8_t input_buffer[NUMBER_OF_UE_MAX][20000],
+ int n_rnti,
+ int n_users,
+ int transmission_mode,
+ int retrans,
+ int common_flag,
+ int NB_RB,
+ int DLSCH_RB_ALLOC,
+ int TPC,
+ int mcs1,
+ int mcs2,
+ int ndi,
+ int rv,
+ int pa,
+ int *num_common_dci,
+ int *num_ue_spec_dci,
+ int *num_dci) {
+ int k;
+ nfapi_dl_config_request_body_t *dl_req=&sched_resp->DL_req->dl_config_request_body;
+ nfapi_dl_config_request_pdu_t *dl_config_pdu;
+ nfapi_tx_request_body_t *TX_req=&sched_resp->TX_req->tx_request_body;
+ int NB_RB4TBS = common_flag == 0 ? NB_RB : (2+TPC);
+ dl_req->number_dci=0;
+ dl_req->number_pdu=0;
+ TX_req->number_of_pdus=0;
+
+ for(k=0; k<n_users; k++) {
+ switch(transmission_mode) {
+ case 1:
+ case 2:
+ case 7:
+ dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
+ memset((void *) dl_config_pdu, 0,
+ sizeof(nfapi_dl_config_request_pdu_t));
+ dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE;
+ dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu));
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = (common_flag == 0) ? NFAPI_DL_DCI_FORMAT_1 : NFAPI_DL_DCI_FORMAT_1A;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = 4;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_DCI_DL_PDU_REL8_TAG;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = (common_flag == 0) ? n_rnti+k : SI_RNTI;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = (common_flag ==0 ) ? 1: 2; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = 0;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = TPC; // dont adjust power when retransmitting
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = (common_flag == 0) ? ndi : 0;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs1;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = rv;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = (common_flag == 0) ? DLSCH_RB_ALLOC : computeRIV(eNB->frame_parms.N_RB_DL,0,NB_RB);
+ //deactivate second codeword
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_2 = 0;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = 0;
+ dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.cce_idx = 0;
+ dl_req->number_dci++;
+ dl_req->number_pdu++;
+ dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG;
+ AssertFatal(TPC>=0 && TPC<2, "TPC should be 0 or 1\n");
+ if(1){
+ fill_mch_config(
+ dl_req,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ 0,
+ 0xfffd,
+ 0,
+ get_Qm(mcs1),
+ mcs1,
+ 6000, //equal to RS power
+ 0 //mbsfn_area_id
+ );
+
+ fill_tx_req(TX_req,
+ (frame * 10) + subframe,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ 0,
+ input_buffer[0]);
+
+ }else{
+ fill_dlsch_config(dl_req,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ (retrans > 0) ? -1 : 0, /* retransmission, no pdu_index */
+ (common_flag == 0) ? n_rnti : SI_RNTI,
+ 0, // type 0 allocation from 7.1.6 in 36.213
+ 0, // virtual_resource_block_assignment_flag, unused here
+ DLSCH_RB_ALLOC, // resource_block_coding,
+ get_Qm(mcs1),
+ rv, // redundancy version
+ 1, // transport blocks
+ 0, // transport block to codeword swap flag
+ transmission_mode == 1 ? 0 : 1, // transmission_scheme
+ 1, // number of layers
+ 1, // number of subbands
+ // uint8_t codebook_index,
+ 4, // UE category capacity
+ pa, // pa
+ 0, // delta_power_offset for TM5
+ 0, // ngap
+ 0, // nprb
+ transmission_mode,
+ 0, //number of PRBs treated as one subband, not used here
+ 0 // number of beamforming vectors, not used here
+ );
+ fill_tx_req(TX_req,
+ (frame * 10) + subframe,
+ get_TBS_DL(mcs1,NB_RB4TBS),
+ 0,
+ input_buffer[k]);
+ }
+ break;
+
+ case 3:
+ if (common_flag == 0) {
+ if (eNB->frame_parms.nb_antennas_tx == 2) {
+ if (eNB->frame_parms.frame_type == TDD) {
+ } else {
+ }
+ }
+ }
+
+ break;
+
+ case 4:
+ if (common_flag == 0) {
+ if (eNB->frame_parms.nb_antennas_tx == 2) {
+ if (eNB->frame_parms.frame_type == TDD) {
+ } else {
+ }
+ } else if (eNB->frame_parms.nb_antennas_tx == 4) {
+ }
+ } else {
+ }
+
+ break;
+
+ case 5:
+ case 6:
+ break;
+
+ default:
+ printf("Unsupported Transmission Mode %d!!!\n",transmission_mode);
+ exit(-1);
+ break;
+ }
+ }
+
+ *num_dci = dl_req->number_dci;
+ *num_ue_spec_dci = dl_req->number_dci;
+ *num_common_dci = 0;
+}
+
+int n_users = 1;
+int subframe=7;
+int num_common_dci=0,num_ue_spec_dci=0,num_dci=0,num_pdcch_symbols=1;
+uint16_t n_rnti=0x1234;
+
+int abstx=0;
+int Nid_cell=0;
+int N_RB_DL=25;
+int tdd_config=3;
+int dci_flag=0;
+int threequarter_fs=0;
+double snr_step=1,input_snr_step=1, snr_int=30;
+double forgetting_factor=0.0; //in [0,1] 0 means a new channel every time, 1 means keep the same channel
+int test_perf=0;
+int n_frames;
+int n_ch_rlz = 1;
+int rx_sample_offset = 0;
+int xforms=0;
+int dump_table=0;
+int loglvl=OAILOG_WARNING;
+int mcs1=0,mcs2=0,mcs_i=0,dual_stream_UE = 0,awgn_flag=0;
+int two_thread_flag=0;
+int num_rounds = 4;//,fix_rounds=0;
+int perfect_ce = 0;
+int extended_prefix_flag=0;
+int verbose=0, help=0;
+double SNR,snr0=-2.0,snr1,rate = 0;
+int print_perf=0;
+
int main(int argc, char **argv) {
- char c;
- int i,l,l2,aa,aarx,k;
- double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0;
- uint8_t snr1set=0;
- double snr_step=1,input_snr_step=1;
- int **txdata;
- double s_re0[2*30720],s_im0[2*30720],s_re1[2*30720],s_im1[2*30720];
- double r_re0[2*30720],r_im0[2*30720],r_re1[2*30720],r_im1[2*30720];
- double *s_re[2]= {s_re0,s_re1},*s_im[2]= {s_im0,s_im1},*r_re[2]= {r_re0,r_re1},*r_im[2]= {r_im0,r_im1};
- double iqim = 0.0;
- int subframe=1;
- char fname[40];//, vname[40];
- uint8_t transmission_mode = 1,n_tx=1,n_rx=2;
- uint16_t Nid_cell=0;
- FILE *fd;
- int eNB_id = 0;
- unsigned char mcs=0,awgn_flag=0,round;
- int n_frames=1;
- channel_desc_t *eNB2UE;
- uint32_t nsymb,tx_lev,tx_lev_dB;
- uint8_t extended_prefix_flag=1;
+ int k,i,j,aa;
+ int re;
+ int s,Kr,Kr_bytes;
LTE_DL_FRAME_PARMS *frame_parms;
+ double s_re0[30720*2],s_im0[30720*2],r_re0[30720*2],r_im0[30720*2];
+ double s_re1[30720*2],s_im1[30720*2],r_re1[30720*2],r_im1[30720*2];
+ double *s_re[2]= {s_re0,s_re1};
+ double *s_im[2]= {s_im0,s_im1};
+ double *r_re[2]= {r_re0,r_re1};
+ double *r_im[2]= {r_im0,r_im1};
+ uint8_t transmission_mode=1,n_tx_port=1,n_tx_phy=1,n_rx=2;
+ int eNB_id = 0;
+ unsigned char round;
+ unsigned char i_mod = 2;
+ int NB_RB;
+ SCM_t channel_model=Rayleigh1;
+ // unsigned char *input_data,*decoded_output;
+ DCI_ALLOC_t da;
+ DCI_ALLOC_t *dci_alloc = &da;
+ unsigned int coded_bits_per_codeword=0,nsymb; //,tbs=0;
+ unsigned int tx_lev=0,tx_lev_dB=0,trials;
+ unsigned int errs[4],errs2[4],round_trials[4],dci_errors[4];//,num_layers;
+ memset(errs,0,4*sizeof(unsigned int));
+ memset(errs2,0,4*sizeof(unsigned int));
+ memset(round_trials,0,4*sizeof(unsigned int));
+ memset(dci_errors,0,4*sizeof(unsigned int));
+ //int re_allocated;
+ char fname[32],vname[32];
+ FILE *bler_fd;
+ char bler_fname[256];
+ FILE *time_meas_fd;
+ char time_meas_fname[256];
+ // FILE *tikz_fd;
+ // char tikz_fname[256];
+ FILE *input_trch_fd=NULL;
+ unsigned char input_trch_file=0;
+ FILE *input_fd=NULL;
+ unsigned char input_file=0;
+ channel_desc_t *eNB2UE[4];
+ //uint8_t num_pdcch_symbols_2=0;
+ //char stats_buffer[4096];
+ //int len;
+ //int u;
+ int n=0;
+ //int iii;
+ int ch_realization;
+ //int pmi_feedback=0;
int hold_channel=0;
- uint16_t NB_RB=25;
- int tdd_config=3;
- SCM_t channel_model=MBSFN;
- unsigned char *input_buffer;
- unsigned short input_buffer_length;
- unsigned int ret;
- unsigned int trials,errs[4]= {0,0,0,0}; //,round_trials[4]={0,0,0,0};
- uint8_t N_RB_DL=25,osf=1;
- uint32_t perfect_ce = 0;
- lte_frame_type_t frame_type = FDD;
- uint32_t Nsoft = 1827072;
- /*
- #ifdef XFORMS
- FD_lte_phy_scope_ue *form_ue;
+ // void *data;
+ // int ii;
+ // int bler;
+ double blerr[4];
+ short *uncoded_ber_bit=NULL;
+ int osf=1;
+ frame_t frame_type = FDD;
+ FD_lte_phy_scope_ue *form_ue = NULL;
char title[255];
+ int numCCE=0;
+ //int dci_length_bytes=0,dci_length=0;
+ //double channel_bandwidth = 5.0, sampling_rate=7.68;
+ int common_flag=0,TPC=0;
+ double cpu_freq_GHz;
+ // time_stats_t ts;//,sts,usts;
+ int avg_iter,iter_trials;
+ int rballocset=0;
+ int test_passed=0;
+ double effective_rate=0.0;
+ char channel_model_input[10]="I";
+ int TB0_active = 1;
+ // LTE_DL_UE_HARQ_t *dlsch0_ue_harq;
+ // LTE_DL_eNB_HARQ_t *dlsch0_eNB_harq;
+ uint8_t Kmimo;
+ uint8_t ue_category=4;
+ uint32_t Nsoft;
+ int sf;
+ int CCE_table[800];
+ opp_enabled=1; // to enable the time meas
+ FILE *csv_fd=NULL;
+ char csv_fname[FILENAME_MAX];
+ int DLSCH_RB_ALLOC = 0;
+ int dci_received;
+ PHY_VARS_eNB *eNB;
+ RU_t *ru;
+ PHY_VARS_UE *UE=NULL;
+ nfapi_dl_config_request_t DL_req;
+ nfapi_ul_config_request_t UL_req;
+ nfapi_hi_dci0_request_t HI_DCI0_req;
+ nfapi_dl_config_request_pdu_t dl_config_pdu_list[MAX_NUM_DL_PDU];
+ nfapi_tx_request_pdu_t tx_pdu_list[MAX_NUM_TX_REQUEST_PDU];
+ nfapi_tx_request_t TX_req;
+ Sched_Rsp_t sched_resp;
+ int pa=dB0;
+#if defined(__arm__)
+ FILE *proc_fd = NULL;
+ char buf[64];
+ memset(buf,0,sizeof(buf));
+ proc_fd = fopen("/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq", "r");
+
+ if(!proc_fd)
+ printf("cannot open /sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq");
+ else {
+ while(fgets(buf, 63, proc_fd))
+ printf("%s", buf);
+ }
- fl_initialize (&argc, argv, NULL, 0, 0);
- form_ue = create_lte_phy_scope_ue();
- sprintf (title, "LTE DL SCOPE UE");
- fl_show_form (form_ue->lte_phy_scope_ue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title);
- #endif
- */
- cpuf = get_cpu_freq_GHz();
- logInit();
- number_of_cards = 1;
+ fclose(proc_fd);
+ cpu_freq_GHz = ((double)atof(buf))/1e6;
+#else
+ cpu_freq_GHz = get_cpu_freq_GHz();
+#endif
+ printf("Detected cpu_freq %f GHz\n",cpu_freq_GHz);
+ memset((void *)&sched_resp,0,sizeof(sched_resp));
+ sched_resp.DL_req = &DL_req;
+ sched_resp.UL_req = &UL_req;
+ sched_resp.HI_DCI0_req = &HI_DCI0_req;
+ sched_resp.TX_req = &TX_req;
+ memset((void *)&DL_req,0,sizeof(DL_req));
+ memset((void *)&UL_req,0,sizeof(UL_req));
+ memset((void *)&HI_DCI0_req,0,sizeof(HI_DCI0_req));
+ memset((void *)&TX_req,0,sizeof(TX_req));
+ DL_req.dl_config_request_body.dl_config_pdu_list = dl_config_pdu_list;
+ TX_req.tx_request_body.tx_pdu_list = tx_pdu_list;
+ set_parallel_conf("PARALLEL_SINGLE_THREAD");
+ cpuf = cpu_freq_GHz;
+ //signal(SIGSEGV, handler);
+ //signal(SIGABRT, handler);
+ // default parameters
+ n_frames = 1000;
+ snr0 = 0;
+ // num_layers = 1;
+ perfect_ce = 0;
+ static paramdef_t options[] = {
+ { "awgn", "Use AWGN channel and not multipath", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL },
+ { "Abstx", "Turns on calibration mode for abstraction.", PARAMFLAG_BOOL, iptr:&abstx, defintval:0, TYPE_INT, 0 },
+ { "bTDD", "Set the tdd configuration mode",0, iptr:&tdd_config, defintval:3, TYPE_INT, 0 },
+ { "BnbRBs", "The LTE bandwith in RBs (100 is 20MHz)",0, iptr:&N_RB_DL, defintval:25, TYPE_INT, 0 },
+ { "cPdcch", "Number of PDCCH symbols",0, iptr:&num_pdcch_symbols, defintval:1, TYPE_INT, 0 },
+ { "CnidCell", "The cell id ",0, iptr:&Nid_cell, defintval:0, TYPE_INT, 0 },
+ { "dciFlag", "Transmit the DCI and compute its error statistics", PARAMFLAG_BOOL, iptr:&dci_flag, defintval:0, TYPE_INT, 0 },
+ { "Dtdd", "Enable tdd", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL },
+ { "eRounds", "Number of rounds",0, iptr:NULL, defintval:25, TYPE_INT, 0 },
+ { "EsubSampling","three quarters sub-sampling",PARAMFLAG_BOOL, iptr:&threequarter_fs, defintval:0, TYPE_INT, 0 },
+ { "f_snr_step", "step size of SNR, default value is 1.",0, dblptr:&input_snr_step, defdblval:1, TYPE_DOUBLE, 0 },
+ { "Forgetting", "forgetting factor (0 new channel every trial, 1 channel constant)",0, dblptr:&forgetting_factor, defdblval:0.0, TYPE_DOUBLE, 0 },
+ { "input_file", "input IQ data file",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "Input_file_trch", " Input filename for TrCH data (binary)",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "WtwoThreads", "two_thread_flag", PARAMFLAG_BOOL, iptr:&two_thread_flag, defintval:0, TYPE_INT, 0 },
+ { "lMuMimo", "offset_mumimo_llr_drange_fix",0, u8ptr:&offset_mumimo_llr_drange_fix, defintval:0, TYPE_UINT8, 0 },
+ { "mcs1", "The MCS for TB 1", 0, iptr:&mcs1, defintval:0, TYPE_INT, 0 },
+ { "Mcs2", "The MCS for TB 2", 0, iptr:&mcs2, defintval:0, TYPE_INT, 0 },
+ { "Operf", "Set the percenatge of effective rate to testbench the modem performance (typically 30 and 70, range 1-100)",0, iptr:&test_perf, defintval:0, TYPE_INT, 0 },
+ { "tmcs_i", "MCS of interfering UE",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "nb_frame", "number of frame in a test",0, iptr:&n_frames, defintval:1, TYPE_INT, 0 },
+ { "offsetRxSample", "Sample offset for receiver", 0, iptr:&rx_sample_offset, defintval:0, TYPE_INT, 0 },
+ { "rballocset", "ressource block allocation (see section 7.1.6.3 in 36.213)",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "snr", "Starting SNR, runs from SNR to SNR+%.1fdB in steps of %.1fdB. If n_frames is 1 then just SNR is simulated and MATLAB/OCTAVE output is generated", dblptr:&snr0, defdblval:-2.0, TYPE_DOUBLE, 0 },
+ { "wsnrInterrupt", "snr int ?", 0, dblptr:&snr_int, defdblval:30, TYPE_DOUBLE, 0 },
+ { "N_ch_rlzN0", "Determines the number of Channel Realizations in Abstraction mode. Default value is 1",0, iptr:&n_ch_rlz, defintval:1, TYPE_INT, 0 },
+ { "prefix_extended","Enable extended prefix", PARAMFLAG_BOOL, iptr:&extended_prefix_flag, defintval:0, TYPE_INT, 0 },
+ { "RNumRound", "Number of HARQ rounds (fixed)",0, iptr:&num_rounds, defintval:4, TYPE_INT, 0 },
+ { "Subframe", "subframe ",0, iptr:&subframe, defintval:7, TYPE_INT, 0 },
+ { "Trnti", "rnti",0, u16ptr:&n_rnti, defuintval:0x1234, TYPE_UINT16, 0 },
+ { "vi_mod", "i_mod",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "Qparallel", "Enable parallel execution",0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0 },
+ { "Performance", "Display CPU perfomance of each L1 piece", PARAMFLAG_BOOL, iptr:&print_perf, defintval:0, TYPE_INT, 0 },
+ { "q_tx_port", "Number of TX antennas ports used in eNB",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "uEdual", "Enables the Interference Aware Receiver for TM5 (default is normal receiver)",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ { "xTransmission","Transmission mode (1,2,6,7 for the moment)",0, iptr:NULL, defintval:25, TYPE_INT, 0 },
+ { "yn_tx_phy","Number of TX antennas used in eNB",0, iptr:NULL, defintval:25, TYPE_INT, 0 },
+ { "XForms", "Display the soft scope", PARAMFLAG_BOOL, iptr:&xforms, defintval:0, TYPE_INT, 0 },
+ { "Yperfect_ce","Perfect CE", PARAMFLAG_BOOL, iptr:&perfect_ce, defintval:0, TYPE_INT, 0 },
+ { "Zdump", "dump table",PARAMFLAG_BOOL, iptr:&dump_table, defintval:0, TYPE_INT, 0 },
+ { "Loglvl", "log level",0, iptr:&loglvl, defintval:OAILOG_DEBUG, TYPE_INT, 0 },
+ { "zn_rx", "Number of RX antennas used in UE",0, iptr:NULL, defintval:2, TYPE_INT, 0 },
+ { "gchannel", "[A:M] Use 3GPP 25.814 SCM-A/B/C/D('A','B','C','D') or 36-101 EPA('E'), EVA ('F'),ETU('G') models (ignores delay spread and Ricean factor), Rayghleigh8 ('H'), Rayleigh1('I'), Rayleigh1_corr('J'), Rayleigh1_anticorr ('K'), Rice8('L'), Rice1('M')",0, strptr:NULL, defstrval:NULL, TYPE_STRING, 0 },
+ { "verbose", "display debug text", PARAMFLAG_BOOL, iptr:&verbose, defintval:0, TYPE_INT, 0 },
+ { "mmse", "Use MMSE whitening", PARAMFLAG_BOOL, strptr:NULL, defintval:0, TYPE_INT, 0, NULL, NULL },
+ { "help", "display help and exit", PARAMFLAG_BOOL, iptr:&help, defintval:0, TYPE_INT, 0 },
+ { "", "",0, iptr:NULL, defintval:0, TYPE_INT, 0 },
+ };
+ struct option *long_options = parse_oai_options(options);
+ int option_index;
+ int res;
+
+ while ((res=getopt_long_only(argc, argv, "", long_options, &option_index)) == 0) {
+ if (options[option_index].voidptr != NULL ) {
+ if (long_options[option_index].has_arg==no_argument)
+ *(bool *)options[option_index].iptr=1;
+ else switch (options[option_index].type) {
+ case TYPE_INT:
+ *(int *)options[option_index].iptr=atoi(optarg);
+ break;
+
+ case TYPE_DOUBLE:
+ *(double *)options[option_index].dblptr=atof(optarg);
+ break;
+
+ case TYPE_UINT8:
+ *(uint8_t *)options[option_index].dblptr=atoi(optarg);
+ break;
+
+ case TYPE_UINT16:
+ *(uint16_t *)options[option_index].dblptr=atoi(optarg);
+ break;
+
+ default:
+ printf("not decoded type.\n");
+ exit(1);
+ }
+
+ continue;
+ }
- while ((c = getopt (argc, argv, "ahA:Cp:n:s:S:t:x:y:z:N:F:R:O:dm:i:Y")) != -1) {
- switch (c) {
+ switch (long_options[option_index].name[0]) {
case 'a':
- awgn_flag=1;
+ awgn_flag = 1;
+ channel_model = AWGN;
break;
- case 'd':
- frame_type = 0;
+ case 'D':
+ frame_type=TDD;
break;
- case 'n':
- n_frames = atoi(optarg);
+ case 'e':
+ num_rounds=1;
+ common_flag = 1;
+ TPC = atoi(optarg);
break;
- case 'm':
- mcs=atoi(optarg);
+ case 'i':
+ input_fd = fopen(optarg,"r");
+ input_file=1;
+ dci_flag = 1;
break;
- case 's':
- snr0 = atof(optarg);
- msg("Setting SNR0 to %f\n",snr0);
+ case 'I':
+ input_trch_fd = fopen(optarg,"r");
+ input_trch_file=1;
break;
- case 'i':
- input_snr_step = atof(optarg);
+ case 't':
+ mcs_i = atoi(optarg);
+ i_mod = get_Qm(mcs_i);
break;
- case 'S':
- snr1 = atof(optarg);
- snr1set=1;
- msg("Setting SNR1 to %f\n",snr1);
+ case 'r':
+ DLSCH_RB_ALLOC = atoi(optarg);
+ rballocset = 1;
break;
- case 'p': // subframe no;
- subframe=atoi(optarg);
+ case 'g':
+ strncpy(channel_model_input,optarg,9);
+ struct tmp {
+ char opt;
+ int m;
+ int M;
+ }
+ tmp[]= {
+ {'A',SCM_A,2},
+ {'B',SCM_B,3},
+ {'C',SCM_C,4},
+ {'D',SCM_D,5},
+ {'E',EPA,6},
+ {'F',EVA,6},
+ {'G',ETU,8},
+ {'H',Rayleigh8,9},
+ {'I',Rayleigh1,10},
+ {'J',Rayleigh1_corr,11},
+ {'K',Rayleigh1_anticorr,12},
+ {'L',Rice8,13},
+ {'M',Rice1,14},
+ {'N',AWGN,1},
+ {0,0,0}
+ };
+ struct tmp *ptr;
+
+ for (ptr=tmp; ptr->opt!=0; ptr++)
+ if ( ptr->opt == optarg[0] ) {
+ channel_model=ptr->m;
+ break;
+ }
+
+ AssertFatal(ptr->opt != 0, "Unsupported channel model: %s !\n", optarg );
break;
- case 'z':
- n_rx=atoi(optarg);
+ case 'u':
+ dual_stream_UE=1;
- if ((n_rx==0) || (n_rx>2)) {
- msg("Unsupported number of rx antennas %d\n",n_rx);
+ if (UE != NULL)
+ UE->use_ia_receiver = 1;
+ else {
+ printf("UE is NULL\n");
+ exit(-1);
+ }
+
+ if ((n_tx_port!=2) || (transmission_mode!=5)) {
+ printf("IA receiver only supported for TM5!");
exit(-1);
}
break;
- case 'N':
- Nid_cell = atoi(optarg);
+ case 'v':
+ i_mod = atoi(optarg);
+
+ if (i_mod!=2 && i_mod!=4 && i_mod!=6) {
+ printf("Wrong i_mod %d, should be 2,4 or 6\n",i_mod);
+ exit(-1);
+ }
+
break;
- case 'R':
- N_RB_DL = atoi(optarg);
+ case 'q':
+ n_tx_port=atoi(optarg);
- if ((N_RB_DL!=6) && (N_RB_DL!=25) && (N_RB_DL!=50) && (N_RB_DL!=100)) {
- printf("Unsupported Bandwidth %d\n",N_RB_DL);
+ if ((n_tx_port==0) || ((n_tx_port>2))) {
+ printf("Unsupported number of cell specific antennas ports %d\n",n_tx_port);
exit(-1);
}
break;
- case 'O':
- osf = atoi(optarg);
+ case 'x':
+ transmission_mode=atoi(optarg);
+
+ if ((transmission_mode!=1) &&
+ (transmission_mode!=2) &&
+ (transmission_mode!=3) &&
+ (transmission_mode!=4) &&
+ (transmission_mode!=5) &&
+ (transmission_mode!=6) &&
+ (transmission_mode!=7)) {
+ printf("Unsupported transmission mode %d\n",transmission_mode);
+ exit(-1);
+ }
+
+ if (transmission_mode>1 && transmission_mode<7) {
+ n_tx_port = 2;
+ }
+
break;
- case 'Y':
- perfect_ce = 1;
+ case 'y':
+ n_tx_phy=atoi(optarg);
+
+ if (n_tx_phy < n_tx_port) {
+ printf("n_tx_phy mush not be smaller than n_tx_port");
+ exit(-1);
+ }
+
+ if ((transmission_mode>1 && transmission_mode<7) && n_tx_port<2) {
+ printf("n_tx_port must be >1 for transmission_mode %d\n",transmission_mode);
+ exit(-1);
+ }
+
+ if (transmission_mode==7 && (n_tx_phy!=1 && n_tx_phy!=2 && n_tx_phy!=4 && n_tx_phy!=8 && n_tx_phy!=16 && n_tx_phy!=64 && n_tx_phy!=128)) {
+ printf("Physical number of antennas not supported for TM7.\n");
+ exit(-1);
+ }
+
+ break;
+
+ case 'z':
+ n_rx=atoi(optarg);
+
+ if ((n_rx==0) || (n_rx>2)) {
+ printf("Unsupported number of rx antennas %d\n",n_rx);
+ exit(-1);
+ }
+
+ break;
+
+ case 'Q':
+ set_parallel_conf(optarg);
break;
default:
- case 'h':
- printf("%s -h(elp) -p(subframe) -N cell_id -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -i snr increment -z RXant \n",argv[0]);
- printf("-h This message\n");
- printf("-a Use AWGN Channel\n");
- printf("-p Use extended prefix mode\n");
- printf("-d Use TDD\n");
- printf("-n Number of frames to simulate\n");
- printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n");
- printf("-S Ending SNR, runs from SNR0 to SNR1\n");
- printf("-t Delay spread for multipath channel\n");
- printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n");
- printf("-x Transmission mode (1,2,6 for the moment)\n");
- printf("-y Number of TX antennas used in eNB\n");
- printf("-z Number of RX antennas used in UE\n");
- printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n");
- printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n");
- printf("-N Nid_cell\n");
- printf("-R N_RB_DL\n");
- printf("-O oversampling factor (1,2,4,8,16)\n");
- printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n");
- printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
- printf("-f Output filename (.txt format) for Pe/SNR results\n");
- printf("-F Input filename (.txt format) for RX conformance testing\n");
- exit (-1);
+ printf("Wrong option: %s\n",long_options[option_index].name);
+ exit(1);
break;
}
}
- if (awgn_flag == 1)
- channel_model = AWGN;
+ if ( res != -1 ) {
+ printf("A wrong option has been found\n");
+ exit(1);
+ }
- // check that subframe is legal for eMBMS
+ if (help || verbose )
+ display_options_values(options, true);
- if ((subframe == 0) || (subframe == 5) || // TDD and FDD SFn 0,5;
- ((frame_type == FDD) && ((subframe == 4) || (subframe == 9))) || // FDD SFn 4,9;
- ((frame_type == TDD ) && ((subframe<3) || (subframe==6)))) { // TDD SFn 1,2,6;
- printf("Illegal subframe %d for eMBMS transmission (frame_type %d)\n",subframe,frame_type);
- exit(-1);
+ if (help)
+ exit(0);
+ if (thread_struct.parallel_conf != PARALLEL_SINGLE_THREAD)
+ set_worker_conf("WORKER_ENABLE");
+
+ if (transmission_mode>1) pa=dBm3;
+
+ printf("dlsim: tmode %d, pa %d\n",transmission_mode,pa);
+ AssertFatal(load_configmodule(argc,argv, CONFIG_ENABLECMDLINEONLY) != NULL,
+ "cannot load configuration module, exiting\n");
+ logInit();
+ set_glog_onlinelog(true);
+ // enable these lines if you need debug info
+ set_glog(loglvl);
+ SET_LOG_DEBUG(UE_TIMING);
+ // moreover you need to init itti with the following line
+ // however itti will catch all signals, so ctrl-c won't work anymore
+ // alternatively you can disable ITTI completely in CMakeLists.txt
+ //itti_init(TASK_MAX, THREAD_MAX, MESSAGES_ID_MAX, tasks_info, messages_info, messages_definition_xml, NULL);
+
+ if (common_flag == 0) {
+ switch (N_RB_DL) {
+ case 6:
+ if (rballocset==0) DLSCH_RB_ALLOC = 0x3f;
+
+ num_pdcch_symbols = 3;
+ break;
+
+ case 25:
+ if (rballocset==0) DLSCH_RB_ALLOC = 0x1fff;
+
+ break;
+
+ case 50:
+ if (rballocset==0) DLSCH_RB_ALLOC = 0x1ffff;
+
+ break;
+
+ case 100:
+ if (rballocset==0) DLSCH_RB_ALLOC = 0x1ffffff;
+
+ break;
+ }
+
+ NB_RB = conv_nprb(0,DLSCH_RB_ALLOC,N_RB_DL);
+ } else {
+ if (rballocset==0) NB_RB = 8;
+ else NB_RB = DLSCH_RB_ALLOC;
+
+ AssertFatal(NB_RB <= N_RB_DL,"illegal NB_RB %d\n",NB_RB);
}
- if (transmission_mode==2)
- n_tx=2;
+ if (xforms==1) {
+ fl_initialize (&argc, argv, NULL, 0, 0);
+ form_ue = create_lte_phy_scope_ue();
+ sprintf (title, "LTE PHY SCOPE eNB");
+ fl_show_form (form_ue->lte_phy_scope_ue, FL_PLACE_HOTSPOT, FL_FULLBORDER, title);
+
+ if (!dual_stream_UE==0) {
+ if (UE) {
+ UE->use_ia_receiver = 1;
+ fl_set_button(form_ue->button_0,1);
+ fl_set_object_label(form_ue->button_0, "IA Receiver ON");
+ fl_set_object_color(form_ue->button_0, FL_GREEN, FL_GREEN);
+ } else {
+ printf("UE is NULL\n");
+ exit(-1);
+ }
+ }
+ }
+
+ if (transmission_mode==5) {
+ n_users = 2;
+ printf("dual_stream_UE=%d\n", dual_stream_UE);
+ }
- lte_param_init(n_tx,
- n_tx,
+ RC.nb_L1_inst = 1;
+ RC.nb_RU = 1;
+ lte_param_init(&eNB,&UE,&ru,
+ n_tx_port,
+ n_tx_phy,
+ 1,
n_rx,
transmission_mode,
extended_prefix_flag,
@@ -224,281 +1068,1251 @@ int main(int argc, char **argv) {
Nid_cell,
tdd_config,
N_RB_DL,
- 0,
+ pa,
+ threequarter_fs,
osf,
perfect_ce);
+ RC.eNB = (PHY_VARS_eNB ** *)malloc(sizeof(PHY_VARS_eNB **));
+ RC.eNB[0] = (PHY_VARS_eNB **)malloc(sizeof(PHY_VARS_eNB *));
+ RC.ru = (RU_t **)malloc(sizeof(RC.ru));
+ RC.eNB[0][0] = eNB;
+ RC.ru[0] = ru;
+ printf("lte_param_init done\n");
+
+ if ((transmission_mode==1) || (transmission_mode==7)) {
+ for (aa=0; aa<ru->nb_tx; aa++)
+ for (re=0; re<ru->frame_parms.ofdm_symbol_size; re++)
+ ru->beam_weights[0][0][aa][re] = 0x00007fff/eNB->frame_parms.nb_antennas_tx;
+ }
+
+ if (transmission_mode<7)
+ ru->do_precoding=0;
+ else
+ ru->do_precoding=1;
- if (snr1set==0) {
- if (n_frames==1)
- snr1 = snr0+.1;
- else
- snr1 = snr0+5.0;
+ eNB->mac_enabled=1;
+
+
+#ifdef ENABLE_MBMS_SIM
+ //eNB->pbch_configured=1;
+ eNB_MAC_INST ** mac;
+ mac = malloc16(1 * sizeof(eNB_MAC_INST *));
+ for (int ii = 0;ii < 1; ii++) {
+ mac[ii] = malloc16(sizeof(eNB_MAC_INST));
+ bzero(mac[ii], sizeof(eNB_MAC_INST));
+ }
+ RC.mac = mac;
+ COMMON_channels_t *cc = &RC.mac[0]->common_channels[0];
+ cc->MCH_pdu.mcs = 9;
+ cc->MCH_pdu.Pdu_size = get_TBS_DL(cc->MCH_pdu.mcs,N_RB_DL);
+ printf("MCH_pdu.Pdu_size %d\n",cc->MCH_pdu.Pdu_size);
+ cc->MCH_pdu.sync_area =0;
+ for(int ii=0; ii < cc->MCH_pdu.Pdu_size; ii++)
+ cc->MCH_pdu.payload[ii] = (char)(taus() & 0xff);
+ eNB->frame_parms.Nid_cell_mbsfn=0;
+#endif
+
+
+ if(get_thread_worker_conf() == WORKER_ENABLE) {
+ extern void init_td_thread(PHY_VARS_eNB *);
+ extern void init_te_thread(PHY_VARS_eNB *);
+ init_td_thread(eNB);
+ init_te_thread(eNB);
}
+ // callback functions required for phy_procedures_tx
+ // eNB_id_i = UE->n_connected_eNB;
+ printf("Setting mcs1 = %d\n",mcs1);
+ printf("Setting mcs2 = %d\n",mcs2);
+ printf("NPRB = %d\n",NB_RB);
+ printf("n_frames = %d\n",n_frames);
+ printf("Transmission mode %d with %dx%d antenna configuration, Extended Prefix %d\n",transmission_mode,n_tx_phy,n_rx,extended_prefix_flag);
+ snr1 = snr0+snr_int;
printf("SNR0 %f, SNR1 %f\n",snr0,snr1);
+ uint8_t input_buffer[NUMBER_OF_UE_MAX][20000];
+
+ for (i=0; i<n_users; i++)
+ for (j=0; j<20000; j++) input_buffer[i][j] = (uint8_t)((taus())&255);
+
frame_parms = &eNB->frame_parms;
+ nsymb = (eNB->frame_parms.Ncp == 0) ? 14 : 12;
+ printf("Channel Model= (%s,%d)\n",channel_model_input, channel_model);
+ printf("SCM-A=%d, SCM-B=%d, SCM-C=%d, SCM-D=%d, EPA=%d, EVA=%d, ETU=%d, Rayleigh8=%d, Rayleigh1=%d, Rayleigh1_corr=%d, Rayleigh1_anticorr=%d, Rice1=%d, Rice8=%d\n",
+ SCM_A, SCM_B, SCM_C, SCM_D, EPA, EVA, ETU, Rayleigh8, Rayleigh1, Rayleigh1_corr, Rayleigh1_anticorr, Rice1, Rice8);
- if (awgn_flag == 0)
- sprintf(fname,"embms_%d_%d.m",mcs,N_RB_DL);
+ if(transmission_mode==5)
+ sprintf(bler_fname,"bler_tx%d_chan%d_nrx%d_mcs%d_mcsi%d_u%d_imod%d.csv",transmission_mode,channel_model,n_rx,mcs1,mcs_i,dual_stream_UE,i_mod);
else
- sprintf(fname,"embms_awgn_%d_%d.m",mcs,N_RB_DL);
+ sprintf(bler_fname,"bler_tx%d_chan%d_nrx%d_mcs%d.csv",transmission_mode,channel_model,n_rx,mcs1);
+
+ bler_fd = fopen(bler_fname,"w");
- if (!(fd = fopen(fname,"w"))) {
- printf("Cannot open %s, check permissions\n",fname);
+ if (bler_fd==NULL) {
+ fprintf(stderr,"Cannot create file %s!\n",bler_fname);
exit(-1);
}
- if (awgn_flag==0)
- fprintf(fd,"SNR_%d_%d=[];errs_mch_%d_%d=[];mch_trials_%d_%d=[];\n",
- mcs,N_RB_DL,
- mcs,N_RB_DL,
- mcs,N_RB_DL);
- else
- fprintf(fd,"SNR_awgn_%d_%d=[];errs_mch_awgn_%d_%d=[];mch_trials_awgn_%d_%d=[];\n",
- mcs,N_RB_DL,
- mcs,N_RB_DL,
- mcs,N_RB_DL);
-
- fflush(fd);
- txdata = eNB->common_vars.txdata[0];
- nsymb = 12;
- printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d, Symbols per subframe %d, AWGN %d\n",NUMBER_OF_OFDM_CARRIERS,
- frame_parms->Ncp,frame_parms->samples_per_tti,nsymb,awgn_flag);
- eNB2UE = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx,
- UE->frame_parms.nb_antennas_rx,
- channel_model,
- N_RB2sampling_rate(eNB->frame_parms.N_RB_DL),
- N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL),
- 0,
- 0,
- 0);
- // Create transport channel structures for 2 transport blocks (MIMO)
- eNB->dlsch_MCH = new_eNB_dlsch(1,8,Nsoft,N_RB_DL,0,&eNB->frame_parms);
-
- if (!eNB->dlsch_MCH) {
- printf("Can't get eNB dlsch structures\n");
- exit(-1);
+ fprintf(bler_fd,"SNR; MCS; TBS; rate; err0; trials0; err1; trials1; err2; trials2; err3; trials3; dci_err\n");
+
+ if (test_perf != 0) {
+ char hostname[1024];
+ hostname[1023] = '\0';
+ gethostname(hostname, 1023);
+ printf("Hostname: %s\n", hostname);
+ //char dirname[FILENAME_MAX];
+ //sprintf(dirname, "%s/SIMU/USER/pre-ci-logs-%s", getenv("OPENAIR_TARGETS"),hostname );
+ sprintf(time_meas_fname,"time_meas_prb%d_mcs%d_anttx%d_antrx%d_pdcch%d_channel%s_tx%d.csv",
+ N_RB_DL,mcs1,n_tx_phy,n_rx,num_pdcch_symbols,channel_model_input,transmission_mode);
+ //mkdir(dirname,0777);
+ time_meas_fd = fopen(time_meas_fname,"w");
+
+ if (time_meas_fd==NULL) {
+ fprintf(stderr,"Cannot create file %s!\n",time_meas_fname);
+ exit(-1);
+ }
}
- UE->dlsch_MCH[0] = new_ue_dlsch(1,8,Nsoft,MAX_TURBO_ITERATIONS_MBSFN,N_RB_DL,0);
- eNB->frame_parms.num_MBSFN_config = 1;
- eNB->frame_parms.MBSFN_config[0].radioframeAllocationPeriod = 0;
- eNB->frame_parms.MBSFN_config[0].radioframeAllocationOffset = 0;
- eNB->frame_parms.MBSFN_config[0].fourFrames_flag = 0;
- eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xff; // activate all possible subframes
- UE->frame_parms.num_MBSFN_config = 1;
- UE->frame_parms.MBSFN_config[0].radioframeAllocationPeriod = 0;
- UE->frame_parms.MBSFN_config[0].radioframeAllocationOffset = 0;
- UE->frame_parms.MBSFN_config[0].fourFrames_flag = 0;
- UE->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xff; // activate all possible subframes
- fill_eNB_dlsch_MCH(eNB,mcs,1,0);
- fill_UE_dlsch_MCH(UE,mcs,1,0,0);
-
- if (is_pmch_subframe(0,subframe,&eNB->frame_parms)==0) {
- printf("eNB is not configured for MBSFN in subframe %d\n",subframe);
- exit(-1);
- } else if (is_pmch_subframe(0,subframe,&UE->frame_parms)==0) {
- printf("UE is not configured for MBSFN in subframe %d\n",subframe);
- exit(-1);
+ if(abstx) {
+ // CSV file
+ sprintf(csv_fname,"dataout_tx%d_u2%d_mcs%d_chan%d_nsimus%d_R%d.m",transmission_mode,dual_stream_UE,mcs1,channel_model,n_frames,num_rounds);
+ csv_fd = fopen(csv_fname,"w");
+
+ if (csv_fd==NULL) {
+ fprintf(stderr,"Cannot create file %s!\n",csv_fname);
+ exit(-1);
+ }
+
+ fprintf(csv_fd,"data_all%d=[",mcs1);
}
- input_buffer_length = eNB->dlsch_MCH->harq_processes[0]->TBS/8;
- input_buffer = (unsigned char *)malloc(input_buffer_length+4);
- memset(input_buffer,0,input_buffer_length+4);
+ /*
+ //sprintf(tikz_fname, "second_bler_tx%d_u2=%d_mcs%d_chan%d_nsimus%d.tex",transmission_mode,dual_stream_UE,mcs,channel_model,n_frames);
+ sprintf(tikz_fname, "second_bler_tx%d_u2%d_mcs%d_chan%d_nsimus%d",transmission_mode,dual_stream_UE,mcs,channel_model,n_frames);
+ tikz_fd = fopen(tikz_fname,"w");
+ //fprintf(tikz_fd,"\\addplot[color=red, mark=o] plot coordinates {");
+ switch (mcs)
+ {
+ case 0:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=star] plot coordinates {");
+ break;
+ case 1:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=star] plot coordinates {");
+ break;
+ case 2:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=star] plot coordinates {");
+ break;
+ case 3:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=star] plot coordinates {");
+ break;
+ case 4:
+ fprintf(tikz_fd,"\\addplot[color=black, mark=star] plot coordinates {");
+ break;
+ case 5:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=o] plot coordinates {");
+ break;
+ case 6:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=o] plot coordinates {");
+ break;
+ case 7:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=o] plot coordinates {");
+ break;
+ case 8:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=o] plot coordinates {");
+ break;
+ case 9:
+ fprintf(tikz_fd,"\\addplot[color=black, mark=o] plot coordinates {");
+ break;
+ case 10:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=square] plot coordinates {");
+ break;
+ case 11:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=square] plot coordinates {");
+ break;
+ case 12:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=square] plot coordinates {");
+ break;
+ case 13:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=square] plot coordinates {");
+ break;
+ case 14:
+ fprintf(tikz_fd,"\\addplot[color=black, mark=square] plot coordinates {");
+ break;
+ case 15:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=diamond] plot coordinates {");
+ break;
+ case 16:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=diamond] plot coordinates {");
+ break;
+ case 17:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=diamond] plot coordinates {");
+ break;
+ case 18:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=diamond] plot coordinates {");
+ break;
+ case 19:
+ fprintf(tikz_fd,"\\addplot[color=black, mark=diamond] plot coordinates {");
+ break;
+ case 20:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=x] plot coordinates {");
+ break;
+ case 21:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=x] plot coordinates {");
+ break;
+ case 22:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=x] plot coordinates {");
+ break;
+ case 23:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=x] plot coordinates {");
+ break;
+ case 24:
+ fprintf(tikz_fd,"\\addplot[color=black, mark=x] plot coordinates {");
+ break;
+ case 25:
+ fprintf(tikz_fd,"\\addplot[color=blue, mark=x] plot coordinates {");
+ break;
+ case 26:
+ fprintf(tikz_fd,"\\addplot[color=red, mark=+] plot coordinates {");
+ break;
+ case 27:
+ fprintf(tikz_fd,"\\addplot[color=green, mark=+] plot coordinates {");
+ break;
+ case 28:
+ fprintf(tikz_fd,"\\addplot[color=yellow, mark=+] plot coordinates {");
+ break;
+ }
+ */
+ UE->pdcch_vars[UE->current_thread_id[subframe]][0]->crnti = n_rnti;
+ UE->n_connected_eNB = 1;
+ printf("Allocating %dx%d eNB->UE channel descriptor\n",eNB->frame_parms.nb_antennas_tx,UE->frame_parms.nb_antennas_rx);
+ eNB2UE[0] = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx,
+ UE->frame_parms.nb_antennas_rx,
+ channel_model,
+ N_RB2sampling_rate(eNB->frame_parms.N_RB_DL),
+ N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL),
+ forgetting_factor,
+ rx_sample_offset,
+ 0);
+ reset_meas(&eNB2UE[0]->random_channel);
+ reset_meas(&eNB2UE[0]->interp_time);
+
+ if(num_rounds>1) {
+ for(n=1; n<4; n++) {
+ eNB2UE[n] = new_channel_desc_scm(eNB->frame_parms.nb_antennas_tx,
+ UE->frame_parms.nb_antennas_rx,
+ channel_model,
+ N_RB2sampling_rate(eNB->frame_parms.N_RB_DL),
+ N_RB2channel_bandwidth(eNB->frame_parms.N_RB_DL),
+ forgetting_factor,
+ rx_sample_offset,
+ 0);
+ reset_meas(&eNB2UE[n]->random_channel);
+ reset_meas(&eNB2UE[n]->interp_time);
+ }
+ }
- for (i=0; i<input_buffer_length+4; i++) {
- input_buffer[i]= (unsigned char)(taus()&0xff);
+ if (eNB2UE[0]==NULL) {
+ printf("Problem generating channel model. Exiting.\n");
+ exit(-1);
}
- snr_step = input_snr_step;
+ if ((transmission_mode == 3) || (transmission_mode==4))
+ Kmimo=2;
+ else
+ Kmimo=1;
- for (SNR=snr0; SNR<snr1; SNR+=snr_step) {
- UE->proc.proc_rxtx[0].frame_tx=0;
- eNB->proc.proc_rxtx[0].frame_tx=0;
- eNB->proc.proc_rxtx[0].subframe_tx=subframe;
- errs[0]=0;
- errs[1]=0;
- errs[2]=0;
- errs[3]=0;
- /*
- round_trials[0] = 0;
- round_trials[1] = 0;
- round_trials[2] = 0;
- round_trials[3] = 0;*/
- printf("********************** SNR %f (step %f)\n",SNR,snr_step);
-
- for (trials = 0; trials<n_frames; trials++) {
- // printf("Trial %d\n",trials);
- fflush(stdout);
- round=0;
- //if (trials%100==0)
- //eNB2UE[0]->first_run = 1;
- eNB2UE->first_run = 1;
- memset(&eNB->common_vars.txdataF[0][0][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t));
- generate_mch(eNB,&eNB->proc.proc_rxtx[0],input_buffer);
- PHY_ofdm_mod(eNB->common_vars.txdataF[0][0], // input,
- txdata[0], // output
- frame_parms->ofdm_symbol_size,
- LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*nsymb, // number of symbols
- frame_parms->nb_prefix_samples, // number of prefix samples
- CYCLIC_PREFIX);
+ switch (ue_category) {
+ case 1:
+ Nsoft = 250368;
+ break;
- if (n_frames==1) {
- LOG_M("txsigF0.m","txsF0", &eNB->common_vars.txdataF[0][0][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],
- nsymb*eNB->frame_parms.ofdm_symbol_size,1,1);
- //if (eNB->frame_parms.nb_antennas_tx>1)
- //LOG_M("txsigF1.m","txsF1", &eNB->lte_eNB_common_vars.txdataF[eNB_id][1][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1);
- }
+ case 2:
+ case 3:
+ Nsoft = 1237248;
+ break;
- tx_lev = 0;
+ case 4:
+ Nsoft = 1827072;
+ break;
- for (aa=0; aa<eNB->frame_parms.nb_antennas_tx; aa++) {
- tx_lev += signal_energy(&eNB->common_vars.txdata[eNB_id][aa]
- [subframe*eNB->frame_parms.samples_per_tti],
- eNB->frame_parms.samples_per_tti);
- }
+ default:
+ printf("Unsupported UE category %d\n",ue_category);
+ exit(-1);
+ break;
+ }
- tx_lev_dB = (unsigned int) dB_fixed(tx_lev);
+ for (k=0; k<NUMBER_OF_UE_MAX; k++) {
+ // Create transport channel structures for 2 transport blocks (MIMO)
+ for (i=0; i<2; i++) {
+ eNB->dlsch[k][i] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0,&eNB->frame_parms);
- if (n_frames==1) {
- printf("tx_lev = %d (%d dB)\n",tx_lev,tx_lev_dB);
- // LOG_M("txsig0.m","txs0", &eNB->common_vars.txdata[0][0][subframe* eNB->frame_parms.samples_per_tti],
- // eNB->frame_parms.samples_per_tti,1,1);
+ if (!eNB->dlsch[k][i]) {
+ printf("Can't get eNB dlsch structures\n");
+ exit(-1);
}
- for (i=0; i<2*frame_parms->samples_per_tti; i++) {
- for (aa=0; aa<eNB->frame_parms.nb_antennas_tx; aa++) {
- s_re[aa][i] = ((double)(((short *)eNB->common_vars.txdata[0][aa]))[(2*subframe*UE->frame_parms.samples_per_tti) + (i<<1)]);
- s_im[aa][i] = ((double)(((short *)eNB->common_vars.txdata[0][aa]))[(2*subframe*UE->frame_parms.samples_per_tti) +(i<<1)+1]);
- }
+ eNB->dlsch[k][i]->rnti = n_rnti+k;
+ }
+ }
+
+#ifdef ENABLE_MBMS_SIM
+ eNB->dlsch_MCH = new_eNB_dlsch(1,8,Nsoft,N_RB_DL, 0, &eNB->frame_parms);
+#endif
+
+
+ /* allocate memory for both subframes (only one is really used
+ * but there is now "copy_harq_proc_struct" which needs both
+ * to be valid)
+ * TODO: refine this somehow (necessary?)
+ */
+ for (sf = 0; sf < 2; sf++) {
+ for (i=0; i<2; i++) {
+ UE->dlsch[sf][0][i] = new_ue_dlsch(Kmimo,8,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0);
+
+ if (!UE->dlsch[sf][0][i]) {
+ printf("Can't get ue dlsch structures\n");
+ exit(-1);
}
- //Multipath channel
- multipath_channel(eNB2UE,s_re,s_im,r_re,r_im,
- 2*frame_parms->samples_per_tti,hold_channel);
- //AWGN
- sigma2_dB = 10*log10((double)tx_lev) +10*log10((double)eNB->frame_parms.ofdm_symbol_size/(NB_RB*12)) - SNR;
- sigma2 = pow(10,sigma2_dB/10);
-
- if (n_frames==1)
- printf("Sigma2 %f (sigma2_dB %f)\n",sigma2,sigma2_dB);
-
- for (i=0; i<2*frame_parms->samples_per_tti; i++) {
- for (aa=0; aa<eNB->frame_parms.nb_antennas_rx; aa++) {
- //printf("s_re[0][%d]=> %f , r_re[0][%d]=> %f\n",i,s_re[aa][i],i,r_re[aa][i]);
- ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i] =
- (short) (r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0));
- ((short *) UE->common_vars.rxdata[aa])[(2*subframe*UE->frame_parms.samples_per_tti)+2*i+1] =
- (short) (r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0));
- }
+ UE->dlsch[sf][0][i]->rnti = n_rnti;
+ }
+ }
+
+#ifdef ENABLE_MBMS_SIM
+ UE->dlsch_MCH[0] = new_ue_dlsch(1,8,Nsoft,MAX_TURBO_ITERATIONS_MBSFN,N_RB_DL,0);
+ UE->dlsch_MCH[0]->active = 1;
+ UE->dlsch_MCH[0]->harq_processes[0]->mcs = mcs1;
+#endif
+
+ UE->dlsch_SI[0] = new_ue_dlsch(1,1,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0);
+ UE->dlsch_ra[0] = new_ue_dlsch(1,1,Nsoft,MAX_TURBO_ITERATIONS,N_RB_DL,0);
+ UE->ulsch[0] = new_ue_ulsch(N_RB_DL,0);
+ // structure for SIC at UE
+ UE->dlsch_eNB[0] = new_eNB_dlsch(Kmimo,8,Nsoft,N_RB_DL,0,&eNB->frame_parms);
+
+ if (DLSCH_alloc_pdu2_1E[0].tpmi == 5) {
+ eNB->UE_stats[0].DL_pmi_single = (unsigned short)(taus()&0xffff);
+
+ if (n_users>1)
+ eNB->UE_stats[1].DL_pmi_single = (eNB->UE_stats[0].DL_pmi_single ^ 0x1555); //opposite PMI
+ } else {
+ eNB->UE_stats[0].DL_pmi_single = 0;
+
+ if (n_users>1)
+ eNB->UE_stats[1].DL_pmi_single = 0;
+ }
+
+ L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc;
+
+ if (input_fd==NULL) {
+ DL_req.dl_config_request_body.number_pdcch_ofdm_symbols = num_pdcch_symbols;
+ DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ // UE specific DCI
+ fill_DCI(eNB,
+ proc_eNB->frame_tx,subframe,
+ &sched_resp,
+ input_buffer,
+ n_rnti,
+ n_users,
+ transmission_mode,
+ 0,
+ common_flag,
+ NB_RB,
+ DLSCH_RB_ALLOC,
+ TPC,
+ mcs1,
+ mcs2,
+ 1,
+ 0,
+ pa,
+ &num_common_dci,
+ &num_ue_spec_dci,
+ &num_dci);
+ numCCE = get_nCCE(num_pdcch_symbols,&eNB->frame_parms,get_mi(&eNB->frame_parms,subframe));
+
+ if (n_frames==1) printf("num_pdcch_symbols %d, numCCE %d, num_dci %d/%d/%d\n",num_pdcch_symbols,numCCE, num_dci,num_ue_spec_dci,num_common_dci);
+ }
+
+ eNB->frame_parms.Nid_cell_mbsfn=0;
+ if(enable_fembms){
+ lte_gold_mbsfn_khz_1dot25 (&eNB->frame_parms, eNB->lte_gold_mbsfn_khz_1dot25_table, eNB->frame_parms.Nid_cell_mbsfn);
+ eNB->frame_parms.NonMBSFN_config_flag=1;
+ }else{
+ lte_gold_mbsfn (&eNB->frame_parms, eNB->lte_gold_mbsfn_table, eNB->frame_parms.Nid_cell_mbsfn);
+ eNB->frame_parms.num_MBSFN_config=1;
+ eNB->frame_parms.MBSFN_config[0].radioframeAllocationPeriod=0;
+ eNB->frame_parms.MBSFN_config[0].fourFrames_flag=0;
+ eNB->frame_parms.MBSFN_config[0].radioframeAllocationOffset=0;
+ //eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xC0;
+ eNB->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xFC;
+ }
+
+
+
+ snr_step = input_snr_step;
+ UE->high_speed_flag = 1;
+ UE->ch_est_alpha=0;
+
+ for (ch_realization=0; ch_realization<n_ch_rlz; ch_realization++) {
+ if(abstx) {
+ printf("**********************Channel Realization Index = %d **************************\n", ch_realization);
+ }
+
+ for (SNR=snr0; SNR<snr1; SNR+=snr_step) {
+ UE->proc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx=0;
+ errs[0]=0;
+ errs[1]=0;
+ errs[2]=0;
+ errs[3]=0;
+ errs2[0]=0;
+ errs2[1]=0;
+ errs2[2]=0;
+ errs2[3]=0;
+ round_trials[0] = 0;
+ round_trials[1] = 0;
+ round_trials[2] = 0;
+ round_trials[3] = 0;
+ dci_errors[0]=0;
+ dci_errors[1]=0;
+ dci_errors[2]=0;
+ dci_errors[3]=0;
+ // avg_ber = 0;
+ round=0;
+ avg_iter = 0;
+ iter_trials=0;
+ reset_meas(&eNB->phy_proc_tx); // total eNB tx
+ reset_meas(&eNB->dlsch_scrambling_stats);
+ reset_meas(&UE->dlsch_unscrambling_stats);
+ reset_meas(&eNB->ofdm_mod_stats);
+ reset_meas(&eNB->dlsch_modulation_stats);
+ reset_meas(&eNB->dlsch_encoding_stats);
+ reset_meas(&eNB->dlsch_interleaving_stats);
+ reset_meas(&eNB->dlsch_rate_matching_stats);
+ reset_meas(&eNB->dlsch_turbo_encoding_stats);
+ reset_meas(&eNB->dlsch_common_and_dci);
+ reset_meas(&eNB->dlsch_ue_specific);
+
+ for (int i=0; i<RX_NB_TH; i++) {
+ reset_meas(&UE->phy_proc_rx[i]); // total UE rx
+ reset_meas(&UE->ue_front_end_stat[i]);
+ reset_meas(&UE->pdsch_procedures_stat[i]);
+ reset_meas(&UE->dlsch_procedures_stat[i]);
+ reset_meas(&UE->dlsch_decoding_stats[i]);
+ reset_meas(&UE->dlsch_llr_stats_parallelization[i][0]);
+ reset_meas(&UE->dlsch_llr_stats_parallelization[i][1]);
}
- for (l=2; l<12; l++) {
- slot_fep_mbsfn(UE,
- l,
- subframe%10,
- 0,
- 0);
-
- if (UE->perfect_ce==1) {
- // fill in perfect channel estimates
- freq_channel(eNB2UE,UE->frame_parms.N_RB_DL,12*UE->frame_parms.N_RB_DL + 1);
-
- for(k=0; k<NUMBER_OF_eNB_MAX; k++) {
- for(aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
- for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
- for (i=0; i<frame_parms->N_RB_DL*12; i++) {
- ((int16_t *) UE->common_vars.common_vars_rx_data_per_thread[subframe&0x1].dl_ch_estimates[k][(aa<<1)+aarx])[2*i+(l*frame_parms->ofdm_symbol_size+LTE_CE_FILTER_LENGTH)*2]=(int16_t)(eNB2UE->chF[aarx+
- (aa*frame_parms->nb_antennas_rx)][i].x*AMP);
- ((int16_t *) UE->common_vars.common_vars_rx_data_per_thread[subframe&0x1].dl_ch_estimates[k][(aa<<1)+aarx])[2*i+1+(l*frame_parms->ofdm_symbol_size+LTE_CE_FILTER_LENGTH)*2]=(int16_t)(eNB2UE->chF[aarx+
- (aa*frame_parms->nb_antennas_rx)][i].y*AMP);
- }
+ reset_meas(&UE->ofdm_demod_stats);
+ reset_meas(&UE->crnti_procedures_stats);
+ reset_meas(&UE->dlsch_channel_estimation_stats);
+ reset_meas(&UE->dlsch_freq_offset_estimation_stats);
+ reset_meas(&UE->rx_dft_stats);
+ reset_meas(&UE->dlsch_decoding_stats[0]);
+ reset_meas(&UE->dlsch_decoding_stats[1]);
+ reset_meas(&UE->dlsch_turbo_decoding_stats);
+ reset_meas(&UE->dlsch_deinterleaving_stats);
+ reset_meas(&UE->dlsch_rate_unmatching_stats);
+ reset_meas(&UE->dlsch_tc_init_stats);
+ reset_meas(&UE->dlsch_tc_alpha_stats);
+ reset_meas(&UE->dlsch_tc_beta_stats);
+ reset_meas(&UE->dlsch_tc_gamma_stats);
+ reset_meas(&UE->dlsch_tc_ext_stats);
+ reset_meas(&UE->dlsch_tc_intl1_stats);
+ reset_meas(&UE->dlsch_tc_intl2_stats);
+ // initialization
+ // initialization
+ varArray_t *table_tx=initVarArray(1000,sizeof(double));
+ varArray_t *table_tx_ifft=initVarArray(1000,sizeof(double));
+ varArray_t *table_tx_mod=initVarArray(1000,sizeof(double));
+ varArray_t *table_tx_enc=initVarArray(1000,sizeof(double));
+ varArray_t *table_rx=initVarArray(1000,sizeof(double));
+ time_stats_t phy_proc_rx_tot;
+ time_stats_t pdsch_procedures_tot;
+ time_stats_t dlsch_procedures_tot;
+ time_stats_t dlsch_decoding_tot;
+ time_stats_t dlsch_llr_tot;
+ time_stats_t ue_front_end_tot;
+ varArray_t *table_rx_fft=initVarArray(1000,sizeof(double));
+ varArray_t *table_rx_demod=initVarArray(1000,sizeof(double));
+ varArray_t *table_rx_dec=initVarArray(1000,sizeof(double));
+
+ for (trials = 0; trials<n_frames; trials++) {
+ //printf("Trial %d\n",trials);
+ fflush(stdout);
+ round=0;
+ //if (trials%100==0)
+ eNB2UE[0]->first_run = 1;
+ UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack = 0;
+ UE->dlsch[UE->current_thread_id[subframe]][eNB_id][1]->harq_ack[subframe].ack = 0;
+
+ while ((round < num_rounds) && (UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack == 0)) {
+ // printf("Trial %d, round %d\n",trials,round);
+ round_trials[round]++;
+
+ //if(transmission_mode>=5)
+ // pmi_feedback=1;
+ //else
+ // pmi_feedback=0;
+
+ if (abstx) {
+ if (trials==0 && round==0 && SNR==snr0) //generate a new channel
+ hold_channel = 0;
+ else
+ hold_channel = 1;
+ } else
+ hold_channel = 0;//(round==0) ? 0 : 1;
+
+ //PMI_FEEDBACK:
+
+ // printf("Trial %d : Round %d, pmi_feedback %d \n",trials,round,pmi_feedback);
+ for (aa=0; aa<eNB->frame_parms.nb_antennas_tx; aa++) {
+ memset(&eNB->common_vars.txdataF[aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t));
+ }
+
+ if (input_fd==NULL) {
+ // Simulate HARQ procedures!!!
+ memset(CCE_table,0,800*sizeof(int));
+
+ if (/*common_flag == 0*/ 1) {
+ num_dci=0;
+ num_common_dci=0;
+ num_ue_spec_dci=0;
+
+ if (round == 0) { // First round
+ TB0_active = 1;
+ eNB->dlsch[0][0]->harq_processes[0]->rvidx = round&3;
+ DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ fill_DCI(eNB,proc_eNB->frame_tx,subframe,&sched_resp,input_buffer,n_rnti,n_users,transmission_mode,0,common_flag,NB_RB,DLSCH_RB_ALLOC,TPC,
+ mcs1,mcs2,!(trials&1),round&3,pa,&num_common_dci,&num_ue_spec_dci,&num_dci);
+ } else {
+ DL_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ TX_req.sfn_sf = (proc_eNB->frame_tx<<4)+subframe;
+ fill_DCI(eNB,proc_eNB->frame_tx,subframe,&sched_resp,input_buffer,n_rnti,n_users,transmission_mode,1,common_flag,NB_RB,DLSCH_RB_ALLOC,TPC,
+ (TB0_active==1)?mcs1:0,mcs2,!(trials&1),(TB0_active==1)?round&3:0,pa,&num_common_dci,&num_ue_spec_dci,&num_dci);
+ }
+ }
+
+//#ifdef ENABLE_MBMS_SIM
+// eNB->frame_parms.Nid_cell_mbsfn=0;
+// lte_gold_mbsfn (&eNB->frame_parms, eNB->lte_gold_mbsfn_table, eNB->frame_parms.Nid_cell_mbsfn);
+//#endif
+
+ UE->measurements.n0_power_tot_dB = 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR;
+ UE->measurements.n0_power_tot = pow(10,( 10*log10((double)tx_lev) +10*log10((double)ru->frame_parms.ofdm_symbol_size/(double)(ru->frame_parms.N_RB_DL*12)) - SNR)/10);
+
+ proc_eNB->subframe_tx = subframe;
+ sched_resp.subframe=subframe;
+ sched_resp.frame=proc_eNB->frame_tx;
+ eNB->abstraction_flag=0;
+ schedule_response(&sched_resp);
+ phy_procedures_eNB_TX(eNB,proc_eNB,1);
+
+ if (uncoded_ber_bit == NULL) {
+ // this is for user 0 only
+ printf("nb_rb %d, rb_alloc %x, mcs %d\n",
+ eNB->dlsch[0][0]->harq_processes[0]->nb_rb,
+ eNB->dlsch[0][0]->harq_processes[0]->rb_alloc[0],
+ eNB->dlsch[0][0]->harq_processes[0]->mcs);
+ coded_bits_per_codeword = get_G(&eNB->frame_parms,
+ eNB->dlsch[0][0]->harq_processes[0]->nb_rb,
+ eNB->dlsch[0][0]->harq_processes[0]->rb_alloc,
+ get_Qm(eNB->dlsch[0][0]->harq_processes[0]->mcs),
+ eNB->dlsch[0][0]->harq_processes[0]->Nl,
+ num_pdcch_symbols,
+ 0,
+ subframe,
+ transmission_mode>=7?transmission_mode:0);
+ uncoded_ber_bit = (short *) malloc(sizeof(short)*coded_bits_per_codeword);
+ printf("uncoded_ber_bit=%p\n",uncoded_ber_bit);
+ }
+
+
+
+ start_meas(&eNB->ofdm_mod_stats);
+ ru->proc.subframe_tx=subframe;
+ LOG_W(PHY,"eNB %d\n",eNB->frame_parms.num_MBSFN_config);
+ LOG_W(PHY,"eNB %d\n",eNB->frame_parms.NonMBSFN_config_flag);
+ memcpy((void *)&ru->frame_parms,(void *)&eNB->frame_parms,sizeof(LTE_DL_FRAME_PARMS));
+ LOG_W(PHY,"RU %d\n",ru->frame_parms.num_MBSFN_config);
+ LOG_W(PHY,"RU %d\n",ru->frame_parms.NonMBSFN_config_flag);
+ feptx_prec(ru);
+ feptx_ofdm(ru);
+ stop_meas(&eNB->ofdm_mod_stats);
+ // generate next subframe for channel estimation
+ DL_req.dl_config_request_body.number_dci=0;
+ DL_req.dl_config_request_body.number_pdu=0;
+ TX_req.tx_request_body.number_of_pdus=0;
+ proc_eNB->subframe_tx = subframe+1;
+ sched_resp.subframe=subframe+1;
+ schedule_response(&sched_resp);
+
+ phy_procedures_eNB_TX(eNB,proc_eNB,0);
+ ru->proc.subframe_tx=(subframe+1)%10;
+ feptx_prec(ru);
+ feptx_ofdm(ru);
+ proc_eNB->frame_tx++;
+ tx_lev = 0;
+
+ for (aa=0; aa<eNB->frame_parms.nb_antennas_tx; aa++) {
+ tx_lev += signal_energy(&ru->common.txdata[aa]
+ [subframe*eNB->frame_parms.samples_per_tti],
+ eNB->frame_parms.samples_per_tti);
+ }
+
+ tx_lev_dB = (unsigned int) dB_fixed(tx_lev);
+
+ if (n_frames==1) {
+ printf("tx_lev = %u (%u dB)\n",tx_lev,tx_lev_dB);
+ LOG_M("txsig0.m","txs0", &ru->common.txdata[0][subframe* eNB->frame_parms.samples_per_tti], eNB->frame_parms.samples_per_tti,1,1);
+
+ if (transmission_mode<7) {
+ LOG_M("txsigF0.m","txsF0x", &ru->common.txdataF_BF[0][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1);
+ } else if (transmission_mode == 7) {
+ LOG_M("txsigF0.m","txsF0", &ru->common.txdataF_BF[5][subframe*nsymb*eNB->frame_parms.ofdm_symbol_size],nsymb*eNB->frame_parms.ofdm_symbol_size,1,1);
+ LOG_M("txsigF0_BF.m","txsF0_BF", &ru->common.txdataF_BF[0][0],eNB->frame_parms.ofdm_symbol_size,1,1);
}
}
}
+
+ DL_channel(ru,UE,subframe,awgn_flag,SNR,tx_lev,hold_channel,abstx,num_rounds,trials,round,eNB2UE,s_re,s_im,r_re,r_im,csv_fd);
+ UE_rxtx_proc_t *proc = &UE->proc.proc_rxtx[UE->current_thread_id[subframe]];
+ proc->subframe_rx = subframe;
+ UE->UE_mode[0] = PUSCH;
+ // first symbol has to be done separately in one-shot mode
+ slot_fep(UE,
+ 0,
+ (proc->subframe_rx<<1),
+ UE->rx_offset,
+ 0,
+ 0);
+
+ if (n_frames==1) printf("Running phy_procedures_UE_RX\n");
+
+ if (dci_flag==0) {
+ memcpy(dci_alloc,eNB->pdcch_vars[subframe&1].dci_alloc,num_dci*sizeof(DCI_ALLOC_t));
+ UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->num_pdcch_symbols = num_pdcch_symbols;
+
+ if (n_frames==1)
+ printf("bypassing PDCCH/DCI detection\n");
+
+ if (generate_ue_dlsch_params_from_dci(proc->frame_rx,
+ proc->subframe_rx,
+ (void *)&dci_alloc[0].dci_pdu,
+ common_flag == 0 ? n_rnti : SI_RNTI,
+ dci_alloc[0].format,
+ UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id],
+ UE->pdsch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id],
+ UE->dlsch[UE->current_thread_id[proc->subframe_rx]][0],
+ &UE->frame_parms,
+ UE->pdsch_config_dedicated,
+ SI_RNTI,
+ 0,
+ P_RNTI,
+ UE->transmission_mode[eNB_id]<7?0:UE->transmission_mode[eNB_id],
+ 0)==0) {
+ dump_dci(&UE->frame_parms, &dci_alloc[0]);
+ //UE->dlsch[UE->current_thread_id[proc->subframe_rx]][eNB_id][0]->active = 1;
+ //UE->dlsch[UE->current_thread_id[proc->subframe_rx]][eNB_id][1]->active = 1;
+ UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->num_pdcch_symbols = num_pdcch_symbols;
+ UE->dlsch_received[eNB_id]++;
+ } else {
+ LOG_E(PHY,"Problem in DCI!\n");
+ }
+ }
+
+
+ UE->frame_parms.Nid_cell_mbsfn=0;
+ if(enable_fembms){
+ lte_gold_mbsfn_khz_1dot25 (&UE->frame_parms, UE->lte_gold_mbsfn_khz_1dot25_table, UE->frame_parms.Nid_cell_mbsfn);
+ UE->frame_parms.NonMBSFN_config_flag=1;
+ }else{
+ lte_gold_mbsfn (&UE->frame_parms, UE->lte_gold_mbsfn_table, UE->frame_parms.Nid_cell_mbsfn);
+ UE->frame_parms.num_MBSFN_config=1;
+ UE->frame_parms.MBSFN_config[0].radioframeAllocationPeriod=0;
+ UE->frame_parms.MBSFN_config[0].fourFrames_flag=0;
+ UE->frame_parms.MBSFN_config[0].radioframeAllocationOffset=0;
+ UE->frame_parms.MBSFN_config[0].mbsfn_SubframeConfig=0xC0;
+ }
+
+
+
+
+ dci_received = UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->dci_received;
+ phy_procedures_UE_RX(UE,proc,0,0,dci_flag,normal_txrx);
+ dci_received = dci_received - UE->pdcch_vars[UE->current_thread_id[proc->subframe_rx]][eNB_id]->dci_received;
+
+ if (dci_flag && (dci_received == 0)) {
+ printf("DCI not received\n");
+ dci_errors[round]++;
+ LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1);
+ LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1);
+ LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1);
+ LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4);
+ LOG_M("rxsig0.m","rxs0", &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1);
+ LOG_M("rxsigF0.m","rxsF0", &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+ exit(-1);
+ }
+
+ int bit_errors=0;
+
+ if ((test_perf ==0 ) && (n_frames==1)) {
+ dlsch_unscrambling(&eNB->frame_parms,
+ 0,
+ UE->dlsch[UE->current_thread_id[subframe]][0][0],
+ coded_bits_per_codeword,
+ UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0],
+ 0,
+ subframe<<1);
+
+ for (i=0; i<coded_bits_per_codeword; i++)
+ if ((eNB->dlsch[0][0]->harq_processes[0]->e[i]==1 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] > 0)||
+ (eNB->dlsch[0][0]->harq_processes[0]->e[i]==0 && UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i] < 0)) {
+ uncoded_ber_bit[bit_errors++] = 1;
+ printf("error in pos %d : %d => %d\n",i,
+ eNB->dlsch[0][0]->harq_processes[0]->e[i],
+ UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i]);
+ } else {
+ /*
+ printf("no error in pos %d : %d => %d\n",i,
+ eNB->dlsch[0][0]->harq_processes[0]->e[i],
+ UE->pdsch_vars[UE->current_thread_id[subframe]][0]->llr[0][i]);
+ */
+ }
+
+ LOG_M("dlsch_ber_bit.m","ber_bit",uncoded_ber_bit,coded_bits_per_codeword,1,0);
+ LOG_M("ch0.m","ch0",eNB2UE[0]->ch[0],eNB2UE[0]->channel_length,1,8);
+
+ if (eNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("ch1.m","ch1",eNB2UE[0]->ch[eNB->frame_parms.nb_antennas_rx],eNB2UE[0]->channel_length,1,8);
+
+ //common vars
+ LOG_M("rxsig0.m","rxs0", &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1);
+ LOG_M("rxsigF0.m","rxsF0", &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if (UE->frame_parms.nb_antennas_rx>1) {
+ LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1],UE->frame_parms.samples_per_tti,1,1);
+ LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[1],UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+ }
+
+ LOG_M("dlsch00_r0.m","dl00_r0",
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][0][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if (UE->frame_parms.nb_antennas_rx>1)
+ LOG_M("dlsch01_r0.m","dl01_r0",
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][1][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if (eNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("dlsch10_r0.m","dl10_r0",
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][2][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if ((UE->frame_parms.nb_antennas_rx>1) && (eNB->frame_parms.nb_antennas_tx>1))
+ LOG_M("dlsch11_r0.m","dl11_r0",
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][3][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1);
+
+ //pdsch_vars
+ printf("coded_bits_per_codeword %u\n",coded_bits_per_codeword);
+ dump_dlsch2(UE,eNB_id,subframe,&coded_bits_per_codeword,round, UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid);
+ LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->e,coded_bits_per_codeword,1,4);
+ //pdcch_vars
+ LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1);
+ LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1);
+ LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1);
+ LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4);
+ }
+
+ if (UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_ack[subframe].ack == 1) {
+ avg_iter += UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->last_iteration_cnt;
+ iter_trials++;
+
+ if (n_frames==1)
+ printf("No DLSCH errors found (round %d),uncoded ber %f\n",round,(double)bit_errors/coded_bits_per_codeword);
+
+ UE->total_TBS[eNB_id] = UE->total_TBS[eNB_id] + UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->harq_processes[UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->current_harq_pid]->TBS;
+ TB0_active = 0;
+ } // DLSCH received ok
+ else {
+ errs[round]++;
+ avg_iter += UE->dlsch[UE->current_thread_id[subframe]][eNB_id][0]->last_iteration_cnt-1;
+ iter_trials++;
+
+ if (n_frames==1) {
+ //if ((n_frames==1) || (SNR>=30)) {
+ printf("DLSCH errors found (round %d), uncoded ber %f\n",round,(double)bit_errors/coded_bits_per_codeword);
+
+ for (s=0; s<UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->C; s++) {
+ if (s<UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus)
+ Kr = UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus;
+ else
+ Kr = UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus;
+
+ Kr_bytes = Kr>>3;
+ printf("Decoded_output (Segment %d):\n",s);
+
+ for (i=0; i<Kr_bytes; i++)
+ printf("%d : %x (%x)\n",i,UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->c[s][i],
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->c[s][i]^eNB->dlsch[0][0]->harq_processes[0]->c[s][i]);
+ }
+
+ sprintf(fname,"rxsig0_r%d.m",round);
+ sprintf(vname,"rxs0_r%d",round);
+ LOG_M(fname,vname, &UE->common_vars.rxdata[0][0],10*UE->frame_parms.samples_per_tti,1,1);
+ sprintf(fname,"rxsigF0_r%d.m",round);
+ sprintf(vname,"rxs0F_r%d",round);
+ LOG_M(fname,vname, &UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[0][0],UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if (UE->frame_parms.nb_antennas_rx>1) {
+ sprintf(fname,"rxsig1_r%d.m",round);
+ sprintf(vname,"rxs1_r%d.m",round);
+ LOG_M(fname,vname, UE->common_vars.rxdata[1],UE->frame_parms.samples_per_tti,1,1);
+ sprintf(fname,"rxsigF1_r%d.m",round);
+ sprintf(vname,"rxs1F_r%d.m",round);
+ LOG_M(fname,vname, UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].rxdataF[1],UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+ }
+
+ sprintf(fname,"dlsch00_r%d.m",round);
+ sprintf(vname,"dl00_r%d",round);
+ LOG_M(fname,vname,
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][0][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb,1,1);
+
+ if (UE->frame_parms.nb_antennas_rx>1) {
+ sprintf(fname,"dlsch01_r%d.m",round);
+ sprintf(vname,"dl01_r%d",round);
+ LOG_M(fname,vname,
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][1][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1);
+ }
+
+ if (eNB->frame_parms.nb_antennas_tx>1) {
+ sprintf(fname,"dlsch10_r%d.m",round);
+ sprintf(vname,"dl10_r%d",round);
+ LOG_M(fname,vname,
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][2][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1);
+ }
+
+ if ((UE->frame_parms.nb_antennas_rx>1) && (eNB->frame_parms.nb_antennas_tx>1)) {
+ sprintf(fname,"dlsch11_r%d.m",round);
+ sprintf(vname,"dl11_r%d",round);
+ LOG_M(fname,vname,
+ &(UE->common_vars.common_vars_rx_data_per_thread[UE->current_thread_id[subframe]].dl_ch_estimates[eNB_id][3][0]),
+ UE->frame_parms.ofdm_symbol_size*nsymb/2,1,1);
+ }
+
+ //pdsch_vars
+ dump_dlsch2(UE,eNB_id,subframe,&coded_bits_per_codeword,round, UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid);
+ //LOG_M("dlsch_e.m","e",eNB->dlsch[0][0]->harq_processes[0]->e,coded_bits_per_codeword,1,4);
+ //LOG_M("dlsch_ber_bit.m","ber_bit",uncoded_ber_bit,coded_bits_per_codeword,1,0);
+ //LOG_M("dlsch_w.m","w",eNB->dlsch[0][0]->harq_processes[0]->w[0],3*(tbs+64),1,4);
+ //LOG_M("dlsch_w.m","w",UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->w[0],3*(tbs+64),1,0);
+ //pdcch_vars
+ LOG_M("pdcchF0_ext.m","pdcchF_ext", UE->pdcch_vars[0][eNB_id]->rxdataF_ext[0],2*3*UE->frame_parms.ofdm_symbol_size,1,1);
+ LOG_M("pdcch00_ch0_ext.m","pdcch00_ch0_ext",UE->pdcch_vars[0][eNB_id]->dl_ch_estimates_ext[0],300*3,1,1);
+ LOG_M("pdcch_rxF_comp0.m","pdcch0_rxF_comp0",UE->pdcch_vars[0][eNB_id]->rxdataF_comp[0],4*300,1,1);
+ LOG_M("pdcch_rxF_llr.m","pdcch_llr",UE->pdcch_vars[0][eNB_id]->llr,2400,1,4);
+
+ if (round == 3) exit(-1);
+ }
+
+ // printf("round %d errors %d/%d\n",round,errs[round],trials);
+ round++;
+ // UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->round++;
+ }
+
+ if (xforms==1) {
+ phy_scope_UE(form_ue,
+ UE,
+ eNB_id,
+ 0,// UE_id
+ subframe);
+ }
+
+ UE->proc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx++;
+ } //round
+
+ // printf("\n");
+
+ if ((errs[0]>=n_frames/10) && (trials>(n_frames/2)))
+ break;
+
+ //len = chbch_stats_read(stats_buffer,NULL,0,4096);
+ //printf("%s\n\n",stats_buffer);
+
+ if (UE->proc.proc_rxtx[UE->current_thread_id[subframe]].frame_rx % 10 == 0) {
+ UE->bitrate[eNB_id] = (UE->total_TBS[eNB_id] - UE->total_TBS_last[eNB_id])*10;
+ LOG_D(PHY,"[UE %d] Calculating bitrate: total_TBS = %d, total_TBS_last = %d, bitrate = %d kbits/s\n",UE->Mod_id,UE->total_TBS[eNB_id],UE->total_TBS_last[eNB_id],
+ UE->bitrate[eNB_id]/1000);
+ UE->total_TBS_last[eNB_id] = UE->total_TBS[eNB_id];
}
- if (l==6)
- for (l2=2; l2<7; l2++)
- rx_pmch(UE,
- 0,
- subframe%10,
- l2);
+ /* calculate the total processing time for each packet,
+ * get the max, min, and number of packets that exceed t>2000us
+ */
+ double t_tx = inMicroS(eNB->phy_proc_tx.p_time);
+ double t_tx_ifft = inMicroS(eNB->ofdm_mod_stats.p_time);
+ double t_rx = inMicroS(UE->phy_proc_rx[UE->current_thread_id[subframe]].p_time);
+ sumUpStats(&phy_proc_rx_tot, UE->phy_proc_rx, UE->current_thread_id[subframe]);
+ sumUpStats(&ue_front_end_tot, UE->ue_front_end_stat, UE->current_thread_id[subframe]);
+ sumUpStats(&pdsch_procedures_tot, UE->pdsch_procedures_stat, UE->current_thread_id[subframe]);
+ sumUpStats(&dlsch_procedures_tot, UE->dlsch_procedures_stat, UE->current_thread_id[subframe]);
+ sumUpStats(&dlsch_decoding_tot, UE->dlsch_decoding_stats, UE->current_thread_id[subframe]);
+ sumUpStatsSlot(&dlsch_llr_tot, UE->dlsch_llr_stats_parallelization, UE->current_thread_id[subframe]);
+ double t_rx_fft = inMicroS(UE->ofdm_demod_stats.p_time);
+ double t_rx_demod = inMicroS(UE->dlsch_rx_pdcch_stats.p_time);
+ double t_rx_dec = inMicroS(UE->dlsch_decoding_stats[UE->current_thread_id[subframe]].p_time);
+
+ if (t_tx > 2000 )// 2ms is too much time for a subframe
+ n_tx_dropped++;
+
+ if (t_rx > 2000 )
+ n_rx_dropped++;
+
+ appendVarArray(table_tx, &t_tx);
+ appendVarArray(table_tx_ifft, &t_tx_ifft);
+ appendVarArray(table_rx, &t_rx );
+ appendVarArray(table_rx_fft, &t_rx_fft );
+ appendVarArray(table_rx_demod, &t_rx_demod );
+ appendVarArray(table_rx_dec, &t_rx_dec );
+ } //trials
+
+ // round_trials[0]: number of code word : goodput the protocol
+ // sort table
+ qsort (dataArray(table_tx), table_tx->size, table_tx->atomSize, &cmpdouble);
+ qsort (dataArray(table_tx_ifft), table_tx_ifft->size, table_tx_ifft->atomSize, &cmpdouble);
+ qsort (dataArray(table_tx_mod), table_tx_mod->size, table_tx_mod->atomSize, &cmpdouble);
+ qsort (dataArray(table_tx_enc), table_tx_enc->size, table_tx_enc->atomSize, &cmpdouble);
+ qsort (dataArray(table_rx), table_rx->size, table_rx->atomSize, &cmpdouble);
+ qsort (dataArray(table_rx_fft), table_rx_fft->size, table_rx_fft->atomSize, &cmpdouble);
+ qsort (dataArray(table_rx_demod), table_rx_demod->size, table_rx_demod->atomSize, &cmpdouble);
+ qsort (dataArray(table_rx_dec), table_rx_dec->size, table_rx_dec->atomSize, &cmpdouble);
+
+ if (dump_table == 1 ) {
+ set_component_filelog(SIM); // file located in /tmp/usim.txt
+ LOG_UDUMPMSG(SIM,table_tx,table_tx->size,LOG_DUMP_DOUBLE,"The transmitter raw data: \n");
+ LOG_UDUMPMSG(SIM,table_rx,table_rx->size,LOG_DUMP_DOUBLE,"Thereceiver raw data: \n");
+ }
- if (l==6)
- for (l2=2; l2<7; l2++)
- rx_pmch(UE,
- 0,
- subframe%10,
- l2);
+ effective_rate = 1.0-((double)(errs[0]+errs[1]+errs[2]+errs[3])/((double)round_trials[0] + round_trials[1] + round_trials[2] + round_trials[3]));
+ printf("\n**********************SNR = %f dB (tx_lev %f)**************************\n",
+ SNR,
+ (double)tx_lev_dB+10*log10(UE->frame_parms.ofdm_symbol_size/(NB_RB*12)));
+ printf("Errors (%u(%u)/%u %u/%u %u/%u %u/%u), Pe = (%e,%e,%e,%e), dci_errors %u/%u, Pe = %e => effective rate %f, normalized delay %f (%f)\n",
+ errs[0],
+ errs2[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ (double)errs[0]/(round_trials[0]),
+ (double)errs[1]/(round_trials[1]),
+ (double)errs[2]/(round_trials[2]),
+ (double)errs[3]/(round_trials[3]),
+ dci_errors[0]+dci_errors[1]+dci_errors[2]+dci_errors[3],
+ round_trials[0]+round_trials[1]+round_trials[2]+round_trials[3],
+ (double)(dci_errors[0]+dci_errors[1]+dci_errors[2]+dci_errors[3])/(round_trials[0]+round_trials[1]+round_trials[2]+round_trials[3]),
+ //rate*effective_rate,
+ 100*effective_rate,
+ //rate,
+ //rate*get_Qm(UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[UE->dlsch[UE->current_thread_id[subframe]][0][0]->current_harq_pid]->mcs),
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/
+ (double)eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0]));
+ double timeBase=1/(1000*cpu_freq_GHz);
+
+ if (print_perf==1) {
+ printf("\neNB TX function statistics (per 1ms subframe)\n");
+ printDistribution(&eNB->phy_proc_tx,table_tx,"PHY proc tx");
+ printStatIndent(&eNB->dlsch_common_and_dci,"DL common channels and dci time");
+ printStatIndent(&eNB->dlsch_ue_specific,"DL per ue part time");
+ printStatIndent2(&eNB->dlsch_encoding_stats,"DLSCH encoding time");
+ printStatIndent3(&eNB->dlsch_rate_matching_stats,"DLSCH rate matching time");
+ printStatIndent3(&eNB->dlsch_turbo_encoding_stats,"DLSCH turbo encoding time");
+ printStatIndent3(&eNB->dlsch_interleaving_stats,"DLSCH interleaving time");
+ printStatIndent2(&eNB->dlsch_scrambling_stats, "DLSCH scrambling time");
+ printStatIndent2(&eNB->dlsch_modulation_stats, "DLSCH modulation time");
+ printDistribution(&eNB->ofdm_mod_stats,table_tx_ifft,"OFDM_mod (idft) time");
+ printf("\nUE RX function statistics (per 1ms subframe)\n");
+ printDistribution(&phy_proc_rx_tot, table_rx,"Total PHY proc rx");
+ printStatIndent(&ue_front_end_tot,"Front end processing");
+ printStatIndent(&dlsch_llr_tot,"rx_pdsch processing");
+ printStatIndent2(&pdsch_procedures_tot,"pdsch processing");
+ printStatIndent2(&dlsch_procedures_tot,"dlsch processing");
+ printStatIndent2(&UE->crnti_procedures_stats,"C-RNTI processing");
+ printStatIndent(&UE->ofdm_demod_stats,"ofdm demodulation");
+ printStatIndent(&UE->dlsch_channel_estimation_stats,"DLSCH channel estimation time");
+ printStatIndent(&UE->dlsch_freq_offset_estimation_stats,"DLSCH frequency offset estimation time");
+ printStatIndent(&dlsch_decoding_tot, "DLSCH Decoding time ");
+ printStatIndent(&UE->dlsch_unscrambling_stats,"DLSCH unscrambling time");
+ printStatIndent(&UE->dlsch_rate_unmatching_stats,"DLSCH Rate Unmatching");
+ printf("|__ DLSCH Turbo Decoding(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n",
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus ?
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus :
+ UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus,
+ UE->dlsch_tc_intl1_stats.trials/(double)UE->dlsch_tc_init_stats.trials,
+ (double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials*timeBase,
+ (int)((double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials),
+ UE->dlsch_turbo_decoding_stats.trials);
+ printStatIndent2(&UE->dlsch_tc_init_stats,"init");
+ printStatIndent2(&UE->dlsch_tc_alpha_stats,"alpha");
+ printStatIndent2(&UE->dlsch_tc_beta_stats,"beta");
+ printStatIndent2(&UE->dlsch_tc_gamma_stats,"gamma");
+ printStatIndent2(&UE->dlsch_tc_ext_stats,"ext");
+ printStatIndent2(&UE->dlsch_tc_intl1_stats,"turbo internal interleaver");
+ printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
+ }
- if (l==11)
- for (l2=7; l2<12; l2++)
- rx_pmch(UE,
- 0,
- subframe%10,
- l2);
+ if ((transmission_mode != 3) && (transmission_mode != 4)) {
+ fprintf(bler_fd,"%f;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u\n",
+ SNR,
+ mcs1,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ rate,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ dci_errors[0]);
+ } else {
+ fprintf(bler_fd,"%f;%d;%d;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u\n",
+ SNR,
+ mcs1,mcs2,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ eNB->dlsch[0][1]->harq_processes[0]->TBS,
+ rate,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ dci_errors[0]);
}
- UE->dlsch_MCH[0]->harq_processes[0]->G = get_G(&UE->frame_parms,
- UE->dlsch_MCH[0]->harq_processes[0]->nb_rb,
- UE->dlsch_MCH[0]->harq_processes[0]->rb_alloc_even,
- get_Qm(UE->dlsch_MCH[0]->harq_processes[0]->mcs),
- 1,2,
- UE->proc.proc_rxtx[0].frame_tx,subframe,0);
- UE->dlsch_MCH[0]->harq_processes[0]->Qm = get_Qm(UE->dlsch_MCH[0]->harq_processes[0]->mcs);
- dlsch_unscrambling(&UE->frame_parms,1,UE->dlsch_MCH[0],
- UE->dlsch_MCH[0]->harq_processes[0]->G,
- UE->pdsch_vars_MCH[0]->llr[0],0,subframe<<1);
- ret = dlsch_decoding(UE,
- UE->pdsch_vars_MCH[0]->llr[0],
- &UE->frame_parms,
- UE->dlsch_MCH[0],
- UE->dlsch_MCH[0]->harq_processes[0],
- trials,
- subframe,
- 0,0,0);
-
- if (n_frames==1)
- printf("MCH decoding returns %u\n",ret);
-
- if (ret == (1+UE->dlsch_MCH[0]->max_turbo_iterations))
- errs[0]++;
-
- UE->proc.proc_rxtx[0].frame_tx++;
- eNB->proc.proc_rxtx[0].frame_tx++;
- }
+ if(abstx) { //ABSTRACTION
+ blerr[0] = (double)errs[0]/(round_trials[0]);
+
+ if(num_rounds>1) {
+ blerr[1] = (double)errs[1]/(round_trials[1]);
+ blerr[2] = (double)errs[2]/(round_trials[2]);
+ blerr[3] = (double)errs[3]/(round_trials[3]);
+ fprintf(csv_fd,"%e,%e,%e,%e;\n",blerr[0],blerr[1],blerr[2],blerr[3]);
+ } else {
+ fprintf(csv_fd,"%e;\n",blerr[0]);
+ }
+ } //ABStraction
+
+ if ( (test_perf != 0) && (100 * effective_rate > test_perf )) {
+ //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; err0; trials0; err1; trials1; err2; trials2; err3; trials3; dci_err\n");
+ if ((transmission_mode != 3) && (transmission_mode != 4)) {
+ fprintf(time_meas_fd,"%f;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u;",
+ SNR,
+ mcs1,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ rate,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ dci_errors[0]);
+ //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; DL_DECOD_ITER; err0; trials0; err1; trials1; err2; trials2; err3; trials3; PE; dci_err;PE;ND;\n");
+ fprintf(time_meas_fd,"%f;%d;%d;%f; %2.1f%%;%f;%f;%u;%u;%u;%u;%u;%u;%u;%u;%e;%e;%e;%e;%u;%u;%e;%f;%f;",
+ SNR,
+ mcs1,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ rate*effective_rate,
+ 100*effective_rate,
+ rate,
+ (double)avg_iter/iter_trials,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ (double)errs[0]/(round_trials[0]),
+ (double)errs[1]/(round_trials[0]),
+ (double)errs[2]/(round_trials[0]),
+ (double)errs[3]/(round_trials[0]),
+ dci_errors[0],
+ round_trials[0],
+ (double)dci_errors[0]/(round_trials[0]),
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/
+ (double)eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0]));
+ } else {
+ fprintf(time_meas_fd,"%f;%d;%d;%d;%d;%f;%u;%u;%u;%u;%u;%u;%u;%u;%u;",
+ SNR,
+ mcs1,mcs2,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ eNB->dlsch[0][1]->harq_processes[0]->TBS,
+ rate,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ dci_errors[0]);
+ //fprintf(time_meas_fd,"SNR; MCS; TBS; rate; DL_DECOD_ITER; err0; trials0; err1; trials1; err2; trials2; err3; trials3; PE; dci_err;PE;ND;\n");
+ fprintf(time_meas_fd,"%f;%d;%d;%d;%d;%f;%2.1f;%f;%f;%u;%u;%u;%u;%u;%u;%u;%u;%e;%e;%e;%e;%u;%u;%e;%f;%f;",
+ SNR,
+ mcs1,mcs2,
+ eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ eNB->dlsch[0][1]->harq_processes[0]->TBS,
+ rate*effective_rate,
+ 100*effective_rate,
+ rate,
+ (double)avg_iter/iter_trials,
+ errs[0],
+ round_trials[0],
+ errs[1],
+ round_trials[1],
+ errs[2],
+ round_trials[2],
+ errs[3],
+ round_trials[3],
+ (double)errs[0]/(round_trials[0]),
+ (double)errs[1]/(round_trials[0]),
+ (double)errs[2]/(round_trials[0]),
+ (double)errs[3]/(round_trials[0]),
+ dci_errors[0],
+ round_trials[0],
+ (double)dci_errors[0]/(round_trials[0]),
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0])/
+ (double)eNB->dlsch[0][0]->harq_processes[0]->TBS,
+ (1.0*(round_trials[0]-errs[0])+2.0*(round_trials[1]-errs[1])+3.0*(round_trials[2]-errs[2])+4.0*(round_trials[3]-errs[3]))/((double)round_trials[0]));
+ }
- printf("errors %u/%u (Pe %e)\n",errs[round],trials,(double)errs[round]/trials);
+ //fprintf(time_meas_fd,"eNB_PROC_TX(%d); OFDM_MOD(%d); DL_MOD(%d); DL_SCR(%d); DL_ENC(%d); UE_PROC_RX(%d); OFDM_DEMOD_CH_EST(%d); RX_PDCCH(%d); CH_COMP_LLR(%d); DL_USCR(%d); DL_DECOD(%d);\n",
+ fprintf(time_meas_fd,"%d; %d; %d; %d; %d; %d; %d; %d; %d; %d; %d;",
+ eNB->phy_proc_tx.trials,
+ eNB->ofdm_mod_stats.trials,
+ eNB->dlsch_modulation_stats.trials,
+ eNB->dlsch_scrambling_stats.trials,
+ eNB->dlsch_encoding_stats.trials,
+ phy_proc_rx_tot.trials,
+ UE->ofdm_demod_stats.trials,
+ UE->dlsch_rx_pdcch_stats.trials,
+ UE->dlsch_llr_stats.trials,
+ UE->dlsch_unscrambling_stats.trials,
+ UE->dlsch_decoding_stats[UE->current_thread_id[subframe]].trials
+ );
+ fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;%f;",
+ get_time_meas_us(&eNB->phy_proc_tx),
+ get_time_meas_us(&eNB->ofdm_mod_stats),
+ get_time_meas_us(&eNB->dlsch_modulation_stats),
+ get_time_meas_us(&eNB->dlsch_scrambling_stats),
+ get_time_meas_us(&eNB->dlsch_encoding_stats),
+ get_time_meas_us(&phy_proc_rx_tot),
+ nsymb*get_time_meas_us(&UE->ofdm_demod_stats),
+ get_time_meas_us(&UE->dlsch_rx_pdcch_stats),
+ 3*get_time_meas_us(&UE->dlsch_llr_stats),
+ get_time_meas_us(&UE->dlsch_unscrambling_stats),
+ get_time_meas_us(&UE->dlsch_decoding_stats[UE->current_thread_id[subframe]])
+ );
+ //fprintf(time_meas_fd,"eNB_PROC_TX_STD;eNB_PROC_TX_MAX;eNB_PROC_TX_MIN;eNB_PROC_TX_MED;eNB_PROC_TX_Q1;eNB_PROC_TX_Q3;eNB_PROC_TX_DROPPED;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%d;",squareRoot(&UE->phy_proc_tx), t_tx_max, t_tx_min, median(table_tx), q1(table_tx), q3(table_tx), n_tx_dropped);
+ //fprintf(time_meas_fd,"IFFT;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;",
+ squareRoot(&eNB->ofdm_mod_stats),
+ median(table_tx_ifft),q1(table_tx_ifft),q3(table_tx_ifft));
+ //fprintf(time_meas_fd,"MOD;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;",
+ squareRoot(&eNB->dlsch_modulation_stats),
+ median(table_tx_mod), q1(table_tx_mod), q3(table_tx_mod));
+ //fprintf(time_meas_fd,"ENC;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;",
+ squareRoot(&eNB->dlsch_encoding_stats),
+ median(table_tx_enc),q1(table_tx_enc),q3(table_tx_enc));
+ //fprintf(time_meas_fd,"eNB_PROC_RX_STD;eNB_PROC_RX_MAX;eNB_PROC_RX_MIN;eNB_PROC_RX_MED;eNB_PROC_RX_Q1;eNB_PROC_RX_Q3;eNB_PROC_RX_DROPPED;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;%f;%f;%d;",
+ squareRoot(&phy_proc_rx_tot), t_rx_max, t_rx_min,
+ median(table_rx), q1(table_rx), q3(table_rx), n_rx_dropped);
+ //fprintf(time_meas_fd,"FFT;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;",
+ squareRoot(&UE->ofdm_demod_stats),
+ median(table_rx_fft), q1(table_rx_fft), q3(table_rx_fft));
+ //fprintf(time_meas_fd,"DEMOD;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f;",
+ squareRoot(&UE->dlsch_demodulation_stats),
+ median(table_rx_demod), q1(table_rx_demod), q3(table_rx_demod));
+ //fprintf(time_meas_fd,"DEC;\n");
+ fprintf(time_meas_fd,"%f;%f;%f;%f\n",
+ squareRoot(&UE->dlsch_decoding_stats[subframe]),
+ median(table_rx_dec), q1(table_rx_dec), q3(table_rx_dec));
+ printf("[passed] effective rate : %f (%2.1f%%,%f)): log and break \n",rate*effective_rate, 100*effective_rate, rate );
+ test_passed = 1;
+ break;
+ } else if (test_perf !=0 ) {
+ printf("[continue] effective rate : %f (%2.1f%%,%f)): increase snr \n",rate*effective_rate, 100*effective_rate, rate);
+ test_passed = 0;
+ }
- if (awgn_flag==0)
- fprintf(fd,"SNR_%d_%d = [SNR_%d_%d %f]; errs_mch_%d_%d =[errs_mch_%d_%d %u]; mch_trials_%d_%d =[mch_trials_%d_%d %u];\n",
- mcs,N_RB_DL,mcs,N_RB_DL,SNR,
- mcs,N_RB_DL,mcs,N_RB_DL,errs[0],
- mcs,N_RB_DL,mcs,N_RB_DL,trials);
- else
- fprintf(fd,"SNR_awgn_%d = [SNR_awgn_%d %f]; errs_mch_awgn_%d =[errs_mch_awgn_%d %u]; mch_trials_awgn_%d =[mch_trials_awgn_%d %u];\n",
- N_RB_DL,N_RB_DL,SNR,
- N_RB_DL,N_RB_DL,errs[0],
- N_RB_DL,N_RB_DL,trials);
+ if (((double)errs[0]/(round_trials[0]))<(10.0/n_frames))
+ break;
+ }// SNR
+ } //ch_realization
- fflush(fd);
+ fclose(bler_fd);
- if (errs[0] == 0)
- break;
- }
+ if (test_perf !=0)
+ fclose (time_meas_fd);
- if (n_frames==1) {
- printf("Dumping PMCH files ( G %d)\n",UE->dlsch_MCH[0]->harq_processes[0]->G);
- dump_mch(UE,0,
- UE->dlsch_MCH[0]->harq_processes[0]->G,
- subframe);
+ //fprintf(tikz_fd,"};\n");
+ //fclose(tikz_fd);
+
+ if (input_trch_file==1)
+ fclose(input_trch_fd);
+
+ if (input_file==1)
+ fclose(input_fd);
+
+ if(abstx) { // ABSTRACTION
+ fprintf(csv_fd,"];");
+ fclose(csv_fd);
}
+ if (uncoded_ber_bit)
+ free(uncoded_ber_bit);
+
+ uncoded_ber_bit = NULL;
printf("Freeing dlsch structures\n");
- free_eNB_dlsch(eNB->dlsch_MCH);
- free_ue_dlsch(UE->dlsch_MCH[0]);
- fclose(fd);
- return(0);
-}
+ for (i=0; i<2; i++) {
+ printf("eNB %d\n",i);
+ free_eNB_dlsch(eNB->dlsch[0][i]);
+ printf("UE %d\n",i);
+ free_ue_dlsch(UE->dlsch[UE->current_thread_id[subframe]][0][i]);
+ }
+
+ if (test_perf && !test_passed)
+ return(-1);
+ else
+ return(0);
+}
+/* temporary dummy implem of get_softmodem_optmask, till basic simulators implemented as device */
+uint64_t get_softmodem_optmask(void) {
+ return 0;
+}
diff --git a/openair1/SIMULATION/NR_PHY/dlschsim.c b/openair1/SIMULATION/NR_PHY/dlschsim.c
index 80b26c0bbde2e7198a9f74ed1c9faebce95e55bf..5e2d42a0f72ad569d56dbbeb841b1ac4e214995c 100644
--- a/openair1/SIMULATION/NR_PHY/dlschsim.c
+++ b/openair1/SIMULATION/NR_PHY/dlschsim.c
@@ -37,10 +37,9 @@
#include "PHY/INIT/phy_init.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "SCHED_NR/sched_nr.h"
#include "openair1/SIMULATION/TOOLS/sim.h"
@@ -66,6 +65,8 @@ PHY_VARS_NR_UE *PHY_vars_UE_g[1][1] = { { NULL } };
uint16_t n_rnti = 0x1234;
openair0_config_t openair0_cfg[MAX_CARDS];
+void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {}
+
int main(int argc, char **argv)
{
char c;
@@ -428,7 +429,7 @@ int main(int argc, char **argv)
uint8_t is_crnti = 0, llr8_flag = 0;
unsigned int TBS = 8424;
unsigned int available_bits;
- uint8_t nb_re_dmrs = 6;
+ uint8_t nb_re_dmrs = 6; // No data in dmrs symbol
uint16_t length_dmrs = 1;
unsigned char mod_order;
uint16_t rate;
@@ -442,7 +443,7 @@ int main(int argc, char **argv)
mod_order = nr_get_Qm_dl(Imcs, mcs_table);
rate = nr_get_code_rate_dl(Imcs, mcs_table);
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
- TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl);
+ TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl);
printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order);
//dlsch->harq_ids[subframe]= 0;
rel15->rbSize = nb_rb;
@@ -455,6 +456,7 @@ int main(int argc, char **argv)
rel15->dmrsConfigType = NFAPI_NR_DMRS_TYPE1;
rel15->dlDmrsSymbPos = 4;
rel15->mcsIndex[0] = Imcs;
+ rel15->numDmrsCdmGrpsNoData = 1;
double *modulated_input = malloc16(sizeof(double) * 16 * 68 * 384); // [hna] 16 segments, 68*Zc
short *channel_output_fixed = malloc16(sizeof(short) * 16 * 68 * 384);
short *channel_output_uncoded = malloc16(sizeof(unsigned short) * 16 * 68 * 384);
@@ -475,8 +477,9 @@ int main(int argc, char **argv)
harq_process->Qm = mod_order;
harq_process->rvidx = rvidx;
harq_process->R = rate;
- harq_process->dmrsConfigType = 1;
+ harq_process->dmrsConfigType = NFAPI_NR_DMRS_TYPE1;
harq_process->dlDmrsSymbPos = 4;
+ harq_process->n_dmrs_cdm_groups = 1;
printf("harq process ue mcs = %d Qm = %d, symb %d\n", harq_process->mcs, harq_process->Qm, nb_symb_sch);
unsigned char *test_input;
test_input = (unsigned char *) malloc16(sizeof(unsigned char) * TBS / 8);
diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c
index 7982937e6d52d025157cbdfd60b1d0162e034dcb..64ab482db894faef45b7637b5ae70e0277a970de 100644
--- a/openair1/SIMULATION/NR_PHY/dlsim.c
+++ b/openair1/SIMULATION/NR_PHY/dlsim.c
@@ -28,11 +28,9 @@
#include "common/ran_context.h"
#include "common/config/config_userapi.h"
#include "common/utils/LOG/log.h"
-#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
-#include "openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
-#include "openair2/LAYER2/NR_MAC_UE/mac_defs.h"
-#include "openair2/LAYER2/NR_MAC_UE/mac_extern.h"
-#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h"
+#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
+#include "LAYER2/NR_MAC_UE/mac_defs.h"
+#include "LAYER2/NR_MAC_UE/mac_extern.h"
#include "PHY/defs_gNB.h"
#include "PHY/defs_nr_common.h"
#include "PHY/defs_nr_UE.h"
@@ -41,9 +39,8 @@
#include "PHY/INIT/phy_init.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "SCHED_NR/fapi_nr_l1.h"
#include "SCHED_NR/sched_nr.h"
@@ -55,7 +52,7 @@
#include "LAYER2/NR_MAC_UE/mac_proto.h"
//#include "LAYER2/NR_MAC_gNB/mac_proto.h"
//#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h"
-#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "NR_asn_constant.h"
#include "RRC/NR/MESSAGES/asn1_msg.h"
#include "openair1/SIMULATION/RF/rf.h"
@@ -139,6 +136,12 @@ int main(int argc, char **argv)
int i,aa;//,l;
double sigma2, sigma2_dB=10, SNR, snr0=-2.0, snr1=2.0;
uint8_t snr1set=0;
+ float roundStats[50];
+ float effRate;
+ //float psnr;
+ float eff_tp_check = 0.7;
+ uint8_t snrRun;
+ uint32_t TBS;
int **txdata;
double **s_re,**s_im,**r_re,**r_im;
//double iqim = 0.0;
@@ -154,6 +157,8 @@ int main(int argc, char **argv)
int trial, n_trials = 1, n_errors = 0, n_false_positive = 0;
//int n_errors2, n_alamouti;
uint8_t transmission_mode = 1,n_tx=1,n_rx=1;
+ uint8_t round;
+ uint8_t num_rounds = 4;
channel_desc_t *gNB2UE;
//uint32_t nsymb,tx_lev,tx_lev1 = 0,tx_lev2 = 0;
@@ -171,6 +176,7 @@ int main(int argc, char **argv)
//int pbch_tx_ant;
int N_RB_DL=106,mu=1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t dlsch_config;
+ NR_sched_pucch pucch_sched;
//unsigned char frame_type = 0;
@@ -204,7 +210,7 @@ int main(int argc, char **argv)
FILE *scg_fd=NULL;
- while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:")) != -1) {
+ while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:w")) != -1) {
switch (c) {
case 'f':
scg_fd = fopen(optarg,"r");
@@ -383,6 +389,14 @@ int main(int argc, char **argv)
mu = atoi(optarg);
break;
+ case 't':
+ eff_tp_check = (float)atoi(optarg)/100;
+ break;
+
+ case 'w':
+ output_fd = fopen("txdata.dat", "w+");
+ break;
+
default:
case 'h':
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n",
@@ -412,7 +426,9 @@ int main(int argc, char **argv)
printf("-c Start symbol for PDSCH (fixed for now)\n");
printf("-j Number of symbols for PDSCH (fixed for now)\n");
printf("-e MSC index\n");
+ printf("-t Acceptable effective throughput (in percentage)\n");
printf("-P Print DLSCH performances\n");
+ printf("-w Write txdata to binary file (one frame)\n");
exit (-1);
break;
}
@@ -657,7 +673,7 @@ int main(int argc, char **argv)
rrc.carrier.MIB = (uint8_t*) malloc(4);
rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0);
- nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig);
+ nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup);
nr_dcireq_t dcireq;
@@ -678,6 +694,9 @@ int main(int argc, char **argv)
nr_ue_phy_config_request(&UE_mac->phy_config);
+ NR_UE_list_t *UE_list = &RC.nrmac[0]->UE_list;
+ //NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels;
+ snrRun = 0;
for (SNR = snr0; SNR < snr1; SNR += .2) {
@@ -695,6 +714,7 @@ int main(int argc, char **argv)
reset_meas(&gNB->toutput);
n_errors = 0;
+ effRate = 0;
//n_errors2 = 0;
//n_alamouti = 0;
errors_scrambling=0;
@@ -705,94 +725,6 @@ int main(int argc, char **argv)
//multipath channel
//multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0);
- memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
- clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
- if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config);
- else nr_schedule_css_dlsch_phytest(0,frame,slot);
-
-
- Sched_INFO.module_id = 0;
- Sched_INFO.CC_id = 0;
- Sched_INFO.frame = frame;
- Sched_INFO.slot = slot;
- Sched_INFO.DL_req = &gNB_mac->DL_req[0];
- Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
- Sched_INFO.UL_dci_req = NULL;
- Sched_INFO.TX_req = &gNB_mac->TX_req[0];
- nr_schedule_response(&Sched_INFO);
-
- if (run_initial_sync)
- nr_common_signal_procedures(gNB,frame,slot);
- else
- phy_procedures_gNB_TX(gNB,frame,slot,0);
-
- int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
-
- if (n_trials==1) {
- LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
- if (gNB->frame_parms.nb_antennas_tx>1)
- LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
- }
- int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
- if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
-
- //TODO: loop over slots
- for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
-
- if (cyclic_prefix_type == 1) {
- PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
- &txdata[aa][tx_offset],
- frame_parms->ofdm_symbol_size,
- 12,
- frame_parms->nb_prefix_samples,
- CYCLIC_PREFIX);
- } else {
- nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
- &txdata[aa][tx_offset],
- 14,
- frame_parms);
- }
- }
-
- if (n_trials==1) {
- LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
- if (gNB->frame_parms.nb_antennas_tx>1)
- LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
- }
- if (output_fd)
- fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
-
- int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
- frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
-
- // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev));
-
- for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0));
- i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0));
- i++) {
- for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
- r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
- r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
- }
- }
-
- NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
- nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15;
-
- //AWGN
- sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize))) - SNR;
- sigma2 = pow(10, sigma2_dB/10);
- if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15.rbSize));
-
- for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
- i<frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0);
- i++) {
- for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
- ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
- ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
- }
- }
-
UE->rx_offset=0;
UE_proc.frame_rx = frame;
UE_proc.nr_tti_rx= slot;
@@ -800,43 +732,147 @@ int main(int argc, char **argv)
dcireq.frame = frame;
dcireq.slot = slot;
+
+ NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
+
+ int harq_pid = slot;
+ NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
+
+ NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
+ nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[slot]->pdsch_pdu.pdsch_pdu_rel15;
- nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
- nr_ue_scheduled_response(&scheduled_response);
-
- phy_procedures_nrUE_RX(UE,
- &UE_proc,
- 0,
- do_pdcch_flag,
- normal_txrx);
+ UE_harq_process->harq_ack.ack = 0;
+ round = 0;
+ UE_harq_process->round = round;
+ UE_harq_process->first_tx = 1;
+
+ while ((round<num_rounds) && (UE_harq_process->harq_ack.ack==0)) {
+ memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
+ memset(RC.nrmac[0]->cce_list[1][1],0,MAX_NUM_CCE*sizeof(int));
+ clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
+
+ UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1);
+
+ UE_list->UE_sched_ctrl[0].harq_processes[harq_pid].round = round;
+ UE_list->UE_sched_ctrl[0].current_harq_pid = harq_pid;
+ gNB->dlsch[0][0]->harq_processes[harq_pid]->round = round;
- if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
- UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
- n_errors++;
+ if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config);
+ else nr_schedule_css_dlsch_phytest(0,frame,slot);
+ Sched_INFO.module_id = 0;
+ Sched_INFO.CC_id = 0;
+ Sched_INFO.frame = frame;
+ Sched_INFO.slot = slot;
+ Sched_INFO.DL_req = &gNB_mac->DL_req[0];
+ Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
+ Sched_INFO.UL_dci_req = NULL;
+ Sched_INFO.TX_req = &gNB_mac->TX_req[0];
+ nr_schedule_response(&Sched_INFO);
+
+ if (run_initial_sync)
+ nr_common_signal_procedures(gNB,frame,slot);
+ else
+ phy_procedures_gNB_TX(gNB,frame,slot,0);
+
+ int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
+
+ if (n_trials==1) {
+ LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
+ if (gNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
+ }
+ int tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
+ if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
+
+ //TODO: loop over slots
+ for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
+
+ if (cyclic_prefix_type == 1) {
+ PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
+ &txdata[aa][tx_offset],
+ frame_parms->ofdm_symbol_size,
+ 12,
+ frame_parms->nb_prefix_samples,
+ CYCLIC_PREFIX);
+ } else {
+ nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
+ &txdata[aa][tx_offset],
+ 14,
+ frame_parms);
+ }
+ }
+
+ if (n_trials==1) {
+ LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
+ if (gNB->frame_parms.nb_antennas_tx>1)
+ LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
+ }
+ if (output_fd) {
+ printf("writing txdata to binary file\n");
+ fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
+ }
+
+ int txlev = signal_energy(&txdata[0][frame_parms->get_samples_slot_timestamp(slot,frame_parms,0)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0], frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
+
+ // if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev));
+
+ for (i=(frame_parms->get_samples_slot_timestamp(slot,frame_parms,0));
+ i<(frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0));
+ i++) {
+
+ for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
+ r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
+ r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
+ }
+ }
+
+ //AWGN
+ sigma2_dB = 10 * log10((double)txlev * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize))) - SNR;
+ sigma2 = pow(10, sigma2_dB/10);
+ if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize));
+
+ for (i=frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
+ i<frame_parms->get_samples_slot_timestamp(slot+1,frame_parms,0);
+ i++) {
+
+ for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
+ ((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
+ ((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
+ }
+ }
+
+ nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
+ nr_ue_scheduled_response(&scheduled_response);
+
+ phy_procedures_nrUE_RX(UE,
+ &UE_proc,
+ 0,
+ do_pdcch_flag,
+ normal_txrx);
+
+ //printf("dlsim round %d ends\n",round);
+ round++;
+ } // round
//----------------------------------------------------------
//---------------------- count errors ----------------------
//----------------------------------------------------------
-
-
- NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
-
- int harq_pid = dlsch0->current_harq_pid;
- NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
-
+ if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
+ UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
+ n_errors++;
+
NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]];
int16_t *UE_llr = pdsch_vars[0]->llr[0];
-
- uint32_t TBS = rel15.TBSize[0];
+ TBS = UE_harq_process->TBS;//rel15->TBSize[0];
uint16_t length_dmrs = 1;
- uint16_t nb_rb = rel15.rbSize;
- uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4;
- uint8_t mod_order = rel15.qamModOrder[0];
- uint8_t nb_symb_sch = rel15.NrOfSymbols;
+ uint16_t nb_rb = rel15->rbSize;
+ uint8_t nb_re_dmrs = rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4;
+ uint8_t mod_order = rel15->qamModOrder[0];
+ uint8_t nb_symb_sch = rel15->NrOfSymbols;
- available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers);
+ available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15->nrOfLayers);
for (i = 0; i < available_bits; i++) {
@@ -868,7 +904,7 @@ int main(int argc, char **argv)
if (errors_scrambling > 0) {
if (n_trials == 1)
- printf("errors_scrambling = %d/%d (trial %d)\n", errors_scrambling, available_bits,trial);
+ printf("errors_scrambling = %u/%u (trial %d)\n", errors_scrambling, available_bits,trial);
}
if (errors_bit > 0) {
@@ -876,32 +912,20 @@ int main(int argc, char **argv)
if (n_trials == 1)
printf("errors_bit = %u (trial %d)\n", errors_bit, trial);
}
-
+ roundStats[snrRun]+=((float)round);
+ if (UE_harq_process->harq_ack.ack==1) effRate += ((float)TBS)/round;
} // noise trials
+ roundStats[snrRun]/=((float)n_trials);
+ effRate /= n_trials;
printf("*****************************************\n");
printf("SNR %f, (false positive %f)\n", SNR,
(float) n_errors / (float) n_trials);
printf("*****************************************\n");
printf("\n");
- printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials);
+ printf("SNR %f : n_errors (negative CRC) = %d/%d, Avg round %.2f, Channel BER %e, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %d bits/slot\n", SNR, n_errors, n_trials,roundStats[snrRun],(double)errors_scrambling/available_bits/n_trials,effRate,effRate/TBS*100,TBS);
printf("\n");
- if (n_trials == 1) {
-
- LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
- if (UE->frame_parms.nb_antennas_rx>1)
- LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
- LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1);
- write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1);
- break;
- }
-
- if ((float)n_errors/(float)n_trials <= target_error_rate) {
- printf("PDSCH test OK\n");
- break;
- }
-
if (print_perf==1) {
printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n",
1000>>*scc->ssbSubcarrierSpacing,dlsch_config.rbSize,dlsch_config.mcsIndex[0],
@@ -952,8 +976,35 @@ int main(int argc, char **argv)
printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
*/
}
+
+ if (n_trials == 1) {
+
+ LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
+ if (UE->frame_parms.nb_antennas_rx>1)
+ LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
+ LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1);
+ write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1);
+ break;
+ }
+
+ //if ((float)n_errors/(float)n_trials <= target_error_rate) {
+ if (effRate >= (eff_tp_check*TBS)) {
+ printf("PDSCH test OK\n");
+ break;
+ }
+
+ snrRun++;
} // NSR
+ /*if (n_trials>1) {
+ printf("HARQ stats:\nSNR\tRounds\n");
+ psnr = snr0;
+ for (uint8_t i=0; i<snrRun; i++) {
+ printf("%.1f\t%.2f\n",psnr,roundStats[i]);
+ psnr+=0.2;
+ }
+ }*/
+
for (i = 0; i < 2; i++) {
free(s_re[i]);
free(s_im[i]);
@@ -976,6 +1027,8 @@ int main(int argc, char **argv)
if (input_fd)
fclose(input_fd);
+ if (scg_fd)
+ fclose(scg_fd);
return(n_errors);
}
diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c
index c9253aeedf577d8d4a552ea3c2401769eedc00a2..c7ee863c3562e4fcb30bc766ef8f35638ea51bab 100644
--- a/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c
+++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions.c
@@ -1,7 +1,7 @@
int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { return(0); }
int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); }
int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); }
-int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); }
+//int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); }
//int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); }
int32_t get_uldl_offset(int nr_bandP) { return(0); }
NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);}
diff --git a/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c
new file mode 100644
index 0000000000000000000000000000000000000000..bfb9150868da49fb40a79d0dc42d6a6211ca7248
--- /dev/null
+++ b/openair1/SIMULATION/NR_PHY/nr_dummy_functions_prach.c
@@ -0,0 +1,348 @@
+int oai_nfapi_hi_dci0_req(nfapi_hi_dci0_request_t *hi_dci0_req) { return(0); }
+int oai_nfapi_tx_req(nfapi_tx_request_t *tx_req) { return(0); }
+int oai_nfapi_dl_config_req(nfapi_dl_config_request_t *dl_config_req) { return(0); }
+int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); }
+//int oai_nfapi_nr_dl_config_req(nfapi_nr_dl_config_request_t *dl_config_req) { return(0); }
+int32_t get_uldl_offset(int nr_bandP) { return(0); }
+NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {return(NULL);}
+int dummy_nr_ue_dl_indication(nr_downlink_indication_t *dl_info) { return(0); }
+int dummy_nr_ue_ul_indication(nr_uplink_indication_t *ul_info) { return(0); }
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file ra_procedures.c
+ * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15)
+ * \author R. Knopp, Navid Nikaein, Guido Casati
+ * \date 2019
+ * \version 0.1
+ * \company Eurecom
+ * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de
+ * \note
+ * \warning
+ */
+
+
+/*
+#include "common/utils/LOG/vcd_signal_dumper.h"
+#include "PHY_INTERFACE/phy_interface_extern.h"
+#include "SCHED_UE/sched_UE.h"
+#include "COMMON/mac_rrc_primitives.h"
+#include "RRC/LTE/rrc_extern.h"
+#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h"
+#include "common/utils/LOG/log.h"
+#include "UTIL/OPT/opt.h"
+#include "OCG.h"
+#include "OCG_extern.h"
+#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/
+
+/* Tools */
+#include "SIMULATION/TOOLS/sim.h" // for taus
+
+/* RRC */
+#include "NR_RACH-ConfigCommon.h"
+
+/* PHY */
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
+#include "PHY/defs_common.h"
+#include "PHY/defs_nr_common.h"
+#include "PHY/NR_UE_ESTIMATION/nr_estimation.h"
+
+/* MAC */
+#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_COMMON/nr_mac.h"
+#include "LAYER2/NR_MAC_UE/mac_proto.h"
+#include "LAYER2/MAC/mac.h"
+
+extern int64_t table_6_3_3_2_2_prachConfig_Index [256][9];
+extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9];
+
+//extern uint8_t nfapi_mode;
+
+// WIP
+// This routine implements Section 5.1.2 (UE Random Access Resource Selection)
+// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321
+void nr_get_prach_resources(module_id_t mod_id,
+ int CC_id,
+ uint8_t gNB_id,
+ uint8_t t_id,
+ uint8_t first_Msg3,
+ NR_PRACH_RESOURCES_t *prach_resources,
+ NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon;
+ // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
+
+ int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0;
+ uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, msg1_FDM, prach_ConfigIndex, SFN_nbr, Msg3_size;
+
+ // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo
+
+ ///////////////////////////////////////////////////////////
+ //////////* UE Random Access Resource Selection *//////////
+ ///////////////////////////////////////////////////////////
+
+ // todo:
+ // - switch initialisation cases
+ // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321)
+ // --- SSB selection, set prach_resources->ra_PreambleIndex
+ // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000
+ // --- set PREAMBLE_INDEX to ra_preamble_index
+ // --- select the SSB signalled by PDCCH
+ // -- RA initiated for SI request:
+ // --- SSB selection, set prach_resources->ra_PreambleIndex
+
+ // if (rach_ConfigDedicated) { // This is for network controlled Mobility
+ // // operation for contention-free RA resources when:
+ // // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection
+ // // - availalbe CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection
+ // prach_resources->ra_PreambleIndex = rach_ConfigDedicated->ra_PreambleIndex;
+ // return;
+ // }
+
+ //////////* Contention-based RA preamble selection *//////////
+ // todo:
+ // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB
+ // - todo determine next available PRACH occasion
+
+ // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB;
+
+ AssertFatal(mac->nr_rach_ConfigCommon != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id);
+
+ nr_rach_ConfigCommon = mac->nr_rach_ConfigCommon;
+
+ Msg3_size = mac->RA_Msg3_size;
+ numberOfRA_Preambles = *nr_rach_ConfigCommon->totalNumberOfRA_Preambles;
+
+ if (!nr_rach_ConfigCommon->groupBconfigured) {
+ noGroupB = 1;
+ } else {
+ // RA preambles group B is configured
+ // - Defining the number of RA preambles in RA Preamble Group A for each SSB */
+ sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA;
+ switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){
+ /* - Threshold to determine the groups of RA preambles */
+ case 0:
+ messageSizeGroupA = 56;
+ break;
+ case 1:
+ messageSizeGroupA = 144;
+ break;
+ case 2:
+ messageSizeGroupA = 208;
+ break;
+ case 3:
+ messageSizeGroupA = 256;
+ break;
+ case 4:
+ messageSizeGroupA = 282;
+ break;
+ case 5:
+ messageSizeGroupA = 480;
+ break;
+ case 6:
+ messageSizeGroupA = 640;
+ break;
+ case 7:
+ messageSizeGroupA = 800;
+ break;
+ case 8:
+ messageSizeGroupA = 1000;
+ break;
+ case 9:
+ messageSizeGroupA = 72;
+ break;
+ default:
+ AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA);
+ /* todo cases 10 -15*/
+ }
+
+ /* Power offset for preamble selection in dB */
+ messagePowerOffsetGroupB = -9999;
+ switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){
+ case 0:
+ messagePowerOffsetGroupB = -9999;
+ break;
+ case 1:
+ messagePowerOffsetGroupB = 0;
+ break;
+ case 2:
+ messagePowerOffsetGroupB = 5;
+ break;
+ case 3:
+ messagePowerOffsetGroupB = 8;
+ break;
+ case 4:
+ messagePowerOffsetGroupB = 10;
+ break;
+ case 5:
+ messagePowerOffsetGroupB = 12;
+ break;
+ case 6:
+ messagePowerOffsetGroupB = 15;
+ break;
+ case 7:
+ messagePowerOffsetGroupB = 18;
+ break;
+ default:
+ AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB);
+ }
+
+ // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0
+ mac->deltaPreamble_Msg3 = 0;
+ deltaPreamble_Msg3 = mac->deltaPreamble_Msg3;
+ }
+
+ PLThreshold = prach_resources->RA_PCMAX - nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB;
+
+ /* Msg3 has not been transmitted yet */
+ if (first_Msg3 == 1) {
+ if (noGroupB == 1) {
+ // use Group A preamble
+ prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles;
+ mac->RA_usedGroupA = 1;
+ } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) {
+ // Group B is configured and RA preamble Group A is used
+ // - todo add condition on CCCH_sdu_size for initiation by CCCH
+ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA;
+ mac->RA_usedGroupA = 1;
+ } else {
+ // Group B preamble is configured and used
+ // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A
+ // the remaining belong to RA Preambles Group B
+ prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA);
+ mac->RA_usedGroupA = 0;
+ }
+ } else { // Msg3 is being retransmitted
+ if (mac->RA_usedGroupA == 1 && noGroupB == 1) {
+ prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles;
+ } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){
+ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA;
+ } else {
+ prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA);
+ }
+ }
+
+ // todo determine next available PRACH occasion
+ // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured
+ // - else if SSB is selected above
+ // - else if CSI-RS is selected above
+
+ /////////////////////////////////////////////////////////////////////////////
+ //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *//////////
+ /////////////////////////////////////////////////////////////////////////////
+ // todo:
+ // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321)
+ // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission
+ // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded)
+
+ if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1)
+ mac->RA_PREAMBLE_TRANSMISSION_COUNTER++;
+
+ prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id);
+
+ // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted)
+ // 1) this does not apply to contention-free RA Preamble for beam failure recovery request
+ // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario)
+
+ switch (nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM){ // todo this is not used
+ case 0:
+ msg1_FDM = 1;
+ break;
+ case 1:
+ msg1_FDM = 2;
+ break;
+ case 2:
+ msg1_FDM = 4;
+ break;
+ case 3:
+ msg1_FDM = 8;
+ break;
+ default:
+ AssertFatal(1 == 0,"Unknown msg1_FDM %lu\n", nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FDM);
+ }
+
+ prach_ConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex;
+
+ // ra_RNTI computation
+ // - todo: this is for TDD FR1 only
+ // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier
+ // - f_id: index of the PRACH occasion in the frequency domain
+ // - s_id is starting symbol of the PRACH occasion [0...14]
+ // - t_id is the first slot of the PRACH occasion in a system frame [0...80]
+
+ ul_carrier_id = 0; // NUL
+ f_id = nr_rach_ConfigCommon->rach_ConfigGeneric.msg1_FrequencyStart;
+ SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4];
+ s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5];
+
+ // Pick the first slot of the PRACH occasion in a system frame
+ for (i = 0; i < 10; i++){
+ if (((SFN_nbr & (1 << i)) >> i) == 1){
+ t_id = 2*i;
+ break;
+ }
+ }
+ prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id;
+ mac->ra_rnti = prach_resources->ra_RNTI;
+
+ LOG_D(MAC, "Computed ra_RNTI is %d", prach_resources->ra_RNTI);
+}
+
+// TbD: RA_attempt_number not used
+void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
+ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ mac->ra_state = WAIT_RAR;
+ // Start contention resolution timer
+ mac->RA_attempt_number++;
+}
+
+void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
+ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
+ LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP);
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ // start contention resolution timer
+ mac->RA_contention_resolution_cnt = 0;
+ mac->RA_contention_resolution_timer_active = 1;
+}
+
+/////////////////////////////////////////////////////////////////////////
+///////* Random Access Preamble Initialization (5.1.1 TS 38.321) *///////
+/////////////////////////////////////////////////////////////////////////
+/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300)
+/// Only one RA procedure is ongoing at any point in time in a MAC entity
+/// the RA procedure on a SCell shall only be initiated by PDCCH order
+
+// WIP
+// todo TS 38.321:
+// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX
+// - BWP operation (subclause 5.15 TS 38.321)
+// - handle initialization by beam failure recovery
+// - handle initialization by handover
+// - handle transmission on DCCH using PRACH (during handover, or sending SR for example)
+// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader)
+// - fix rrc data req logic
+// - retrieve TBS
+// - add mac_rrc_nr_data_req_ue, etc ...
+// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator)
+
+
diff --git a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h
index c7a30f826e7039ef8a0987eadb98a987ca323c35..7a465e0ea3335249baef979b92136a00c2365f24 100644
--- a/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h
+++ b/openair1/SIMULATION/NR_PHY/nr_unitary_defs.h
@@ -55,6 +55,24 @@ signed char quantize(double D, double x, unsigned char B) {
return ((char) qxd);
}
+
+int8_t
+mac_rrc_data_req_ue(
+ const module_id_t Mod_idP,
+ const int CC_id,
+ const frame_t frameP,
+ const rb_id_t Srb_id,
+ const uint8_t Nb_tb,
+ uint8_t *const buffer_pP,
+ const mac_enb_index_t eNB_indexP,
+ const uint8_t mbsfn_sync_area
+ ) { return(0);}
+
+int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);}
+//NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);}
+int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); }
+
+
void fill_scc(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_RB_DL,int N_RB_UL,int mu_dl,int mu_ul) {
*scc->physCellId=0; \
diff --git a/openair1/SIMULATION/NR_PHY/pbchsim.c b/openair1/SIMULATION/NR_PHY/pbchsim.c
index 99ca466fee46e8be6b0396d8d2123ccd8db458e3..8c37024858408eac29cc897d662f3af267d5b436 100644
--- a/openair1/SIMULATION/NR_PHY/pbchsim.c
+++ b/openair1/SIMULATION/NR_PHY/pbchsim.c
@@ -33,11 +33,10 @@
#include "PHY/defs_nr_UE.h"
#include "PHY/defs_gNB.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
#include "PHY/INIT/phy_init.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "PHY/NR_UE_ESTIMATION/nr_estimation.h"
#include "PHY/phy_vars.h"
@@ -62,6 +61,8 @@ uint16_t NB_UE_INST = 1;
openair0_config_t openair0_cfg[MAX_CARDS];
uint64_t get_softmodem_optmask(void) {return 0;}
+void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {}
+
void nr_phy_config_request_sim_pbchsim(PHY_VARS_gNB *gNB,
int N_RB_DL,
int N_RB_UL,
@@ -410,7 +411,7 @@ int main(int argc, char **argv)
uint8_t n_hf = 0;
int cyclic_prefix_type = NFAPI_CP_NORMAL;
- double fs, eps;
+ double fs=0, eps;
double scs = 30000;
double bw = 100e6;
diff --git a/openair1/SIMULATION/NR_PHY/prachsim.c b/openair1/SIMULATION/NR_PHY/prachsim.c
index 5c0035251582d571d541de339af5117373b376c5..950f9a67f665a0c548e56650af71889dea70dfd0 100644
--- a/openair1/SIMULATION/NR_PHY/prachsim.c
+++ b/openair1/SIMULATION/NR_PHY/prachsim.c
@@ -22,6 +22,7 @@
#include <string.h>
#include <math.h>
#include <unistd.h>
+#include <pthread.h>
#include "common/config/config_userapi.h"
#include "common/utils/LOG/log.h"
@@ -35,107 +36,82 @@
#include "SCHED_NR/sched_nr.h"
#include "SCHED_NR_UE/phy_frame_config_nr.h"
#include "PHY/phy_vars_nr_ue.h"
-
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
#include "PHY/INIT/phy_init.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
+#include "nr_unitary_defs.h"
#include "OCG_vars.h"
-#include <pthread.h>
+#define NR_PRACH_DEBUG 1
+#define PRACH_WRITE_OUTPUT_DEBUG 1
PHY_VARS_gNB *gNB;
PHY_VARS_NR_UE *UE;
RAN_CONTEXT_t RC;
RU_t *ru;
-
double cpuf;
-
extern uint16_t prach_root_sequence_map0_3[838];
-
-void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
-
uint16_t NB_UE_INST=1;
-volatile int oai_exit=0;
-
-void exit_function(const char* file, const char* function, const int line,const char *s) {
- const char * msg= s==NULL ? "no comment": s;
- printf("Exiting at: %s:%d %s(), %s\n", file, line, function, msg);
- exit(-1);
-}
+openair0_config_t openair0_cfg[MAX_CARDS];
+uint8_t nfapi_mode=0;
+int sl_ahead = 0;
+//void dump_nr_prach_config(NR_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
-int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe) {
- AssertFatal(1==0,"Shouldn't be here ...\n");
- return 0;
-}
+/* temporary dummy implem of get_softmodem_optmask, till basic simulators implemented as device */
+uint64_t get_softmodem_optmask(void) {return 0;}
+softmodem_params_t *get_softmodem_params(void) {return 0;}
-uint8_t nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
- sub_frame_t subframe, uint8_t eNB_index,
- uint8_t *ulsch_buffer, uint16_t buflen, uint8_t *access_mode) {return(0);}
+void pdcp_run (const protocol_ctxt_t *const ctxt_pP) { return;}
-int oai_nfapi_rach_ind(nfapi_rach_indication_t *rach_ind) {return(0);}
+boolean_t pdcp_data_ind(const protocol_ctxt_t *const ctxt_pP,
+ const srb_flag_t srb_flagP,
+ const MBMS_flag_t MBMS_flagP,
+ const rb_id_t rb_idP,
+ const sdu_size_t sdu_buffer_sizeP,
+ mem_block_t *const sdu_buffer_pP) {return(false);}
-openair0_config_t openair0_cfg[MAX_CARDS];
-uint8_t nfapi_mode=0;
-NR_IF_Module_t *NR_IF_Module_init(int Mod_id){return(NULL);}
-int oai_nfapi_ul_config_req(nfapi_ul_config_request_t *ul_config_req) { return(0); }
+void nr_ip_over_LTE_DRB_preconfiguration(void){}
+void pdcp_layer_init(void) {}
+int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const int8_t channel, const uint8_t* pduP, const sdu_size_t pdu_len) {return 0;}
-uint64_t get_softmodem_optmask(void) {
- return 0;
-}
-
-int main(int argc, char **argv)
-{
+int main(int argc, char **argv){
char c;
- int i,aa,aarx;
- double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0,ue_speed0=0.0,ue_speed1=0.0;
- uint8_t snr1set=0;
- uint8_t ue_speed1set=0;
- int **txdata;
- double **s_re,**s_im,**r_re,**r_im;
- double iqim=0.0;
- int trial; //, ntrials=1;
- uint8_t transmission_mode = 1,n_tx=1,n_rx=1;
- uint16_t Nid_cell=0;
-
- uint8_t awgn_flag=0;
- uint8_t hs_flag=0;
- int n_frames=1;
- channel_desc_t *UE2gNB;
- uint32_t nsymb,tx_lev; //,tx_lev_dB;
- // int8_t interf1=-19,interf2=-19;
- NR_DL_FRAME_PARMS *frame_parms;
-
- SCM_t channel_model=Rayleigh1;
+ double sigma2, sigma2_dB = 0, SNR, snr0 = -2.0, snr1 = 0.0, ue_speed0 = 0.0, ue_speed1 = 0.0;
+ double **s_re, **s_im, **r_re, **r_im, iqim = 0.0, delay_avg = 0, ue_speed = 0, fs, bw;
+ int i, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1;
+ int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0;
+ uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format=0;
+ uint8_t frame = 1, subframe = 9, slot=19, slot_gNB=19, config_index = 98, prach_sequence_length = 1, num_root_sequences = 16, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol;
+ uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1;
+ uint32_t tx_lev = 10000, prach_errors = 0, samp_count; //,tx_lev_dB;
+ uint64_t SSB_positions = 0x01, absoluteFrequencyPointA = 640000;
+ // int8_t interf1=-19,interf2=-19;
// uint8_t abstraction_flag=0,calibration_flag=0;
// double prach_sinr;
- int N_RB_UL=273;
- uint32_t prach_errors=0;
- uint8_t subframe=9;
- uint16_t preamble_energy_list[64],preamble_tx=50,preamble_delay_list[64];
- uint16_t preamble_max,preamble_energy_max;
- PRACH_RESOURCES_t prach_resources;
- //uint8_t prach_fmt;
- //int N_ZC;
- int delay = 0;
- double delay_avg=0;
- double ue_speed = 0;
- int NCS_config = 13,rootSequenceIndex=0;
- int threequarter_fs = 0;
- int mu=1;
- uint64_t SSB_positions=0x01;
-
- int loglvl=OAILOG_INFO;
+ // uint32_t nsymb;
+ // uint16_t preamble_max, preamble_energy_max;
+ FILE *input_fd=NULL;
+ char* input_file=NULL;
+ int n_bytes=0;
- cpuf = get_cpu_freq_GHz();
+ NR_DL_FRAME_PARMS *frame_parms;
+ NR_PRACH_RESOURCES_t prach_resources;
+ nfapi_nr_prach_config_t *prach_config;
+ nfapi_nr_prach_pdu_t *prach_pdu;
+ fapi_nr_prach_config_t *ue_prach_config;
+ fapi_nr_ul_config_prach_pdu *ue_prach_pdu;
+ channel_desc_t *UE2gNB;
+ SCM_t channel_model = Rayleigh1;
+ cpuf = get_cpu_freq_GHz();
if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) {
exit_fun("[SOFTMODEM] Error, configuration module init failed\n");
@@ -143,8 +119,7 @@ int main(int argc, char **argv)
randominit(0);
-
- while ((c = getopt (argc, argv, "hHaA:Cr:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) {
+ while ((c = getopt (argc, argv, "hHaA:Cc:r:p:g:n:s:S:t:x:y:v:V:z:N:F:d:Z:L:R:E")) != -1) {
switch (c) {
case 'a':
printf("Running AWGN simulation\n");
@@ -153,6 +128,14 @@ int main(int argc, char **argv)
//ntrials=1;
break;
+ case 'c':
+ config_index = atoi(optarg);
+ break;
+
+ case 'r':
+ msg1_frequencystart = atoi(optarg);
+ break;
+
case 'd':
delay = atoi(optarg);
break;
@@ -189,28 +172,34 @@ int main(int argc, char **argv)
case 'H':
channel_model=Rayleigh8;
+ break;
case 'I':
channel_model=Rayleigh1;
+ break;
case 'J':
channel_model=Rayleigh1_corr;
+ break;
case 'K':
channel_model=Rayleigh1_anticorr;
+ break;
case 'L':
channel_model=Rice8;
+ break;
case 'M':
channel_model=Rice1;
+ break;
case 'N':
channel_model=Rayleigh1_800;
break;
default:
- msg("Unsupported channel model!\n");
+ printf("Unsupported channel model!\n");
exit(-1);
}
@@ -226,13 +215,13 @@ int main(int argc, char **argv)
case 's':
snr0 = atof(optarg);
- msg("Setting SNR0 to %f\n",snr0);
+ printf("Setting SNR0 to %f\n",snr0);
break;
case 'S':
snr1 = atof(optarg);
snr1set=1;
- msg("Setting SNR1 to %f\n",snr1);
+ printf("Setting SNR1 to %f\n",snr1);
break;
case 'p':
@@ -258,7 +247,7 @@ int main(int argc, char **argv)
case 'H':
printf("High-Speed Flag enabled\n");
- hs_flag = 1;
+ restrictedSetConfig = 1;
break;
case 'L':
@@ -275,7 +264,7 @@ int main(int argc, char **argv)
if ((transmission_mode!=1) &&
(transmission_mode!=2) &&
(transmission_mode!=6)) {
- msg("Unsupported transmission mode %d\n",transmission_mode);
+ printf("Unsupported transmission mode %d\n",transmission_mode);
exit(-1);
}
@@ -285,7 +274,7 @@ int main(int argc, char **argv)
n_tx=atoi(optarg);
if ((n_tx==0) || (n_tx>2)) {
- msg("Unsupported number of tx antennas %d\n",n_tx);
+ printf("Unsupported number of tx antennas %d\n",n_tx);
exit(-1);
}
@@ -295,7 +284,7 @@ int main(int argc, char **argv)
n_rx=atoi(optarg);
if ((n_rx==0) || (n_rx>2)) {
- msg("Unsupported number of rx antennas %d\n",n_rx);
+ printf("Unsupported number of rx antennas %d\n",n_rx);
exit(-1);
}
@@ -310,6 +299,14 @@ int main(int argc, char **argv)
break;
case 'F':
+ input_fd = fopen(optarg,"r");
+ input_file = optarg;
+
+ if (input_fd==NULL) {
+ printf("Problem with filename %s\n",optarg);
+ exit(-1);
+ }
+
break;
default:
@@ -339,20 +336,20 @@ int main(int argc, char **argv)
}
}
- logInit();
+
+ if (config_index<67) { prach_sequence_length=0; slot = subframe*2; slot_gNB = 1+(subframe*2); }
+ uint16_t N_ZC;
+ N_ZC = prach_sequence_length == 0 ? 839 : 139;
+ printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length);
+
+ // Configure log
+ logInit();
set_glog(loglvl);
T_stdout = 1;
-
SET_LOG_DEBUG(PRACH);
- if (snr1set==0) {
- if (n_frames==1)
- snr1 = snr0+.1;
- else
- snr1 = snr0+5.0;
- }
-
+ // Configure gNB and RU
RC.gNB = (PHY_VARS_gNB**) malloc(2*sizeof(PHY_VARS_gNB *));
RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB));
memset(RC.gNB[0],0,sizeof(PHY_VARS_gNB));
@@ -362,90 +359,204 @@ int main(int argc, char **argv)
memset(RC.ru[0],0,sizeof(RU_t));
RC.nb_RU = 1;
- gNB = RC.gNB[0];
- ru = RC.ru[0];
-
-
- if (ue_speed1set==0) {
- if (n_frames==1)
- ue_speed1 = ue_speed0+10;
- else
- ue_speed1 = ue_speed0+50;
- }
-
- printf("SNR0 %f, SNR1 %f\n",snr0,snr1);
-
- frame_parms = &gNB->frame_parms;
-
-
+ gNB = RC.gNB[0];
+ ru = RC.ru[0];
+ frame_parms = &gNB->frame_parms;
+ prach_config = &gNB->gNB_config.prach_config;
+ prach_pdu = &gNB->prach_vars.list[0].pdu;
+ frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH)
s_re = malloc(2*sizeof(double*));
s_im = malloc(2*sizeof(double*));
r_re = malloc(2*sizeof(double*));
r_im = malloc(2*sizeof(double*));
- frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH)
- frame_parms->nb_antennas_tx = n_tx;
- frame_parms->nb_antennas_rx = n_rx;
- frame_parms->N_RB_DL = N_RB_UL;
- frame_parms->N_RB_UL = N_RB_UL;
- frame_parms->threequarter_fs = threequarter_fs;
-
-
- nr_phy_config_request_sim(gNB,N_RB_UL,N_RB_UL,mu,Nid_cell,SSB_positions);
-
- frame_parms->frame_type = TDD;
- frame_parms->freq_range = nr_FR1;
-
- nsymb = (frame_parms->Ncp == 0) ? 14 : 12;
-
- printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d,Frame type %s, Frequency Range %s\n",NUMBER_OF_OFDM_CARRIERS,
- frame_parms->Ncp,frame_parms->samples_per_subframe,frame_parms->frame_type == FDD ? "FDD" : "TDD", frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2");
-
- ru->nr_frame_parms=frame_parms;
- ru->if_south = LOCAL_RF;
- ru->nb_tx = n_tx;
- ru->nb_rx = n_rx;
+ frame_parms->nb_antennas_tx = n_tx;
+ frame_parms->nb_antennas_rx = n_rx;
+ frame_parms->N_RB_DL = N_RB_UL;
+ frame_parms->N_RB_UL = N_RB_UL;
+ frame_parms->threequarter_fs = threequarter_fs;
+ frame_parms->frame_type = TDD;
+ frame_parms->freq_range = nr_FR1;
+ frame_parms->numerology_index = mu;
+
+ nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions);
+
+ //nsymb = (frame_parms->Ncp == 0) ? 14 : 12;
+
+ printf("FFT Size %d, Extended Prefix %d, Samples per subframe %d, Frame type %s, Frequency Range %s\n",
+ NUMBER_OF_OFDM_CARRIERS,
+ frame_parms->Ncp,
+ frame_parms->samples_per_subframe,
+ frame_parms->frame_type == FDD ? "FDD" : "TDD",
+ frame_parms->freq_range == nr_FR1 ? "FR1" : "FR2");
+
+ ru->nr_frame_parms = frame_parms;
+ ru->if_south = LOCAL_RF;
+ ru->nb_tx = n_tx;
+ ru->nb_rx = n_rx;
+
+ gNB->gNB_config.carrier_config.num_tx_ant.value = 1;
+ gNB->gNB_config.carrier_config.num_rx_ant.value = 1;
+ gNB->gNB_config.tdd_table.tdd_period.value = 6;
+
+ gNB->gNB_config.prach_config.num_prach_fd_occasions.value = num_prach_fd_occasions;
+ gNB->gNB_config.prach_config.num_prach_fd_occasions_list = (nfapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(nfapi_nr_num_prach_fd_occasions_t));
+
+ gNB->proc.slot_rx = slot;
+
+ int ret = get_nr_prach_info_from_index(config_index,
+ (int)frame,
+ (int)slot_gNB,
+ absoluteFrequencyPointA,
+ mu,
+ frame_parms->frame_type,
+ &format,
+ &start_symbol,
+ &N_t_slot,
+ &N_dur);
+
+ if (ret == 0) {printf("No prach in %d.%d, mu %d, config_index %d\n",frame,slot,mu,config_index); exit(-1);}
+ format0 = format&0xff; // first column of format from table
+ format1 = (format>>8)&0xff; // second column of format from table
+
+ if (format1 != 0xff) {
+ switch(format0) {
+ case 0xa1:
+ prach_format = 9;
+ break;
+ case 0xa2:
+ prach_format = 10;
+ break;
+ case 0xa3:
+ prach_format = 11;
+ break;
+ default:
+ AssertFatal(1==0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format");
+ }
+ } else {
+ switch(format0) {
+ case 0xa1:
+ prach_format = 0;
+ break;
+ case 0xa2:
+ prach_format = 1;
+ break;
+ case 0xa3:
+ prach_format = 2;
+ break;
+ case 0xb1:
+ prach_format = 3;
+ break;
+ case 0xb2:
+ prach_format = 4;
+ break;
+ case 0xb3:
+ prach_format = 5;
+ break;
+ case 0xb4:
+ prach_format = 6;
+ break;
+ case 0xc0:
+ prach_format = 7;
+ break;
+ case 0xc2:
+ prach_format = 8;
+ break;
+ case 0:
+ // long formats are handled @ PHY
+ break;
+ case 1:
+ // long formats are handled @ PHY
+ break;
+ case 2:
+ // long formats are handled @ PHY
+ break;
+ case 3:
+ // long formats are handled @ PHY
+ break;
+ default:
+ AssertFatal(1==0, "Invalid PRACH format");
+ }
+ }
+ printf("PRACH format %d\n",prach_format);
+
+ prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value = rootSequenceIndex;
+ prach_config->num_prach_fd_occasions_list[fd_occasion].k1.value = msg1_frequencystart;
+ prach_config->restricted_set_config.value = restrictedSetConfig;
+ prach_config->prach_sequence_length.value = prach_sequence_length;
+ prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig);
+ prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value = 1+(64/(N_ZC/prach_pdu->num_cs));
+ prach_pdu->prach_format = prach_format;
+
+ memcpy((void*)&ru->config,(void*)&RC.gNB[0]->gNB_config,sizeof(ru->config));
RC.nb_nr_L1_inst=1;
phy_init_nr_gNB(gNB,0,0);
nr_phy_init_RU(ru);
- set_tdd_config_nr(&gNB->gNB_config, 5000,
- 7, 6,
- 2, 4);
+ gNB->common_vars.rxdata = ru->common.rxdata;
+ set_tdd_config_nr(&gNB->gNB_config, mu, 7, 6, 2, 4);
- //configure UE
+ // Configure UE
UE = malloc(sizeof(PHY_VARS_NR_UE));
memset((void*)UE,0,sizeof(PHY_VARS_NR_UE));
PHY_vars_UE_g = malloc(2*sizeof(PHY_VARS_NR_UE**));
PHY_vars_UE_g[0] = malloc(2*sizeof(PHY_VARS_NR_UE*));
PHY_vars_UE_g[0][0] = UE;
memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS));
- if (init_nr_ue_signal(UE, 1, 0) != 0)
- {
+ UE->nrUE_config.prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t));
+
+ if (init_nr_ue_signal(UE, 1, 0) != 0){
printf("Error at UE NR initialisation\n");
exit(-1);
}
- txdata = UE->common_vars.txdata;
- printf("txdata %p\n",&txdata[0][subframe*frame_parms->samples_per_subframe]);
+ ue_prach_pdu = &UE->prach_vars[0]->prach_pdu;
+ ue_prach_config = &UE->nrUE_config.prach_config;
+ UE->prach_resources[0] = &prach_resources;
+ txdata = UE->common_vars.txdata;
+
+ UE->prach_vars[0]->amp = AMP;
+ ue_prach_pdu->root_seq_id = rootSequenceIndex;
+ ue_prach_pdu->num_cs = get_NCS(NCS_config, format0, restrictedSetConfig);
+ ue_prach_pdu->restricted_set = restrictedSetConfig;
+ ue_prach_pdu->freq_msg1 = msg1_frequencystart;
+ ue_prach_pdu->prach_format = prach_format;
+
+ ue_prach_config->prach_sub_c_spacing = mu;
+ ue_prach_config->prach_sequence_length = prach_sequence_length;
+ ue_prach_config->restricted_set_config = restrictedSetConfig;
+ ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences = prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value ;
+ ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index = rootSequenceIndex;
+ ue_prach_config->num_prach_fd_occasions_list[fd_occasion].k1 = msg1_frequencystart;
+
+ if (preamble_tx == 99)
+ preamble_tx = (uint16_t)(taus()&0x3f);
+
+ if (n_frames == 1)
+ printf("raPreamble %d\n",preamble_tx);
+
+ UE->prach_resources[0]->ra_PreambleIndex = preamble_tx;
+ UE->prach_resources[0]->init_msg1 = 1;
- double fs,bw;
+ // Configure channel
+ bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index);
+ AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n", bw, frame_parms->numerology_index, N_RB_UL);
+ if (bw <= 30.72e6)
+ fs = 30.72e6;
+ else if (bw <= 61.44e6)
+ fs = 61.44e6;
+ else if (bw <= 122.88e6)
+ fs = 122.88e6;
- bw = N_RB_UL*(180e3)*(1<<gNB->frame_parms.numerology_index);
- AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n",gNB->frame_parms.numerology_index,N_RB_UL);
- if (bw <= 30.72e6) fs = 30.72e6;
- else if (bw <= 61.44e6) fs = 61.44e6;
- else if (bw <= 122.88e6) fs = 122.88e6;
LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES);
-
UE2gNB = new_channel_desc_scm(UE->frame_parms.nb_antennas_tx,
gNB->frame_parms.nb_antennas_rx,
channel_model,
- fs,
- bw,
+ fs,
+ bw,
0.0,
delay,
0);
@@ -468,97 +579,80 @@ int main(int argc, char **argv)
bzero(r_im[i],FRAME_LENGTH_COMPLEX_SAMPLES*sizeof(double));
}
- UE->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex;
- UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98;
- UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config;
- UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag;
- UE->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0;
- UE->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0;
-
-
- gNB->frame_parms.prach_config_common.rootSequenceIndex=rootSequenceIndex;
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex=98;
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig=NCS_config;
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag=hs_flag;
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.restrictedSetConfig=0;
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.msg1_frequencystart=0;
-
- gNB->proc.slot_rx = subframe<<1;
-
- gNB->common_vars.rxdata = ru->common.rxdata;
-
-
- compute_nr_prach_seq(gNB->frame_parms.prach_config_common.rootSequenceIndex,
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
- gNB->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag,
- gNB->frame_parms.frame_type,
- gNB->frame_parms.freq_range,
- gNB->X_u);
+ // compute PRACH sequence
+ compute_nr_prach_seq(prach_config->prach_sequence_length.value,
+ prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value,
+ prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index.value,
+ gNB->X_u);
- compute_nr_prach_seq(UE->frame_parms.prach_config_common.rootSequenceIndex,
- UE->frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex,
- UE->frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig,
- UE->frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag,
- UE->frame_parms.frame_type,
- UE->frame_parms.freq_range,
- UE->X_u);
-
-
-
- UE->prach_vars[0]->amp = AMP;
-
- UE->prach_resources[0] = &prach_resources;
-
- if (preamble_tx == 99)
- preamble_tx = (uint16_t)(taus()&0x3f);
-
- if (n_frames == 1)
- printf("raPreamble %d\n",preamble_tx);
-
- UE->prach_resources[0]->ra_PreambleIndex = preamble_tx;
- UE->prach_resources[0]->ra_TDD_map_index = 0;
+ compute_nr_prach_seq(ue_prach_config->prach_sequence_length,
+ ue_prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences,
+ ue_prach_config->num_prach_fd_occasions_list[fd_occasion].prach_root_sequence_index,
+ UE->X_u);
/*tx_lev = generate_nr_prach(UE,
0, //gNB_id,
- subframe,
- 0); //Nf */ //commented for testing purpose
+ subframe); */ //commented for testing purpose
UE_nr_rxtx_proc_t proc={0};
- nr_ue_prach_procedures(UE,&proc,0,0,0);
-
+ proc.frame_tx = frame;
+ proc.nr_tti_tx = slot;
+ nr_ue_prach_procedures(UE,&proc,0,0);
/* tx_lev_dB not used later, no need to set */
//tx_lev_dB = (unsigned int) dB_fixed(tx_lev);
- LOG_M("txsig0.m","txs0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1);
- //LOG_M("txsig1.m","txs1", txdata[1],FRAME_LENGTH_COMPLEX_SAMPLES,1,1);
+ prach_start = subframe*frame_parms->samples_per_subframe-UE->N_TA_offset;
+
+ #ifdef NR_PRACH_DEBUG
+ LOG_M("txsig0.m", "txs0", &txdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1);
+ LOG_M("txsig0_frame.m","txs0", txdata[0],frame_parms->samples_per_frame,1,1);
+ #endif
// multipath channel
- dump_nr_prach_config(&gNB->frame_parms,subframe);
+ // dump_nr_prach_config(&gNB->frame_parms,subframe);
- for (i=0; i<2*frame_parms->samples_per_subframe; i++) {
+ for (i = 0; i < frame_parms->samples_per_subframe<<1; i++) {
for (aa=0; aa<1; aa++) {
if (awgn_flag == 0) {
- s_re[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]);
- s_im[aa][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]);
+ s_re[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]);
+ s_im[aa][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]);
} else {
for (aarx=0; aarx<gNB->frame_parms.nb_antennas_rx; aarx++) {
if (aa==0) {
- r_re[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]);
- r_im[aarx][i] = ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]);
+ r_re[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]);
+ r_im[aarx][i] = ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]);
} else {
- r_re[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)]);
- r_im[aarx][i] += ((double)(((short *)&txdata[aa][subframe*frame_parms->samples_per_subframe]))[(i<<1)+1]);
+ r_re[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)]);
+ r_im[aarx][i] += ((double)(((short *)&txdata[aa][prach_start]))[(i<<1)+1]);
}
}
}
}
}
+ if (snr1set == 0) {
+ if (n_frames == 1)
+ snr1 = snr0 + .1;
+ else
+ snr1 = snr0 + 5.0;
+ }
+
+ printf("SNR0 %f, SNR1 %f\n", snr0, snr1);
+ if (ue_speed1set == 0) {
+ if (n_frames == 1)
+ ue_speed1 = ue_speed0 + 10;
+ else
+ ue_speed1 = ue_speed0 + 50;
+ }
+
+ rx_prach_start = subframe*frame_parms->samples_per_subframe;
+ if (n_frames==1) printf("slot %d, rx_prach_start %d\n",slot,rx_prach_start);
+ uint16_t preamble_rx, preamble_energy;
- for (SNR=snr0; SNR<snr1; SNR+=.2) {
+
+ for (SNR=snr0; SNR<snr1; SNR+=.1) {
for (ue_speed=ue_speed0; ue_speed<ue_speed1; ue_speed+=10) {
delay_avg = 0.0;
// max Doppler shift
@@ -568,7 +662,8 @@ int main(int argc, char **argv)
for (trial=0; trial<n_frames; trial++) {
- sigma2_dB = 10*log10((double)tx_lev) - SNR;
+ if (input_fd==NULL) {
+ sigma2_dB = 10*log10((double)tx_lev) - SNR - 10*log10(N_RB_UL*12/N_ZC);
if (n_frames==1)
printf("sigma2_dB %f (SNR %f dB) tx_lev_dB %f\n",sigma2_dB,SNR,10*log10((double)tx_lev));
@@ -577,10 +672,8 @@ int main(int argc, char **argv)
sigma2 = pow(10,sigma2_dB/10);
// printf("Sigma2 %f (sigma2_dB %f)\n",sigma2,sigma2_dB);
-
if (awgn_flag == 0) {
- multipath_tv_channel(UE2gNB,s_re,s_im,r_re,r_im,
- 2*frame_parms->samples_per_subframe,0);
+ multipath_tv_channel(UE2gNB, s_re, s_im, r_re, r_im, frame_parms->samples_per_tti<<1, 0);
}
if (n_frames==1) {
@@ -589,55 +682,66 @@ int main(int argc, char **argv)
10*log10(tx_lev));
}
- for (i=0; i<frame_parms->samples_per_subframe; i++) {
- for (aa=0; aa<gNB->frame_parms.nb_antennas_rx; aa++) {
-
- ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
- ((short*) &gNB->common_vars.rxdata[aa][subframe*(frame_parms->samples_per_subframe)])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
+ for (i = 0; i< frame_parms->samples_per_subframe; i++) {
+ for (aa = 0; aa < frame_parms->nb_antennas_rx; aa++) {
+ ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i] = (short) (.167*(r_re[aa][i] +sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
+ ((short*) &ru->common.rxdata[aa][rx_prach_start])[2*i+1] = (short) (.167*(r_im[aa][i] + (iqim*r_re[aa][i]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
}
}
- uint16_t preamble_rx;
- rx_nr_prach_ru(ru,
- 0,
- subframe);
- gNB->prach_vars.rxsigF = ru->prach_rxsigF;
-
- rx_nr_prach(gNB,
- 0,
- subframe,
- &preamble_rx,
- preamble_energy_list,
- preamble_delay_list);
-
- if (preamble_rx!=preamble_tx)
+ } else {
+ n_bytes = fread(&ru->common.rxdata[0][rx_prach_start],sizeof(int32_t),frame_parms->samples_per_subframe,input_fd);
+ printf("fread %d bytes from file %s\n",n_bytes,input_file);
+ if (n_bytes!=frame_parms->samples_per_subframe) {
+ printf("expected %d bytes\n",frame_parms->samples_per_subframe);
+ exit(-1);
+ }
+ }
+
+
+ rx_nr_prach_ru(ru, prach_format, numRA, prachStartSymbol, frame, slot);
+
+ gNB->prach_vars.rxsigF = ru->prach_rxsigF;
+ if (n_frames == 1) printf("ncs %d,num_seq %d\n",prach_pdu->num_cs, prach_config->num_prach_fd_occasions_list[fd_occasion].num_root_sequences.value);
+ rx_nr_prach(gNB, prach_pdu, frame, subframe, &preamble_rx, &preamble_energy, &preamble_delay);
+
+ // printf(" preamble_energy %d preamble_rx %d preamble_tx %d \n", preamble_energy, preamble_rx, preamble_tx);
+
+ if (preamble_rx != preamble_tx)
prach_errors++;
- else {
- delay_avg += (double)preamble_delay_list[preamble_tx];
- }
+ else
+ delay_avg += (double)preamble_delay;
+
+ N_ZC = (prach_sequence_length) ? 139 : 839;
if (n_frames==1) {
- printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy_list[0],preamble_delay_list[0]);
-
-
- LOG_M("prach0.m","prach0", &txdata[0][subframe*frame_parms->samples_per_subframe],frame_parms->samples_per_subframe,1,1);
- LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0],24576,1,1);
- LOG_M("rxsig0.m","rxs0",
- &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe],
- frame_parms->samples_per_subframe,1,1);
- LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0],839*4,1,1);
- LOG_M("prach_preamble.m","prachp",&gNB->X_u[0],839,1,1);
+ printf("preamble %d (tx %d) : energy %d, delay %d\n",preamble_rx,preamble_tx,preamble_energy,preamble_delay);
+ #ifdef NR_PRACH_DEBUG
+ LOG_M("prach0.m","prach0", &txdata[0][prach_start], frame_parms->samples_per_subframe, 1, 1);
+ LOG_M("prachF0.m","prachF0", &gNB->prach_vars.prachF[0], N_ZC, 1, 1);
+ LOG_M("rxsig0.m","rxs0", &gNB->common_vars.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1);
+ LOG_M("ru_rxsig0.m","rxs0", &ru->common.rxdata[0][subframe*frame_parms->samples_per_subframe], frame_parms->samples_per_subframe, 1, 1);
+ LOG_M("rxsigF0.m","rxsF0", gNB->prach_vars.rxsigF[0], N_ZC, 1, 1);
+ LOG_M("prach_preamble.m","prachp", &gNB->X_u[0], N_ZC, 1, 1);
+ LOG_M("ue_prach_preamble.m","prachp", &UE->X_u[0], N_ZC, 1, 1);
+ #endif
}
}
- printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors));
- //printf("(%f,%f)\n",ue_speed,(double)prach_errors/(double)n_frames);
- } // UE Speed loop
+ printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n", SNR, ue_speed, prach_errors, n_frames, delay_avg/(double)(n_frames-prach_errors));
+ if (input_fd)
+ break;
+ if (prach_errors)
+ break;
- //printf("SNR %f dB, UE Speed %f km/h: errors %d/%d (delay %f)\n",SNR,ue_speed,prach_errors,n_frames,delay_avg/(double)(n_frames-prach_errors));
- // printf("(%f,%f)\n",SNR,(double)prach_errors/(double)n_frames);
+ } // UE Speed loop
+ if (!prach_errors) {
+ printf("PRACH test OK\n");
+ break;
+ }
+ if (input_fd)
+ break;
} //SNR loop
-
for (i=0; i<2; i++) {
free(s_re[i]);
free(s_im[i]);
@@ -650,17 +754,7 @@ int main(int argc, char **argv)
free(r_re);
free(r_im);
+ if (input_fd) fclose(input_fd);
return(0);
-
}
-
-
-
-/*
- for (i=1;i<4;i++)
- memcpy((void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[i*12*OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES_NO_PREFIX*2],
- (void *)&PHY_vars->tx_vars[0].TX_DMA_BUFFER[0],
- 12*OFDM_SYMBOL_SIZE_SAMPLES_NO_PREFIX*2);
-*/
-
diff --git a/openair1/SIMULATION/NR_PHY/pucchsim.c b/openair1/SIMULATION/NR_PHY/pucchsim.c
index 445c45693ed7ce5c46a52cd7021f9101adc0a29c..86f7d651e40129023245d2ca82e2719caca32a7a 100644
--- a/openair1/SIMULATION/NR_PHY/pucchsim.c
+++ b/openair1/SIMULATION/NR_PHY/pucchsim.c
@@ -33,11 +33,10 @@
#include "PHY/defs_nr_UE.h"
#include "PHY/defs_gNB.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
#include "PHY/INIT/phy_init.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "PHY/NR_UE_TRANSPORT/pucch_nr.h"
#include "SCHED_NR/sched_nr.h"
@@ -59,6 +58,8 @@ uint16_t NB_UE_INST = 1;
// needed for some functions
PHY_VARS_NR_UE * PHY_vars_UE_g[1][1]={{NULL}};
+void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {}
+
int main(int argc, char **argv)
{
char c;
@@ -66,7 +67,7 @@ int main(int argc, char **argv)
double sigma2, sigma2_dB=10,SNR,snr0=-2.0,snr1=2.0;
double cfo=0;
uint8_t snr1set=0;
- int **txdata;
+ int **txdataF,**rxdataF;
double **s_re,**s_im,**r_re,**r_im;
//int sync_pos, sync_pos_slot;
//FILE *rx_frame_file;
@@ -84,25 +85,27 @@ int main(int argc, char **argv)
int format=0;
//uint8_t extended_prefix_flag=0;
FILE *input_fd=NULL;
- uint8_t nacktoack_flag=0;
+ //uint8_t nacktoack_flag=0;
int16_t amp=0x7FFF;
int nr_tti_tx=0;
- uint64_t actual_payload=0,payload_received;//payload bits b7b6...b2b1b0 where b7..b3=0 b2b1=HARQ b0 is SR. payload maximum value is 7 for pucch format 0
+ uint64_t actual_payload=0,payload_received;
int nr_bit=1; // maximum value possible is 2
uint8_t m0=0;// higher layer paramater initial cyclic shift
uint8_t nrofSymbols=1; //number of OFDM symbols can be 1-2 for format 1
uint8_t startingSymbolIndex=0; // resource allocated see 9.2.1, 38.213 for more info.should be actually present in the resource set provided
uint16_t startingPRB=0,startingPRB_intraSlotHopping=0; //PRB number not sure see 9.2.1, 38.213 for more info. Should be actually present in the resource set provided
+ uint16_t nrofPRB=2;
uint8_t timeDomainOCC=0;
SCM_t channel_model=AWGN;//Rayleigh1_anticorr;
int N_RB_DL=273,mu=1;
- float target_error_rate=0.01;
+ float target_error_rate=0.001;
int frame_length_complex_samples;
//int frame_length_complex_samples_no_prefix;
NR_DL_FRAME_PARMS *frame_parms;
//unsigned char frame_type = 0;
int loglvl=OAILOG_WARNING;
+ int sr_flag = 0;
cpuf = get_cpu_freq_GHz();
@@ -112,9 +115,8 @@ int main(int argc, char **argv)
randominit(0);
logInit();
- set_glog(loglvl);
- while ((c = getopt (argc, argv, "f:hA:f:g:i:P:b:T:n:o:s:S:x:y:z:N:F:GR:IL")) != -1) {
+ while ((c = getopt (argc, argv, "f:hA:f:g:i:I:P:B:b:T:m:n:r:o:s:S:x:y:z:N:F:GR:IL:q:c")) != -1) {
switch (c) {
case 'f':
//write_output_file=1;
@@ -257,14 +259,32 @@ int main(int argc, char **argv)
case 'i':
nrofSymbols=(uint8_t)atoi(optarg);
break;
+ case 'I':
+ startingSymbolIndex=(uint8_t)atoi(optarg);
+ break;
+ case 'r':
+ startingPRB=atoi(optarg);
+ break;
+ case 'q':
+ nrofPRB=atoi(optarg);
+ break;
case 'P':
format=atoi(optarg);
break;
+ case 'm':
+ m0=atoi(optarg);
+ break;
case 'b':
nr_bit=atoi(optarg);
break;
+ case 'c':
+ sr_flag=1;
+ break;
+ case 'B':
+ actual_payload=atoi(optarg);
+ break;
case 'T':
- nacktoack_flag=(uint8_t)atoi(optarg);
+ //nacktoack_flag=(uint8_t)atoi(optarg);
target_error_rate=0.001;
break;
default:
@@ -292,23 +312,42 @@ int main(int argc, char **argv)
printf("-f Output filename (.txt format) for Pe/SNR results\n");
printf("-F Input filename (.txt format) for RX conformance testing\n");
printf("-i Enter number of ofdm symbols for pucch\n");
+ printf("-I Starting symbol index for pucch\n");
+ printf("-r PUCCH starting PRB\n");
+ printf("-q PUCCH number of PRB\n");
printf("-P Enter the format of PUCCH\n");
printf("-b number of HARQ bits (1-2)\n");
+ printf("-B payload to be transmitted on PUCCH\n");
+ printf("-m initial cyclic shift m0\n");
printf("-T to check nacktoack miss for format 1");
exit (-1);
break;
}
}
+ set_glog(loglvl);
+
if (snr1set==0) snr1 = snr0+10;
printf("Initializing gNodeB for mu %d, N_RB_DL %d\n",mu,N_RB_DL);
+ if((format!=0) && (format!=1) && (format!=2)){
+ printf("PUCCH format %d not supported\n",format);
+ exit(0);
+ }
+
+ AssertFatal(((format < 2)&&(nr_bit<3)&&(actual_payload<4)) ||
+ ((format == 2)&&(nr_bit>2)&&(nr_bit<65)),"illegal combination format %d, nr_bit %d\n",
+ format,nr_bit);
+
+ actual_payload &= ((1<<nr_bit)-1);
+
+ printf("Transmitted payload is %ld\n",actual_payload);
RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *));
RC.gNB[0] = malloc(sizeof(PHY_VARS_gNB));
gNB = RC.gNB[0];
-
+ memset((void*)gNB,0,sizeof(*gNB));
frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH)
frame_parms->nb_antennas_tx = n_tx;
frame_parms->nb_antennas_rx = n_rx;
@@ -374,8 +413,10 @@ int main(int argc, char **argv)
s_im = malloc(2*sizeof(double*));
r_re = malloc(2*sizeof(double*));
r_im = malloc(2*sizeof(double*));
- txdata = malloc(2*sizeof(int*));
-
+ txdataF = malloc(2*sizeof(int*));
+ rxdataF = malloc(2*sizeof(int*));
+ gNB->common_vars.rxdataF=rxdataF;
+ memcpy((void*)&gNB->frame_parms,(void*)frame_parms,sizeof(frame_parms));
for (i=0; i<2; i++) {
s_re[i] = malloc(frame_length_complex_samples*sizeof(double));
@@ -388,16 +429,18 @@ int main(int argc, char **argv)
r_im[i] = malloc(frame_length_complex_samples*sizeof(double));
bzero(r_im[i],frame_length_complex_samples*sizeof(double));
- printf("Allocating %d samples for txdata\n",frame_length_complex_samples);
- txdata[i] = malloc(frame_length_complex_samples*sizeof(int));
- bzero(r_re[i],frame_length_complex_samples*sizeof(int));
-
+ printf("Allocating %d samples for txdataF/rxdataF\n",14*frame_parms->ofdm_symbol_size);
+ txdataF[i] = memalign(32,14*frame_parms->ofdm_symbol_size*sizeof(int));
+ bzero(txdataF[i],14*frame_parms->ofdm_symbol_size*sizeof(int));
+ rxdataF[i] = memalign(32,14*frame_parms->ofdm_symbol_size*sizeof(int));
+ bzero(rxdataF[i],14*frame_parms->ofdm_symbol_size*sizeof(int));
}
//configure UE
UE = malloc(sizeof(PHY_VARS_NR_UE));
memcpy(&UE->frame_parms,frame_parms,sizeof(NR_DL_FRAME_PARMS));
+ UE->pucch_config_common_nr->hoppingId = Nid_cell;
//phy_init_nr_top(UE); //called from init_nr_ue_signal
UE->perfect_ce = 0;
@@ -413,83 +456,118 @@ int main(int argc, char **argv)
uint8_t mcs=0;
startingPRB_intraSlotHopping=N_RB_DL-1;
pucch_GroupHopping_t PUCCH_GroupHopping=UE->pucch_config_common_nr->pucch_GroupHopping;
- uint32_t n_id=UE->pucch_config_common_nr->hoppingId;
- if((format!=0) && (format!=1)){
- printf("format not supported\n");
- exit(0);
+ uint32_t hopping_id=UE->pucch_config_common_nr->hoppingId;
+ uint32_t dmrs_scrambling_id = 0, data_scrambling_id=0;
+ //t_nrPolar_params *currentPtr;
+
+ if(format==0){
+ // for now we are not considering SR just HARQ-ACK
+ if (nr_bit ==0)
+ mcs=table1_mcs[0];
+ else if(nr_bit==1)
+ mcs=table1_mcs[actual_payload];
+ else if(nr_bit==2)
+ mcs=table2_mcs[actual_payload];
+ else AssertFatal(1==0,"Either nr_bit %d or sr_flag %d must be non-zero\n", nr_bit, sr_flag);
}
- if(nacktoack_flag==0){
- if(format==0){
- if(nr_bit==1){
- actual_payload=2;
- mcs=table1_mcs[actual_payload];
- }
- else if(nr_bit==2){
- actual_payload=6;
- mcs=table2_mcs[actual_payload];
- }
- else{
- printf("Number of HARQ bits possible is 1-2\n");
- exit(0);
- }
- }
- else {
- if(nr_bit==1)
- actual_payload=1;
- else if(nr_bit==2)
- actual_payload=3;
- else{
- printf("number of bits carried by PUCCH format1 is 1-2\n");
- }
- }
- }
+ else if (format == 2 && nr_bit > 11) gNB->uci_polarParams = nr_polar_params(2, nr_bit, nrofPRB, 1, NULL);
+
for(SNR=snr0;SNR<=snr1;SNR=SNR+1){
ack_nack_errors=0;
n_errors = 0;
- sigma2_dB = 20*log10((double)amp/32767)-SNR;
- sigma2 = pow(10,sigma2_dB/10);
for (trial=0; trial<n_trials; trial++) {
- bzero(txdata[0],frame_length_complex_samples*sizeof(int));
+ bzero(txdataF[aa],frame_parms->ofdm_symbol_size*sizeof(int));
if(format==0){
- nr_generate_pucch0(UE,txdata,frame_parms,UE->pucch_config_dedicated,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB);
+ nr_generate_pucch0(UE,txdataF,frame_parms,PUCCH_GroupHopping,hopping_id,amp,nr_tti_tx,m0,mcs,nrofSymbols,startingSymbolIndex,startingPRB);
}
- else{
- nr_generate_pucch1(UE,txdata,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit);
+ else if (format == 1){
+ nr_generate_pucch1(UE,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,0,nr_bit);
}
- for(i=0; i<frame_length_complex_samples; i++) {
- r_re[aa][i]=((double)(((int16_t *)txdata[0])[(i<<1)])/32767 + sqrt(sigma2/2)*gaussdouble(0.0,1.0));
- r_im[aa][i]=((double)(((int16_t *)txdata[0])[(i<<1)+1])/32767+ sqrt(sigma2/2)*gaussdouble(0.0,1.0));
- r_re[aa][i]=r_re[0][i]/(sqrt(sigma2/2)+1);
- r_im[aa][i]=r_im[0][i]/(sqrt(sigma2/2)+1);
- if(r_re[aa][i]<-1)
- r_re[aa][i]=-1;
- else if(r_re[aa][i]>1)
- r_re[aa][i]=1;
- if(r_im[aa][i]<-1)
- r_im[aa][i]=-1;
- else if(r_im[aa][i]>1)
- r_im[aa][i]=1;
- ((int16_t *)txdata[aa])[(i<<1)] = (int16_t)round(r_re[aa][i]*32767);
- ((int16_t *)txdata[aa])[(i<<1)+1] =(int16_t)round(r_im[aa][i]*32767);
+ else {
+ nr_generate_pucch2(UE,0x1234,dmrs_scrambling_id,data_scrambling_id,txdataF,frame_parms,UE->pucch_config_dedicated,actual_payload,amp,nr_tti_tx,nrofSymbols,startingSymbolIndex,nrofPRB,startingPRB,nr_bit);
}
+
+ int txlev = signal_energy(&txdataF[aa][startingSymbolIndex*frame_parms->ofdm_symbol_size],
+ frame_parms->ofdm_symbol_size);
+ // printf("txlev %d (%d dB), offset %d\n",txlev,dB_fixed(txlev),startingSymbolIndex*frame_parms->ofdm_symbol_size);
+
+ // note : this scaling
+ int nb_re = (format == 0 || format == 1)? 12 : 12*nrofPRB;
+ sigma2_dB = 10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/nb_re)-SNR;
+ sigma2 = pow(10,sigma2_dB/10);
+
+ for(i=startingSymbolIndex*frame_parms->ofdm_symbol_size; i<(startingSymbolIndex+1)*frame_parms->ofdm_symbol_size; i++) {
+ ((int16_t*)rxdataF[aa])[i<<1] = (int16_t)(100.0*((double)(((int16_t *)txdataF[aa])[(i<<1)]) + sqrt(sigma2/2)*gaussdouble(0.0,1.0))/sqrt((double)txlev));
+ ((int16_t*)rxdataF[aa])[1+(i<<1)]=(int16_t)(100.0*((double)(((int16_t *)txdataF[aa])[(i<<1)+1])+ sqrt(sigma2/2)*gaussdouble(0.0,1.0))/sqrt((double)txlev));
+ }
+ int rxlev = signal_energy(&rxdataF[aa][startingSymbolIndex*frame_parms->ofdm_symbol_size],
+ frame_parms->ofdm_symbol_size);
+ if (n_trials==1) printf("rxlev %d (%d dB), sigma2 %f dB, SNR %f, TX %f\n",rxlev,dB_fixed(rxlev),sigma2_dB,SNR,10*log10((double)txlev*UE->frame_parms.ofdm_symbol_size/12));
if(format==0){
- nr_decode_pucch0(txdata,PUCCH_GroupHopping,n_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,nr_bit);
+ nfapi_nr_uci_pucch_pdu_format_0_1_t uci_pdu;
+ nfapi_nr_pucch_pdu_t pucch_pdu;
+ pucch_pdu.subcarrier_spacing = 1;
+ pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1;
+ pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1;
+ pucch_pdu.bit_len_harq = nr_bit;
+ pucch_pdu.bit_len_csi_part1 = 0;
+ pucch_pdu.bit_len_csi_part2 = 0;
+ pucch_pdu.sr_flag = sr_flag;
+ pucch_pdu.nr_of_symbols = nrofSymbols;
+ pucch_pdu.hopping_id = hopping_id;
+ pucch_pdu.initial_cyclic_shift = 0;
+ pucch_pdu.start_symbol_index = startingSymbolIndex;
+ pucch_pdu.prb_start = startingPRB;
+ nr_decode_pucch0(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu);
if(nr_bit==1)
- ack_nack_errors+=(((actual_payload^payload_received)&2)>>1);
+ ack_nack_errors+=(actual_payload^uci_pdu.harq->harq_list[0].harq_value);
else
- ack_nack_errors+=(((actual_payload^payload_received)&2)>>1) + (((actual_payload^payload_received)&4)>>2);
+ ack_nack_errors+=(((actual_payload&1)^uci_pdu.harq->harq_list[0].harq_value)+((actual_payload>>1)^uci_pdu.harq->harq_list[1].harq_value));
+ free(uci_pdu.harq->harq_list);
}
- else{
- nr_decode_pucch1(txdata,PUCCH_GroupHopping,n_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit);
+ else if (format==1) {
+
+ nr_decode_pucch1(rxdataF,PUCCH_GroupHopping,hopping_id,&(payload_received),frame_parms,amp,nr_tti_tx,m0,nrofSymbols,startingSymbolIndex,startingPRB,startingPRB_intraSlotHopping,timeDomainOCC,nr_bit);
if(nr_bit==1)
ack_nack_errors+=((actual_payload^payload_received)&1);
else
ack_nack_errors+=((actual_payload^payload_received)&1) + (((actual_payload^payload_received)&2)>>1);
}
+ else if (format==2) {
+ nfapi_nr_uci_pucch_pdu_format_2_3_4_t uci_pdu;
+ nfapi_nr_pucch_pdu_t pucch_pdu;
+ pucch_pdu.rnti = 0x1234;
+ pucch_pdu.subcarrier_spacing = 1;
+ pucch_pdu.group_hop_flag = PUCCH_GroupHopping&1;
+ pucch_pdu.sequence_hop_flag = (PUCCH_GroupHopping>>1)&1;
+ pucch_pdu.bit_len_csi_part1 = nr_bit;
+ pucch_pdu.bit_len_harq = 0;
+ pucch_pdu.bit_len_csi_part2 = 0;
+ pucch_pdu.sr_flag = 0;
+ pucch_pdu.nr_of_symbols = nrofSymbols;
+ pucch_pdu.hopping_id = hopping_id;
+ pucch_pdu.initial_cyclic_shift = 0;
+ pucch_pdu.start_symbol_index = startingSymbolIndex;
+ pucch_pdu.prb_size = nrofPRB;
+ pucch_pdu.prb_start = startingPRB;
+ pucch_pdu.dmrs_scrambling_id = dmrs_scrambling_id;
+ pucch_pdu.data_scrambling_id = data_scrambling_id;
+ nr_decode_pucch2(gNB,nr_tti_tx,&uci_pdu,&pucch_pdu);
+ int csi_part1_bytes=pucch_pdu.bit_len_csi_part1>>3;
+ if ((pucch_pdu.bit_len_csi_part1&7) > 0) csi_part1_bytes++;
+ for (int i=0;i<csi_part1_bytes;i++) {
+ if (uci_pdu.csi_part1.csi_part1_payload[i] != ((uint8_t*)&actual_payload)[i]) {
+ ack_nack_errors++;
+ break;
+ }
+ }
+ free(uci_pdu.csi_part1.csi_part1_payload);
+
+ }
n_errors=((actual_payload^payload_received)&1)+(((actual_payload^payload_received)&2)>>1)+(((actual_payload^payload_received)&4)>>2)+n_errors;
}
- printf("SNR=%f, n_trials=%d, n_bit_errors=%d\n",SNR,n_trials,n_errors);
- if((float)ack_nack_errors/(float)(nr_bit*n_trials)<=target_error_rate){
+ printf("SNR=%f, n_trials=%d, n_bit_errors=%d\n",SNR,n_trials,ack_nack_errors);
+ if((float)ack_nack_errors/(float)(n_trials)<=target_error_rate){
printf("PUCCH test OK\n");
break;
}
@@ -500,13 +578,15 @@ int main(int argc, char **argv)
free(s_im[i]);
free(r_re[i]);
free(r_im[i]);
- free(txdata[i]);
+ free(txdataF[i]);
+ free(rxdataF[i]);
}
free(s_re);
free(s_im);
free(r_re);
free(r_im);
- free(txdata);
+ free(txdataF);
+ free(rxdataF);
if (output_fd) fclose(output_fd);
if (input_fd) fclose(input_fd);
diff --git a/openair1/SIMULATION/NR_PHY/ulschsim.c b/openair1/SIMULATION/NR_PHY/ulschsim.c
index 48ea26da8f081224e5e28ccd4c18c220ca99e9d2..af49aa757b94f88d2082def48678bae547ac62a8 100644
--- a/openair1/SIMULATION/NR_PHY/ulschsim.c
+++ b/openair1/SIMULATION/NR_PHY/ulschsim.c
@@ -34,10 +34,9 @@
#include "PHY/defs_gNB.h"
#include "PHY/INIT/phy_init.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
+#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
@@ -54,6 +53,8 @@ PHY_VARS_NR_UE *UE;
RAN_CONTEXT_t RC;
int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
+void init_downlink_harq_status(NR_DL_UE_HARQ_t *dl_harq) {}
+
double cpuf;
uint8_t nfapi_mode = 0;
uint16_t NB_UE_INST = 1;
@@ -391,7 +392,7 @@ int main(int argc, char **argv)
mod_order = nr_get_Qm_ul(Imcs, 0);
code_rate = nr_get_code_rate_ul(Imcs, 0);
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
- TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, Nl);
+ TBS = nr_compute_tbs(mod_order,code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl);
printf("\nAvailable bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order);
@@ -402,7 +403,6 @@ int main(int argc, char **argv)
rel15_ul->mcs_index = Imcs;
rel15_ul->pusch_data.rv_index = rvidx;
rel15_ul->nrOfLayers = Nl;
- //rel15_ul->length_dmrs = length_dmrs;
rel15_ul->target_code_rate = code_rate;
rel15_ul->pusch_data.tb_size = TBS>>3;
///////////////////////////////////////////////////
@@ -424,15 +424,6 @@ int main(int argc, char **argv)
for (i = 0; i < TBS / 8; i++)
test_input[i] = (unsigned char) rand();
-
- /////////////////////////[adk] preparing NR_UE_ULSCH_t parameters///////////////////////// A HOT FIX until creating nfapi_nr_ul_config_ulsch_pdu_rel15_t
- ///////////
- ulsch_ue->nb_re_dmrs = nb_re_dmrs;
- ulsch_ue->length_dmrs = length_dmrs;
- ulsch_ue->rnti = n_rnti;
- ///////////
- ////////////////////////////////////////////////////////////////////////////////////////////
-
/////////////////////////[adk] preparing UL harq_process parameters/////////////////////////
///////////
NR_UL_UE_HARQ_t *harq_process_ul_ue = ulsch_ue->harq_processes[harq_pid];
@@ -442,13 +433,14 @@ int main(int argc, char **argv)
if (harq_process_ul_ue) {
- harq_process_ul_ue->mcs = Imcs;
- harq_process_ul_ue->Nl = Nl;
- harq_process_ul_ue->nb_rb = nb_rb;
- harq_process_ul_ue->number_of_symbols = nb_symb_sch;
+ harq_process_ul_ue->pusch_pdu.rnti = n_rnti;
+ harq_process_ul_ue->pusch_pdu.mcs_index = Imcs;
+ harq_process_ul_ue->pusch_pdu.nrOfLayers = Nl;
+ harq_process_ul_ue->pusch_pdu.rb_size = nb_rb;
+ harq_process_ul_ue->pusch_pdu.nr_of_symbols = nb_symb_sch;
harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*nb_codewords;
- harq_process_ul_ue->rvidx = rvidx;
- harq_process_ul_ue->TBS = TBS;
+ harq_process_ul_ue->pusch_pdu.pusch_data.rv_index = rvidx;
+ harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS;
harq_process_ul_ue->a = &test_input[0];
}
@@ -461,9 +453,10 @@ int main(int argc, char **argv)
/////////////////////////ULSCH coding/////////////////////////
///////////
+ unsigned int G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, Nl);
if (input_fd == NULL) {
- nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid);
+ nr_ulsch_encoding(ulsch_ue, frame_parms, harq_pid, G);
}
printf("\n");
diff --git a/openair1/SIMULATION/NR_PHY/ulsim.c b/openair1/SIMULATION/NR_PHY/ulsim.c
index 7c1b441b6a30bd1934a4470dd998927f535943d8..ac4b93b9736a3e4c0e13c54969a9aa4b125021f7 100644
--- a/openair1/SIMULATION/NR_PHY/ulsim.c
+++ b/openair1/SIMULATION/NR_PHY/ulsim.c
@@ -37,15 +37,14 @@
#include "PHY/MODULATION/modulation_UE.h"
#include "PHY/MODULATION/nr_modulation.h"
#include "PHY/NR_REFSIG/dmrs_nr.h"
-#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_TRANSPORT/nr_sch_dmrs.h"
-#include "PHY/NR_TRANSPORT/nr_transport.h"
#include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/NR_TRANSPORT/nr_ulsch.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "PHY/TOOLS/tools_defs.h"
+#include "SCHED_NR/fapi_nr_l1.h"
#include "SCHED_NR/sched_nr.h"
#include "SCHED_NR_UE/defs.h"
#include "SCHED_NR_UE/fapi_nr_ue_l1.h"
@@ -53,10 +52,13 @@
#include "openair1/SIMULATION/RF/rf.h"
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
#include "openair2/RRC/NR/MESSAGES/asn1_msg.h"
+//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "openair2/LAYER2/NR_MAC_UE/mac_proto.h"
#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
+
#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0))
#include "SIMULATION/LTE_PHY/common_sim.h"
+
//#define DEBUG_ULSIM
PHY_VARS_gNB *gNB;
@@ -105,18 +107,18 @@ openair0_config_t openair0_cfg[MAX_CARDS];
int main(int argc, char **argv)
{
char c;
- int i,sf;
+ int i;
double SNR, snr0 = -2.0, snr1 = 2.0;
double sigma, sigma_dB;
- double snr_step = 1;
+ double snr_step = .2;
uint8_t snr1set = 0;
- int slot = 0, frame = 0;
+ int slot = 8, frame = 0;
FILE *output_fd = NULL;
//uint8_t write_output_file = 0;
int trial, n_trials = 1, n_errors = 0, n_false_positive = 0, delay = 0;
uint8_t n_tx = 1, n_rx = 1;
//uint8_t transmission_mode = 1;
- uint16_t Nid_cell = 0;
+ //uint16_t Nid_cell = 0;
channel_desc_t *gNB2UE;
uint8_t extended_prefix_flag = 0;
//int8_t interf1 = -21, interf2 = -21;
@@ -124,12 +126,11 @@ int main(int argc, char **argv)
SCM_t channel_model = AWGN; //Rayleigh1_anticorr;
uint16_t N_RB_DL = 106, N_RB_UL = 106, mu = 1;
//unsigned char frame_type = 0;
- int frame_length_complex_samples,frame_length_complex_samples_no_prefix;
NR_DL_FRAME_PARMS *frame_parms;
int loglvl = OAILOG_WARNING;
- uint64_t SSB_positions=0x01;
+ //uint64_t SSB_positions=0x01;
uint16_t nb_symb_sch = 12;
- int start_symbol = 0;
+ int start_symbol = 2;
uint16_t nb_rb = 50;
uint8_t Imcs = 9;
uint8_t precod_nbr_layers = 1;
@@ -143,12 +144,13 @@ int main(int argc, char **argv)
float target_error_rate = 0.01;
int print_perf = 0;
cpuf = get_cpu_freq_GHz();
-
+ int msg3_flag = 0;
UE_nr_rxtx_proc_t UE_proc;
FILE *scg_fd=NULL;
-
+ int ibwps=24;
+ int ibwp_rboffset=41;
if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0 ) {
exit_fun("[NR_ULSIM] Error, configuration module init failed\n");
}
@@ -156,208 +158,236 @@ int main(int argc, char **argv)
//logInit();
randominit(0);
- while ((c = getopt(argc, argv, "d:f:g:h:i:j:l:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) {
+ while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:i:j:kl:m:n:p:r:s:y:z:F:M:N:PR:S:L:")) != -1) {
+ printf("handling optarg %c\n",c);
switch (c) {
/*case 'd':
frame_type = 1;
break;*/
- case 'd':
- delay = atoi(optarg);
- break;
-
- case 'f':
- scg_fd = fopen(optarg, "r");
-
- if (scg_fd == NULL) {
- printf("Error opening %s\n", optarg);
- exit(-1);
- }
-
- break;
-
- case 'g':
- switch ((char) *optarg) {
- case 'A':
- channel_model = SCM_A;
- break;
-
- case 'B':
- channel_model = SCM_B;
- break;
-
- case 'C':
- channel_model = SCM_C;
- break;
-
- case 'D':
- channel_model = SCM_D;
- break;
-
- case 'E':
- channel_model = EPA;
- break;
-
- case 'F':
- channel_model = EVA;
- break;
-
- case 'G':
- channel_model = ETU;
- break;
-
- default:
- printf("Unsupported channel model!\n");
- exit(-1);
- }
-
- break;
+ case 'a':
+ start_symbol = atoi(optarg);
+ AssertFatal(start_symbol >= 0 && start_symbol < 13,"start_symbol %d is not in 0..12\n",start_symbol);
+ break;
+
+ case 'b':
+ nb_symb_sch = atoi(optarg);
+ AssertFatal(nb_symb_sch > 0 && nb_symb_sch < 15,"start_symbol %d is not in 1..14\n",nb_symb_sch);
+ break;
+ case 'c':
+ n_rnti = atoi(optarg);
+ AssertFatal(n_rnti > 0 && n_rnti<=65535,"Illegal n_rnti %x\n",n_rnti);
+ break;
+
+ case 'd':
+ delay = atoi(optarg);
+ break;
+
+ case 'e':
+ msg3_flag = 1;
+ break;
+
+ case 'f':
+ scg_fd = fopen(optarg, "r");
+
+ if (scg_fd == NULL) {
+ printf("Error opening %s\n", optarg);
+ exit(-1);
+ }
+ break;
+
+ case 'g':
+ switch ((char) *optarg) {
+ case 'A':
+ channel_model = SCM_A;
+ break;
+
+ case 'B':
+ channel_model = SCM_B;
+ break;
+
+ case 'C':
+ channel_model = SCM_C;
+ break;
+
+ case 'D':
+ channel_model = SCM_D;
+ break;
+
+ case 'E':
+ channel_model = EPA;
+ break;
+
+ case 'F':
+ channel_model = EVA;
+ break;
+
+ case 'G':
+ channel_model = ETU;
+ break;
+
+ default:
+ printf("Unsupported channel model!\n");
+ exit(-1);
+ }
+
+ break;
+
/*case 'i':
interf1 = atoi(optarg);
break;
-
- case 'j':
+
+ case 'j':
interf2 = atoi(optarg);
break;*/
- case 'l':
- nb_symb_sch = atoi(optarg);
- break;
-
- case 'm':
- Imcs = atoi(optarg);
- break;
-
- case 'n':
- n_trials = atoi(optarg);
- break;
-
- case 'p':
- extended_prefix_flag = 1;
- break;
-
- case 'r':
- nb_rb = atoi(optarg);
- break;
-
- case 's':
- snr0 = atof(optarg);
- printf("Setting SNR0 to %f\n", snr0);
- break;
+ case 'k':
+ printf("Setting threequarter_fs_flag\n");
+ openair0_cfg[0].threequarter_fs= 1;
+ break;
+ case 'l':
+ nb_symb_sch = atoi(optarg);
+ break;
+
+ case 'm':
+ Imcs = atoi(optarg);
+ break;
+
+ case 'n':
+ n_trials = atoi(optarg);
+ break;
+
+ case 'p':
+ extended_prefix_flag = 1;
+ break;
+
+ case 'r':
+ nb_rb = atoi(optarg);
+ break;
+
+ case 's':
+ snr0 = atof(optarg);
+ printf("Setting SNR0 to %f\n", snr0);
+ break;
+
/*
- case 'r':
- ricean_factor = pow(10,-.1*atof(optarg));
- if (ricean_factor>1) {
- printf("Ricean factor must be between 0 and 1\n");
- exit(-1);
- }
- break;
- */
-
+ case 'r':
+ ricean_factor = pow(10,-.1*atof(optarg));
+ if (ricean_factor>1) {
+ printf("Ricean factor must be between 0 and 1\n");
+ exit(-1);
+ }
+ break;
+ */
+
/*case 'x':
transmission_mode = atoi(optarg);
break;*/
+
+ case 'y':
+ n_tx = atoi(optarg);
+
+ if ((n_tx == 0) || (n_tx > 2)) {
+ printf("Unsupported number of tx antennas %d\n", n_tx);
+ exit(-1);
+ }
+
+ break;
+
+ case 'z':
+ n_rx = atoi(optarg);
+
+ if ((n_rx == 0) || (n_rx > 2)) {
+ printf("Unsupported number of rx antennas %d\n", n_rx);
+ exit(-1);
+ }
+
+ break;
+
+ case 'F':
+ input_fd = fopen(optarg, "r");
+
+ if (input_fd == NULL) {
+ printf("Problem with filename %s\n", optarg);
+ exit(-1);
+ }
+
+ break;
+
+ case 'M':
+ // SSB_positions = atoi(optarg);
+ break;
+
+ case 'N':
+ // Nid_cell = atoi(optarg);
+ break;
+
+ case 'R':
+ N_RB_DL = atoi(optarg);
+ N_RB_UL = N_RB_DL;
+ break;
+
+ case 'S':
+ snr1 = atof(optarg);
+ snr1set = 1;
+ printf("Setting SNR1 to %f\n", snr1);
+ break;
+
+ case 'P':
+ print_perf=1;
+ opp_enabled=1;
+ break;
+
+ case 'L':
+ loglvl = atoi(optarg);
+ break;
+
+ default:
+ case 'h':
+ printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]);
+ //printf("-d Use TDD\n");
+ printf("-d Introduce delay in terms of number of samples\n");
+ printf("-f Number of frames to simulate\n");
+ printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n");
+ printf("-h This message\n");
+ //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n");
+ //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n");
+ printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n");
+ printf("-m MCS value\n");
+ printf("-n Number of trials to simulate\n");
+ printf("-p Use extended prefix mode\n");
+ printf("-t Delay spread for multipath channel\n");
+ //printf("-x Transmission mode (1,2,6 for the moment)\n");
+ printf("-y Number of TX antennas used in eNB\n");
+ printf("-z Number of RX antennas used in UE\n");
+ printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n");
+ //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
+ printf("-F Input filename (.txt format) for RX conformance testing\n");
+ printf("-G raw file containing RRC configuration (generated by gNB)\n");
+ printf("-M Multiple SSB positions in burst\n");
+ printf("-N Nid_cell\n");
+ printf("-O oversampling factor (1,2,4,8,16)\n");
+ printf("-R N_RB_DL\n");
+ printf("-S Ending SNR, runs from SNR0 to SNR1\n");
+ printf("-P Print ULSCH performances\n");
+ exit(-1);
+ break;
- case 'y':
- n_tx = atoi(optarg);
-
- if ((n_tx == 0) || (n_tx > 2)) {
- printf("Unsupported number of tx antennas %d\n", n_tx);
- exit(-1);
- }
-
- break;
-
- case 'z':
- n_rx = atoi(optarg);
-
- if ((n_rx == 0) || (n_rx > 2)) {
- printf("Unsupported number of rx antennas %d\n", n_rx);
- exit(-1);
- }
-
- break;
-
- case 'F':
- input_fd = fopen(optarg, "r");
-
- if (input_fd == NULL) {
- printf("Problem with filename %s\n", optarg);
- exit(-1);
- }
-
- break;
-
- case 'M':
- SSB_positions = atoi(optarg);
- break;
-
- case 'N':
- Nid_cell = atoi(optarg);
- break;
-
- case 'R':
- N_RB_DL = atoi(optarg);
- N_RB_UL = N_RB_DL;
- break;
-
- case 'S':
- snr1 = atof(optarg);
- snr1set = 1;
- printf("Setting SNR1 to %f\n", snr1);
- break;
-
- case 'P':
- print_perf=1;
- opp_enabled=1;
- break;
-
- case 'L':
- loglvl = atoi(optarg);
- break;
-
- default:
- case 'h':
- printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n", argv[0]);
- //printf("-d Use TDD\n");
- printf("-d Introduce delay in terms of number of samples\n");
- printf("-f Number of frames to simulate\n");
- printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n");
- printf("-h This message\n");
- //printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n");
- //printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n");
- printf("-s Starting SNR, runs from SNR0 to SNR0 + 10 dB if ending SNR isn't given\n");
- printf("-m MCS value\n");
- printf("-n Number of trials to simulate\n");
- printf("-p Use extended prefix mode\n");
- printf("-t Delay spread for multipath channel\n");
- //printf("-x Transmission mode (1,2,6 for the moment)\n");
- printf("-y Number of TX antennas used in eNB\n");
- printf("-z Number of RX antennas used in UE\n");
- printf("-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file\n");
- //printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
- printf("-F Input filename (.txt format) for RX conformance testing\n");
- printf("-G raw file containing RRC configuration (generated by gNB)\n");
- printf("-M Multiple SSB positions in burst\n");
- printf("-N Nid_cell\n");
- printf("-O oversampling factor (1,2,4,8,16)\n");
- printf("-R N_RB_DL\n");
- printf("-S Ending SNR, runs from SNR0 to SNR1\n");
- printf("-P Print ULSCH performances\n");
- exit(-1);
- break;
}
}
-
+
logInit();
set_glog(loglvl);
T_stdout = 1;
get_softmodem_params()->phy_test = 1;
-
+ get_softmodem_params()->do_ra = 0;
+ get_softmodem_params()->usim_test = 1;
+
+
if (snr1set == 0)
snr1 = snr0 + 10;
@@ -382,18 +412,21 @@ int main(int argc, char **argv)
gNB->UL_INFO.rx_ind.number_of_pdus = 0;
gNB->UL_INFO.crc_ind.number_crcs = 0;
frame_parms = &gNB->frame_parms; //to be initialized I suppose (maybe not necessary for PBCH)
+
+
frame_parms->nb_antennas_tx = n_tx;
frame_parms->nb_antennas_rx = n_rx;
frame_parms->N_RB_DL = N_RB_DL;
frame_parms->N_RB_UL = N_RB_UL;
frame_parms->Ncp = extended_prefix_flag ? EXTENDED : NORMAL;
+
RC.nb_nr_macrlc_inst = 1;
RC.nb_nr_mac_CC = (int*)malloc(RC.nb_nr_macrlc_inst*sizeof(int));
for (i = 0; i < RC.nb_nr_macrlc_inst; i++)
RC.nb_nr_mac_CC[i] = 1;
mac_top_init_gNB();
- gNB_MAC_INST* gNB_mac = RC.nrmac[0];
+ //gNB_MAC_INST* gNB_mac = RC.nrmac[0];
gNB_RRC_INST rrc;
memset((void*)&rrc,0,sizeof(rrc));
@@ -416,6 +449,7 @@ int main(int argc, char **argv)
xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup);
AssertFatal((gNB->if_inst = NR_IF_Module_init(0))!=NULL,"Cannot register interface");
+
gNB->if_inst->NR_PHY_config_req = nr_phy_config_request;
// common configuration
rrc_mac_config_req_gNB(0,0,1,scc,0,0,NULL);
@@ -424,12 +458,14 @@ int main(int argc, char **argv)
phy_init_nr_gNB(gNB,0,0);
N_RB_DL = gNB->frame_parms.N_RB_DL;
+
+
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0];
+
//crcTableInit();
//nr_phy_config_request_sim(gNB, N_RB_DL, N_RB_UL, mu, Nid_cell, SSB_positions);
- frame_length_complex_samples = frame_parms->samples_per_subframe;
- frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP;
//configure UE
UE = malloc(sizeof(PHY_VARS_NR_UE));
@@ -449,7 +485,7 @@ int main(int argc, char **argv)
init_nr_ue_transport(UE, 0);
/*
- for (sf = 0; sf < 2; sf++) {
+ for (int sf = 0; sf < 2; sf++) {
for (i = 0; i < 2; i++) {
UE->ulsch[sf][0][i] = new_nr_ue_ulsch(N_RB_UL, 8, 0);
@@ -477,7 +513,7 @@ int main(int argc, char **argv)
rrc.carrier.MIB = (uint8_t*) malloc(4);
rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0);
- nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup->spCellConfig);
+ nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,secondaryCellGroup);
nr_ue_phy_config_request(&UE_mac->phy_config);
@@ -486,7 +522,11 @@ int main(int argc, char **argv)
NR_gNB_ULSCH_t *ulsch_gNB = gNB->ulsch[UE_id][0];
//nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch_gNB->harq_processes[harq_pid]->ulsch_pdu;
- nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req;
+ nfapi_nr_ul_tti_request_t *UL_tti_req = malloc(sizeof(*UL_tti_req));
+ NR_Sched_Rsp_t *Sched_INFO = malloc(sizeof(*Sched_INFO));
+ memset((void*)Sched_INFO,0,sizeof(*Sched_INFO));
+ Sched_INFO->UL_tti_req=UL_tti_req;
+
nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
NR_UE_ULSCH_t **ulsch_ue = UE->ulsch[0][0];
@@ -506,29 +546,34 @@ int main(int argc, char **argv)
uint16_t number_dmrs_symbols = 0;
unsigned int available_bits;
uint8_t nb_re_dmrs;
- uint8_t length_dmrs = UE->pusch_config.dmrs_UplinkConfig.pusch_maxLength;
unsigned char mod_order;
uint16_t code_rate;
-
- for (i = start_symbol; i < nb_symb_sch; i++)
- number_dmrs_symbols += is_dmrs_symbol(i,
- 0,
- 0,
- 0,
- 0,
- 0,
- nb_symb_sch,
- UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type,
- frame_parms->ofdm_symbol_size);
+ uint8_t ptrs_mcs1 = 2;
+ uint8_t ptrs_mcs2 = 4;
+ uint8_t ptrs_mcs3 = 10;
+ uint16_t n_rb0 = 25;
+ uint16_t n_rb1 = 75;
+ uint8_t mcs_table = 0;
+ uint16_t pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA; // | PUSCH_PDU_BITMAP_PUSCH_PTRS;
+
+ uint8_t length_dmrs = pusch_len1; // [hna] remove dmrs struct
+ uint16_t l_prime_mask = get_l_prime(nb_symb_sch, typeB, pusch_dmrs_pos0, length_dmrs); // [hna] remove dmrs struct
+ uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, Imcs, mcs_table);
+ uint8_t ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, nb_rb);
+
+ if(1<<ptrs_time_density >= nb_symb_sch)
+ pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS
+
+ for (i = 0; i < nb_symb_sch; i++) {
+ number_dmrs_symbols += (l_prime_mask >> i) & 0x01;
+ }
mod_order = nr_get_Qm_ul(Imcs, 0);
- nb_re_dmrs = ((UE->pusch_config.dmrs_UplinkConfig.pusch_dmrs_type == pusch_dmrs_type1) ? 6 : 4) * number_dmrs_symbols;
code_rate = nr_get_code_rate_ul(Imcs, 0);
- available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
- TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, precod_nbr_layers);
printf("\n");
+ for (int i=0;i<16;i++) printf("%f\n",gaussdouble(0.0,1.0));
for (SNR = snr0; SNR < snr1; SNR += snr_step) {
varArray_t *table_rx=initVarArray(1000,sizeof(double));
@@ -570,19 +615,40 @@ int main(int argc, char **argv)
UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t));
- pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
+ int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ int ibwp_size = ibwps;
+ int ibwp_start = ibwp_rboffset;
+ if (msg3_flag == 1) {
+ if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size))
+ pusch_pdu->bwp_start = abwp_start;
+ else
+ pusch_pdu->bwp_start = ibwp_start;
+ pusch_pdu->bwp_size = ibwp_size;
+ start_rb += (ibwp_start - abwp_start);
+ printf("msg3: ibwp_size %d, abwp_size %d, ibwp_start %d, abwp_start %d\n",
+ ibwp_size,abwp_size,ibwp_start,abwp_start);
+ }
+ else {
+ pusch_pdu->bwp_start = abwp_start;
+ pusch_pdu->bwp_size = abwp_size;
+ }
+
+ pusch_pdu->pdu_bit_map = pdu_bit_map;
pusch_pdu->rnti = n_rnti;
pusch_pdu->mcs_index = Imcs;
- pusch_pdu->mcs_table = 0;
+ pusch_pdu->mcs_table = mcs_table;
pusch_pdu->target_code_rate = code_rate;
pusch_pdu->qam_mod_order = mod_order;
- pusch_pdu->transform_precoding = 0;
- pusch_pdu->data_scrambling_id = 0;
+ pusch_pdu->transform_precoding = 1;
+ pusch_pdu->data_scrambling_id = *scc->physCellId;
pusch_pdu->nrOfLayers = 1;
- pusch_pdu->ul_dmrs_symb_pos = 1;
+ pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << start_symbol;
pusch_pdu->dmrs_config_type = 0;
- pusch_pdu->ul_dmrs_scrambling_id = 0;
+ pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
pusch_pdu->scid = 0;
+ pusch_pdu->dmrs_ports = 1;
+ pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
pusch_pdu->resource_alloc = 1;
pusch_pdu->rb_start = start_rb;
pusch_pdu->rb_size = nb_rb;
@@ -594,9 +660,14 @@ int main(int argc, char **argv)
pusch_pdu->pusch_data.rv_index = 0;
pusch_pdu->pusch_data.harq_process_id = 0;
pusch_pdu->pusch_data.new_data_indicator = 0;
- pusch_pdu->pusch_data.tb_size = TBS>>3;
pusch_pdu->pusch_data.num_cb = 0;
+ pusch_pdu->pusch_ptrs.ptrs_time_density = ptrs_time_density;
+ pusch_pdu->pusch_ptrs.ptrs_freq_density = ptrs_freq_density;
+ pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t));
+ pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
+ // prepare ULSCH/PUSCH reception
+ nr_schedule_response(Sched_INFO);
// --------- setting parameters for UE --------
@@ -606,87 +677,163 @@ int main(int argc, char **argv)
scheduled_response.slot = slot;
scheduled_response.dl_config = NULL;
scheduled_response.ul_config = &ul_config;
- scheduled_response.dl_config = NULL;
+ scheduled_response.tx_request = (fapi_nr_tx_request_t *) malloc(sizeof(fapi_nr_tx_request_t));
+ scheduled_response.tx_request->tx_request_body = (fapi_nr_tx_request_body_t *) malloc(sizeof(fapi_nr_tx_request_body_t));
ul_config.slot = slot;
ul_config.number_pdus = 1;
ul_config.ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- ul_config.ul_config_list[0].ulsch_config_pdu.rnti = n_rnti;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = nb_rb;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = start_rb;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = nb_symb_sch;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = start_symbol;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.mcs = Imcs;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers;
- ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = harq_pid;
+ ul_config.ul_config_list[0].pusch_config_pdu.rnti = n_rnti;
+ ul_config.ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map;
+ ul_config.ul_config_list[0].pusch_config_pdu.rb_size = nb_rb;
+ ul_config.ul_config_list[0].pusch_config_pdu.rb_start = start_rb;
+ ul_config.ul_config_list[0].pusch_config_pdu.nr_of_symbols = nb_symb_sch;
+ ul_config.ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol;
+ ul_config.ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = l_prime_mask << start_symbol;
+ ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type = 0;
+ ul_config.ul_config_list[0].pusch_config_pdu.mcs_index = Imcs;
+ ul_config.ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table;
+ ul_config.ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = 0;
+ ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_pid;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t));
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
//there are plenty of other parameters that we don't seem to be using for now. e.g.
- //ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
-
- // set FAPI parameters for UE, put them in the scheduled response and call
- nr_ue_scheduled_response(&scheduled_response);
-
- /////////////////////////phy_procedures_nr_ue_TX///////////////////////
- ///////////
+ ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0;
- phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0);
+ nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4);
- if (n_trials==1)
- LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_length_complex_samples,1,1);
-
- ///////////
- ////////////////////////////////////////////////////
- tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
+ available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1);
+ TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers);
+ pusch_pdu->pusch_data.tb_size = TBS>>3;
+ ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS;
+
+ nr_fill_ulsch(gNB,frame,slot,pusch_pdu);
+ int slot_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);// - (int)(800*factor);
+ int slot_length = slot_offset - frame_parms->get_samples_slot_timestamp(slot-1,frame_parms,0);
+
+ for (int i=0;i<(TBS>>3);i++) ulsch_ue[0]->harq_processes[harq_pid]->a[i]=i&0xff;
+ double scale = 1;
+
+ if (input_fd == NULL) {
+
+ if (SNR==snr0) {
+ // set FAPI parameters for UE, put them in the scheduled response and call
+ nr_ue_scheduled_response(&scheduled_response);
+
+
+ /////////////////////////phy_procedures_nr_ue_TX///////////////////////
+ ///////////
+
+ phy_procedures_nrUE_TX(UE, &UE_proc, gNB_id, 0);
+
+
+ if (n_trials==1) {
+ LOG_M("txsig0.m","txs0", UE->common_vars.txdata[0],frame_parms->samples_per_subframe*10,1,1);
+ LOG_M("txsig0F.m","txs0F", UE->common_vars.txdataF[0],frame_parms->ofdm_symbol_size*14,1,1);
+ }
+ ///////////
+ ////////////////////////////////////////////////////
+ tx_offset = frame_parms->get_samples_slot_timestamp(slot,frame_parms,0);
+
+ txlev = signal_energy(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
+ frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
+
+ txlev_float = (double)txlev/scale; // output of signal_energy is fixed point representation
+
+
+ //AWGN
+ }
+ }
+ else n_trials = 1;
- txlev = signal_energy_amp_shift(&UE->common_vars.txdata[0][tx_offset + 5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
- frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
- txlev_float = (double)txlev/(double)AMP; // output of signal_energy is fixed point representation
+ sigma_dB = 10*log10(txlev_float)-SNR;
+ sigma = pow(10,sigma_dB/10);
+ printf("txlev_float %f, sigma_dB %f\n",10*log10(txlev_float),sigma_dB);
n_errors = 0;
n_false_positive = 0;
- //AWGN
- sigma_dB = 10*log10(txlev_float)-SNR;
- sigma = pow(10,sigma_dB/10);
+ errors_scrambling = 0;
+ errors_decoding = 0;
+ int error_flag;
for (trial = 0; trial < n_trials; trial++) {
-
- errors_scrambling = 0;
- errors_decoding = 0;
-
- //----------------------------------------------------------
- //------------------------ add noise -----------------------
- //----------------------------------------------------------
- for (i=0; i<frame_length_complex_samples; i++) {
- for (ap=0; ap<frame_parms->nb_antennas_rx; ap++) {
- ((short*) gNB->common_vars.rxdata[ap])[(2*i) + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)*(double)AMP); // convert to fixed point
- ((short*) gNB->common_vars.rxdata[ap])[2*i+1 + (delay*2)] = (((int16_t *)UE->common_vars.txdata[ap])[(i<<1)+1]) + (int16_t)(sqrt(sigma/2)*gaussdouble(0.0,1.0)*(double)AMP);
- }
- }
- ////////////////////////////////////////////////////////////
-
- //----------------------------------------------------------
- //------------------- gNB phy procedures -------------------
- //----------------------------------------------------------
- gNB->UL_INFO.rx_ind.number_of_pdus = 0;
- gNB->UL_INFO.crc_ind.number_crcs = 0;
+
+ error_flag = 0;
+ //----------------------------------------------------------
+ //------------------------ add noise -----------------------
+ //----------------------------------------------------------
+ if (input_fd == NULL ) {
+ for (i=0; i<slot_length; i++) {
+ for (ap=0; ap<frame_parms->nb_antennas_rx; ap++) {
+ ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i) + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0))); // convert to fixed point
+ ((int16_t*) &gNB->common_vars.rxdata[ap][slot_offset])[(2*i)+1 + (delay*2)] = (int16_t)((double)(((int16_t *)&UE->common_vars.txdata[ap][slot_offset])[(i<<1)+1])/sqrt(scale) + (sqrt(sigma/2)*gaussdouble(0.0,1.0)));
+ }
+ }
+ }
+ else {
+ AssertFatal(frame_parms->nb_antennas_rx == 1, "nb_ant != 1\n");
+ // 800 samples is N_TA_OFFSET for FR1 @ 30.72 Ms/s,
+ AssertFatal(frame_parms->subcarrier_spacing==30000,"only 30 kHz for file input for now (%d)\n",frame_parms->subcarrier_spacing);
+ double factor = 1;
+ if (openair0_cfg[0].threequarter_fs== 1) factor =.75;
+ int ta_offset=1600;
+ if (N_RB_DL <217) ta_offset=800;
+ else if (N_RB_DL < 106) ta_offset = 400;
+
+ fread((void*)&gNB->common_vars.rxdata[0][slot_offset],
+ sizeof(int16_t),
+ slot_length<<1,
+ input_fd);
+ for (int i=0;i<16;i+=2) printf("slot_offset %d : %d,%d\n",
+ slot_offset,
+ ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[i],
+ ((int16_t*)&gNB->common_vars.rxdata[0][slot_offset])[1+i]);
+ fclose(input_fd);
+ }
+ ////////////////////////////////////////////////////////////
+
+ //----------------------------------------------------------
+ //------------------- gNB phy procedures -------------------
+ //----------------------------------------------------------
+ gNB->UL_INFO.rx_ind.number_of_pdus = 0;
+ gNB->UL_INFO.crc_ind.number_crcs = 0;
start_meas(&gNB->phy_proc_rx);
phy_procedures_gNB_common_RX(gNB, frame, slot);
- if (n_trials==1)
- LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0],frame_length_complex_samples_no_prefix,1,1);
+ if (n_trials==1) {
+ LOG_M("rxsig0.m","rx0",&gNB->common_vars.rxdata[0][0],frame_parms->samples_per_subframe*10,1,1);
+
+ LOG_M("rxsigF0.m","rxsF0",gNB->common_vars.rxdataF[0]+start_symbol*frame_parms->ofdm_symbol_size,nb_symb_sch*frame_parms->ofdm_symbol_size,1,1);
+ }
phy_procedures_gNB_uespec_RX(gNB, frame, slot);
+ if (n_trials == 1) {
+ LOG_M("rxsigF0_ext.m","rxsF0_ext",
+ &gNB->pusch_vars[0]->rxdataF_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1);
+ LOG_M("chestF0.m","chF0",
+ &gNB->pusch_vars[0]->ul_ch_estimates[0][start_symbol*frame_parms->ofdm_symbol_size],frame_parms->ofdm_symbol_size,1,1);
+ LOG_M("chestF0_ext.m","chF0_ext",
+ &gNB->pusch_vars[0]->ul_ch_estimates_ext[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1);
+ LOG_M("rxsigF0_comp.m","rxsF0_comp",
+ &gNB->pusch_vars[0]->rxdataF_comp[0][(start_symbol+1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size],(nb_symb_sch-1)*NR_NB_SC_PER_RB * pusch_pdu->rb_size,1,1);
+ }
start_meas(&gNB->phy_proc_rx);
////////////////////////////////////////////////////////////
if (gNB->ulsch[0][0]->last_iteration_cnt >=
- gNB->ulsch[0][0]->max_ldpc_iterations+1)
+ gNB->ulsch[0][0]->max_ldpc_iterations+1) {
+ error_flag = 1;
n_errors++;
-
+ }
+
//----------------------------------------------------------
//----------------- count and print errors -----------------
//----------------------------------------------------------
@@ -704,7 +851,7 @@ int main(int argc, char **argv)
if (errors_scrambling > 0) {
if (n_trials==1)
- printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %d\n" "\x1B[0m", frame, trial, errors_scrambling);
+ printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in unscrambling = %u\n" "\x1B[0m", frame, trial, errors_scrambling);
}
for (i = 0; i < TBS; i++) {
@@ -718,22 +865,30 @@ int main(int argc, char **argv)
errors_decoding++;
}
}
-
- if (errors_decoding > 0) {
+ if (n_trials == 1) {
+ for (int r=0;r<ulsch_ue[0]->harq_processes[harq_pid]->C;r++)
+ for (int i=0;i<ulsch_ue[0]->harq_processes[harq_pid]->K>>3;i++) {
+ if ((ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]) != 0) printf("************");
+ printf("r %d: in[%d] %x, out[%d] %x (%x)\n",r,
+ i,ulsch_ue[0]->harq_processes[harq_pid]->c[r][i],
+ i,ulsch_gNB->harq_processes[harq_pid]->c[r][i],
+ ulsch_ue[0]->harq_processes[harq_pid]->c[r][i]^ulsch_gNB->harq_processes[harq_pid]->c[r][i]);
+ }
+ }
+ if (errors_decoding > 0 && error_flag == 0) {
n_false_positive++;
if (n_trials==1)
- printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %d\n" "\x1B[0m", frame, trial, errors_decoding);
+ printf("\x1B[31m""[frame %d][trial %d]\tnumber of errors in decoding = %u\n" "\x1B[0m", frame, trial, errors_decoding);
}
-
} // trial loop
printf("*****************************************\n");
- printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %d/%d\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, n_trials);
+ printf("SNR %f: n_errors (negative CRC) = %d/%d, false_positive %d/%d, errors_scrambling %u/%u\n", SNR, n_errors, n_trials, n_false_positive, n_trials, errors_scrambling, available_bits*n_trials);
printf("\n");
printf("SNR %f: Channel BLER %e, Channel BER %e\n", SNR,(double)n_errors/n_trials,(double)errors_scrambling/available_bits/n_trials);
printf("*****************************************\n");
printf("\n");
-
+
if (print_perf==1) {
printDistribution(&gNB->phy_proc_rx,table_rx,"Total PHY proc rx");
printStatIndent(&gNB->ulsch_channel_estimation_stats,"ULSCH channel estimation time");
@@ -759,7 +914,6 @@ int main(int argc, char **argv)
}
} // SNR loop
-
printf("\n");
free(test_input_bit);
@@ -771,5 +925,8 @@ int main(int argc, char **argv)
if (input_fd)
fclose(input_fd);
+ if (scg_fd)
+ fclose(scg_fd);
+
return (n_errors);
}
diff --git a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c
index a93f0d48f3bd0e16c2258eebbfe5e8c136fe7918..cc8c62a36d96511290b28cb15e356b418209b86d 100644
--- a/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c
+++ b/openair1/SIMULATION/NR_UE_PHY/unit_tests/src/dummy_functions.c
@@ -115,6 +115,11 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
sub_frame_t subframe, uint8_t eNB_index,
uint8_t * sync_area, uint8_t * mcch_active){ return(0);}
+
+int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
+ sub_frame_t subframe, uint8_t eNB_index,
+ uint8_t * sync_area, uint8_t * mcch_active){ return(0);}
+
void dl_phy_sync_success(module_id_t module_idP,
frame_t frameP,
unsigned char eNB_index, uint8_t first_sync){}
diff --git a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c
index f4835570bf386eef8435720825d8e620c3b49c37..d344992586f85025abe01b356ccb021ba41a25b0 100644
--- a/openair1/SIMULATION/TOOLS/multipath_tv_channel.c
+++ b/openair1/SIMULATION/TOOLS/multipath_tv_channel.c
@@ -27,18 +27,20 @@
#include "SIMULATION/RF/rf.h"
#include <complex.h>
-void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length);
+void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length);
double frand_a_b(double a, double b);
-void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int delay);
+void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int delay);
void multipath_tv_channel(channel_desc_t *desc,
double **tx_sig_re,
double **tx_sig_im,
double **rx_sig_re,
double **rx_sig_im,
- uint16_t length,
- uint8_t keep_channel) {
- double complex **tx,**rx,* **H_t,*rx_temp; //, *tv_H_t;
+ uint32_t length,
+ uint8_t keep_channel)
+{
+
+ double complex **tx,**rx,***H_t,*rx_temp;//, *tv_H_t;
double path_loss = pow(10,desc->path_loss_dB/20);
int i,j,k,dd;
dd = abs(desc->channel_offset);
@@ -126,7 +128,8 @@ void multipath_tv_channel(channel_desc_t *desc,
}
//TODO: make phi_rad a parameter of this function
-void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) {
+void tv_channel(channel_desc_t *desc,double complex ***H,uint32_t length){
+
int i,j,p,l,k;
double *alpha,*phi_rad,pi=acos(-1),*w_Hz;
alpha = (double *)calloc(desc->nb_paths,sizeof(double));
@@ -193,7 +196,8 @@ void tv_channel(channel_desc_t *desc,double complex ***H,uint16_t length) {
}
// time varying convolution
-void tv_conv(double complex **h, double complex *x, double complex *y, uint16_t nb_samples, uint8_t nb_taps, int dd) {
+void tv_conv(double complex **h, double complex *x, double complex *y, uint32_t nb_samples, uint8_t nb_taps, int dd){
+
int i,j;
for(i=0; i<((int)nb_samples-dd); i++) {
diff --git a/openair1/SIMULATION/TOOLS/random_channel.c b/openair1/SIMULATION/TOOLS/random_channel.c
index 41d8551e75726427f356cc0a78226723ad8bd1ff..f97b9dfb78a1d7bdebd35c8324d1ecac635b3936 100644
--- a/openair1/SIMULATION/TOOLS/random_channel.c
+++ b/openair1/SIMULATION/TOOLS/random_channel.c
@@ -45,8 +45,12 @@ static mapping channelmod_names[] = {
};
static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt);
+static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt);
+static int channelmod_print_help(char *buff, int debug, telnet_printfunc_t prnt);
static telnetshell_cmddef_t channelmod_cmdarray[] = {
- {"show","",channelmod_show_cmd},
+ {"help","",channelmod_print_help},
+ {"show","<predef,current>",channelmod_show_cmd},
+ {"modify","<channelid> <param> <value>",channelmod_modify_cmd},
{"","",NULL},
};
@@ -56,14 +60,15 @@ static telnetshell_vardef_t channelmod_vardef[] = {
static double snr_dB=25;
static double sinr_dB=0;
-
+static unsigned int max_chan;
+static channel_desc_t** defined_channels;
void fill_channel_desc(channel_desc_t *chan_desc,
uint8_t nb_tx,
uint8_t nb_rx,
uint8_t nb_taps,
uint8_t channel_length,
double *amps,
- double *delays,
+ double *delays,
struct complex **R_sqrt,
double Td,
double sampling_rate,
@@ -88,6 +93,7 @@ void fill_channel_desc(channel_desc_t *chan_desc,
if (delays==NULL) {
chan_desc->delays = (double *) malloc(nb_taps*sizeof(double));
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_DELAY ;
delta_tau = Td/nb_taps;
for (i=0; i<nb_taps; i++)
@@ -129,10 +135,9 @@ void fill_channel_desc(channel_desc_t *chan_desc,
if (R_sqrt == NULL) {
chan_desc->R_sqrt = (struct complex **) calloc(nb_taps,sizeof(struct complex *));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_NTAPS ;
for (i = 0; i<nb_taps; i++) {
- chan_desc->R_sqrt[i] = (struct complex *) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex));
-
+ chan_desc->R_sqrt[i] = (struct complex *) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex));
for (j = 0; j<nb_tx*nb_rx*nb_tx*nb_rx; j+=(nb_tx*nb_rx+1)) {
chan_desc->R_sqrt[i][j].x = 1.0;
chan_desc->R_sqrt[i][j].y = 0.0;
@@ -140,7 +145,7 @@ void fill_channel_desc(channel_desc_t *chan_desc,
}
} else {
chan_desc->R_sqrt = (struct complex **) calloc(nb_taps,sizeof(struct complex *));
-
+
for (i = 0; i<nb_taps; i++) {
//chan_desc->R_sqrt[i] = (struct complex*) calloc(nb_tx*nb_rx*nb_tx*nb_rx,sizeof(struct complex));
//chan_desc->R_sqrt = (struct complex*)&R_sqrt[i][0];
@@ -170,7 +175,7 @@ void fill_channel_desc(channel_desc_t *chan_desc,
double mbsfn_delays[] = {0,.03,.15,.31,.37,1.09,12.490,12.52,12.64,12.80,12.86,13.58,27.49,27.52,27.64,27.80,27.86,28.58};
double mbsfn_amps_dB[] = {0,-1.5,-1.4,-3.6,-0.6,-7.0,-10,-11.5,-11.4,-13.6,-10.6,-17.0,-20,-21.5,-21.4,-23.6,-20.6,-27};
-double scm_c_delays[] = {0, 0.0125, 0.0250, 0.3625, 0.3750, 0.3875, 0.2500, 0.2625, 0.2750, 1.0375, 1.0500, 1.0625, 2.7250, 2.7375, 2.7500, 4.6000, 4.6125, 4.6250};
+double scm_c_delays[] = {0, 0.0125, 0.0250, 0.3625, 0.3750, 0.3875, 0.2500, 0.2625, 0.2750, 1.0375, 1.0500, 1.0625, 2.7250, 2.7375, 2.7500, 4.6000, 4.6125, 4.6250};
double scm_c_amps_dB[] = {0.00, -2.22, -3.98, -1.86, -4.08, -5.84, -1.08, -3.30, -5.06, -9.08, -11.30, -13.06, -15.14, -17.36, -19.12, -20.64, -22.85, -24.62};
double epa_delays[] = { 0,.03,.07,.09,.11,.19,.41};
@@ -277,14 +282,26 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
SCM_t channel_model,
double sampling_rate,
double channel_bandwidth,
- double forgetting_factor,
+ double forgetting_factor,
int32_t channel_offset,
double path_loss_dB) {
- channel_desc_t *chan_desc = (channel_desc_t *)malloc(sizeof(channel_desc_t));
+ channel_desc_t *chan_desc = (channel_desc_t *)calloc(1,sizeof(channel_desc_t));
+ for(int i=0; i<max_chan;i++) {
+ if (defined_channels[i] == NULL) {
+ defined_channels[i]=chan_desc;
+ chan_desc->chan_idx=i;
+ break;
+ }
+ else {
+ AssertFatal(i<(max_chan-1),
+ "No more channel descriptors available, increase channelmod.max_chan parameter above %u\n",max_chan);
+ }
+ }
uint16_t i,j;
double sum_amps;
double aoa,ricean_factor,Td,maxDoppler;
int channel_length,nb_taps;
+ chan_desc->modelid = channel_model;
chan_desc->nb_tx = nb_tx;
chan_desc->nb_rx = nb_rx;
chan_desc->sampling_rate = sampling_rate;
@@ -313,7 +330,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*scm_c_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -351,9 +368,10 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
for (i = 0; i<6; i++)
chan_desc->R_sqrt[i] = (struct complex *) &R12_sqrt[i][0];
} else {
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ;
for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
-
+
for (j = 0; j<nb_tx*nb_rx*nb_tx*nb_rx; j+=(nb_tx*nb_rx+1)) {
chan_desc->R_sqrt[i][j].x = 1.0;
chan_desc->R_sqrt[i][j].y = 0.0;
@@ -372,7 +390,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*scm_c_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -410,6 +428,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
for (i = 0; i<6; i++)
chan_desc->R_sqrt[i] = (struct complex *) &R12_sqrt[i][0];
} else {
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ;
for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
@@ -423,14 +442,14 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
}
break;
-
+
case EPA:
chan_desc->nb_taps = 7;
chan_desc->Td = .410;
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -449,7 +468,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
for (i = 0; i<nb_tx*nb_rx; i++)
chan_desc->ch[i] = (struct complex *) malloc(chan_desc->channel_length * sizeof(struct complex));
-
+
for (i = 0; i<nb_tx*nb_rx; i++)
chan_desc->chF[i] = (struct complex *) malloc(1200 * sizeof(struct complex));
@@ -463,7 +482,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0];
} else {
chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ;
for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
@@ -484,7 +503,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -530,7 +549,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
LOG_W(OCM,"correlation matrix only implemented for nb_tx==2 and nb_rx==2, using identity\n");
}
}*/
- break;
+ break;
case EPA_high:
chan_desc->nb_taps = 7;
@@ -538,7 +557,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -592,7 +611,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*epa_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -646,7 +665,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*eva_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -679,8 +698,8 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0];
} else {
chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **));
-
- for (i = 0; i<6; i++) {
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ;
+ for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
for (j = 0; j<nb_tx*nb_rx*nb_tx*nb_rx; j+=(nb_tx*nb_rx+1)) {
@@ -700,7 +719,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*etu_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -733,7 +752,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->R_sqrt[i] = (struct complex *) &R22_sqrt[i][0];
} else {
chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex **));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6 ;
for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
@@ -754,7 +773,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->channel_length = (int) (2*chan_desc->sampling_rate*chan_desc->Td + 1 + 2/(M_PI*M_PI)*log(4*M_PI*chan_desc->sampling_rate*chan_desc->Td));
sum_amps = 0;
chan_desc->amps = (double *) malloc(chan_desc->nb_taps*sizeof(double));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_AMPS ;
for (i = 0; i<chan_desc->nb_taps; i++) {
chan_desc->amps[i] = pow(10,.1*mbsfn_amps_dB[i]);
sum_amps += chan_desc->amps[i];
@@ -781,7 +800,7 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->a[i] = (struct complex *) malloc(nb_tx*nb_rx * sizeof(struct complex));
chan_desc->R_sqrt = (struct complex **) malloc(6*sizeof(struct complex *));
-
+ chan_desc->free_flags=chan_desc->free_flags|CHANMODEL_FREE_RSQRT_6;
for (i = 0; i<6; i++) {
chan_desc->R_sqrt[i] = (struct complex *) malloc(nb_tx*nb_rx*nb_tx*nb_rx * sizeof(struct complex));
@@ -1292,10 +1311,37 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
chan_desc->nb_paths = 10;
return(chan_desc);
}
-
+
void free_channel_desc_scm(channel_desc_t *ch) {
// Must be made cleanly, a lot of leaks...
- free(ch);
+ defined_channels[ch->chan_idx]=NULL;
+ if(ch->free_flags&CHANMODEL_FREE_AMPS)
+ free(ch->amps);
+ for (int i = 0; i<ch->nb_tx*ch->nb_rx; i++) {
+ free(ch->ch[i]);
+ free(ch->chF[i]);
+ }
+
+ for (int i = 0; i<ch->nb_taps; i++) {
+ free(ch->a[i]);
+ }
+ if(ch->free_flags&CHANMODEL_FREE_DELAY)
+ free(ch->delays);
+ if(ch->free_flags&CHANMODEL_FREE_RSQRT_6)
+ for (int i = 0; i<6; i++)
+ free(ch->R_sqrt[i]);
+ if(ch->free_flags&CHANMODEL_FREE_RSQRT_NTAPS)
+ for (int i = 0; i<ch->nb_taps;i++)
+ free(ch->R_sqrt[i]);
+ free(ch->R_sqrt);
+ free(ch->ch);
+ free(ch->chF);
+ free(ch->a);
+ free(ch);
+}
+
+void set_channeldesc_owner(channel_desc_t *cdesc, uint32_t module_id) {
+ cdesc->module_id=module_id;
}
int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) {
@@ -1408,11 +1454,11 @@ int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) {
desc->ch[aarx+(aatx*desc->nb_rx)][k].y = 0.0;
for (l=0; l<desc->nb_taps; l++) {
- if ((k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET) == 0)
+ if ((k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset) == 0)
s = 1.0;
else
- s = sin(M_PI*(k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET))/
- (M_PI*(k - (desc->delays[l]*desc->sampling_rate) - NB_SAMPLES_CHANNEL_OFFSET));
+ s = sin(M_PI*(k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset))/
+ (M_PI*(k - (desc->delays[l]*desc->sampling_rate) - desc->channel_offset));
desc->ch[aarx+(aatx*desc->nb_rx)][k].x += s*desc->a[l][aarx+(aatx*desc->nb_rx)].x;
desc->ch[aarx+(aatx*desc->nb_rx)][k].y += s*desc->a[l][aarx+(aatx*desc->nb_rx)].y;
@@ -1436,7 +1482,7 @@ int random_channel(channel_desc_t *desc, uint8_t abstraction_flag) {
return (0);
}
-
+
double N_RB2sampling_rate(uint16_t N_RB) {
double sampling_rate;
@@ -1488,22 +1534,125 @@ double N_RB2channel_bandwidth(uint16_t N_RB) {
LOG_E(PHY,"Unknown N_PRB\n");
return(-1);
}
-
return(channel_bandwidth);
+}
+
+
+static int channelmod_print_help(char *buff, int debug, telnet_printfunc_t prnt ) {
+ prnt("channelmod commands can be used to display or modify channel models parameters\n");
+ prnt("channelmod show predef: display predefined model algorithms available in oai\n");
+ prnt("channelmod show current: display the currently used models in the running executable\n");
+ prnt("channelmod modify <model index> <param name> <param value>: set the specified parameters in a current model to the given value\n");
+ prnt(" <model index> specifies the model, the show current model command can be used to list the current models indexes\n");
+ prnt(" <param name> can be one of \"riceanf\", \"aoa\", \"randaoa\", \"ploss\", \"offset\", \"forgetf\"\n");
+ return CMDSTATUS_FOUND;
}
+
+static void display_channelmodel(channel_desc_t *cd,int debug, telnet_printfunc_t prnt) {
+ char *module_id_str[]=MODULEID_STR_INIT;
+ if (cd->module_id != 0) {
+ prnt("model owner: %s\n",module_id_str[cd->module_id]);
+ }
+ prnt("nb_tx: %i nb_rx: %i taps: %i bandwidth: %lf sampling: %lf\n",cd->nb_tx, cd->nb_rx, cd->nb_taps, cd->channel_bandwidth, cd->sampling_rate);
+ prnt("channel length: %i Max path delay: %lf ricean fact.: %lf angle of arrival: %lf (randomized:%s)\n",
+ cd->channel_length, cd->Td, cd->ricean_factor, cd->aoa, (cd->random_aoa?"Yes":"No"));
+ prnt("max Doppler: %lf path loss: %lf rchannel offset: %i forget factor; %lf\n",
+ cd->max_Doppler, cd->path_loss_dB, cd->channel_offset, cd->forgetting_factor);
+ prnt("Initial phase: %lf nb_path: %i \n",
+ cd->ip, cd->nb_paths);
+ for (int i=0; i<cd->nb_taps ; i++) {
+ prnt("taps: %i lin. ampli. : %lf delay: %lf \n",i,cd->amps[i], cd->delays[i]);
+ }
+}
+
+
static int channelmod_show_cmd(char *buff, int debug, telnet_printfunc_t prnt) {
- for(int i=0; channelmod_names[i].name != NULL ; i++) {
- prnt(" %i %s\n", i, map_int_to_str(channelmod_names,i ));
+ char *subcmd=NULL;
+ int s = sscanf(buff,"%ms\n",&subcmd);
+
+ if (s>0) {
+ if ( strcmp(subcmd,"predef") == 0) {
+ for (int i=0; channelmod_names[i].name != NULL ; i++) {
+ prnt(" %i %s\n", i, map_int_to_str(channelmod_names,i ));
+ }
+ } else if ( strcmp(subcmd,"current") == 0) {
+ for (int i=0; i < max_chan ; i++) {
+ if (defined_channels[i] != NULL) {
+ prnt("model %i %s: \n----------------\n", i, map_int_to_str(channelmod_names,defined_channels[i]->modelid));
+ display_channelmodel(defined_channels[i],debug,prnt);
+ }
+ }
+ } else {
+ channelmod_print_help(buff, debug, prnt);
+ }
+ free(subcmd);
}
-
- return 0;
+ return CMDSTATUS_FOUND;
}
-int modelid_fromname(char *modelname) {
- int modelid=map_str_to_int(channelmod_names,modelname);
- AssertFatal(modelid>0,
- "random_channel.c: Error channel model %s unknown\n",modelname);
+
+
+static int channelmod_modify_cmd(char *buff, int debug, telnet_printfunc_t prnt) {
+ char *param=NULL, *value=NULL;
+ int cd_id= -1;
+ int s = sscanf(buff,"%i %ms %ms \n",&cd_id,¶m, &value);
+ if (cd_id<0 || cd_id >= max_chan) {
+ prnt("ERROR, %i: Channel model id outof range (0-%i)\n",cd_id,max_chan-1);
+ return CMDSTATUS_FOUND;
+ }
+ if (defined_channels[cd_id]==NULL) {
+ prnt("ERROR, %i: Channel model has not been set\n",cd_id);
+ return CMDSTATUS_FOUND;
+ }
+
+ if (s==3) {
+ if ( strcmp(param,"riceanf") == 0) {
+ double dbl = atof(value);
+ if (dbl <0 || dbl > 1)
+ prnt("ERROR: ricean factor range: 0 to 1, %lf is outof range\n",dbl);
+ else
+ defined_channels[cd_id]->ricean_factor=dbl;
+ } else if ( strcmp(param,"aoa") == 0) {
+ double dbl = atof(value);
+ if (dbl <0 || dbl >6.28)
+ prnt("ERROR: angle of arrival range: 0 to 2*Pi, %lf is outof range\n",dbl);
+ else
+ defined_channels[cd_id]->aoa=dbl;
+ } else if ( strcmp(param,"randaoa") == 0) {
+ int i = atoi(value);
+ if (i!=0 && i!=1)
+ prnt("ERROR: randaoa is a boolean, must be 0 or 1\n");
+ else
+ defined_channels[cd_id]->random_aoa=i;
+ } else if ( strcmp(param,"ploss") == 0) {
+ double dbl = atof(value);
+ defined_channels[cd_id]->path_loss_dB=dbl;
+ } else if ( strcmp(param,"offset") == 0) {
+ int i = atoi(value);
+ defined_channels[cd_id]->channel_offset=i;
+ } else if ( strcmp(param,"forgetf") == 0) {
+ double dbl = atof(value);
+ if (dbl <0 || dbl > 1)
+ prnt("ERROR: forgetting factor range: 0 to 1 (disable variation), %lf is outof range\n",dbl);
+ else
+ defined_channels[cd_id]->forgetting_factor=dbl;
+ } else {
+ prnt("ERROR: %s, unknown channel parameter\n",param);
+ return CMDSTATUS_FOUND;
+ }
+ display_channelmodel(defined_channels[cd_id],debug,prnt);
+ free(param);
+ free(value);
+ random_channel(defined_channels[cd_id],false);
+ }
+ return CMDSTATUS_FOUND;
+}
+
+int modelid_fromname(char *modelname) {
+ int modelid=map_str_to_int(channelmod_names,modelname);
+ if (modelid < 0)
+ LOG_E(OCM,"random_channel.c: Error channel model %s unknown\n",modelname);
return modelid;
}
@@ -1519,6 +1668,9 @@ void init_channelmod(void) {
paramdef_t channelmod_params[] = CHANNELMOD_PARAMS_DESC;
int ret = config_get( channelmod_params,sizeof(channelmod_params)/sizeof(paramdef_t),CHANNELMOD_SECTION);
AssertFatal(ret >= 0, "configuration couldn't be performed");
+ defined_channels=calloc(max_chan,sizeof( channel_desc_t*));
+ AssertFatal(defined_channels!=NULL, "couldn't allocate %u channel descriptors\n",max_chan);
+
/* look for telnet server, if it is loaded, add the channel modeling commands to it */
add_telnetcmd_func_t addcmd = (add_telnetcmd_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_ADDCMD_FNAME);
diff --git a/openair1/SIMULATION/TOOLS/sim.h b/openair1/SIMULATION/TOOLS/sim.h
index 0bc5975d99bb6d17f8a326e7da5f6f9685e3aecd..cc06e2f85c784ad0b196c3be29f40a695389cfeb 100644
--- a/openair1/SIMULATION/TOOLS/sim.h
+++ b/openair1/SIMULATION/TOOLS/sim.h
@@ -40,6 +40,16 @@ The present clause specifies several numerical functions for testing of digital
#define NB_SAMPLES_CHANNEL_OFFSET 4
+typedef enum {
+ UNSPECIFIED_MODID=0,
+ RFSIMU_MODULEID=1
+} channelmod_moduleid_t;
+#define MODULEID_STR_INIT {"","rfsimulator"}
+
+#define CHANMODEL_FREE_DELAY 1<<0
+#define CHANMODEL_FREE_RSQRT_6 1<<1
+#define CHANMODEL_FREE_RSQRT_NTAPS 1<<2
+#define CHANMODEL_FREE_AMPS 1<<3
typedef struct {
///Number of tx antennas
uint8_t nb_tx;
@@ -92,6 +102,14 @@ typedef struct {
time_stats_t interp_time;
time_stats_t interp_freq;
time_stats_t convolution;
+ /// index in the channel descriptors array
+ unsigned int chan_idx;
+ /// id of the channel modeling algorithm
+ int modelid;
+ /// identifies channel descriptor owner (the module which created this descriptor)
+ channelmod_moduleid_t module_id;
+ /// flags to properly trigger memory free
+ unsigned int free_flags;
} channel_desc_t;
typedef struct {
@@ -214,8 +232,9 @@ typedef enum {
#define CONFIG_HLP_SNR "Set average SNR in dB (for --siml1 option)\n"
#define CHANNELMOD_SECTION "channelmod"
#define CHANNELMOD_PARAMS_DESC { \
- {"s" , CONFIG_HLP_SNR, PARAMFLAG_CMDLINE_NOPREFIXENABLED, dblptr:&snr_dB , defdblval:25, TYPE_DOUBLE, 0},\
- {"sinr_dB", NULL , 0 , dblptr:&sinr_dB, defdblval:0 , TYPE_DOUBLE, 0},\
+ {"s" , CONFIG_HLP_SNR, PARAMFLAG_CMDLINE_NOPREFIXENABLED, dblptr:&snr_dB, defdblval:25, TYPE_DOUBLE, 0},\
+ {"sinr_dB", NULL, 0 , dblptr:&sinr_dB, defdblval:0 , TYPE_DOUBLE, 0},\
+ {"max_chan, CONFIG_HLP_MAX_CHAN", 0, uptr:&max_chan, defintval:10, TYPE_UINT, 0},\
}
#include "platform_constants.h"
@@ -273,9 +292,18 @@ channel_desc_t *new_channel_desc_scm(uint8_t nb_tx,
double forgetting_factor,
int32_t channel_offset,
double path_loss_dB);
+/**
+\brief free memory allocated for a model descriptor
+\param ch points to the model, which cannot be used after calling this fuction
+*/
+void free_channel_desc_scm(channel_desc_t *ch);
-
-
+/**
+\brief This set the ownerid of a model descriptor, can be later used to check what module created a channel model
+\param cdesc points to the model descriptor
+\param module_id identifies the channel model. should be define as a macro in simu.h
+*/
+void set_channeldesc_owner(channel_desc_t *cdesc, channelmod_moduleid_t module_id);
/** \fn void random_channel(channel_desc_t *desc)
\brief This routine generates a random channel response (time domain) according to a tapped delay line model.
\param desc Pointer to the channel descriptor
@@ -426,21 +454,12 @@ void multipath_tv_channel(channel_desc_t *desc,
double **tx_sig_im,
double **rx_sig_re,
double **rx_sig_im,
- uint16_t length,
+ uint32_t length,
uint8_t keep_channel);
/**@} */
/**@} */
-void rxAddInput( struct complex16 *input_sig,
- struct complex16 *after_channel_sig,
- int rxAnt,
- channel_desc_t *channelDesc,
- int nbSamples,
- uint64_t TS,
- uint32_t CirSize
- );
-
int modelid_fromname(char *modelname);
double channelmod_get_snr_dB(void);
double channelmod_get_sinr_dB(void);
diff --git a/openair1/SIMULATION/TOOLS/taus.c b/openair1/SIMULATION/TOOLS/taus.c
index 5fe0ce4d7887a36b6888629a3c97d985988803cc..cdd4aebec3dff23605946f97d1fb45e3e9ba81f1 100644
--- a/openair1/SIMULATION/TOOLS/taus.c
+++ b/openair1/SIMULATION/TOOLS/taus.c
@@ -21,7 +21,8 @@
#include <time.h>
#include <stdlib.h>
-#include "SIMULATION/TOOLS/sim.h"
+//#include "SIMULATION/TOOLS/sim.h"
+
unsigned int s0, s1, s2, b;
diff --git a/openair2/COMMON/m2ap_messages_def.h b/openair2/COMMON/m2ap_messages_def.h
index adad70c9cc429458d297b827565b402f83ad6977..743ca126fbe257e4b5446804538a43513cae9327 100644
--- a/openair2/COMMON/m2ap_messages_def.h
+++ b/openair2/COMMON/m2ap_messages_def.h
@@ -50,6 +50,7 @@ MESSAGE_DEF(M2AP_DEREGISTERED_ENB_IND , MESSAGE_PRIORITY_MED, m2ap_der
/* M2AP -> SCTP */
MESSAGE_DEF(M2AP_MCE_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_mce_sctp_req_t , m2ap_mce_sctp_req)
+MESSAGE_DEF(M2AP_ENB_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_enb_sctp_req_t , m2ap_enb_sctp_req)
//MESSAGE_DEF(M2AP_ENB_SCTP_REQ , MESSAGE_PRIORITY_MED, m2ap_enb_setup_req_t , f1ap_enb_setup_req)
/* eNB_DU application layer -> M2AP messages or CU M2AP -> RRC*/
diff --git a/openair2/COMMON/m2ap_messages_types.h b/openair2/COMMON/m2ap_messages_types.h
index 501414f296eaabe725f7aa26b77a475387731936..c70c50fc642517e5e7f7bf095d41f5c6a1256744 100644
--- a/openair2/COMMON/m2ap_messages_types.h
+++ b/openair2/COMMON/m2ap_messages_types.h
@@ -480,7 +480,7 @@ typedef struct m2ap_mbms_scheduling_information_s {
uint8_t common_sf_allocation_period;
uint8_t mbms_area_id;
struct{
- uint8_t allocated_sf_end;
+ uint16_t allocated_sf_end;
uint8_t data_mcs;
uint8_t mch_scheduling_period;
struct{
@@ -533,6 +533,15 @@ typedef struct m2ap_mce_sctp_req_s {
uint32_t mce_port_for_M2C;
}m2ap_mce_sctp_req_t;
+typedef struct m2ap_enb_sctp_req_s {
+ /* The local MCE IP address to bind */
+ net_ip_address_t enb_m2_ip_address;
+
+ /* eNB port for M2C*/
+ uint32_t enb_port_for_M2C;
+}m2ap_enb_sctp_req_t;
+
+
typedef struct m2ap_mbms_scheduling_information_resp_s {
} m2ap_mbms_scheduling_information_resp_t;
typedef struct m2ap_session_start_req_s {
diff --git a/openair2/COMMON/platform_constants.h b/openair2/COMMON/platform_constants.h
index 7a7e984aca0cbb7cce60c25b2890d79d61fa39d8..77f7e26c67345dba27778cfed6270e574a880cfa 100644
--- a/openair2/COMMON/platform_constants.h
+++ b/openair2/COMMON/platform_constants.h
@@ -73,7 +73,9 @@
#ifdef UESIM_EXPANSION
#define MAX_MOBILES_PER_ENB 256
#define MAX_MOBILES_PER_ENB_NB_IoT 256
+ #define MAX_MOBILES_PER_GNB 256
#define MAX_eNB 2
+ #define MAX_gNB 2
#else
#ifdef LARGE_SCALE
#define MAX_MOBILES_PER_ENB 128
@@ -99,6 +101,7 @@
#define NUMBER_OF_NR_DLSCH_MAX 2//16
#define NUMBER_OF_NR_ULSCH_MAX 2//16
+#define NUMBER_OF_NR_PUCCH_MAX 2
#define NUMBER_OF_NR_SR_MAX 16
diff --git a/openair2/COMMON/s1ap_messages_def.h b/openair2/COMMON/s1ap_messages_def.h
index 57201721ced6b4019577343a897bae1bdb3db2cd..5e5794fc55dc81a482d7942368b2b7d6dc46c7ea 100644
--- a/openair2/COMMON/s1ap_messages_def.h
+++ b/openair2/COMMON/s1ap_messages_def.h
@@ -66,6 +66,7 @@ MESSAGE_DEF(S1AP_E_RAB_MODIFY_RESP , MESSAGE_PRIORITY_MED, s1ap_e_rab_m
MESSAGE_DEF(S1AP_E_RAB_RELEASE_RESPONSE , MESSAGE_PRIORITY_MED, s1ap_e_rab_release_resp_t , s1ap_e_rab_release_resp)
MESSAGE_DEF(S1AP_PATH_SWITCH_REQ , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_t , s1ap_path_switch_req)
MESSAGE_DEF(S1AP_PATH_SWITCH_REQ_ACK , MESSAGE_PRIORITY_MED, s1ap_path_switch_req_ack_t , s1ap_path_switch_req_ack)
+MESSAGE_DEF(S1AP_E_RAB_MODIFICATION_IND , MESSAGE_PRIORITY_MED, s1ap_e_rab_modification_ind_t , s1ap_e_rab_modification_ind)
/* S1AP -> RRC messages */
MESSAGE_DEF(S1AP_DOWNLINK_NAS , MESSAGE_PRIORITY_MED, s1ap_downlink_nas_t , s1ap_downlink_nas )
diff --git a/openair2/COMMON/s1ap_messages_types.h b/openair2/COMMON/s1ap_messages_types.h
index aa718dbcf888507bff2c653729bf169314b128fb..befab4ebdf9440586192bad4d692ad40c3dd80bd 100644
--- a/openair2/COMMON/s1ap_messages_types.h
+++ b/openair2/COMMON/s1ap_messages_types.h
@@ -45,6 +45,7 @@
#define S1AP_E_RAB_MODIFY_RESP(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modify_resp
#define S1AP_PATH_SWITCH_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req
#define S1AP_PATH_SWITCH_REQ_ACK(mSGpTR) (mSGpTR)->ittiMsg.s1ap_path_switch_req_ack
+#define S1AP_E_RAB_MODIFICATION_IND(mSGpTR) (mSGpTR)->ittiMsg.s1ap_e_rab_modification_ind
#define S1AP_DOWNLINK_NAS(mSGpTR) (mSGpTR)->ittiMsg.s1ap_downlink_nas
#define S1AP_INITIAL_CONTEXT_SETUP_REQ(mSGpTR) (mSGpTR)->ittiMsg.s1ap_initial_context_setup_req
@@ -78,7 +79,6 @@
* the key length is 32 bytes (256 bits)
*/
#define SECURITY_KEY_LENGTH 32
-#ifndef OCP_FRAMEWORK
typedef enum cell_type_e {
CELL_MACRO_ENB,
CELL_HOME_ENB,
@@ -110,7 +110,6 @@ typedef enum cn_domain_s {
CN_DOMAIN_PS = 1,
CN_DOMAIN_CS = 2
} cn_domain_t;
-#endif
typedef struct net_ip_address_s {
unsigned ipv4:1;
@@ -126,7 +125,6 @@ typedef struct ambr_s {
bitrate_t br_dl;
} ambr_t;
-#ifndef OCP_FRAMEWORK
typedef enum priority_level_s {
PRIORITY_LEVEL_SPARE = 0,
PRIORITY_LEVEL_HIGHEST = 1,
@@ -145,7 +143,6 @@ typedef enum pre_emp_vulnerability_e {
PRE_EMPTION_VULNERABILITY_DISABLED = 1,
PRE_EMPTION_VULNERABILITY_MAX,
} pre_emp_vulnerability_t;
-#endif
typedef struct allocation_retention_priority_s {
priority_level_t priority_level;
@@ -281,12 +278,26 @@ typedef struct e_rab_tobe_added_s {
uint8_t drb_ID;
/* The transport layer address for the IP packets */
- transport_layer_addr_t eNB_addr;
+ transport_layer_addr_t sgw_addr;
/* S-GW Tunnel endpoint identifier */
uint32_t gtp_teid;
} e_rab_tobe_added_t;
+typedef struct e_rab_admitted_tobe_added_s {
+ /* Unique e_rab_id for the UE. */
+ uint8_t e_rab_id;
+
+ /* Unique drb_ID for the UE. */
+ uint8_t drb_ID;
+
+ /* The transport layer address for the IP packets */
+ transport_layer_addr_t gnb_addr;
+
+ /* S-GW Tunnel endpoint identifier */
+ uint32_t gtp_teid;
+} e_rab_admitted_tobe_added_t;
+
typedef struct e_rab_tobeswitched_s {
@@ -646,6 +657,27 @@ typedef struct s1ap_path_switch_req_ack_s {
} s1ap_path_switch_req_ack_t;
+typedef struct s1ap_e_rab_modification_ind_s {
+
+ unsigned eNB_ue_s1ap_id:24;
+
+ /* MME UE id */
+ uint32_t mme_ue_s1ap_id;
+
+ /* Number of e_rab setup-ed in the list */
+ uint8_t nb_of_e_rabs_tobemodified;
+
+ uint8_t nb_of_e_rabs_nottobemodified;
+
+ /* list of e_rab setup-ed by RRC layers */
+ e_rab_setup_t e_rabs_tobemodified[S1AP_MAX_E_RAB];
+
+ e_rab_setup_t e_rabs_nottobemodified[S1AP_MAX_E_RAB];
+
+ uint16_t ue_initial_id;
+
+} s1ap_e_rab_modification_ind_t;
+
// S1AP --> RRC messages
typedef struct s1ap_ue_release_command_s {
diff --git a/openair2/COMMON/x2ap_messages_types.h b/openair2/COMMON/x2ap_messages_types.h
index ed3470a7d6bae365aab1ac30ccb223a32249e964..f0743e60a52daaedd91cfc3afdb225f4eac8e856 100644
--- a/openair2/COMMON/x2ap_messages_types.h
+++ b/openair2/COMMON/x2ap_messages_types.h
@@ -315,7 +315,7 @@ typedef struct x2ap_senb_addition_req_ack_s {
typedef struct x2ap_ENDC_sgnb_addition_req_s {
int ue_x2_id;
-
+ LTE_PhysCellId_t target_physCellId;
/* used for RRC->X2AP in source eNB */
int rnti;
@@ -363,7 +363,7 @@ typedef struct x2ap_ENDC_sgnb_addition_req_ACK_s {
uint8_t nb_e_rabs_admitted_tobeadded;
/* list of e_rab to be added by RRC layers */
- e_rab_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB];
+ e_rab_admitted_tobe_added_t e_rabs_admitted_tobeadded[S1AP_MAX_E_RAB];
/* list of e_rab to be setup by RRC layers */
e_rab_t e_rab_param[S1AP_MAX_E_RAB];
@@ -386,6 +386,7 @@ typedef struct x2ap_ENDC_reconf_complete_s {
int MeNB_ue_x2_id;
int SgNB_ue_x2_id;
+ LTE_PhysCellId_t target_physCellId;
x2ap_sgNB_reconf_response_information_t reconf_response;
diff --git a/openair2/DOCS/TEMPLATES/CODE/example_doxy.h b/openair2/DOCS/TEMPLATES/CODE/example_doxy.h
index c51bdbccabc2ea6bb007b728567e7c8b62f9ac05..30d8ddb600923498440a57bb32f961409e0c4653 100644
--- a/openair2/DOCS/TEMPLATES/CODE/example_doxy.h
+++ b/openair2/DOCS/TEMPLATES/CODE/example_doxy.h
@@ -31,6 +31,9 @@
* \warning this is a warning
*/
+#ifndef __DOCS_TEMPLATES_CODE_EXAMPLE_DOXY__H__
+#define __DOCS_TEMPLATES_CODE_EXAMPLE_DOXY__H__
+
//-----------------------------------begin group-----------------------------
@@ -138,3 +141,4 @@ struct frame {
int init(int src, int dst);
//-----------------------end func proto-------------------
+#endif
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c
index 975ac4e96ff5ae3c2492c7a374bcd5359f56a517..f1daacbb650225f681330339e8870603d8a73b2d 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.c
@@ -49,18 +49,13 @@ struct lfds700_misc_prng_state ps[NUM_MAX_ENB];
struct lfds700_ringbuffer_element *dl_mac_config_array[NUM_MAX_ENB];
struct lfds700_ringbuffer_state ringbuffer_state[NUM_MAX_ENB];
-/* the slice config as kept in the underlying system */
-Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES];
-/* a structure that keeps updates which will be reflected in slice_config later */
-Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES];
-/* indicates whether sc_update contains new data */
-int perform_slice_config_update_count = 1;
-/* queue of incoming new UE<>slice association commands */
-Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES];
-int n_ue_slice_assoc_updates = 0;
-/* mutex for sc_update: do not receive new config and write it at the same time */
-pthread_mutex_t sc_update_mtx = PTHREAD_MUTEX_INITIALIZER;
+/* Ringbuffer-related to slice configuration */
+struct lfds700_ringbuffer_element *slice_config_array[NUM_MAX_ENB];
+struct lfds700_ringbuffer_state slice_config_ringbuffer_state[NUM_MAX_ENB];
+/* Ringbuffer-related to slice configuration */
+struct lfds700_ringbuffer_element *ue_assoc_array[NUM_MAX_ENB];
+struct lfds700_ringbuffer_state ue_assoc_ringbuffer_state[NUM_MAX_ENB];
int flexran_agent_mac_stats_reply_ue(mid_t mod_id,
Protocol__FlexUeStatsReport **ue_report,
@@ -1354,6 +1349,33 @@ void flexran_agent_init_mac_agent(mid_t mod_id) {
AssertFatal(i == 0, "posix_memalign(): could not allocate aligned memory for lfds library\n");
lfds700_ringbuffer_init_valid_on_current_logical_core(&ringbuffer_state[mod_id],
dl_mac_config_array[mod_id], num_elements, &ps[mod_id], NULL);
+
+ struct lfds700_misc_prng_state scrng;
+ i = posix_memalign((void **) &slice_config_array[mod_id],
+ LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES,
+ sizeof(struct lfds700_ringbuffer_element) * num_elements);
+ AssertFatal(i == 0,
+ "posix_memalign(): could not allocate aligned memory\n");
+ lfds700_ringbuffer_init_valid_on_current_logical_core(
+ &slice_config_ringbuffer_state[mod_id],
+ slice_config_array[mod_id],
+ num_elements,
+ &scrng,
+ NULL);
+
+ struct lfds700_misc_prng_state uarng;
+ i = posix_memalign((void **) &ue_assoc_array[mod_id],
+ LFDS700_PAL_ATOMIC_ISOLATION_IN_BYTES,
+ sizeof(struct lfds700_ringbuffer_element) * num_elements);
+ AssertFatal(i == 0,
+ "posix_memalign(): could not allocate aligned memory\n");
+ lfds700_ringbuffer_init_valid_on_current_logical_core(
+ &ue_assoc_ringbuffer_state[mod_id],
+ ue_assoc_array[mod_id],
+ num_elements,
+ &uarng,
+ NULL);
+
for (i = 0; i < MAX_MOBILES_PER_ENB; i++) {
for (j = 0; j < 8; j++) {
if (RC.mac && RC.mac[mod_id])
@@ -1465,9 +1487,74 @@ void flexran_agent_fill_mac_cell_config(mid_t mod_id, uint8_t cc_id,
conf->si_config->has_sfn = 1;
}
- /* get a pointer to the config which is maintained in the agent throughout
- * its lifetime */
- conf->slice_config = flexran_agent_get_slice_config(mod_id);
+ conf->slice_config = malloc(sizeof(Protocol__FlexSliceConfig));
+ if (conf->slice_config) {
+ protocol__flex_slice_config__init(conf->slice_config);
+ Protocol__FlexSliceConfig *sc = conf->slice_config;
+
+ sc->dl = malloc(sizeof(Protocol__FlexSliceDlUlConfig));
+ DevAssert(sc->dl);
+ protocol__flex_slice_dl_ul_config__init(sc->dl);
+ sc->dl->algorithm = flexran_get_dl_slice_algo(mod_id);
+ sc->dl->has_algorithm = 1;
+ sc->dl->n_slices = flexran_get_num_dl_slices(mod_id);
+ if (sc->dl->n_slices > 0) {
+ sc->dl->slices = calloc(sc->dl->n_slices, sizeof(Protocol__FlexSlice *));
+ DevAssert(sc->dl->slices);
+ for (int i = 0; i < sc->dl->n_slices; ++i) {
+ sc->dl->slices[i] = malloc(sizeof(Protocol__FlexSlice));
+ DevAssert(sc->dl->slices[i]);
+ protocol__flex_slice__init(sc->dl->slices[i]);
+ flexran_get_dl_slice(mod_id, i, sc->dl->slices[i], sc->dl->algorithm);
+ }
+ } else {
+ sc->dl->scheduler = flexran_get_dl_scheduler_name(mod_id);
+ }
+
+ sc->ul = malloc(sizeof(Protocol__FlexSliceDlUlConfig));
+ DevAssert(sc->ul);
+ protocol__flex_slice_dl_ul_config__init(sc->ul);
+ sc->ul->algorithm = flexran_get_ul_slice_algo(mod_id);
+ sc->ul->has_algorithm = 1;
+ sc->ul->n_slices = flexran_get_num_ul_slices(mod_id);
+ if (sc->ul->n_slices > 0) {
+ sc->ul->slices = calloc(sc->ul->n_slices, sizeof(Protocol__FlexSlice *));
+ DevAssert(sc->ul->slices);
+ for (int i = 0; i < sc->ul->n_slices; ++i) {
+ sc->ul->slices[i] = malloc(sizeof(Protocol__FlexSlice));
+ DevAssert(sc->ul->slices[i]);
+ protocol__flex_slice__init(sc->ul->slices[i]);
+ flexran_get_ul_slice(mod_id, i, sc->ul->slices[i], sc->ul->algorithm);
+ }
+ } else {
+ sc->ul->scheduler = flexran_get_ul_scheduler_name(mod_id);
+ }
+ }
+}
+
+void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf) {
+ Protocol__FlexSliceConfig *sc = conf->slice_config;
+ for (int i = 0; i < sc->dl->n_slices; ++i) {
+ free(sc->dl->slices[i]);
+ sc->dl->slices[i] = NULL;
+ /* scheduler names are not freed: we assume we read them directly from the
+ * underlying memory and do not dispose it */
+ }
+ free(sc->dl->slices);
+ /* scheduler name is not freed */
+ free(sc->dl);
+ sc->dl = NULL;
+ for (int i = 0; i < sc->ul->n_slices; ++i) {
+ free(sc->ul->slices[i]);
+ sc->ul->slices[i] = NULL;
+ /* scheduler names are not freed */
+ }
+ free(sc->ul->slices);
+ /* scheduler name is not freed */
+ free(sc->ul);
+ sc->ul = NULL;
+ free(conf->slice_config);
+ conf->slice_config = NULL;
}
void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id,
@@ -1481,10 +1568,12 @@ void flexran_agent_fill_mac_ue_config(mid_t mod_id, mid_t ue_id,
ue_conf->rnti = flexran_get_mac_ue_crnti(mod_id, ue_id);
ue_conf->has_rnti = 1;
- ue_conf->dl_slice_id = flexran_get_ue_dl_slice_id(mod_id, ue_id);
- ue_conf->has_dl_slice_id = 1;
- ue_conf->ul_slice_id = flexran_get_ue_ul_slice_id(mod_id, ue_id);
- ue_conf->has_ul_slice_id = 1;
+ int dl_id = flexran_get_ue_dl_slice_id(mod_id, ue_id);
+ ue_conf->dl_slice_id = dl_id;
+ ue_conf->has_dl_slice_id = dl_id >= 0;
+ int ul_id = flexran_get_ue_ul_slice_id(mod_id, ue_id);
+ ue_conf->ul_slice_id = ul_id;
+ ue_conf->has_ul_slice_id = ul_id >= 0;
ue_conf->ue_aggregated_max_bitrate_ul = flexran_get_ue_aggregated_max_bitrate_ul(mod_id, ue_id);
ue_conf->has_ue_aggregated_max_bitrate_ul = 1;
@@ -1565,6 +1654,15 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id)
LOG_E(FLEXRAN_AGENT, "MAC agent CM for eNB %d is not registered\n", mod_id);
return -1;
}
+
+ lfds700_ringbuffer_cleanup(&ringbuffer_state[mod_id], NULL );
+ free(dl_mac_config_array[mod_id]);
+ lfds700_ringbuffer_cleanup(&slice_config_ringbuffer_state[mod_id], NULL );
+ free(slice_config_array[mod_id]);
+ lfds700_ringbuffer_cleanup(&ue_assoc_ringbuffer_state[mod_id], NULL );
+ free(ue_assoc_array[mod_id]);
+ lfds700_misc_library_cleanup();
+
AGENT_MAC_xface *xface = agent_mac_xface[mod_id];
xface->flexran_agent_send_sr_info = NULL;
xface->flexran_agent_send_sf_trigger = NULL;
@@ -1579,234 +1677,91 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id)
return 0;
}
-AGENT_MAC_xface *flexran_agent_get_mac_xface(mid_t mod_id)
-{
- return agent_mac_xface[mod_id];
-}
-
-void flexran_create_config_structures(mid_t mod_id)
-{
- int i;
- int n_dl = flexran_get_num_dl_slices(mod_id);
- int m_ul = flexran_get_num_ul_slices(mod_id);
- slice_config[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul);
- sc_update[mod_id] = flexran_agent_create_slice_config(n_dl, m_ul);
- if (!slice_config[mod_id] || !sc_update[mod_id]) return;
-
- flexran_agent_read_slice_config(mod_id, slice_config[mod_id]);
- flexran_agent_read_slice_config(mod_id, sc_update[mod_id]);
- for (i = 0; i < n_dl; i++) {
- flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]);
- flexran_agent_read_slice_dl_config(mod_id, i, sc_update[mod_id]->dl[i]);
+void helper_destroy_mac_slice_config(Protocol__FlexSliceConfig *slice_config) {
+ if (slice_config->dl) {
+ if (slice_config->dl->scheduler)
+ free(slice_config->dl->scheduler);
+ for (int i = 0; i < slice_config->dl->n_slices; i++)
+ if (slice_config->dl->slices[i]->scheduler)
+ free(slice_config->dl->slices[i]->scheduler);
}
- for (i = 0; i < m_ul; i++) {
- flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]);
- flexran_agent_read_slice_ul_config(mod_id, i, sc_update[mod_id]->ul[i]);
+ if (slice_config->ul) {
+ if (slice_config->ul->scheduler)
+ free(slice_config->ul->scheduler);
+ for (int i = 0; i < slice_config->ul->n_slices; i++)
+ if (slice_config->ul->slices[i]->scheduler)
+ free(slice_config->ul->slices[i]->scheduler);
}
-}
-void flexran_check_and_remove_slices(mid_t mod_id)
-{
- Protocol__FlexDlSlice **dl = sc_update[mod_id]->dl;
- Protocol__FlexDlSlice **dlreal = slice_config[mod_id]->dl;
- int i = 0;
- while (i < sc_update[mod_id]->n_dl) {
- /* remove slices whose percentage is zero */
- if (dl[i]->percentage > 0) {
- ++i;
- continue;
- }
- if (flexran_remove_dl_slice(mod_id, i) < 1) {
- LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n",
- mod_id, i, dl[i]->id);
- ++i;
- continue;
- }
- LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n",
- mod_id, i, dl[i]->id);
- if (dl[i]->n_sorting > 0) free(dl[i]->sorting);
- free(dl[i]->scheduler_name);
- if (dlreal[i]->n_sorting > 0) {
- dlreal[i]->n_sorting = 0;
- free(dlreal[i]->sorting);
- }
- free(dlreal[i]->scheduler_name);
- --sc_update[mod_id]->n_dl;
- --slice_config[mod_id]->n_dl;
- const size_t last = sc_update[mod_id]->n_dl;
- /* we need to memcpy the higher slice to the position we just deleted */
- memcpy(dl[i], dl[last], sizeof(*dl[last]));
- memset(dl[last], 0, sizeof(*dl[last]));
- memcpy(dlreal[i], dlreal[last], sizeof(*dlreal[last]));
- memset(dlreal[last], 0, sizeof(*dlreal[last]));
- /* dont increase i but recheck the slice which has been copied to here */
- }
- Protocol__FlexUlSlice **ul = sc_update[mod_id]->ul;
- Protocol__FlexUlSlice **ulreal = slice_config[mod_id]->ul;
- i = 0;
- while (i < sc_update[mod_id]->n_ul) {
- if (ul[i]->percentage > 0) {
- ++i;
- continue;
- }
- if (flexran_remove_ul_slice(mod_id, i) < 1) {
- LOG_W(FLEXRAN_AGENT, "[%d] can not remove slice index %d ID %d\n",
- mod_id, i, ul[i]->id);
- ++i;
- continue;
- }
- LOG_I(FLEXRAN_AGENT, "[%d] removed slice index %d ID %d\n",
- mod_id, i, ul[i]->id);
- free(ul[i]->scheduler_name);
- free(ulreal[i]->scheduler_name);
- --sc_update[mod_id]->n_ul;
- --slice_config[mod_id]->n_ul;
- const size_t last = sc_update[mod_id]->n_ul;
- /* see DL remarks */
- memcpy(ul[i], ul[last], sizeof(*ul[last]));
- memset(ul[last], 0, sizeof(*ul[last]));
- memcpy(ulreal[i], ulreal[last], sizeof(*ulreal[last]));
- memset(ulreal[last], 0, sizeof(*ulreal[last]));
- /* dont increase i but recheck the slice which has been copied to here */
- }
+ Protocol__FlexCellConfig helper;
+ helper.slice_config = slice_config;
+ flexran_agent_destroy_mac_slice_config(&helper);
}
-void flexran_agent_slice_update(mid_t mod_id)
-{
- int i;
- int changes = 0;
+void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice_config) {
+ if (!*slice_config) return;
+ /* just use the memory and set to NULL in original */
+ Protocol__FlexSliceConfig *sc = *slice_config;
+ *slice_config = NULL;
- if (perform_slice_config_update_count <= 0) return;
- perform_slice_config_update_count--;
+ struct lfds700_misc_prng_state ls;
+ LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE;
+ lfds700_misc_prng_init(&ls);
+ enum lfds700_misc_flag overwrite_occurred_flag;
- pthread_mutex_lock(&sc_update_mtx);
+ Protocol__FlexSliceConfig *overwritten_sc;
+ lfds700_ringbuffer_write(&slice_config_ringbuffer_state[mod_id],
+ NULL,
+ (void *)sc,
+ &overwrite_occurred_flag,
+ NULL,
+ (void **)&overwritten_sc,
+ &ls);
- if (!slice_config[mod_id]) {
- /* if the configuration does not exist for agent, create from eNB structure
- * and exit */
- flexran_create_config_structures(mod_id);
- pthread_mutex_unlock(&sc_update_mtx);
- return;
+ if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) {
+ helper_destroy_mac_slice_config(overwritten_sc);
+ LOG_E(FLEXRAN_AGENT, "lost slice config: too many reconfigurations at once\n");
}
+}
- /********* read existing config *********/
- /* simply update slice_config all the time and write new config
- * (apply_new_slice_dl_config() only updates if changes are necessary) */
- slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id);
- slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id);
- for (i = 0; i < slice_config[mod_id]->n_dl; i++) {
- flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]);
- }
- for (i = 0; i < slice_config[mod_id]->n_ul; i++) {
- flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]);
- }
+void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config) {
+ struct lfds700_misc_prng_state ls;
+ LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE;
+ lfds700_misc_prng_init(&ls);
+ enum lfds700_misc_flag overwrite_occurred_flag;
- /********* write new config *********/
- /* check for removal (sc_update[X]->dl[Y].percentage == 0)
- * and update sc_update & slice_config accordingly */
- flexran_check_and_remove_slices(mod_id);
+ Protocol__FlexUeConfig *overwritten_ue_config;
+ lfds700_ringbuffer_write(&ue_assoc_ringbuffer_state[mod_id],
+ NULL,
+ (void *) *ue_config,
+ &overwrite_occurred_flag,
+ NULL,
+ (void **)&overwritten_ue_config,
+ &ls);
- /* create new DL and UL slices if necessary */
- for (i = slice_config[mod_id]->n_dl; i < sc_update[mod_id]->n_dl; i++) {
- flexran_create_dl_slice(mod_id, sc_update[mod_id]->dl[i]->id);
- }
- for (i = slice_config[mod_id]->n_ul; i < sc_update[mod_id]->n_ul; i++) {
- flexran_create_ul_slice(mod_id, sc_update[mod_id]->ul[i]->id);
- }
- slice_config[mod_id]->n_dl = flexran_get_num_dl_slices(mod_id);
- slice_config[mod_id]->n_ul = flexran_get_num_ul_slices(mod_id);
- changes += apply_new_slice_config(mod_id, slice_config[mod_id], sc_update[mod_id]);
- for (i = 0; i < slice_config[mod_id]->n_dl; i++) {
- changes += apply_new_slice_dl_config(mod_id,
- slice_config[mod_id]->dl[i],
- sc_update[mod_id]->dl[i]);
- flexran_agent_read_slice_dl_config(mod_id, i, slice_config[mod_id]->dl[i]);
- }
- for (i = 0; i < slice_config[mod_id]->n_ul; i++) {
- changes += apply_new_slice_ul_config(mod_id,
- slice_config[mod_id]->ul[i],
- sc_update[mod_id]->ul[i]);
- flexran_agent_read_slice_ul_config(mod_id, i, slice_config[mod_id]->ul[i]);
- }
- flexran_agent_read_slice_config(mod_id, slice_config[mod_id]);
- if (n_ue_slice_assoc_updates > 0) {
- changes += apply_ue_slice_assoc_update(mod_id);
+ if (overwrite_occurred_flag == LFDS700_MISC_FLAG_RAISED) {
+ free(overwritten_ue_config);
+ LOG_E(FLEXRAN_AGENT, "lost UE-slice association: too many UE-slice associations at once\n");
}
- if (changes > 0)
- LOG_I(FLEXRAN_AGENT, "[%d] slice configuration: applied %d changes\n", mod_id, changes);
-
- pthread_mutex_unlock(&sc_update_mtx);
}
-Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id)
-{
- if (!slice_config[mod_id]) return NULL;
- Protocol__FlexSliceConfig *config = NULL;
-
- pthread_mutex_lock(&sc_update_mtx);
- config = flexran_agent_create_slice_config(slice_config[mod_id]->n_dl,
- slice_config[mod_id]->n_ul);
- if (!config) {
- pthread_mutex_unlock(&sc_update_mtx);
- return NULL;
- }
- config->has_intraslice_share_active = 1;
- config->intraslice_share_active = slice_config[mod_id]->intraslice_share_active;
- config->has_interslice_share_active = 1;
- config->interslice_share_active = slice_config[mod_id]->interslice_share_active;
- for (int i = 0; i < slice_config[mod_id]->n_dl; ++i) {
- if (!config->dl[i]) continue;
- config->dl[i]->has_id = 1;
- config->dl[i]->id = slice_config[mod_id]->dl[i]->id;
- config->dl[i]->has_label = 1;
- config->dl[i]->label = slice_config[mod_id]->dl[i]->label;
- config->dl[i]->has_percentage = 1;
- config->dl[i]->percentage = slice_config[mod_id]->dl[i]->percentage;
- config->dl[i]->has_isolation = 1;
- config->dl[i]->isolation = slice_config[mod_id]->dl[i]->isolation;
- config->dl[i]->has_priority = 1;
- config->dl[i]->priority = slice_config[mod_id]->dl[i]->priority;
- config->dl[i]->has_position_low = 1;
- config->dl[i]->position_low = slice_config[mod_id]->dl[i]->position_low;
- config->dl[i]->has_position_high = 1;
- config->dl[i]->position_high = slice_config[mod_id]->dl[i]->position_high;
- config->dl[i]->has_maxmcs = 1;
- config->dl[i]->maxmcs = slice_config[mod_id]->dl[i]->maxmcs;
- config->dl[i]->n_sorting = slice_config[mod_id]->dl[i]->n_sorting;
- config->dl[i]->sorting = calloc(config->dl[i]->n_sorting, sizeof(Protocol__FlexDlSorting));
- if (!config->dl[i]->sorting) config->dl[i]->n_sorting = 0;
- for (int j = 0; j < config->dl[i]->n_sorting; ++j)
- config->dl[i]->sorting[j] = slice_config[mod_id]->dl[i]->sorting[j];
- config->dl[i]->has_accounting = 1;
- config->dl[i]->accounting = slice_config[mod_id]->dl[i]->accounting;
- config->dl[i]->scheduler_name = strdup(slice_config[mod_id]->dl[i]->scheduler_name);
- }
- for (int i = 0; i < slice_config[mod_id]->n_ul; ++i) {
- if (!config->ul[i]) continue;
- config->ul[i]->has_id = 1;
- config->ul[i]->id = slice_config[mod_id]->ul[i]->id;
- config->ul[i]->has_label = 1;
- config->ul[i]->label = slice_config[mod_id]->ul[i]->label;
- config->ul[i]->has_percentage = 1;
- config->ul[i]->percentage = slice_config[mod_id]->ul[i]->percentage;
- config->ul[i]->has_isolation = 1;
- config->ul[i]->isolation = slice_config[mod_id]->ul[i]->isolation;
- config->ul[i]->has_priority = 1;
- config->ul[i]->priority = slice_config[mod_id]->ul[i]->priority;
- config->ul[i]->has_first_rb = 1;
- config->ul[i]->first_rb = slice_config[mod_id]->ul[i]->first_rb;
- config->ul[i]->has_maxmcs = 1;
- config->ul[i]->maxmcs = slice_config[mod_id]->ul[i]->maxmcs;
- config->ul[i]->n_sorting = slice_config[mod_id]->ul[i]->n_sorting;
- config->ul[i]->sorting = calloc(config->ul[i]->n_sorting, sizeof(Protocol__FlexUlSorting));
- if (!config->ul[i]->sorting) config->ul[i]->n_sorting = 0;
- for (int j = 0; j < config->ul[i]->n_sorting; ++j)
- config->ul[i]->sorting[j] = slice_config[mod_id]->ul[i]->sorting[j];
- config->ul[i]->has_accounting = 1;
- config->ul[i]->accounting = slice_config[mod_id]->ul[i]->accounting;
- config->ul[i]->scheduler_name = strdup(slice_config[mod_id]->ul[i]->scheduler_name);
+void flexran_agent_slice_update(mid_t mod_id) {
+ struct lfds700_misc_prng_state ls;
+ LFDS700_MISC_MAKE_VALID_ON_CURRENT_LOGICAL_CORE_INITS_COMPLETED_BEFORE_NOW_ON_ANY_OTHER_LOGICAL_CORE;
+ lfds700_misc_prng_init(&ls);
+
+ Protocol__FlexSliceConfig *sc = NULL;
+ struct lfds700_ringbuffer_state *state = &slice_config_ringbuffer_state[mod_id];
+ if (lfds700_ringbuffer_read(state, NULL, (void **) &sc, &ls) != 0) {
+ apply_update_dl_slice_config(mod_id, sc->dl);
+ apply_update_ul_slice_config(mod_id, sc->ul);
+ helper_destroy_mac_slice_config(sc);
}
- pthread_mutex_unlock(&sc_update_mtx);
- return config;
+ Protocol__FlexUeConfig *ue_config = NULL;
+ state = &ue_assoc_ringbuffer_state[mod_id];
+ if (lfds700_ringbuffer_read(state, NULL, (void **) &ue_config, &ls) != 0) {
+ apply_ue_slice_assoc_update(mod_id, ue_config);
+ free(ue_config);
+ }
}
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h
index 2f9f99c740bd49791f2cc917f288f394b78ca5ce..5a8d4f31aa70809c79c613b13ea91ad01ade528c 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac.h
@@ -115,7 +115,16 @@ int flexran_agent_unregister_mac_xface(mid_t mod_id);
/* Inform controller about possibility to update slice configuration */
void flexran_agent_slice_update(mid_t mod_id);
-/* return a pointer to the current config */
-Protocol__FlexSliceConfig *flexran_agent_get_slice_config(mid_t mod_id);
+/* marks slice_config so that it can be applied later. Takes ownership of the
+ * FlexSliceConfig message */
+void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig **slice);
+
+/* inserts a new ue_config into the structure keeping ue to slice association
+ * updates and marks so it can be applied. Takes ownership of the FlexUeConfig message */
+void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig **ue_config);
+
+/* free slice_config part of flexCellConfig, filled in
+ * flexran_agent_fill_mac_cell_config() */
+void flexran_agent_destroy_mac_slice_config(Protocol__FlexCellConfig *conf);
#endif
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c
index a85cbac5439465b3ca9d88e2a21241a67bb72ab9..93de0b11ec3d1c228b85bae254b24c559ecc7bab 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.c
@@ -33,14 +33,6 @@
#include "flexran_agent_mac_internal.h"
#include "flexran_agent_mac_slice_verification.h"
-/* from flexran_agent_mac.c */
-extern Protocol__FlexSliceConfig *slice_config[MAX_NUM_SLICES];
-extern Protocol__FlexSliceConfig *sc_update[MAX_NUM_SLICES];
-extern int perform_slice_config_update_count;
-extern Protocol__FlexUeConfig *ue_slice_assoc_update[MAX_NUM_SLICES];
-extern int n_ue_slice_assoc_updates;
-extern pthread_mutex_t sc_update_mtx;
-
Protocol__FlexranMessage * flexran_agent_generate_diff_mac_stats_report(Protocol__FlexranMessage *new_message,
Protocol__FlexranMessage *old_message) {
@@ -1033,724 +1025,166 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name) {
}
-Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul)
-{
- int i;
- Protocol__FlexSliceConfig *fsc = malloc(sizeof(Protocol__FlexSliceConfig));
- if (!fsc) return NULL;
- protocol__flex_slice_config__init(fsc);
-
- /* say there are n_dl slices but reserve memory for up to MAX_NUM_SLICES so
- * we don't need to reserve again later */
- fsc->n_dl = n_dl;
- fsc->dl = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexDlSlice *));
- if (!fsc->dl) fsc->n_dl = 0;
- for (i = 0; i < MAX_NUM_SLICES; i++) {
- fsc->dl[i] = malloc(sizeof(Protocol__FlexDlSlice));
- if (!fsc->dl[i]) continue;
- protocol__flex_dl_slice__init(fsc->dl[i]);
- }
-
- /* as above */
- fsc->n_ul = m_ul;
- fsc->ul = calloc(MAX_NUM_SLICES, sizeof(Protocol__FlexUlSlice *));
- if (!fsc->ul) fsc->n_ul = 0;
- for (i = 0; i < MAX_NUM_SLICES; i++) {
- fsc->ul[i] = malloc(sizeof(Protocol__FlexUlSlice));
- if (!fsc->ul[i]) continue;
- protocol__flex_ul_slice__init(fsc->ul[i]);
- }
- return fsc;
-}
-
-void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s)
-{
- s->intraslice_share_active = flexran_get_intraslice_sharing_active(mod_id);
- s->has_intraslice_share_active = 1;
- s->interslice_share_active = flexran_get_interslice_sharing_active(mod_id);
- s->has_interslice_share_active = 1;
-}
-
-void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice)
-{
- dl_slice->id = flexran_get_dl_slice_id(mod_id, slice_idx);
- dl_slice->has_id = 1;
- /* read label from corresponding sc_update entry or give default */
- dl_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB;
- dl_slice->has_label = 1;
- for (int i = 0; i < sc_update[mod_id]->n_dl; i++) {
- if (sc_update[mod_id]->dl[i]->id == dl_slice->id
- && sc_update[mod_id]->dl[i]->has_label) {
- dl_slice->label = sc_update[mod_id]->dl[i]->label;
- break;
- }
- }
- dl_slice->percentage = flexran_get_dl_slice_percentage(mod_id, slice_idx);
- dl_slice->has_percentage = 1;
- dl_slice->isolation = flexran_get_dl_slice_isolation(mod_id, slice_idx);
- dl_slice->has_isolation = 1;
- dl_slice->priority = flexran_get_dl_slice_priority(mod_id, slice_idx);
- dl_slice->has_priority = 1;
- dl_slice->position_low = flexran_get_dl_slice_position_low(mod_id, slice_idx);
- dl_slice->has_position_low = 1;
- dl_slice->position_high = flexran_get_dl_slice_position_high(mod_id, slice_idx);
- dl_slice->has_position_high = 1;
- dl_slice->maxmcs = flexran_get_dl_slice_maxmcs(mod_id, slice_idx);
- dl_slice->has_maxmcs = 1;
- dl_slice->n_sorting = flexran_get_dl_slice_sorting(mod_id, slice_idx, &dl_slice->sorting);
- if (dl_slice->n_sorting < 1) dl_slice->sorting = NULL;
- dl_slice->accounting = flexran_get_dl_slice_accounting_policy(mod_id, slice_idx);
- dl_slice->has_accounting = 1;
- const char *s_name = flexran_get_dl_slice_scheduler(mod_id, slice_idx);
- if (!dl_slice->scheduler_name
- || strcmp(dl_slice->scheduler_name, s_name) != 0) {
- dl_slice->scheduler_name = realloc(dl_slice->scheduler_name, strlen(s_name) + 1);
- strcpy(dl_slice->scheduler_name, s_name);
- }
-}
-
-void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice)
-{
- ul_slice->id = flexran_get_ul_slice_id(mod_id, slice_idx);
- ul_slice->has_id = 1;
- /* read label from corresponding sc_update entry or give default */
- ul_slice->label = PROTOCOL__FLEX_SLICE_LABEL__xMBB;
- ul_slice->has_label = 1;
- for (int i = 0; i < sc_update[mod_id]->n_ul; i++) {
- if (sc_update[mod_id]->ul[i]->id == ul_slice->id
- && sc_update[mod_id]->ul[i]->has_label) {
- ul_slice->label = sc_update[mod_id]->ul[i]->label;
- break;
- }
- }
- ul_slice->percentage = flexran_get_ul_slice_percentage(mod_id, slice_idx);
- ul_slice->has_percentage = 1;
- /*ul_slice->isolation = flexran_get_ul_slice_isolation(mod_id, slice_idx);*/
- ul_slice->has_isolation = 0;
- /*ul_slice->priority = flexran_get_ul_slice_priority(mod_id, slice_idx);*/
- ul_slice->has_priority = 0;
- ul_slice->first_rb = flexran_get_ul_slice_first_rb(mod_id, slice_idx);
- ul_slice->has_first_rb = 1;
- /*ul_slice-> = flexran_get_ul_slice_length_rb(mod_id, slice_idx);
- ul_slice->has_length_rb = 0;*/
- ul_slice->maxmcs = flexran_get_ul_slice_maxmcs(mod_id, slice_idx);
- ul_slice->has_maxmcs = 1;
- ul_slice->n_sorting = 0;
- /*if (ul_slice->sorting) {
- free(ul_slice->sorting);
- ul_slice->sorting = NULL;
- }
- ul_slice->n_sorting = flexran_get_ul_slice_sorting(mod_id, slice_idx, &ul_slice->sorting);
- if (ul_slice->n_sorting < 1) ul_slice->sorting = NULL;*/
- /*ul_slice->accounting = flexran_get_ul_slice_accounting_policy(mod_id, slice_idx);*/
- ul_slice->has_accounting = 0;
- const char *s_name = flexran_get_ul_slice_scheduler(mod_id, slice_idx);
- if (!ul_slice->scheduler_name
- || strcmp(ul_slice->scheduler_name, s_name) != 0) {
- ul_slice->scheduler_name = realloc(ul_slice->scheduler_name, strlen(s_name) + 1);
- strcpy(ul_slice->scheduler_name, s_name);
+void update_or_remove_dl(mid_t mod_id, Protocol__FlexSlice *s) {
+ if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET
+ && !s->label && !s->scheduler) {
+ LOG_I(FLEXRAN_AGENT, "remove DL slice ID %d\n", s->id);
+ const int rc = flexran_remove_dl_slice(mod_id, s);
+ if (!rc)
+ LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id);
+ } else {
+ LOG_I(FLEXRAN_AGENT, "updating DL slice ID %d\n", s->id);
+ const int rc = flexran_create_dl_slice(mod_id, s);
+ if (rc < 0)
+ LOG_W(FLEXRAN_AGENT,
+ "error while update slice ID %d: flexran_create_dl_slice() -> %d\n",
+ s->id, rc);
}
}
-int check_dl_sorting_update(Protocol__FlexDlSlice *old, Protocol__FlexDlSlice *new)
-{
- /* sorting_update => true when old->n_sorting == 0 or different numbers of
- * elements; otherwise will check * element-wise */
- int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting);
- for (int i = 0; i < old->n_sorting && !sorting_update; ++i) {
- sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]);
+void update_or_remove_ul(mid_t mod_id, Protocol__FlexSlice *s) {
+ if (s->params_case == PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET
+ && !s->label && !s->scheduler) {
+ LOG_I(FLEXRAN_AGENT, "remove UL slice ID %d\n", s->id);
+ const int rc = flexran_remove_ul_slice(mod_id, s);
+ if (!rc)
+ LOG_W(FLEXRAN_AGENT, "error while removing slice ID %d\n", s->id);
+ } else {
+ LOG_I(FLEXRAN_AGENT, "updating UL slice ID %d\n", s->id);
+ const int rc = flexran_create_ul_slice(mod_id, s);
+ if (rc < 0)
+ LOG_W(FLEXRAN_AGENT,
+ "error while updating slice ID %d: flexran_create_ul_slice() -> %d)\n",
+ s->id, rc);
}
- return sorting_update;
}
-int check_ul_sorting_update(Protocol__FlexUlSlice *old, Protocol__FlexUlSlice *new)
-{
- /* sorting_update => true when old->n_sorting == 0 or different numbers of
- * elements; otherwise will check * element-wise */
- int sorting_update = old->n_sorting == 0 || (old->n_sorting != new->n_sorting);
- for (int i = 0; i < old->n_sorting && !sorting_update; ++i) {
- sorting_update = sorting_update || (new->sorting[i] != old->sorting[i]);
- }
- return sorting_update;
-}
+void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *dl) {
+ if (!dl)
+ return;
-void overwrite_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *exist, Protocol__FlexSliceConfig *update)
-{
- if (update->has_intraslice_share_active
- && exist->intraslice_share_active != update->intraslice_share_active) {
- LOG_I(FLEXRAN_AGENT, "[%d] update intraslice_share_active: %d -> %d\n",
- mod_id, exist->intraslice_share_active, update->intraslice_share_active);
- exist->intraslice_share_active = update->intraslice_share_active;
- exist->has_intraslice_share_active = 1;
+ Protocol__FlexSliceAlgorithm dl_algo = flexran_get_dl_slice_algo(mod_id);
+ if (dl->has_algorithm && dl_algo != dl->algorithm) {
+ LOG_I(FLEXRAN_AGENT, "loading new DL slice algorithm %d\n", dl->algorithm);
+ dl_algo = dl->algorithm;
+ flexran_set_dl_slice_algo(mod_id, dl_algo);
}
- if (update->has_interslice_share_active
- && exist->interslice_share_active != update->interslice_share_active) {
- LOG_I(FLEXRAN_AGENT, "[%d] update interslice_share_active: %d -> %d\n",
- mod_id, exist->interslice_share_active, update->interslice_share_active);
- exist->interslice_share_active = update->interslice_share_active;
- exist->has_interslice_share_active = 1;
- }
-}
-void overwrite_slice_config_dl(mid_t mod_id, Protocol__FlexDlSlice *exist, Protocol__FlexDlSlice *update)
-{
- if (update->label != exist->label) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update label: %d -> %d\n",
- mod_id, update->id, exist->label, update->label);
- exist->label = update->label;
- exist->has_label = 1;
- }
- if (update->percentage != exist->percentage) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update percentage: %d -> %d\n",
- mod_id, update->id, exist->percentage, update->percentage);
- exist->percentage = update->percentage;
- exist->has_percentage = 1;
- }
- if (update->isolation != exist->isolation) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update isolation: %d -> %d\n",
- mod_id, update->id, exist->isolation, update->isolation);
- exist->isolation = update->isolation;
- exist->has_isolation = 1;
- }
- if (update->priority != exist->priority) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update priority: %d -> %d\n",
- mod_id, update->id, exist->priority, update->priority);
- exist->priority = update->priority;
- exist->has_priority = 1;
- }
- if (update->position_low != exist->position_low) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_low: %d -> %d\n",
- mod_id, update->id, exist->position_low, update->position_low);
- exist->position_low = update->position_low;
- exist->has_position_low = 1;
- }
- if (update->position_high != exist->position_high) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update position_high: %d -> %d\n",
- mod_id, update->id, exist->position_high, update->position_high);
- exist->position_high = update->position_high;
- exist->has_position_high = 1;
- }
- if (update->maxmcs != exist->maxmcs) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update maxmcs: %d -> %d\n",
- mod_id, update->id, exist->maxmcs, update->maxmcs);
- exist->maxmcs = update->maxmcs;
- exist->has_maxmcs = 1;
- }
- if (check_dl_sorting_update(exist, update)) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update sorting array\n", mod_id, update->id);
- if (exist->n_sorting != update->n_sorting) {
- exist->n_sorting = update->n_sorting;
- exist->sorting = realloc(exist->sorting, exist->n_sorting * sizeof(Protocol__FlexDlSorting));
- if (!exist->sorting) exist->n_sorting = 0;
+ /* first update existing slices, then create new. Thus, we go through the
+ * list twice. First round, if a slice exists, handle and mark as such. Then,
+ * apply all others in the second round */
+ if (dl->n_slices > 0) {
+ if (dl_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n");
+ return;
}
- for (int i = 0; i < exist->n_sorting; i++)
- exist->sorting[i] = update->sorting[i];
- }
- if (update->accounting != exist->accounting) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update accounting: %d -> %d\n",
- mod_id, update->id, exist->accounting, update->accounting);
- exist->accounting = update->accounting;
- exist->has_accounting = 1;
- }
- if (!exist->scheduler_name
- || strcmp(update->scheduler_name, exist->scheduler_name) != 0) {
- LOG_I(FLEXRAN_AGENT, "[%d][DL slice %d] update scheduler: %s -> %s\n",
- mod_id, update->id, exist->scheduler_name, update->scheduler_name);
- if (exist->scheduler_name) free(exist->scheduler_name);
- exist->scheduler_name = strdup(update->scheduler_name);
- }
-}
-
-void overwrite_slice_config_ul(mid_t mod_id, Protocol__FlexUlSlice *exist, Protocol__FlexUlSlice *update)
-{
- if (update->label != exist->label) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update label: %d -> %d\n",
- mod_id, update->id, exist->label, update->label);
- exist->label = update->label;
- exist->has_label = 1;
- }
- if (update->percentage != exist->percentage) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update percentage: %d -> %d\n",
- mod_id, update->id, exist->percentage, update->percentage);
- exist->percentage = update->percentage;
- exist->has_percentage = 1;
- }
- if (update->isolation != exist->isolation) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update isolation: %d -> %d\n",
- mod_id, update->id, exist->isolation, update->isolation);
- exist->isolation = update->isolation;
- exist->has_isolation = 1;
- }
- if (update->priority != exist->priority) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update priority: %d -> %d\n",
- mod_id, update->id, exist->priority, update->priority);
- exist->priority = update->priority;
- exist->has_priority = 1;
- }
- if (update->first_rb != exist->first_rb) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update first_rb: %d -> %d\n",
- mod_id, update->id, exist->first_rb, update->first_rb);
- exist->first_rb = update ->first_rb;
- exist->has_first_rb = 1;
- }
- /*if (update->lenght_rb != exist->lenght_rb) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update lenght_rb: %d -> %d\n",
- mod_id, update->id, exist->lenght_rb, update->lenght_rb);
- exist->lenght_rb = update->lenght_rb;
- }*/
- if (update->maxmcs != exist->maxmcs) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update maxmcs: %d -> %d\n",
- mod_id, update->id, exist->maxmcs, update->maxmcs);
- exist->maxmcs = update->maxmcs;
- exist->has_maxmcs = 1;
- }
- /* TODO
- int sorting_update = 0;
- int n = min(exist->n_sorting, update->n_sorting);
- int i = 0;
- while (i < n && !sorting_update) {
- sorting_update = sorting_update || (update->sorting[i] != exist->sorting[i]);
- i++;
- }
- if (sorting_update) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update sorting array\n", update->id, mod_id);
- if (exist->n_sorting != update->n_sorting)
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] only writing %d elements\n",
- mod_id, update->id, n);
- for (i = 0; i < n; i++)
- exist->sorting[i] = update->sorting[i];
- }
- */
- if (update->accounting != exist->accounting) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update accounting: %d -> %d\n",
- mod_id, update->id, exist->accounting, update->accounting);
- exist->accounting = update->accounting;
- exist->has_accounting = 1;
- }
- if (!exist->scheduler_name
- || strcmp(update->scheduler_name, exist->scheduler_name) != 0) {
- LOG_I(FLEXRAN_AGENT, "[%d][UL slice %d] update scheduler: %s -> %s\n",
- mod_id, update->id, exist->scheduler_name, update->scheduler_name);
- if (exist->scheduler_name) free(exist->scheduler_name);
- exist->scheduler_name = strdup(update->scheduler_name);
- }
-}
-
-void fill_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *s, Protocol__FlexDlSlice *from)
-{
- /* function fills slice with information from another slice or with default
- * values (currently slice 0) if from is NULL */
- /* TODO fill the slice depending on the chosen label */
- if (!s->has_label) {
- s->has_label = 1;
- s->label = from ? from->label : sc_update[mod_id]->dl[0]->label;
- }
- if (!s->has_percentage) {
- s->has_percentage = 1;
- s->percentage = from ? from->percentage : sc_update[mod_id]->dl[0]->percentage;
- }
- if (!s->has_isolation) {
- s->has_isolation = 1;
- s->isolation = from ? from->isolation : sc_update[mod_id]->dl[0]->isolation;
- }
- if (!s->has_priority) {
- s->has_priority = 1;
- s->priority = from ? from->priority : sc_update[mod_id]->dl[0]->priority;
- }
- if (!s->has_position_low) {
- s->has_position_low = 1;
- s->position_low = from ? from->position_low : sc_update[mod_id]->dl[0]->position_low;
- }
- if (!s->has_position_high) {
- s->has_position_high = 1;
- s->position_high = from ? from->position_high : sc_update[mod_id]->dl[0]->position_high;
- }
- if (!s->has_maxmcs) {
- s->has_maxmcs = 1;
- s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->dl[0]->maxmcs;
- }
- if (s->n_sorting == 0) {
- s->n_sorting = from ? from->n_sorting : sc_update[mod_id]->dl[0]->n_sorting;
- s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexDlSorting));
- if (!s->sorting) s->n_sorting = 0;
- for (int i = 0; i < s->n_sorting; ++i)
- s->sorting[i] = from ? from->sorting[i] : sc_update[0]->dl[0]->sorting[i];
- }
- if (!s->has_accounting) {
- s->accounting = from ? from->accounting : sc_update[mod_id]->dl[0]->accounting;
- }
- if (!s->scheduler_name) {
- s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->dl[0]->scheduler_name);
- }
-}
-
-Protocol__FlexDlSlice *get_existing_dl_slice(mid_t mod_id, int id)
-{
- for (int i = 0; i < sc_update[mod_id]->n_dl; ++i) {
- if (id == sc_update[mod_id]->dl[i]->id) {
- return sc_update[mod_id]->dl[i];
+ int handled_dl[dl->n_slices];
+ for (int i = 0; i < dl->n_slices; ++i) {
+ if (flexran_find_dl_slice(mod_id, dl->slices[i]->id) < 0) {
+ handled_dl[i] = 0;
+ continue;
+ }
+ update_or_remove_dl(mod_id, dl->slices[i]);
+ handled_dl[i] = 1;
+ }
+ for (int i = 0; i < dl->n_slices; ++i) {
+ if (handled_dl[i])
+ continue;
+ update_or_remove_dl(mod_id, dl->slices[i]);
}
}
- return NULL;
-}
-
-Protocol__FlexDlSlice *create_new_dl_slice(mid_t mod_id, int id)
-{
- LOG_I(FLEXRAN_AGENT,
- "[%d] Creating DL slice with ID %d, taking default values from DL slice 0\n",
- mod_id, id);
- Protocol__FlexDlSlice *to = sc_update[mod_id]->dl[sc_update[mod_id]->n_dl];
- sc_update[mod_id]->n_dl++;
- AssertFatal(sc_update[mod_id]->n_dl <= MAX_NUM_SLICES,
- "cannot create more than MAX_NUM_SLICES\n");
- to->id = id;
- return to;
-}
-
-void fill_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *s, Protocol__FlexUlSlice *from)
-{
- /* function fills slice with information from another slice or with default
- * values (currently slice 0) if from is NULL */
- /* TODO fill the slice depending on the chosen label */
- if (!s->has_label) {
- s->has_label = 1;
- s->label = from ? from->label : sc_update[mod_id]->ul[0]->label;
- }
- if (!s->has_percentage) {
- s->has_percentage = 1;
- s->percentage = from ? from->percentage : sc_update[mod_id]->ul[0]->percentage;
- }
- if (!s->has_isolation) {
- s->has_isolation = 1;
- s->isolation = from ? from->isolation : sc_update[mod_id]->ul[0]->isolation;
- }
- if (!s->has_priority) {
- s->has_priority = 1;
- s->priority = from ? from->priority : sc_update[mod_id]->ul[0]->priority;
- }
- if (!s->has_first_rb) {
- s->has_first_rb = 1;
- s->first_rb = from ? from->first_rb : sc_update[mod_id]->ul[0]->first_rb;
- }
- if (!s->has_maxmcs) {
- s->has_maxmcs = 1;
- s->maxmcs = from ? from->maxmcs : sc_update[mod_id]->ul[0]->maxmcs;
- }
- if (s->n_sorting == 0) {
- s->n_sorting = from ? from->n_sorting : sc_update[0]->ul[0]->n_sorting;
- s->sorting = calloc(s->n_sorting, sizeof(Protocol__FlexUlSorting));
- if (!s->sorting) s->n_sorting = 0;
- for (int i = 0; i < s->n_sorting; ++i)
- s->sorting[i] = from ? from->sorting[i] : sc_update[0]->ul[0]->sorting[i];
- }
- if (!s->has_accounting) {
- s->accounting = from ? from->accounting : sc_update[0]->ul[0]->accounting;
- }
- if (!s->scheduler_name) {
- s->scheduler_name = strdup(from ? from->scheduler_name : sc_update[mod_id]->ul[0]->scheduler_name);
- }
-}
-Protocol__FlexUlSlice *get_existing_ul_slice(mid_t mod_id, int id)
-{
- for (int i = 0; i < sc_update[mod_id]->n_ul; ++i) {
- if (id == sc_update[mod_id]->ul[i]->id) {
- return sc_update[mod_id]->ul[i];
+ if (dl->scheduler) {
+ if (dl_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n");
+ return;
+ }
+ LOG_I(FLEXRAN_AGENT, "loading DL new scheduling algorithm '%s'\n", dl->scheduler);
+ const int rc = flexran_set_dl_scheduler(mod_id, dl->scheduler);
+ if (rc < 0) {
+ LOG_E(FLEXRAN_AGENT,
+ "error while updating scheduling algorithm: "
+ "flexran_update_dl_sched_algo() -> %d)\n",
+ rc);
+ return;
}
}
- return NULL;
-}
-
-Protocol__FlexUlSlice *create_new_ul_slice(mid_t mod_id, int id)
-{
- LOG_I(FLEXRAN_AGENT,
- "[%d] Creating UL slice with ID %d, taking default values from UL slice 0\n",
- mod_id, id);
- Protocol__FlexUlSlice *to = sc_update[mod_id]->ul[sc_update[mod_id]->n_ul];
- sc_update[mod_id]->n_ul++;
- AssertFatal(sc_update[mod_id]->n_ul <= MAX_NUM_SLICES,
- "cannot create more than MAX_NUM_SLICES\n");
- to->id = id;
- return to;
}
-void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *sup)
-{
- int verified = 1;
- if (!sc_update[mod_id]) {
- LOG_E(FLEXRAN_AGENT, "Can not update slice policy (no existing slice profile)\n");
+void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *ul) {
+ if (!ul)
return;
- }
-
- pthread_mutex_lock(&sc_update_mtx);
- /* no need for tests in the current state as there are only two protobuf
- * bools for intra-/interslice sharing. The function applies new values if
- * applicable */
- overwrite_slice_config(mod_id, sc_update[mod_id], sup);
- if (sup->n_dl == 0) {
- LOG_I(FLEXRAN_AGENT, "[%d] no DL slice configuration in flex_slice_config message\n", mod_id);
- } else {
- /* verify slice parameters */
- for (int i = 0; i < sup->n_dl; i++) {
- if (!sup->dl[i]->has_id) {
- verified = 0;
- break;
- }
- Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id);
- /* fill up so that the slice is complete. This way, we don't need to
- * worry about it later */
- fill_dl_slice(mod_id, sup->dl[i], dls);
- verified = verified && flexran_verify_dl_slice(mod_id, sup->dl[i]);
- if (!verified) break;
+ Protocol__FlexSliceAlgorithm ul_algo = flexran_get_ul_slice_algo(mod_id);
+ if (ul->has_algorithm && ul_algo != ul->algorithm) {
+ LOG_I(FLEXRAN_AGENT, "loading new UL slice algorithm %d\n", ul->algorithm);
+ ul_algo = ul->algorithm;
+ flexran_set_ul_slice_algo(mod_id, ul_algo);
+ }
+ if (ul->n_slices > 0) {
+ if (ul_algo == PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "cannot update slices: no algorithm loaded\n");
+ return;
}
-
- /* verify group-based parameters (e.g. sum percentage should not exceed
- * 100%). Can be used to perform admission control */
- verified = verified && flexran_verify_group_dl_slices(mod_id,
- sc_update[mod_id]->dl, sc_update[mod_id]->n_dl, sup->dl, sup->n_dl);
-
- if (verified) {
- for (int i = 0; i < sup->n_dl; i++) {
- /* if all verifications were successful, get existing slice for ID or
- * create new one and overwrite with the update */
- Protocol__FlexDlSlice *dls = get_existing_dl_slice(mod_id, sup->dl[i]->id);
- if (!dls) dls = create_new_dl_slice(mod_id, sup->dl[i]->id);
- overwrite_slice_config_dl(mod_id, dls, sup->dl[i]);
+ int handled_ul[ul->n_slices];
+ for (int i = 0; i < ul->n_slices; ++i) {
+ if (flexran_find_ul_slice(mod_id, ul->slices[i]->id) < 0) {
+ handled_ul[i] = 0;
+ continue;
}
- } else {
- LOG_E(FLEXRAN_AGENT, "[%d] DL slice verification failed, refusing application\n", mod_id);
+ update_or_remove_ul(mod_id, ul->slices[i]);
+ handled_ul[i] = 1;
+ }
+ for (int i = 0; i < ul->n_slices; ++i) {
+ if (handled_ul[i])
+ continue;
+ update_or_remove_ul(mod_id, ul->slices[i]);
}
}
- verified = 1;
- if (sup->n_ul == 0) {
- LOG_I(FLEXRAN_AGENT, "[%d] no UL slice configuration in flex_slice_config message\n", mod_id);
- } else {
- /* verify slice parameters */
- for (int i = 0; i < sup->n_ul; i++) {
- if (!sup->ul[i]->has_id) {
- verified = 0;
- break;
- }
- Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id);
- /* fill up so that the slice is complete. This way, we don't need to
- * worry about it later */
- fill_ul_slice(mod_id, sup->ul[i], uls);
- verified = verified && flexran_verify_ul_slice(mod_id, sup->ul[i]);
- if (!verified) break;
+ if (ul->scheduler) {
+ if (ul_algo != PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "cannot update scheduling algorithm: slice algorithm loaded\n");
+ return;
}
-
- /* verify group-based parameters (e.g. sum percentage should not exceed
- * 100%). Can be used to perform admission control */
- verified = verified && flexran_verify_group_ul_slices(mod_id,
- sc_update[mod_id]->ul, sc_update[mod_id]->n_ul, sup->ul, sup->n_ul);
-
- if (verified) {
- for (int i = 0; i < sup->n_ul; i++) {
- /* if all verifications were successful, get existing slice for ID or
- * create new one and overwrite with the update */
- Protocol__FlexUlSlice *uls = get_existing_ul_slice(mod_id, sup->ul[i]->id);
- if (!uls) uls = create_new_ul_slice(mod_id, sup->ul[i]->id);
- overwrite_slice_config_ul(mod_id, uls, sup->ul[i]);
- }
- } else {
- LOG_E(FLEXRAN_AGENT, "[%d] UL slice verification failed, refusing application\n", mod_id);
+ LOG_I(FLEXRAN_AGENT, "loading new UL scheduling algorithm '%s'\n", ul->scheduler);
+ const int rc = flexran_set_ul_scheduler(mod_id, ul->scheduler);
+ if (rc < 0) {
+ LOG_E(FLEXRAN_AGENT,
+ "error while updating scheduling algorithm: "
+ "flexran_update_dl_sched_algo() -> %d)\n",
+ rc);
+ return;
}
}
- pthread_mutex_unlock(&sc_update_mtx);
-
- perform_slice_config_update_count = 1;
-}
-
-int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news)
-{
- /* not setting the old configuration is intentional, as it will be picked up
- * later when reading the configuration. There is thus a direct feedback
- * whether it has been set. */
- int changes = 0;
- if (olds->intraslice_share_active != news->intraslice_share_active) {
- flexran_set_intraslice_sharing_active(mod_id, news->intraslice_share_active);
- changes++;
- }
- if (olds->interslice_share_active != news->interslice_share_active) {
- flexran_set_interslice_sharing_active(mod_id, news->interslice_share_active);
- changes++;
- }
- return changes;
}
-int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc)
+int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config)
{
- /* not setting the old configuration is intentional, as it will be picked up
- * later when reading the configuration. There is thus a direct feedback
- * whether it has been set. */
- int changes = 0;
- int slice_idx = flexran_find_dl_slice(mod_id, newc->id);
- if (slice_idx < 0) {
- LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id);
- return 0;
- }
- if (oldc->percentage != newc->percentage) {
- flexran_set_dl_slice_percentage(mod_id, slice_idx, newc->percentage);
- changes++;
- }
- if (oldc->isolation != newc->isolation) {
- flexran_set_dl_slice_isolation(mod_id, slice_idx, newc->isolation);
- changes++;
- }
- if (oldc->priority != newc->priority) {
- flexran_set_dl_slice_priority(mod_id, slice_idx, newc->priority);
- changes++;
- }
- if (oldc->position_low != newc->position_low) {
- flexran_set_dl_slice_position_low(mod_id, slice_idx, newc->position_low);
- changes++;
- }
- if (oldc->position_high != newc->position_high) {
- flexran_set_dl_slice_position_high(mod_id, slice_idx, newc->position_high);
- changes++;
- }
- if (oldc->maxmcs != newc->maxmcs) {
- flexran_set_dl_slice_maxmcs(mod_id, slice_idx, newc->maxmcs);
- changes++;
- }
- if (check_dl_sorting_update(oldc, newc)) {
- flexran_set_dl_slice_sorting(mod_id, slice_idx, newc->sorting, newc->n_sorting);
- changes++;
- }
- if (oldc->accounting != newc->accounting) {
- flexran_set_dl_slice_accounting_policy(mod_id, slice_idx, newc->accounting);
- changes++;
- }
- if (!oldc->scheduler_name
- || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) {
- int ret = flexran_set_dl_slice_scheduler(mod_id, slice_idx, newc->scheduler_name);
- AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n",
- newc->id, slice_idx);
- changes++;
- }
- return changes;
-}
-
-int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc)
-{
- /* not setting the old configuration is intentional, as it will be picked up
- * later when reading the configuration. There is thus a direct feedback
- * whether it has been set. */
- int changes = 0;
- int slice_idx = flexran_find_ul_slice(mod_id, newc->id);
- if (slice_idx < 0) {
- LOG_W(FLEXRAN_AGENT, "[%d] cannot find index for slice ID %d\n", mod_id, newc->id);
- return 0;
- }
- if (oldc->percentage != newc->percentage) {
- flexran_set_ul_slice_percentage(mod_id, slice_idx, newc->percentage);
- changes++;
- }
- if (oldc->isolation != newc->isolation) {
- /*flexran_set_ul_slice_isolation(mod_id, slice_idx, newc->isolation);
- *changes++;*/
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting isolation is not supported\n",
- mod_id, newc->id);
- }
- if (oldc->priority != newc->priority) {
- /*flexran_set_ul_slice_priority(mod_id, slice_idx, newc->priority);
- *changes++;*/
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the priority is not supported\n",
- mod_id, newc->id);
- }
- if (oldc->first_rb != newc->first_rb) {
- flexran_set_ul_slice_first_rb(mod_id, slice_idx, newc->first_rb);
- changes++;
- }
- /*if (oldc->length_rb != newc->length_rb) {
- flexran_set_ul_slice_length_rb(mod_id, slice_idx, newc->length_rb);
- changes++;
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting length_rb is not supported\n",
- mod_id, newc->id);
- }*/
- if (oldc->maxmcs != newc->maxmcs) {
- flexran_set_ul_slice_maxmcs(mod_id, slice_idx, newc->maxmcs);
- changes++;
- }
- /*if (check_ul_sorting_update(oldc, newc)) {
- flexran_set_ul_slice_sorting(mod_id, slice_idx, newc->sorting, n);
- changes++;
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the sorting is not supported\n",
- mod_id, newc->id);
- }*/
- if (oldc->accounting != newc->accounting) {
- /*flexran_set_ul_slice_accounting_policy(mod_id, slice_idx, newc->accounting);
- *changes++;*/
- LOG_W(FLEXRAN_AGENT, "[%d][UL slice %d] setting the accounting is not supported\n",
- mod_id, newc->id);
- }
- if (!oldc->scheduler_name
- || strcmp(oldc->scheduler_name, newc->scheduler_name) != 0) {
- int ret = flexran_set_ul_slice_scheduler(mod_id, slice_idx, newc->scheduler_name);
- AssertFatal(ret, "could not set DL slice scheduler for slice %d idx %d\n",
- newc->id, slice_idx);
- changes++;
- }
- return changes;
-}
-
-void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config)
-{
- if (n_ue_slice_assoc_updates == MAX_NUM_SLICES) {
- LOG_E(FLEXRAN_AGENT,
- "[%d] can not handle flex_ue_config message, buffer is full; try again later\n",
- mod_id);
- return;
- }
if (!ue_config->has_rnti) {
LOG_E(FLEXRAN_AGENT,
"[%d] cannot update UE to slice association, no RNTI in flex_ue_config message\n",
mod_id);
- return;
+ return 0;
}
- if (ue_config->has_dl_slice_id)
- LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to DL slice ID %d\n",
- mod_id, ue_config->rnti, ue_config->dl_slice_id);
- if (ue_config->has_ul_slice_id)
- LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %#x to UL slice ID %d\n",
- mod_id, ue_config->rnti, ue_config->ul_slice_id);
- ue_slice_assoc_update[n_ue_slice_assoc_updates++] = ue_config;
- perform_slice_config_update_count = 2;
-}
-
-int apply_ue_slice_assoc_update(mid_t mod_id)
-{
- int i;
- int changes = 0;
- for (i = 0; i < n_ue_slice_assoc_updates; i++) {
- int ue_id = find_UE_id(mod_id, ue_slice_assoc_update[i]->rnti);
- if (ue_id < 0 || ue_id > MAX_MOBILES_PER_ENB){
- LOG_E(FLEXRAN_AGENT,"UE_id %d is wrong!!\n",ue_id);
- continue;
- }
- if (ue_slice_assoc_update[i]->has_dl_slice_id) {
- int slice_idx = flexran_find_dl_slice(mod_id, ue_slice_assoc_update[i]->dl_slice_id);
- if (flexran_dl_slice_exists(mod_id, slice_idx)) {
- flexran_set_ue_dl_slice_idx(mod_id, ue_id, slice_idx);
- changes++;
- } else {
- LOG_W(FLEXRAN_AGENT, "[%d] DL slice %d does not exist, refusing change\n",
- mod_id, ue_slice_assoc_update[i]->dl_slice_id);
- }
+ int UE_id = flexran_get_mac_ue_id_rnti(mod_id, ue_config->rnti);
+ if (ue_config->has_dl_slice_id) {
+ if (flexran_get_dl_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "no DL slice algorithm loaded\n");
+ } else {
+ LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to DL slice ID %d\n",
+ mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->dl_slice_id);
+ flexran_set_ue_dl_slice_id(mod_id, UE_id, ue_config->dl_slice_id);
}
- if (ue_slice_assoc_update[i]->has_ul_slice_id) {
- int slice_idx = flexran_find_ul_slice(mod_id, ue_slice_assoc_update[i]->ul_slice_id);
- if (flexran_ul_slice_exists(mod_id, slice_idx)) {
- flexran_set_ue_ul_slice_idx(mod_id, ue_id, slice_idx);
- changes++;
- } else {
- LOG_W(FLEXRAN_AGENT, "[%d] UL slice %d does not exist, refusing change\n",
- mod_id, ue_slice_assoc_update[i]->ul_slice_id);
- }
+ }
+ if (ue_config->has_ul_slice_id) {
+ if (flexran_get_ul_slice_algo(mod_id) == PROTOCOL__FLEX_SLICE_ALGORITHM__None) {
+ LOG_E(FLEXRAN_AGENT, "no UL slice algorithm loaded\n");
+ } else {
+ LOG_I(FLEXRAN_AGENT, "[%d] associating UE RNTI %04x - %d/UE %d to UL slice ID %d\n",
+ mod_id, ue_config->rnti, ue_config->rnti, UE_id, ue_config->ul_slice_id);
+ flexran_set_ue_ul_slice_id(mod_id, UE_id, ue_config->ul_slice_id);
}
}
- n_ue_slice_assoc_updates = 0;
- return changes;
+ return 0;
}
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h
index 957fe6065edfee892de34e17c436cbc84a275fc5..9db5d61a11693ca899811628d9eb18d7592f716d 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_internal.h
@@ -103,43 +103,11 @@ int load_dl_scheduler_function(mid_t mod_id, const char *function_name);
/*** Functions for handling a slice config ***/
-/* allocate memory for a Protocol__FlexSliceConfig structure with n_dl DL slice
- * configs and m_ul UL slice configs */
-Protocol__FlexSliceConfig *flexran_agent_create_slice_config(int n_dl, int m_ul);
-
-/* read the general slice parameters via RAN into the given
- * Protocol__FlexSliceConfig struct */
-void flexran_agent_read_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *s);
-
-/* read the DL slice config via the RAN into a given Protocol__FlexDlSlice
- * struct */
-void flexran_agent_read_slice_dl_config(mid_t mod_id, int slice_idx, Protocol__FlexDlSlice *dl_slice);
-
-/* read the UL slice config via the RAN into a given Protocol__FlexUlSlice
- * struct */
-void flexran_agent_read_slice_ul_config(mid_t mod_id, int slice_idx, Protocol__FlexUlSlice *ul_slice);
-
-/* reads content of slice over the sc_update structure, so that it can be
- * applied later by performing a diff between slice_config and sc_update */
-void prepare_update_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *slice);
-
-/* apply generic slice parameters (e.g. intra-/interslice sharing activated or
- * not) if there are changes. Returns the number of changed parameters. */
-int apply_new_slice_config(mid_t mod_id, Protocol__FlexSliceConfig *olds, Protocol__FlexSliceConfig *news);
-
-/* apply new configuration of slice in DL if there are changes between the
- * parameters. Returns the number of changed parameters. */
-int apply_new_slice_dl_config(mid_t mod_id, Protocol__FlexDlSlice *oldc, Protocol__FlexDlSlice *newc);
-
-/* apply new configuration of slice in UL if there are changes between the
- * parameters. Returns the number of changed parameters. */
-int apply_new_slice_ul_config(mid_t mod_id, Protocol__FlexUlSlice *oldc, Protocol__FlexUlSlice *newc);
-
-/* inserts a new ue_config into the structure keeping ue to slice association
- * updates and marks so it can be applied */
-void prepare_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config);
+/* Prepare the application of a slicing config */
+void apply_update_dl_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice);
+void apply_update_ul_slice_config(mid_t mod_id, Protocol__FlexSliceDlUlConfig *slice);
/* apply a new association between a UE and a slice (both DL and UL) */
-int apply_ue_slice_assoc_update(mid_t mod_id);
+int apply_ue_slice_assoc_update(mid_t mod_id, Protocol__FlexUeConfig *ue_config);
#endif /*FLEXRAN_AGENT_MAC_INTERNAL_H_*/
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c
index 67329e91be0d9508c5943dd527dfb990ef654201..6e54e155c260cb86d5358298409e26691ca8910a 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.c
@@ -28,346 +28,3 @@
#include "flexran_agent_mac_slice_verification.h"
-
-/* overlap check for UL slices, helper type */
-struct sregion_s {
- int start;
- int length;
-};
-
-/* forward declaration of locally-used verification functions */
-int flexran_dl_slice_verify_pct(int pct);
-int flexran_dl_slice_verify_priority(int prio);
-int flexran_dl_slice_verify_position(int pos_low, int pos_high);
-int flexran_dl_slice_verify_maxmcs(int maxmcs);
-int flexran_ul_slice_verify_pct(int pct);
-int flexran_ul_slice_verify_priority(int prio);
-int flexran_ul_slice_verify_first_rb(int first_rb);
-int flexran_ul_slice_verify_maxmcs(int maxmcs);
-int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n);
-
-int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls)
-{
- /* check mandatory parameters */
- if (!dls->has_id) {
- LOG_E(FLEXRAN_AGENT, "[%d] Incoming DL slice configuration has no ID\n", mod_id);
- return 0;
- }
-
- /* verify parameters individualy */
- /* label is enum */
- if (!flexran_dl_slice_verify_pct(dls->percentage)) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice percentage (%d)\n",
- mod_id, dls->id, dls->percentage);
- return 0;
- }
- /* isolation is a protobuf bool */
- if (!flexran_dl_slice_verify_priority(dls->priority)) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice priority (%d)\n",
- mod_id, dls->id, dls->priority);
- return 0;
- }
- if (!flexran_dl_slice_verify_position(dls->position_low, dls->position_high)) {
- LOG_E(FLEXRAN_AGENT,
- "[%d][DL slice %d] illegal DL slice position low (%d) and/or high (%d)\n",
- mod_id, dls->id, dls->position_low, dls->position_high);
- return 0;
- }
- if (!flexran_dl_slice_verify_maxmcs(dls->maxmcs)) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] illegal DL slice max mcs %d\n",
- mod_id, dls->id, dls->maxmcs);
- return 0;
- }
- if (dls->n_sorting == 0) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting in DL slice\n",
- mod_id, dls->id);
- return 0;
- }
- if (!dls->sorting) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no sorting found in DL slice\n",
- mod_id, dls->id);
- return 0;
- }
- /* sorting is an enum */
- /* accounting is an enum */
- if (!dls->scheduler_name) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] no scheduler name found\n",
- mod_id, dls->id);
- return 0;
- }
- if (strcmp(dls->scheduler_name, "schedule_ue_spec") != 0) {
- LOG_E(FLEXRAN_AGENT, "[%d][DL slice %d] setting the scheduler to something "
- "different than schedule_ue_spec is currently not allowed\n",
- mod_id, dls->id);
- return 0;
- }
-
- return 1;
-}
-
-int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing,
- int n_ex, Protocol__FlexDlSlice **update, int n_up)
-{
- int i, j, n;
- int pct, pct_orig;
- /* for every update, array points to existing slice, or NULL if update
- * creates new slice */
- Protocol__FlexDlSlice *s[n_up];
- for (i = 0; i < n_up; i++) {
- s[i] = NULL;
- for (j = 0; j < n_ex; j++) {
- if (existing[j]->id == update[i]->id)
- s[i] = existing[j];
- }
- }
-
- /* check that number of created and number of added slices in total matches
- * [1,10] */
- n = n_ex;
- for (i = 0; i < n_up; i++) {
- /* new slice */
- if (!s[i]) n += 1;
- /* slice will be deleted */
- else if (s[i]->percentage == 0) n -= 1;
- /* else "only" an update */
- }
-
- if (n < 1 || n > MAX_NUM_SLICES) {
- LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting DL slices (%d -> %d)\n",
- mod_id, n_ex, n);
- return 0;
- }
-
- /* check that the sum of all slices percentages (including removed/added
- * slices) matches [1,100] */
- pct = 0;
- for (i = 0; i < n_ex; i++) {
- pct += existing[i]->percentage;
- }
- pct_orig = pct;
- for (i = 0; i < n_up; i++) {
- /* if there is an existing slice, subtract its percentage and add the
- * update's percentage */
- if (s[i])
- pct -= s[i]->percentage;
- pct += update[i]->percentage;
- }
- if (pct < 1 || pct > 100) {
- LOG_E(FLEXRAN_AGENT,
- "[%d] invalid total RB share for DL slices (%d%% -> %d%%)\n",
- mod_id, pct_orig, pct);
- return 0;
- }
-
- return 1;
-}
-
-int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls)
-{
- /* check mandatory parameters */
- if (!uls->has_id) {
- LOG_E(FLEXRAN_AGENT, "[%d] Incoming UL slice configuration has no ID\n", mod_id);
- return 0;
- }
-
- /* verify parameters individually */
- /* label is enum */
- if (!flexran_ul_slice_verify_pct(uls->percentage)) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n",
- mod_id, uls->id, uls->percentage);
- return 0;
- }
- /* isolation is a protobuf bool */
- if (!flexran_ul_slice_verify_priority(uls->priority)) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice percentage (%d)\n",
- mod_id, uls->id, uls->priority);
- return 0;
- }
- if (!flexran_ul_slice_verify_first_rb(uls->first_rb)) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice first RB (%d)\n",
- mod_id, uls->id, uls->first_rb);
- return 0;
- }
- if (!flexran_ul_slice_verify_maxmcs(uls->maxmcs)) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] illegal UL slice max mcs (%d)\n",
- mod_id, uls->id, uls->maxmcs);
- return 0;
- }
- /* TODO
- if (uls->n_sorting == 0) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting in UL slice\n",
- mod_id, uls->id);
- return 0;
- }
- if (!uls->sorting) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no sorting found in UL slice\n",
- mod_id, uls->id);
- return 0;
- }
- */
- /* sorting is an enum */
- /* accounting is an enum */
- if (!uls->scheduler_name) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] no scheduler name found\n",
- mod_id, uls->id);
- return 0;
- }
- if (strcmp(uls->scheduler_name, "schedule_ulsch_rnti") != 0) {
- LOG_E(FLEXRAN_AGENT, "[%d][UL slice %d] setting the scheduler to something "
- "different than schedule_ulsch_rnti is currently not allowed\n",
- mod_id, uls->id);
- return 0;
- }
-
- return 1;
-}
-
-int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing,
- int n_ex, Protocol__FlexUlSlice **update, int n_up)
-{
- int i, j, n;
- int pct, pct_orig;
- /* for every update, array "s" points to existing slice, or NULL if update
- * creates new slice; array "offs" gives the offset of this slice */
- Protocol__FlexUlSlice *s[n_up];
- int offs[n_up];
- for (i = 0; i < n_up; i++) {
- s[i] = NULL;
- offs[i] = 0;
- for (j = 0; j < n_ex; j++) {
- if (existing[j]->id == update[i]->id) {
- s[i] = existing[j];
- offs[i] = j;
- }
- }
- }
-
- /* check that number of created and number of added slices in total matches
- * [1,10] */
- n = n_ex;
- for (i = 0; i < n_up; i++) {
- /* new slice */
- if (!s[i]) n += 1;
- /* slice will be deleted */
- else if (s[i]->percentage == 0) n -= 1;
- /* else "only" an update */
- }
-
- if (n < 1 || n > MAX_NUM_SLICES) {
- LOG_E(FLEXRAN_AGENT, "[%d] Illegal number of resulting UL slices (%d -> %d)\n",
- mod_id, n_ex, n);
- return 0;
- }
-
- /* check that the sum of all slices percentages (including removed/added
- * slices) matches [1,100] */
- pct = 0;
- for (i = 0; i < n_ex; i++) {
- pct += existing[i]->percentage;
- }
- pct_orig = pct;
- for (i = 0; i < n_up; i++) {
- /* if there is an existing slice, subtract its percentage and add the
- * update's percentage */
- if (s[i])
- pct -= s[i]->percentage;
- pct += update[i]->percentage;
- }
- if (pct < 1 || pct > 100) {
- LOG_E(FLEXRAN_AGENT, "[%d] invalid total RB share (%d%% -> %d%%)\n",
- mod_id, pct_orig, pct);
- return 0;
- }
-
- /* check that there is no overlap in slices resulting as the combination of
- * first_rb and percentage */
- struct sregion_s sregion[n];
- const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */
- int k = n_ex;
- for (i = 0; i < n_ex; i++) {
- sregion[i].start = existing[i]->first_rb;
- sregion[i].length = existing[i]->percentage * N_RB / 100;
- }
- for (i = 0; i < n_up; i++) {
- ptrdiff_t d = s[i] ? offs[i] : k++;
- AssertFatal(d >= 0 && d < k, "illegal pointer offset (%ld, k=%d)\n", d, k);
- sregion[d].start = update[i]->first_rb;
- sregion[d].length = update[i]->percentage * N_RB / 100;
- }
- AssertFatal(k == n, "illegal number of slices while calculating overlap\n");
- if (!check_ul_slice_overlap(mod_id, sregion, k)) {
- LOG_E(FLEXRAN_AGENT, "[%d] UL slices are overlapping\n", mod_id);
- return 0;
- }
-
- return 1;
-}
-
-int flexran_dl_slice_verify_pct(int pct)
-{
- return pct >= 0 && pct <= 100;
-}
-
-int flexran_dl_slice_verify_priority(int prio)
-{
- return prio >= 0;
-}
-
-int flexran_dl_slice_verify_position(int pos_low, int pos_high)
-{
- return pos_low < pos_high && pos_low >= 0 && pos_high <= N_RBG_MAX;
-}
-
-int flexran_dl_slice_verify_maxmcs(int maxmcs)
-{
- return maxmcs >= 0 && maxmcs <= 28;
-}
-
-int flexran_ul_slice_verify_pct(int pct)
-{
- return pct >= 0 && pct <= 100;
-}
-
-int flexran_ul_slice_verify_priority(int prio)
-{
- return prio >= 0;
-}
-
-int flexran_ul_slice_verify_first_rb(int first_rb)
-{
- return first_rb >= 0 && first_rb < 100;
-}
-
-int flexran_ul_slice_verify_maxmcs(int maxmcs)
-{
- return maxmcs >= 0 && maxmcs <= 20;
-}
-
-int sregion_compare(const void *_a, const void *_b)
-{
- const struct sregion_s *a = (const struct sregion_s *)_a;
- const struct sregion_s *b = (const struct sregion_s *)_b;
- const int res = a->start - b->start;
- if (res < 0) return -1;
- else if (res == 0) return 0;
- else return 1;
-}
-
-int check_ul_slice_overlap(mid_t mod_id, struct sregion_s *sr, int n)
-{
- int i;
- int overlap, op, u;
- const int N_RB = flexran_get_N_RB_UL(mod_id, 0); /* assume PCC */
- qsort(sr, n, sizeof(sr[0]), sregion_compare);
- for (i = 0; i < n; i++) {
- u = i == n-1 ? N_RB : sr[i+1].start;
- AssertFatal(sr[i].start <= u, "unsorted slice list\n");
- overlap = sr[i].start + sr[i].length - u;
- if (overlap <= 0) continue;
- op = overlap * 100 / sr[i].length;
- LOG_W(FLEXRAN_AGENT, "[%d] slice overlap of %d%% detected\n", mod_id, op);
- if (op >= 10) /* more than 10% overlap -> refuse */
- return 0;
- }
- return 1;
-}
diff --git a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h
index a8f4030d3664be1e1388d8d42cae8feed9a4dd90..c9e66b6f88236c9410f19a429ca916fafdf07f20 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h
+++ b/openair2/ENB_APP/CONTROL_MODULES/MAC/flexran_agent_mac_slice_verification.h
@@ -29,9 +29,3 @@
#include "flexran_agent_common_internal.h"
#include "flexran_agent_mac_internal.h"
-int flexran_verify_dl_slice(mid_t mod_id, Protocol__FlexDlSlice *dls);
-int flexran_verify_group_dl_slices(mid_t mod_id, Protocol__FlexDlSlice **existing,
- int n_ex, Protocol__FlexDlSlice **update, int n_up);
-int flexran_verify_ul_slice(mid_t mod_id, Protocol__FlexUlSlice *uls);
-int flexran_verify_group_ul_slices(mid_t mod_id, Protocol__FlexUlSlice **existing,
- int n_ex, Protocol__FlexUlSlice **update, int n_up);
diff --git a/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c b/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c
index 92c991762266f2bf0ed7affbc842d2d8b108487f..ec907a1956ca56b12b06e2c537c7fc4873eb9ab6 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c
+++ b/openair2/ENB_APP/CONTROL_MODULES/RRC/flexran_agent_rrc.c
@@ -921,7 +921,4 @@ int flexran_agent_unregister_rrc_xface(mid_t mod_id)
return 0;
}
-AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id)
-{
- return agent_rrc_xface[mod_id];
-}
+
diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c
index 04a47406e1b9d6e7f58acd9ae9da94a4d3dbff63..c2d7cb9e552bc0746b307a1af0bc57367b01d8f3 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c
+++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.c
@@ -125,6 +125,63 @@ void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply) {
}
}
+void flexran_agent_handle_mme_update(mid_t mod_id,
+ size_t n_mme,
+ Protocol__FlexS1apMme **mme) {
+ if (n_mme == 0 || n_mme > 1) {
+ LOG_E(FLEXRAN_AGENT, "cannot handle %lu MMEs yet\n", n_mme);
+ return;
+ }
+
+ if (!mme[0]->s1_ip) {
+ LOG_E(FLEXRAN_AGENT, "no S1 IP present, cannot handle request\n");
+ return;
+ }
+
+ if (mme[0]->has_state
+ && mme[0]->state == PROTOCOL__FLEX_MME_STATE__FLMMES_DISCONNECTED) {
+ int rc = flexran_remove_s1ap_mme(mod_id, 1, &mme[0]->s1_ip);
+ if (rc == 0)
+ LOG_I(FLEXRAN_AGENT, "remove MME at IP %s\n", mme[0]->s1_ip);
+ else
+ LOG_W(FLEXRAN_AGENT,
+ "could not remove MME: flexran_remove_s1ap_mme() returned %d\n",
+ rc);
+ } else {
+ int rc = flexran_add_s1ap_mme(mod_id, 1, &mme[0]->s1_ip);
+ if (rc == 0)
+ LOG_I(FLEXRAN_AGENT, "add MME at IP %s\n", mme[0]->s1_ip);
+ else
+ LOG_W(FLEXRAN_AGENT,
+ "could not add MME: flexran_add_s1ap_mme() returned %d\n",
+ rc);
+ }
+}
+
+void flexran_agent_handle_plmn_update(mid_t mod_id,
+ int CC_id,
+ size_t n_plmn,
+ Protocol__FlexPlmn **plmn_id) {
+ if (n_plmn < 1 || n_plmn > 6) {
+ LOG_E(FLEXRAN_AGENT, "cannot handle %lu PLMNs\n", n_plmn);
+ return;
+ }
+
+ /* We assume the controller has checked all the parameters within each
+ * plmn_id */
+ int rc = flexran_set_new_plmn_id(mod_id, CC_id, n_plmn, plmn_id);
+ if (rc == 0) {
+ LOG_I(FLEXRAN_AGENT, "set %lu new PLMNs:\n", n_plmn);
+ for (int i = 0; i < (int)n_plmn; ++i)
+ LOG_I(FLEXRAN_AGENT, " MCC %d MNC %d MNC length %d\n",
+ plmn_id[i]->mcc, plmn_id[i]->mnc, plmn_id[0]->mnc_length);
+ } else {
+ LOG_W(FLEXRAN_AGENT,
+ "could not set new PLMN configuration: flexran_set_new_plmn_id() returned %d\n",
+ rc);
+ }
+}
+
int flexran_agent_register_s1ap_xface(mid_t mod_id) {
if (agent_s1ap_xface[mod_id]) {
LOG_E(FLEXRAN_AGENT, "S1AP agent CM for eNB %d is already registered\n", mod_id);
diff --git a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h
index 1cca6ac9c15e0a26d59b2b832fdd361d31c65de8..006eaa1d3ca67f571fd764409d930af620394b9e 100644
--- a/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h
+++ b/openair2/ENB_APP/CONTROL_MODULES/S1AP/flexran_agent_s1ap.h
@@ -60,6 +60,17 @@ int flexran_agent_s1ap_stats_reply(mid_t mod_id,
/* Free allocated S1AP stats message */
void flexran_agent_s1ap_destroy_stats_reply(Protocol__FlexStatsReply *reply);
+/* Add or remove MME updates */
+void flexran_agent_handle_mme_update(mid_t mod_id,
+ size_t n_mme,
+ Protocol__FlexS1apMme **mme);
+
+/* Set a new PLMN configuration */
+void flexran_agent_handle_plmn_update(mid_t mod_id,
+ int CC_id,
+ size_t n_plmn,
+ Protocol__FlexPlmn **plmn_id);
+
/* Register technology specific interface callbacks */
int flexran_agent_register_s1ap_xface(mid_t mod_id);
diff --git a/openair2/ENB_APP/L1_paramdef.h b/openair2/ENB_APP/L1_paramdef.h
index 210b753afbb19e84ba04693393651f1d73442373..72e77c38000c44da6d5ebb4b5e6a79fab8f8a16a 100644
--- a/openair2/ENB_APP/L1_paramdef.h
+++ b/openair2/ENB_APP/L1_paramdef.h
@@ -30,6 +30,8 @@
* \warning
*/
+#ifndef __ENB_APP_L1_PARAMDEF__H__
+#define __ENB_APP_L1_PARAMDEF__H__
/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
@@ -114,3 +116,5 @@
#define L1_PUCCH1_DTX_EMTC3_THRESHOLD_IDX 22
#define L1_PUCCH1AB_DTX_EMTC3_THRESHOLD_IDX 23
/*----------------------------------------------------------------------------------------------------------------------------------------------------*/
+
+#endif
diff --git a/openair2/ENB_APP/MACRLC_paramdef.h b/openair2/ENB_APP/MACRLC_paramdef.h
index 724dde6557e01bffc2c1a33f905b1dd5c7311577..fcee6142f0bc7cce1a0cec70f4b19e93267e669a 100644
--- a/openair2/ENB_APP/MACRLC_paramdef.h
+++ b/openair2/ENB_APP/MACRLC_paramdef.h
@@ -31,6 +31,8 @@
*/
+#ifndef __ENB_APP_MACRLC_PARAMDEF__H__
+#define __ENB_APP_MACRLC_PARAMDEF__H__
/*----------------------------------------------------------------------------------------------------------------------------------------------------*/
@@ -56,6 +58,7 @@
#define CONFIG_STRING_MACRLC_SCHED_MODE "scheduler_mode"
#define CONFIG_MACRLC_PUSCH10xSNR "puSch10xSnr"
#define CONFIG_MACRLC_PUCCH10xSNR "puCch10xSnr"
+#define CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO "default_sched_dl_algo"
/*-------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* MacRLC configuration parameters */
@@ -82,6 +85,7 @@
{CONFIG_STRING_MACRLC_SCHED_MODE, NULL, 0, strptr:NULL, defstrval:"default", TYPE_STRING, 0}, \
{CONFIG_MACRLC_PUSCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \
{CONFIG_MACRLC_PUCCH10xSNR, NULL, 0, iptr:NULL, defintval:200, TYPE_INT, 0}, \
+{CONFIG_STRING_MACRLC_DEFAULT_SCHED_DL_ALGO, NULL, 0, strptr:NULL, defstrval:"round_robin_dl", TYPE_STRING, 0}, \
}
#define MACRLC_CC_IDX 0
#define MACRLC_TRANSPORT_N_PREFERENCE_IDX 1
@@ -103,4 +107,7 @@
#define MACRLC_SCHED_MODE_IDX 17
#define MACRLC_PUSCH10xSNR_IDX 18
#define MACRLC_PUCCH10xSNR_IDX 19
+#define MACRLC_DEFAULT_SCHED_DL_ALGO_IDX 20
/*---------------------------------------------------------------------------------------------------------------------------------------------------------*/
+
+#endif
diff --git a/openair2/ENB_APP/MESSAGES/V2/config_common.proto b/openair2/ENB_APP/MESSAGES/V2/config_common.proto
index 733d883c92c0ed5af68e848051e6d2783ff937d6..2f2267b62815ac3891981a0088355c2423112410 100644
--- a/openair2/ENB_APP/MESSAGES/V2/config_common.proto
+++ b/openair2/ENB_APP/MESSAGES/V2/config_common.proto
@@ -61,82 +61,30 @@ enum flex_qam {
//
// Slice config related structures and enums
//
-enum flex_dl_sorting {
-
- CR_ROUND = 0; // Highest HARQ first
- CR_SRB12 = 1; // Highest SRB1+2 first
- CR_HOL = 2; // Highest HOL first
- CR_LC = 3; // Greatest RLC buffer first
- CR_CQI = 4; // Highest CQI first
- CR_LCP = 5; // Highest LC priority first
-}
-
-enum flex_ul_sorting {
- CRU_ROUND = 0; // Highest HARQ first
- CRU_BUF = 1; // Highest BSR first
- CRU_BTS = 2; // More bytes to schedule first
- CRU_MCS = 3; // Highest MCS first
- CRU_LCP = 4; // Highest LC priority first
- CRU_HOL = 5; // Highest HOL first
-}
-
-enum flex_dl_accounting_policy {
- POL_FAIR = 0;
- POL_GREEDY = 1;
- POL_NUM = 2;
-}
-
-enum flex_ul_accounting_policy {
- POLU_FAIR = 0;
- POLU_GREEDY = 1;
- POLU_NUM = 2;
-}
-
-enum flex_slice_label {
- xMBB = 0;
- URLLC = 1;
- mMTC = 2;
- xMTC = 3;
- Other = 4;
-}
-
-message flex_dl_slice {
- optional uint32 id = 1;
- optional flex_slice_label label = 2;
- // should be between 0 and 100
- optional uint32 percentage = 3;
- // whether this slice should be exempted form interslice sharing
- optional bool isolation = 4;
- // increasing value means increasing prio
- optional uint32 priority = 5;
- // min and max RB to use (in frequency) in the range [0, N_RBG_MAX]
- optional uint32 position_low = 6;
- optional uint32 position_high = 7;
- // maximum MCS to be allowed in this slice
- optional uint32 maxmcs = 8;
- repeated flex_dl_sorting sorting = 9;
- optional flex_dl_accounting_policy accounting = 10;
- optional string scheduler_name = 11;
-}
-
-message flex_ul_slice {
- optional uint32 id = 1;
- optional flex_slice_label label = 2;
- // should be between 0 and 100
- optional uint32 percentage = 3;
- // whether this slice should be exempted form interslice sharing
- optional bool isolation = 4;
- // increasing value means increasing prio
- optional uint32 priority = 5;
- // RB start to use (in frequency) in the range [0, N_RB_MAX]
- optional uint32 first_rb = 6;
- // TODO RB number
- //optional uint32 length_rb = 7;
- // maximum MCS to be allowed in this slice
- optional uint32 maxmcs = 8;
- repeated flex_ul_sorting sorting = 9;
- optional flex_ul_accounting_policy accounting = 10;
- optional string scheduler_name = 11;
+enum flex_slice_algorithm {
+ None = 0;
+ Static = 1;
+ NVS = 2;
+}
+
+message flex_slice_static {
+ optional uint32 posLow = 1;
+ optional uint32 posHigh = 2;
+}
+
+message flex_slice {
+ optional uint32 id = 1;
+ optional string label = 2;
+ optional string scheduler = 3;
+ oneof params {
+ flex_slice_static static = 10;
+ }
+}
+
+message flex_slice_dl_ul_config {
+ optional flex_slice_algorithm algorithm = 1;
+ repeated flex_slice slices = 2;
+ optional string scheduler = 3; // if no slicing
}
//
diff --git a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto
index 324153613d396307e3a37bce643bdcb60220e19e..1a69deec7146e2941e91f0f894ee9d7c680d97c7 100644
--- a/openair2/ENB_APP/MESSAGES/V2/config_messages.proto
+++ b/openair2/ENB_APP/MESSAGES/V2/config_messages.proto
@@ -49,14 +49,8 @@ message flex_cell_config {
}
message flex_slice_config {
- // whether remaining RBs after first intra-slice allocation will
- // be allocated to UEs of the same slice
- optional bool intraslice_share_active = 3;
- // whether remaining RBs after slice allocation will be allocated
- // to UEs of another slice. Isolated slices will be ignored.
- optional bool interslice_share_active = 4;
- repeated flex_dl_slice dl = 1;
- repeated flex_ul_slice ul = 2;
+ optional flex_slice_dl_ul_config dl = 6;
+ optional flex_slice_dl_ul_config ul = 7;
}
message flex_ue_config {
diff --git a/openair2/ENB_APP/NB_IoT_paramdef.h b/openair2/ENB_APP/NB_IoT_paramdef.h
index 6409fe63ee56479b9cc1fca486b9d63bd77f8bda..8778f6d2e4067cf2f7a49f1a2dd1d0a97503df58 100644
--- a/openair2/ENB_APP/NB_IoT_paramdef.h
+++ b/openair2/ENB_APP/NB_IoT_paramdef.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __ENB_APP_NB_IOT_PARAMDEF__H__
+#define __ENB_APP_NB_IOT_PARAMDEF__H__
+
#include "common/config/config_paramdesc.h"
#include "SystemInformationBlockType2.h"
#include "DL-GapConfig-NB-r13.h"
@@ -398,3 +401,5 @@
/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* NB IoT L1 configuration list section name */
#define NBIOT_L1LIST_CONFIG_STRING "NB-IoT_L1s"
+
+#endif
diff --git a/openair2/ENB_APP/enb_app.c b/openair2/ENB_APP/enb_app.c
index 0e1c7e64bc8025ad5358f952ed2800c71ebbac32..1d001022d21078f94f702327cb73fc5964c4b74f 100644
--- a/openair2/ENB_APP/enb_app.c
+++ b/openair2/ENB_APP/enb_app.c
@@ -214,7 +214,7 @@ void *eNB_app_task(void *args_p) {
long x2_enb_register_retry_timer_id;
uint32_t m2_register_enb_pending = 0;
uint32_t m2_registered_enb = 0;
- long m2_enb_register_retry_timer_id;
+ //long m2_enb_register_retry_timer_id;
MessageDef *msg_p = NULL;
instance_t instance;
int result;
@@ -236,16 +236,11 @@ void *eNB_app_task(void *args_p) {
/* Try to register each eNB with MCE each other */
if (is_m2ap_eNB_enabled() /*&& !NODE_IS_DU(RC.rrc[0]->node_type)*/) {
//eNB_app_register_MBMS_STA(RC.rrc[0]->node_type, enb_id_start, enb_id_end);
- //m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end);
+ m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end);
- if (timer_setup (5, 0, TASK_ENB_APP, INSTANCE_DEFAULT, TIMER_ONE_SHOT,
- NULL, &m2_enb_register_retry_timer_id) < 0) {
- //LOG_E(ENB_APP, " Can not start eNB register retry timer, use \"sleep\" instead!\n");
- //sleep(ENB_REGISTER_RETRY_DELAY);
- /* Restart the registration process */
- //registered_enb = 0;
- //register_enb_pending = eNB_app_register (RC.rrc[0]->node_type,enb_id_start, enb_id_end);
- }
+ //if (timer_setup (5, 0, TASK_ENB_APP, INSTANCE_DEFAULT, TIMER_ONE_SHOT,
+ // NULL, &m2_enb_register_retry_timer_id) < 0) {
+ //}
}
@@ -273,7 +268,6 @@ void *eNB_app_task(void *args_p) {
if (EPC_MODE_ENABLED) {
LOG_I(ENB_APP, "[eNB %d] Received %s: associated MME %d\n", instance, ITTI_MSG_NAME (msg_p),
S1AP_REGISTER_ENB_CNF(msg_p).nb_mme);
- DevAssert(register_enb_pending > 0);
register_enb_pending--;
/* Check if at least eNB is registered with one MME */
@@ -377,11 +371,11 @@ void *eNB_app_task(void *args_p) {
}
} /* if (EPC_MODE_ENABLED) */
- if(TIMER_HAS_EXPIRED (msg_p).timer_id == m2_enb_register_retry_timer_id) {
-
- LOG_I(ENB_APP, " Received %s: timer_id %ld M2 register\n", ITTI_MSG_NAME (msg_p), TIMER_HAS_EXPIRED(msg_p).timer_id);
- m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end);
- }
+// if(TIMER_HAS_EXPIRED (msg_p).timer_id == m2_enb_register_retry_timer_id) {
+//
+// LOG_I(ENB_APP, " Received %s: timer_id %ld M2 register\n", ITTI_MSG_NAME (msg_p), TIMER_HAS_EXPIRED(msg_p).timer_id);
+// m2_register_enb_pending = eNB_app_register_m2 (enb_id_start, enb_id_end);
+// }
break;
diff --git a/openair2/ENB_APP/enb_config.c b/openair2/ENB_APP/enb_config.c
index 6dcc57474683b68b2c4d87c7c5c292c4fac51a9b..4c6a7885c3e1168a50a1f1a9aff119d1665d6461 100644
--- a/openair2/ENB_APP/enb_config.c
+++ b/openair2/ENB_APP/enb_config.c
@@ -29,6 +29,7 @@
#include <string.h>
#include <inttypes.h>
+#include <dlfcn.h>
#include "common/utils/LOG/log.h"
#include "assertions.h"
@@ -260,6 +261,16 @@ void RCconfig_macrlc(int macrlc_has_f1[MAX_MAC_INST]) {
global_scheduler_mode=SCHED_MODE_DEFAULT;
printf("sched mode = default %d [%s]\n",global_scheduler_mode,*(MacRLC_ParamList.paramarray[j][MACRLC_SCHED_MODE_IDX].strptr));
}
+
+ char *s = *MacRLC_ParamList.paramarray[j][MACRLC_DEFAULT_SCHED_DL_ALGO_IDX].strptr;
+ void *d = dlsym(NULL, s);
+ AssertFatal(d, "%s(): no default scheduler DL algo '%s' found\n", __func__, s);
+ // release default, add new
+ pp_impl_param_t *dl_pp = &RC.mac[j]->pre_processor_dl;
+ dl_pp->dl_algo.unset(&dl_pp->dl_algo.data);
+ dl_pp->dl_algo = *(default_sched_dl_algo_t *) d;
+ dl_pp->dl_algo.data = dl_pp->dl_algo.setup();
+ LOG_I(ENB_APP, "using default scheduler DL algo '%s'\n", dl_pp->dl_algo.name);
}// j=0..num_inst
} /*else {// MacRLC_ParamList.numelt > 0 // ignore it
@@ -1545,7 +1556,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) {
RRC_CONFIGURATION_REQ(msg_p).eMBMS_configured = 0;
printf("No eMBMS configuration, skipping it\n");
// eMTC configuration
- char brparamspath[MAX_OPTNAME_SIZE*2 + 16];
+ char brparamspath[MAX_OPTNAME_SIZE*2 + 160];
sprintf(brparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_EMTC_PARAMETERS);
config_get(eMTCParams, sizeof(eMTCParams)/sizeof(paramdef_t), brparamspath);
RRC_CONFIGURATION_REQ(msg_p).eMTC_configured = eMTCconfig.eMTC_configured&1;
@@ -1554,7 +1565,7 @@ int RCconfig_RRC(uint32_t i, eNB_RRC_INST *rrc, int macrlc_has_f1) {
else printf("No eMTC configuration, skipping it\n");
// Sidelink configuration
- char SLparamspath[MAX_OPTNAME_SIZE*2 + 16];
+ char SLparamspath[MAX_OPTNAME_SIZE*2 + 160];
sprintf(SLparamspath,"%s.%s", ccspath, ENB_CONFIG_STRING_SL_PARAMETERS);
config_get( SLParams, sizeof(SLParams)/sizeof(paramdef_t), SLparamspath);
// Sidelink Resource pool information
@@ -3041,7 +3052,8 @@ void configure_du_mac(int inst) {
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
diff --git a/openair2/ENB_APP/enb_paramdef_emtc.h b/openair2/ENB_APP/enb_paramdef_emtc.h
index 7ec6f4940a32d9366d9da13baafa7b4747c42438..de774c4ea694d13c5bc75173072606e95f157594 100644
--- a/openair2/ENB_APP/enb_paramdef_emtc.h
+++ b/openair2/ENB_APP/enb_paramdef_emtc.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __ENB_APP_ENB_PARAMDEF_EMTC__H__
+#define __ENB_APP_ENB_PARAMDEF_EMTC__H__
+
#include "common/config/config_paramdesc.h"
#include "RRC_paramsvalues.h"
@@ -405,3 +408,5 @@ typedef struct ccparams_eMTC_s {
{"sib2_interval_ULHoppingConfigCommonModeB_r13_val", NULL, 0, iptr:&eMTCconfig->sib2_interval_ULHoppingConfigCommonModeB_r13_val, defintval:0, TYPE_UINT, 0}, \
{"sib2_mpdcch_pdsch_hoppingOffset_r13", NULL, 0, iptr:&eMTCconfig->sib2_mpdcch_pdsch_hoppingOffset_r13, defintval:1, TYPE_UINT, 0} \
}
+
+#endif
diff --git a/openair2/ENB_APP/enb_paramdef_mce.h b/openair2/ENB_APP/enb_paramdef_mce.h
index 8a4dd157667856947b0678a4f39624c6b82ba381..fdc2731e16b6b2af2b1778023d72983e20d7f9d4 100644
--- a/openair2/ENB_APP/enb_paramdef_mce.h
+++ b/openair2/ENB_APP/enb_paramdef_mce.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __ENB_APP_ENB_PARAMDEF_MCE__H__
+#define __ENB_APP_ENB_PARAMDEF_MCE__H__
+
#include "common/config/config_paramdesc.h"
#include "RRC_paramsvalues.h"
@@ -235,5 +238,4 @@
#define MCE_CONFIG_STRING_NUM_FRAME_IDX 2
#define MCE_CONFIG_STRING_SUBFRAME_ALLOCATION_IDX 3
-
-
+#endif
diff --git a/openair2/ENB_APP/enb_paramdef_mme.h b/openair2/ENB_APP/enb_paramdef_mme.h
index 0ff1df765c07411d5b146e9ecfe73ada65deb0e3..fde9b1c3a871b9bfe4df2dd1a014a481002178c5 100644
--- a/openair2/ENB_APP/enb_paramdef_mme.h
+++ b/openair2/ENB_APP/enb_paramdef_mme.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __ENB_APP_ENB_PARAMDEF_MME__H__
+#define __ENB_APP_ENB_PARAMDEF_MME__H__
+
#include "common/config/config_paramdesc.h"
#include "RRC_paramsvalues.h"
@@ -77,6 +80,4 @@
{MME_CONFIG_STRING_MME_PORT_FOR_M3C, NULL, 0, uptr:&mme_port_for_m3c, defintval:36444L, TYPE_UINT, 0}, \
}
-
-
-
+#endif
diff --git a/openair2/ENB_APP/flexran_agent_common.c b/openair2/ENB_APP/flexran_agent_common.c
index dc320ef974731a4dd1542989ffd81e5a685830c4..7569ca1ac155e45f9cb8dd831c7599c54372a53b 100644
--- a/openair2/ENB_APP/flexran_agent_common.c
+++ b/openair2/ENB_APP/flexran_agent_common.c
@@ -306,6 +306,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) {
if (reply->cell_config[i]->mbsfn_subframe_config_sfalloc)
free(reply->cell_config[i]->mbsfn_subframe_config_sfalloc);
+ /* si_config is shared between MAC and RRC, free here */
if (reply->cell_config[i]->si_config) {
for(int j = 0; j < reply->cell_config[i]->si_config->n_si_message; j++) {
free(reply->cell_config[i]->si_config->si_message[j]);
@@ -316,26 +317,7 @@ int flexran_agent_destroy_enb_config_reply(Protocol__FlexranMessage *msg) {
}
if (reply->cell_config[i]->slice_config) {
- for (int j = 0; j < reply->cell_config[i]->slice_config->n_dl; ++j) {
- if (reply->cell_config[i]->slice_config->dl[j]->n_sorting > 0)
- free(reply->cell_config[i]->slice_config->dl[j]->sorting);
-
- free(reply->cell_config[i]->slice_config->dl[j]->scheduler_name);
- free(reply->cell_config[i]->slice_config->dl[j]);
- }
-
- free(reply->cell_config[i]->slice_config->dl);
-
- for (int j = 0; j < reply->cell_config[i]->slice_config->n_ul; ++j) {
- if (reply->cell_config[i]->slice_config->ul[j]->n_sorting > 0)
- free(reply->cell_config[i]->slice_config->ul[j]->sorting);
-
- free(reply->cell_config[i]->slice_config->ul[j]->scheduler_name);
- free(reply->cell_config[i]->slice_config->ul[j]);
- }
-
- free(reply->cell_config[i]->slice_config->ul);
- free(reply->cell_config[i]->slice_config);
+ flexran_agent_destroy_mac_slice_config(reply->cell_config[i]);
}
free(reply->cell_config[i]);
@@ -893,31 +875,40 @@ int flexran_agent_handle_enb_config_reply(mid_t mod_id, const void *params, Prot
Protocol__FlexranMessage *input = (Protocol__FlexranMessage *)params;
Protocol__FlexEnbConfigReply *enb_config = input->enb_config_reply_msg;
- if (enb_config->n_cell_config == 0) {
- LOG_W(FLEXRAN_AGENT,
- "received enb_config_reply message does not contain a cell_config\n");
- *msg = NULL;
- return 0;
- }
-
if (enb_config->n_cell_config > 1)
LOG_W(FLEXRAN_AGENT, "ignoring slice configs for other cell except cell 0\n");
- if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) {
- prepare_update_slice_config(mod_id, enb_config->cell_config[0]->slice_config);
- } else if (enb_config->cell_config[0]->has_eutra_band
- && enb_config->cell_config[0]->has_dl_freq
- && enb_config->cell_config[0]->has_ul_freq
- && enb_config->cell_config[0]->has_dl_bandwidth) {
- initiate_soft_restart(mod_id, enb_config->cell_config[0]);
- } else if (flexran_agent_get_rrc_xface(mod_id)
- && enb_config->cell_config[0]->has_x2_ho_net_control) {
- LOG_I(FLEXRAN_AGENT,
- "setting X2 HO NetControl to %d\n",
- enb_config->cell_config[0]->x2_ho_net_control);
- const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control);
- if (rc < 0)
- LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network");
+ if (enb_config->n_cell_config > 0) {
+ if (flexran_agent_get_mac_xface(mod_id) && enb_config->cell_config[0]->slice_config) {
+ prepare_update_slice_config(mod_id, &enb_config->cell_config[0]->slice_config);
+ }
+ if (enb_config->cell_config[0]->has_eutra_band
+ && enb_config->cell_config[0]->has_dl_freq
+ && enb_config->cell_config[0]->has_ul_freq
+ && enb_config->cell_config[0]->has_dl_bandwidth) {
+ initiate_soft_restart(mod_id, enb_config->cell_config[0]);
+ }
+ if (flexran_agent_get_rrc_xface(mod_id)
+ && enb_config->cell_config[0]->has_x2_ho_net_control) {
+ LOG_I(FLEXRAN_AGENT,
+ "setting X2 HO NetControl to %d\n",
+ enb_config->cell_config[0]->x2_ho_net_control);
+ const int rc = flexran_set_x2_ho_net_control(mod_id, enb_config->cell_config[0]->x2_ho_net_control);
+ if (rc < 0)
+ LOG_E(FLEXRAN_AGENT, "Error in configuring X2 handover controlled by network");
+ }
+ if (flexran_agent_get_rrc_xface(mod_id) && enb_config->cell_config[0]->n_plmn_id > 0) {
+ flexran_agent_handle_plmn_update(mod_id,
+ 0,
+ enb_config->cell_config[0]->n_plmn_id,
+ enb_config->cell_config[0]->plmn_id);
+ }
+ }
+
+ if (flexran_agent_get_s1ap_xface(mod_id) && enb_config->s1ap) {
+ flexran_agent_handle_mme_update(mod_id,
+ enb_config->s1ap->n_mme,
+ enb_config->s1ap->mme);
}
*msg = NULL;
@@ -930,7 +921,11 @@ int flexran_agent_handle_ue_config_reply(mid_t mod_id, const void *params, Proto
Protocol__FlexUeConfigReply *ue_config_reply = input->ue_config_reply_msg;
for (i = 0; flexran_agent_get_mac_xface(mod_id) && i < ue_config_reply->n_ue_config; i++)
- prepare_ue_slice_assoc_update(mod_id, ue_config_reply->ue_config[i]);
+ prepare_ue_slice_assoc_update(mod_id, &ue_config_reply->ue_config[i]);
+ /* prepare_ue_slice_assoc_update takes ownership of the individual
+ * FlexUeConfig messages. Therefore, mark zero messages to not accidentally
+ * free them twice */
+ ue_config_reply->n_ue_config = 0;
*msg = NULL;
return 0;
diff --git a/openair2/ENB_APP/flexran_agent_extern.h b/openair2/ENB_APP/flexran_agent_extern.h
index 119bc3d44c6b32967efb6e50f64495b5d72960af..2a5930e1a8b5dd9a18704c04d2df7e2ae777572b 100644
--- a/openair2/ENB_APP/flexran_agent_extern.h
+++ b/openair2/ENB_APP/flexran_agent_extern.h
@@ -41,10 +41,13 @@
AGENT_PHY_xface *flexran_agent_get_phy_xface(mid_t mod_id);
/* Control module interface for the communication of the MAC Control Module with the agent */
-AGENT_MAC_xface *flexran_agent_get_mac_xface(mid_t mod_id);
+extern AGENT_MAC_xface *agent_mac_xface[NUM_MAX_ENB];
+#define flexran_agent_get_mac_xface(mod_id) (agent_mac_xface[mod_id])
/* Control module interface for the communication of the RRC Control Module with the agent */
-AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id);
+// AGENT_RRC_xface *flexran_agent_get_rrc_xface(mid_t mod_id);
+extern AGENT_RRC_xface *agent_rrc_xface[NUM_MAX_ENB];
+#define flexran_agent_get_rrc_xface(mod_id) (agent_rrc_xface[mod_id])
/* Control module interface for the communication of the RRC Control Module with the agent */
AGENT_PDCP_xface *flexran_agent_get_pdcp_xface(mid_t mod_id);
diff --git a/openair2/ENB_APP/flexran_agent_ran_api.c b/openair2/ENB_APP/flexran_agent_ran_api.c
index 32cb8c74e18d0cde3f657a4dd4e8246ae752ccfe..79c992a4d7ce678609544616db7187e984f453c3 100644
--- a/openair2/ENB_APP/flexran_agent_ran_api.c
+++ b/openair2/ENB_APP/flexran_agent_ran_api.c
@@ -30,6 +30,7 @@
#include "flexran_agent_ran_api.h"
#include "s1ap_eNB_ue_context.h"
#include "s1ap_eNB_management_procedures.h"
+#include "openair2/LAYER2/MAC/slicing/slicing.h"
static inline int phy_is_present(mid_t mod_id, uint8_t cc_id) {
return RC.eNB && RC.eNB[mod_id] && RC.eNB[mod_id][cc_id];
@@ -3013,471 +3014,293 @@ uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti)
}
/**************************** SLICING ****************************/
-int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id];
-
- if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl)
- return RC.mac[mod_id]->slice_info.dl[slice_idx].id;
-
- return 0;
-}
-
-void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return;
-
- if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return;
-
- if (!flexran_dl_slice_exists(mod_id, slice_idx)) return;
-
- //RC.mac[mod_id]->UE_info.assoc_dl_slice_idx[ue_id] = slice_idx;
-}
-
-int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- int slice_idx = 0; //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id];
-
- if (slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul)
- return RC.mac[mod_id]->slice_info.ul[slice_idx].id;
-
- return 0;
-}
-
-void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return;
-
- if (flexran_get_mac_ue_crnti(mod_id, ue_id) == NOT_A_RNTI) return;
-
- if (!flexran_ul_slice_exists(mod_id, slice_idx)) return;
-
- //RC.mac[mod_id]->UE_info.assoc_ul_slice_idx[ue_id] = slice_idx;
-}
-
-int flexran_dl_slice_exists(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_dl;
-}
-
-int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- int newidx = RC.mac[mod_id]->slice_info.n_dl;
-
- if (newidx >= MAX_NUM_SLICES) return -1;
-
- ++RC.mac[mod_id]->slice_info.n_dl;
- flexran_set_dl_slice_id(mod_id, newidx, slice_id);
- return newidx;
-}
+Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id) {
+ if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None;
-int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- slice_info_t *sli = &RC.mac[mod_id]->slice_info;
- int n = sli->n_dl;
-
- for (int i = 0; i < n; i++) {
- if (sli->dl[i].id == slice_id) return i;
+ switch (RC.mac[mod_id]->pre_processor_dl.algorithm) {
+ case STATIC_SLICING:
+ return PROTOCOL__FLEX_SLICE_ALGORITHM__Static;
+ default:
+ return PROTOCOL__FLEX_SLICE_ALGORITHM__None;
}
-
- return -1;
}
-int flexran_remove_dl_slice(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- slice_info_t *sli = &RC.mac[mod_id]->slice_info;
-
- if (sli->n_dl <= 1) return -1;
-
- if (sli->dl[slice_idx].sched_name) free(sli->dl[slice_idx].sched_name);
-
- --sli->n_dl;
-
- /* move last element to the position of the removed one */
- if (slice_idx != sli->n_dl)
- memcpy(&sli->dl[slice_idx], &sli->dl[sli->n_dl], sizeof(sli->dl[sli->n_dl]));
-
- memset(&sli->dl[sli->n_dl], 0, sizeof(sli->dl[sli->n_dl]));
- /* all UEs that have been in the old slice are put into slice index 0 */
- //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_dl_slice_idx;
-
- //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) {
- // if (assoc_list[i] == slice_idx)
- // assoc_list[i] = 0;
- //}
+int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) {
+ if (!mac_is_present(mod_id)) return 0;
+ eNB_MAC_INST *mac = RC.mac[mod_id];
+ const int cc_id = 0;
+ pp_impl_param_t dl = mac->pre_processor_dl;
+ switch (algo) {
+ case PROTOCOL__FLEX_SLICE_ALGORITHM__Static:
+ mac->pre_processor_dl = static_dl_init(mod_id, cc_id);
+ break;
+ default:
+ mac->pre_processor_dl.algorithm = 0;
+ mac->pre_processor_dl.dl = dlsch_scheduler_pre_processor;
+ mac->pre_processor_dl.dl_algo.data = mac->pre_processor_dl.dl_algo.setup();
+ mac->pre_processor_dl.slices = NULL;
+ break;
+ }
+ if (dl.slices)
+ dl.destroy(&dl.slices);
+ if (dl.dl_algo.data)
+ dl.dl_algo.unset(&dl.dl_algo.data);
return 1;
}
-int flexran_get_num_dl_slices(mid_t mod_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.n_dl;
-}
-
-int flexran_get_intraslice_sharing_active(mid_t mod_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.intraslice_share_active;
-}
-void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active) {
- if (!mac_is_present(mod_id)) return;
+Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id) {
+ if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_SLICE_ALGORITHM__None;
- RC.mac[mod_id]->slice_info.intraslice_share_active = intraslice_active;
+ switch (RC.mac[mod_id]->pre_processor_ul.algorithm) {
+ case STATIC_SLICING:
+ return PROTOCOL__FLEX_SLICE_ALGORITHM__Static;
+ default:
+ return PROTOCOL__FLEX_SLICE_ALGORITHM__None;
+ }
}
-int flexran_get_interslice_sharing_active(mid_t mod_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.interslice_share_active;
-}
-void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active) {
- if (!mac_is_present(mod_id)) return;
+int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo) {
+ if (!mac_is_present(mod_id)) return 0;
+ eNB_MAC_INST *mac = RC.mac[mod_id];
+ const int cc_id = 0;
- RC.mac[mod_id]->slice_info.interslice_share_active = interslice_active;
+ pp_impl_param_t ul = mac->pre_processor_ul;
+ switch (algo) {
+ case PROTOCOL__FLEX_SLICE_ALGORITHM__Static:
+ mac->pre_processor_ul = static_ul_init(mod_id, cc_id);
+ break;
+ default:
+ mac->pre_processor_ul.algorithm = 0;
+ mac->pre_processor_ul.ul = ulsch_scheduler_pre_processor;
+ mac->pre_processor_ul.ul_algo.data = mac->pre_processor_ul.ul_algo.setup();
+ mac->pre_processor_ul.slices = NULL;
+ break;
+ }
+ if (ul.slices)
+ ul.destroy(&ul.slices);
+ if (ul.ul_algo.data)
+ ul.ul_algo.unset(&ul.ul_algo.data);
+ return 1;
}
-slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx) {
+int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id) {
if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].id;
-}
-void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].id = slice_id;
+ slice_info_t *slices = RC.mac[mod_id]->pre_processor_dl.slices;
+ if (!slices) return -1;
+ const int idx = slices->UE_assoc_slice[ue_id];
+ return slices->s[idx]->id;
}
-int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].pct * 100.0f;
-}
-void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage) {
+void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) {
if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].pct = percentage / 100.0f;
+ int idx = flexran_find_dl_slice(mod_id, slice_id);
+ if (idx < 0) return;
+ pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl;
+ dl->move_UE(dl->slices, ue_id, idx);
}
-int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx) {
+int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id) {
if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].isol;
-}
-void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].isol = is_isolated;
+ slice_info_t *slices = RC.mac[mod_id]->pre_processor_ul.slices;
+ if (!slices) return -1;
+ const int idx = slices->UE_assoc_slice[ue_id];
+ return slices->s[idx]->id;
}
-int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].prio;
-}
-void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority) {
+void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id) {
if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].prio = priority;
+ int idx = flexran_find_ul_slice(mod_id, slice_id);
+ if (idx < 0) return;
+ pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul;
+ ul->move_UE(ul->slices, ue_id, idx);
}
-int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low;
+int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) {
+ if (!mac_is_present(mod_id)) return 0;
+ void *params = NULL;
+ switch (s->params_case) {
+ case PROTOCOL__FLEX_SLICE__PARAMS_STATIC:
+ params = malloc(sizeof(static_slice_param_t));
+ if (!params) return 0;
+ ((static_slice_param_t *)params)->posLow = s->static_->poslow;
+ ((static_slice_param_t *)params)->posHigh = s->static_->poshigh;
+ break;
+ default:
+ break;
+ }
+ pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl;
+ char *l = s->label ? strdup(s->label) : NULL;
+ void *algo = &dl->dl_algo; // default scheduler
+ if (s->scheduler) {
+ algo = dlsym(NULL, s->scheduler);
+ if (!algo) {
+ free(params);
+ LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler);
+ return -15;
+ }
+ }
+ return dl->addmod_slice(dl->slices, s->id, l, algo, params);
}
-void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow) {
- if (!mac_is_present(mod_id)) return;
- RC.mac[mod_id]->slice_info.dl[slice_idx].pos_low = poslow;
+int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s) {
+ if (!mac_is_present(mod_id)) return 0;
+ const int idx = flexran_find_dl_slice(mod_id, s->id);
+ if (idx < 0) return 0;
+ pp_impl_param_t *dl = &RC.mac[mod_id]->pre_processor_dl;
+ return dl->remove_slice(dl->slices, idx);
}
-int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx) {
+int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id) {
if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high;
-}
-void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].pos_high = poshigh;
+ slice_info_t *si = RC.mac[mod_id]->pre_processor_dl.slices;
+ for (int i = 0; i < si->num; ++i)
+ if (si->s[i]->id == slice_id)
+ return i;
+ return -1;
}
-int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs;
-}
-void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) {
+void flexran_get_dl_slice(mid_t mod_id,
+ int slice_idx,
+ Protocol__FlexSlice *slice,
+ Protocol__FlexSliceAlgorithm algo) {
if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].maxmcs = maxmcs;
-}
-
-int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list) {
- if (!mac_is_present(mod_id)) return -1;
-
- if (!(*sorting_list)) {
- *sorting_list = calloc(CR_NUM, sizeof(Protocol__FlexDlSorting));
-
- if (!(*sorting_list)) return -1;
- }
-
- uint32_t policy = RC.mac[mod_id]->slice_info.dl[slice_idx].sorting;
-
- for (int i = 0; i < CR_NUM; i++) {
- switch (policy >> 4 * (CR_NUM - 1 - i) & 0xF) {
- case CR_ROUND:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND;
- break;
-
- case CR_SRB12:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_SRB12;
- break;
-
- case CR_HOL:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_HOL;
- break;
-
- case CR_LC:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LC;
- break;
-
- case CR_CQI:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_CQI;
- break;
-
- case CR_LCP:
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_LCP;
- break;
-
- default:
- /* this should not happen, but a "default" */
- (*sorting_list)[i] = PROTOCOL__FLEX_DL_SORTING__CR_ROUND;
- break;
- }
+ slice_t *s_ = RC.mac[mod_id]->pre_processor_dl.slices->s[slice_idx];
+ slice->has_id = 1;
+ slice->id = s_->id;
+ slice->label = s_->label;
+ slice->scheduler = s_->dl_algo.name;
+ slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET;
+ switch (algo) {
+ case PROTOCOL__FLEX_SLICE_ALGORITHM__Static:
+ slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic));
+ if (!slice->static_) return;
+ protocol__flex_slice_static__init(slice->static_);
+ slice->static_->has_poslow = 1;
+ slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow;
+ slice->static_->has_poshigh = 1;
+ slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh;
+ slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC;
+ break;
+ default:
+ break;
}
-
- return CR_NUM;
}
-void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n) {
- if (!mac_is_present(mod_id)) return;
-
- uint32_t policy = 0;
- for (int i = 0; i < n && i < CR_NUM; i++) {
- switch (sorting_list[i]) {
- case PROTOCOL__FLEX_DL_SORTING__CR_ROUND:
- policy = policy << 4 | CR_ROUND;
- break;
-
- case PROTOCOL__FLEX_DL_SORTING__CR_SRB12:
- policy = policy << 4 | CR_SRB12;
- break;
-
- case PROTOCOL__FLEX_DL_SORTING__CR_HOL:
- policy = policy << 4 | CR_HOL;
- break;
-
- case PROTOCOL__FLEX_DL_SORTING__CR_LC:
- policy = policy << 4 | CR_LC;
- break;
-
- case PROTOCOL__FLEX_DL_SORTING__CR_CQI:
- policy = policy << 4 | CR_CQI;
- break;
-
- case PROTOCOL__FLEX_DL_SORTING__CR_LCP:
- policy = policy << 4 | CR_LCP;
- break;
-
- default: /* suppresses warnings */
- policy = policy << 4 | CR_ROUND;
- break;
- }
- }
-
- /* fill up with 0 == CR_ROUND */
- if (CR_NUM > n) policy = policy << 4 * (CR_NUM - n);
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].sorting = policy;
+int flexran_get_num_dl_slices(mid_t mod_id) {
+ if (!mac_is_present(mod_id)) return 0;
+ if (!RC.mac[mod_id]->pre_processor_dl.slices) return 0;
+ return RC.mac[mod_id]->pre_processor_dl.slices->num;
}
-Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR;
-
- switch (RC.mac[mod_id]->slice_info.dl[slice_idx].accounting) {
- case POL_FAIR:
- return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR;
-
- case POL_GREEDY:
- return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY;
-
+int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) {
+ if (!mac_is_present(mod_id)) return -1;
+ void *params = NULL;
+ switch (s->params_case) {
+ case PROTOCOL__FLEX_SLICE__PARAMS_STATIC:
+ params = malloc(sizeof(static_slice_param_t));
+ if (!params) return 0;
+ ((static_slice_param_t *)params)->posLow = s->static_->poslow;
+ ((static_slice_param_t *)params)->posHigh = s->static_->poshigh;
+ break;
default:
- return PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR;
+ break;
}
-}
-void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting) {
- if (!mac_is_present(mod_id)) return;
-
- switch (accounting) {
- case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_FAIR:
- RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR;
- return;
-
- case PROTOCOL__FLEX_DL_ACCOUNTING_POLICY__POL_GREEDY:
- RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_GREEDY;
- return;
-
- default:
- RC.mac[mod_id]->slice_info.dl[slice_idx].accounting = POL_FAIR;
- return;
+ pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul;
+ char *l = s->label ? strdup(s->label) : NULL;
+ void *algo = &ul->ul_algo; // default scheduler
+ if (s->scheduler) {
+ algo = dlsym(NULL, s->scheduler);
+ if (!algo) {
+ free(params);
+ LOG_E(FLEXRAN_AGENT, "cannot locate scheduler '%s'\n", s->scheduler);
+ return -15;
+ }
}
+ return ul->addmod_slice(ul->slices, s->id, l, algo, params);
}
-char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return NULL;
-
- return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name;
-}
-int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name) {
+int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s) {
if (!mac_is_present(mod_id)) return 0;
-
- if (RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name)
- free(RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name);
-
- RC.mac[mod_id]->slice_info.dl[slice_idx].sched_name = strdup(name);
- RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb = dlsym(NULL, name);
- return RC.mac[mod_id]->slice_info.dl[slice_idx].sched_cb != NULL;
-}
-
-int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- int newidx = RC.mac[mod_id]->slice_info.n_ul;
-
- if (newidx >= MAX_NUM_SLICES) return -1;
-
- ++RC.mac[mod_id]->slice_info.n_ul;
- flexran_set_ul_slice_id(mod_id, newidx, slice_id);
- return newidx;
+ const int idx = flexran_find_ul_slice(mod_id, s->id);
+ if (idx < 0) return 0;
+ pp_impl_param_t *ul = &RC.mac[mod_id]->pre_processor_ul;
+ return ul->remove_slice(ul->slices, idx);
}
int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id) {
if (!mac_is_present(mod_id)) return -1;
-
- slice_info_t *sli = &RC.mac[mod_id]->slice_info;
- int n = sli->n_ul;
-
- for (int i = 0; i < n; i++) {
- if (sli->ul[i].id == slice_id) return i;
- }
-
+ slice_info_t *si = RC.mac[mod_id]->pre_processor_ul.slices;
+ for (int i = 0; i < si->num; ++i)
+ if (si->s[i]->id == slice_id)
+ return i;
return -1;
}
-int flexran_remove_ul_slice(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- slice_info_t *sli = &RC.mac[mod_id]->slice_info;
-
- if (sli->n_ul <= 1) return -1;
-
- if (sli->ul[slice_idx].sched_name) free(sli->ul[slice_idx].sched_name);
-
- --sli->n_ul;
-
- /* move last element to the position of the removed one */
- if (slice_idx != sli->n_ul)
- memcpy(&sli->ul[slice_idx], &sli->ul[sli->n_ul], sizeof(sli->ul[sli->n_ul]));
-
- memset(&sli->ul[sli->n_ul], 0, sizeof(sli->ul[sli->n_ul]));
- /* all UEs that have been in the old slice are put into slice index 0 */
- //int *assoc_list = RC.mac[mod_id]->UE_info.assoc_ul_slice_idx;
-
- //for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i) {
- // if (assoc_list[i] == slice_idx)
- // assoc_list[i] = 0;
- //}
-
- return sli->n_ul;
-}
-
-int flexran_get_num_ul_slices(mid_t mod_id) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.n_ul;
-}
-
-int flexran_ul_slice_exists(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return slice_idx >= 0 && slice_idx < RC.mac[mod_id]->slice_info.n_ul;
-}
-
-slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.ul[slice_idx].id;
-}
-void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.ul[slice_idx].id = slice_id;
-}
-
-int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.ul[slice_idx].pct * 100.0f;
-}
-void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage) {
+void flexran_get_ul_slice(mid_t mod_id,
+ int slice_idx,
+ Protocol__FlexSlice *slice,
+ Protocol__FlexSliceAlgorithm algo) {
if (!mac_is_present(mod_id)) return;
+ slice_t *s_ = RC.mac[mod_id]->pre_processor_ul.slices->s[slice_idx];
+ slice->has_id = 1;
+ slice->id = s_->id;
+ slice->label = s_->label;
+ slice->scheduler = s_->ul_algo.name;
+ slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS__NOT_SET;
+ switch (algo) {
+ case PROTOCOL__FLEX_SLICE_ALGORITHM__Static:
+ slice->static_ = malloc(sizeof(Protocol__FlexSliceStatic));
+ if (!slice->static_) return;
+ protocol__flex_slice_static__init(slice->static_);
+ slice->static_->has_poslow = 1;
+ slice->static_->poslow = ((static_slice_param_t *)s_->algo_data)->posLow;
+ slice->static_->has_poshigh = 1;
+ slice->static_->poshigh = ((static_slice_param_t *)s_->algo_data)->posHigh;
+ slice->params_case = PROTOCOL__FLEX_SLICE__PARAMS_STATIC;
+ break;
+ default:
+ break;
+ }
- RC.mac[mod_id]->slice_info.ul[slice_idx].pct = percentage / 100.0f;
}
-int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx) {
- if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb;
+int flexran_get_num_ul_slices(mid_t mod_id) {
+ if (!mac_is_present(mod_id)) return 0;
+ if (!RC.mac[mod_id]->pre_processor_ul.slices) return 0;
+ return RC.mac[mod_id]->pre_processor_ul.slices->num;
}
-void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.ul[slice_idx].first_rb = first_rb;
+char *flexran_get_dl_scheduler_name(mid_t mod_id) {
+ if (!mac_is_present(mod_id)) return NULL;
+ return RC.mac[mod_id]->pre_processor_dl.dl_algo.name;
}
-int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx) {
+int flexran_set_dl_scheduler(mid_t mod_id, char *sched) {
if (!mac_is_present(mod_id)) return -1;
-
- return RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs;
-}
-void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs) {
- if (!mac_is_present(mod_id)) return;
-
- RC.mac[mod_id]->slice_info.ul[slice_idx].maxmcs = maxmcs;
+ void *d = dlsym(NULL, sched);
+ if (!d) return -2;
+ pp_impl_param_t *dl_pp = &RC.mac[mod_id]->pre_processor_dl;
+ dl_pp->dl_algo.unset(&dl_pp->dl_algo.data);
+ dl_pp->dl_algo = *(default_sched_dl_algo_t *) d;
+ dl_pp->dl_algo.data = dl_pp->dl_algo.setup();
+ return 0;
}
-char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx) {
+char *flexran_get_ul_scheduler_name(mid_t mod_id) {
if (!mac_is_present(mod_id)) return NULL;
-
- return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name;
+ return RC.mac[mod_id]->pre_processor_ul.ul_algo.name;
}
-int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name) {
- if (!mac_is_present(mod_id)) return 0;
- if (RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name)
- free(RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name);
-
- RC.mac[mod_id]->slice_info.ul[slice_idx].sched_name = strdup(name);
- RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb = dlsym(NULL, name);
- return RC.mac[mod_id]->slice_info.ul[slice_idx].sched_cb != NULL;
+int flexran_set_ul_scheduler(mid_t mod_id, char *sched) {
+ if (!mac_is_present(mod_id)) return -1;
+ void *d = dlsym(NULL, sched);
+ if (!d) return -2;
+ pp_impl_param_t *ul_pp = &RC.mac[mod_id]->pre_processor_ul;
+ ul_pp->ul_algo.unset(&ul_pp->ul_algo.data);
+ ul_pp->ul_algo = *(default_sched_ul_algo_t *) d;
+ ul_pp->ul_algo.data = ul_pp->ul_algo.setup();
+ return 0;
}
/************************** S1AP **************************/
@@ -3634,6 +3457,168 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM
return 0;
}
+int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) {
+ s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id);
+ if (!s1ap) return -1;
+ if (!rrc_is_present(mod_id)) return -2;
+
+ /* Reconstruct S1AP_REGISTER_ENB_REQ */
+ MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, S1AP_REGISTER_ENB_REQ);
+ RCconfig_S1(m, mod_id);
+
+ const int CC_id = 0;
+ eNB_RRC_INST *rrc = RC.rrc[CC_id];
+ RrcConfigurationReq *conf = &rrc->configuration;
+ S1AP_REGISTER_ENB_REQ(m).num_plmn = conf->num_plmn;
+ for (int i = 0; i < conf->num_plmn; ++i) {
+ S1AP_REGISTER_ENB_REQ(m).mcc[i] = conf->mcc[i];
+ S1AP_REGISTER_ENB_REQ(m).mnc[i] = conf->mnc[i];
+ S1AP_REGISTER_ENB_REQ(m).mnc_digit_length[i] = conf->mnc_digit_length[i];
+ }
+
+ /* reconstruct MME list, it might have been updated since initial
+ * configuration */
+ S1AP_REGISTER_ENB_REQ(m).nb_mme = 0;
+ struct s1ap_eNB_mme_data_s *mme = NULL;
+ RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) {
+ const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme;
+ S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = mme->mme_s1_ip.ipv4;
+ strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme->mme_s1_ip.ipv4_address);
+ S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = mme->mme_s1_ip.ipv6;
+ strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6_address, mme->mme_s1_ip.ipv6_address);
+ S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = mme->broadcast_plmn_num;
+ for (int i = 0; i < mme->broadcast_plmn_num; ++i)
+ S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = mme->broadcast_plmn_index[i];
+ S1AP_REGISTER_ENB_REQ(m).nb_mme += 1;
+ }
+
+ if (S1AP_REGISTER_ENB_REQ(m).nb_mme + n_mme > S1AP_MAX_NB_MME_IP_ADDRESS)
+ return -1;
+
+ for (int i = 0; i < n_mme; ++i) {
+ const int n = S1AP_REGISTER_ENB_REQ(m).nb_mme;
+ strcpy(S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4_address, mme_ipv4[0]);
+ S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv4 = 1;
+ S1AP_REGISTER_ENB_REQ(m).mme_ip_address[n].ipv6 = 0;
+ S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_num[n] = S1AP_REGISTER_ENB_REQ(m).num_plmn;
+ for (int i = 0; i < S1AP_REGISTER_ENB_REQ(m).num_plmn; ++i)
+ S1AP_REGISTER_ENB_REQ(m).broadcast_plmn_index[n][i] = i;
+ S1AP_REGISTER_ENB_REQ(m).nb_mme += 1;
+ }
+
+ itti_send_msg_to_task (TASK_S1AP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m);
+
+ return 0;
+}
+
+int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4) {
+ s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id);
+ if (!s1ap) return -1;
+ struct s1ap_eNB_mme_data_s *mme = NULL;
+ RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) {
+ if (mme->mme_s1_ip.ipv4
+ && strncmp(mme->mme_s1_ip.ipv4_address, mme_ipv4[0], 16) == 0)
+ break;
+ }
+ if (!mme)
+ return -2;
+
+ MessageDef *m = itti_alloc_new_message(TASK_FLEXRAN_AGENT, SCTP_CLOSE_ASSOCIATION);
+ SCTP_CLOSE_ASSOCIATION(m).assoc_id = mme->assoc_id;
+ itti_send_msg_to_task (TASK_SCTP, ENB_MODULE_ID_TO_INSTANCE(mod_id), m);
+
+ switch (mme->state) {
+ case S1AP_ENB_STATE_WAITING:
+ s1ap->s1ap_mme_nb -= 1;
+ if (s1ap->s1ap_mme_pending_nb > 0)
+ s1ap->s1ap_mme_pending_nb -= 1;
+ break;
+ case S1AP_ENB_STATE_CONNECTED:
+ case S1AP_ENB_OVERLOAD: /* I am not sure the decrements are right here */
+ s1ap->s1ap_mme_nb -= 1;
+ s1ap->s1ap_mme_associated_nb -= 1;
+ break;
+ case S1AP_ENB_STATE_DISCONNECTED:
+ default:
+ break;
+ }
+ RB_REMOVE(s1ap_mme_map, &s1ap->s1ap_mme_head, mme);
+
+ return 0;
+}
+
+int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id) {
+ if (!rrc_is_present(mod_id))
+ return -1;
+ s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id);
+ if (!s1ap)
+ return -2;
+
+ eNB_RRC_INST *rrc = RC.rrc[CC_id];
+ RrcConfigurationReq *conf = &rrc->configuration;
+
+ uint8_t num_plmn_old = conf->num_plmn;
+ uint16_t mcc[PLMN_LIST_MAX_SIZE];
+ uint16_t mnc[PLMN_LIST_MAX_SIZE];
+ uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE];
+ for (int i = 0; i < num_plmn_old; ++i) {
+ mcc[i] = conf->mcc[i];
+ mnc[i] = conf->mnc[i];
+ mnc_digit_length[i] = conf->mnc_digit_length[i];
+ }
+
+ conf->num_plmn = (uint8_t) n_plmn;
+ for (int i = 0; i < conf->num_plmn; ++i) {
+ conf->mcc[i] = plmn_id[i]->mcc;
+ conf->mnc[i] = plmn_id[i]->mnc;
+ conf->mnc_digit_length[i] = plmn_id[i]->mnc_length;
+ }
+
+ rrc_eNB_carrier_data_t *carrier = &rrc->carrier[CC_id];
+ extern uint8_t do_SIB1(rrc_eNB_carrier_data_t *carrier,
+ int Mod_id,
+ int CC_id,
+ BOOLEAN_t brOption,
+ RrcConfigurationReq *configuration);
+ carrier->sizeof_SIB1 = do_SIB1(carrier, mod_id, CC_id, FALSE, conf);
+ if (carrier->sizeof_SIB1 < 0)
+ return -1337; /* SIB1 encoding failed, hell will probably break loose */
+
+ s1ap->num_plmn = (uint8_t) n_plmn;
+ for (int i = 0; i < conf->num_plmn; ++i) {
+ s1ap->mcc[i] = plmn_id[i]->mcc;
+ s1ap->mnc[i] = plmn_id[i]->mnc;
+ s1ap->mnc_digit_length[i] = plmn_id[i]->mnc_length;
+ }
+
+ int bpn_failed = 0;
+ struct s1ap_eNB_mme_data_s *mme = NULL;
+ RB_FOREACH(mme, s1ap_mme_map, &s1ap->s1ap_mme_head) {
+ for (int i = 0; i < mme->broadcast_plmn_num; ++i) {
+ /* search the new index and update. If we don't find, we count this using
+ * bpn_failed to now how many broadcast_plmns could not be updated */
+ int idx = mme->broadcast_plmn_index[i];
+ int omcc = mcc[idx];
+ int omnc = mnc[idx];
+ int omncl = mnc_digit_length[idx];
+ int j = 0;
+ for (j = 0; j < s1ap->num_plmn; ++j) {
+ if (s1ap->mcc[j] == omcc
+ && s1ap->mnc[j] == omnc
+ && s1ap->mnc_digit_length[j] == omncl) {
+ mme->broadcast_plmn_index[i] = j;
+ break;
+ }
+ }
+ if (j == s1ap->num_plmn) /* could not find the old PLMN in the new ones */
+ bpn_failed++;
+ }
+ }
+ if (bpn_failed > 0)
+ return -10000 - bpn_failed;
+ return 0;
+}
+
int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf){
if (!rrc_is_present(mod_id)) return -1;
s1ap_eNB_instance_t *s1ap = s1ap_eNB_get_instance(mod_id);
@@ -3644,7 +3629,7 @@ int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_con
RB_FOREACH(ue, s1ap_ue_map, &s1ap->s1ap_ue_head){
if (ue->eNB_ue_s1ap_id == enb_ue_s1ap_id) break;
}
- if (ue == NULL) return -1;
+ if (!ue) return 0; // UE does not exist: it might be connected but CN did not answer
if (ue->mme_ref->mme_s1_ip.ipv4)
ue_conf->mme_s1_ip = (char*) &ue->mme_ref->mme_s1_ip.ipv4_address[0];
diff --git a/openair2/ENB_APP/flexran_agent_ran_api.h b/openair2/ENB_APP/flexran_agent_ran_api.h
index ce328838529508ba3e65153e83171ab2d0a7c978..2d8a86f7d01de163f08c524ae80d2cbede17b81b 100644
--- a/openair2/ENB_APP/flexran_agent_ran_api.h
+++ b/openair2/ENB_APP/flexran_agent_ran_api.h
@@ -656,156 +656,66 @@ int flexran_agent_rrc_gtp_get_teid_sgw(mid_t mod_id, rnti_t rnti, int index);
uint32_t flexran_get_rrc_enb_ue_s1ap_id(mid_t mod_id, rnti_t rnti);
/************************** Slice configuration **************************/
+/* Get the currently active DL slicing algorithm */
+Protocol__FlexSliceAlgorithm flexran_get_dl_slice_algo(mid_t mod_id);
+/* Set the active DL slicing algorithm */
+int flexran_set_dl_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo);
+
+/* Get the currently active UL slicing algorithm */
+Protocol__FlexSliceAlgorithm flexran_get_ul_slice_algo(mid_t mod_id);
+/* Set the active UL slicing algorithm */
+int flexran_set_ul_slice_algo(mid_t mod_id, Protocol__FlexSliceAlgorithm algo);
/* Get the DL slice ID for a UE */
int flexran_get_ue_dl_slice_id(mid_t mod_id, mid_t ue_id);
-
-/* Set the DL slice index(!) for a UE */
-void flexran_set_ue_dl_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx);
+/* Set the DL slice for a UE */
+void flexran_set_ue_dl_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id);
/* Get the UL slice ID for a UE */
int flexran_get_ue_ul_slice_id(mid_t mod_id, mid_t ue_id);
+/* Set the UL slice for a UE */
+void flexran_set_ue_ul_slice_id(mid_t mod_id, mid_t ue_id, slice_id_t slice_id);
-/* Set the UL slice index(!) for a UE */
-void flexran_set_ue_ul_slice_idx(mid_t mod_id, mid_t ue_id, int slice_idx);
-
-/* Whether intraslice sharing is active, return boolean */
-int flexran_get_intraslice_sharing_active(mid_t mod_id);
-/* Set whether intraslice sharing is active */
-void flexran_set_intraslice_sharing_active(mid_t mod_id, int intraslice_active);
-
-/* Whether intraslice sharing is active, return boolean */
-int flexran_get_interslice_sharing_active(mid_t mod_id);
-/* Set whether intraslice sharing is active */
-void flexran_set_interslice_sharing_active(mid_t mod_id, int interslice_active);
+/* Create slice in DL, returns the new slice index */
+int flexran_create_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s);
+/* Remove slice in DL, returns new number of slices or -1 on error */
+int flexran_remove_dl_slice(mid_t mod_id, const Protocol__FlexSlice *s);
+/* Finds slice in DL with given slice_id and returns slice index */
+int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id);
+/* Return the parameters of slice at index slice_idx */
+void flexran_get_dl_slice(mid_t mod_id,
+ int slice_idx,
+ Protocol__FlexSlice *slice,
+ Protocol__FlexSliceAlgorithm algo);
/* Get the number of slices in DL */
int flexran_get_num_dl_slices(mid_t mod_id);
-/* Query slice existence in DL. Return is boolean value */
-int flexran_dl_slice_exists(mid_t mod_id, int slice_idx);
+/* Create slice in UL, returns the new slice index */
+int flexran_create_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s);
+/* Remove slice in UL */
+int flexran_remove_ul_slice(mid_t mod_id, const Protocol__FlexSlice *s);
-/* Create slice in DL, returns the new slice index */
-int flexran_create_dl_slice(mid_t mod_id, slice_id_t slice_id);
/* Finds slice in DL with given slice_id and returns slice index */
-int flexran_find_dl_slice(mid_t mod_id, slice_id_t slice_id);
-/* Remove slice in DL, returns new number of slices or -1 on error */
-int flexran_remove_dl_slice(mid_t mod_id, int slice_idx);
-
-/* Get the ID of a slice in DL */
-slice_id_t flexran_get_dl_slice_id(mid_t mod_id, int slice_idx);
-/* Set the ID of a slice in DL */
-void flexran_set_dl_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id);
-
-/* Get the RB share a slice in DL, value 0-100 */
-int flexran_get_dl_slice_percentage(mid_t mod_id, int slice_idx);
-/* Set the RB share a slice in DL, value 0-100 */
-void flexran_set_dl_slice_percentage(mid_t mod_id, int slice_idx, int percentage);
-
-/* Whether a slice in DL is isolated */
-int flexran_get_dl_slice_isolation(mid_t mod_id, int slice_idx);
-/* Set whether a slice in DL is isolated */
-void flexran_set_dl_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated);
-
-/* Get the priority of a slice in DL */
-int flexran_get_dl_slice_priority(mid_t mod_id, int slice_idx);
-/* Get the priority of a slice in DL */
-void flexran_set_dl_slice_priority(mid_t mod_id, int slice_idx, int priority);
-
-/* Get the lower end of the frequency range for the slice positioning in DL */
-int flexran_get_dl_slice_position_low(mid_t mod_id, int slice_idx);
-/* Set the lower end of the frequency range for the slice positioning in DL */
-void flexran_set_dl_slice_position_low(mid_t mod_id, int slice_idx, int poslow);
-
-/* Get the higher end of the frequency range for the slice positioning in DL */
-int flexran_get_dl_slice_position_high(mid_t mod_id, int slice_idx);
-/* Set the higher end of the frequency range for the slice positioning in DL */
-void flexran_set_dl_slice_position_high(mid_t mod_id, int slice_idx, int poshigh);
-
-/* Get the maximum MCS for slice in DL */
-int flexran_get_dl_slice_maxmcs(mid_t mod_id, int slice_idx);
-/* Set the maximum MCS for slice in DL */
-void flexran_set_dl_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs);
-
-/* Get the sorting order of a slice in DL, return value is number of elements
- * in sorting_list */
-int flexran_get_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting **sorting_list);
-/* Set the sorting order of a slice in DL */
-void flexran_set_dl_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexDlSorting *sorting_list, int n);
-
-/* Get the accounting policy for a slice in DL */
-Protocol__FlexDlAccountingPolicy flexran_get_dl_slice_accounting_policy(mid_t mod_id, int slice_idx);
-/* Set the accounting policy for a slice in DL */
-void flexran_set_dl_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__FlexDlAccountingPolicy accounting);
-
-/* Get the scheduler name for a slice in DL */
-char *flexran_get_dl_slice_scheduler(mid_t mod_id, int slice_idx);
-/* Set the scheduler name for a slice in DL */
-int flexran_set_dl_slice_scheduler(mid_t mod_id, int slice_idx, char *name);
-
+int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id);
+/* Return the parameters of slice at index slice_idx */
+void flexran_get_ul_slice(mid_t mod_id,
+ int slice_idx,
+ Protocol__FlexSlice *slice,
+ Protocol__FlexSliceAlgorithm algo);
/* Get the number of slices in UL */
int flexran_get_num_ul_slices(mid_t mod_id);
-/* Query slice existence in UL. Return is boolean value */
-int flexran_ul_slice_exists(mid_t mod_id, int slice_idx);
+/* Get the name of/Set the DL scheduling algorithm. If slicing is active, this
+ * corresponds to the default algorithm for slices, otherwise the currently
+ * used one. */
+char *flexran_get_dl_scheduler_name(mid_t mod_id);
+int flexran_set_dl_scheduler(mid_t mod_id, char *sched);
-/* Create slice in UL, returns the new slice index */
-int flexran_create_ul_slice(mid_t mod_id, slice_id_t slice_id);
-/* Finds slice in UL with given slice_id and returns slice index */
-int flexran_find_ul_slice(mid_t mod_id, slice_id_t slice_id);
-/* Remove slice in UL */
-int flexran_remove_ul_slice(mid_t mod_id, int slice_idx);
-
-/* Get the ID of a slice in UL */
-slice_id_t flexran_get_ul_slice_id(mid_t mod_id, int slice_idx);
-/* Set the ID of a slice in UL */
-void flexran_set_ul_slice_id(mid_t mod_id, int slice_idx, slice_id_t slice_id);
-
-/* Get the RB share a slice in UL, value 0-100 */
-int flexran_get_ul_slice_percentage(mid_t mod_id, int slice_idx);
-/* Set the RB share a slice in UL, value 0-100 */
-void flexran_set_ul_slice_percentage(mid_t mod_id, int slice_idx, int percentage);
-
-/* TODO Whether a slice in UL is isolated */
-/*int flexran_get_ul_slice_isolation(mid_t mod_id, int slice_idx);*/
-/* TODO Set whether a slice in UL is isolated */
-/*void flexran_set_ul_slice_isolation(mid_t mod_id, int slice_idx, int is_isolated);*/
-
-/* TODO Get the priority of a slice in UL */
-/*int flexran_get_ul_slice_priority(mid_t mod_id, int slice_idx);*/
-/* TODO Set the priority of a slice in UL */
-/*void flexran_set_ul_slice_priority(mid_t mod_id, int slice_idx, int priority);*/
-
-/* Get the first RB for allocation in a slice in UL */
-int flexran_get_ul_slice_first_rb(mid_t mod_id, int slice_idx);
-/* Set the first RB for allocation in a slice in UL */
-void flexran_set_ul_slice_first_rb(mid_t mod_id, int slice_idx, int first_rb);
-
-/* TODO Get the number of RB for the allocation in a slice in UL */
-/*int flexran_get_ul_slice_length_rb(mid_t mod_id, int slice_idx);*/
-/* TODO Set the of number of RB for the allocation in a slice in UL */
-/*void flexran_set_ul_slice_length_rb(mid_t mod_id, int slice_idx, int poshigh);*/
-
-/* Get the maximum MCS for slice in UL */
-int flexran_get_ul_slice_maxmcs(mid_t mod_id, int slice_idx);
-/* Set the maximum MCS for slice in UL */
-void flexran_set_ul_slice_maxmcs(mid_t mod_id, int slice_idx, int maxmcs);
-
-/* TODO Get the sorting order of a slice in UL, return value is number of elements
- * in sorting_list */
-/*int flexran_get_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting **sorting_list);*/
-/* TODO Set the sorting order of a slice in UL */
-/*void flexran_set_ul_slice_sorting(mid_t mod_id, int slice_idx, Protocol__FlexUlSorting *sorting_list, int n);*/
-
-/* TODO Get the accounting policy for a slice in UL */
-/*Protocol__UlAccountingPolicy flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx);*/
-/* TODO Set the accounting policy for a slice in UL */
-/*void flexran_get_ul_slice_accounting_policy(mid_t mod_id, int slice_idx, Protocol__UlAccountingPolicy accountin);*/
-
-/* Get the scheduler name for a slice in UL */
-char *flexran_get_ul_slice_scheduler(mid_t mod_id, int slice_idx);
-/* Set the scheduler name for a slice in UL */
-int flexran_set_ul_slice_scheduler(mid_t mod_id, int slice_idx, char *name);
+/* Get the name of/Set the UL scheduler algorithm. Same applies as for the DL
+ * case */
+char *flexran_get_ul_scheduler_name(mid_t mod_id);
+int flexran_set_ul_scheduler(mid_t mod_id, char *sched);
/************************** S1AP **************************/
/* Get the number of MMEs to be connected */
@@ -832,6 +742,15 @@ int flexran_get_s1ap_mme_conf(mid_t mod_id, mid_t mme_index, Protocol__FlexS1apM
/* Get the S1AP UE conf */
int flexran_get_s1ap_ue(mid_t mod_id, rnti_t rnti, Protocol__FlexS1apUe * ue_conf);
+/* Add MMEs and re-issue S1AP Registration Request */
+int flexran_add_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4);
+
+/* Remove MMEs and and cut SCTP to MME */
+int flexran_remove_s1ap_mme(mid_t mod_id, size_t n_mme, char **mme_ipv4);
+
+/* Set a new PLMN configuration */
+int flexran_set_new_plmn_id(mid_t mod_id, int CC_id, size_t n_plmn, Protocol__FlexPlmn **plmn_id);
+
/********************* general information *****************/
/* get an ID for this BS (or part of a BS) */
uint64_t flexran_get_bs_id(mid_t mod_id);
diff --git a/openair2/F1AP/f1ap_cu_ue_context_management.c b/openair2/F1AP/f1ap_cu_ue_context_management.c
index a64f2d529b302b99338d2f6e6b9b2097d46443fe..789ce4c715b3dd5336e866786b5fd5c150ce4962 100644
--- a/openair2/F1AP/f1ap_cu_ue_context_management.c
+++ b/openair2/F1AP/f1ap_cu_ue_context_management.c
@@ -226,7 +226,7 @@ int CU_send_UE_CONTEXT_SETUP_REQUEST(instance_t instance,
ie->value.choice.ResourceCoordinationTransferContainer.buf = malloc(4);
ie->value.choice.ResourceCoordinationTransferContainer.size = 4;
- strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 3);
+ strncpy((char *)ie->value.choice.ResourceCoordinationTransferContainer.buf, "123", 4);
OCTET_STRING_fromBuf(&ie->value.choice.ResourceCoordinationTransferContainer, "asdsa1d32sa1d31asd31as",
diff --git a/openair2/F1AP/f1ap_du_rrc_message_transfer.c b/openair2/F1AP/f1ap_du_rrc_message_transfer.c
index fb9450728b40dada6301df9be74b61c1d3289886..695358881822d8bc4fcfec411d296e248ace62a9 100644
--- a/openair2/F1AP/f1ap_du_rrc_message_transfer.c
+++ b/openair2/F1AP/f1ap_du_rrc_message_transfer.c
@@ -306,7 +306,8 @@ int DU_handle_DL_RRC_MESSAGE_TRANSFER(instance_t instance,
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
break;
} // case
@@ -480,7 +481,8 @@ int DU_handle_DL_RRC_MESSAGE_TRANSFER(instance_t instance,
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
diff --git a/openair2/GNB_APP/L1_nr_paramdef.h b/openair2/GNB_APP/L1_nr_paramdef.h
index 889a50c814bab349536cfee5d33986f2411fe4b6..a5a808c2811ad21684cabbedb572ea03fc810518 100644
--- a/openair2/GNB_APP/L1_nr_paramdef.h
+++ b/openair2/GNB_APP/L1_nr_paramdef.h
@@ -30,6 +30,8 @@
* \warning
*/
+#ifndef __GNB_APP_L1_NR_PARAMDEF__H__
+#define __GNB_APP_L1_NR_PARAMDEF__H__
/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
@@ -71,3 +73,4 @@
#define L1_REMOTE_N_PORTD_IDX 8
/*----------------------------------------------------------------------------------------------------------------------------------------------------*/
+#endif
diff --git a/openair2/GNB_APP/MACRLC_nr_paramdef.h b/openair2/GNB_APP/MACRLC_nr_paramdef.h
index b55aeacdce706288df8c03e6584b6be24d88b3fd..308af2eeb916b760f5643f19c0e84b4874d5dc7d 100644
--- a/openair2/GNB_APP/MACRLC_nr_paramdef.h
+++ b/openair2/GNB_APP/MACRLC_nr_paramdef.h
@@ -31,6 +31,8 @@
*/
+#ifndef __GNB_APP_MACRLC_NR_PARAMDEF__H__
+#define __GNB_APP_MACRLC_NR_PARAMDEF__H__
/*----------------------------------------------------------------------------------------------------------------------------------------------------*/
@@ -96,3 +98,4 @@
#define MACRLC_LOCAL_S_PORTD_IDX 15
#define MACRLC_REMOTE_S_PORTD_IDX 16
/*---------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#endif
diff --git a/openair2/GNB_APP/RRC_nr_paramsvalues.h b/openair2/GNB_APP/RRC_nr_paramsvalues.h
index 82873f22b4bcdbf8ab68b3ca73e023c12b91a832..bc4c4cf9d945600a92e536aaefd19d3e3638a844 100644
--- a/openair2/GNB_APP/RRC_nr_paramsvalues.h
+++ b/openair2/GNB_APP/RRC_nr_paramsvalues.h
@@ -128,18 +128,19 @@
#define GNB_CONFIG_STRING_RARESPONSEWINDOW "ra_ResponseWindow"
#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSBPR "ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR"
#define GNB_CONFIG_STRING_SSBPERRACHOCCASIONANDCBPREAMBLESPERSSB "ssb_perRACH_OccasionAndCB_PreamblesPerSSB"
-#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer"
-#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB"
-#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR"
-#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex"
-#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing"
-#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig"
-#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList"
-#define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble"
-#define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant"
-#define GNB_CONFIG_STRING_PUCCHGROUPHOPPING "pucchGroupHopping"
-#define GNB_CONFIG_STRING_HOPPINGID "hoppingId"
-#define GNB_CONFIG_STRING_P0NOMINAL "p0_nominal"
+#define GNB_CONFIG_STRING_RACONTENTIONRESOLUTIONTIMER "ra_ContentionResolutionTimer"
+#define GNB_CONFIG_STRING_RSRPTHRESHOLDSSB "rsrp_ThresholdSSB"
+#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR "prach_RootSequenceIndex_PR"
+#define GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX "prach_RootSequenceIndex"
+#define GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING "msg1_SubcarrierSpacing"
+#define GNB_CONFIG_STRING_RESTRICTEDSETCONFIG "restrictedSetConfig"
+#define GNB_CONFIG_STRING_MSG3TRANSFPREC "msg3_transformPrecoder"
+#define GNB_CONFIG_STRING_PUSCHTIMEDOMAINALLOCATIONLIST "puschTimeDomainAllocationList"
+#define GNB_CONFIG_STRING_MSG3DELTAPREABMLE "msg3_DeltaPreamble"
+#define GNB_CONFIG_STRING_P0NOMINALWITHGRANT "p0_NominalWithGrant"
+#define GNB_CONFIG_STRING_PUCCHGROUPHOPPING "pucchGroupHopping"
+#define GNB_CONFIG_STRING_HOPPINGID "hoppingId"
+#define GNB_CONFIG_STRING_P0NOMINAL "p0_nominal"
#define GNB_CONFIG_STRING_INITIALULBWPK2_0 "initialULBWPk2_0"
#define GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0 "initialULBWPmappingType_0"
#define GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0 "initialULBWPstartSymbolAndLength_0"
@@ -246,7 +247,7 @@
{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:-1,TYPE_INT64,0/*17*/},\
{GNB_CONFIG_STRING_INITIALDLBWPK0_1,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->k0,defint64val:-1,TYPE_INT64,0/*18*/},\
{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*19*/},\
-{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \
+{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*20*/}, \
{GNB_CONFIG_STRING_INITIALDLBWPK0_2,NULL,0,i64ptr:scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->k0,defint64val:-1,TYPE_INT64,0/*21*/},\
{GNB_CONFIG_STRING_INITIALDLBWPMAPPINGTYPE_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA,TYPE_INT64,0/*22*/},\
{GNB_CONFIG_STRING_INITIALDLBWPSTARTSYMBOLANDLENGTH_2,NULL,0,i64ptr:&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[2]->startSymbolAndLength,defint64val:54,TYPE_INT64,0/*23*/},\
@@ -311,11 +312,12 @@
{GNB_CONFIG_STRING_RSRPTHRESHOLDSSB,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rsrp_ThresholdSSB,defint64val:19,TYPE_INT64,0/*82*/},\
{GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEXPR,NULL,0,uptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present,defuintval:NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139,TYPE_UINT,0/*83*/},\
{GNB_CONFIG_STRING_PRACHROOTSEQUENCEINDEX,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139,defint64val:0,TYPE_INT64,0/*84*/},\
-{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \
-{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*86*/},\
-{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*87*/},\
-{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*88*/},\
-{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*89*/}, \
+{GNB_CONFIG_STRING_RESTRICTEDSETCONFIG,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig,defintval:NR_RACH_ConfigCommon__restrictedSetConfig_unrestrictedSet,TYPE_INT64,0/*85*/}, \
+{GNB_CONFIG_STRING_MSG3TRANSFPREC,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder,defintval:1,TYPE_INT64,0/*86*/}, \
+{GNB_CONFIG_STRING_INITIALULBWPK2_0,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->k2,defint64val:-1,TYPE_INT64,0/*87*/},\
+{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,/*88*/},\
+{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_0,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[0]->startSymbolAndLength,defint64val:55,TYPE_INT64,0/*89*/},\
+{GNB_CONFIG_STRING_INITIALULBWPK2_1,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->k2,defint64val:-1,TYPE_INT64,0/*90*/}, \
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_1,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[1]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_2,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[2]->k2,defint64val:-1,TYPE_INT64,0},\
@@ -325,7 +327,7 @@
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_3,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[3]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_4,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->k2,defint64val:-1,TYPE_INT64,0},\
-{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*99*/}, \
+{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*100*/}, \
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_4,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[4]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_5,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->k2,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_5,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[5]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
@@ -335,7 +337,7 @@
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_6,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[6]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_7,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->k2,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
-{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*109*/}, \
+{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_7,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[7]->startSymbolAndLength,defint64val:53,TYPE_INT64,0/*110*/}, \
{GNB_CONFIG_STRING_INITIALULBWPK2_8,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->k2,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_8,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[8]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\
@@ -345,7 +347,7 @@
{GNB_CONFIG_STRING_INITIALULBWPK2_10,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->k2,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_10,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[10]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\
-{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*119*/}, \
+{GNB_CONFIG_STRING_INITIALULBWPK2_11,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->k2,defint64val:-1,TYPE_INT64,0/*120*/}, \
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_11,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[11]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_12,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[12]->k2,defint64val:-1,TYPE_INT64,0},\
@@ -355,7 +357,7 @@
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_13,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[13]->startSymbolAndLength,defint64val:53,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_14,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->k2,defint64val:-1,TYPE_INT64,0},\
-{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*129*/}, \
+{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->mappingType,defint64val:NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0 /*130*/}, \
{GNB_CONFIG_STRING_INITIALULBWPSTARTSYMBOLANDLENGTH_14,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[14]->startSymbolAndLength,defint64val:55,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPK2_15,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->k2,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_INITIALULBWPMAPPINGTYPE_15,NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[15]->mappingType,defint64val:NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB,TYPE_INT64,0},\
@@ -365,7 +367,7 @@
{GNB_CONFIG_STRING_PUCCHGROUPHOPPING, NULL,0,i64ptr:&scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->pucch_GroupHopping,defint64val:NR_PUCCH_ConfigCommon__pucch_GroupHopping_neither,TYPE_INT64,0},\
{GNB_CONFIG_STRING_HOPPINGID, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->hoppingId,defint64val:40,TYPE_INT64,0},\
{GNB_CONFIG_STRING_P0NOMINAL, NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal,defint64val:1,TYPE_INT64,0},\
-{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*139*/}, \
+{GNB_CONFIG_STRING_SSBPOSITIONSINBURSTPR,NULL,0,uptr:&scc->ssb_PositionsInBurst->present,defuintval:NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap,TYPE_UINT,0/*140*/}, \
{GNB_CONFIG_STRING_SSBPOSITIONSINBURST,NULL,0,u64ptr:&ssb_bitmap,defintval:0xff,TYPE_UINT64,0}, \
{GNB_CONFIG_STRING_REFERENCESUBCARRIERSPACING,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing,defint64val:NR_SubcarrierSpacing_kHz30,TYPE_INT64,0},\
{GNB_CONFIG_STRING_DLULTRANSMISSIONPERIODICITY,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity,defint64val:NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5,TYPE_INT64,0},\
@@ -379,7 +381,7 @@
{GNB_CONFIG_STRING_NROFUPLINKSLOTS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSlots,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_NROFUPLINKSYMBOLS2,NULL,0,i64ptr:&scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofUplinkSymbols,defint64val:-1,TYPE_INT64,0},\
{GNB_CONFIG_STRING_SSPBCHBLOCKPOWER,NULL,0,i64ptr:&scc->ss_PBCH_BlockPower,defint64val:20,TYPE_INT64,0}, \
-{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0/*86*/}}
+{GNB_CONFIG_STRING_MSG1SUBCARRIERSPACING,NULL,0,i64ptr:scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing,defintval:-1,TYPE_INT64,0}}
diff --git a/openair2/GNB_APP/gnb_app.c b/openair2/GNB_APP/gnb_app.c
index f11e302771d8542db5f1b3722e929025c308660c..9bdd70926241bc8d86765b40e213a45bcfe615b0 100644
--- a/openair2/GNB_APP/gnb_app.c
+++ b/openair2/GNB_APP/gnb_app.c
@@ -71,30 +71,30 @@ static void configure_nr_rrc(uint32_t gnb_id)
/*------------------------------------------------------------------------------*/
-/*
+
static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//, const Enb_properties_array_t *enb_properties)
{
uint32_t gnb_id;
- MessageDef *msg_p;
+ //MessageDef *msg_p;
uint32_t register_gnb_pending = 0;
for (gnb_id = gnb_id_start; (gnb_id < gnb_id_end) ; gnb_id++) {
{
- s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse
+ //s1ap_register_enb_req_t *s1ap_register_gNB; //Type Temporarily reuse
// note: there is an implicit relationship between the data structure and the message name
- msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse
+ /*msg_p = itti_alloc_new_message (TASK_GNB_APP, S1AP_REGISTER_ENB_REQ); //Message Temporarily reuse
- RCconfig_NR_S1(msg_p, gnb_id);
+ RCconfig_NR_S1(msg_p, gnb_id);*/
if (gnb_id == 0) RCconfig_nr_gtpu();
- s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse
- LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx);
+ /*s1ap_register_gNB = &S1AP_REGISTER_ENB_REQ(msg_p); //Message Temporarily reuse
+ LOG_I(GNB_APP,"default drx %d\n",s1ap_register_gNB->default_drx);*/
LOG_I(GNB_APP,"[gNB %d] gNB_app_register for instance %d\n", gnb_id, GNB_MODULE_ID_TO_INSTANCE(gnb_id));
- itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p);
+ //itti_send_msg_to_task (TASK_S1AP, GNB_MODULE_ID_TO_INSTANCE(gnb_id), msg_p);
register_gnb_pending++;
}
@@ -102,7 +102,7 @@ static uint32_t gNB_app_register(uint32_t gnb_id_start, uint32_t gnb_id_end)//,
return register_gnb_pending;
}
-*/
+
/*------------------------------------------------------------------------------*/
static uint32_t gNB_app_register_x2(uint32_t gnb_id_start, uint32_t gnb_id_end) {
@@ -131,7 +131,7 @@ void *gNB_app_task(void *args_p)
uint32_t gnb_nb = RC.nb_nr_inst;
uint32_t gnb_id_start = 0;
uint32_t gnb_id_end = gnb_id_start + gnb_nb;
- uint32_t x2_register_gnb_pending = 0;
+
uint32_t gnb_id;
MessageDef *msg_p = NULL;
const char *msg_name = NULL;
@@ -170,13 +170,13 @@ void *gNB_app_task(void *args_p)
if (is_x2ap_enabled() ) { //&& !NODE_IS_DU(RC.rrc[0]->node_type)
LOG_I(X2AP, "X2AP enabled \n");
- x2_register_gnb_pending = gNB_app_register_x2 (gnb_id_start, gnb_id_end);
+ __attribute__((unused)) uint32_t x2_register_gnb_pending = gNB_app_register_x2 (gnb_id_start, gnb_id_end);
}
if (EPC_MODE_ENABLED) {
/* Try to register each gNB */
//registered_gnb = 0;
- //register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p);
+ __attribute__((unused)) uint32_t register_gnb_pending = gNB_app_register (gnb_id_start, gnb_id_end);//, gnb_properties_p);
} else {
/* Start L2L1 task */
msg_p = itti_alloc_new_message(TASK_GNB_APP, INITIALIZE_MESSAGE);
diff --git a/openair2/GNB_APP/gnb_config.c b/openair2/GNB_APP/gnb_config.c
index 935551707261e1535d4dbc8acebb1a9b3fb046eb..61aa10e47b7310023712007af2677d5257cbf684 100644
--- a/openair2/GNB_APP/gnb_config.c
+++ b/openair2/GNB_APP/gnb_config.c
@@ -54,7 +54,8 @@
#include "common/config/config_userapi.h"
//#include "RRC_config_tools.h"
#include "gnb_paramdef.h"
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_gNB/mac_proto.h"
+
#include "NR_asn_constant.h"
#include "executables/thread-common.h"
#include "NR_SCS-SpecificCarrier.h"
@@ -254,10 +255,9 @@ void fix_scc(NR_ServingCellConfigCommon_t *scc,uint64_t ssbmap) {
scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA = NULL;
}
- // fix libconfig (asn1c uses long)
- scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.preambleReceivedTargetPower-=((long)1<<32);
- *scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->p0_NominalWithGrant-=((long)1<<32);
- *scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal-=((long)1<<32);
+ // default value for msg3 precoder is NULL (0 means enabled)
+ if (*scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder!=0)
+ scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder = NULL;
// fix DL and UL Allocation lists
@@ -714,10 +714,14 @@ int RCconfig_nr_gtpu(void ) {
if (address) {
MessageDef *message;
AssertFatal((message = itti_alloc_new_message(TASK_GNB_APP, GTPV1U_ENB_S1_REQ))!=NULL,"");
- IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" );
- LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up);
- GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U;
- itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id)
+ // IPV4_STR_ADDR_TO_INT_NWBO ( address, RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" );
+ // LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up);
+
+
+ IPV4_STR_ADDR_TO_INT_NWBO ( address, GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up, "BAD IP ADDRESS FORMAT FOR eNB S1_U !\n" );
+ LOG_I(GTPU,"Configuring GTPu address : %s -> %x\n",address,GTPV1U_ENB_S1_REQ(message).enb_ip_address_for_S1u_S12_S4_up);
+ GTPV1U_ENB_S1_REQ(message).enb_port_for_S1u_S12_S4_up = gnb_port_for_S1U;
+ itti_send_msg_to_task (TASK_GTPV1_U, 0, message); // data model is wrong: gtpu doesn't have enb_id (or module_id)
} else
LOG_E(GTPU,"invalid address for S1U\n");
@@ -978,8 +982,6 @@ void NRRCConfig(void) {
paramlist_def_t RUParamList = {CONFIG_STRING_RU_LIST,NULL,0};
paramdef_t GNBSParams[] = GNBSPARAMS_DESC;
- char aprefix[MAX_OPTNAME_SIZE*2 + 8];
-
/* get global parameters, defined outside any section in the config file */
LOG_I(GNB_APP, "Getting GNBSParams\n");
diff --git a/openair2/GNB_APP/gnb_paramdef.h b/openair2/GNB_APP/gnb_paramdef.h
index 2d9ecb8c8a5290ebb000889ba0c936a0d12240c9..84045fc622f0a38fb7f8d16f520fc694fab415ec 100644
--- a/openair2/GNB_APP/gnb_paramdef.h
+++ b/openair2/GNB_APP/gnb_paramdef.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __GNB_APP_GNB_PARAMDEF__H__
+#define __GNB_APP_GNB_PARAMDEF__H__
+
#include "common/config/config_paramdesc.h"
#include "RRC_nr_paramsvalues.h"
@@ -430,3 +433,4 @@ typedef struct ccparams_nr_x2 {
#define CONFIG_HLP_WORKER "coding and FEP worker thread WORKER_DISABLE or WORKER_ENABLE\n"
#define CONFIG_HLP_PARALLEL "PARALLEL_SINGLE_THREAD, PARALLEL_RU_L1_SPLIT, or PARALLEL_RU_L1_TRX_SPLIT(RU_L1_TRX_SPLIT by defult)\n"
/*-------------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#endif
diff --git a/openair2/LAYER2/MAC/config.c b/openair2/LAYER2/MAC/config.c
index 49949bd771b119447a1694755a1a80455644d7b3..781347abaaea42610de39f573ff1a4385af2d5d3 100644
--- a/openair2/LAYER2/MAC/config.c
+++ b/openair2/LAYER2/MAC/config.c
@@ -660,7 +660,7 @@ config_sib2_mbsfn_part( int Mod_idP,
if (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) {
phycfg.cfg->embms_mbsfn_config.fourframes_flag[i] = 0;
phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i] = mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]; // 6-bit subframe configuration
- LOG_I (MAC, "[CONFIG] MBSFN_SubframeConfig[%d] pattern is %d\n", i, phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]);
+ LOG_I (MAC, "[CONFIG] MBSFN_SubframeConfig[%d] oneFrame pattern is %d\n", i, phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]);
} else if (mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames) { // 24-bit subframe configuration
phycfg.cfg->embms_mbsfn_config.fourframes_flag[i] = 1;
phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i] =
@@ -668,7 +668,7 @@ config_sib2_mbsfn_part( int Mod_idP,
(mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[1]<<8)|
(mbsfn_SubframeConfigListP->list.array[i]->subframeAllocation.choice.oneFrame.buf[0]<<16);
- LOG_I(MAC, "[CONFIG] MBSFN_SubframeConfig[%d] pattern is %x\n", i,
+ LOG_I(MAC, "[CONFIG] MBSFN_SubframeConfig[%d] fourFrame pattern is %x\n", i,
phycfg.cfg->embms_mbsfn_config.mbsfn_subframeconfig[i]);
}
}
@@ -777,7 +777,8 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP,
LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo_fembms,
struct LTE_NonMBSFN_SubframeConfig_r14 *nonMBSFN_SubframeConfig,
LTE_SystemInformationBlockType1_MBMS_r14_t *sib1_mbms_r14_fembms,
- LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms
+ LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms,
+ LTE_MBSFNAreaConfiguration_r9_t*mbms_AreaConfig
) {
int i;
int UE_id = -1;
@@ -989,6 +990,7 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP,
cfg->num_tlv++;
//We need to reuse current MCH scheduler
//TOCHECK whether we can simply reuse current mbsfn_SubframeConfig stuff
+ RC.mac[Mod_idP]->common_channels[0].FeMBMS_flag = FeMBMS_Flag;
}
if (mbsfn_AreaInfoList != NULL) {
@@ -1005,6 +1007,21 @@ int rrc_mac_config_req_eNB(module_id_t Mod_idP,
}
}
+ if(mbms_AreaConfig != NULL) {
+ RC.mac[Mod_idP]->common_channels[0].commonSF_AllocPeriod_r9 = mbms_AreaConfig->commonSF_AllocPeriod_r9;
+ LOG_I(MAC, "[eNB %d][CONFIG] LTE_MBSFNAreaConfiguration_r9_t(%p) commonSF_AllocPeriod_r9(%d)\n",Mod_idP,mbms_AreaConfig, RC.mac[Mod_idP]->common_channels[0].commonSF_AllocPeriod_r9);
+ for(i=0; i < mbms_AreaConfig->commonSF_Alloc_r9.list.count; i++){
+ RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i] = mbms_AreaConfig->commonSF_Alloc_r9.list.array[i];
+ LOG_I(RRC,"[eNB %d][CONFIG] MBSFNArea[%d] commonSF_Alloc_r9: radioframeAllocationPeriod(%ldn),radioframeAllocationOffset(%ld), subframeAllocation(%x,%x,%x)\n"
+ ,Mod_idP,i
+ ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->radioframeAllocationPeriod
+ ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->radioframeAllocationOffset
+ ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[0]
+ ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[1]
+ ,RC.mac[Mod_idP]->common_channels[0].commonSF_Alloc_r9_mbsfn_SubframeConfig[i]->subframeAllocation.choice.oneFrame.buf[2]);
+ }
+ }
+
if (pmch_InfoList != NULL) {
// LOG_I(MAC,"DUY: lcid when entering rrc_mac config_req is %02d\n",(pmch_InfoList->list.array[0]->mbms_SessionInfoList_r9.list.array[0]->logicalChannelIdentity_r9));
LOG_I(MAC, "[CONFIG] Number of PMCH in this MBSFN Area %d\n",
diff --git a/openair2/LAYER2/MAC/config_NB_IoT.h b/openair2/LAYER2/MAC/config_NB_IoT.h
index fb8c85ebed22570bd49907f3d3b4021f496ceb65..1821b4e12d885a3dd202aa6bab856743762ac59b 100644
--- a/openair2/LAYER2/MAC/config_NB_IoT.h
+++ b/openair2/LAYER2/MAC/config_NB_IoT.h
@@ -8,8 +8,8 @@
*
*/
-#ifndef _CONFIG_H_
-#define _CONFIG_H_
+#ifndef __LAYER2_MAC_CONFIG_NB_IOT__H__
+#define __LAYER2_MAC_CONFIG_NB_IOT__H__
//#include "NB_IoT_Message_definitions.h"
diff --git a/openair2/LAYER2/MAC/config_ue.c b/openair2/LAYER2/MAC/config_ue.c
index 897afbf62bc960dc73070aaef2e94715de4971b9..1c5e70621803a3ad8dec8b80aead42b771b11ac3 100644
--- a/openair2/LAYER2/MAC/config_ue.c
+++ b/openair2/LAYER2/MAC/config_ue.c
@@ -530,6 +530,7 @@ rrc_mac_config_req_ue(module_id_t Mod_idP,
LOG_I(MAC, "[UE %d] Configuring LTE_NonMBSFN \n",
Mod_idP);
phy_config_sib1_fembms_ue(Mod_idP, CC_idP, 0, nonMBSFN_SubframeConfig);
+ UE_mac_inst[Mod_idP].non_mbsfn_SubframeConfig = nonMBSFN_SubframeConfig;
}
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
diff --git a/openair2/LAYER2/MAC/eNB_scheduler.c b/openair2/LAYER2/MAC/eNB_scheduler.c
index c46005ee2d5f28935f3dfe6a806e718718ef7fd1..8f5aab99a7706f1b858ac045f6e7ea5d33dcef34 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler.c
@@ -547,7 +547,7 @@ copy_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
ul_req_tmp->ul_config_request_body.number_of_pdus = 0;
if (ul_req->ul_config_request_body.number_of_pdus>0) {
- LOG_D(PHY, "%s() active NOW (frameP:%d subframeP:%d) pdus:%d\n", __FUNCTION__, frameP, subframeP, ul_req->ul_config_request_body.number_of_pdus);
+ LOG_D(MAC, "%s() active NOW (frameP:%d subframeP:%d) pdus:%d\n", __FUNCTION__, frameP, subframeP, ul_req->ul_config_request_body.number_of_pdus);
}
memcpy((void *)ul_req->ul_config_request_body.ul_config_pdu_list,
@@ -556,6 +556,11 @@ copy_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
}
}
+extern int16_t find_dlsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type);
+extern int16_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type);
+extern void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch);
+extern void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch);
+
void
eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
frame_t frameP,
@@ -843,6 +848,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
/* Note: This should not be done in the MAC! */
+ /*
for (int ii=0; ii<MAX_MOBILES_PER_ENB; ii++) {
LTE_eNB_ULSCH_t *ulsch = RC.eNB[module_idP][CC_id]->ulsch[ii];
@@ -862,6 +868,17 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
clean_eNb_dlsch(dlsch);
}
}
+ */
+
+ int id;
+
+ // clean ULSCH entries for rnti
+ id = find_ulsch(rnti,RC.eNB[module_idP][CC_id],SEARCH_EXIST);
+ if (id>=0) clean_eNb_ulsch(RC.eNB[module_idP][CC_id]->ulsch[id]);
+
+ // clean DLSCH entries for rnti
+ id = find_dlsch(rnti,RC.eNB[module_idP][CC_id],SEARCH_EXIST);
+ if (id>=0) clean_eNb_dlsch(RC.eNB[module_idP][CC_id]->dlsch[id][0]);
for (int j = 0; j < 10; j++) {
nfapi_ul_config_request_body_t *ul_req_tmp = NULL;
@@ -904,6 +921,7 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
#endif
+ int do_fembms_si=0;
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
if (cc[CC_id].MBMS_flag > 0) {
start_meas(&RC.mac[module_idP]->schedule_mch);
@@ -914,6 +932,10 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
stop_meas(&RC.mac[module_idP]->schedule_mch);
}
+ if (cc[CC_id].FeMBMS_flag > 0) {
+ do_fembms_si = 1;
+ }
+
}
static int debug_flag = 0;
@@ -935,12 +957,22 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
/* This schedules MIB */
- if ((subframeP == 0) && (frameP & 3) == 0)
- schedule_mib(module_idP, frameP, subframeP);
+ if(!do_fembms_si/*get_softmodem_params()->fembms*/){
+ if ((subframeP == 0) && (frameP & 3) == 0)
+ schedule_mib(module_idP, frameP, subframeP);
+ }else{
+ if ((subframeP == 0) && (frameP & 15) == 0 ){
+ schedule_fembms_mib(module_idP, frameP, subframeP);
+ //schedule_SI_MBMS(module_idP, frameP, subframeP);
+ }
+ }
if (get_softmodem_params()->phy_test == 0) {
/* This schedules SI for legacy LTE and eMTC starting in subframeP */
- schedule_SI(module_idP, frameP, subframeP);
+ if(!do_fembms_si/*get_softmodem_params()->fembms*/)
+ schedule_SI(module_idP, frameP, subframeP);
+ else
+ schedule_SI_MBMS(module_idP, frameP, subframeP);
/* This schedules Paging in subframeP */
schedule_PCH(module_idP,frameP,subframeP);
/* This schedules Random-Access for legacy LTE and eMTC starting in subframeP */
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_bch.c b/openair2/LAYER2/MAC/eNB_scheduler_bch.c
index 5b99578d57d340bd724f6d6b81c9f219d9b0994d..e4b9a7a65bf85781f3dc40b358f91f4c8c29b195 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_bch.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_bch.c
@@ -731,6 +731,7 @@ schedule_SI_MBMS(module_id_t module_idP, frame_t frameP,
if (subframeP == 0) {
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
cc = &eNB->common_channels[CC_id];
+ //printf("*cc->sib1_MBMS->si_WindowLength_r14 %d \n", *cc->sib1_MBMS->si_WindowLength_r14);
vrb_map = (void *) &cc->vrb_map;
N_RB_DL = to_prb(cc->mib->message.dl_Bandwidth);
dl_config_request = &eNB->DL_req[CC_id];
@@ -911,6 +912,64 @@ schedule_SI_MBMS(module_id_t module_idP, frame_t frameP,
stop_meas(&eNB->schedule_si_mbms);
}
+void
+schedule_fembms_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
+ eNB_MAC_INST *eNB = RC.mac[module_idP];
+ COMMON_channels_t *cc;
+ nfapi_dl_config_request_pdu_t *dl_config_pdu;
+ nfapi_tx_request_pdu_t *TX_req;
+ int mib_sdu_length;
+ int CC_id;
+ nfapi_dl_config_request_t *dl_config_request;
+ nfapi_dl_config_request_body_t *dl_req;
+ uint16_t sfn_sf = frameP << 4 | subframeP;
+ AssertFatal(subframeP == 0, "Subframe must be 0\n");
+ AssertFatal((frameP & 15) == 0, "Frame must be a multiple of 16\n");
+
+ for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
+ dl_config_request = &eNB->DL_req[CC_id];
+ dl_req = &dl_config_request->dl_config_request_body;
+ cc = &eNB->common_channels[CC_id];
+ mib_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MIBCH_MBMS, 0xFFFF, 1, &cc->MIB_pdu.payload[0], 0); // not used in this case
+ LOG_D(MAC, "Frame %d, subframe %d: BCH PDU length %d\n", frameP, subframeP, mib_sdu_length);
+
+ if (mib_sdu_length > 0) {
+ LOG_D(MAC, "Frame %d, subframe %d: Adding BCH PDU in position %d (length %d)\n", frameP, subframeP, dl_req->number_pdu, mib_sdu_length);
+
+ if ((frameP & 1023) < 40)
+ LOG_D(MAC,
+ "[eNB %d] Frame %d : MIB->BCH CC_id %d, Received %d bytes (cc->mib->message.schedulingInfoSIB1_BR_r13 %d)\n",
+ module_idP, frameP, CC_id, mib_sdu_length,
+ (int) cc->mib->message.schedulingInfoSIB1_BR_r13);
+
+ dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
+ memset((void *) dl_config_pdu, 0,
+ sizeof(nfapi_dl_config_request_pdu_t));
+ dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_BCH_PDU_TYPE, dl_config_pdu->pdu_size =
+ 2 + sizeof(nfapi_dl_config_bch_pdu);
+ dl_config_pdu->bch_pdu.bch_pdu_rel8.tl.tag = NFAPI_DL_CONFIG_REQUEST_BCH_PDU_REL8_TAG;
+ dl_config_pdu->bch_pdu.bch_pdu_rel8.length = mib_sdu_length;
+ dl_config_pdu->bch_pdu.bch_pdu_rel8.pdu_index = eNB->pdu_index[CC_id];
+ dl_config_pdu->bch_pdu.bch_pdu_rel8.transmission_power = 6000;
+ dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG;
+ dl_req->number_pdu++;
+ dl_config_request->header.message_id = NFAPI_DL_CONFIG_REQUEST;
+ dl_config_request->sfn_sf = sfn_sf;
+ LOG_D(MAC, "eNB->DL_req[0].number_pdu %d (%p)\n", dl_req->number_pdu, &dl_req->number_pdu);
+ // DL request
+ TX_req = &eNB->TX_req[CC_id].tx_request_body.tx_pdu_list[eNB->TX_req[CC_id].tx_request_body.number_of_pdus];
+ TX_req->pdu_length = 3;
+ TX_req->pdu_index = eNB->pdu_index[CC_id]++;
+ TX_req->num_segments = 1;
+ TX_req->segments[0].segment_length = 3;
+ TX_req->segments[0].segment_data = cc[CC_id].MIB_pdu.payload;
+ eNB->TX_req[CC_id].tx_request_body.number_of_pdus++;
+ eNB->TX_req[CC_id].sfn_sf = sfn_sf;
+ eNB->TX_req[CC_id].tx_request_body.tl.tag = NFAPI_TX_REQUEST_BODY_TAG;
+ eNB->TX_req[CC_id].header.message_id = NFAPI_TX_REQUEST;
+ }
+ }
+}
void
schedule_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
index 7621994ab2e1f247011f7ea7d03db1ef298d32be..1f99f50ece2019987b4b2e47dd8fe7bd68a46201 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
@@ -573,10 +573,7 @@ schedule_ue_spec(module_id_t module_idP,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR,
VCD_FUNCTION_IN);
start_meas(&eNB->schedule_dlsch_preprocessor);
- dlsch_scheduler_pre_processor(module_idP,
- CC_id,
- frameP,
- subframeP);
+ eNB->pre_processor_dl.dl(module_idP, CC_id, frameP, subframeP);
stop_meas(&eNB->schedule_dlsch_preprocessor);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_PREPROCESSOR,
VCD_FUNCTION_OUT);
@@ -588,6 +585,7 @@ schedule_ue_spec(module_id_t module_idP,
UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id];
eNB_UE_STATS *eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id];
+ eNB_UE_stats->TBS = 0;
const rnti_t rnti = ue_template->rnti;
// If TDD
@@ -679,15 +677,15 @@ schedule_ue_spec(module_id_t module_idP,
const uint32_t rbc = allocate_prbs_sub(
nb_rb, N_RB_DL, N_RBG, ue_sched_ctrl->rballoc_sub_UE[CC_id]);
- if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id]) {
- LOG_D(MAC,
- "[eNB %d] Frame %d CC_id %d : don't schedule UE %d, its retransmission takes more resources than we have\n",
+ if (nb_rb > ue_sched_ctrl->pre_nb_available_rbs[CC_id])
+ LOG_W(MAC,
+ "[eNB %d] %d.%d CC_id %d : should not schedule UE %d, its "
+ "retransmission takes more resources than we have\n",
module_idP,
frameP,
+ subframeP,
CC_id,
UE_id);
- continue;
- }
/* CDRX */
ue_sched_ctrl->harq_rtt_timer[CC_id][harq_pid] = 1; // restart HARQ RTT timer
@@ -799,6 +797,7 @@ schedule_ue_spec(module_id_t module_idP,
eNB_UE_stats->rbs_used_retx = nb_rb;
eNB_UE_stats->total_rbs_used_retx += nb_rb;
eNB_UE_stats->dlsch_mcs2 = eNB_UE_stats->dlsch_mcs1;
+ eNB_UE_stats->TBS = TBS;
} else {
// Now check RLC information to compute number of required RBs
// get maximum TBS size for RLC request
@@ -842,13 +841,18 @@ schedule_ue_spec(module_id_t module_idP,
if (ue_sched_ctrl->dl_lc_bytes[i] == 0) // no data in this LC!
continue;
- LOG_D(MAC, "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d bytes from RLC (RRC message)\n",
+ const uint32_t data =
+ min(ue_sched_ctrl->dl_lc_bytes[i],
+ TBS - ta_len - header_length_total - sdu_length_total - 3);
+ LOG_D(MAC,
+ "[eNB %d] SFN/SF %d.%d, LC%d->DLSCH CC_id %d, Requesting %d "
+ "bytes from RLC (RRC message)\n",
module_idP,
frameP,
subframeP,
lcid,
CC_id,
- TBS - ta_len - header_length_total - sdu_length_total - 3);
+ data);
sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP,
rnti,
@@ -857,7 +861,7 @@ schedule_ue_spec(module_id_t module_idP,
ENB_FLAG_YES,
MBMS_FLAG_NO,
lcid,
- TBS - ta_len - header_length_total - sdu_length_total - 3,
+ data,
(char *)&dlsch_buffer[sdu_length_total],
0,
0
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
index 00fd40109db819a754e3bbf9ad79810df59b0641..f6220fa46de3d59b198a6a54ac89a340a307ada9 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
@@ -2240,7 +2240,7 @@ void ulsch_scheduler_pre_ue_select_fairRR(
uint8_t first_ue_total[MAX_NUM_CCs][20];
uint8_t first_ue_id[MAX_NUM_CCs][20];
uint8_t ul_inactivity_num[MAX_NUM_CCs];
- uint8_t ul_inactivity_id[MAX_NUM_CCs][20]={0};
+ uint8_t ul_inactivity_id[MAX_NUM_CCs][20]={{0}};
// LTE_DL_FRAME_PARMS *frame_parms;
uint8_t ulsch_ue_max_num[MAX_NUM_CCs];
uint16_t saved_ulsch_dci[MAX_NUM_CCs];
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_mch.c b/openair2/LAYER2/MAC/eNB_scheduler_mch.c
index eb5d78fd3f4b25d22c177d636a14cec72988b306..0c686a6475c57240fa31818fef6d6be699cb2656 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_mch.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_mch.c
@@ -66,7 +66,11 @@ get_mbsfn_sf_alloction(module_id_t module_idP, uint8_t CC_id,
"[eNB %d] CC_id %d MBSFN synchronization area %d out of range\n ",
module_idP, CC_id, mbsfn_sync_area);
return -1;
- } else if (RC.mac[module_idP]->
+ }else if (RC.mac[module_idP]->
+ common_channels[CC_id].non_mbsfn_SubframeConfig
+ != NULL) {
+ return mbsfn_sync_area;
+ }else if (RC.mac[module_idP]->
common_channels[CC_id].mbsfn_SubframeConfig[mbsfn_sync_area]
!= NULL) {
return mbsfn_sync_area;
@@ -80,14 +84,30 @@ get_mbsfn_sf_alloction(module_id_t module_idP, uint8_t CC_id,
static uint32_t bytes_in_buffer=0;
static uint32_t msi_pmch_stop=0;
-//static uint8_t msi_active=0;
-//static uint8_t msi_pmch_stop2=0;
-uint16_t mbms_rab_id = 2047;
+uint16_t mbms_rab_id=2047;//[8] = {2047,2047,2047,2047,2047,2047,2047,2047};
static uint32_t msi_sfs=0;
//MSI_ELEMENT * ptr =NULL;
+static int check_CAS_sf(frame_t frameP,sub_frame_t subframeP){
+ if( ((frameP&3)==0) && (subframeP == 0))
+ return 1;
+ else
+ return 0;
+}
+static int check_nonMBSFN_sf(frame_t frameP,COMMON_channels_t *cc,int sf){
+ uint32_t non_mbsfn_SubframeConfig = (cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
+ if( frameP % (4<<cc->non_mbsfn_SubframeConfig->radioFrameAllocationPeriod_r14) == cc->non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14 ){
+ return (non_mbsfn_SubframeConfig & (0x200>>(sf)))==(0x200 >> (sf));
+ }
+ return 0;
+}
+
+
+static int x=0;
+static int mbms_mch_i=0;
+
int
schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
sub_frame_t subframeP)
@@ -99,395 +119,571 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
int mcch_flag = 0, mtch_flag = 0, msi_flag = 0;
int mbsfn_period = 0; // 1<<(RC.mac[module_idP]->mbsfn_SubframeConfig[0]->radioframeAllocationPeriod);
int mcch_period = 0; //32<<(RC.mac[module_idP]->mbsfn_AreaInfo[0]->mcch_Config_r9.mcch_RepetitionPeriod_r9);
+ //TOCHECK mtch index here
if(RC.mac[module_idP]->common_channels[CC_id].
pmch_Config[0] == NULL )
-
return 0;
-
-
-
+ //TOCHECK mtch index here
int mch_scheduling_period =
8 << (RC.mac[module_idP]->common_channels[CC_id].
pmch_Config[0]->mch_SchedulingPeriod_r9);
- unsigned char mcch_sdu_length;
- unsigned char header_len_mcch = 0, header_len_msi =
- 0, header_len_mtch = 0, header_len_mtch_temp =
- 0, header_len_mcch_temp = 0, header_len_msi_temp = 0;
- int ii = 0, msi_pos = 0;
- int mcch_mcs = -1;
- uint16_t TBS, j = -1, padding = 0, post_padding = 0;
- mac_rlc_status_resp_t rlc_status;
- //mac_rlc_status_resp_t rlc_status2;
- int num_mtch;
- int msi_length=0, i, k;
- //uint8_t l =0;
- unsigned char sdu_lcids[11], num_sdus = 0, offset = 0;
- uint16_t sdu_lengths[11], sdu_length_total = 0;
- unsigned char mch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; // check the max value, this is for dlsch only
-
- COMMON_channels_t *cc = &RC.mac[module_idP]->common_channels[CC_id];
-
- cc->MCH_pdu.Pdu_size = 0;
-
- for (i = 0; i < cc->num_active_mbsfn_area; i++) {
- // assume, that there is always a mapping
- if ((j = get_mbsfn_sf_alloction(module_idP, CC_id, i)) == -1) {
- return 0;
- }
-
- mbsfn_period =
- 1 << (cc->mbsfn_SubframeConfig[j]->radioframeAllocationPeriod);
- mcch_period =
- 32 << (cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_RepetitionPeriod_r9);
- msi_pos = 0;
- ii = 0;
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d : Checking MBSFN Sync Area %d/%d with SF allocation %d/%d for MCCH and MTCH (mbsfn period %d, mcch period %d)\n",
- module_idP, CC_id, frameP, subframeP, i,
- cc->num_active_mbsfn_area, j, cc->num_sf_allocation_pattern,
- mbsfn_period, mcch_period);
-
-
- switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) {
- case 0:
- mcch_mcs = 2;
- break;
-
- case 1:
- mcch_mcs = 7;
- break;
-
- case 2:
- mcch_mcs = 13;
- break;
-
- case 3:
- mcch_mcs = 19;
- break;
- }
-
- // 1st: Check the MBSFN subframes from SIB2 info (SF allocation pattern i, max 8 non-overlapping patterns exist)
- if (frameP % mbsfn_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) { // MBSFN frameP
- if (cc->mbsfn_SubframeConfig[j]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { // one-frameP format
-
- // Find the first subframeP in this MCH to transmit MSI
- if (frameP % mch_scheduling_period ==
- cc->mbsfn_SubframeConfig[j]->
- radioframeAllocationOffset) {
- while (ii == 0) {
- ii = cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & (0x80 >> msi_pos);
- msi_pos++;
- }
-
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d : sync area %d sf allocation pattern %d sf alloc %x msi pos is %d \n",
- module_idP, CC_id, frameP, subframeP, i, j,
- cc->mbsfn_SubframeConfig[j]->
- subframeAllocation.choice.oneFrame.buf[0],
- msi_pos);
- }
- // Check if the subframeP is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
- switch (subframeP) {
- case 1:
- if (cc->tdd_Config == NULL) {
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF1) ==
- MBSFN_FDD_SF1) {
- if (msi_pos == 1) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF1) ==
- MBSFN_FDD_SF1)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 2:
- if (cc->tdd_Config == NULL) {
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF2) ==
- MBSFN_FDD_SF2) {
- if (msi_pos == 2) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF2) ==
- MBSFN_FDD_SF2)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 3:
- if (cc->tdd_Config != NULL) { // TDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_TDD_SF3) ==
- MBSFN_TDD_SF3) {
- if (msi_pos == 1) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_TDD_SF3) ==
- MBSFN_TDD_SF3)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- } else { // FDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF3) ==
- MBSFN_FDD_SF3) {
- if (msi_pos == 3) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF3) ==
- MBSFN_FDD_SF3)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 4:
- if (cc->tdd_Config != NULL) {
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_TDD_SF4) ==
- MBSFN_TDD_SF4) {
- if (msi_pos == 2) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_TDD_SF4) ==
- MBSFN_TDD_SF4)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 6:
- if (cc->tdd_Config == NULL) {
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF6) ==
- MBSFN_FDD_SF6) {
- if (msi_pos == 4) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF6) ==
- MBSFN_FDD_SF6)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 7:
- if (cc->tdd_Config != NULL) { // TDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_TDD_SF7) ==
- MBSFN_TDD_SF7) {
- if (msi_pos == 3) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_TDD_SF7) ==
- MBSFN_TDD_SF7)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- } else { // FDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF7) ==
- MBSFN_FDD_SF7) {
- if (msi_pos == 5) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF7) ==
- MBSFN_FDD_SF7)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- }
-
- break;
-
- case 8:
- if (cc->tdd_Config != NULL) { //TDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_TDD_SF8) ==
- MBSFN_TDD_SF8) {
- if (msi_pos == 4) {
- msi_flag = 1;
- }
-
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_TDD_SF8) ==
- MBSFN_TDD_SF8)) {
- mcch_flag = 1;
- }
-
- mtch_flag = 1;
- }
- } else { // FDD
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_FDD_SF8) ==
- MBSFN_FDD_SF8) {
- if (msi_pos == 6) {
- msi_flag = 1;
- }
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_FDD_SF8) ==
- MBSFN_FDD_SF8)) {
- mcch_flag = 1;
- }
+ unsigned char mcch_sdu_length;
+ unsigned char header_len_mcch = 0, header_len_msi =
+ 0, header_len_mtch = 0, header_len_mtch_temp =
+ 0, header_len_mcch_temp = 0, header_len_msi_temp = 0;
+ int ii = 0, msi_pos = -1;
+ int mcch_mcs = -1;
+ int shifted_sf = 0;
+ uint16_t TBS, j = -1, padding = 0, post_padding = 0;
+ mac_rlc_status_resp_t rlc_status;
+ int num_mtch=0;
+ int msi_length=0, i, k;
- mtch_flag = 1;
- }
- }
+ unsigned char sdu_lcids[11], num_sdus = 0, offset = 0;
+ uint16_t sdu_lengths[11], sdu_length_total = 0;
+ unsigned char mch_buffer[MAX_DLSCH_PAYLOAD_BYTES]; // check the max value, this is for dlsch only
- break;
+ COMMON_channels_t *cc = &RC.mac[module_idP]->common_channels[CC_id];
- case 9:
- if (cc->tdd_Config != NULL) {
- if ((cc->
- mbsfn_SubframeConfig[j]->subframeAllocation.
- choice.oneFrame.buf[0] & MBSFN_TDD_SF9) ==
- MBSFN_TDD_SF9) {
- if (msi_pos == 5) {
- msi_flag = 1;
- }
+ cc->MCH_pdu.Pdu_size = 0;
- if ((frameP % mcch_period ==
- cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.mcch_Offset_r9)
- &&
- ((cc->mbsfn_AreaInfo[i]->
- mcch_Config_r9.sf_AllocInfo_r9.
- buf[0] & MBSFN_TDD_SF9) ==
- MBSFN_TDD_SF9)) {
- mcch_flag = 1;
- }
+ for (i = 0; i < cc->num_active_mbsfn_area; i++) {
+ // assume, that there is always a mapping
+ if ((j = get_mbsfn_sf_alloction(module_idP, CC_id, i)) == -1) {
+ return 0;
+ }
- mtch_flag = 1;
- }
- }
+ if(cc->non_mbsfn_SubframeConfig){
+ int alloc_offset=0;
+ uint32_t period;
+
+ uint32_t non_mbsfn_SubframeConfig = (cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | cc->non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
+ long mcch_offset = cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9;
+
+ period = 4<<cc->non_mbsfn_SubframeConfig->radioFrameAllocationPeriod_r14;
+ alloc_offset = cc->non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14;
+ mcch_period = 32 << cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_RepetitionPeriod_r9;
+
+ // get the real MCS value
+ switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) {
+ case 0:
+ mcch_mcs = 2;
+ break;
+
+ case 1:
+ mcch_mcs = 7;
+ break;
+
+ case 2:
+ mcch_mcs = 13;
+ break;
+
+ case 3:
+ mcch_mcs = 19;
+ break;
+ }
+
+ if (cc->pmch_Config[0]) {
+ mch_scheduling_period = 8 << cc->pmch_Config[0]->mch_SchedulingPeriod_r9;
+ }
+
+ LOG_D(MAC,"frameP %d subframe %d period %d alloc_offset %d mcch_mcs %d mcch_period %d mcch_offset %ld buf %x mch_scheduling_period %d\n",frameP, subframeP, period, alloc_offset,mcch_mcs, mcch_period, mcch_offset,(cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0]),mch_scheduling_period);
+ //if( (frameP % (4 << cc->commonSF_AllocPeriod_r9) ) == 0 ){
+ // if((subframeP==0)){
+ // x=0;
+ // mbms_mch_i=0;
+ // }
+ //}
+ //if (frameP % (4 << cc->commonSF_AllocPeriod_r9 ) == 0) {
+ // if((subframeP==0)){
+ // x=0;
+ // mbms_mch_i=0;
+ // }
+ //}
+ if (cc->pmch_Config[0]) {
+ // Find the first subframe in this MCH to transmit MSI
+ if (frameP % 1 == 0) {
+ if (frameP % mch_scheduling_period == 0) {
+ msi_pos=0;
+ if((frameP&3)==0)
+ msi_pos++;
+ while((non_mbsfn_SubframeConfig & (0x100 >> msi_pos)) == (0x100>>msi_pos))
+ msi_pos++;
+ mbms_mch_i=0;
- break;
- } // end switch
+ if((subframeP==0)){
+ x=0;
+ mbms_mch_i=0;
+ }
+
+ }
+ }
+ }
- // sf allocation is non-overlapping
- if ((msi_flag == 1) || (mcch_flag == 1)
- || (mtch_flag == 1)) {
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n",
- module_idP, CC_id, frameP, subframeP, i, j,
- msi_flag, mcch_flag, mtch_flag);
- break;
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9+shifted_sf){
+
+ shifted_sf = check_nonMBSFN_sf(frameP,cc,subframeP)+check_CAS_sf(frameP,subframeP);
+ msi_pos=subframeP+shifted_sf;
+ if(shifted_sf==0)
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d shifted_sf %d\n",frameP, subframeP, msi_pos,mbms_mch_i,shifted_sf);
}
- } else { // four-frameP format
}
- }
- } // end of for loop
+
+ // Check if the subframe is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
+ switch (subframeP) {
+ case 0:
+ if (msi_pos == 0) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+ case 1:
+ if (msi_pos == 1) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 2:
+ if (msi_pos == 2) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+
+ break;
+
+ case 3:
+ if (msi_pos == 3) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 4:
+ if (msi_pos == 4) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 5:
+ if (msi_pos == 5) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 6:
+ if (msi_pos == 6) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 7:
+ if (msi_pos == 7) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 8:
+ if (msi_pos == 8) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 9:
+ if (msi_pos == 9) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+ }// end switch
+
+ if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) {
+ LOG_D(MAC,
+ "[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n",
+ module_idP, CC_id, frameP, subframeP, i, j,
+ msi_flag, mcch_flag, mtch_flag);
+ }
+
+ //TODO quitar la subframe 0 del otro switch ... está mal interpretado ?
+ // if((frameP&3) == 0){
+ // mtch_flag=0;mcch_flag=0;msi_flag=0;
+ // }
+
+ if((frameP % period ) == alloc_offset){
+ LOG_D(MAC,"non_mbsfn_SubframeConfig %x\n",non_mbsfn_SubframeConfig);
+ switch(subframeP){
+ case 0:{
+ mtch_flag=0;mcch_flag=0;msi_flag=0;
+ }
+ break;
+ case 1:{
+ if ((non_mbsfn_SubframeConfig & 0x100) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 2:{
+ if ((non_mbsfn_SubframeConfig & 0x80) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 3:{
+ if ((non_mbsfn_SubframeConfig & 0x40) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 4:{
+ if ((non_mbsfn_SubframeConfig & 0x20) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 5:{
+ if ((non_mbsfn_SubframeConfig & 0x10) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 6:{
+ if ((non_mbsfn_SubframeConfig & 0x8) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 7:{
+ if ((non_mbsfn_SubframeConfig & 0x4) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 8:{
+ if ((non_mbsfn_SubframeConfig & 0x2) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ case 9:{
+ if ((non_mbsfn_SubframeConfig & 0x1) > 0)
+ {mtch_flag=0;mcch_flag=0;msi_flag=0;}
+ }
+ break;
+ }
+ }
+ // sf allocation is non-overlapping
+ if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) {
+ x++;
+ //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){
+ //x++;
+ //}
+
+ if(msi_flag==1){
+ if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %( 4 << cc->commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 << cc->pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){
+ msi_flag=0;
+ LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframeP, mbms_mch_i);
+ }
+
+ }
+
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d, x %d\n",
+ module_idP, CC_id, frameP, subframeP, i, j,
+ msi_flag, mcch_flag, mtch_flag,x);
+ break;
+ }
+
+
+ }else if(cc->mbsfn_SubframeConfig[j]){
+
+ mbsfn_period =
+ 1 << (cc->mbsfn_SubframeConfig[j]->radioframeAllocationPeriod);
+ mcch_period =
+ 32 << (cc->mbsfn_AreaInfo[i]->
+ mcch_Config_r9.mcch_RepetitionPeriod_r9);
+ msi_pos = 0;
+ ii = 0;
+ LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : Checking MBSFN Sync Area %d/%d with SF allocation %d/%d for MCCH and MTCH (mbsfn period %d, mcch period %d)\n",
+ module_idP, CC_id, frameP, subframeP, i,
+ cc->num_active_mbsfn_area, j, cc->num_sf_allocation_pattern,
+ mbsfn_period, mcch_period);
+
+ switch (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) {
+ case 0:
+ mcch_mcs = 2;
+ break;
+
+ case 1:
+ mcch_mcs = 7;
+ break;
+
+ case 2:
+ mcch_mcs = 13;
+ break;
+
+ case 3:
+ mcch_mcs = 19;
+ break;
+ }
+
+ // 1st: Check the MBSFN subframes from SIB2 info (SF allocation pattern i, max 8 non-overlapping patterns exist)
+ if (frameP % mbsfn_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) { // MBSFN frameP
+ if (cc->mbsfn_SubframeConfig[j]->subframeAllocation.present == LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame) { // one-frameP format
+ // Find the first subframeP in this MCH to transmit MSI
+ if (frameP % mch_scheduling_period == cc->mbsfn_SubframeConfig[j]->radioframeAllocationOffset) {
+ while (ii == 0) {
+ ii = cc->
+ mbsfn_SubframeConfig[j]->subframeAllocation.
+ choice.oneFrame.buf[0] & (0x80 >> msi_pos);
+ msi_pos++;
+ }
+ LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : sync area %d sf allocation pattern %d sf alloc %x msi pos is %d \n",
+ module_idP, CC_id, frameP, subframeP, i, j,
+ cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0],
+ msi_pos);
+ if((subframeP==1)){
+ x=0;
+ mbms_mch_i=0;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+
+ // Check if the subframeP is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
+ switch (subframeP) {
+ case 1:
+ if (cc->tdd_Config == NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=1;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+ if (msi_pos == 1) {
+ msi_flag = 1;
+ }
+ if ( (frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ && ( (cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) ) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 2:
+ if (cc->tdd_Config == NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=2;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+
+ if (msi_pos == 2) {
+ msi_flag = 1;
+ }
+ if ( (frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ && ((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 3:
+ if (cc->tdd_Config != NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3) {
+ if (msi_pos == 1) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF3) == MBSFN_TDD_SF3)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ } else { // FDD
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=3;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+ if (msi_pos == 3) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 4:
+ if (cc->tdd_Config != NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4) {
+ if (msi_pos == 2) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF4) == MBSFN_TDD_SF4)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 6:
+ if (cc->tdd_Config == NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=4;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+ if (msi_pos == 4) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 7:
+ if (cc->tdd_Config != NULL) { // TDD
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7) {
+ if (msi_pos == 3) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF7) == MBSFN_TDD_SF7)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ } else { // FDD
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=5;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+
+ if (msi_pos == 5) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 8:
+ if (cc->tdd_Config != NULL) { //TDD
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8) {
+ if (msi_pos == 4) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF8) == MBSFN_TDD_SF8)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ } else { // FDD
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8) {
+ if(cc->pmch_Config[mbms_mch_i+1]!=NULL){
+ if( x == cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=6;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframeP, msi_pos,mbms_mch_i);
+ }
+ }
+ if (msi_pos == 6) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ case 9:
+ if (cc->tdd_Config != NULL) {
+ if ((cc->mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9) {
+ if (msi_pos == 5) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == cc->mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9)
+ &&((cc->mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_TDD_SF9) == MBSFN_TDD_SF9)) {
+ mcch_flag = 1;
+ }
+ mtch_flag = 1;
+ }
+ }
+ break;
+ } // end switch
+ // sf allocation is non-overlapping
+ if ((msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1)) {
+ x++;
+ //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){
+ //x++;
+ //}
+ if(msi_flag==1){
+ if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %( 4 << cc->commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 << cc->pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){
+ msi_flag=0;
+ LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframeP, mbms_mch_i);
+ }
+
+ }
+
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d x %d\n",
+ module_idP, CC_id, frameP, subframeP, i, j,
+ msi_flag, mcch_flag, mtch_flag,x);
+ break;
+ }
+ } else {// four-frameP format
+ printf("Hola\n");
+ AssertFatal(1==0,"four-frameP format: not implemented yet\n");
+ }
+ }
+ } // MBMS format
+ }// end of for loop
cc->msi_active = 0;
cc->mcch_active = 0;
@@ -497,7 +693,7 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
if ((msi_flag == 1) || (mcch_flag == 1)) {
cc->MCH_pdu.mcs = mcch_mcs;
} else if (mtch_flag == 1) { // only MTCH in this subframeP
- cc->MCH_pdu.mcs = cc->pmch_Config[0]->dataMCS_r9;
+ cc->MCH_pdu.mcs = cc->pmch_Config[mbms_mch_i]->dataMCS_r9;
}
@@ -510,26 +706,14 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
// there is MSI (MCH Scheduling Info)
uint16_t msi_control_element[29], *msi_ptr;
+ // MSI buffer pointer
char *buffer_pointer=NULL;
if (msi_flag == 1) {
// Create MSI here
- //uint16_t msi_control_element[29], *msi_ptr;
-
msi_ptr = &msi_control_element[0];
- //((MSI_ELEMENT *) msi_ptr)->lcid = MCCH_LCHANID; //MCCH
-
- //if (mcch_flag == 1) {
- // ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0;
- // ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0;
- //} else { // no mcch for this MSP
- // ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // stop value is 2047
- // ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xff;
- //}
-
- //msi_ptr += sizeof(MSI_ELEMENT);
//Header for MTCHs
- num_mtch = cc->mbms_SessionList[0]->list.count;
+ num_mtch = cc->mbms_SessionList[mbms_mch_i]->list.count;
TBS =
get_TBS_DL(cc->MCH_pdu.mcs, to_prb(cc->mib->message.dl_Bandwidth));
@@ -537,7 +721,7 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
for (k = 0; k < num_mtch; k++) { // loop for all session in this MCH (MCH[0]) at this moment
- ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[0]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid;
+ ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[mbms_mch_i]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid;
if( msi_sfs != 0 )
msi_pmch_stop = msi_sfs-1;
@@ -546,22 +730,15 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
msi_pmch_stop = msi_sfs;
- //if( msi_pmch_stop > cc->pmch_Config[0]->sf_AllocEnd_r9)
- //LOG_W(MAC,"e-MBMS Buffer Overflow\n");
-
if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) {
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0; // last subframeP of this mtch (only one mtch now) & stop_sf limited to 256
- //((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = msi_pmch_stop;
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9);
- msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9);
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = (((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) >> 8) & 0x7f);
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = ((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) & 0xff);
+ msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9);
}else{
((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now)
((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF;
msi_pmch_stop=0;
}
-
-
-
msi_ptr += sizeof(MSI_ELEMENT);
}
@@ -573,15 +750,11 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
header_len_msi = 3;
}
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d : MSI->MCH, length of MSI is %d bytes TBS %d, bytes in buffer %d stop_sf_LSB %d msi_sfs %d cc->pmch_Config[0]->sf_AllocEnd_r9 %ld\n",
- module_idP, CC_id, frameP, msi_length,TBS, bytes_in_buffer,msi_pmch_stop,msi_sfs,cc->pmch_Config[0]->sf_AllocEnd_r9);
+ LOG_D(MAC, "[eNB %d] CC_id %d Frame %d : MSI->MCH, length of MSI is %d bytes TBS %d, bytes in buffer %d stop_sf_LSB %d msi_sfs %d cc->pmch_Config[0]->sf_AllocEnd_r9 %ld\n",
+ module_idP, CC_id, frameP, msi_length,TBS, bytes_in_buffer,msi_pmch_stop,msi_sfs,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9);
msi_sfs = 0;
- //LOG_D(MAC,"Scheduler: MSI is transmitted in this subframeP \n" );
-
- // LOG_D(MAC,"Scheduler: MSI length is %d bytes\n",msi_length);
// Store MSI data to mch_buffer[0]
memcpy((char *) &mch_buffer[sdu_length_total],
msi_control_element, msi_length);
@@ -598,75 +771,93 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
}
// there is MCCH
if (mcch_flag == 1) {
-
- //LOG_E(MAC,
- //"[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (mod %d)\n",module_idP, CC_id, frameP, subframeP,frameP%2==0);
- if(1/*frameP%2==0*/){
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE (area %d, sfAlloc %d)\n",
- module_idP, CC_id, frameP, subframeP, i, j);
-
- mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH, 0xFFFC, 1, &cc->MCCH_pdu.payload[0],
- i); // this is the mbsfn sync area index
- }
- else{
- LOG_E(MAC,
- "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (area %d, sfAlloc %d)\n",
- module_idP, CC_id, frameP, subframeP, i, j);
-
-//
-// mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH_COUNTING, 0xFFFC, 1, &cc->MCCH_pdu.payload[0],
-// i); // this is the mbsfn sync area index
+ //MCCH scheduling if !FeMBMS
+ if(!cc->non_mbsfn_SubframeConfig){
+ mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH_COUNTING, 0xFFFC, 1, &cc->MCCH_pdu.payload[0],
+ i); // this is the mbsfn sync area index
+ if(mcch_sdu_length>0)
+ LOG_I(MAC, "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE COUNTING (area %d, sfAlloc %d)\n",
+ module_idP, CC_id, frameP, subframeP, i, j);
+
+ if (mcch_sdu_length > 0) {
+ mcch_sdu_length+=1; //RLC ?
+ LOG_D(MAC, "[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n",
+ module_idP, CC_id, frameP, subframeP, mcch_sdu_length);
+
+ header_len_mcch = 2;
+
+ if (cc->tdd_Config != NULL) {
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n",
+ module_idP, CC_id, frameP, subframeP,
+ mcch_sdu_length, mcch_mcs);
+ } else {
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n",
+ module_idP, CC_id, frameP, subframeP,
+ mcch_sdu_length, mcch_mcs);
+ }
+
+ cc->mcch_active = 1;
+
+ memcpy((char *) &mch_buffer[sdu_length_total]+1,
+ &cc->MCCH_pdu.payload[0], mcch_sdu_length);
+ sdu_lcids[num_sdus] = MCCH_LCHANID;
+ sdu_lengths[num_sdus] = mcch_sdu_length;
+
+ if (sdu_lengths[num_sdus] > 128) {
+ header_len_mcch = 3;
+ }
+
+ sdu_length_total += sdu_lengths[num_sdus];
+ LOG_D(MAC,
+ "[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n",
+ module_idP, CC_id, sdu_lengths[num_sdus]);
+ num_sdus++;
+ }
}
- mcch_sdu_length+=1; //RLC ?
-
- if (mcch_sdu_length > 0) {
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n",
- module_idP, CC_id, frameP, subframeP, mcch_sdu_length);
-
- header_len_mcch = 2;
-
- if (cc->tdd_Config != NULL) {
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n",
- module_idP, CC_id, frameP, subframeP,
- mcch_sdu_length, mcch_mcs);
- } else {
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n",
- module_idP, CC_id, frameP, subframeP,
- mcch_sdu_length, mcch_mcs);
- }
-
- cc->mcch_active = 1;
+ //MCCH scheduling ... do it anyway
+ {
+ LOG_I(MAC, "[eNB %d] CC_id %d Frame %d Subframe %d: Schedule MCCH MESSAGE (area %d, sfAlloc %d)\n",
+ module_idP, CC_id, frameP, subframeP, i, j);
+
+ mcch_sdu_length = mac_rrc_data_req(module_idP, CC_id, frameP, MCCH, 0xFFFC, 1, &cc->MCCH_pdu.payload[0],
+ i); // this is the mbsfn sync area index
+
+ if (mcch_sdu_length > 0) {
+ mcch_sdu_length+=1; //RLC ?
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d : MCCH->MCH, Received %d bytes from RRC \n",
+ module_idP, CC_id, frameP, subframeP, mcch_sdu_length);
+
+ header_len_mcch = 2;
+
+ if (cc->tdd_Config != NULL) {
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (TDD) for MCCH message %d bytes (mcs %d )\n",
+ module_idP, CC_id, frameP, subframeP,
+ mcch_sdu_length, mcch_mcs);
+ } else {
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Scheduling MCCH->MCH (FDD) for MCCH message %d bytes (mcs %d)\n",
+ module_idP, CC_id, frameP, subframeP,
+ mcch_sdu_length, mcch_mcs);
+ }
- memcpy((char *) &mch_buffer[sdu_length_total]+1,
- &cc->MCCH_pdu.payload[0], mcch_sdu_length);
- sdu_lcids[num_sdus] = MCCH_LCHANID;
- sdu_lengths[num_sdus] = mcch_sdu_length;
+ cc->mcch_active = 1;
- // LOG_W(MAC,"MCCH RLC %x:",(unsigned char)mch_buffer[sdu_length_total]);
- // for (int kk = 7; kk >= 0; kk--)
- // {
- // printf("%d",(((unsigned char)mch_buffer[sdu_length_total]) >> kk) & 1 ? '1' : '0');
- // }
- // printf("\n");
- //mch_buffer[sdu_length_total] = (unsigned char)0;
+ memcpy((char *) &mch_buffer[sdu_length_total]+1,
+ &cc->MCCH_pdu.payload[0], mcch_sdu_length);
+ sdu_lcids[num_sdus] = MCCH_LCHANID;
+ sdu_lengths[num_sdus] = mcch_sdu_length;
+ if (sdu_lengths[num_sdus] > 128) {
+ header_len_mcch = 3;
+ }
- if (sdu_lengths[num_sdus] > 128) {
- header_len_mcch = 3;
+ sdu_length_total += sdu_lengths[num_sdus];
+ LOG_D(MAC,"[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n",
+ module_idP, CC_id, sdu_lengths[num_sdus]);
+ num_sdus++;
}
-
- sdu_length_total += sdu_lengths[num_sdus];
- LOG_D(MAC,
- "[eNB %d] CC_id %d Got %d bytes for MCCH from RRC \n",
- module_idP, CC_id, sdu_lengths[num_sdus]);
- num_sdus++;
}
- }
+ }// mcch_flag
TBS =
@@ -678,154 +869,108 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
// there is MTCHs, loop if there are more than 1
if (mtch_flag == 1 ) {
// Calculate TBS
- /* if ((msi_flag==1) || (mcch_flag==1)) {
- TBS = mac_xface->get_TBS(mcch_mcs, mac_xface->frame_parms->N_RB_DL);
- }
- else { // only MTCH in this subframeP
- TBS = mac_xface->get_TBS(RC.mac[module_idP]->pmch_Config[0]->dataMCS_r9, mac_xface->frame_parms->N_RB_DL);
- }
-
- // get MTCH data from RLC (like for DTCH)
- LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframe %d: Schedule MTCH (area %d, sfAlloc %d)\n",Mod_id,CC_id,frame,subframe,i,j);
-
- header_len_mtch = 3;
- LOG_D(MAC,"[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n",
- Mod_id,CC_id,frame,MTCH,TBS,
- TBS-header_len_mcch-header_len_msi-sdu_length_total-header_len_mtch);
-
- rlc_status = mac_rlc_status_ind(Mod_id,frame,1,RLC_MBMS_YES,MTCH+ (maxDRB + 3) * MAX_MOBILES_PER_RG,
- TBS-header_len_mcch-header_len_msi-sdu_length_total-header_len_mtch);
- printf("frame %d, subframe %d, rlc_status.bytes_in_buffer is %d\n",frame,subframe, rlc_status.bytes_in_buffer);
-
- */
-
// get MTCH data from RLC (like for DTCH)
- LOG_D(MAC,
- "[eNB %d] CC_id %d Frame %d subframeP %d: Schedule MTCH (area %d, sfAlloc %d)\n",
+ LOG_D(MAC,"[eNB %d] CC_id %d Frame %d subframeP %d: Schedule MTCH (area %d, sfAlloc %d)\n",
module_idP, CC_id, frameP, subframeP, i, j);
header_len_mtch = 3;
- LOG_D(MAC,
- "[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n",
+ LOG_D(MAC,"[eNB %d], CC_id %d, Frame %d, MTCH->MCH, Checking RLC status (rab %d, tbs %d, len %d)\n",
module_idP, CC_id, frameP, MTCH, TBS,
TBS - header_len_mcch - header_len_msi - sdu_length_total -
header_len_mtch);
- mbms_rab_id = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9;
+ //TODO
+ mbms_rab_id = cc->mbms_SessionList[0/*mbms_mch_i*/]->list.array[0]->logicalChannelIdentity_r9;
rlc_status =
mac_rlc_status_ind(module_idP, 0xfffd, frameP, subframeP,
module_idP, ENB_FLAG_YES, MBMS_FLAG_YES,
- cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9,
+ cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9,
//MTCH,
0, 0
);
- bytes_in_buffer = rlc_status.bytes_in_buffer;
+ bytes_in_buffer = rlc_status.bytes_in_buffer;
+ //TOCHECK is this really neede?
if( !(mcch_flag==1 || msi_flag==1) )
msi_sfs = rlc_status.bytes_in_buffer/(TBS- header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)+(rlc_status.bytes_in_buffer%(TBS- header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)?1:0);
- //uint16_t msi_control_element[29], *msi_ptr;
- //
- //
- uint16_t TBS_MTCH =
- get_TBS_DL(cc->pmch_Config[0]->dataMCS_r9, to_prb(cc->mib->message.dl_Bandwidth));
- if(msi_flag==1 && buffer_pointer!=NULL){
- msi_ptr = &msi_control_element[0];
- //memcpy(buffer_pointer,
- // msi_control_element, msi_length);
+ uint16_t TBS_MTCH =
+ get_TBS_DL(cc->pmch_Config[mbms_mch_i]->dataMCS_r9, to_prb(cc->mib->message.dl_Bandwidth));
+
+ if(msi_flag==1 && buffer_pointer!=NULL){
+ // msi_ptr = &msi_control_element[0];
- // msi_pmch_stop = rlc_status.bytes_in_buffer/TBS+(rlc_status.bytes_in_buffer%TBS?1:0);
msi_pmch_stop = (rlc_status.bytes_in_buffer - header_len_mcch - header_len_msi -sdu_length_total - header_len_mtch)/(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)+((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0);
- if( msi_pmch_stop > cc->pmch_Config[0]->sf_AllocEnd_r9)
- LOG_E(MAC,"e-MBMS Buffer Overflow\n");
- if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) {
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0; // last subframeP of this mtch (only one mtch now) & stop_sf limited to 256
- //((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = msi_pmch_stop;
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9);
- msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[0]->sf_AllocEnd_r9);
- }else{
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now)
- ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF;
- msi_pmch_stop=0;
- }
- LOG_I(MAC,"frameP %d, subframeP %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d\n",frameP,subframeP,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB);
- //LOG_W(MAC,"frameP %d, subframeP %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d msi_calc:%d remainder %d\n",frameP,subframeP,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,rlc_status.bytes_in_buffer/(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)+((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0),((rlc_status.bytes_in_buffer-TBS-header_len_mcch - header_len_msi -sdu_length_total)%(TBS_MTCH/*- header_len_mcch - header_len_msi -sdu_length_total*/ - header_len_mtch)?0:0));
+ for (k = 0; k < num_mtch; k++) { // loop for all session in this MCH (MCH[0]) at this moment
+ msi_ptr = &msi_control_element[k];
- memcpy(buffer_pointer,
- msi_control_element, msi_length);
+ ((MSI_ELEMENT *) msi_ptr)->lcid = cc->mbms_SessionList[mbms_mch_i]->list.array[k]->logicalChannelIdentity_r9; //mtch_lcid;
+
+ if( msi_pmch_stop > cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9)
+ LOG_E(MAC,"e-MBMS Buffer Overflow\n");
+
+ if(msi_pmch_stop>=num_sf_alloc /*&& msi_pmch_stop <=cc->pmch_Config[0]->sf_AllocEnd_r9*/) {
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = (((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) >> 8) & 0x7f);
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = ((msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9) & 0xff);
+ msi_pmch_stop = (msi_pmch_stop <=cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9 ? msi_pmch_stop: cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9);
+ }else{
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB = 0x7; // last subframeP of this mtch (only one mtch now)
+ ((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB = 0xFF;
+ msi_pmch_stop=0;
+ }
+ LOG_I(MAC,"frameP %d, subframeP %d LCID %d rlc_status.bytes_in_buffer %d stop_sf_LSB %d stop_sf_MSB %d msi_pmch_stop %d sf_AllocEnd_r9 %ld, msi_length %d\n",frameP,subframeP,((MSI_ELEMENT *) msi_ptr)->lcid,rlc_status.bytes_in_buffer,((MSI_ELEMENT *) msi_ptr)->stop_sf_LSB,((MSI_ELEMENT *) msi_ptr)->stop_sf_MSB, msi_pmch_stop,cc->pmch_Config[mbms_mch_i]->sf_AllocEnd_r9, msi_length);
+ }
+ memcpy((char*)buffer_pointer,
+ msi_control_element, msi_length);
}
- LOG_D(MAC,
- "e-MBMS log channel %u frameP %d, subframeP %d, rlc_status.bytes_in_buffer is %d TBS_MTCH %d pmch_stop %d msi_sfs %d\n",
+ LOG_D(MAC, "e-MBMS log channel %u frameP %d, subframeP %d, rlc_status.bytes_in_buffer is %d TBS_MTCH %d pmch_stop %d msi_sfs %d\n",
MTCH, frameP, subframeP, rlc_status.bytes_in_buffer,TBS_MTCH,msi_pmch_stop,msi_sfs);
- if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) && ((msi_flag!=1 || mcch_flag!=1)) /*|| (rlc_status.bytes_in_buffer > 0 && (msi_flag==1 || mcch_flag==1))*//*|| msi_sfs > cc->pmch_Config[0]->sf_AllocEnd_r9 */ /*msi_pmch_stop>=num_sf_alloc*/ ) {
- //if(rlc_status.bytes_in_buffer > 0){
- LOG_D(MAC,
- "[eNB %d][MBMS USER-PLANE], CC_id %d, Frame %d, MTCH->MCH, Requesting %d bytes from RLC (header len mtch %d) rlc_status.bytes_in_buffer %d\n",
- module_idP, CC_id, frameP,
+ //TODO not sure whether msi and mch MCH should be precluded ... keep in mind this konditions just in case if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) && ((msi_flag!=1 || mcch_flag!=1))
+ if ((rlc_status.bytes_in_buffer > 0 && msi_pmch_stop > 0) /*&& ((msi_flag!=1 || mcch_flag!=1))*/ /*|| (rlc_status.bytes_in_buffer > 0 && (msi_flag==1 || mcch_flag==1))*//*|| msi_sfs > cc->pmch_Config[0]->sf_AllocEnd_r9 */ /*msi_pmch_stop>=num_sf_alloc*/ ) {
+ LOG_I(MAC,"[eNB %d][MBMS USER-PLANE], CC_id %d, Frame %d, Subframe %d MTCH->MCH, Requesting %d bytes from RLC (header len mtch %d) rlc_status.bytes_in_buffer %d, LCID %ld\n",
+ module_idP, CC_id, frameP, subframeP,
TBS - header_len_mcch - header_len_msi -
- sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer);
+ sdu_length_total - header_len_mtch, header_len_mtch, rlc_status.bytes_in_buffer,cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9);
- sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9,
+ sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP, 0xfffd, module_idP, frameP, ENB_FLAG_YES, MBMS_FLAG_YES,cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9,
TBS - header_len_mcch - header_len_msi - sdu_length_total - header_len_mtch,
(char *)
&mch_buffer[sdu_length_total]
,0,
0
);
-
- // LOG_I(MAC,"RLC %x:",(unsigned char)mch_buffer[sdu_length_total]);
- // for (int kk = 7; kk >= 0; kk--)
- // {
- // printf("%d",(((unsigned char)mch_buffer[sdu_length_total]) >> kk) & 1 ? '1' : '0');
- // }
- // printf("\n");
-
- //sdu_lengths[num_sdus] = mac_rlc_data_req(module_idP,frameP, MBMS_FLAG_NO, MTCH+(MAX_NUM_RB*(MAX_MOBILES_PER_ENB+1)), (char*)&mch_buffer[sdu_length_total]);
- LOG_D(MAC,
- "[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_sfs %d sdu_lengths[num_sdus] %d\n",
+ LOG_D(MAC,"[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_sfs %d sdu_lengths[num_sdus] %d\n",
module_idP, CC_id, sdu_lengths[num_sdus], MTCH,msi_pmch_stop,msi_sfs, sdu_lengths[num_sdus]);
+
cc->mtch_active = 1;
- sdu_lcids[num_sdus] = cc->mbms_SessionList[0]->list.array[0]->logicalChannelIdentity_r9/*MTCH*/;
+
+ sdu_lcids[num_sdus] = cc->mbms_SessionList[mbms_mch_i]->list.array[0]->logicalChannelIdentity_r9/*MTCH*/;
sdu_length_total += sdu_lengths[num_sdus];
if (msi_pmch_stop != 0 && msi_flag !=1)
msi_pmch_stop--;
-
if (sdu_lengths[num_sdus] < 128) {
header_len_mtch = 2;
}
num_sdus++;
- //}
}
else {
- // LOG_E(MAC,
- // "[eNB %d][MBMS USER-PLANE] CC_id %d Got %d bytes for MTCH %d msi_pmch_stop %d msi_buffer %d msi_sfs %ld msi_buffer_act %ld sdu_lengths[num_sdus] %d\n",
- // module_idP, CC_id, sdu_lengths[num_sdus], MTCH,msi_pmch_stop,msi_sfs,msi_buffer_act, sdu_lengths[num_sdus]);
-
header_len_mtch = 0;
}
}
- // }
// FINAL STEP: Prepare and multiplexe MSI, MCCH and MTCHs
- if ((sdu_length_total + header_len_msi + header_len_mcch +
- header_len_mtch) > 0) {
+ if ((sdu_length_total + header_len_msi + header_len_mcch + header_len_mtch) > 0) {
+
// Adjust the last subheader
- /* if ((msi_flag==1) || (mcch_flag==1)) {
- RC.mac[module_idP]->MCH_pdu.mcs = mcch_mcs;
- }
- else if (mtch_flag == 1) { // only MTCH in this subframeP
- RC.mac[module_idP]->MCH_pdu.mcs = RC.mac[module_idP]->pmch_Config[0]->dataMCS_r9;
- }
- */
header_len_mtch_temp = header_len_mtch;
header_len_mcch_temp = header_len_mcch;
header_len_msi_temp = header_len_msi;
@@ -881,12 +1026,10 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
cc->MCH_pdu.msi_active = cc->msi_active;
cc->MCH_pdu.mcch_active = cc->mcch_active;
cc->MCH_pdu.mtch_active = cc->mtch_active;
- LOG_D(MAC,
- " MCS for this sf is %d (mcch active %d, mtch active %d)\n",
+ LOG_D(MAC, " MCS for this sf is %d (mcch active %d, mtch active %d)\n",
cc->MCH_pdu.mcs, cc->MCH_pdu.mcch_active,
cc->MCH_pdu.mtch_active);
- LOG_D(MAC,
- "[eNB %d][MBMS USER-PLANE ] CC_id %d Generate header : sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,padding %d,post_padding %d (mcs %d, TBS %d), header MTCH %d, header MCCH %d, header MSI %d\n",
+ LOG_D(MAC, "[eNB %d][MBMS USER-PLANE ] CC_id %d Generate header : sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d,padding %d,post_padding %d (mcs %d, TBS %d), header MTCH %d, header MCCH %d, header MSI %d\n",
module_idP, CC_id, sdu_length_total, num_sdus,
sdu_lengths[0], sdu_lcids[0], offset, padding, post_padding,
cc->MCH_pdu.mcs, TBS, header_len_mtch, header_len_mcch,
@@ -902,20 +1045,15 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
/* Tracing of PDU is done on UE side */
//if (opt_enabled == 1) {
- trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) cc->MCH_pdu.payload, TBS, module_idP, WS_M_RNTI , 0xfffd, // M_RNTI = 6 in wirehsark
- RC.mac[module_idP]->frame,
- RC.mac[module_idP]->subframe, 0, 0);
- LOG_D(OPT,
- "[eNB %d][MCH] CC_id %d Frame %d : MAC PDU with size %d\n",
+ trace_pdu(DIRECTION_DOWNLINK, (uint8_t *) cc->MCH_pdu.payload, TBS, module_idP, WS_M_RNTI , 0xfffd, // M_RNTI = 6 in wirehsark
+ RC.mac[module_idP]->frame,
+ RC.mac[module_idP]->subframe, 0, 0);
+ LOG_D(OPT, "[eNB %d][MCH] CC_id %d Frame %d : MAC PDU with size %d\n",
module_idP, CC_id, frameP, TBS);
//}
eNB_MAC_INST *eNB = RC.mac[module_idP];
dl_req = &eNB->DL_req[CC_id].dl_config_request_body;
- // dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
- // memset((void *) dl_config_pdu,
- // 0,
- // sizeof(nfapi_dl_config_request_pdu_t));
dl_req->tl.tag = NFAPI_DL_CONFIG_REQUEST_BODY_TAG;
fill_nfapi_mch_config(
dl_req,
@@ -934,12 +1072,6 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
TBS,
eNB->pdu_index[CC_id],
(uint8_t*)cc->MCH_pdu.payload);
-
-
- /*
- for (j=0;j<sdu_length_total;j++)
- printf("%2x.",RC.mac[module_idP]->MCH_pdu.payload[j+offset]);
- printf(" \n"); */
return 1;
} else {
cc->MCH_pdu.Pdu_size = 0;
@@ -947,21 +1079,8 @@ schedule_MBMS_NFAPI(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
cc->MCH_pdu.msi_active = 0;
cc->MCH_pdu.mcch_active = 0;
cc->MCH_pdu.mtch_active = 0;
- // for testing purpose, fill with random data
- //for (j=0;j<(TBS-sdu_length_total-offset);j++)
- // RC.mac[module_idP]->MCH_pdu.payload[offset+sdu_length_total+j] = (char)(taus()&0xff);
return 0;
}
-
- //this is for testing
- /*
- if (mtch_flag == 1) {
- // LOG_D(MAC,"DUY: mch_buffer length so far is : %ld\n", &mch_buffer[sdu_length_total]-&mch_buffer[0]);
- return 1;
- }
- else
- return 0;
- */
}
int
schedule_MBMS(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c
index 78d6f6a3d76574d1b8ab70d96184b5e5297095c0..89c2ecc83d28bb9f04d06e57f7c31ec9c15a4268 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_primitives.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_primitives.c
@@ -2131,33 +2131,36 @@ dump_ue_list(UE_list_t *listP) {
* Add a UE to UE_list listP
*/
inline void add_ue_list(UE_list_t *listP, int UE_id) {
- if (listP->head == -1) {
- listP->head = UE_id;
- listP->next[UE_id] = -1;
- } else {
- int i = listP->head;
- while (listP->next[i] >= 0)
- i = listP->next[i];
- listP->next[i] = UE_id;
- listP->next[UE_id] = -1;
- }
+ int *cur = &listP->head;
+ while (*cur >= 0)
+ cur = &listP->next[*cur];
+ *cur = UE_id;
}
//------------------------------------------------------------------------------
/*
- * Remove a UE from the UE_list listP, return the previous element
+ * Remove a UE from the UE_list listP
*/
inline int remove_ue_list(UE_list_t *listP, int UE_id) {
- listP->next[UE_id] = -1;
- if (listP->head == UE_id) {
- listP->head = listP->next[UE_id];
- return -1;
- }
+ int *cur = &listP->head;
+ while (*cur != -1 && *cur != UE_id)
+ cur = &listP->next[*cur];
+ if (*cur == -1)
+ return 0;
+ int *next = &listP->next[*cur];
+ *cur = listP->next[*cur];
+ *next = -1;
+ return 1;
+}
- int previous = prev(listP, UE_id);
- if (previous != -1)
- listP->next[previous] = listP->next[UE_id];
- return previous;
+//------------------------------------------------------------------------------
+/*
+ * Initialize the UE_list listP
+ */
+inline void init_ue_list(UE_list_t *listP) {
+ listP->head = -1;
+ for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
+ listP->next[i] = -1;
}
//------------------------------------------------------------------------------
@@ -2196,6 +2199,12 @@ add_new_ue(module_id_t mod_idP,
UE_info->active[UE_id] = TRUE;
add_ue_list(&UE_info->list, UE_id);
dump_ue_list(&UE_info->list);
+ pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl;
+ if (dl->slices) // inform slice implementation about new UE
+ dl->add_UE(dl->slices, UE_id);
+ pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul;
+ if (ul->slices) // inform slice implementation about new UE
+ ul->add_UE(ul->slices, UE_id);
if (IS_SOFTMODEM_IQPLAYER)// not specific to record/playback ?
UE_info->UE_template[cc_idP][UE_id].pre_assigned_mcs_ul = 0;
UE_info->UE_template[cc_idP][UE_id].rach_resource_type = rach_resource_type;
@@ -2259,6 +2268,12 @@ rrc_mac_remove_ue(module_id_t mod_idP,
UE_info->num_UEs--;
remove_ue_list(&UE_info->list, UE_id);
+ pp_impl_param_t* dl = &RC.mac[mod_idP]->pre_processor_dl;
+ if (dl->slices) // inform slice implementation about new UE
+ dl->remove_UE(dl->slices, UE_id);
+ pp_impl_param_t* ul = &RC.mac[mod_idP]->pre_processor_ul;
+ if (ul->slices) // inform slice implementation about new UE
+ ul->remove_UE(ul->slices, UE_id);
/* Clear all remaining pending transmissions */
memset(&UE_info->UE_template[pCC_id][UE_id], 0, sizeof(UE_TEMPLATE));
diff --git a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
index 3062e5c9647826af5fe547d5fa7a06c7f6707004..2de45db8565e47aacecbee004b0a315fdec903df 100644
--- a/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+++ b/openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
@@ -1301,11 +1301,11 @@ schedule_ulsch_rnti(module_id_t module_idP,
/*
* ULSCH preprocessor: set UE_template->
- * pre_allocated_nb_rb_ul[slice_idx]
+ * pre_allocated_nb_rb_ul
* pre_assigned_mcs_ul
* pre_allocated_rb_table_index_ul
*/
- ulsch_scheduler_pre_processor(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP);
+ mac->pre_processor_ul.ul(module_idP, CC_id, frameP, subframeP, sched_frame, sched_subframeP);
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
if (UE_info->UE_template[CC_id][UE_id].rach_resource_type > 0)
diff --git a/openair2/LAYER2/MAC/mac.h b/openair2/LAYER2/MAC/mac.h
index 329e262c828e1008c4f74c712f91684ac1ec0ce4..7eccc6222d42718e67dcce60f5bf9ee18ed36ff9 100644
--- a/openair2/LAYER2/MAC/mac.h
+++ b/openair2/LAYER2/MAC/mac.h
@@ -56,6 +56,7 @@
#include "LTE_MobilityControlInfo.h"
#include "LTE_MBSFN-AreaInfoList-r9.h"
#include "LTE_MBSFN-SubframeConfigList.h"
+#include "LTE_MBSFNAreaConfiguration-r9.h"
#include "LTE_PMCH-InfoList-r9.h"
#include "LTE_SCellToAddMod-r10.h"
#include "LTE_SystemInformationBlockType1-v1310-IEs.h"
@@ -155,9 +156,6 @@
/*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */
#define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE)
-/*!\brief maximum number of slices / groups */
-#define MAX_NUM_SLICES 10
-
#define U_PLANE_INACTIVITY_VALUE 0 /* defined 10ms order (zero means infinity) */
@@ -412,9 +410,11 @@ typedef struct {
/*!\brief Values of BCCH SIB_BR logical channel (fake) */
#define BCCH_SI_BR 7 // SI-BR
/*!\brief Values of BCCH SIB1_MBMS logical channel (fake) */
-#define BCCH_SIB1_MBMS 60 // SIB1_MBMS //TODO better armonize index
+#define MIBCH_MBMS 10 // SIB1_MBMS //TODO better armonize index
+#define BCCH_SIB1_MBMS 12 // SIB1_MBMS //TODO better armonize index
/*!\brief Values of BCCH SI_MBMS logical channel (fake) */
-#define BCCH_SI_MBMS 61 // SIB_MBMS //TODO better armonize index
+#define BCCH_SI_MBMS 13 // SIB_MBMS //TODO better armonize index
+#define MCCH_COUNTING 14
/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0 // srb0
/*!\brief DCCH / SRB1 logical channel */
@@ -543,7 +543,6 @@ typedef enum {
SCHED_MODE_FAIR_RR /// fair raund robin
} SCHEDULER_MODES;
-
/*! \brief temporary struct for ULSCH sched */
typedef struct {
rnti_t rnti;
@@ -1150,9 +1149,6 @@ typedef struct {
UE_list_t list;
int num_UEs;
boolean_t active[MAX_MOBILES_PER_ENB];
-
- /// Sorting criteria for the UE list in the MAC preprocessor
- uint16_t sorting_criteria[MAX_NUM_SLICES][CR_NUM];
} UE_info_t;
/*! \brief deleting control information*/
@@ -1172,107 +1168,88 @@ typedef struct {
} UE_free_list_t;
/**
- * slice specific scheduler for the DL
+ * describes contiguous RBs
*/
-typedef void (*slice_scheduler_dl)(module_id_t mod_id,
- int slice_idx,
- frame_t frame,
- sub_frame_t subframe,
- int *mbsfn_flag);
-
-typedef struct {
- slice_id_t id;
-
- /// RB share for each slice
- float pct;
-
- /// whether this slice is isolated from the others
- int isol;
-
- int prio;
-
- /// Frequency ranges for slice positioning
- int pos_low;
- int pos_high;
-
- // max mcs for each slice
- int maxmcs;
-
- /// criteria for sorting policies of the slices
- uint32_t sorting;
-
- /// Accounting policy (just greedy(1) or fair(0) setting for now)
- int accounting;
-
- /// name of available scheduler
- char *sched_name;
-
- /// pointer to the slice specific scheduler in DL
- slice_scheduler_dl sched_cb;
-
-} slice_sched_conf_dl_t;
-
-typedef void (*slice_scheduler_ul)(module_id_t mod_id,
- int slice_idx,
- frame_t frame,
- sub_frame_t subframe,
- unsigned char sched_subframe,
- uint16_t *first_rb);
-
typedef struct {
- slice_id_t id;
-
- /// RB share for each slice
- float pct;
-
- // MAX MCS for each slice
- int maxmcs;
-
- /// criteria for sorting policies of the slices
- uint32_t sorting;
-
- /// starting RB (RB offset) of UL scheduling
- int first_rb;
-
- /// name of available scheduler
- char *sched_name;
-
- /// pointer to the slice specific scheduler in UL
- slice_scheduler_ul sched_cb;
-
-} slice_sched_conf_ul_t;
-
+ int start;
+ int length;
+} contig_rbs_t;
+/**
+ * definition of a scheduling algorithm implementation used in the
+ * default DL scheduler
+ */
typedef struct {
- /// counter used to indicate when all slices have pre-allocated UEs
- //int slice_counter;
-
- /// indicates whether remaining RBs after first intra-slice allocation will
- /// be allocated to UEs of the same slice
- int intraslice_share_active;
- /// indicates whether remaining RBs after slice allocation will be
- /// allocated to UEs of another slice. Isolated slices will be ignored
- int interslice_share_active;
-
- /// number of active DL slices
- int n_dl;
- slice_sched_conf_dl_t dl[MAX_NUM_SLICES];
-
- /// number of active UL slices
- int n_ul;
- slice_sched_conf_ul_t ul[MAX_NUM_SLICES];
-
- /// common rb allocation list between slices
- uint8_t rballoc_sub[NFAPI_CC_MAX][N_RBG_MAX];
-} slice_info_t;
+ char *name;
+ void *(*setup)(void);
+ void (*unset)(void **);
+ int (*run)(
+ module_id_t, int, int, int, UE_list_t *, int, int, uint8_t *, void *);
+ void *data;
+} default_sched_dl_algo_t;
/**
- * describes contiguous RBs
+ * definition of a scheduling algorithm implementation used in the
+ * default UL scheduler
*/
typedef struct {
- int start;
- int length;
-} contig_rbs_t;
+ char *name;
+ void *(*setup)(void);
+ void (*unset)(void **);
+ int (*run)(
+ module_id_t, int, int, int, int, int, UE_list_t *, int, int, contig_rbs_t *, void *);
+ void *data;
+} default_sched_ul_algo_t;
+
+typedef void (*pp_impl_dl)(module_id_t mod_id,
+ int CC_id,
+ frame_t frame,
+ sub_frame_t subframe);
+typedef void (*pp_impl_ul)(module_id_t mod_id,
+ int CC_id,
+ frame_t frame,
+ sub_frame_t subframe,
+ frame_t sched_frame,
+ sub_frame_t sched_subframe);
+
+struct slice_info_s;
+typedef struct {
+ int algorithm;
+
+ /// inform the slice algorithm about a new UE
+ void (*add_UE)(struct slice_info_s *s, int UE_id);
+ /// inform the slice algorithm about a UE that disconnected
+ void (*remove_UE)(struct slice_info_s *s, int UE_id);
+ /// move a UE to a slice in DL/UL, -1 means don't move (no-op).
+ void (*move_UE)(struct slice_info_s *s, int UE_id, int idx);
+
+ /// Adds a new slice through admission control. slice_params are
+ /// algorithm-specific parameters. sched is either a default_sched_ul_algo_t
+ /// or default_sched_dl_algo_t, depending on whether this implementation
+ /// handles UL/DL. If slice at index exists, updates existing
+ /// slice. Returns index of new slice or -1 on failure.
+ int (*addmod_slice)(struct slice_info_s *s,
+ int id,
+ char *label,
+ void *sched,
+ void *slice_params);
+ /// Returns slice through slice_idx. 1 if successful, 0 if not.
+ int (*remove_slice)(struct slice_info_s *s, uint8_t slice_idx);
+
+ union {
+ pp_impl_dl dl;
+ pp_impl_ul ul;
+ };
+
+ union {
+ default_sched_ul_algo_t ul_algo;
+ default_sched_dl_algo_t dl_algo;
+ };
+
+ void (*destroy)(struct slice_info_s **s);
+
+ struct slice_info_s *slices;
+} pp_impl_param_t;
/*! \brief eNB common channels */
typedef struct {
@@ -1312,6 +1289,8 @@ typedef struct {
/// MBSFN SubframeConfig
struct LTE_MBSFN_SubframeConfig *mbsfn_SubframeConfig[8];
struct LTE_NonMBSFN_SubframeConfig_r14 *non_mbsfn_SubframeConfig;
+ struct LTE_MBSFN_SubframeConfig *commonSF_Alloc_r9_mbsfn_SubframeConfig[8]; // FIXME replace 8 by MAX_MBSFN_AREA?
+ uint8_t commonSF_AllocPeriod_r9;
/// number of subframe allocation pattern available for MBSFN sync area
uint8_t num_sf_allocation_pattern;
/// MBMS Flag
@@ -1395,9 +1374,6 @@ typedef struct eNB_MAC_INST_s {
uint32_t ul_handle;
UE_info_t UE_info;
- /// slice-related configuration
- slice_info_t slice_info;
-
///subband bitmap configuration
SBMAP_CONF sbmap_conf;
/// CCE table used to build DCI scheduling information
@@ -1432,6 +1408,11 @@ typedef struct eNB_MAC_INST_s {
UE_free_list_t UE_free_list;
/// for scheduling selection
SCHEDULER_MODES scheduler_mode;
+ /// Default scheduler: Pre-processor implementation. Algorithms for UL/DL
+ /// are called by ULSCH/DLSCH, respectively. Pro-processor implementation can
+ /// encapsulate slicing.
+ pp_impl_param_t pre_processor_dl;
+ pp_impl_param_t pre_processor_ul;
int32_t puSch10xSnr;
int32_t puCch10xSnr;
diff --git a/openair2/LAYER2/MAC/mac_extern.h b/openair2/LAYER2/MAC/mac_extern.h
index dbf5b57b6b28cdd095fb2094afbc7b55f5e732f0..cee6066a9ebb174119b3fe6b22ce4ed6c9ae738a 100644
--- a/openair2/LAYER2/MAC/mac_extern.h
+++ b/openair2/LAYER2/MAC/mac_extern.h
@@ -60,7 +60,7 @@ extern uint16_t NB_THREAD_INST;
extern unsigned char NB_RN_INST;
extern unsigned short NODE_ID[1];
-extern int cqi_to_mcs[16];
+extern const int cqi_to_mcs[16];
extern uint32_t RRC_CONNECTION_FLAG;
diff --git a/openair2/LAYER2/MAC/mac_proto.h b/openair2/LAYER2/MAC/mac_proto.h
index 2cb86c25af221c003757dc961f51a8b7eea9c5f0..b92ce85608fa726952fad9574589ac1ef3dde6e1 100644
--- a/openair2/LAYER2/MAC/mac_proto.h
+++ b/openair2/LAYER2/MAC/mac_proto.h
@@ -33,6 +33,16 @@
#include "PHY/defs_common.h" // for PRACH_RESOURCES_t and lte_subframe_t
#include "openair2/COMMON/mac_messages_types.h"
+/** \fn void schedule_fembms_mib(module_id_t module_idP,frame_t frameP,sub_frame_t subframe);
+\brief MIB scheduling for PBCH. This function requests the MIB from RRC and provides it to L1.
+@param Mod_id Instance ID of eNB
+@param frame Frame index
+@param subframe Subframe number on which to act
+
+*/
+
+void schedule_fembms_mib(module_id_t module_idP,
+ frame_t frameP, sub_frame_t subframeP);
/** \addtogroup _mac
* @{
@@ -187,8 +197,6 @@ void add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP,
void init_UE_info(UE_info_t *UE_info);
-void init_slice_info(slice_info_t *sli);
-
int mac_top_init(int eMBMS_active, char *uecap_xer,
uint8_t cba_group_active, uint8_t HO_active);
@@ -534,6 +542,10 @@ int ue_query_mch(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
sub_frame_t subframe, uint8_t eNB_index,
uint8_t *sync_area, uint8_t *mcch_active);
+int ue_query_mch_fembms(module_id_t Mod_id, uint8_t CC_id, uint32_t frame,
+ sub_frame_t subframe, uint8_t eNB_index,
+ uint8_t * sync_area, uint8_t * mcch_active);
+
/* \brief Called by PHY to get sdu for PUSCH transmission. It performs the following operations: Checks BSR for DCCH, DCCH1 and DTCH corresponding to previous values computed either in SR or BSR procedures. It gets rlc status indications on DCCH,DCCH1 and DTCH and forms BSR elements and PHR in MAC header. CRNTI element is not supported yet. It computes transport block for up to 3 SDUs and generates header and forms the complete MAC SDU.
@param Mod_id Instance id of UE in machine
@@ -661,6 +673,7 @@ int prev(UE_list_t *listP, int nodeP);
void add_ue_list(UE_list_t *listP, int UE_id);
int remove_ue_list(UE_list_t *listP, int UE_id);
void dump_ue_list(UE_list_t *listP);
+void init_ue_list(UE_list_t *listP);
int UE_num_active_CC(UE_info_t *listP, int ue_idP);
int UE_PCCID(module_id_t mod_idP, int ue_idP);
rnti_t UE_RNTI(module_id_t mod_idP, int ue_idP);
@@ -675,10 +688,10 @@ void set_ul_DAI(int module_idP,
void ulsch_scheduler_pre_processor(module_id_t module_idP,
int CC_id,
- int frameP,
+ frame_t frameP,
sub_frame_t subframeP,
- int sched_frameP,
- unsigned char sched_subframeP);
+ frame_t sched_frameP,
+ sub_frame_t sched_subframeP);
int phy_stats_exist(module_id_t Mod_id, int rnti);
@@ -900,6 +913,7 @@ int generate_dlsch_header(unsigned char *mac_header,
@param non_MBSFN_SubframeConfig pointer to FeMBMS Non MBSFN Subframe Config
@param sib1_mbms_r14_fembms pointer SI Scheduling infomration for SI-MBMS
@param mbsfn_AreaInfoList_fembms pointer to FeMBMS MBSFN Area Info list from SIB1-MBMS
+@param mbms_AreaConfiguration pointer to eMBMS MBSFN Area Configuration
*/
int rrc_mac_config_req_eNB(module_id_t module_idP,
@@ -936,7 +950,8 @@ int rrc_mac_config_req_eNB(module_id_t module_idP,
LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo_fembms,
struct LTE_NonMBSFN_SubframeConfig_r14 *nonMBSFN_SubframeConfig,
LTE_SystemInformationBlockType1_MBMS_r14_t *sib1_mbms_r14_fembms,
- LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms
+ LTE_MBSFN_AreaInfoList_r9_t *mbsfn_AreaInfoList_fembms,
+ LTE_MBSFNAreaConfiguration_r9_t * mbms_AreaConfiguration
);
/** \brief RRC eNB Configuration primitive for PHY/MAC. Allows configuration of PHY/MAC resources based on System Information (SI), RRCConnectionSetup and RRCConnectionReconfiguration messages.
diff --git a/openair2/LAYER2/MAC/main.c b/openair2/LAYER2/MAC/main.c
index 1a88623a1f3d31396cc362dbaff22a65caa279ea..af6d1a7ac355b8fe4182c48bfde08ce53445566d 100644
--- a/openair2/LAYER2/MAC/main.c
+++ b/openair2/LAYER2/MAC/main.c
@@ -45,11 +45,8 @@ extern RAN_CONTEXT_t RC;
void init_UE_info(UE_info_t *UE_info)
{
- int list_el;
UE_info->num_UEs = 0;
- UE_info->list.head = -1;
- for (list_el = 0; list_el < MAX_MOBILES_PER_ENB; list_el++)
- UE_info->list.next[list_el] = -1;
+ init_ue_list(&UE_info->list);
memset(UE_info->DLSCH_pdu, 0, sizeof(UE_info->DLSCH_pdu));
memset(UE_info->UE_template, 0, sizeof(UE_info->UE_template));
memset(UE_info->eNB_UE_stats, 0, sizeof(UE_info->eNB_UE_stats));
@@ -57,32 +54,6 @@ void init_UE_info(UE_info_t *UE_info)
memset(UE_info->active, 0, sizeof(UE_info->active));
}
-void init_slice_info(slice_info_t *sli)
-{
- sli->intraslice_share_active = 1;
- sli->interslice_share_active = 1;
-
- sli->n_dl = 1;
- memset(sli->dl, 0, sizeof(slice_sched_conf_dl_t) * MAX_NUM_SLICES);
- sli->dl[0].pct = 1.0;
- sli->dl[0].prio = 10;
- sli->dl[0].pos_high = N_RBG_MAX;
- sli->dl[0].maxmcs = 28;
- sli->dl[0].sorting = 0x012345;
- sli->dl[0].sched_name = "schedule_ue_spec";
- sli->dl[0].sched_cb = dlsym(NULL, sli->dl[0].sched_name);
- AssertFatal(sli->dl[0].sched_cb, "DLSCH scheduler callback is NULL\n");
-
- sli->n_ul = 1;
- memset(sli->ul, 0, sizeof(slice_sched_conf_ul_t) * MAX_NUM_SLICES);
- sli->ul[0].pct = 1.0;
- sli->ul[0].maxmcs = 20;
- sli->ul[0].sorting = 0x0123;
- sli->ul[0].sched_name = "schedule_ulsch_rnti";
- sli->ul[0].sched_cb = dlsym(NULL, sli->ul[0].sched_name);
- AssertFatal(sli->ul[0].sched_cb, "ULSCH scheduler callback is NULL\n");
-}
-
void mac_top_init_eNB(void)
{
module_id_t i, j;
@@ -129,8 +100,23 @@ void mac_top_init_eNB(void)
mac[i]->if_inst = IF_Module_init(i);
+ mac[i]->pre_processor_dl.algorithm = 0;
+ mac[i]->pre_processor_dl.dl = dlsch_scheduler_pre_processor;
+ char *s = "round_robin_dl";
+ void *d = dlsym(NULL, s);
+ AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s);
+ mac[i]->pre_processor_dl.dl_algo = *(default_sched_dl_algo_t *) d;
+ mac[i]->pre_processor_dl.dl_algo.data = mac[i]->pre_processor_dl.dl_algo.setup();
+
+ mac[i]->pre_processor_ul.algorithm = 0;
+ mac[i]->pre_processor_ul.ul = ulsch_scheduler_pre_processor;
+ s = "round_robin_ul";
+ d = dlsym(NULL, s);
+ AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s);
+ mac[i]->pre_processor_ul.ul_algo = *(default_sched_ul_algo_t *) d;
+ mac[i]->pre_processor_ul.ul_algo.data = mac[i]->pre_processor_ul.ul_algo.setup();
+
init_UE_info(&mac[i]->UE_info);
- init_slice_info(&mac[i]->slice_info);
}
RC.mac = mac;
diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c
index c4dd6b841966d8d902d40bc95a7d78359eb4b961..6477d600215f5c75d5e23c5e6385078be4188fc3 100644
--- a/openair2/LAYER2/MAC/pre_processor.c
+++ b/openair2/LAYER2/MAC/pre_processor.c
@@ -36,6 +36,7 @@
#include "LAYER2/MAC/mac.h"
#include "LAYER2/MAC/mac_proto.h"
#include "LAYER2/MAC/mac_extern.h"
+#include <openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h>
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "UTIL/OPT/opt.h"
@@ -68,32 +69,47 @@ int get_rbg_size_last(module_id_t Mod_id, int CC_id) {
return RBGsize;
}
-int g_start_ue_dl = -1;
-int round_robin_dl(module_id_t Mod_id,
- int CC_id,
- int frame,
- int subframe,
- UE_list_t *UE_list,
- int max_num_ue,
- int n_rbg_sched,
- uint8_t *rbgalloc_mask) {
+void *rr_dl_setup(void) {
+ void *data = malloc(sizeof(int));
+ *(int *) data = 0;
+ AssertFatal(data, "could not allocate data in %s()\n", __func__);
+ return data;
+}
+void rr_dl_unset(void **data) {
+ if (*data)
+ free(*data);
+ *data = NULL;
+}
+int rr_dl_run(module_id_t Mod_id,
+ int CC_id,
+ int frame,
+ int subframe,
+ UE_list_t *UE_list,
+ int max_num_ue,
+ int n_rbg_sched,
+ uint8_t *rbgalloc_mask,
+ void *data) {
DevAssert(UE_list->head >= 0);
DevAssert(n_rbg_sched > 0);
const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth);
const int RBGsize = get_min_rb_unit(Mod_id, CC_id);
const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id);
- int num_ue_req = 0;
UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
- int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request
- memset(rb_required, 0, sizeof(rb_required));
-
int rbg = 0;
for (; !rbgalloc_mask[rbg]; rbg++)
; /* fast-forward to first allowed RBG */
- // Calculate the amount of RBs every UE wants to send.
- for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
+ /* just start with the UE after the one we had last time. If it does not
+ * exist, this will start at the head */
+ int *start_ue = data;
+ *start_ue = next_ue_list_looped(UE_list, *start_ue);
+
+ int UE_id = *start_ue;
+ UE_list_t UE_sched;
+ int *cur_UE = &UE_sched.head;
+ // Allocate retransmissions, and mark UEs with new transmissions
+ do {
// check whether there are HARQ retransmissions
const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id];
const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe);
@@ -102,14 +118,14 @@ int round_robin_dl(module_id_t Mod_id,
if (round != 8) { // retransmission: allocate
const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid];
if (nb_rb == 0)
- continue;
+ goto skip_ue;
int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize;
// needs more RBGs than we can allocate
if (nb_rbg > n_rbg_sched) {
LOG_D(MAC,
"retransmission of UE %d needs more RBGs (%d) than we have (%d)\n",
UE_id, nb_rbg, n_rbg_sched);
- continue;
+ goto skip_ue;
}
// ensure that the number of RBs can be contained by the RBGs (!), i.e.
// if we allocate the last RBG this one should have the full RBGsize
@@ -118,12 +134,12 @@ int round_robin_dl(module_id_t Mod_id,
LOG_D(MAC,
"retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n",
UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize);
- continue;
+ goto skip_ue;
}
const uint8_t cqi = ue_ctrl->dl_cqi[CC_id];
const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
if (idx < 0)
- continue; // cannot allocate CCE
+ goto skip_ue; // cannot allocate CCE
ue_ctrl->pre_dci_dl_pdu_idx = idx;
// retransmissions: directly allocate
n_rbg_sched -= nb_rbg;
@@ -132,6 +148,7 @@ int round_robin_dl(module_id_t Mod_id,
if (!rbgalloc_mask[rbg])
continue;
ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
nb_rbg--;
}
LOG_D(MAC,
@@ -149,90 +166,390 @@ int round_robin_dl(module_id_t Mod_id,
return n_rbg_sched;
for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
} else {
- const int dlsch_mcs1 = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]];
- UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = dlsch_mcs1;
- rb_required[UE_id] =
- find_nb_rb_DL(dlsch_mcs1,
- UE_info->UE_template[CC_id][UE_id].dl_buffer_total,
- n_rbg_sched * RBGsize,
- RBGsize);
- if (rb_required[UE_id] > 0)
- num_ue_req++;
- LOG_D(MAC,
- "%d/%d UE_id %d rb_required %d n_rbg_sched %d\n",
- frame,
- subframe,
- UE_id,
- rb_required[UE_id],
- n_rbg_sched);
+ if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total > 0) {
+ *cur_UE = UE_id;
+ cur_UE = &UE_sched.next[UE_id];
+ }
}
- }
- if (num_ue_req == 0)
+skip_ue:
+ UE_id = next_ue_list_looped(UE_list, UE_id);
+ } while (UE_id != *start_ue);
+ *cur_UE = -1; // mark end
+
+ if (UE_sched.head < 0)
return n_rbg_sched; // no UE has a transmission
- // after allocating retransmissions: build list of UE to allocate.
- // if start_UE does not exist anymore (detach etc), start at first UE
- if (g_start_ue_dl == -1)
- g_start_ue_dl = UE_list->head;
- int UE_id = g_start_ue_dl;
- UE_list_t UE_sched;
- int rb_required_total = 0;
- int num_ue_sched = 0;
- max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched);
- int *cur_UE = &UE_sched.head;
- while (num_ue_sched < max_num_ue) {
- while (rb_required[UE_id] == 0)
- UE_id = next_ue_list_looped(UE_list, UE_id);
+ // after allocating retransmissions: pre-allocate CCE, compute number of
+ // requested RBGs
+ max_num_ue = min(max_num_ue, n_rbg_sched);
+ int rb_required[MAX_MOBILES_PER_ENB]; // how much UEs request
+ cur_UE = &UE_sched.head;
+ while (*cur_UE >= 0 && max_num_ue > 0) {
+ const int UE_id = *cur_UE;
+ cur_UE = &UE_sched.next[UE_id]; // go to next
const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
if (idx < 0) {
LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", UE_id);
- num_ue_req--;
- max_num_ue = min(min(max_num_ue, num_ue_req), n_rbg_sched);
- UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate
continue;
}
UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx;
- *cur_UE = UE_id;
- cur_UE = &UE_sched.next[UE_id];
- rb_required_total += rb_required[UE_id];
- num_ue_sched++;
- UE_id = next_ue_list_looped(UE_list, UE_id); // next candidate
+ const int mcs = cqi_to_mcs[cqi];
+ UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs;
+ const uint32_t B = UE_info->UE_template[CC_id][UE_id].dl_buffer_total;
+ rb_required[UE_id] = find_nb_rb_DL(mcs, B, n_rbg_sched * RBGsize, RBGsize);
+ max_num_ue--;
}
- *cur_UE = -1;
+ *cur_UE = -1; // not all UEs might be allocated, mark end
/* for one UE after the next: allocate resources */
- for (int UE_id = UE_sched.head; UE_id >= 0;
- UE_id = next_ue_list_looped(&UE_sched, UE_id)) {
- if (rb_required[UE_id] <= 0)
- continue;
+ cur_UE = &UE_sched.head;
+ while (*cur_UE >= 0) {
+ const int UE_id = *cur_UE;
UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id];
ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize;
ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG;
rb_required[UE_id] -= sRBG;
- rb_required_total -= sRBG;
- if (rb_required_total <= 0)
- break;
+ if (rb_required[UE_id] <= 0) {
+ *cur_UE = UE_sched.next[*cur_UE];
+ if (*cur_UE < 0)
+ cur_UE = &UE_sched.head;
+ } else {
+ cur_UE = UE_sched.next[*cur_UE] < 0 ? &UE_sched.head : &UE_sched.next[*cur_UE];
+ }
n_rbg_sched--;
if (n_rbg_sched <= 0)
break;
for (rbg++; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
}
- /* if not all UEs could be allocated in this round */
- if (num_ue_req > max_num_ue) {
- /* go to the first one we missed */
- for (int i = 0; i < max_num_ue; ++i)
- g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl);
- } else {
- /* else, just start with the next UE next time */
- g_start_ue_dl = next_ue_list_looped(UE_list, g_start_ue_dl);
+ return n_rbg_sched;
+}
+default_sched_dl_algo_t round_robin_dl = {
+ .name = "round_robin_dl",
+ .setup = rr_dl_setup,
+ .unset = rr_dl_unset,
+ .run = rr_dl_run,
+ .data = NULL
+};
+
+
+void *pf_dl_setup(void) {
+ void *data = calloc(MAX_MOBILES_PER_ENB, sizeof(float));
+ for (int i = 0; i < MAX_MOBILES_PER_ENB; i++)
+ *(float *) data = 0.0f;
+ AssertFatal(data, "could not allocate data in %s()\n", __func__);
+ return data;
+}
+void pf_dl_unset(void **data) {
+ if (*data)
+ free(*data);
+ *data = NULL;
+}
+int pf_wbcqi_dl_run(module_id_t Mod_id,
+ int CC_id,
+ int frame,
+ int subframe,
+ UE_list_t *UE_list,
+ int max_num_ue,
+ int n_rbg_sched,
+ uint8_t *rbgalloc_mask,
+ void *data) {
+ DevAssert(UE_list->head >= 0);
+ DevAssert(n_rbg_sched > 0);
+ const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth);
+ const int RBGsize = get_min_rb_unit(Mod_id, CC_id);
+ const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id);
+ UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
+
+ int rbg = 0;
+ for (; !rbgalloc_mask[rbg]; rbg++)
+ ; /* fast-forward to first allowed RBG */
+
+ UE_list_t UE_sched; // UEs that could be scheduled
+ int *uep = &UE_sched.head;
+ float *thr_ue = data;
+ float coeff_ue[MAX_MOBILES_PER_ENB];
+
+ for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
+ const float a = 0.0005f; // corresponds to 200ms window
+ const uint32_t b = UE_info->eNB_UE_stats[CC_id][UE_id].TBS;
+ thr_ue[UE_id] = (1 - a) * thr_ue[UE_id] + a * b;
+
+ // check whether there are HARQ retransmissions
+ const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id];
+ const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe);
+ UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ const uint8_t round = ue_ctrl->round[CC_id][harq_pid];
+ if (round != 8) { // retransmission: allocate
+ const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid];
+ if (nb_rb == 0)
+ continue;
+ int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize;
+ // needs more RBGs than we can allocate
+ if (nb_rbg > n_rbg_sched) {
+ LOG_D(MAC,
+ "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n",
+ UE_id, nb_rbg, n_rbg_sched);
+ continue;
+ }
+ // ensure that the number of RBs can be contained by the RBGs (!), i.e.
+ // if we allocate the last RBG this one should have the full RBGsize
+ if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched
+ && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) {
+ LOG_D(MAC,
+ "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n",
+ UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize);
+ continue;
+ }
+ const uint8_t cqi = ue_ctrl->dl_cqi[CC_id];
+ const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
+ if (idx < 0)
+ continue; // cannot allocate CCE
+ ue_ctrl->pre_dci_dl_pdu_idx = idx;
+ // retransmissions: directly allocate
+ n_rbg_sched -= nb_rbg;
+ ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb;
+ for (; nb_rbg > 0; rbg++) {
+ if (!rbgalloc_mask[rbg])
+ continue;
+ ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
+ nb_rbg--;
+ }
+ LOG_D(MAC,
+ "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d "
+ "round %d retx nb_rb %d pre_nb_available_rbs %d\n",
+ frame, subframe, n_rbg_sched, UE_id, round,
+ UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid],
+ ue_ctrl->pre_nb_available_rbs[CC_id]);
+ /* if there are no more RBG to give, return */
+ if (n_rbg_sched <= 0)
+ return 0;
+ max_num_ue--;
+ /* if there are no UEs that can be allocated anymore, return */
+ if (max_num_ue == 0)
+ return n_rbg_sched;
+ for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
+ } else {
+ if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0)
+ continue;
+
+ const int mcs = cqi_to_mcs[UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id]];
+ const uint32_t tbs = get_TBS_DL(mcs, RBGsize);
+ coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id];
+ //LOG_I(MAC, " pf UE %d: old TBS %d thr %f MCS %d TBS %d coeff %f\n",
+ // UE_id, b, thr_ue[UE_id], mcs, tbs, coeff_ue[UE_id]);
+ *uep = UE_id;
+ uep = &UE_sched.next[UE_id];
+ }
+ }
+ *uep = -1;
+
+ while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) {
+ int *max = &UE_sched.head; /* assume head is max */
+ int *p = &UE_sched.next[*max];
+ while (*p >= 0) {
+ /* if the current one has larger coeff, save for later */
+ if (coeff_ue[*p] > coeff_ue[*max])
+ max = p;
+ p = &UE_sched.next[*p];
+ }
+ /* remove the max one */
+ const int UE_id = *max;
+ p = &UE_sched.next[*max];
+ *max = UE_sched.next[*max];
+ *p = -1;
+
+ const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
+ const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
+ if (idx < 0)
+ continue;
+ UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx;
+
+ max_num_ue--;
+
+ /* allocate as much as possible */
+ const int mcs = cqi_to_mcs[cqi];
+ UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs;
+ int req = find_nb_rb_DL(mcs,
+ UE_info->UE_template[CC_id][UE_id].dl_buffer_total,
+ n_rbg_sched * RBGsize,
+ RBGsize);
+ UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ while (req > 0 && n_rbg_sched > 0) {
+ ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
+ const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize;
+ ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG;
+ req -= sRBG;
+ n_rbg_sched--;
+ for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
+ }
}
return n_rbg_sched;
}
+default_sched_dl_algo_t proportional_fair_wbcqi_dl = {
+ .name = "proportional_fair_wbcqi_dl",
+ .setup = pf_dl_setup,
+ .unset = pf_dl_unset,
+ .run = pf_wbcqi_dl_run,
+ .data = NULL
+};
+
+void *mt_dl_setup(void) {
+ return NULL;
+}
+void mt_dl_unset(void **data) {
+ *data = NULL;
+}
+int mt_wbcqi_dl_run(module_id_t Mod_id,
+ int CC_id,
+ int frame,
+ int subframe,
+ UE_list_t *UE_list,
+ int max_num_ue,
+ int n_rbg_sched,
+ uint8_t *rbgalloc_mask,
+ void *data) {
+ DevAssert(UE_list->head >= 0);
+ DevAssert(n_rbg_sched > 0);
+ const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth);
+ const int RBGsize = get_min_rb_unit(Mod_id, CC_id);
+ const int RBGlastsize = get_rbg_size_last(Mod_id, CC_id);
+ UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
+
+ int rbg = 0;
+ for (; !rbgalloc_mask[rbg]; rbg++)
+ ; /* fast-forward to first allowed RBG */
+
+ UE_list_t UE_sched; // UEs that could be scheduled
+ int *uep = &UE_sched.head;
+
+ for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
+ // check whether there are HARQ retransmissions
+ const COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id];
+ const uint8_t harq_pid = frame_subframe2_dl_harq_pid(cc->tdd_Config, frame, subframe);
+ UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ const uint8_t round = ue_ctrl->round[CC_id][harq_pid];
+ if (round != 8) { // retransmission: allocate
+ const int nb_rb = UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid];
+ if (nb_rb == 0)
+ continue;
+ int nb_rbg = (nb_rb + (nb_rb % RBGsize)) / RBGsize;
+ // needs more RBGs than we can allocate
+ if (nb_rbg > n_rbg_sched) {
+ LOG_D(MAC,
+ "retransmission of UE %d needs more RBGs (%d) than we have (%d)\n",
+ UE_id, nb_rbg, n_rbg_sched);
+ continue;
+ }
+ // ensure that the number of RBs can be contained by the RBGs (!), i.e.
+ // if we allocate the last RBG this one should have the full RBGsize
+ if ((nb_rb % RBGsize) == 0 && nb_rbg == n_rbg_sched
+ && rbgalloc_mask[N_RBG - 1] && RBGlastsize != RBGsize) {
+ LOG_D(MAC,
+ "retransmission of UE %d needs %d RBs, but the last RBG %d is too small (%d, normal %d)\n",
+ UE_id, nb_rb, N_RBG - 1, RBGlastsize, RBGsize);
+ continue;
+ }
+ const uint8_t cqi = ue_ctrl->dl_cqi[CC_id];
+ const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
+ if (idx < 0)
+ continue; // cannot allocate CCE
+ ue_ctrl->pre_dci_dl_pdu_idx = idx;
+ // retransmissions: directly allocate
+ n_rbg_sched -= nb_rbg;
+ ue_ctrl->pre_nb_available_rbs[CC_id] += nb_rb;
+ for (; nb_rbg > 0; rbg++) {
+ if (!rbgalloc_mask[rbg])
+ continue;
+ ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
+ nb_rbg--;
+ }
+ LOG_D(MAC,
+ "%4d.%d n_rbg_sched %d after retransmission reservation for UE %d "
+ "round %d retx nb_rb %d pre_nb_available_rbs %d\n",
+ frame, subframe, n_rbg_sched, UE_id, round,
+ UE_info->UE_template[CC_id][UE_id].nb_rb[harq_pid],
+ ue_ctrl->pre_nb_available_rbs[CC_id]);
+ /* if there are no more RBG to give, return */
+ if (n_rbg_sched <= 0)
+ return 0;
+ max_num_ue--;
+ /* if there are no UEs that can be allocated anymore, return */
+ if (max_num_ue == 0)
+ return n_rbg_sched;
+ for (; !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
+ } else {
+ if (UE_info->UE_template[CC_id][UE_id].dl_buffer_total == 0)
+ continue;
+ *uep = UE_id;
+ uep = &UE_sched.next[UE_id];
+ }
+ }
+ *uep = -1;
+
+ while (max_num_ue > 0 && n_rbg_sched > 0 && UE_sched.head >= 0) {
+ int *max = &UE_sched.head; /* assume head is max */
+ int *p = &UE_sched.next[*max];
+ while (*p >= 0) {
+ /* if the current one has better CQI, or the same and more data */
+ const uint8_t maxCqi = UE_info->UE_sched_ctrl[*max].dl_cqi[CC_id];
+ const uint32_t maxB = UE_info->UE_template[CC_id][*max].dl_buffer_total;
+ const uint8_t pCqi = UE_info->UE_sched_ctrl[*p].dl_cqi[CC_id];
+ const uint32_t pB = UE_info->UE_template[CC_id][*p].dl_buffer_total;
+ if (pCqi > maxCqi || (pCqi == maxCqi && pB > maxB))
+ max = p;
+ p = &UE_sched.next[*p];
+ }
+ /* remove the max one */
+ const int UE_id = *max;
+ p = &UE_sched.next[*max];
+ *max = UE_sched.next[*max];
+ *p = -1;
+
+ const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
+ const int idx = CCE_try_allocate_dlsch(Mod_id, CC_id, subframe, UE_id, cqi);
+ if (idx < 0)
+ continue;
+ UE_info->UE_sched_ctrl[UE_id].pre_dci_dl_pdu_idx = idx;
+
+ max_num_ue--;
+
+ /* allocate as much as possible */
+ const int mcs = cqi_to_mcs[cqi];
+ UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1 = mcs;
+ int req = find_nb_rb_DL(mcs,
+ UE_info->UE_template[CC_id][UE_id].dl_buffer_total,
+ n_rbg_sched * RBGsize,
+ RBGsize);
+ UE_sched_ctrl_t *ue_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+ while (req > 0 && n_rbg_sched > 0) {
+ ue_ctrl->rballoc_sub_UE[CC_id][rbg] = 1;
+ rbgalloc_mask[rbg] = 0;
+ const int sRBG = rbg == N_RBG - 1 ? RBGlastsize : RBGsize;
+ ue_ctrl->pre_nb_available_rbs[CC_id] += sRBG;
+ req -= sRBG;
+ n_rbg_sched--;
+ for (rbg++; n_rbg_sched > 0 && !rbgalloc_mask[rbg]; rbg++) /* fast-forward */ ;
+ }
+ }
+
+ return n_rbg_sched;
+}
+default_sched_dl_algo_t maximum_throughput_wbcqi_dl = {
+ .name = "maximum_throughput_wbcqi_dl",
+ .setup = mt_dl_setup,
+ .unset = mt_dl_unset,
+ .run = mt_wbcqi_dl_run,
+ .data = NULL
+};
// This function stores the downlink buffer for all the logical channels
void
@@ -294,6 +611,18 @@ store_dlsch_buffer(module_id_t Mod_id,
#endif
}
+ /* hack: in schedule_ue_spec, 3 bytes are "reserved" (this should be
+ * done better). An RLC AM entity may ask for only 2 bytes for
+ * ACKing and get a TBS of 32 bits and due to these 3 reserved bytes we may
+ * end up with only 1 byte left for RLC, which is not enough. This hack
+ * prevents the problem. To be done better at some point. If the function
+ * schedule_ue_spec is (has been) reworked, this hack can be removed.
+ * Dig for "TBS - ta_len - header_length_total - sdu_length_total - 3"
+ * in schedule_ue_spec.
+ */
+ if (UE_template->dl_buffer_total > 0 && UE_template->dl_buffer_total <= 2)
+ UE_template->dl_buffer_total += 3;
+
if (UE_template->dl_buffer_total > 0)
LOG_D(MAC,
"[eNB %d] Frame %d Subframe %d : RLC status for UE %d : total DL buffer size %d and total number of pdu %d \n",
@@ -310,19 +639,18 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
int CC_id,
frame_t frameP,
sub_frame_t subframeP) {
- UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
- const int N_RBG = to_rbg(RC.mac[Mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth);
+ eNB_MAC_INST *mac = RC.mac[Mod_id];
+ UE_info_t *UE_info = &mac->UE_info;
+ const int N_RBG = to_rbg(mac->common_channels[CC_id].mib->message.dl_Bandwidth);
const int RBGsize = get_min_rb_unit(Mod_id, CC_id);
store_dlsch_buffer(Mod_id, CC_id, frameP, subframeP);
UE_list_t UE_to_sched;
- UE_to_sched.head = -1;
for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
UE_to_sched.next[i] = -1;
+ int *cur = &UE_to_sched.head;
- int first = 1;
- int last_UE_id = -1;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const UE_TEMPLATE *ue_template = &UE_info->UE_template[CC_id][UE_id];
@@ -355,20 +683,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
}
/* define UEs to schedule */
- if (first) {
- first = 0;
- UE_to_sched.head = UE_id;
- } else {
- UE_to_sched.next[last_UE_id] = UE_id;
- }
- UE_to_sched.next[UE_id] = -1;
- last_UE_id = UE_id;
+ *cur = UE_id;
+ cur = &UE_to_sched.next[UE_id];
}
+ *cur = -1;
if (UE_to_sched.head < 0)
return;
- uint8_t *vrb_map = RC.mac[Mod_id]->common_channels[CC_id].vrb_map;
+ uint8_t *vrb_map = mac->common_channels[CC_id].vrb_map;
uint8_t rbgalloc_mask[N_RBG_MAX];
int n_rbg_sched = 0;
for (int i = 0; i < N_RBG; i++) {
@@ -380,14 +703,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
n_rbg_sched += rbgalloc_mask[i];
}
- round_robin_dl(Mod_id,
- CC_id,
- frameP,
- subframeP,
- &UE_to_sched,
- 4, // max_num_ue
- n_rbg_sched,
- rbgalloc_mask);
+ mac->pre_processor_dl.dl_algo.run(Mod_id,
+ CC_id,
+ frameP,
+ subframeP,
+ &UE_to_sched,
+ 4, // max_num_ue
+ n_rbg_sched,
+ rbgalloc_mask,
+ mac->pre_processor_dl.dl_algo.data);
// the following block is meant for validation of the pre-processor to check
// whether all UE allocations are non-overlapping and is not necessary for
@@ -499,17 +823,28 @@ int pp_find_rb_table_index(int approximate) {
return p + 1;
}
-int g_start_ue_ul = -1;
-int round_robin_ul(module_id_t Mod_id,
- int CC_id,
- int frame,
- int subframe,
- int sched_frame,
- int sched_subframe,
- UE_list_t *UE_list,
- int max_num_ue,
- int num_contig_rb,
- contig_rbs_t *rbs) {
+void *rr_ul_setup(void) {
+ void *data = malloc(sizeof(int));
+ *(int *) data = 0;
+ AssertFatal(data, "could not allocate data in %s()\n", __func__);
+ return data;
+}
+void rr_ul_unset(void **data) {
+ if (*data)
+ free(*data);
+ *data = NULL;
+}
+int rr_ul_run(module_id_t Mod_id,
+ int CC_id,
+ int frame,
+ int subframe,
+ int sched_frame,
+ int sched_subframe,
+ UE_list_t *UE_list,
+ int max_num_ue,
+ int num_contig_rb,
+ contig_rbs_t *rbs,
+ void *data) {
AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n");
UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length;
@@ -649,9 +984,10 @@ int round_robin_ul(module_id_t Mod_id,
end = la > lb ? 2 : -1;
}
- if (g_start_ue_ul == -1)
- g_start_ue_ul = UE_list->head;
- int sUE_id = g_start_ue_ul;
+ int *start_ue = data;
+ if (*start_ue == -1)
+ *start_ue = UE_list->head;
+ int sUE_id = *start_ue;
int rb_idx_given[MAX_MOBILES_PER_ENB];
memset(rb_idx_given, 0, sizeof(rb_idx_given));
@@ -729,35 +1065,35 @@ int round_robin_ul(module_id_t Mod_id,
}
}
- /* if not all UEs could be allocated in this round */
- if (num_ue_req > max_num_ue) {
- /* go to the first one we missed */
- for (int i = 0; i < max_num_ue; ++i)
- g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul);
- } else {
- /* else, just start with the next UE next time */
- g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul);
- }
+ /* just start with the next UE next time */
+ *start_ue = next_ue_list_looped(UE_list, *start_ue);
return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0);
}
+default_sched_ul_algo_t round_robin_ul = {
+ .name = "round_robin_ul",
+ .setup = rr_ul_setup,
+ .unset = rr_ul_unset,
+ .run = rr_ul_run,
+ .data = NULL
+};
void ulsch_scheduler_pre_processor(module_id_t Mod_id,
int CC_id,
- int frameP,
+ frame_t frameP,
sub_frame_t subframeP,
- int sched_frameP,
- unsigned char sched_subframeP) {
- UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
- const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth);
- COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id];
+ frame_t sched_frameP,
+ sub_frame_t sched_subframeP) {
+ eNB_MAC_INST *mac = RC.mac[Mod_id];
+ UE_info_t *UE_info = &mac->UE_info;
+ const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth);
+ COMMON_channels_t *cc = &mac->common_channels[CC_id];
UE_list_t UE_to_sched;
- UE_to_sched.head = -1;
for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
UE_to_sched.next[i] = -1;
+ int *cur = &UE_to_sched.head;
- int last_UE_id = -1;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id];
UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
@@ -780,13 +1116,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
continue;
/* define UEs to schedule */
- if (UE_to_sched.head < 0)
- UE_to_sched.head = UE_id;
- else
- UE_to_sched.next[last_UE_id] = UE_id;
- UE_to_sched.next[UE_id] = -1;
- last_UE_id = UE_id;
+ *cur = UE_id;
+ cur = &UE_to_sched.next[UE_id];
}
+ *cur = -1;
if (UE_to_sched.head < 0)
return;
@@ -807,16 +1140,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
}
}
- round_robin_ul(Mod_id,
- CC_id,
- frameP,
- subframeP,
- sched_frameP,
- sched_subframeP,
- &UE_to_sched,
- 4, // max_num_ue
- n_contig,
- rbs);
+ mac->pre_processor_ul.ul_algo.run(Mod_id,
+ CC_id,
+ frameP,
+ subframeP,
+ sched_frameP,
+ sched_subframeP,
+ &UE_to_sched,
+ 4, // max_num_ue
+ n_contig,
+ rbs,
+ mac->pre_processor_ul.ul_algo.data);
// the following block is meant for validation of the pre-processor to check
// whether all UE allocations are non-overlapping and is not necessary for
@@ -835,7 +1169,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
continue;
print = 1;
- uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id],
+ uint8_t harq_pid = subframe2harqpid(&mac->common_channels[CC_id],
sched_frameP, sched_subframeP);
LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n",
frameP,
diff --git a/openair2/LAYER2/MAC/slicing/slicing.c b/openair2/LAYER2/MAC/slicing/slicing.c
new file mode 100644
index 0000000000000000000000000000000000000000..9c88f6cffbbbb723756b97558dc93c31a16353eb
--- /dev/null
+++ b/openair2/LAYER2/MAC/slicing/slicing.c
@@ -0,0 +1,601 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*!
+ * \file slicing.c
+ * \brief Generic slicing helper functions and Static Slicing Implementation
+ * \author Robert Schmidt
+ * \date 2020
+ * \email robert.schmidt@eurecom.fr
+ */
+
+#define _GNU_SOURCE
+#include <stdlib.h>
+#include <dlfcn.h>
+
+#include "assertions.h"
+#include "common/utils/LOG/log.h"
+
+#include "slicing.h"
+#include "slicing_internal.h"
+
+#include "common/ran_context.h"
+extern RAN_CONTEXT_t RC;
+
+#define RET_FAIL(ret, x...) do { LOG_E(MAC, x); return ret; } while (0)
+
+int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id) {
+ return si->UE_assoc_slice[UE_id];
+}
+
+void slicing_add_UE(slice_info_t *si, int UE_id) {
+ add_ue_list(&si->s[0]->UEs, UE_id);
+ si->UE_assoc_slice[UE_id] = 0;
+}
+
+void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id) {
+ const uint8_t i = assoc[UE_id];
+ DevAssert(remove_ue_list(&s[i]->UEs, UE_id));
+ assoc[UE_id] = -1;
+}
+
+void slicing_remove_UE(slice_info_t *si, int UE_id) {
+ _remove_UE(si->s, si->UE_assoc_slice, UE_id);
+}
+
+void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to) {
+ const uint8_t i = assoc[UE_id];
+ const int ri = remove_ue_list(&s[i]->UEs, UE_id);
+ if (!ri)
+ LOG_W(MAC, "did not find UE %d in DL slice index %d\n", UE_id, i);
+ add_ue_list(&s[to]->UEs, UE_id);
+ assoc[UE_id] = to;
+}
+
+void slicing_move_UE(slice_info_t *si, int UE_id, int idx) {
+ DevAssert(idx >= -1 && idx < si->num);
+ if (idx >= 0)
+ _move_UE(si->s, si->UE_assoc_slice, UE_id, idx);
+}
+
+int _exists_slice(uint8_t n, slice_t **s, int id) {
+ for (int i = 0; i < n; ++i)
+ if (s[i]->id == id)
+ return i;
+ return -1;
+}
+
+slice_t *_add_slice(uint8_t *n, slice_t **s) {
+ s[*n] = calloc(1, sizeof(slice_t));
+ if (!s[*n])
+ return NULL;
+ init_ue_list(&s[*n]->UEs);
+ *n += 1;
+ return s[*n - 1];
+}
+
+slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx) {
+ if (idx >= *n)
+ return NULL;
+
+ slice_t *sr = s[idx];
+ while (sr->UEs.head >= 0)
+ _move_UE(s, assoc, sr->UEs.head, 0);
+
+ for (int i = idx + 1; i < *n; ++i)
+ s[i - 1] = s[i];
+ *n -= 1;
+ s[*n] = NULL;
+
+ for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
+ if (assoc[i] > idx)
+ assoc[i] -= 1;
+
+ if (sr->label)
+ free(sr->label);
+
+ return sr;
+}
+
+/************************ Static Slicing Implementation ************************/
+
+int addmod_static_slice_dl(slice_info_t *si,
+ int id,
+ char *label,
+ void *algo,
+ void *slice_params_dl) {
+ static_slice_param_t *dl = slice_params_dl;
+ if (dl && dl->posLow > dl->posHigh)
+ RET_FAIL(-1, "%s(): slice id %d posLow > posHigh\n", __func__, id);
+
+ uint8_t rbgMap[25] = { 0 };
+ int index = _exists_slice(si->num, si->s, id);
+ if (index >= 0) {
+ for (int s = 0; s < si->num; ++s) {
+ static_slice_param_t *sd = dl && si->s[s]->id == id ? dl : si->s[s]->algo_data;
+ for (int i = sd->posLow; i <= sd->posHigh; ++i) {
+ if (rbgMap[i])
+ RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i);
+ rbgMap[i] = 1;
+ }
+ }
+ /* no problem, can allocate */
+ slice_t *s = si->s[index];
+ if (label) {
+ if (s->label) free(s->label);
+ s->label = label;
+ }
+ if (algo) {
+ s->dl_algo.unset(&s->dl_algo.data);
+ s->dl_algo = *(default_sched_dl_algo_t *) algo;
+ if (!s->dl_algo.data)
+ s->dl_algo.data = s->dl_algo.setup();
+ }
+ if (dl) {
+ free(s->algo_data);
+ s->algo_data = dl;
+ }
+ return index;
+ }
+
+ if (!dl)
+ RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id);
+
+ if (si->num >= MAX_STATIC_SLICES)
+ RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES);
+ for (int s = 0; s < si->num; ++s) {
+ static_slice_param_t *sd = si->s[s]->algo_data;
+ for (int i = sd->posLow; i <= sd->posHigh; ++i)
+ rbgMap[i] = 1;
+ }
+
+ for (int i = dl->posLow; i <= dl->posHigh; ++i)
+ if (rbgMap[i])
+ RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i);
+
+ if (!algo)
+ RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__);
+
+ slice_t *ns = _add_slice(&si->num, si->s);
+ if (!ns)
+ RET_FAIL(-4, "%s(): could not create new slice\n", __func__);
+ ns->id = id;
+ ns->label = label;
+ ns->dl_algo = *(default_sched_dl_algo_t *) algo;
+ if (!ns->dl_algo.data)
+ ns->dl_algo.data = ns->dl_algo.setup();
+ ns->algo_data = dl;
+
+ return si->num - 1;
+}
+
+int addmod_static_slice_ul(slice_info_t *si,
+ int id,
+ char *label,
+ void *algo,
+ void *slice_params_ul) {
+ static_slice_param_t *ul = slice_params_ul;
+ /* Minimum 3RBs, because LTE stack requires this */
+ if (ul && ul->posLow + 2 > ul->posHigh)
+ RET_FAIL(-1, "%s(): slice id %d posLow + 2 > posHigh\n", __func__, id);
+
+ uint8_t rbMap[110] = { 0 };
+ int index = _exists_slice(si->num, si->s, id);
+ if (index >= 0) {
+ for (int s = 0; s < si->num; ++s) {
+ static_slice_param_t *su = ul && si->s[s]->id == id && ul ? ul : si->s[s]->algo_data;
+ for (int i = su->posLow; i <= su->posHigh; ++i) {
+ if (rbMap[i])
+ RET_FAIL(-33, "%s(): overlap of slices detected at RBG %d\n", __func__, i);
+ rbMap[i] = 1;
+ }
+ }
+ /* no problem, can allocate */
+ slice_t *s = si->s[index];
+ if (algo) {
+ s->ul_algo.unset(&s->ul_algo.data);
+ s->ul_algo = *(default_sched_ul_algo_t *) algo;
+ if (!s->ul_algo.data)
+ s->ul_algo.data = s->ul_algo.setup();
+ }
+ if (label) {
+ if (s->label) free(s->label);
+ s->label = label;
+ }
+ if (ul) {
+ free(s->algo_data);
+ s->algo_data = ul;
+ }
+ return index;
+ }
+
+ if (!ul)
+ RET_FAIL(-100, "%s(): no parameters for new slice %d, aborting\n", __func__, id);
+
+ if (si->num >= MAX_STATIC_SLICES)
+ RET_FAIL(-2, "%s(): cannot have more than %d slices\n", __func__, MAX_STATIC_SLICES);
+ for (int s = 0; s < si->num; ++s) {
+ static_slice_param_t *sd = si->s[s]->algo_data;
+ for (int i = sd->posLow; i <= sd->posHigh; ++i)
+ rbMap[i] = 1;
+ }
+
+ for (int i = ul->posLow; i <= ul->posHigh; ++i)
+ if (rbMap[i])
+ RET_FAIL(-3, "%s(): overlap of slices detected at RBG %d\n", __func__, i);
+
+ if (!algo)
+ RET_FAIL(-14, "%s(): no scheduler algorithm provided\n", __func__);
+
+ slice_t *ns = _add_slice(&si->num, si->s);
+ if (!ns)
+ RET_FAIL(-4, "%s(): could not create new slice\n", __func__);
+ ns->id = id;
+ ns->label = label;
+ ns->ul_algo = *(default_sched_ul_algo_t *) algo;
+ if (!ns->ul_algo.data)
+ ns->ul_algo.data = ns->ul_algo.setup();
+ ns->algo_data = ul;
+
+ return si->num - 1;
+}
+
+int remove_static_slice_dl(slice_info_t *si, uint8_t slice_idx) {
+ if (slice_idx == 0)
+ return 0;
+ slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx);
+ if (!sr)
+ return 0;
+ free(sr->algo_data);
+ sr->dl_algo.unset(&sr->dl_algo.data);
+ free(sr);
+ return 1;
+}
+
+int remove_static_slice_ul(slice_info_t *si, uint8_t slice_idx) {
+ if (slice_idx == 0)
+ return 0;
+ slice_t *sr = _remove_slice(&si->num, si->s, si->UE_assoc_slice, slice_idx);
+ if (!sr)
+ return 0;
+ free(sr->algo_data);
+ sr->ul_algo.unset(&sr->ul_algo.data);
+ free(sr);
+ return 1;
+}
+
+void static_dl(module_id_t mod_id,
+ int CC_id,
+ frame_t frame,
+ sub_frame_t subframe) {
+ UE_info_t *UE_info = &RC.mac[mod_id]->UE_info;
+
+ store_dlsch_buffer(mod_id, CC_id, frame, subframe);
+
+ for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
+ UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+
+ /* initialize per-UE scheduling information */
+ ue_sched_ctrl->pre_nb_available_rbs[CC_id] = 0;
+ ue_sched_ctrl->dl_pow_off[CC_id] = 2;
+ memset(ue_sched_ctrl->rballoc_sub_UE[CC_id], 0, sizeof(ue_sched_ctrl->rballoc_sub_UE[CC_id]));
+ ue_sched_ctrl->pre_dci_dl_pdu_idx = -1;
+ }
+
+ const int N_RBG = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth);
+ const int RBGsize = get_min_rb_unit(mod_id, CC_id);
+ uint8_t *vrb_map = RC.mac[mod_id]->common_channels[CC_id].vrb_map;
+ uint8_t rbgalloc_mask[N_RBG_MAX];
+ for (int i = 0; i < N_RBG; i++) {
+ // calculate mask: init to one + "AND" with vrb_map:
+ // if any RB in vrb_map is blocked (1), the current RBG will be 0
+ rbgalloc_mask[i] = 1;
+ for (int j = 0; j < RBGsize; j++)
+ rbgalloc_mask[i] &= !vrb_map[RBGsize * i + j];
+ }
+
+ slice_info_t *s = RC.mac[mod_id]->pre_processor_dl.slices;
+ int max_num_ue;
+ switch (s->num) {
+ case 1:
+ max_num_ue = 4;
+ break;
+ case 2:
+ max_num_ue = 2;
+ break;
+ default:
+ max_num_ue = 1;
+ break;
+ }
+ for (int i = 0; i < s->num; ++i) {
+ if (s->s[i]->UEs.head < 0)
+ continue;
+ uint8_t rbgalloc_slice_mask[N_RBG_MAX];
+ memset(rbgalloc_slice_mask, 0, sizeof(rbgalloc_slice_mask));
+ static_slice_param_t *p = s->s[i]->algo_data;
+ int n_rbg_sched = 0;
+ for (int rbg = p->posLow; rbg <= p->posHigh && rbg <= N_RBG; ++rbg) {
+ rbgalloc_slice_mask[rbg] = rbgalloc_mask[rbg];
+ n_rbg_sched += rbgalloc_mask[rbg];
+ }
+
+ s->s[i]->dl_algo.run(mod_id,
+ CC_id,
+ frame,
+ subframe,
+ &s->s[i]->UEs,
+ max_num_ue, // max_num_ue
+ n_rbg_sched,
+ rbgalloc_slice_mask,
+ s->s[i]->dl_algo.data);
+ }
+
+ // the following block is meant for validation of the pre-processor to check
+ // whether all UE allocations are non-overlapping and is not necessary for
+ // scheduling functionality
+ char t[26] = "_________________________";
+ t[N_RBG] = 0;
+ for (int i = 0; i < N_RBG; i++)
+ for (int j = 0; j < RBGsize; j++)
+ if (vrb_map[RBGsize*i+j] != 0)
+ t[i] = 'x';
+ int print = 0;
+ for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
+ const UE_sched_ctrl_t *ue_sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
+
+ if (ue_sched_ctrl->pre_nb_available_rbs[CC_id] == 0)
+ continue;
+
+ LOG_D(MAC,
+ "%4d.%d UE%d %d RBs allocated, pre MCS %d\n",
+ frame,
+ subframe,
+ UE_id,
+ ue_sched_ctrl->pre_nb_available_rbs[CC_id],
+ UE_info->eNB_UE_stats[CC_id][UE_id].dlsch_mcs1);
+
+ print = 1;
+
+ for (int i = 0; i < N_RBG; i++) {
+ if (!ue_sched_ctrl->rballoc_sub_UE[CC_id][i])
+ continue;
+ for (int j = 0; j < RBGsize; j++) {
+ if (vrb_map[RBGsize*i+j] != 0) {
+ LOG_I(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t);
+ LOG_E(MAC, "%4d.%d: UE %d allocated at locked RB %d/RBG %d\n", frame,
+ subframe, UE_id, RBGsize * i + j, i);
+ }
+ vrb_map[RBGsize*i+j] = 1;
+ }
+ t[i] = '0' + UE_id;
+ }
+ }
+ if (print)
+ LOG_D(MAC, "%4d.%d DL scheduler allocation list: %s\n", frame, subframe, t);
+}
+
+void static_ul(module_id_t mod_id,
+ int CC_id,
+ frame_t frame,
+ sub_frame_t subframe,
+ frame_t sched_frame,
+ sub_frame_t sched_subframe) {
+ UE_info_t *UE_info = &RC.mac[mod_id]->UE_info;
+ const int N_RB_UL = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth);
+ COMMON_channels_t *cc = &RC.mac[mod_id]->common_channels[CC_id];
+
+ for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
+ UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id];
+ UE_template->pre_assigned_mcs_ul = 0;
+ UE_template->pre_allocated_nb_rb_ul = 0;
+ UE_template->pre_allocated_rb_table_index_ul = -1;
+ UE_template->pre_first_nb_rb_ul = 0;
+ UE_template->pre_dci_ul_pdu_idx = -1;
+ }
+
+ slice_info_t *s = RC.mac[mod_id]->pre_processor_ul.slices;
+ int max_num_ue;
+ switch (s->num) {
+ case 1:
+ max_num_ue = 4;
+ break;
+ case 2:
+ max_num_ue = 2;
+ break;
+ default:
+ max_num_ue = 1;
+ break;
+ }
+ for (int i = 0; i < s->num; ++i) {
+ if (s->s[i]->UEs.head < 0)
+ continue;
+ int last_rb_blocked = 1;
+ int n_contig = 0;
+ contig_rbs_t rbs[2]; // up to two contig RBs for PRACH in between
+ static_slice_param_t *p = s->s[i]->algo_data;
+ for (int rb = p->posLow; rb <= p->posHigh && rb < N_RB_UL; ++rb) {
+ if (cc->vrb_map_UL[rb] == 0 && last_rb_blocked) {
+ last_rb_blocked = 0;
+ n_contig++;
+ AssertFatal(n_contig <= 2, "cannot handle more than two contiguous RB regions\n");
+ rbs[n_contig - 1].start = rb;
+ }
+ if (cc->vrb_map_UL[rb] == 1 && !last_rb_blocked) {
+ last_rb_blocked = 1;
+ rbs[n_contig - 1].length = rb - rbs[n_contig - 1].start;
+ }
+ }
+ if (!last_rb_blocked)
+ rbs[n_contig - 1].length = p->posHigh - rbs[n_contig - 1].start + 1;
+
+ s->s[i]->ul_algo.run(mod_id,
+ CC_id,
+ frame,
+ subframe,
+ sched_frame,
+ sched_subframe,
+ &s->s[i]->UEs,
+ max_num_ue, // max_num_ue
+ n_contig,
+ rbs,
+ s->s[i]->ul_algo.data);
+ }
+
+ // the following block is meant for validation of the pre-processor to check
+ // whether all UE allocations are non-overlapping and is not necessary for
+ // scheduling functionality
+ char t[101] = "__________________________________________________"
+ "__________________________________________________";
+ t[N_RB_UL] = 0;
+ for (int j = 0; j < N_RB_UL; j++)
+ if (cc->vrb_map_UL[j] != 0)
+ t[j] = 'x';
+ int print = 0;
+ for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
+ UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id];
+ if (UE_template->pre_allocated_nb_rb_ul == 0)
+ continue;
+
+ print = 1;
+ uint8_t harq_pid = subframe2harqpid(&RC.mac[mod_id]->common_channels[CC_id],
+ sched_frame, sched_subframe);
+ LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n",
+ frame,
+ subframe,
+ UE_id,
+ UE_template->pre_allocated_nb_rb_ul,
+ UE_template->pre_allocated_rb_table_index_ul,
+ UE_template->pre_first_nb_rb_ul,
+ UE_template->pre_assigned_mcs_ul,
+ UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0 ? "(retx)" : "");
+
+ for (int i = 0; i < UE_template->pre_allocated_nb_rb_ul; ++i) {
+ /* only check if this is not a retransmission */
+ if (UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] == 0
+ && cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] == 1) {
+
+ LOG_I(MAC, "%4d.%d UL scheduler allocation list: %s\n", frame, subframe, t);
+ LOG_E(MAC,
+ "%4d.%d: UE %d allocated at locked RB %d (is: allocated start "
+ "%d/length %d)\n",
+ frame, subframe, UE_id, UE_template->pre_first_nb_rb_ul + i,
+ UE_template->pre_first_nb_rb_ul,
+ UE_template->pre_allocated_nb_rb_ul);
+ }
+ cc->vrb_map_UL[UE_template->pre_first_nb_rb_ul + i] = 1;
+ t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0';
+ }
+ }
+ if (print)
+ LOG_D(MAC,
+ "%4d.%d UL scheduler allocation list: %s\n",
+ sched_frame,
+ sched_subframe,
+ t);
+}
+
+void static_destroy(slice_info_t **si) {
+ const int n = (*si)->num;
+ (*si)->num = 0;
+ for (int i = 0; i < n; ++i) {
+ slice_t *s = (*si)->s[i];
+ if (s->label)
+ free(s->label);
+ free(s->algo_data);
+ free(s);
+ }
+ free((*si)->s);
+ free(*si);
+}
+
+pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id) {
+ slice_info_t *si = calloc(1, sizeof(slice_info_t));
+ DevAssert(si);
+
+ si->num = 0;
+ si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t));
+ DevAssert(si->s);
+ for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
+ si->UE_assoc_slice[i] = -1;
+
+ /* insert default slice, all resources */
+ static_slice_param_t *dlp = malloc(sizeof(static_slice_param_t));
+ dlp->posLow = 0;
+ dlp->posHigh = to_rbg(RC.mac[mod_id]->common_channels[CC_id].mib->message.dl_Bandwidth) - 1;
+ default_sched_dl_algo_t *algo = &RC.mac[mod_id]->pre_processor_dl.dl_algo;
+ algo->data = NULL;
+ DevAssert(0 == addmod_static_slice_dl(si, 0, strdup("default"), algo, dlp));
+ const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list;
+ for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id])
+ slicing_add_UE(si, UE_id);
+
+ pp_impl_param_t sttc;
+ sttc.algorithm = STATIC_SLICING;
+ sttc.add_UE = slicing_add_UE;
+ sttc.remove_UE = slicing_remove_UE;
+ sttc.move_UE = slicing_move_UE;
+ sttc.addmod_slice = addmod_static_slice_dl;
+ sttc.remove_slice = remove_static_slice_dl;
+ sttc.dl = static_dl;
+ // current DL algo becomes default scheduler
+ sttc.dl_algo = *algo;
+ sttc.destroy = static_destroy;
+ sttc.slices = si;
+
+ return sttc;
+}
+
+pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id) {
+ slice_info_t *si = calloc(1, sizeof(slice_info_t));
+ DevAssert(si);
+
+ si->num = 0;
+ si->s = calloc(MAX_STATIC_SLICES, sizeof(slice_t));
+ DevAssert(si->s);
+ for (int i = 0; i < MAX_MOBILES_PER_ENB; ++i)
+ si->UE_assoc_slice[i] = -1;
+
+ /* insert default slice, all resources */
+ static_slice_param_t *ulp = malloc(sizeof(static_slice_param_t));
+ ulp->posLow = 0;
+ ulp->posHigh = to_prb(RC.mac[mod_id]->common_channels[CC_id].ul_Bandwidth) - 1;
+ default_sched_ul_algo_t *algo = &RC.mac[mod_id]->pre_processor_ul.ul_algo;
+ algo->data = NULL;
+ DevAssert(0 == addmod_static_slice_ul(si, 0, strdup("default"), algo, ulp));
+ const UE_list_t *UE_list = &RC.mac[mod_id]->UE_info.list;
+ for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id])
+ slicing_add_UE(si, UE_id);
+
+ pp_impl_param_t sttc;
+ sttc.algorithm = STATIC_SLICING;
+ sttc.add_UE = slicing_add_UE;
+ sttc.remove_UE = slicing_remove_UE;
+ sttc.move_UE = slicing_move_UE;
+ sttc.addmod_slice = addmod_static_slice_ul;
+ sttc.remove_slice = remove_static_slice_ul;
+ sttc.ul = static_ul;
+ // current DL algo becomes default scheduler
+ sttc.ul_algo = *algo;
+ sttc.destroy = static_destroy;
+ sttc.slices = si;
+
+ return sttc;
+}
diff --git a/openair2/LAYER2/MAC/slicing/slicing.h b/openair2/LAYER2/MAC/slicing/slicing.h
new file mode 100644
index 0000000000000000000000000000000000000000..1099b50ea0cb92533d14a1bfa57945de0deefcb9
--- /dev/null
+++ b/openair2/LAYER2/MAC/slicing/slicing.h
@@ -0,0 +1,74 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*!
+ * \file slicing.h
+ * \brief General slice definition and helper parameters
+ * \author Robert Schmidt
+ * \date 2020
+ * \email robert.schmidt@eurecom.fr
+ */
+
+#ifndef __SLICING_H__
+#define __SLICING_H__
+
+#include "openair2/LAYER2/MAC/mac.h"
+
+typedef struct slice_s {
+ /// Arbitrary ID
+ slice_id_t id;
+ /// Arbitrary label
+ char *label;
+
+ union {
+ default_sched_dl_algo_t dl_algo;
+ default_sched_ul_algo_t ul_algo;
+ };
+
+ /// A specific algorithm's implementation parameters
+ void *algo_data;
+ /// Internal data that might be kept alongside a slice's params
+ void *int_data;
+
+ // list of users in this slice
+ UE_list_t UEs;
+} slice_t;
+
+typedef struct slice_info_s {
+ uint8_t num;
+ slice_t **s;
+ uint8_t UE_assoc_slice[MAX_MOBILES_PER_ENB];
+} slice_info_t;
+
+int slicing_get_UE_slice_idx(slice_info_t *si, int UE_id);
+
+#define STATIC_SLICING 10
+/* only four static slices for UL, DL resp. (not enough DCIs) */
+#define MAX_STATIC_SLICES 4
+typedef struct {
+ uint16_t posLow;
+ uint16_t posHigh;
+} static_slice_param_t;
+pp_impl_param_t static_dl_init(module_id_t mod_id, int CC_id);
+pp_impl_param_t static_ul_init(module_id_t mod_id, int CC_id);
+
+
+#endif /* __SLICING_H__ */
diff --git a/openair2/LAYER2/MAC/slicing/slicing_internal.h b/openair2/LAYER2/MAC/slicing/slicing_internal.h
new file mode 100644
index 0000000000000000000000000000000000000000..744f8924d925ed81de1d30883e6e44e4d2fbbfb8
--- /dev/null
+++ b/openair2/LAYER2/MAC/slicing/slicing_internal.h
@@ -0,0 +1,46 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*!
+ * \file slicing_internal.h
+ * \brief Internal slice helper functions
+ * \author Robert Schmidt
+ * \date 2020
+ * \email robert.schmidt@eurecom.fr
+ */
+
+#ifndef __SLICING_INTERNAL_H__
+#define __SLICING_INTERNAL_H__
+
+#include "slicing.h"
+
+void slicing_add_UE(slice_info_t *si, int UE_id);
+
+void _remove_UE(slice_t **s, uint8_t *assoc, int UE_id);
+void slicing_remove_UE(slice_info_t *si, int UE_id);
+
+void _move_UE(slice_t **s, uint8_t *assoc, int UE_id, int to);
+void slicing_move_UE(slice_info_t *si, int UE_id, int idx);
+
+slice_t *_add_slice(uint8_t *n, slice_t **s);
+slice_t *_remove_slice(uint8_t *n, slice_t **s, uint8_t *assoc, int idx);
+
+#endif /* __SLICING_INTERNAL_H__ */
diff --git a/openair2/LAYER2/MAC/ue_procedures.c b/openair2/LAYER2/MAC/ue_procedures.c
index 24630c0fe2cc8e095198e9ae9bdfd0c2d385ab56..e97f1bebddab7afaf76d161666b8dc5b159e7338 100644
--- a/openair2/LAYER2/MAC/ue_procedures.c
+++ b/openair2/LAYER2/MAC/ue_procedures.c
@@ -72,7 +72,10 @@ extern UL_IND_t *UL_INFO;
extern int next_ra_frame;
extern module_id_t next_Mod_id;
-int mbms_rab_id = 2047;
+int mbms_rab_id=2047;//[8] = {2047,2047,2047,2047,2047,2047,2047,2047};
+static int mbms_mch_i=0;
+//static int num_msi_per_CSA[28];
+
/*
*
@@ -753,8 +756,9 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
LOG_E(MAC,"MCH Scheduling Information MAC Control Element should have an even size\n");
}
- LOG_D(MAC,"MCH Scheduling Information, len(%d)\n",rx_lengths[i]);
+ LOG_D(MAC,"MCH Scheduling Information, len(%d)\n",rx_lengths[i]);
+
for (j=0; j<rx_lengths[i]/2; j++) {
uint16_t stop_mtch_val = ((uint16_t)(payload_ptr[2*j] & 0x07) << 8) | (uint16_t)payload_ptr[2*j+1];
UE_mac_inst[module_idP].pmch_lcids[j] = (payload_ptr[2*j] & 0xF8) >> 3;
@@ -768,7 +772,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
UE_mac_inst[module_idP].msi_status_v[j] = 0;
if (UE_mac_inst[module_idP].mcch_status==1) {
- LOG_D(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), i(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_stop_mtch[j]);
+ LOG_D(MAC,"[UE %d] Frame %d : MCH->MSI for sync area %d (eNB %d, %d bytes), LCID(%d)(%d)\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], UE_mac_inst[module_idP].pmch_lcids[j] , UE_mac_inst[module_idP].pmch_stop_mtch[j]);
if (UE_mac_inst[module_idP].pmch_stop_mtch[j] < 2043) {
UE_mac_inst[module_idP].pmch_stop_mtch[j] += UE_mac_inst[module_idP].msi_current_alloc;
@@ -794,7 +798,7 @@ ue_send_mch_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP,
}
if (j<28 && UE_mac_inst[module_idP].msi_status_v[j]==1) {
- LOG_D(MAC,"[UE %d] Frame %d : MCH->MTCH for sync area %d (eNB %d, %d bytes), j=%d\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], j);
+ LOG_D(MAC,"[UE %d] Frame %d : MCH->MTCH for sync area %d (eNB %d, %d bytes), j=%d lcid %d\n", module_idP, frameP, sync_area, eNB_index, rx_lengths[i], j,rx_lcids[i]);
//This sucks I know ... workaround !
mbms_rab_id = rx_lcids[i];
//end sucks :-(
@@ -951,7 +955,9 @@ int ue_query_p_mch_info(module_id_t module_idP, uint32_t frameP, uint32_t subfra
}
} else { //more that one MCH ?? check better this condition
//msi and mtch are mutally excluded then the break is safe
+ //TODO
if ((num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[i-1]->sf_AllocEnd_r9 + 1) && (sf_AllocEnd_r9 >= (num_sf_alloc+1))) {
+ //if ((num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[i-1]->sf_AllocEnd_r9) && (sf_AllocEnd_r9 >= (num_sf_alloc))) {
//msi should be just after
msi_flag = 1;
LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%d),common_num_sf_alloc(%d)\n",i,frameP,subframe,num_sf_alloc,sf_AllocEnd_r9,
@@ -986,6 +992,458 @@ int ue_query_p_mch_info(module_id_t module_idP, uint32_t frameP, uint32_t subfra
return mtch_mcs;
}
+//static int common_num_sf_alloc=0;
+//static int x=0;
+int ue_query_mch_fembms(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_t subframe, uint8_t eNB_index,uint8_t *sync_area, uint8_t *mcch_active) {
+ int i = 0, j = 0,/* ii = 0,*/ msi_pos = -1, mcch_mcs = -1, mtch_mcs = -1, l=0/*,ii=0*/;
+ int mcch_flag = 0, mtch_flag = 0, msi_flag = 0;
+ int alloc_offset=0;
+ uint32_t period;
+ //uint16_t num_non_mbsfn_SubframeConfig=0;
+ long mch_scheduling_period = -1;
+ uint8_t mch_lcid = 0;
+ //int first_pos=0;
+
+ if(UE_mac_inst[module_idP].non_mbsfn_SubframeConfig == NULL )
+ return -1;
+
+ int non_mbsfn_SubframeConfig = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
+
+ period = 4<<UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->radioFrameAllocationPeriod_r14;
+ alloc_offset = UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->radioFrameAllocationOffset_r14;
+
+ long mcch_period = 32 << UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_RepetitionPeriod_r9;
+ long mcch_offset = UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.mcch_Offset_r9;
+
+ if (UE_mac_inst[module_idP].pmch_Config[0]) {
+ mch_scheduling_period = 8 << UE_mac_inst[module_idP].pmch_Config[0]->mch_SchedulingPeriod_r9;
+ }
+
+
+// for(l=0;l<8;l++){
+// if(UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]!=NULL){
+// if(frameP%(4<<UE_mac_inst[module_idP].commonSF_AllocPeriod_r9)==0){
+// first_pos=0;
+// if((frameP&3)==0)
+// first_pos++;
+// while((non_mbsfn_SubframeConfig & (0x100 >> msi_pos)) == (0x100>>msi_pos))
+// first_pos++;
+// if(first_pos == subframe){
+// ii=0;
+// while(UE_mac_inst[module_idP].pmch_Config[ii]!=NULL){
+// num_msi_per_CSA[ii]= ( ( 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9) / (8 << UE_mac_inst[module_idP].pmch_Config[ii]->mch_SchedulingPeriod_r9) );
+// ii++;
+// LOG_D(MAC,"frameP %d subframe %d num_msi_per_CSA[%d] %d\n",frameP,subframe,ii,num_msi_per_CSA[ii]);
+// }
+// }
+//
+// }
+// }
+// }
+//
+
+ // get the real MCS value
+ switch (UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.signallingMCS_r9) {
+ case 0:
+ mcch_mcs = 2;
+ break;
+
+ case 1:
+ mcch_mcs = 7;
+ break;
+
+ case 2:
+ mcch_mcs = 13;
+ break;
+
+ case 3:
+ mcch_mcs = 19;
+ break;
+ }
+ LOG_D(MAC,"frameP %d subframe %d period %d alloc_offset %d mcch_mcs %d mcch_period %ld mcch_offset %ld buf %x mch_scheduling_period %ld\n",frameP, subframe, period, alloc_offset,mcch_mcs, mcch_period, mcch_offset,(UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0]),mch_scheduling_period);
+
+ if((frameP % period ) == alloc_offset){
+ switch(subframe){
+ case 0:
+ return (-1);
+ break;
+ case 1:
+ if ((non_mbsfn_SubframeConfig & 0x100) > 0)
+ return (-1);
+ break;
+ case 2:
+ if ((non_mbsfn_SubframeConfig & 0x80) > 0)
+ return (-1);
+ break;
+ case 3:
+ if ((non_mbsfn_SubframeConfig & 0x40) > 0)
+ return (-1);
+ break;
+ case 4:
+ if ((non_mbsfn_SubframeConfig & 0x20) > 0)
+ return (-1);
+ break;
+ case 5:
+ if ((non_mbsfn_SubframeConfig & 0x10) > 0)
+ return (-1);
+ break;
+ case 6:
+ if ((non_mbsfn_SubframeConfig & 0x8) > 0)
+ return (-1);
+ break;
+ case 7:
+ if ((non_mbsfn_SubframeConfig & 0x4) > 0)
+ return (-1);
+ break;
+ case 8:
+ if ((non_mbsfn_SubframeConfig & 0x2) > 0)
+ return (-1);
+ break;
+ case 9:
+ if ((non_mbsfn_SubframeConfig & 0x1) > 0)
+ return (-1);
+ break;
+ }
+ }
+
+ if (UE_mac_inst[module_idP].pmch_Config[0]) {
+ // Find the first subframe in this MCH to transmit MSI
+ if (frameP % 1 == 0) {
+ if (frameP % mch_scheduling_period == 0) {
+ msi_pos=0;
+ if((frameP&3)==0)
+ msi_pos++;
+ while((non_mbsfn_SubframeConfig & (0x100 >> msi_pos)) == (0x100>>msi_pos))
+ msi_pos++;
+ if(msi_pos == subframe){
+ UE_mac_inst[module_idP].common_num_sf_alloc=0;
+ mbms_mch_i=0;
+ //LOG_W(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+ }
+ }
+
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=subframe;
+ mbms_mch_i++;
+ // LOG_W(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
+
+ // Check if the subframe is for MSI, MCCH or MTCHs and Set the correspoding flag to 1
+ switch (subframe) {
+ case 0:
+ if (msi_pos == 0) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+ case 1:
+ if (msi_pos == 1) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+ break;
+
+ case 2:
+ if (msi_pos == 2) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+
+ break;
+
+ case 3:
+ if (msi_pos == 3) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+
+ break;
+ case 4:
+ if (msi_pos == 4) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+ case 5:
+ if (msi_pos == 5) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+
+ case 6:
+ if (msi_pos == 6) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+
+ break;
+
+ case 7:
+ if (msi_pos == 7) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+
+ break;
+
+ case 8:
+ if (msi_pos == 8) {
+ msi_flag = 1;
+ }
+ if ((frameP % mcch_period == mcch_offset) &&
+ ((UE_mac_inst[module_idP].mbsfn_AreaInfo[i]->mcch_Config_r9.sf_AllocInfo_r9.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8)) {
+ mcch_flag = 1;
+ }
+
+ mtch_flag = 1;
+ break;
+
+ case 9:
+ if (msi_pos == 9) {
+ msi_flag = 1;
+ }
+ mtch_flag = 1;
+ break;
+ }// end switch
+
+ if( (msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1) ){
+ UE_mac_inst[module_idP].common_num_sf_alloc++;
+ //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){
+ //UE_mac_inst[module_idP].common_num_sf_alloc++;
+ //if(msi_flag == 1)
+ // if((num_msi_per_CSA[mbms_mch_i]--)==0){
+ // LOG_E(MAC,"Both MSI and MTCH Should be reset?\n");
+ // msi_flag=0;
+ //}
+ //}
+
+ }
+
+
+
+
+#ifdef OLD
+ // Acount for sf_allocable in CSA
+ int num_sf_alloc = 0;
+
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame)
+ continue;
+
+ uint32_t common_mbsfn_SubframeConfig = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.choice.oneFrame.buf[0];
+
+
+ for (j = 0; j < 6; j++)
+ num_sf_alloc += ((common_mbsfn_SubframeConfig & (0x80 >> j)) == (0x80 >> j));
+ //num_sf_alloc=1;
+ }
+
+ num_sf_alloc = 10;
+
+ num_non_mbsfn_SubframeConfig = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
+ int ones=0;
+ for(j=0; j < 16; j++){
+ if(num_non_mbsfn_SubframeConfig & 1)
+ ones++;
+ num_non_mbsfn_SubframeConfig>>=1;
+ }
+
+ for (l = 0; l < 28; l++) {
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[l] >= 1/*num_sf_alloc*/) {
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[l] != 2047) {
+ if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL){
+ mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9;
+ //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[0]->radioframeAllocationOffset;
+ long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[0]->radioframeAllocationPeriod;
+ long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9;
+ if(UE_mac_inst[module_idP].common_num_sf_alloc >= UE_mac_inst[module_idP].pmch_stop_mtch[l]){
+ //LOG_E(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d\n",UE_mac_inst[module_idP].common_num_sf_alloc);
+
+ mtch_mcs = -1;
+ }/*else
+ OG_W(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d\n",UE_mac_inst[module_idP].common_num_sf_alloc);*/
+ LOG_D(MAC,"Attemp to UE_mac_inst[module_idP].common_num_sf_alloc %d num_sf_alloc %d commonSF_AllocPeriod %ld, common_mbsfn_period %ld num_non_mbsfn_SubframeConfig %x ones %d\n",UE_mac_inst[module_idP].common_num_sf_alloc,num_sf_alloc, commonSF_AllocPeriod,common_mbsfn_period,num_non_mbsfn_SubframeConfig,ones);
+ UE_mac_inst[module_idP].common_num_sf_alloc++;
+ UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % (num_sf_alloc * commonSF_AllocPeriod / common_mbsfn_period-(1+ones)*(commonSF_AllocPeriod/4)); //TODO
+ }
+ else
+ mtch_mcs = -1;
+
+ mch_lcid = (uint8_t)l;
+ break;
+ }
+ }
+ }
+#endif
+
+{
+ // Acount for sf_allocable in Common SF Allocation
+ int num_sf_alloc = 0;
+
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame)
+ continue;
+
+ //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset;
+ long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod;
+ long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9;
+
+
+ num_sf_alloc =10*commonSF_AllocPeriod/common_mbsfn_period;
+ num_sf_alloc -=1*((commonSF_AllocPeriod/common_mbsfn_period)/4); //CAS sfs
+ uint32_t num_non_mbsfn_SubframeConfig2 = (UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]<<1 | UE_mac_inst[module_idP].non_mbsfn_SubframeConfig->subframeAllocation_r14.buf[0]>>7);
+ for (j = 0; j < 10; j++)
+ num_sf_alloc -= ((num_non_mbsfn_SubframeConfig2 & (0x200 >> j)) == (0x200 >> j))*((commonSF_AllocPeriod/common_mbsfn_period)/period);
+
+ }
+
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame)
+ continue;
+
+ //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset;
+ long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod;
+ //long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9;
+
+
+ if(msi_flag==1 && UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){
+ LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%ld),common_num_sf_alloc(%d)\n",mbms_mch_i,frameP,subframe,num_sf_alloc,UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9,
+ UE_mac_inst[module_idP].common_num_sf_alloc);
+ UE_mac_inst[module_idP].msi_current_alloc = UE_mac_inst[module_idP].common_num_sf_alloc;//num_sf_alloc;
+ UE_mac_inst[module_idP].msi_pmch = mbms_mch_i;
+ }else if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] >= UE_mac_inst[module_idP].common_num_sf_alloc/*num_sf_alloc*/) {
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] != 2047) {
+ mtch_flag = 1;
+ if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL)
+ mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9;
+ else
+ mtch_mcs = -1;
+ mch_lcid = (uint8_t)mbms_mch_i;
+ LOG_D(MAC,"mtch should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),mtch_mcs(%d),pmch_stop_mtch(%d),lcid(%d),msi_pmch(%d)\n",frameP,subframe,num_sf_alloc,mtch_mcs,
+ UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i],UE_mac_inst[module_idP].pmch_lcids[mbms_mch_i],UE_mac_inst[module_idP].msi_pmch);
+ }
+ }
+ }
+ UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % ((num_sf_alloc-mbms_mch_i) /** commonSF_AllocPeriod *// common_mbsfn_period);//48;
+
+ if(mtch_flag)
+ break;
+ }
+ if(msi_flag==1){
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %(4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 <<UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){
+ msi_flag=0;
+ LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframe, mbms_mch_i);
+ }
+ }
+ }
+}
+
+ // sf allocation is non-overlapping
+ if ((msi_flag==1) || (mcch_flag==1) || (mtch_flag==1)) {
+ LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n",
+ module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag);
+ *sync_area=i;
+ }
+
+ //if(msi_flag == 1)
+ // if((num_msi_per_CSA[mbms_mch_i]--)==0){
+ // LOG_E(MAC,"Both MSI and MTCH Should be reset?\n");
+ // msi_flag=mtch_flag=0;
+ //}
+
+
+ if ((mcch_flag == 1)) { // || (msi_flag==1))
+ *mcch_active = 1;
+ }
+
+ if ( (mcch_flag==1) || ((msi_flag==1) && (UE_mac_inst[module_idP].mcch_status==1)) ) {
+ if (msi_flag!=1) {
+ for (i=0; i<8; i++)
+ UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[i] = NULL;
+
+ for (i=0; i<15; i++)
+ UE_mac_inst[module_idP].pmch_Config[i] = NULL;
+
+ for (i=0; i<28 ; i++) {
+ UE_mac_inst[module_idP].pmch_lcids[i] = -1;
+ UE_mac_inst[module_idP].pmch_stop_mtch[i] = 2047;
+ UE_mac_inst[module_idP].msi_status_v[i] = 0;
+ }
+ } else {
+ for (i=0; i<28; i++) {
+ UE_mac_inst[module_idP].pmch_lcids[i] = -1;
+ UE_mac_inst[module_idP].pmch_stop_mtch[i] = 2047;
+ UE_mac_inst[module_idP].msi_status_v[i] = 0;
+ }
+ }
+
+ return mcch_mcs;
+ } else if ((mtch_flag==1) && (UE_mac_inst[module_idP].msi_status_v[(mch_lcid > 27) ? 27 : mch_lcid] == 1)) {
+ return mtch_mcs;
+ } else {
+ return -1;
+ }
+
+
+
+ // if(mcch_flag == 1 || msi_flag == 1 ){
+ // *mcch_active = 1;
+ // return (mcch_mcs);
+ // }else if(mtch_flag == 1){
+ // mtch_mcs=-1;
+ // return (mtch_mcs);
+ // }
+
+ // return -1;
+
+}
+
+
int ue_query_p_mch(module_id_t module_idP, uint32_t frameP, uint32_t subframe, int *mtch_active, int *msi_active, uint8_t *mch_lcid) {
int i, j, mtch_mcs = -1;
int mtch_flag = 0;
@@ -1100,6 +1558,7 @@ int ue_query_p_mch(module_id_t module_idP, uint32_t frameP, uint32_t subframe, i
return mtch_mcs;
}
+
int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_t subframe, uint8_t eNB_index,uint8_t *sync_area, uint8_t *mcch_active) {
int i = 0, j = 0, ii = 0, jj = 0, msi_pos = 0, mcch_mcs = -1, mtch_mcs = -1;
int l =0;
@@ -1162,6 +1621,11 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
ii = UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & (0x80 >> msi_pos);
msi_pos++;
}
+ if(msi_pos == subframe){
+ UE_mac_inst[module_idP].common_num_sf_alloc=0;
+ mbms_mch_i=0;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
}
}
@@ -1170,6 +1634,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
case 1:
if (UE_mac_inst[module_idP].tdd_Config == NULL) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF1) == MBSFN_FDD_SF1) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=1;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
if (msi_pos == 1) {
msi_flag = 1;
}
@@ -1188,6 +1660,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
case 2:
if (UE_mac_inst[module_idP].tdd_Config == NULL) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF2) == MBSFN_FDD_SF2) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=2;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
if (msi_pos == 2) {
msi_flag = 1;
}
@@ -1219,6 +1699,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
}
} else { // FDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF3) == MBSFN_FDD_SF3) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=3;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
if (msi_pos == 3) {
msi_flag = 1;
}
@@ -1255,6 +1743,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
case 6:
if (UE_mac_inst[module_idP].tdd_Config == NULL) {
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF6) == MBSFN_FDD_SF6) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=6;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
if (msi_pos == 4) {
msi_flag = 1;
}
@@ -1286,6 +1782,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
}
} else { // FDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF7) == MBSFN_FDD_SF7) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=5;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
+
if (msi_pos == 5) {
msi_flag = 1;
}
@@ -1317,6 +1821,13 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
}
} else { // FDD
if ((UE_mac_inst[module_idP].mbsfn_SubframeConfig[j]->subframeAllocation.choice.oneFrame.buf[0] & MBSFN_FDD_SF8) == MBSFN_FDD_SF8) {
+ if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i+1]!=NULL){
+ if( UE_mac_inst[module_idP].common_num_sf_alloc == UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9){
+ msi_pos=6;
+ mbms_mch_i++;
+ LOG_D(MAC,"MSP, frameP %d subframeP %d msi_pos(%d) mbms_mch_i %d\n",frameP, subframe, msi_pos,mbms_mch_i);
+ }
+ }
if (msi_pos == 6) {
msi_flag = 1;
}
@@ -1351,6 +1862,14 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
break;
}// end switch
+ if( (msi_flag == 1) || (mcch_flag == 1) || (mtch_flag == 1) ){
+ UE_mac_inst[module_idP].common_num_sf_alloc++;
+ //if( (msi_flag!=1 && mcch_flag!=1) || (msi_flag!=1 && mcch_flag!=1 && mtch_flag!=1) ){
+ //UE_mac_inst[module_idP].common_num_sf_alloc++;
+ //}
+ }
+
+#ifdef OLD
// Acount for sf_allocable in CSA
int num_sf_alloc = 0;
@@ -1392,11 +1911,86 @@ int ue_query_mch(module_id_t module_idP, uint8_t CC_id, uint32_t frameP, uint32_
}
}
}
+#endif
+
+{
+ // Acount for sf_allocable in Common SF Allocation
+ int num_sf_alloc = 0;
+
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame)
+ continue;
+
+ //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset;
+ //long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod;
+ //long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9;
+
+ uint32_t common_mbsfn_SubframeConfig = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.choice.oneFrame.buf[0];
+
+ for (j = 0; j < 6; j++)
+ num_sf_alloc += ((common_mbsfn_SubframeConfig & (0x80 >> j)) == (0x80 >> j));
+ }
+
+
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->subframeAllocation.present != LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame)
+ continue;
+
+ //int common_mbsfn_alloc_offset = UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationOffset;
+ long common_mbsfn_period = 1 << UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l]->radioframeAllocationPeriod;
+ long commonSF_AllocPeriod = 4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9;
+
+
+ if(msi_flag==1 && UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){
+ LOG_D(MAC,"msi(%d) should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),sf_AllocEnd_r9(%ld),common_num_sf_alloc(%d)\n",mbms_mch_i,frameP,subframe,num_sf_alloc,UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->sf_AllocEnd_r9,
+ UE_mac_inst[module_idP].common_num_sf_alloc);
+ UE_mac_inst[module_idP].msi_current_alloc = UE_mac_inst[module_idP].common_num_sf_alloc;//num_sf_alloc;
+ UE_mac_inst[module_idP].msi_pmch = mbms_mch_i;
+ }else if(UE_mac_inst[module_idP].pmch_Config[mbms_mch_i] != NULL){
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] >= UE_mac_inst[module_idP].common_num_sf_alloc/*num_sf_alloc*/) {
+ if (UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i] != 2047) {
+ mtch_flag = 1;
+ if (UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch] != NULL)
+ mtch_mcs = UE_mac_inst[module_idP].pmch_Config[UE_mac_inst[module_idP].msi_pmch]->dataMCS_r9;
+ else
+ mtch_mcs = -1;
+ mch_lcid = (uint8_t)mbms_mch_i;
+ LOG_D(MAC,"mtch should be allocated:frame(%d),submframe(%d),num_sf_alloc(%d),mtch_mcs(%d),pmch_stop_mtch(%d),lcid(%d),msi_pmch(%d)\n",frameP,subframe,num_sf_alloc,mtch_mcs,
+ UE_mac_inst[module_idP].pmch_stop_mtch[mbms_mch_i],UE_mac_inst[module_idP].pmch_lcids[mbms_mch_i],UE_mac_inst[module_idP].msi_pmch);
+ }
+ }
+ }
+ //LOG_D(MAC,"UE_mac_inst[module_idP].common_num_sf_alloc: %d num_sf_alloc %d mbms_mch_i %d commonSF_AllocPeriod %d common_mbsfn_period %d\n",UE_mac_inst[module_idP].common_num_sf_alloc,num_sf_alloc,mbms_mch_i,commonSF_AllocPeriod,common_mbsfn_period);
+ UE_mac_inst[module_idP].common_num_sf_alloc = UE_mac_inst[module_idP].common_num_sf_alloc % ((num_sf_alloc* commonSF_AllocPeriod-mbms_mch_i) / common_mbsfn_period);//48;
+
+
+ if(mtch_flag)
+ break;
+ }
+ if(msi_flag==1){
+ for (l = 0; l < 8; l++) {
+ if (UE_mac_inst[module_idP].commonSF_Alloc_r9_mbsfn_SubframeConfig[l] == NULL)
+ continue;
+
+ if ( (/*AJ*/ (/*V*/ ( /*U*/ (frameP %(4 << UE_mac_inst[module_idP].commonSF_AllocPeriod_r9)) ) / 8 ) % ((8 <<UE_mac_inst[module_idP].pmch_Config[mbms_mch_i]->mch_SchedulingPeriod_r9) / 8 ) ) != 0 ){
+ msi_flag=0;
+ LOG_D(MAC,"frameP %d subframeP %d reset(%d)\n",frameP, subframe, mbms_mch_i);
+ }
+ }
+ }
+
+}
// sf allocation is non-overlapping
if ((msi_flag==1) || (mcch_flag==1) || (mtch_flag==1)) {
- LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d\n",
- module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag);
+ LOG_D(MAC,"[UE %d] Frame %d Subframe %d: sync area %d SF alloc %d: msi flag %d, mcch flag %d, mtch flag %d x %d\n",
+ module_idP, frameP, subframe,l,j,msi_flag,mcch_flag,mtch_flag,UE_mac_inst[module_idP].common_num_sf_alloc);
*sync_area=i;
break;
}
diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
index 5801fabcfb7d7e9e44ad717e08de1efa05e41cda..d8583167dd5e1a193fcda6ad7c84e86ad974f046 100644
--- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
+++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
@@ -24,8 +24,8 @@
* \author R. Knopp, K.H. HSU, G. Casati
* \date 2019
* \version 0.1
- * \company Eurecom / NTUST / Fraunhofer IIS
- * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de
+ * \company Eurecom / NTUST / Fraunhofer IIS
+ * \email: knopp@eurecom.fr, kai-hsiang.hsu@eurecom.fr, guido.casati@iis.fraunhofer.de
* \note
* \warning
*/
@@ -41,6 +41,10 @@
#define NR_BCCH_BCH 5 // MIB
+#define CCCH_PAYLOAD_SIZE_MAX 128
+
+#define RAR_PAYLOAD_SIZE_MAX 128
+
// For both DL/UL-SCH
// Except:
// - UL/DL-SCH: fixed-size MAC CE(known by LCID)
@@ -67,36 +71,234 @@
// R: Reserved bit, set to zero.
typedef struct {
- uint8_t LCID:6; // octet 1 [5:0]
- uint8_t F:1; // octet 1 [6]
- uint8_t R:1; // octet 1 [7]
- uint8_t L:8; // octet 2 [7:0]
+ uint8_t LCID: 6; // octet 1 [5:0]
+ uint8_t F: 1; // octet 1 [6]
+ uint8_t R: 1; // octet 1 [7]
+ uint8_t L: 8; // octet 2 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_SHORT;
typedef struct {
- uint8_t LCID:6; // octet 1 [5:0]
- uint8_t F:1; // octet 1 [6]
- uint8_t R:1; // octet 1 [7]
- uint8_t L1:8; // octet 2 [7:0]
- uint8_t L2:8; // octet 3 [7:0]
+ uint8_t LCID: 6; // octet 1 [5:0]
+ uint8_t F: 1; // octet 1 [6]
+ uint8_t R: 1; // octet 1 [7]
+ uint8_t L1: 8; // octet 2 [7:0]
+ uint8_t L2: 8; // octet 3 [7:0]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_LONG;
typedef struct {
- uint8_t LCID:6; // octet 1 [5:0]
- uint8_t R:2; // octet 1 [7:6]
+ uint8_t LCID: 6; // octet 1 [5:0]
+ uint8_t R: 2; // octet 1 [7:6]
} __attribute__ ((__packed__)) NR_MAC_SUBHEADER_FIXED;
+// BSR MAC CEs
+// TS 38.321 ch. 6.1.3.1
+// Short BSR for a specific logical channel group ID
+typedef struct {
+ uint8_t Buffer_size: 5; // octet 1 LSB
+ uint8_t LcgID: 3; // octet 1 MSB
+} __attribute__ ((__packed__)) NR_BSR_SHORT;
+
+typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED;
+
+// Long BSR for all logical channel group ID
+typedef struct {
+ uint8_t Buffer_size7: 8;
+ uint8_t Buffer_size6: 8;
+ uint8_t Buffer_size5: 8;
+ uint8_t Buffer_size4: 8;
+ uint8_t Buffer_size3: 8;
+ uint8_t Buffer_size2: 8;
+ uint8_t Buffer_size1: 8;
+ uint8_t Buffer_size0: 8;
+ uint8_t LcgID0: 1;
+ uint8_t LcgID1: 1;
+ uint8_t LcgID2: 1;
+ uint8_t LcgID3: 1;
+ uint8_t LcgID4: 1;
+ uint8_t LcgID5: 1;
+ uint8_t LcgID6: 1;
+ uint8_t LcgID7: 1;
+} __attribute__ ((__packed__)) NR_BSR_LONG;
+
+typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED;
+
// 38.321 ch. 6.1.3.4
typedef struct {
- uint8_t TA_COMMAND:6; // octet 1 [5:0]
- uint8_t TAGID:2; // octet 1 [7:6]
+ uint8_t TA_COMMAND: 6; // octet 1 [5:0]
+ uint8_t TAGID: 2; // octet 1 [7:6]
} __attribute__ ((__packed__)) NR_MAC_CE_TA;
+// single Entry PHR MAC CE
+// TS 38.321 ch. 6.1.3.8
+typedef struct {
+ uint8_t PH: 6;
+ uint8_t R1: 2;
+ uint8_t PCMAX: 6;
+ uint8_t R2: 6;
+} __attribute__ ((__packed__)) NR_SINGLE_ENTRY_PHR_MAC_CE;
+
+
+// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
+// 38.321 ch. 6.1.3.19
+typedef struct {
+ uint8_t BWPID: 2; // octet 1 [1:0]
+ uint8_t CELLID: 5; // octet 1 [6:2]
+ uint8_t A_D: 1; // octet 1 [7]
+ uint8_t CSIRS_RSC_ID: 4; // octet 2 [3:0]
+ uint8_t R: 4; // octet 2 [7:4]
+} __attribute__ ((__packed__)) NR_MAC_CE_SP_ZP_CSI_RS_RES_SET;
+
+//TS 38.321 Sec 6.1.3.15, TCI State indicaton for UE-Specific PDCCH MAC CE
+typedef struct {
+ uint8_t CoresetId1: 3; //Octect 1 [2:0]
+ uint8_t ServingCellId: 5; //Octect 1 [7:3]
+ uint8_t TciStateId: 7; //Octect 2 [6:0]
+ uint8_t CoresetId2: 1; //Octect 2 [7]
+} __attribute__ ((__packed__)) NR_TCI_PDCCH;
+
+//TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
+typedef struct {
+ uint8_t BWP_Id: 2; //Octect 1 [1:0]
+ uint8_t ServingCellId: 5; //Octect 1 [6:2]
+ uint8_t R: 1; //Octect 1 [7]
+ uint8_t T[]; //Octects 2 to MAX TCI States/8
+} __attribute__ ((__packed__)) NR_TCI_PDSCH_APERIODIC_CSI;
+
+//TS 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
+typedef struct {
+ uint8_t BWP_Id: 2; //Octect 1 [1:0]
+ uint8_t ServingCellId: 5; //Octect 1 [6:2]
+ uint8_t R1: 1; //Octect 1 [7]
+ uint8_t S0: 1; //Octect 2 [0]
+ uint8_t S1: 1; //Octect 2 [1]
+ uint8_t S2: 1; //Octect 2 [2]
+ uint8_t S3: 1; //Octect 2 [3]
+ uint8_t R2: 4; //Octect 2 [7:4]
+} __attribute__ ((__packed__)) NR_PUCCH_CSI_REPORTING;
+
+
+//TS 38.321 sec 6.1.3.12
+//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
+typedef struct {
+ uint8_t BWP_ID: 2;
+ uint8_t SCID: 5;
+ uint8_t A_D: 1;
+ uint8_t SP_CSI_RSID: 6;
+ uint8_t IM: 1;
+ uint8_t R1: 1;
+ uint8_t SP_CSI_IMID: 6;
+ uint8_t R2: 2;
+ struct TCI_S {
+ uint8_t TCI_STATE_ID: 6;
+ uint8_t R: 2;
+ } __attribute__ ((__packed__)) TCI_STATE;
+} __attribute__ ((__packed__)) CSI_RS_CSI_IM_ACT_DEACT_MAC_CE;
+
+
+//* RAR MAC subheader // TS 38.321 ch. 6.1.5, 6.2.2 *//
+// - E: The Extension field is a flag indicating if the MAC subPDU including this MAC subheader is the last MAC subPDU or not in the MAC PDU
+// - T: The Type field is a flag indicating whether the MAC subheader contains a Random Access Preamble ID or a Backoff Indicator (0, BI) (1, RAPID)
+// - R: Reserved bit, set to "0"
+// - BI: The Backoff Indicator field identifies the overload condition in the cell.
+// - RAPID: The Random Access Preamble IDentifier field identifies the transmitted Random Access Preamble
+
+/*!\brief RAR MAC subheader with RAPID */
+typedef struct {
+ uint8_t RAPID: 6;
+ uint8_t T: 1;
+ uint8_t E: 1;
+} __attribute__ ((__packed__)) NR_RA_HEADER_RAPID;
+
+/*!\brief RAR MAC subheader with Backoff Indicator */
+typedef struct {
+ uint8_t BI: 4;
+ uint8_t R: 2;
+ uint8_t T: 1;
+ uint8_t E: 1;
+} __attribute__ ((__packed__)) NR_RA_HEADER_BI;
+
+// TS 38.321 ch. 6.2.3
+typedef struct {
+ uint8_t TA1: 7; // octet 1 [6:0]
+ uint8_t R: 1; // octet 1 [7]
+ uint8_t UL_GRANT_1: 3; // octet 2 [2:0]
+ uint8_t TA2: 5; // octet 2 [7:3]
+ uint8_t UL_GRANT_2: 8; // octet 3 [7:0]
+ uint8_t UL_GRANT_3: 8; // octet 4 [7:0]
+ uint8_t UL_GRANT_4: 8; // octet 5 [7:0]
+ uint8_t TCRNTI_1: 8; // octet 6 [7:0]
+ uint8_t TCRNTI_2: 8; // octet 7 [7:0]
+} __attribute__ ((__packed__)) NR_MAC_RAR;
+
+// DCI pdu structures. Used by both gNB and UE.
+typedef struct {
+ uint16_t val;
+ uint8_t nbits;
+} dci_field_t;
+
+typedef struct {
+
+ uint8_t format_indicator; //1 bit
+ uint8_t ra_preamble_index; //6 bits
+ uint8_t ss_pbch_index; //6 bits
+ uint8_t prach_mask_index; //4 bits
+ uint8_t mcs; //5 bits
+ uint8_t ndi; //1 bit
+ uint8_t rv; //2 bits
+ uint8_t harq_pid; //4 bits
+ uint8_t tpc; //2 bits
+ uint8_t short_messages_indicator; //2 bits
+ uint8_t short_messages; //8 bits
+ uint8_t tb_scaling; //2 bits
+ uint8_t pucch_resource_indicator; //3 bits
+ uint8_t system_info_indicator; //1 bit
+ uint8_t ulsch_indicator;
+ uint8_t slot_format_indicator_count;
+ uint8_t *slot_format_indicators;
+
+ uint8_t pre_emption_indication_count;
+ uint16_t *pre_emption_indications; //14 bit each
+
+ uint8_t block_number_count;
+ uint8_t *block_numbers;
+ uint8_t padding;
+
+ dci_field_t mcs2; //variable
+ dci_field_t ndi2; //variable
+ dci_field_t rv2; //variable
+ dci_field_t frequency_domain_assignment; //variable
+ dci_field_t time_domain_assignment; //variable
+ dci_field_t frequency_hopping_flag; //variable
+ dci_field_t vrb_to_prb_mapping; //variable
+ dci_field_t dai[2]; //variable
+ dci_field_t pdsch_to_harq_feedback_timing_indicator; //variable
+ dci_field_t carrier_indicator; //variable
+ dci_field_t bwp_indicator; //variable
+ dci_field_t prb_bundling_size_indicator; //variable
+ dci_field_t rate_matching_indicator; //variable
+ dci_field_t zp_csi_rs_trigger; //variable
+ dci_field_t transmission_configuration_indication; //variable
+ dci_field_t srs_request; //variable
+ dci_field_t cbgti; //variable
+ dci_field_t cbgfi; //variable
+ dci_field_t srs_resource_indicator; //variable
+ dci_field_t precoding_information; //variable
+ dci_field_t csi_request; //variable
+ dci_field_t ptrs_dmrs_association; //variable
+ dci_field_t beta_offset_indicator; //variable
+ dci_field_t cloded_loop_indicator; //variable
+ dci_field_t ul_sul_indicator; //variable
+ dci_field_t antenna_ports; //variable
+ dci_field_t dmrs_sequence_initialization;
+ dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
+
+} dci_pdu_rel15_t;
+
// 38.321 ch6.2.1, 38.331
#define DL_SCH_LCID_CCCH 0x00
#define DL_SCH_LCID_DCCH 0x01
#define DL_SCH_LCID_DCCH1 0x02
-#define DL_SCH_LCID_DTCH 0x03
+#define DL_SCH_LCID_DTCH 0x04
#define DL_SCH_LCID_RECOMMENDED_BITRATE 0x2F
#define DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT 0x30
#define DL_SCH_LCID_PUCCH_SPATIAL_RELATION_ACT 0x31
@@ -105,7 +307,7 @@ typedef struct {
#define DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH 0x34
#define DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH 0x35
#define DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL 0x36
-#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37
+#define DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT 0X37
#define DL_SCH_LCID_DUPLICATION_ACT 0X38
#define DL_SCH_LCID_SCell_ACT_4_OCT 0X39
#define DL_SCH_LCID_SCell_ACT_1_OCT 0X3A
@@ -118,8 +320,8 @@ typedef struct {
#define UL_SCH_LCID_CCCH 0x00
#define UL_SCH_LCID_SRB1 0x01
#define UL_SCH_LCID_SRB2 0x02
-#define UL_SCH_LCID_DTCH 0x03
-#define UL_SCH_LCID_SRB3 0x04
+#define UL_SCH_LCID_SRB3 0x03
+#define UL_SCH_LCID_DTCH 0x04
#define UL_SCH_LCID_CCCH_MSG3 0x21
#define UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY 0x35
#define UL_SCH_LCID_MULTI_ENTRY_PHR_4_OCT 0x36
@@ -133,9 +335,9 @@ typedef struct {
#define UL_SCH_LCID_L_BSR 0x3E
#define UL_SCH_LCID_PADDING 0x3F
-#define NR_MAX_NUM_LCID 32
-#define NR_MAX_NUM_LCGID 8
-#define MAX_RLC_SDU_SUBHEADER_SIZE 3
+#define NR_MAX_NUM_LCID 32
+#define NR_MAX_NUM_LCGID 8
+#define MAX_RLC_SDU_SUBHEADER_SIZE 3
#endif /*__LAYER2_MAC_H__ */
diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
index ae231641943ace1a3392ffa10b1481cfab0b9e90..f40d822b6bff1e72d1316a55801e8b261605f60c 100644
--- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
@@ -31,6 +31,1169 @@
*/
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+#include <limits.h>
+
+const uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160};
+
+// Table 6.3.3.1-5 (38.211) NCS for preamble formats with delta_f_RA = 1.25 KHz
+uint16_t NCS_unrestricted_delta_f_RA_125[16] = {0,13,15,18,22,26,32,38,46,59,76,93,119,167,279,419};
+uint16_t NCS_restricted_TypeA_delta_f_RA_125[15] = {15,18,22,26,32,38,46,55,68,82,100,128,158,202,237}; // high-speed case set Type A
+uint16_t NCS_restricted_TypeB_delta_f_RA_125[13] = {15,18,22,26,32,38,46,55,68,82,100,118,137}; // high-speed case set Type B
+
+// Table 6.3.3.1-6 (38.211) NCS for preamble formats with delta_f_RA = 5 KHz
+uint16_t NCS_unrestricted_delta_f_RA_5[16] = {0,13,26,33,38,41,49,55,64,76,93,119,139,209,279,419};
+uint16_t NCS_restricted_TypeA_delta_f_RA_5[16] = {36,57,72,81,89,94,103,112,121,132,137,152,173,195,216,237}; // high-speed case set Type A
+uint16_t NCS_restricted_TypeB_delta_f_RA_5[14] = {36,57,60,63,65,68,71,77,81,85,97,109,122,137}; // high-speed case set Type B
+
+// Table 6.3.3.1-7 (38.211) NCS for preamble formats with delta_f_RA = 15 * 2mu KHz where mu = {0,1,2,3}
+uint16_t NCS_unrestricted_delta_f_RA_15[16] = {0,2,4,6,8,10,12,13,15,17,19,23,27,34,46,69};
+
+const char *prachfmt[]={"A1","A2","A3","B1","B2","B3","B4","C0","C2"};
+const char *prachfmt03[]={"0","1","2","3"};
+
+uint16_t get_NCS(uint8_t index, uint16_t format0, uint8_t restricted_set_config) {
+
+ LOG_D(MAC,"get_NCS: indx %d,format0 %d, restriced_set_config %d\n",
+ index,format0,restricted_set_config);
+
+ if (format0 < 3) {
+ switch(restricted_set_config){
+ case 0:
+ return(NCS_unrestricted_delta_f_RA_125[index]);
+ case 1:
+ return(NCS_restricted_TypeA_delta_f_RA_125[index]);
+ case 2:
+ return(NCS_restricted_TypeB_delta_f_RA_125[index]);
+ default:
+ AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config);
+ }
+ }
+ else {
+ if (format0 == 3) {
+ switch(restricted_set_config){
+ case 0:
+ return(NCS_unrestricted_delta_f_RA_5[index]);
+ case 1:
+ return(NCS_restricted_TypeA_delta_f_RA_5[index]);
+ case 2:
+ return(NCS_restricted_TypeB_delta_f_RA_5[index]);
+ default:
+ AssertFatal(1==0,"Invalid restricted set config value %d",restricted_set_config);
+ }
+ }
+ else
+ return(NCS_unrestricted_delta_f_RA_15[index]);
+ }
+}
+
+
+// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum/supplementary uplink
+// the column 5, (SFN_nbr is a bitmap where we set bit to '1' in the position of the subframe where the RACH can be sent.
+// E.g. in row 4, and column 5 we have set value 512 ('1000000000') which means RACH can be sent at subframe 9.
+// E.g. in row 20 and column 5 we have set value 66 ('0001000010') which means RACH can be sent at subframe 1 or 6
+int64_t table_6_3_3_2_2_prachConfig_Index [256][9] = {
+//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
+{0, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{0, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{0, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{0, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{0, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{0, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{0, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{0, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{0, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{0, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{0, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{0, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
+{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
+{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
+{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
+{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
+{0, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
+{0, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
+{0, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9
+{0, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8
+{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9
+{0, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{1, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{1, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{1, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{1, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{1, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{1, -1, 8, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{1, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{1, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{1, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{1, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{1, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{1, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{1, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{1, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
+{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
+{1, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
+{1, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
+{1, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
+{1, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
+{1, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
+{1, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3,6,9
+{2, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{2, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{2, -1, 4, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{2, -1, 2, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{2, -1, 2, 0, 32, 0, -1, -1, 0}, // (subframe number) 5
+{2, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{2, -1, 1, 0, 32, 0, -1, -1, 0}, // (subframe number) 5
+{3, -1, 16, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{3, -1, 16, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{3, -1, 16, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{3, -1, 8, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{3, -1, 8, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{3, -1, 8, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{3, -1, 4, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{3, -1, 4, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{3, -1, 4, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{3, -1, 2, 1, 2, 0, -1, -1, 0}, // (subframe number) 1
+{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subframe number) 4
+{3, -1, 2, 1, 128, 0, -1, -1, 0}, // (subframe number) 7
+{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subframe number) 9
+{3, -1, 1, 0, 2, 0, -1, -1, 0}, // (subframe number) 1
+{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subframe number) 4
+{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subframe number) 7
+{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subframe number) 1,6
+{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subframe number) 2,7
+{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subframe number) 3,8
+{3, -1, 1, 0, 146, 0, -1, -1, 0}, // (subframe number) 1,4,7
+{3, -1, 1, 0, 292, 0, -1, -1, 0}, // (subframe number) 2,5,8
+{3, -1, 1, 0, 584, 0, -1, -1, 0}, // (subframe number) 3, 6, 9
+{3, -1, 1, 0, 341, 0, -1, -1, 0}, // (subframe number) 0,2,4,6,8
+{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subframe number) 1,3,5,7,9
+{3, -1, 1, 0, 1023, 0, -1, -1, 0}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xa1, -1, 16, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 16, 1, 16, 0, 2, 6, 2}, // (subframe number) 4
+{0xa1, -1, 8, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 8, 1, 16, 0, 2, 6, 2}, // (subframe number) 4
+{0xa1, -1, 4, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 4, 1, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 4, 0, 16, 0, 2, 6, 2}, // (subframe number) 4
+{0xa1, -1, 2, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 2, 0, 2, 0, 2, 6, 2}, // (subframe number) 1
+{0xa1, -1, 2, 0, 16, 0, 2, 6, 2}, // (subframe number) 4
+{0xa1, -1, 2, 0, 128, 0, 2, 6, 2}, // (subframe number) 7
+{0xa1, -1, 1, 0, 16, 0, 1, 6, 2}, // (subframe number) 4
+{0xa1, -1, 1, 0, 66, 0, 1, 6, 2}, // (subframe number) 1,6
+{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subframe number) 4,9
+{0xa1, -1, 1, 0, 2, 0, 2, 6, 2}, // (subframe number) 1
+{0xa1, -1, 1, 0, 128, 0, 2, 6, 2}, // (subframe number) 7
+{0xa1, -1, 1, 0, 132, 0, 2, 6, 2}, // (subframe number) 2,7
+{0xa1, -1, 1, 0, 146, 0, 2, 6, 2}, // (subframe number) 1,4,7
+{0xa1, -1, 1, 0, 341, 0, 2, 6, 2}, // (subframe number) 0,2,4,6,8
+{0xa1, -1, 1, 0, 1023, 0, 2, 6, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xa1, -1, 1, 0, 682, 0, 2, 6, 2}, // (subframe number) 1,3,5,7,9
+{0xa1, 0xb1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xa1, 0xb1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xa1, 0xb1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
+{0xa1, 0xb1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
+{0xa1, 0xb1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xa1, 0xb1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
+{0xa1, 0xb1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
+{0xa1, 0xb1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
+{0xa1, 0xb1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
+{0xa2, -1, 16, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
+{0xa2, -1, 16, 1, 16, 0, 2, 3, 4}, // (subframe number) 4
+{0xa2, -1, 8, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
+{0xa2, -1, 8, 1, 16, 0, 2, 3, 4}, // (subframe number) 4
+{0xa2, -1, 4, 0, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
+{0xa2, -1, 4, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
+{0xa2, -1, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
+{0xa2, -1, 2, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
+{0xa2, -1, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
+{0xa2, -1, 2, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
+{0xa2, -1, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4
+{0xa2, -1, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6
+{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9
+{0xa2, -1, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
+{0xa2, -1, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
+{0xa2, -1, 1, 0, 132, 0, 2, 3, 4}, // (subframe number) 2,7
+{0xa2, -1, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7
+{0xa2, -1, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8
+{0xa2, -1, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xa2, -1, 1, 0, 682, 0, 2, 3, 4}, // (subframe number) 1,3,5,7,9
+{0xa2, 0xb2, 2, 1, 580, 0, 1, 3, 4}, // (subframe number) 2,6,9
+{0xa2, 0xb2, 2, 0, 16, 0, 2, 3, 4}, // (subframe number) 4
+{0xa2, 0xb2, 1, 0, 16, 0, 1, 3, 4}, // (subframe number) 4
+{0xa2, 0xb2, 1, 0, 66, 0, 1, 3, 4}, // (subframe number) 1,6
+{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subframe number) 4,9
+{0xa2, 0xb2, 1, 0, 2, 0, 2, 3, 4}, // (subframe number) 1
+{0xa2, 0xb2, 1, 0, 128, 0, 2, 3, 4}, // (subframe number) 7
+{0xa2, 0xb2, 1, 0, 146, 0, 2, 3, 4}, // (subframe number) 1,4,7
+{0xa2, 0xb2, 1, 0, 341, 0, 2, 3, 4}, // (subframe number) 0,2,4,6,8
+{0xa2, 0xb2, 1, 0, 1023, 0, 2, 3, 4}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xa3, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xa3, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xa3, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xa3, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xa3, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xa3, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xa3, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
+{0xa3, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
+{0xa3, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xa3, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
+{0xa3, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
+{0xa3, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
+{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xa3, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
+{0xa3, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
+{0xa3, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7
+{0xa3, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
+{0xa3, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
+{0xa3, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xa3, -1, 1, 0, 682, 0, 2, 2, 6}, // (subframe number) 1,3,5,7,9
+{0xa3, 0xb3, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
+{0xa3, 0xb3, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xa3, 0xb3, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
+{0xa3, 0xb3, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
+{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xa3, 0xb3, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
+{0xa3, 0xb3, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
+{0xa3, 0xb3, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
+{0xa3, 0xb3, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
+{0xa3, 0xb3, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xb1, -1, 16, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 16, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xb1, -1, 8, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xb1, -1, 4, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xb1, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
+{0xb1, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xb1, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
+{0xb1, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
+{0xb1, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
+{0xb1, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xb1, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
+{0xb1, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
+{0xb1, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7
+{0xb1, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
+{0xb1, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
+{0xb1, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xb1, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9
+{0xb4, -1, 16, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 16, 1, 16, 0, 2, 1, 12}, // (subframe number) 4
+{0xb4, -1, 8, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 8, 1, 16, 0, 2, 1, 12}, // (subframe number) 4
+{0xb4, -1, 4, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 4, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
+{0xb4, -1, 4, 1, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 2, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 2, 0, 2, 0, 2, 1, 12}, // (subframe number) 1
+{0xb4, -1, 2, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
+{0xb4, -1, 2, 0, 128, 0, 2, 1, 12}, // (subframe number) 7
+{0xb4, -1, 1, 0, 2, 0, 2, 1, 12}, // (subframe number) 1
+{0xb4, -1, 1, 0, 16, 0, 2, 1, 12}, // (subframe number) 4
+{0xb4, -1, 1, 0, 128, 0, 2, 1, 12}, // (subframe number) 7
+{0xb4, -1, 1, 0, 66, 0, 2, 1, 12}, // (subframe number) 1,6
+{0xb4, -1, 1, 0, 132, 0, 2, 1, 12}, // (subframe number) 2,7
+{0xb4, -1, 1, 0, 528, 0, 2, 1, 12}, // (subframe number) 4,9
+{0xb4, -1, 1, 0, 146, 0, 2, 1, 12}, // (subframe number) 1,4,7
+{0xb4, -1, 1, 0, 341, 0, 2, 1, 12}, // (subframe number) 0,2,4,6,8
+{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xb4, -1, 1, 0, 682, 0, 2, 1, 12}, // (subframe number) 1,3,5,7,9
+{0xc0, -1, 8, 1, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xc0, -1, 4, 1, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xc0, -1, 4, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xc0, -1, 2, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xc0, -1, 2, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
+{0xc0, -1, 2, 0, 16, 0, 2, 7, 2}, // (subframe number) 4
+{0xc0, -1, 2, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
+{0xc0, -1, 1, 0, 16, 0, 1, 7, 2}, // (subframe number) 4
+{0xc0, -1, 1, 0, 66, 0, 1, 7, 2}, // (subframe number) 1,6
+{0xc0, -1, 1, 0, 528, 0, 1, 7, 2}, // (subframe number) 4,9
+{0xc0, -1, 1, 0, 2, 0, 2, 7, 2}, // (subframe number) 1
+{0xc0, -1, 1, 0, 128, 0, 2, 7, 2}, // (subframe number) 7
+{0xc0, -1, 1, 0, 132, 0, 2, 7, 2}, // (subframe number) 2,7
+{0xc0, -1, 1, 0, 146, 0, 2, 7, 2}, // (subframe number) 1,4,7
+{0xc0, -1, 1, 0, 341, 0, 2, 7, 2}, // (subframe number) 0,2,4,6,8
+{0xc0, -1, 1, 0, 1023, 0, 2, 7, 2}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xc0, -1, 1, 0, 682, 0, 2, 7, 2}, // (subframe number) 1,3,5,7,9
+{0xc2, -1, 16, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xc2, -1, 16, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xc2, -1, 8, 1, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xc2, -1, 8, 1, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xc2, -1, 4, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xc2, -1, 4, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xc2, -1, 2, 1, 580, 0, 2, 2, 6}, // (subframe number) 2,6,9
+{0xc2, -1, 2, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
+{0xc2, -1, 2, 0, 16, 0, 2, 2, 6}, // (subframe number) 4
+{0xc2, -1, 2, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
+{0xc2, -1, 1, 0, 16, 0, 1, 2, 6}, // (subframe number) 4
+{0xc2, -1, 1, 0, 66, 0, 1, 2, 6}, // (subframe number) 1,6
+{0xc2, -1, 1, 0, 528, 0, 1, 2, 6}, // (subframe number) 4,9
+{0xc2, -1, 1, 0, 2, 0, 2, 2, 6}, // (subframe number) 1
+{0xc2, -1, 1, 0, 128, 0, 2, 2, 6}, // (subframe number) 7
+{0xc2, -1, 1, 0, 132, 0, 2, 2, 6}, // (subframe number) 2,7
+{0xc2, -1, 1, 0, 146, 0, 2, 2, 6}, // (subframe number) 1,4,7
+{0xc2, -1, 1, 0, 341, 0, 2, 2, 6}, // (subframe number) 0,2,4,6,8
+{0xc2, -1, 1, 0, 1023, 0, 2, 2, 6}, // (subframe number) 0,1,2,3,4,5,6,7,8,9
+{0xc2, -1, 1, 0, 682, 0, 2, 2, 6} // (subframe number) 1,3,5,7,9
+};
+// Table 6.3.3.2-3: Random access configurations for FR1 and unpaired spectrum
+int64_t table_6_3_3_2_3_prachConfig_Index [256][9] = {
+//format, format, x, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
+{0, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
+{0, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4)
+{0, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
+{0, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8)
+{0, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
+{0, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6)
+{0, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5)
+{0, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
+{0, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3)
+{0, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2)
+{0, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6)
+{0, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6)
+{0, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9)
+{0, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8)
+{0, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7)
+{0, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9)
+{0, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9)
+{0, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9)
+{0, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9)
+{0, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9)
+{0, -1, 1, 0, 960, 0, -1, -1, 0}, // (subrame number 6,7,8,9)
+{0, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9)
+{0, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9)
+{1, -1, 16, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
+{1, -1, 8, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
+{1, -1, 4, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
+{1, -1, 2, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
+{1, -1, 2, 1, 128, 0, -1, -1, 0}, // (subrame number 7)
+{1, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
+{2, -1, 16, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
+{2, -1, 8, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
+{2, -1, 4, 1, 64, 0, -1, -1, 0}, // (subrame number 6)
+{2, -1, 2, 0, 64, 7, -1, -1, 0}, // (subrame number 6)
+{2, -1, 2, 1, 64, 7, -1, -1, 0}, // (subrame number 6)
+{2, -1, 1, 0, 64, 7, -1, -1, 0}, // (subrame number 6)
+{3, -1, 16, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 8, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 4, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 2, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 2, 1, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 2, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
+{3, -1, 2, 1, 16, 0, -1, -1, 0}, // (subrame number 4)
+{3, -1, 1, 0, 512, 0, -1, -1, 0}, // (subrame number 9)
+{3, -1, 1, 0, 256, 0, -1, -1, 0}, // (subrame number 8)
+{3, -1, 1, 0, 128, 0, -1, -1, 0}, // (subrame number 7)
+{3, -1, 1, 0, 64, 0, -1, -1, 0}, // (subrame number 6)
+{3, -1, 1, 0, 32, 0, -1, -1, 0}, // (subrame number 5)
+{3, -1, 1, 0, 16, 0, -1, -1, 0}, // (subrame number 4)
+{3, -1, 1, 0, 8, 0, -1, -1, 0}, // (subrame number 3)
+{3, -1, 1, 0, 4, 0, -1, -1, 0}, // (subrame number 2)
+{3, -1, 1, 0, 66, 0, -1, -1, 0}, // (subrame number 1,6)
+{3, -1, 1, 0, 66, 7, -1, -1, 0}, // (subrame number 1,6)
+{3, -1, 1, 0, 528, 0, -1, -1, 0}, // (subrame number 4,9)
+{3, -1, 1, 0, 264, 0, -1, -1, 0}, // (subrame number 3,8)
+{3, -1, 1, 0, 132, 0, -1, -1, 0}, // (subrame number 2,7)
+{3, -1, 1, 0, 768, 0, -1, -1, 0}, // (subrame number 8,9)
+{3, -1, 1, 0, 784, 0, -1, -1, 0}, // (subrame number 4,8,9)
+{3, -1, 1, 0, 536, 0, -1, -1, 0}, // (subrame number 3,4,9)
+{3, -1, 1, 0, 896, 0, -1, -1, 0}, // (subrame number 7,8,9)
+{3, -1, 1, 0, 792, 0, -1, -1, 0}, // (subrame number 3,4,8,9)
+{3, -1, 1, 0, 594, 0, -1, -1, 0}, // (subrame number 1,4,6,9)
+{3, -1, 1, 0, 682, 0, -1, -1, 0}, // (subrame number 1,3,5,7,9)
+{0xa1, -1, 16, 1, 512, 0, 2, 6, 2}, // (subrame number 9)
+{0xa1, -1, 8, 1, 512, 0, 2, 6, 2}, // (subrame number 9)
+{0xa1, -1, 4, 1, 512, 0, 1, 6, 2}, // (subrame number 9)
+{0xa1, -1, 2, 1, 512, 0, 1, 6, 2}, // (subrame number 9)
+{0xa1, -1, 2, 1, 528, 7, 1, 3, 2}, // (subrame number 4,9)
+{0xa1, -1, 2, 1, 640, 7, 1, 3, 2}, // (subrame number 7,9)
+{0xa1, -1, 2, 1, 640, 0, 1, 6, 2}, // (subrame number 7,9)
+{0xa1, -1, 2, 1, 768, 0, 2, 6, 2}, // (subrame number 8,9)
+{0xa1, -1, 2, 1, 528, 0, 2, 6, 2}, // (subrame number 4,9)
+{0xa1, -1, 2, 1, 924, 0, 1, 6, 2}, // (subrame number 2,3,4,7,8,9)
+{0xa1, -1, 1, 0, 512, 0, 2, 6, 2}, // (subrame number 9)
+{0xa1, -1, 1, 0, 512, 7, 1, 3, 2}, // (subrame number 9)
+{0xa1, -1, 1, 0, 512, 0, 1, 6, 2}, // (subrame number 9)
+{0xa1, -1, 1, 0, 768, 0, 2, 6, 2}, // (subrame number 8,9)
+{0xa1, -1, 1, 0, 528, 0, 1, 6, 2}, // (subrame number 4,9)
+{0xa1, -1, 1, 0, 640, 7, 1, 3, 2}, // (subrame number 7,9)
+{0xa1, -1, 1, 0, 792, 0, 1, 6, 2}, // (subrame number 3,4,8,9)
+{0xa1, -1, 1, 0, 792, 0, 2, 6, 2}, // (subrame number 3,4,8,9)
+{0xa1, -1, 1, 0, 682, 0, 1, 6, 2}, // (subrame number 1,3,5,7,9)
+{0xa1, -1, 1, 0, 1023, 7, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xa2, -1, 16, 1, 512, 0, 2, 3, 4}, // (subrame number 9)
+{0xa2, -1, 8, 1, 512, 0, 2, 3, 4}, // (subrame number 9)
+{0xa2, -1, 4, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
+{0xa2, -1, 2, 1, 640, 0, 1, 3, 4}, // (subrame number 7,9)
+{0xa2, -1, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9)
+{0xa2, -1, 2, 1, 640, 9, 1, 1, 4}, // (subrame number 7,9)
+{0xa2, -1, 2, 1, 528, 9, 1, 1, 4}, // (subrame number 4,9)
+{0xa2, -1, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9)
+{0xa2, -1, 16, 1, 924, 0, 1, 3, 4}, // (subrame number 2,3,4,7,8,9)
+{0xa2, -1, 1, 0, 4, 0, 1, 3, 4}, // (subrame number 2)
+{0xa2, -1, 1, 0, 128, 0, 1, 3, 4}, // (subrame number 7)
+{0xa2, -1, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
+{0xa2, -1, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9)
+{0xa2, -1, 1, 0, 512, 9, 1, 1, 4}, // (subrame number 9)
+{0xa2, -1, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9)
+{0xa2, -1, 1, 0, 132, 0, 1, 3, 4}, // (subrame number 2,7)
+{0xa2, -1, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9)
+{0xa2, -1, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9)
+{0xa2, -1, 1, 0, 640, 9, 1, 1, 4}, // (subrame number 7,9)
+{0xa2, -1, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9)
+{0xa2, -1, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9)
+{0xa2, -1, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9)
+{0xa2, -1, 1, 0, 1023, 9, 1, 1, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xa3, -1, 16, 1, 512, 0, 2, 2, 6}, // (subrame number 9)
+{0xa3, -1, 8, 1, 512, 0, 2, 2, 6}, // (subrame number 9)
+{0xa3, -1, 4, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
+{0xa3, -1, 2, 1, 528, 7, 1, 1, 6}, // (subrame number 4,9)
+{0xa3, -1, 2, 1, 640, 7, 1, 1, 6}, // (subrame number 7,9)
+{0xa3, -1, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9)
+{0xa3, -1, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9)
+{0xa3, -1, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9)
+{0xa3, -1, 2, 1, 924, 0, 1, 2, 6}, // (subrame number 2,3,4,7,8,9)
+{0xa3, -1, 1, 0, 4, 0, 1, 2, 6}, // (subrame number 2)
+{0xa3, -1, 1, 0, 128, 0, 1, 2, 6}, // (subrame number 7)
+{0xa3, -1, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
+{0xa3, -1, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9)
+{0xa3, -1, 1, 0, 512, 7, 1, 1, 6}, // (subrame number 9)
+{0xa3, -1, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9)
+{0xa3, -1, 1, 0, 132, 0, 1, 2, 6}, // (subrame number 2,7)
+{0xa3, -1, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9)
+{0xa3, -1, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9)
+{0xa3, -1, 1, 0, 640, 7, 1, 1, 6}, // (subrame number 7,9)
+{0xa3, -1, 1, 0, 792, 0, 1, 2, 6}, // (subrame number 3,4,8,9)
+{0xa3, -1, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9)
+{0xa3, -1, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9)
+{0xa3, -1, 1, 0, 1023, 7, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xb1, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xb1, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xb1, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
+{0xb1, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
+{0xb1, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
+{0xb1, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
+{0xb1, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
+{0xb1, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xb1, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
+{0xb1, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
+{0xb1, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
+{0xb1, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
+{0xb4, -1, 16, 1, 512, 0, 2, 1, 12}, // (subrame number 9)
+{0xb4, -1, 8, 1, 512, 0, 2, 1, 12}, // (subrame number 9)
+{0xb4, -1, 4, 1, 512, 2, 1, 1, 12}, // (subrame number 9)
+{0xb4, -1, 2, 1, 512, 0, 1, 1, 12}, // (subrame number 9)
+{0xb4, -1, 2, 1, 512, 2, 1, 1, 12}, // (subrame number 9)
+{0xb4, -1, 2, 1, 640, 2, 1, 1, 12}, // (subrame number 7,9)
+{0xb4, -1, 2, 1, 528, 2, 1, 1, 12}, // (subrame number 4,9)
+{0xb4, -1, 2, 1, 528, 0, 2, 1, 12}, // (subrame number 4,9)
+{0xb4, -1, 2, 1, 768, 0, 2, 1, 12}, // (subrame number 8,9)
+{0xb4, -1, 2, 1, 924, 0, 1, 1, 12}, // (subrame number 2,3,4,7,8,9)
+{0xb4, -1, 1, 0, 2, 0, 1, 1, 12}, // (subrame number 1)
+{0xb4, -1, 1, 0, 4, 0, 1, 1, 12}, // (subrame number 2)
+{0xb4, -1, 1, 0, 16, 0, 1, 1, 12}, // (subrame number 4)
+{0xb4, -1, 1, 0, 128, 0, 1, 1, 12}, // (subrame number 7)
+{0xb4, -1, 1, 0, 512, 0, 1, 1, 12}, // (subrame number 9)
+{0xb4, -1, 1, 0, 512, 2, 1, 1, 12}, // (subrame number 9)
+{0xb4, -1, 1, 0, 512, 0, 2, 1, 12}, // (subrame number 9)
+{0xb4, -1, 1, 0, 528, 2, 1, 1, 12}, // (subrame number 4,9)
+{0xb4, -1, 1, 0, 640, 2, 1, 1, 12}, // (subrame number 7,9)
+{0xb4, -1, 1, 0, 768, 0, 2, 1, 12}, // (subrame number 8,9)
+{0xb4, -1, 1, 0, 792, 2, 1, 1, 12}, // (subrame number 3,4,8,9)
+{0xb4, -1, 1, 0, 682, 2, 1, 1, 12}, // (subrame number 1,3,5,7,9)
+{0xb4, -1, 1, 0, 1023, 0, 2, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xb4, -1, 1, 0, 1023, 2, 1, 1, 12}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xc0, -1, 16, 1, 512, 2, 2, 6, 2}, // (subrame number 9)
+{0xc0, -1, 8, 1, 512, 2, 2, 6, 2}, // (subrame number 9)
+{0xc0, -1, 4, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xc0, -1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xc0, -1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9)
+{0xc0, -1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
+{0xc0, -1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9)
+{0xc0, -1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
+{0xc0, -1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
+{0xc0, -1, 2, 1, 924, 2, 1, 6, 2}, // (subrame number 2,3,4,7,8,9)
+{0xc0, -1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
+{0xc0, -1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
+{0xc0, -1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xc0, -1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
+{0xc0, -1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
+{0xc0, -1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
+{0xc0, -1, 1, 0, 792, 2, 1, 6, 2}, // (subrame number 3,4,8,9)
+{0xc0, -1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9)
+{0xc0, -1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
+{0xc0, -1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xc2, -1, 16, 1, 512, 2, 2, 2, 6}, // (subrame number 9)
+{0xc2, -1, 8, 1, 512, 2, 2, 2, 6}, // (subrame number 9)
+{0xc2, -1, 4, 1, 512, 2, 1, 2, 6}, // (subrame number 9)
+{0xc2, -1, 2, 1, 512, 2, 1, 2, 6}, // (subrame number 9)
+{0xc2, -1, 2, 1, 768, 2, 2, 2, 6}, // (subrame number 8,9)
+{0xc2, -1, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9)
+{0xc2, -1, 2, 1, 640, 8, 1, 1, 6}, // (subrame number 7,9)
+{0xc2, -1, 2, 1, 528, 8, 1, 1, 6}, // (subrame number 4,9)
+{0xc2, -1, 2, 1, 528, 2, 2, 2, 6}, // (subrame number 4,9)
+{0xc2, -1, 2, 1, 924, 2, 1, 2, 6}, // (subrame number 2,3,4,7,8,9)
+{0xc2, -1, 8, 1, 512, 8, 2, 1, 6}, // (subrame number 9)
+{0xc2, -1, 4, 1, 512, 8, 1, 1, 6}, // (subrame number 9)
+{0xc2, -1, 1, 0, 512, 2, 2, 2, 6}, // (subrame number 9)
+{0xc2, -1, 1, 0, 512, 8, 1, 1, 6}, // (subrame number 9)
+{0xc2, -1, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9)
+{0xc2, -1, 1, 0, 768, 2, 2, 2, 6}, // (subrame number 8,9)
+{0xc2, -1, 1, 0, 528, 2, 1, 2, 6}, // (subrame number 4,9)
+{0xc2, -1, 1, 0, 640, 8, 1, 1, 6}, // (subrame number 7,9)
+{0xc2, -1, 1, 0, 792, 2, 1, 2, 6}, // (subrame number 3,4,8,9)
+{0xc2, -1, 1, 0, 792, 2, 2, 2, 6}, // (subrame number 3,4,8,9)
+{0xc2, -1, 1, 0, 682, 2, 1, 2, 6}, // (subrame number 1,3,5,7,9)
+{0xc2, -1, 1, 0, 1023, 8, 1, 1, 6}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xa1, 0xb1, 2, 1, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xa1, 0xb1, 2, 1, 528, 8, 1, 3, 2}, // (subrame number 4,9)
+{0xa1, 0xb1, 2, 1, 640, 8, 1, 3, 2}, // (subrame number 7,9)
+{0xa1, 0xb1, 2, 1, 640, 2, 1, 6, 2}, // (subrame number 7,9)
+{0xa1, 0xb1, 2, 1, 528, 2, 2, 6, 2}, // (subrame number 4,9)
+{0xa1, 0xb1, 2, 1, 768, 2, 2, 6, 2}, // (subrame number 8,9)
+{0xa1, 0xb1, 1, 0, 512, 2, 2, 6, 2}, // (subrame number 9)
+{0xa1, 0xb1, 1, 0, 512, 8, 1, 3, 2}, // (subrame number 9)
+{0xa1, 0xb1, 1, 0, 512, 2, 1, 6, 2}, // (subrame number 9)
+{0xa1, 0xb1, 1, 0, 768, 2, 2, 6, 2}, // (subrame number 8,9)
+{0xa1, 0xb1, 1, 0, 528, 2, 1, 6, 2}, // (subrame number 4,9)
+{0xa1, 0xb1, 1, 0, 640, 8, 1, 3, 2}, // (subrame number 7,9)
+{0xa1, 0xb1, 1, 0, 792, 2, 2, 6, 2}, // (subrame number 3,4,8,9)
+{0xa1, 0xb1, 1, 0, 682, 2, 1, 6, 2}, // (subrame number 1,3,5,7,9)
+{0xa1, 0xb1, 1, 0, 1023, 8, 1, 3, 2}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xa2, 0xb2, 2, 1, 512, 0, 1, 3, 4}, // (subrame number 9)
+{0xa2, 0xb2, 2, 1, 528, 6, 1, 2, 4}, // (subrame number 4,9)
+{0xa2, 0xb2, 2, 1, 640, 6, 1, 2, 4}, // (subrame number 7,9)
+{0xa2, 0xb2, 2, 1, 528, 0, 2, 3, 4}, // (subrame number 4,9)
+{0xa2, 0xb2, 2, 1, 768, 0, 2, 3, 4}, // (subrame number 8,9)
+{0xa2, 0xb2, 1, 0, 512, 0, 2, 3, 4}, // (subrame number 9)
+{0xa2, 0xb2, 1, 0, 512, 6, 1, 2, 4}, // (subrame number 9)
+{0xa2, 0xb2, 1, 0, 512, 0, 1, 3, 4}, // (subrame number 9)
+{0xa2, 0xb2, 1, 0, 768, 0, 2, 3, 4}, // (subrame number 8,9)
+{0xa2, 0xb2, 1, 0, 528, 0, 1, 3, 4}, // (subrame number 4,9)
+{0xa2, 0xb2, 1, 0, 640, 6, 1, 2, 4}, // (subrame number 7,9)
+{0xa2, 0xb2, 1, 0, 792, 0, 1, 3, 4}, // (subrame number 3,4,8,9)
+{0xa2, 0xb2, 1, 0, 792, 0, 2, 3, 4}, // (subrame number 3,4,8,9)
+{0xa2, 0xb2, 1, 0, 682, 0, 1, 3, 4}, // (subrame number 1,3,5,7,9)
+{0xa2, 0xb2, 1, 0, 1023, 6, 1, 2, 4}, // (subrame number 0,1,2,3,4,5,6,7,8,9)
+{0xa3, 0xb3, 2, 1, 512, 0, 1, 2, 6}, // (subrame number 9)
+{0xa3, 0xb3, 2, 1, 528, 2, 1, 2, 6}, // (subrame number 4,9)
+{0xa3, 0xb3, 2, 1, 640, 0, 1, 2, 6}, // (subrame number 7,9)
+{0xa3, 0xb3, 2, 1, 640, 2, 1, 2, 6}, // (subrame number 7,9)
+{0xa3, 0xb3, 2, 1, 528, 0, 2, 2, 6}, // (subrame number 4,9)
+{0xa3, 0xb3, 2, 1, 768, 0, 2, 2, 6}, // (subrame number 8,9)
+{0xa3, 0xb3, 1, 0, 512, 0, 2, 2, 6}, // (subrame number 9)
+{0xa3, 0xb3, 1, 0, 512, 2, 1, 2, 6}, // (subrame number 9)
+{0xa3, 0xb3, 1, 0, 512, 0, 1, 2, 6}, // (subrame number 9)
+{0xa3, 0xb3, 1, 0, 768, 0, 2, 2, 6}, // (subrame number 8,9)
+{0xa3, 0xb3, 1, 0, 528, 0, 1, 2, 6}, // (subrame number 4,9)
+{0xa3, 0xb3, 1, 0, 640, 2, 1, 2, 6}, // (subrame number 7,9)
+{0xa3, 0xb3, 1, 0, 792, 0, 2, 2, 6}, // (subrame number 3,4,8,9)
+{0xa3, 0xb3, 1, 0, 682, 0, 1, 2, 6}, // (subrame number 1,3,5,7,9)
+{0xa3, 0xb3, 1, 0, 1023, 2, 1, 2, 6} // (subrame number 0,1,2,3,4,5,6,7,8,9)
+};
+// Table 6.3.3.2-4: Random access configurations for FR2 and unpaired spectrum
+int64_t table_6_3_3_2_4_prachConfig_Index [256][10] = {
+//format, format, x, y, y, SFN_nbr, star_symb, slots_sfn, occ_slot, duration
+{0xa1, -1, 16, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 16, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 8, 1, 2, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39)
+{0xa1, -1, 8, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 8, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 4, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 4, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 4, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 2, 1, -1, 551911719040, 0, 2, 6, 2}, // (subframe number :7,15,23,31,39)
+{0xa1, -1, 2, 1, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 2, 1, -1, 567489872400, 0, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 2, 1, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 1, 0, -1, 549756338176, 7, 1, 3, 2}, // (subframe number :19,39)
+{0xa1, -1, 1, 0, -1, 168, 0, 1, 6, 2}, // (subframe number :3,5,7)
+{0xa1, -1, 1, 0, -1, 567489331200, 7, 1, 3, 2}, // (subframe number :24,29,34,39)
+{0xa1, -1, 1, 0, -1, 550293209600, 7, 2, 3, 2}, // (subframe number :9,19,29,39)
+{0xa1, -1, 1, 0, -1, 687195422720, 0, 1, 6, 2}, // (subframe number :17,19,37,39)
+{0xa1, -1, 1, 0, -1, 550293209600, 0, 2, 6, 2}, // (subframe number :9,19,29,39)
+{0xa1, -1, 1, 0, -1, 567489872400, 0, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 1, 0, -1, 567489872400, 7, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, -1, 1, 0, -1, 10920, 7, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
+{0xa1, -1, 1, 0, -1, 586405642240, 7, 1, 3, 2}, // (subframe number :23,27,31,35,39)
+{0xa1, -1, 1, 0, -1, 551911719040, 0, 1, 6, 2}, // (subframe number :7,15,23,31,39)
+{0xa1, -1, 1, 0, -1, 586405642240, 0, 1, 6, 2}, // (subframe number :23,27,31,35,39)
+{0xa1, -1, 1, 0, -1, 965830828032, 7, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xa1, -1, 1, 0, -1, 586406201480, 7, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 1, 0, -1, 586406201480, 0, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, -1, 1, 0, -1, 733007751850, 0, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
+{0xa1, -1, 1, 0, -1, 1099511627775, 7, 1, 3, 2}, // (subframe number :0,1,2,…,39)
+{0xa2, -1, 16, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 16, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 8, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 8, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 8, 1, 2, 550293209600, 0, 2, 3, 4}, // (subframe number :9,19,29,39)
+{0xa2, -1, 4, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 4, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 4, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 2, 1, -1, 551911719040, 0, 2, 3, 4}, // (subframe number :7,15,23,31,39)
+{0xa2, -1, 2, 1, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 2, 1, -1, 567489872400, 0, 2, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 2, 1, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 1, 0, -1, 549756338176, 5, 1, 2, 4}, // (subframe number :19,39)
+{0xa2, -1, 1, 0, -1, 168, 0, 1, 3, 4}, // (subframe number :3,5,7)
+{0xa2, -1, 1, 0, -1, 567489331200, 5, 1, 2, 4}, // (subframe number :24,29,34,39)
+{0xa2, -1, 1, 0, -1, 550293209600, 5, 2, 2, 4}, // (subframe number :9,19,29,39)
+{0xa2, -1, 1, 0, -1, 687195422720, 0, 1, 3, 4}, // (subframe number :17,19,37,39)
+{0xa2, -1, 1, 0, -1, 550293209600, 0, 2, 3, 4}, // (subframe number :9, 19, 29, 39)
+{0xa2, -1, 1, 0, -1, 551911719040, 0, 1, 3, 4}, // (subframe number :7,15,23,31,39)
+{0xa2, -1, 1, 0, -1, 586405642240, 5, 1, 2, 4}, // (subframe number :23,27,31,35,39)
+{0xa2, -1, 1, 0, -1, 586405642240, 0, 1, 3, 4}, // (subframe number :23,27,31,35,39)
+{0xa2, -1, 1, 0, -1, 10920, 5, 1, 2, 4}, // (subframe number :3,5,7,9,11,13)
+{0xa2, -1, 1, 0, -1, 10920, 0, 1, 3, 4}, // (subframe number :3,5,7,9,11,13)
+{0xa2, -1, 1, 0, -1, 567489872400, 5, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 1, 0, -1, 567489872400, 0, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, -1, 1, 0, -1, 965830828032, 5, 2, 2, 4}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xa2, -1, 1, 0, -1, 586406201480, 5, 1, 2, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 1, 0, -1, 586406201480, 0, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, -1, 1, 0, -1, 733007751850, 0, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39)
+{0xa2, -1, 1, 0, -1, 1099511627775, 5, 1, 2, 4}, // (subframe number :0,1,2,…,39)
+{0xa3, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
+{0xa3, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 1, 0, -1, 549756338176, 7, 1, 1, 6}, // (subframe number :19,39)
+{0xa3, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7)
+{0xa3, -1, 1, 0, -1, 10752, 2, 1, 2, 6}, // (subframe number :9,11,13)
+{0xa3, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39)
+{0xa3, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39)
+{0xa3, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39)
+{0xa3, -1, 1, 0, -1, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
+{0xa3, -1, 1, 0, -1, 551911719040, 0, 1, 2, 6}, // (subframe number :7,15,23,31,39)
+{0xa3, -1, 1, 0, -1, 586405642240, 7, 1, 1, 6}, // (subframe number :23,27,31,35,39)
+{0xa3, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39)
+{0xa3, -1, 1, 0, -1, 10920, 0, 1, 2, 6}, // (subframe number :3,5,7,9,11,13)
+{0xa3, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13)
+{0xa3, -1, 1, 0, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 1, 0, -1, 567489872400, 7, 1, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xa3, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39)
+{0xa3, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39)
+{0xb1, -1, 16, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 8, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 8, 1, 2, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
+{0xb1, -1, 4, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 2, 1, -1, 567489872400, 2, 2, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 2, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xb1, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
+{0xb1, -1, 1, 0, -1, 168, 2, 1, 6, 2}, // (subframe number :3,5,7)
+{0xb1, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39)
+{0xb1, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39)
+{0xb1, -1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39)
+{0xb1, -1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
+{0xb1, -1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39)
+{0xb1, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
+{0xb1, -1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39)
+{0xb1, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
+{0xb1, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb1, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xb1, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xb1, -1, 1, 0, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xb1, -1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
+{0xb1, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39)
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+{0xb4, -1, 8, 1, 2, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39)
+{0xb4, -1, 4, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
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+{0xb4, -1, 2, 1, -1, 551911719040, 2, 2, 1, 12}, // (subframe number :7,15,23,31,39)
+{0xb4, -1, 2, 1, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb4, -1, 2, 1, -1, 567489872400, 0, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb4, -1, 2, 1, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xb4, -1, 1, 0, -1, 549756338176, 2, 2, 1, 12}, // (subframe number :19, 39)
+{0xb4, -1, 1, 0, -1, 687195422720, 0, 1, 1, 12}, // (subframe number :17, 19, 37, 39)
+{0xb4, -1, 1, 0, -1, 567489331200, 2, 1, 1, 12}, // (subframe number :24,29,34,39)
+{0xb4, -1, 1, 0, -1, 550293209600, 2, 2, 1, 12}, // (subframe number :9,19,29,39)
+{0xb4, -1, 1, 0, -1, 550293209600, 0, 2, 1, 12}, // (subframe number :9,19,29,39)
+{0xb4, -1, 1, 0, -1, 551911719040, 0, 1, 1, 12}, // (subframe number :7,15,23,31,39)
+{0xb4, -1, 1, 0, -1, 551911719040, 0, 2, 1, 12}, // (subframe number :7,15,23,31,39)
+{0xb4, -1, 1, 0, -1, 586405642240, 0, 1, 1, 12}, // (subframe number :23,27,31,35,39)
+{0xb4, -1, 1, 0, -1, 586405642240, 2, 2, 1, 12}, // (subframe number :23,27,31,35,39)
+{0xb4, -1, 1, 0, -1, 698880, 0, 1, 1, 12}, // (subframe number :9,11,13,15,17,19)
+{0xb4, -1, 1, 0, -1, 10920, 2, 1, 1, 12}, // (subframe number :3,5,7,9,11,13)
+{0xb4, -1, 1, 0, -1, 567489872400, 0, 1, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb4, -1, 1, 0, -1, 567489872400, 2, 2, 1, 12}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xb4, -1, 1, 0, -1, 965830828032, 2, 2, 1, 12}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xb4, -1, 1, 0, -1, 586406201480, 0, 1, 1, 12}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
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+{0xb4, -1, 1, 0, -1, 44739240, 2, 1, 1, 12}, // (subframe number :3, 5, 7, …, 23,25)
+{0xb4, -1, 1, 0, -1, 44739240, 0, 2, 1, 12}, // (subframe number :3, 5, 7, …, 23,25)
+{0xb4, -1, 1, 0, -1, 733007751850, 0, 1, 1, 12}, // (subframe number :1,3,5,7,…,37,39)
+{0xb4, -1, 1, 0, -1, 1099511627775, 2, 1, 1, 12}, // (subframe number :0, 1, 2,…, 39)
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+{0xc0, -1, 4, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
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+{0xc0, -1, 2, 1, -1, 551911719040, 0, 2, 7, 2}, // (subframe number :7,15,23,31,39)
+{0xc0, -1, 2, 1, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc0, -1, 2, 1, -1, 567489872400, 0, 2, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc0, -1, 2, 1, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc0, -1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
+{0xc0, -1, 1, 0, -1, 168, 0, 1, 7, 2}, // (subframe number :3,5,7)
+{0xc0, -1, 1, 0, -1, 567489331200, 8, 1, 3, 2}, // (subframe number :24,29,34,39)
+{0xc0, -1, 1, 0, -1, 550293209600, 8, 2, 3, 2}, // (subframe number :9,19,29,39)
+{0xc0, -1, 1, 0, -1, 687195422720, 0, 1, 7, 2}, // (subframe number :17,19,37,39)
+{0xc0, -1, 1, 0, -1, 550293209600, 0, 2, 7, 2}, // (subframe number :9,19,29,39)
+{0xc0, -1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
+{0xc0, -1, 1, 0, -1, 551911719040, 0, 1, 7, 2}, // (subframe number :7,15,23,31,39)
+{0xc0, -1, 1, 0, -1, 586405642240, 0, 1, 7, 2}, // (subframe number :23,27,31,35,39)
+{0xc0, -1, 1, 0, -1, 10920, 8, 1, 3, 2}, // (subframe number :3,5,7,9,11,13)
+{0xc0, -1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc0, -1, 1, 0, -1, 567489872400, 0, 1, 7, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc0, -1, 1, 0, -1, 965830828032, 8, 2, 3, 2}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xc0, -1, 1, 0, -1, 586406201480, 8, 1, 3, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc0, -1, 1, 0, -1, 586406201480, 0, 1, 7, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc0, -1, 1, 0, -1, 733007751850, 0, 1, 7, 2}, // (subframe number :1,3,5,7,…,37,39)
+{0xc0, -1, 1, 0, -1, 1099511627775, 8, 1, 3, 2}, // (subframe number :0,1,2,…,39)
+{0xc2, -1, 16, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 16, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 8, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 8, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 8, 1, 2, 550293209600, 0, 2, 2, 6}, // (subframe number :9,19,29,39)
+{0xc2, -1, 4, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 4, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 4, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 2, 1, -1, 551911719040, 2, 2, 2, 6}, // (subframe number :7,15,23,31,39)
+{0xc2, -1, 2, 1, -1, 567489872400, 0, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 2, 1, -1, 567489872400, 0, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 2, 1, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39)
+{0xc2, -1, 1, 0, -1, 168, 0, 1, 2, 6}, // (subframe number :3,5,7)
+{0xc2, -1, 1, 0, -1, 567489331200, 7, 1, 1, 6}, // (subframe number :24,29,34,39)
+{0xc2, -1, 1, 0, -1, 550293209600, 7, 2, 1, 6}, // (subframe number :9,19,29,39)
+{0xc2, -1, 1, 0, -1, 687195422720, 0, 1, 2, 6}, // (subframe number :17,19,37,39)
+{0xc2, -1, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39)
+{0xc2, -1, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39)
+{0xc2, -1, 1, 0, -1, 10920, 7, 1, 1, 6}, // (subframe number :3,5,7,9,11,13)
+{0xc2, -1, 1, 0, -1, 586405642240, 7, 2, 1, 6}, // (subframe number :23,27,31,35,39)
+{0xc2, -1, 1, 0, -1, 586405642240, 0, 1, 2, 6}, // (subframe number :23,27,31,35,39)
+{0xc2, -1, 1, 0, -1, 567489872400, 7, 2, 1, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xc2, -1, 1, 0, -1, 965830828032, 7, 2, 1, 6}, // (subframe number :13,14,15, 29,30,31,37,38,39)
+{0xc2, -1, 1, 0, -1, 586406201480, 7, 1, 1, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 1, 0, -1, 586406201480, 0, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xc2, -1, 1, 0, -1, 733007751850, 0, 1, 2, 6}, // (subframe number :1,3,5,7,…,37,39)
+{0xc2, -1, 1, 0, -1, 1099511627775, 7, 1, 1, 6}, // (subframe number :0,1,2,…,39)
+{0xa1, 0xb1, 16, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, 0xb1, 16, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, 0xb1, 8, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, 0xb1, 8, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, 0xb1, 4, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, 0xb1, 4, 1, -1, 586406201480, 2, 1, 6, 2}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa1, 0xb1, 2, 1, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, 0xb1, 1, 0, -1, 549756338176, 8, 1, 3, 2}, // (subframe number :19,39)
+{0xa1, 0xb1, 1, 0, -1, 550293209600, 8, 1, 3, 2}, // (subframe number :9,19,29,39)
+{0xa1, 0xb1, 1, 0, -1, 687195422720, 2, 1, 6, 2}, // (subframe number :17,19,37,39)
+{0xa1, 0xb1, 1, 0, -1, 550293209600, 2, 2, 6, 2}, // (subframe number :9,19,29,39)
+{0xa1, 0xb1, 1, 0, -1, 586405642240, 8, 1, 3, 2}, // (subframe number :23,27,31,35,39)
+{0xa1, 0xb1, 1, 0, -1, 551911719040, 2, 1, 6, 2}, // (subframe number :7,15,23,31,39)
+{0xa1, 0xb1, 1, 0, -1, 586405642240, 2, 1, 6, 2}, // (subframe number :23,27,31,35,39)
+{0xa1, 0xb1, 1, 0, -1, 567489872400, 8, 1, 3, 2}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa1, 0xb1, 1, 0, -1, 567489872400, 2, 1, 6, 2}, // (subframe number :4,9,14,19,24,29,34,39)
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+{0xa1, 0xb1, 1, 0, -1, 733007751850, 2, 1, 6, 2}, // (subframe number :1,3,5,7,…,37,39)
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+{0xa2, 0xb2, 16, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, 0xb2, 8, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, 0xb2, 8, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, 0xb2, 4, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, 0xb2, 4, 1, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, 0xb2, 2, 1, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, 0xb2, 1, 0, -1, 549756338176, 6, 1, 2, 4}, // (subframe number :19,39)
+{0xa2, 0xb2, 1, 0, -1, 550293209600, 6, 1, 2, 4}, // (subframe number :9,19,29,39)
+{0xa2, 0xb2, 1, 0, -1, 687195422720, 2, 1, 3, 4}, // (subframe number :17,19,37,39)
+{0xa2, 0xb2, 1, 0, -1, 550293209600, 2, 2, 3, 4}, // (subframe number :9,19,29,39)
+{0xa2, 0xb2, 1, 0, -1, 586405642240, 6, 1, 2, 4}, // (subframe number :23,27,31,35,39)
+{0xa2, 0xb2, 1, 0, -1, 551911719040, 2, 1, 3, 4}, // (subframe number :7,15,23,31,39)
+{0xa2, 0xb2, 1, 0, -1, 586405642240, 2, 1, 3, 4}, // (subframe number :23,27,31,35,39)
+{0xa2, 0xb2, 1, 0, -1, 567489872400, 6, 1, 2, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, 0xb2, 1, 0, -1, 567489872400, 2, 1, 3, 4}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa2, 0xb2, 1, 0, -1, 586406201480, 2, 1, 3, 4}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa2, 0xb2, 1, 0, -1, 733007751850, 2, 1, 3, 4}, // (subframe number :1,3,5,7,…,37,39)
+{0xa3, 0xb3, 16, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 16, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, 0xb3, 8, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 8, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, 0xb3, 4, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 4, 1, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, 0xb3, 2, 1, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 1, 0, -1, 549756338176, 2, 1, 2, 6}, // (subframe number :19,39)
+{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 1, 2, 6}, // (subframe number :9,19,29,39)
+{0xa3, 0xb3, 1, 0, -1, 687195422720, 2, 1, 2, 6}, // (subframe number :17,19,37,39)
+{0xa3, 0xb3, 1, 0, -1, 550293209600, 2, 2, 2, 6}, // (subframe number :9,19,29,39)
+{0xa3, 0xb3, 1, 0, -1, 551911719040, 2, 1, 2, 6}, // (subframe number :7,15,23,31,39)
+{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 1, 2, 6}, // (subframe number :23,27,31,35,39)
+{0xa3, 0xb3, 1, 0, -1, 586405642240, 2, 2, 2, 6}, // (subframe number :23,27,31,35,39)
+{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 1, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 1, 0, -1, 567489872400, 2, 2, 2, 6}, // (subframe number :4,9,14,19,24,29,34,39)
+{0xa3, 0xb3, 1, 0, -1, 586406201480, 2, 1, 2, 6}, // (subframe number :3,7,11,15,19,23,27,31,35,39)
+{0xa3, 0xb3, 1, 0, -1, 733007751850, 2, 1, 2, 6} // (subframe number :1,3,5,7,…,37,39)
+};
+
+
+int get_format0(uint8_t index,
+ uint8_t unpaired){
+
+ uint16_t format;
+ if (unpaired)
+ format = table_6_3_3_2_3_prachConfig_Index[index][0];
+ else
+ format = table_6_3_3_2_2_prachConfig_Index[index][0];
+
+ return format;
+}
+
+void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss,
+ uint16_t *slot_period,
+ uint16_t *offset) {
+
+ switch(ss->monitoringSlotPeriodicityAndOffset->present) {
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1:
+ *slot_period = 1;
+ *offset = 0;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2:
+ *slot_period = 2;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl4:
+ *slot_period = 4;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl4;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl5:
+ *slot_period = 5;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl5;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl8:
+ *slot_period = 8;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl8;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl10:
+ *slot_period = 10;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl10;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl16:
+ *slot_period = 16;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl16;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl20:
+ *slot_period = 20;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl20;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl40:
+ *slot_period = 40;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl40;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl80:
+ *slot_period = 80;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl80;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl160:
+ *slot_period = 160;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl160;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl320:
+ *slot_period = 320;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl320;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl640:
+ *slot_period = 640;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl640;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1280:
+ *slot_period = 1280;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl1280;
+ break;
+ case NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl2560:
+ *slot_period = 2560;
+ *offset = ss->monitoringSlotPeriodicityAndOffset->choice.sl2560;
+ break;
+ default:
+ AssertFatal(1==0,"Invalid monitoring slot periodicity and offset value\n");
+ break;
+ }
+}
+
+int get_nr_prach_info_from_index(uint8_t index,
+ int frame,
+ int slot,
+ uint32_t pointa,
+ uint8_t mu,
+ uint8_t unpaired,
+ uint16_t *format,
+ uint8_t *start_symbol,
+ uint8_t *N_t_slot,
+ uint8_t *N_dur) {
+
+ int x,y;
+ int64_t s_map;
+ uint8_t format2 = 0xff;
+
+ if (pointa > 2016666) { //FR2
+ int y2;
+ uint8_t slot_60khz;
+ x = table_6_3_3_2_4_prachConfig_Index[index][2];
+ y = table_6_3_3_2_4_prachConfig_Index[index][3];
+ y2 = table_6_3_3_2_4_prachConfig_Index[index][4];
+ // checking n_sfn mod x = y
+ if ( (frame%x)==y || (frame%x)==y2 ) {
+ slot_60khz = slot >> (mu-2); // in table slots are numbered wrt 60kHz
+ s_map = table_6_3_3_2_4_prachConfig_Index[index][5];
+ if ( ((s_map>>slot_60khz)&0x01) ) {
+ if (mu == 3) {
+ if ( (table_6_3_3_2_4_prachConfig_Index[index][7] == 1) && (slot%2 == 0) )
+ return 0; // no prach in even slots @ 120kHz for 1 prach per 60khz slot
+ }
+ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
+ *start_symbol = table_6_3_3_2_4_prachConfig_Index[index][6];
+ *N_t_slot = table_6_3_3_2_4_prachConfig_Index[index][8];
+ *N_dur = table_6_3_3_2_4_prachConfig_Index[index][9];
+ if (table_6_3_3_2_4_prachConfig_Index[index][1] != -1)
+ format2 = (uint8_t) table_6_3_3_2_4_prachConfig_Index[index][1];
+ *format = ((uint8_t) table_6_3_3_2_4_prachConfig_Index[index][0]) | (format2<<8);
+ LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame,
+ slot,
+ index,
+ pointa,
+ mu,
+ unpaired,
+ *start_symbol,
+ *N_t_slot,
+ *N_dur);
+ }
+ return 1;
+ }
+ else
+ return 0; // no prach in current slot
+ }
+ else
+ return 0; // no prach in current frame
+ }
+ else {
+ uint8_t subframe;
+ if (unpaired) {
+ x = table_6_3_3_2_3_prachConfig_Index[index][2];
+ y = table_6_3_3_2_3_prachConfig_Index[index][3];
+ if ( (frame%x)==y ) {
+ subframe = slot >> mu;
+ s_map = table_6_3_3_2_3_prachConfig_Index[index][4];
+ if ( (s_map>>subframe)&0x01 ) {
+ if (mu == 1) {
+ if ( (table_6_3_3_2_3_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) )
+ return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
+ }
+ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
+ *start_symbol = table_6_3_3_2_3_prachConfig_Index[index][5];
+ *N_t_slot = table_6_3_3_2_3_prachConfig_Index[index][7];
+ *N_dur = table_6_3_3_2_3_prachConfig_Index[index][8];
+ if (table_6_3_3_2_3_prachConfig_Index[index][1] != -1)
+ format2 = (uint8_t) table_6_3_3_2_3_prachConfig_Index[index][1];
+ *format = ((uint8_t) table_6_3_3_2_3_prachConfig_Index[index][0]) | (format2<<8);
+ LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d (col 6 %ld) absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame,
+ slot,
+ index, table_6_3_3_2_3_prachConfig_Index[index][6],
+ pointa,
+ mu,
+ unpaired,
+ *start_symbol,
+ *N_t_slot,
+ *N_dur);
+ }
+ return 1;
+ }
+ else
+ return 0; // no prach in current slot
+ }
+ else
+ return 0; // no prach in current frame
+ }
+ else { // FDD
+ x = table_6_3_3_2_2_prachConfig_Index[index][2];
+ y = table_6_3_3_2_2_prachConfig_Index[index][3];
+ if ( (frame%x)==y ) {
+ subframe = slot >> mu;
+ s_map = table_6_3_3_2_2_prachConfig_Index[index][4];
+ if ( (s_map>>subframe)&0x01 ) {
+ if (mu == 1) {
+ if ( (table_6_3_3_2_2_prachConfig_Index[index][6] <= 1) && (slot%2 == 0) )
+ return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
+ }
+ if (start_symbol != NULL && N_t_slot != NULL && N_dur != NULL && format != NULL){
+ *start_symbol = table_6_3_3_2_2_prachConfig_Index[index][5];
+ *N_t_slot = table_6_3_3_2_2_prachConfig_Index[index][7];
+ *N_dur = table_6_3_3_2_2_prachConfig_Index[index][8];
+ if (table_6_3_3_2_2_prachConfig_Index[index][1] != -1)
+ format2 = (uint8_t) table_6_3_3_2_2_prachConfig_Index[index][1];
+ *format = ((uint8_t) table_6_3_3_2_2_prachConfig_Index[index][0]) | (format2<<8);
+ LOG_D(MAC,"Frame %d slot %d: Getting PRACH info from index %d absoluteFrequencyPointA %u mu %u frame_type %u start_symbol %u N_t_slot %u N_dur %u \n", frame,
+ slot,
+ index,
+ pointa,
+ mu,
+ unpaired,
+ *start_symbol,
+ *N_t_slot,
+ *N_dur);
+ }
+ return 1;
+ }
+ else
+ return 0; // no prach in current slot
+ }
+ else
+ return 0; // no prach in current frame
+ }
+ }
+}
+
+//Table 6.3.3.1-3: Mapping from logical index i to sequence number u for preamble formats with L_RA = 839
+uint16_t table_63313[838] = {
+129, 710, 140, 699, 120, 719, 210, 629, 168, 671, 84 , 755, 105, 734, 93 , 746, 70 , 769, 60 , 779,
+2 , 837, 1 , 838, 56 , 783, 112, 727, 148, 691, 80 , 759, 42 , 797, 40 , 799, 35 , 804, 73 , 766,
+146, 693, 31 , 808, 28 , 811, 30 , 809, 27 , 812, 29 , 810, 24 , 815, 48 , 791, 68 , 771, 74 , 765,
+178, 661, 136, 703, 86 , 753, 78 , 761, 43 , 796, 39 , 800, 20 , 819, 21 , 818, 95 , 744, 202, 637,
+190, 649, 181, 658, 137, 702, 125, 714, 151, 688, 217, 622, 128, 711, 142, 697, 122, 717, 203, 636,
+118, 721, 110, 729, 89 , 750, 103, 736, 61 , 778, 55 , 784, 15 , 824, 14 , 825, 12 , 827, 23 , 816,
+34 , 805, 37 , 802, 46 , 793, 207, 632, 179, 660, 145, 694, 130, 709, 223, 616, 228, 611, 227, 612,
+132, 707, 133, 706, 143, 696, 135, 704, 161, 678, 201, 638, 173, 666, 106, 733, 83 , 756, 91 , 748,
+66 , 773, 53 , 786, 10 , 829, 9 , 830, 7 , 832, 8 , 831, 16 , 823, 47 , 792, 64 , 775, 57 , 782,
+104, 735, 101, 738, 108, 731, 208, 631, 184, 655, 197, 642, 191, 648, 121, 718, 141, 698, 149, 690,
+216, 623, 218, 621, 152, 687, 144, 695, 134, 705, 138, 701, 199, 640, 162, 677, 176, 663, 119, 720,
+158, 681, 164, 675, 174, 665, 171, 668, 170, 669, 87 , 752, 169, 670, 88 , 751, 107, 732, 81 , 758,
+82 , 757, 100, 739, 98 , 741, 71 , 768, 59 , 780, 65 , 774, 50 , 789, 49 , 790, 26 , 813, 17 , 822,
+13 , 826, 6 , 833, 5 , 834, 33 , 806, 51 , 788, 75 , 764, 99 , 740, 96 , 743, 97 , 742, 166, 673,
+172, 667, 175, 664, 187, 652, 163, 676, 185, 654, 200, 639, 114, 725, 189, 650, 115, 724, 194, 645,
+195, 644, 192, 647, 182, 657, 157, 682, 156, 683, 211, 628, 154, 685, 123, 716, 139, 700, 212, 627,
+153, 686, 213, 626, 215, 624, 150, 689, 225, 614, 224, 615, 221, 618, 220, 619, 127, 712, 147, 692,
+124, 715, 193, 646, 205, 634, 206, 633, 116, 723, 160, 679, 186, 653, 167, 672, 79 , 760, 85 , 754,
+77 , 762, 92 , 747, 58 , 781, 62 , 777, 69 , 770, 54 , 785, 36 , 803, 32 , 807, 25 , 814, 18 , 821,
+11 , 828, 4 , 835, 3 , 836, 19 , 820, 22 , 817, 41 , 798, 38 , 801, 44 , 795, 52 , 787, 45 , 794,
+63 , 776, 67 , 772, 72 , 767, 76 , 763, 94 , 745, 102, 737, 90 , 749, 109, 730, 165, 674, 111, 728,
+209, 630, 204, 635, 117, 722, 188, 651, 159, 680, 198, 641, 113, 726, 183, 656, 180, 659, 177, 662,
+196, 643, 155, 684, 214, 625, 126, 713, 131, 708, 219, 620, 222, 617, 226, 613, 230, 609, 232, 607,
+262, 577, 252, 587, 418, 421, 416, 423, 413, 426, 411, 428, 376, 463, 395, 444, 283, 556, 285, 554,
+379, 460, 390, 449, 363, 476, 384, 455, 388, 451, 386, 453, 361, 478, 387, 452, 360, 479, 310, 529,
+354, 485, 328, 511, 315, 524, 337, 502, 349, 490, 335, 504, 324, 515, 323, 516, 320, 519, 334, 505,
+359, 480, 295, 544, 385, 454, 292, 547, 291, 548, 381, 458, 399, 440, 380, 459, 397, 442, 369, 470,
+377, 462, 410, 429, 407, 432, 281, 558, 414, 425, 247, 592, 277, 562, 271, 568, 272, 567, 264, 575,
+259, 580, 237, 602, 239, 600, 244, 595, 243, 596, 275, 564, 278, 561, 250, 589, 246, 593, 417, 422,
+248, 591, 394, 445, 393, 446, 370, 469, 365, 474, 300, 539, 299, 540, 364, 475, 362, 477, 298, 541,
+312, 527, 313, 526, 314, 525, 353, 486, 352, 487, 343, 496, 327, 512, 350, 489, 326, 513, 319, 520,
+332, 507, 333, 506, 348, 491, 347, 492, 322, 517, 330, 509, 338, 501, 341, 498, 340, 499, 342, 497,
+301, 538, 366, 473, 401, 438, 371, 468, 408, 431, 375, 464, 249, 590, 269, 570, 238, 601, 234, 605,
+257, 582, 273, 566, 255, 584, 254, 585, 245, 594, 251, 588, 412, 427, 372, 467, 282, 557, 403, 436,
+396, 443, 392, 447, 391, 448, 382, 457, 389, 450, 294, 545, 297, 542, 311, 528, 344, 495, 345, 494,
+318, 521, 331, 508, 325, 514, 321, 518, 346, 493, 339, 500, 351, 488, 306, 533, 289, 550, 400, 439,
+378, 461, 374, 465, 415, 424, 270, 569, 241, 598, 231, 608, 260, 579, 268, 571, 276, 563, 409, 430,
+398, 441, 290, 549, 304, 535, 308, 531, 358, 481, 316, 523, 293, 546, 288, 551, 284, 555, 368, 471,
+253, 586, 256, 583, 263, 576, 242, 597, 274, 565, 402, 437, 383, 456, 357, 482, 329, 510, 317, 522,
+307, 532, 286, 553, 287, 552, 266, 573, 261, 578, 236, 603, 303, 536, 356, 483, 355, 484, 405, 434,
+404, 435, 406, 433, 235, 604, 267, 572, 302, 537, 309, 530, 265, 574, 233, 606, 367, 472, 296, 543,
+336, 503, 305, 534, 373, 466, 280, 559, 279, 560, 419, 420, 240, 599, 258, 581, 229, 610
+};
+
+uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config,
+ uint8_t nb_preambles,
+ uint8_t unpaired) {
+
+ uint8_t config_index = rach_config->rach_ConfigGeneric.prach_ConfigurationIndex;
+ uint8_t ncs_index = rach_config->rach_ConfigGeneric.zeroCorrelationZoneConfig;
+ uint16_t format0 = get_format0(config_index, unpaired);
+ uint16_t NCS = get_NCS(ncs_index, format0, rach_config->restrictedSetConfig);
+ uint16_t L_ra = (rach_config->prach_RootSequenceIndex.present==NR_RACH_ConfigCommon__prach_RootSequenceIndex_PR_l139) ? 139 : 839;
+ uint16_t r,u,index,q,d_u,n_shift_ra,n_shift_ra_bar,d_start;
+ uint32_t w;
+ uint8_t found_preambles = 0;
+ uint8_t found_sequences = 0;
+
+ if (rach_config->restrictedSetConfig == 0) {
+ if (NCS == 0) return nb_preambles;
+ else {
+ r = L_ra/NCS;
+ printf(" found_sequences %u\n", (nb_preambles/r));
+ return (nb_preambles/r);
+ }
+ }
+ else{
+ index = rach_config->prach_RootSequenceIndex.choice.l839;
+ while (found_preambles < nb_preambles) {
+ u = table_63313[index%(L_ra-1)];
+
+ q = 0;
+ while (((q*u)%L_ra) != 1) q++;
+ if (q < 420) d_u = q;
+ else d_u = L_ra - q;
+
+ uint16_t n_group_ra = 0;
+ if (rach_config->restrictedSetConfig == 1) {
+ if ( (d_u<280) && (d_u>=NCS) ) {
+ n_shift_ra = d_u/NCS;
+ d_start = (d_u<<1) + (n_shift_ra * NCS);
+ n_group_ra = L_ra/d_start;
+ n_shift_ra_bar = max(0,(L_ra-(d_u<<1)-(n_group_ra*d_start))/L_ra);
+ } else if ( (d_u>=280) && (d_u<=((L_ra - NCS)>>1)) ) {
+ n_shift_ra = (L_ra - (d_u<<1))/NCS;
+ d_start = L_ra - (d_u<<1) + (n_shift_ra * NCS);
+ n_group_ra = d_u/d_start;
+ n_shift_ra_bar = min(n_shift_ra,max(0,(d_u- (n_group_ra*d_start))/NCS));
+ } else {
+ n_shift_ra = 0;
+ n_shift_ra_bar = 0;
+ }
+ w = n_shift_ra*n_group_ra + n_shift_ra_bar;
+ found_preambles += w;
+ found_sequences++;
+ }
+ else {
+ AssertFatal(1==0,"Procedure to find nb of sequences for restricted type B not implemented yet");
+ }
+ }
+ printf(" found_sequences %u\n", found_sequences);
+ return found_sequences;
+ }
+}
+
nr_bandentry_t nr_bandtable[] = {
{1, 1920000, 1980000, 2110000, 2170000, 20, 422000, 100},
@@ -79,6 +1242,47 @@ nr_bandentry_t nr_bandtable[] = {
{261,27500000,28350000,27500000,28350000, 2,2070833, 120}
};
+
+// TS 38.211 Table 6.4.1.1.3-3: PUSCH DMRS positions l' within a slot for single-symbol DMRS and intra-slot frequency hopping disabled.
+// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B.
+// When l' = l0, it is represented by 1
+// E.g. when symbol duration is 12 in colomn 7, value 1057 ('10000100001') which means l' = l0, 5, 10.
+
+int32_t table_6_4_1_1_3_3_pusch_dmrs_positions_l [12][8] = { // Duration in symbols
+{-1, -1, -1, -1, 1, 1, 1, 1}, //<4 // (DMRS l' position)
+{1, 1, 1, 1, 1, 1, 1, 1}, //4 // (DMRS l' position)
+{1, 1, 1, 1, 1, 5, 5, 5}, //5 // (DMRS l' position)
+{1, 1, 1, 1, 1, 5, 5, 5}, //6 // (DMRS l' position)
+{1, 1, 1, 1, 1, 5, 5, 5}, //7 // (DMRS l' position)
+{1, 129, 129, 129, 1, 65, 73, 73}, //8 // (DMRS l' position)
+{1, 129, 129, 129, 1, 65, 73, 73}, //9 // (DMRS l' position)
+{1, 513, 577, 577, 1, 257, 273, 585}, //10 // (DMRS l' position)
+{1, 513, 577, 577, 1, 257, 273, 585}, //11 // (DMRS l' position)
+{1, 513, 577, 2337, 1, 1025, 1057, 585}, //12 // (DMRS l' position)
+{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //13 // (DMRS l' position)
+{1, 2049, 2177, 2337, 1, 1025, 1057, 585}, //14 // (DMRS l' position)
+};
+
+
+// TS 38.211 Table 6.4.1.1.3-4: PUSCH DMRS positions l' within a slot for double-symbol DMRS and intra-slot frequency hopping disabled.
+// The first 4 colomns are PUSCH mapping type A and the last 4 colomns are PUSCH mapping type B.
+// When l' = l0, it is represented by 1
+
+int32_t table_6_4_1_1_3_4_pusch_dmrs_positions_l [12][8] = { // Duration in symbols
+{-1, -1, -1, -1, -1, -1, -1, -1}, //<4 // (DMRS l' position)
+{1, 1, -1, -1, -1, -1, -1, -1}, //4 // (DMRS l' position)
+{1, 1, -1, -1, 1, 1, -1, -1}, //5 // (DMRS l' position)
+{1, 1, -1, -1, 1, 1, -1, -1}, //6 // (DMRS l' position)
+{1, 1, -1, -1, 1, 1, -1, -1}, //7 // (DMRS l' position)
+{1, 1, -1, -1, 1, 33, -1, -1}, //8 // (DMRS l' position)
+{1, 1, -1, -1, 1, 33, -1, -1}, //9 // (DMRS l' position)
+{1, 257, -1, -1, 1, 129, -1, -1}, //10 // (DMRS l' position)
+{1, 257, -1, -1, 1, 129, -1, -1}, //11 // (DMRS l' position)
+{1, 257, -1, -1, 1, 513, -1, -1}, //12 // (DMRS l' position)
+{1, 1025, -1, -1, 1, 513, -1, -1}, //13 // (DMRS l' position)
+{1, 1025, -1, -1, 1, 513, -1, -1}, //14 // (DMRS l' position)
+};
+
#define NR_BANDTABLE_SIZE (sizeof(nr_bandtable)/sizeof(nr_bandentry_t))
void get_band(uint64_t downlink_frequency,
@@ -332,13 +1536,23 @@ int32_t get_nr_uldl_offset(int nr_bandP)
void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
- int x_overhead) {
+ int x_overhead,
+ uint8_t numdmrscdmgroupnodata,
+ uint8_t tb_scaling) {
LOG_D(MAC, "TBS calculation\n");
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_rel15 = &pdsch_pdu->pdsch_pdu_rel15;
uint16_t N_PRB_oh = x_overhead;
- uint8_t N_PRB_DMRS = (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1)?6:4; //This only works for antenna port 1000
+ uint8_t N_PRB_DMRS;
+ if (pdsch_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) {
+ // if no data in dmrs cdm group is 1 only even REs have no data
+ // if no data in dmrs cdm group is 2 both odd and even REs have no data
+ N_PRB_DMRS = numdmrscdmgroupnodata*6;
+ }
+ else {
+ N_PRB_DMRS = numdmrscdmgroupnodata*4;
+ }
uint8_t N_sh_symb = pdsch_rel15->NrOfSymbols;
uint8_t Imcs = pdsch_rel15->mcsIndex[0];
uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh;
@@ -360,8 +1574,9 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
R,
pdsch_rel15->rbSize,
N_sh_symb,
- N_PRB_DMRS,
+ N_PRB_DMRS, // FIXME // This should be multiplied by the number of dmrs symbols
N_PRB_oh,
+ tb_scaling,
pdsch_rel15->nrOfLayers)>>3;
pdsch_rel15->targetCodeRate[0] = R;
@@ -517,11 +1732,172 @@ int get_num_dmrs(uint16_t dmrs_mask ) {
return(num_dmrs);
}
-uint16_t nr_dci_size(nr_dci_format_t format,
+// Table 5.1.2.2.1-1 38.214
+uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
+
+ AssertFatal(bwp_size<276,"BWP Size > 275\n");
+
+ if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
+ if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
+ if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
+ else return 16;
+}
+
+uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
+
+ uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
+
+ return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
+}
+
+uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
+
+ uint8_t nbitsA = 0;
+ uint8_t nbitsB = 0;
+ uint8_t type,length,nbits;
+
+ if (typeA != NULL) {
+ type = (typeA->choice.setup->dmrs_Type==NULL) ? 1:2;
+ length = (typeA->choice.setup->maxLength==NULL) ? 1:2;
+ nbitsA = type + length + 2;
+ if (typeB == NULL) return nbitsA;
+ }
+ if (typeB != NULL) {
+ type = (typeB->choice.setup->dmrs_Type==NULL) ? 1:2;
+ length = (typeB->choice.setup->maxLength==NULL) ? 1:2;
+ nbitsB = type + length + 2;
+ if (typeA == NULL) return nbitsB;
+ }
+
+ nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
+ return nbits;
+}
+
+
+/*******************************************************************
+*
+* NAME : get_l0_ul
+*
+* PARAMETERS : mapping_type : PUSCH mapping type
+* dmrs_typeA_position : higher layer parameter
+*
+* RETURN : demodulation reference signal for PUSCH
+*
+* DESCRIPTION : see TS 38.211 V15.4.0 Demodulation reference signals for PUSCH
+*
+*********************************************************************/
+
+uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position) {
+
+ return ((mapping_type==typeA)?dmrs_typeA_position:0);
+
+}
+
+int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength) {
+
+ uint8_t row, colomn;
+ int32_t l_prime;
+
+ colomn = additional_pos;
+
+ if (mapping_type == typeB)
+ colomn += 4;
+
+ if (duration_in_symbols < 4)
+ row = 0;
+ else
+ row = duration_in_symbols - 3;
+
+ if (pusch_maxLength == pusch_len1)
+ l_prime = table_6_4_1_1_3_3_pusch_dmrs_positions_l[row][colomn];
+ else
+ l_prime = table_6_4_1_1_3_4_pusch_dmrs_positions_l[row][colomn];
+
+ AssertFatal(l_prime>0,"invalid l_prime < 0\n");
+
+ return l_prime;
+}
+
+/*******************************************************************
+*
+* NAME : get_L_ptrs
+*
+* PARAMETERS : mcs(i) higher layer parameter in PTRS-UplinkConfig
+* I_mcs MCS index used for PUSCH
+* mcs_table 0 for table 5.1.3.1-1, 1 for table 5.1.3.1-1
+*
+* RETURN : the parameter L_ptrs
+*
+* DESCRIPTION : 3GPP TS 38.214 section 6.2.3.1
+*
+*********************************************************************/
+
+uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table) {
+
+ uint8_t mcs4;
+
+ if(mcs_table == 0)
+ mcs4 = 29;
+ else
+ mcs4 = 28;
+
+ if (I_mcs < mcs1) {
+ LOG_I(PHY, "PUSH PT-RS is not present.\n");
+ return -1;
+ } else if (I_mcs >= mcs1 && I_mcs < mcs2)
+ return 2;
+ else if (I_mcs >= mcs2 && I_mcs < mcs3)
+ return 1;
+ else if (I_mcs >= mcs3 && I_mcs < mcs4)
+ return 0;
+ else {
+ LOG_I(PHY, "PT-RS time-density determination is obtained from the DCI for the same transport block in the initial transmission\n");
+ return -1;
+ }
+}
+
+/*******************************************************************
+*
+* NAME : get_K_ptrs
+*
+* PARAMETERS : ptrs_UplinkConfig PTRS uplink configuration
+* N_RB number of RBs scheduled for PUSCH
+*
+* RETURN : the parameter K_ptrs
+*
+* DESCRIPTION : 3GPP TS 38.214 6.2.3 Table 6.2.3.1-2
+*
+*********************************************************************/
+
+uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB) {
+
+ if (N_RB < nrb0) {
+ LOG_I(PHY,"PUSH PT-RS is not present.\n");
+ return -1;
+ } else if (N_RB >= nrb0 && N_RB < nrb1)
+ return 0;
+ else
+ return 1;
+}
+
+uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc,
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ dci_pdu_rel15_t *dci_pdu,
+ nr_dci_format_t format,
nr_rnti_type_t rnti_type,
- uint16_t N_RB) {
+ uint16_t N_RB,
+ int bwp_id) {
uint16_t size = 0;
+ uint16_t numRBG = 0;
+ long rbg_size_config;
+ int num_entries = 0;
+ int pusch_antenna_ports = 1; // TODO hardcoded number of antenna ports for pusch
+ NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
+ NR_PDSCH_Config_t *pdsch_config = bwp->bwp_Dedicated->pdsch_Config->choice.setup;
+ NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup;
+ NR_SRS_Config_t *srs_config = ubwp->bwp_Dedicated->srs_Config->choice.setup;
switch(format) {
/*Only sizes for 0_0 and 1_0 are correct at the moment*/
@@ -529,30 +1905,199 @@ uint16_t nr_dci_size(nr_dci_format_t format,
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
- size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
+ size += nr_dci_size(scc,secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB, bwp_id) - size; // Padding to match 1_0 size
// UL/SUL indicator assumed to be 0
break;
case NR_UL_DCI_FORMAT_0_1:
- /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, SRS request 2 --17
- size += 17;
+ /// fixed: Format identifier 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2, ULSCH indicator 1 --16
+ size += 16;
// Carrier indicator
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
+ dci_pdu->carrier_indicator.nbits=3;
+ size += dci_pdu->carrier_indicator.nbits;
+ }
// UL/SUL indicator
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL) {
+ dci_pdu->carrier_indicator.nbits=1;
+ size += dci_pdu->ul_sul_indicator.nbits;
+ }
// BWP Indicator
+ uint8_t n_ul_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
+ if (n_ul_bwp < 2)
+ dci_pdu->bwp_indicator.nbits = n_ul_bwp;
+ else
+ dci_pdu->bwp_indicator.nbits = 2;
+ size += dci_pdu->bwp_indicator.nbits;
// Freq domain assignment
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pusch_Config->choice.setup->rbg_Size != NULL)
+ rbg_size_config = 1;
+ else
+ rbg_size_config = 0;
+ numRBG = getNRBG(NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+ NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+ rbg_size_config);
+ if (pusch_Config->resourceAllocation == 0)
+ dci_pdu->frequency_domain_assignment.nbits = numRBG;
+ else if (pusch_Config->resourceAllocation == 1)
+ dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ else
+ dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
+ size += dci_pdu->frequency_domain_assignment.nbits;
// Time domain assignment
- // VRB to PRB mapping
+ if (pusch_Config->pusch_TimeDomainAllocationList==NULL) {
+ if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList==NULL)
+ num_entries = 16; // num of entries in default table
+ else
+ num_entries = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count;
+ }
+ else
+ num_entries = pusch_Config->pusch_TimeDomainAllocationList->choice.setup->list.count;
+ dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
+ size += dci_pdu->time_domain_assignment.nbits;
// Frequency Hopping flag
+ if ((pusch_Config->frequencyHopping!=NULL) && (pusch_Config->resourceAllocation != NR_PUSCH_Config__resourceAllocation_resourceAllocationType0)) {
+ dci_pdu->frequency_hopping_flag.nbits = 1;
+ size += 1;
+ }
// 1st DAI
+ if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook==NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic)
+ dci_pdu->dai[0].nbits = 2;
+ else
+ dci_pdu->dai[0].nbits = 1;
+ size += dci_pdu->dai[0].nbits;
// 2nd DAI
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) { //TODO not sure about that
+ dci_pdu->dai[1].nbits = 2;
+ size += dci_pdu->dai[1].nbits;
+ }
// SRS resource indicator
+ if (pusch_Config->txConfig != NULL){
+ int count=0;
+ if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){
+ for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
+ if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_codebook)
+ count++;
+ }
+ if (count>1) {
+ dci_pdu->srs_resource_indicator.nbits = 1;
+ size += dci_pdu->srs_resource_indicator.nbits;
+ }
+ }
+ else {
+ int lmin,Lmax = 0;
+ int lsum = 0;
+ if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig != NULL) {
+ if ( secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers != NULL)
+ Lmax = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers;
+ else
+ AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
+ }
+ else
+ AssertFatal(1==0,"MIMO on PUSCH not supported, maxMIMO_Layers needs to be set to 1\n");
+ for (int i=0; i<srs_config->srs_ResourceSetToAddModList->list.count; i++) {
+ if (srs_config->srs_ResourceSetToAddModList->list.array[i]->usage == NR_SRS_ResourceSet__usage_nonCodebook)
+ count++;
+ if (count < Lmax) lmin = count;
+ else lmin = Lmax;
+ for (int k=1;k<=lmin;k++) {
+ lsum += binomial(count,k);
+ }
+ }
+ dci_pdu->srs_resource_indicator.nbits = (int)ceil(log2(lsum));
+ size += dci_pdu->srs_resource_indicator.nbits;
+ }
+ }
// Precoding info and number of layers
+ long transformPrecoder;
+ if (pusch_Config->transformPrecoder == NULL){
+ // if transform precoder is null, apply the values from msg3
+ if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL)
+ transformPrecoder = 1;
+ else
+ transformPrecoder = 0;
+ }
+ else
+ transformPrecoder = *pusch_Config->transformPrecoder;
+ if (pusch_Config->txConfig != NULL){
+ if (*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook){
+ if (pusch_antenna_ports > 1) {
+ if (pusch_antenna_ports == 4) {
+ if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank>1))
+ dci_pdu->precoding_information.nbits = 6-(*pusch_Config->codebookSubset);
+ else {
+ if(*pusch_Config->codebookSubset == NR_PUSCH_Config__codebookSubset_nonCoherent)
+ dci_pdu->precoding_information.nbits = 2;
+ else
+ dci_pdu->precoding_information.nbits = 5-(*pusch_Config->codebookSubset);
+ }
+ }
+ else {
+ AssertFatal(pusch_antenna_ports==2,"Not valid number of antenna ports");
+ if ((transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) && (*pusch_Config->maxRank==2))
+ dci_pdu->precoding_information.nbits = 4-(*pusch_Config->codebookSubset);
+ else
+ dci_pdu->precoding_information.nbits = 3-(*pusch_Config->codebookSubset);
+ }
+ }
+ }
+ }
+ size += dci_pdu->precoding_information.nbits;
// Antenna ports
+ NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = NULL;
+ int xa=0;
+ int xb=0;
+ if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL){
+ NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup;
+ xa = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder);
+ }
+ if(pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL){
+ NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup;
+ xb = ul_ant_bits(NR_DMRS_UplinkConfig,transformPrecoder);
+ }
+ if (xa>xb)
+ dci_pdu->antenna_ports.nbits = xa;
+ else
+ dci_pdu->antenna_ports.nbits = xb;
+ size += dci_pdu->antenna_ports.nbits;
+ // SRS request
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL)
+ dci_pdu->srs_request.nbits = 2;
+ else
+ dci_pdu->srs_request.nbits = 3;
+ size += dci_pdu->srs_request.nbits;
// CSI request
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig != NULL) {
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize != NULL) {
+ dci_pdu->csi_request.nbits = *secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup->reportTriggerSize;
+ size += dci_pdu->csi_request.nbits;
+ }
+ }
// CBGTI
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) {
+ int num = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock;
+ dci_pdu->cbgti.nbits = 2 + (num<<1);
+ size += dci_pdu->cbgti.nbits;
+ }
// PTRS - DMRS association
+ if ( (NR_DMRS_UplinkConfig->phaseTrackingRS == NULL && transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) ||
+ transformPrecoder == NR_PUSCH_Config__transformPrecoder_enabled || (*pusch_Config->maxRank==1) )
+ dci_pdu->ptrs_dmrs_association.nbits = 0;
+ else
+ dci_pdu->ptrs_dmrs_association.nbits = 2;
+ size += dci_pdu->ptrs_dmrs_association.nbits;
// beta offset indicator
+ if (pusch_Config->uci_OnPUSCH!=NULL){
+ if (pusch_Config->uci_OnPUSCH->choice.setup->betaOffsets->present == NR_UCI_OnPUSCH__betaOffsets_PR_dynamic) {
+ dci_pdu->beta_offset_indicator.nbits = 2;
+ size += dci_pdu->beta_offset_indicator.nbits;
+ }
+ }
// DMRS sequence init
+ if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled) {
+ dci_pdu->dmrs_sequence_initialization.nbits = 1;
+ size += dci_pdu->dmrs_sequence_initialization.nbits;
+ }
break;
case NR_DL_DCI_FORMAT_1_0:
@@ -562,29 +2107,122 @@ uint16_t nr_dci_size(nr_dci_format_t format,
break;
case NR_DL_DCI_FORMAT_1_1:
+ // General note: 0 bits condition is ignored as default nbits is 0.
+ // Format identifier
+ size = 1;
// Carrier indicator
- size += 1; // Format identifier
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
+ dci_pdu->carrier_indicator.nbits=3;
+ size += dci_pdu->carrier_indicator.nbits;
+ }
// BWP Indicator
+ uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
+ if (n_dl_bwp < 2)
+ dci_pdu->bwp_indicator.nbits = n_dl_bwp;
+ else
+ dci_pdu->bwp_indicator.nbits = 2;
+ size += dci_pdu->bwp_indicator.nbits;
// Freq domain assignment
- // Time domain assignment
- // VRB to PRB mapping
+ rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
+ numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+ NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
+ rbg_size_config);
+ if (pdsch_config->resourceAllocation == 0)
+ dci_pdu->frequency_domain_assignment.nbits = numRBG;
+ else if (pdsch_config->resourceAllocation == 1)
+ dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
+ else
+ dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
+ size += dci_pdu->frequency_domain_assignment.nbits;
+ // Time domain assignment (see table 5.1.2.1.1-1 in 38.214
+ if (pdsch_config->pdsch_TimeDomainAllocationList==NULL) {
+ if (bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList==NULL)
+ num_entries = 16; // num of entries in default table
+ else
+ num_entries = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count;
+ }
+ else
+ num_entries = pdsch_config->pdsch_TimeDomainAllocationList->choice.setup->list.count;
+ dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
+ size += dci_pdu->time_domain_assignment.nbits;
+ // VRB to PRB mapping
+ if ((pdsch_config->resourceAllocation == 1) && (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver != NULL)) {
+ dci_pdu->vrb_to_prb_mapping.nbits = 1;
+ size += dci_pdu->vrb_to_prb_mapping.nbits;
+ }
// PRB bundling size indicator
+ if (pdsch_config->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling) {
+ dci_pdu->prb_bundling_size_indicator.nbits = 1;
+ size += dci_pdu->prb_bundling_size_indicator.nbits;
+ }
// Rate matching indicator
+ NR_RateMatchPatternGroup_t *group1 = pdsch_config->rateMatchPatternGroup1;
+ NR_RateMatchPatternGroup_t *group2 = pdsch_config->rateMatchPatternGroup2;
+ if ((group1 != NULL) && (group2 != NULL))
+ dci_pdu->rate_matching_indicator.nbits = 2;
+ if ((group1 != NULL) != (group2 != NULL))
+ dci_pdu->rate_matching_indicator.nbits = 1;
+ size += dci_pdu->rate_matching_indicator.nbits;
// ZP CSI-RS trigger
- /// TB1- MCS 5, NDI 1, RV 2
+ if (pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL) {
+ uint8_t nZP = pdsch_config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count;
+ dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
+ }
+ size += dci_pdu->zp_csi_rs_trigger.nbits;
+ // TB1- MCS 5, NDI 1, RV 2
size += 8;
// TB2
- size += 4 ; // HARQ PID
+ long *maxCWperDCI = pdsch_config->maxNrofCodeWordsScheduledByDCI;
+ if ((maxCWperDCI != NULL) && (*maxCWperDCI == 2)) {
+ size += 8;
+ }
+ // HARQ PID
+ size += 4;
// DAI
- size += 2; // TPC PUCCH
- size += 3; // PUCCH resource indicator
- size += 3; // PDSCH to HARQ timing indicator
+ if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic) { // FIXME in case of more than one serving cell
+ dci_pdu->dai[0].nbits = 2;
+ size += dci_pdu->dai[0].nbits;
+ }
+ // TPC PUCCH
+ size += 2;
+ // PUCCH resource indicator
+ size += 3;
+ // PDSCH to HARQ timing indicator
+ uint8_t I = ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
+ dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
+ size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
// Antenna ports
+ NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeA;
+ NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = pdsch_config->dmrs_DownlinkForPDSCH_MappingTypeB;
+ dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB);
+ size += dci_pdu->antenna_ports.nbits;
// Tx Config Indication
- size += 2; // SRS request
+ long *isTciEnable = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI;
+ if (isTciEnable != NULL) {
+ dci_pdu->transmission_configuration_indication.nbits = 3;
+ size += dci_pdu->transmission_configuration_indication.nbits;
+ }
+ // SRS request
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink==NULL)
+ dci_pdu->srs_request.nbits = 2;
+ else
+ dci_pdu->srs_request.nbits = 3;
+ size += dci_pdu->srs_request.nbits;
// CBGTI
- // CBGFI
- size += 1; // DMRS sequence init
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL) {
+ uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
+ long *maxCWperDCI_rrc = pdsch_config->maxNrofCodeWordsScheduledByDCI;
+ uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
+ dci_pdu->cbgti.nbits = maxCBGperTB * maxCW;
+ size += dci_pdu->cbgti.nbits;
+ // CBGFI
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) {
+ dci_pdu->cbgfi.nbits = 1;
+ size += dci_pdu->cbgfi.nbits;
+ }
+ }
+ // DMRS sequence init
+ size += 1;
break;
case NR_DL_DCI_FORMAT_2_0:
@@ -606,6 +2244,27 @@ uint16_t nr_dci_size(nr_dci_format_t format,
return size;
}
+int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig, long transformPrecoder) {
+
+ uint8_t type,maxl;
+ if(NR_DMRS_UplinkConfig->dmrs_Type == NULL)
+ type = 1;
+ else
+ type = 2;
+ if(NR_DMRS_UplinkConfig->maxLength == NULL)
+ maxl = 1;
+ else
+ maxl = 2;
+ if (transformPrecoder == NR_PUSCH_Config__transformPrecoder_disabled)
+ return( maxl+type+1);
+ else {
+ if (type==1)
+ return (maxl<<1);
+ else
+ AssertFatal(1==0,"DMRS type not valid for this choice");
+ }
+}
+
int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000};
int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) {
@@ -746,3 +2405,20 @@ int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,i
AssertFatal(1==0,"Shouldn't get here\n");
return(-1);
}
+
+
+int binomial(int n, int k) {
+ int c = 1, i;
+
+ if (k > n-k)
+ k = n-k;
+
+ for (i = 1; i <= k; i++, n--) {
+ if (c/i > UINT_MAX/n) // return 0 on overflow
+ return 0;
+
+ c = c / i * n + c % i * n / i;
+ }
+ return c;
+}
+
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
similarity index 50%
rename from openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h
rename to openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
index 6b043963b01816d9e710fa50522814bea7081fbc..a5e38bf128ef95029970069d88414bdeaace756a 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h
+++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
@@ -32,13 +32,9 @@
#ifndef __LAYER2_NR_MAC_COMMON_H__
#define __LAYER2_NR_MAC_COMMON_H__
-uint16_t config_bandwidth(int mu, int nb_rb, int nr_band);
-
-uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn);
-
-uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw);
-
-int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols);
+#include "NR_PDSCH-Config.h"
+#include "NR_CellGroupConfig.h"
+#include "nr_mac.h"
typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0,
@@ -67,4 +63,58 @@ typedef enum {
NR_RNTI_TPC_SRS
} nr_rnti_type_t;
+uint16_t config_bandwidth(int mu, int nb_rb, int nr_band);
+
+void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type);
+
+uint64_t from_nrarfcn(int nr_bandP, uint8_t scs_index, uint32_t dl_nrarfcn);
+
+uint32_t to_nrarfcn(int nr_bandP, uint64_t dl_CarrierFreq, uint8_t scs_index, uint32_t bw);
+
+int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols);
+
+int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
+
+int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
+
+uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc,
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ dci_pdu_rel15_t *dci_pdu,
+ nr_dci_format_t format,
+ nr_rnti_type_t rnti_type,
+ uint16_t N_RB,
+ int bwp_id);
+
+void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss,
+ uint16_t *slot_period,
+ uint16_t *offset);
+
+int get_nr_prach_info_from_index(uint8_t index,
+ int frame,
+ int slot,
+ uint32_t pointa,
+ uint8_t mu,
+ uint8_t unpaired,
+ uint16_t *format,
+ uint8_t *start_symbol,
+ uint8_t *N_t_slot,
+ uint8_t *N_dur);
+
+uint8_t compute_nr_root_seq(NR_RACH_ConfigCommon_t *rach_config,
+ uint8_t nb_preambles,
+ uint8_t unpaired);
+
+int ul_ant_bits(NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig,long transformPrecoder);
+
+int get_format0(uint8_t index, uint8_t unpaired);
+
+uint16_t get_NCS(uint8_t index, uint16_t format, uint8_t restricted_set_config);
+
+int get_num_dmrs(uint16_t dmrs_mask );
+uint8_t get_l0_ul(uint8_t mapping_type, uint8_t dmrs_typeA_position);
+int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmrs_AdditionalPosition_t additional_pos, pusch_maxLength_t pusch_maxLength);
+
+uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table);
+uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB);
+
#endif
diff --git a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
index 2cfce4766f7234e50249f2560e725cfd8f89a7d8..5c714e4a93a9e7558fcfc30cb44b694d1c67ae40 100644
--- a/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
+++ b/openair2/LAYER2/NR_MAC_COMMON/nr_mac_extern.h
@@ -19,12 +19,12 @@
* contact@openairinterface.org
*/
-/*! \file extern.h
+/*! \file nr_mac_extern.h
* \brief NR mac externs
-* \author G. Casati
+* \author Navid Nikaein, Raymond Knopp, Guido Casati
* \date 2019
* \version 1.0
-* \email guido.casati@iis.fraunhofer.de
+* \email navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de
* @ingroup _mac
*/
@@ -32,10 +32,10 @@
#ifndef __NR_MAC_EXTERN_H__
#define __NR_MAC_EXTERN_H__
-//#include "PHY/defs_common.h"
-#include "nr_mac.h"
-#include "RRC/LTE/rrc_defs.h"
#include "common/ran_context.h"
+#include "nr_mac.h"
+
+/*#include "PHY/defs_common.h"*/
/* extern const uint32_t BSR_TABLE[BSR_TABLE_SIZE];
extern const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE];
@@ -43,15 +43,14 @@ extern const uint8_t cqi2fmt0_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE];
extern const uint8_t cqi2fmt1x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE];
extern const uint8_t cqi2fmt2x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE];
extern UE_RRC_INST *UE_rrc_inst;
-extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8
-extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][MAX_MOBILES_PER_ENB]; // eNBxUE = 8x8
-extern int cqi_to_mcs[16];
+extern const int cqi_to_mcs[16];
extern uint32_t RRC_CONNECTION_FLAG;
extern uint8_t rb_table[34];
extern mac_rlc_am_muilist_t rlc_am_mui;
extern SCHEDULER_MODES global_scheduler_mode;
extern unsigned char NB_UE_INST;*/
+
extern unsigned char NB_INST;
extern unsigned char NB_eNB_INST;
extern unsigned char NB_RN_INST;
@@ -60,8 +59,15 @@ extern unsigned short NODE_ID[1];
/* Scheduler */
extern RAN_CONTEXT_t RC;
extern uint8_t nfapi_mode;
+extern mac_rlc_am_muilist_t rlc_am_mui;
+extern SCHEDULER_MODES global_scheduler_mode;
/*#if defined(PRE_SCD_THREAD)
+extern const int cqi_to_mcs[16];
+extern uint32_t RRC_CONNECTION_FLAG;
+extern uint8_t rb_table[34];
+
+#if defined(PRE_SCD_THREAD)
extern uint16_t pre_nb_rbs_required[2][MAX_NUM_CCs][NUMBER_OF_UE_MAX];
extern uint8_t dlsch_ue_select_tbl_in_use;
extern uint8_t new_dlsch_ue_select_tbl_in_use;
@@ -69,4 +75,5 @@ extern boolean_t pre_scd_activeUE[NUMBER_OF_UE_MAX];
extern eNB_UE_STATS pre_scd_eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
#endif*/
+
#endif //DEF_H
diff --git a/openair2/LAYER2/NR_MAC_UE/config_ue.c b/openair2/LAYER2/NR_MAC_UE/config_ue.c
index c98302303496300fc9921f44b30f21c76c279124..bc98e16d39ef07c091affba1b6b72beeb90d09b5 100755
--- a/openair2/LAYER2/NR_MAC_UE/config_ue.c
+++ b/openair2/LAYER2/NR_MAC_UE/config_ue.c
@@ -31,12 +31,9 @@
*/
//#include "mac_defs.h"
-#include "mac_proto.h"
-
+#include "NR_MAC_UE/mac_proto.h"
#include "NR_MAC-CellGroupConfig.h"
-
-#include "../NR_MAC_gNB/nr_mac_common.h"
-#include "SCHED_NR/phy_frame_config_nr.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h"
int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg,
int mu,
@@ -151,8 +148,8 @@ void config_common_ue(NR_UE_MAC_INST_t *mac,
NR_ServingCellConfigCommon_t *scc = mac->scc;
int i;
- mac->phy_config.Mod_id = module_id;
- mac->phy_config.CC_id = cc_idP;
+ mac->phy_config.Mod_id = module_id;
+ mac->phy_config.CC_id = cc_idP;
// carrier config
@@ -203,12 +200,20 @@ void config_common_ue(NR_UE_MAC_INST_t *mac,
}
}
+ lte_frame_type_t frame_type;
+ uint16_t band;
+ int32_t offset;
+
+ get_band((cfg->carrier_config.dl_frequency)*1000,
+ &band,
+ &offset,
+ &frame_type);
+
// cell config
cfg->cell_config.phy_cell_id = *scc->physCellId;
- cfg->cell_config.frame_duplex_type = 1;
-
+ cfg->cell_config.frame_duplex_type = frame_type;
// SSB config
cfg->ssb_config.ss_pbch_power = scc->ss_PBCH_BlockPower;
@@ -270,7 +275,132 @@ void config_common_ue(NR_UE_MAC_INST_t *mac,
LOG_I(PHY,"TDD has been properly configurated\n");
}
+ // PRACH configuration
+
+ uint8_t nb_preambles = 64;
+ if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL)
+ nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles;
+
+ cfg->prach_config.prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1;
+
+ if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing)
+ cfg->prach_config.prach_sub_c_spacing = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing;
+ else
+ cfg->prach_config.prach_sub_c_spacing = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
+
+ cfg->prach_config.restricted_set_config = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig;
+ switch (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM) {
+ case 0 :
+ cfg->prach_config.num_prach_fd_occasions = 1;
+ break;
+ case 1 :
+ cfg->prach_config.num_prach_fd_occasions = 2;
+ break;
+ case 2 :
+ cfg->prach_config.num_prach_fd_occasions = 4;
+ break;
+ case 3 :
+ cfg->prach_config.num_prach_fd_occasions = 8;
+ break;
+ default:
+ AssertFatal(1==0,"msg1 FDM identifier %ld undefined (0,1,2,3) \n", scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM);
+ }
+
+ cfg->prach_config.num_prach_fd_occasions_list = (fapi_nr_num_prach_fd_occasions_t *) malloc(cfg->prach_config.num_prach_fd_occasions*sizeof(fapi_nr_num_prach_fd_occasions_t));
+ for (i=0; i<cfg->prach_config.num_prach_fd_occasions; i++) {
+ cfg->prach_config.num_prach_fd_occasions_list[i].num_prach_fd_occasions = i;
+ if (cfg->prach_config.prach_sequence_length)
+ cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l139;
+ else
+ cfg->prach_config.num_prach_fd_occasions_list[i].prach_root_sequence_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.choice.l839;
+
+ cfg->prach_config.num_prach_fd_occasions_list[i].k1 = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FrequencyStart;
+ cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig;
+ cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup, nb_preambles, frame_type);
+ //cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences = ???
+ }
+
+ cfg->prach_config.ssb_per_rach = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1;
+
+}
+
+/** \brief This function is relavant for the UE procedures for control. It loads the search spaces, the BWPs and the CORESETs into the MAC instance and
+ \brief performs assert checks on the relevant RRC configuration.
+ @param NR_UE_MAC_INST_t mac: pointer to local MAC instance
+ @returns void
+ */
+void config_control_ue(NR_UE_MAC_INST_t *mac){
+
+ uint8_t bwp_id = 1, coreset_id = 1, ss_id;
+ NR_ServingCellConfig_t *scd = mac->scg->spCellConfig->spCellConfigDedicated;
+ AssertFatal(scd->downlinkBWP_ToAddModList != NULL, "downlinkBWP_ToAddModList is null\n");
+ AssertFatal(scd->downlinkBWP_ToAddModList->list.count == 1, "downlinkBWP_ToAddModList->list->count is %d\n", scd->downlinkBWP_ToAddModList->list.count);
+
+ NR_BWP_DownlinkCommon_t *bwp_Common = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1]->bwp_Common;
+ AssertFatal(bwp_Common != NULL, "bwp_Common is null\n");
+
+ NR_BWP_DownlinkDedicated_t *dl_bwp_Dedicated = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1]->bwp_Dedicated;
+ AssertFatal(dl_bwp_Dedicated != NULL, "dl_bwp_Dedicated is null\n");
+
+ NR_SetupRelease_PDCCH_Config_t *pdcch_Config = dl_bwp_Dedicated->pdcch_Config;
+ AssertFatal(pdcch_Config != NULL, "pdcch_Config is null\n");
+
+ NR_SetupRelease_PDCCH_ConfigCommon_t *pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon;
+ AssertFatal(pdcch_ConfigCommon != NULL, "pdcch_ConfigCommon is null\n");
+ AssertFatal(pdcch_ConfigCommon->choice.setup->ra_SearchSpace != NULL, "ra_SearchSpace must be available in DL BWP\n");
+
+ struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
+ AssertFatal(commonSearchSpaceList != NULL, "commonSearchSpaceList is null\n");
+ AssertFatal(commonSearchSpaceList->list.count > 0, "PDCCH CSS list has 0 elements\n");
+
+ struct NR_PDCCH_Config__controlResourceSetToAddModList *controlResourceSetToAddModList = pdcch_Config->choice.setup->controlResourceSetToAddModList;
+ AssertFatal(controlResourceSetToAddModList != NULL, "controlResourceSetToAddModList is null\n");
+ AssertFatal(controlResourceSetToAddModList->list.count == 1, "controlResourceSetToAddModList->list.count=%d\n", controlResourceSetToAddModList->list.count);
+ AssertFatal(controlResourceSetToAddModList->list.array[0] != NULL, "coreset[0][0] is null\n");
+
+ struct NR_PDCCH_Config__searchSpacesToAddModList *searchSpacesToAddModList = pdcch_Config->choice.setup->searchSpacesToAddModList;
+ AssertFatal(searchSpacesToAddModList != NULL, "searchSpacesToAddModList is null\n");
+ AssertFatal(searchSpacesToAddModList->list.count > 0, "list of UE specifically configured Search Spaces is empty\n");
+ AssertFatal(searchSpacesToAddModList->list.count < FAPI_NR_MAX_SS_PER_CORESET, "too many searchpaces per coreset %d\n", searchSpacesToAddModList->list.count);
+
+ struct NR_UplinkConfig__uplinkBWP_ToAddModList *uplinkBWP_ToAddModList = scd->uplinkConfig->uplinkBWP_ToAddModList;
+ AssertFatal(uplinkBWP_ToAddModList != NULL, "uplinkBWP_ToAddModList is null\n");
+ AssertFatal(uplinkBWP_ToAddModList->list.count == 1, "uplinkBWP_ToAddModList->list->count is %d\n", uplinkBWP_ToAddModList->list.count);
+
+ // check pdcch_Config, pdcch_ConfigCommon and DL BWP
+ mac->DLbwp[0] = scd->downlinkBWP_ToAddModList->list.array[bwp_id - 1];
+ mac->coreset[bwp_id - 1][coreset_id - 1] = controlResourceSetToAddModList->list.array[0];
+
+ // Check dedicated UL BWP and pass to MAC
+ mac->ULbwp[0] = uplinkBWP_ToAddModList->list.array[0];
+ AssertFatal(mac->ULbwp[0]->bwp_Dedicated != NULL, "UL bwp_Dedicated is null\n");
+
+ // check available Search Spaces in the searchSpacesToAddModList and pass to MAC
+ // note: the network configures at most 10 Search Spaces per BWP per cell (including UE-specific and common Search Spaces).
+ for (ss_id = 0; ss_id < searchSpacesToAddModList->list.count; ss_id++) {
+ NR_SearchSpace_t *ss = searchSpacesToAddModList->list.array[ss_id];
+ AssertFatal(ss->controlResourceSetId != NULL, "ss->controlResourceSetId is null\n");
+ AssertFatal(ss->searchSpaceType != NULL, "ss->searchSpaceType is null\n");
+ AssertFatal(*ss->controlResourceSetId == mac->coreset[bwp_id - 1][coreset_id - 1]->controlResourceSetId, "ss->controlResourceSetId is unknown\n");
+ AssertFatal(ss->monitoringSymbolsWithinSlot != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot is null\n");
+ AssertFatal(ss->monitoringSymbolsWithinSlot->buf != NULL, "NR_SearchSpace->monitoringSymbolsWithinSlot->buf is null\n");
+ mac->SSpace[0][0][ss_id] = ss;
+ }
+
+ // Check available CSSs in the commonSearchSpaceList (list of additional common search spaces)
+ // note: commonSearchSpaceList SIZE(1..4)
+ for (int css_id = 0; css_id < commonSearchSpaceList->list.count; css_id++) {
+ NR_SearchSpace_t *css = commonSearchSpaceList->list.array[css_id];
+ AssertFatal(css->controlResourceSetId != NULL, "ss->controlResourceSetId is null\n");
+ AssertFatal(*css->controlResourceSetId == mac->coreset[bwp_id - 1][coreset_id - 1]->controlResourceSetId, "ss->controlResourceSetId is unknown\n");
+ AssertFatal(css->searchSpaceId != 0, "css->searchSpaceId is 0\n");
+ AssertFatal(css->searchSpaceType != NULL, "css->searchSpaceType is null\n");
+ AssertFatal(css->monitoringSymbolsWithinSlot != NULL, "css->monitoringSymbolsWithinSlot is null\n");
+ AssertFatal(css->monitoringSymbolsWithinSlot->buf != NULL, "css->monitoringSymbolsWithinSlot->buf is null\n");
+ mac->SSpace[0][0][ss_id] = css;
+ ss_id++;
+ }
}
int nr_rrc_mac_config_req_ue(
@@ -281,28 +411,27 @@ int nr_rrc_mac_config_req_ue(
// NR_ServingCellConfigCommon_t *sccP,
// NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
// NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
- NR_SpCellConfig_t *spCell_ConfigP ){
+ NR_CellGroupConfig_t *cell_group_config ){
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- // NR_ServingCellConfig_t *serving_cell_config = spcell_configP->spCellConfigDedicated;
// TODO do something FAPI-like P5 L1/L2 config interface in config_si, config_mib, etc.
-
if(mibP != NULL){
mac->mib = mibP; // update by every reception
}
-
-
- if(spCell_ConfigP != NULL ){
- mac->servCellIndex = *spCell_ConfigP->servCellIndex;
- if (spCell_ConfigP->reconfigurationWithSync) {
- mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
+
+ if(cell_group_config != NULL ){
+ mac->scg = cell_group_config;
+ mac->servCellIndex = *cell_group_config->spCellConfig->servCellIndex;
+ config_control_ue(mac);
+ if (cell_group_config->spCellConfig->reconfigurationWithSync) {
+ mac->rach_ConfigDedicated = cell_group_config->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink;
+ mac->scc = cell_group_config->spCellConfig->reconfigurationWithSync->spCellConfigCommon;
config_common_ue(mac,module_id,cc_idP);
- mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity;
+ mac->crnti = cell_group_config->spCellConfig->reconfigurationWithSync->newUE_Identity;
LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti);
}
- mac->scd = spCell_ConfigP->spCellConfigDedicated;
/*
if(mac_cell_group_configP != NULL){
@@ -367,8 +496,8 @@ int nr_rrc_mac_config_req_ue(
}
}
*/
- }
-
+ }
+
return 0;
}
diff --git a/openair2/LAYER2/NR_MAC_UE/mac_defs.h b/openair2/LAYER2/NR_MAC_UE/mac_defs.h
index 405ea95eb11962205197bdc1805607d8cf7dbbc0..e45f6a9b695873b1bbb3ca8753150b6269a1379f 100755
--- a/openair2/LAYER2/NR_MAC_UE/mac_defs.h
+++ b/openair2/LAYER2/NR_MAC_UE/mac_defs.h
@@ -37,6 +37,21 @@
#include <stdlib.h>
#include <string.h>
#include "platform_types.h"
+
+/* PHY */
+#include "PHY/defs_nr_common.h"
+
+/* IF */
+#include "NR_IF_Module.h"
+#include "fapi_nr_ue_interface.h"
+
+/* MAC */
+#include "LAYER2/NR_MAC_COMMON/nr_mac.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h"
+#include "LAYER2/MAC/mac.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
+
+/* RRC */
#include "NR_DRX-Config.h"
#include "NR_SchedulingRequestConfig.h"
#include "NR_BSR-Config.h"
@@ -46,13 +61,9 @@
#include "NR_MIB.h"
#include "NR_MAC-CellGroupConfig.h"
#include "NR_PhysicalCellGroupConfig.h"
-#include "NR_SpCellConfig.h"
+#include "NR_CellGroupConfig.h"
#include "NR_ServingCellConfig.h"
-#include "fapi_nr_ue_interface.h"
-#include "NR_IF_Module.h"
-#include "../NR_MAC_gNB/nr_mac_common.h"
-#include "PHY/defs_nr_common.h"
-#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac.h"
+
#define NB_NR_UE_MAC_INST 1
/*!\brief Maximum number of logical channl group IDs */
@@ -61,6 +72,7 @@
/*!\brief value for indicating BSR Timer is not running */
#define NR_MAC_UE_BSR_TIMER_NOT_RUNNING (0xFFFF)
+
typedef enum {
SFN_C_MOD_2_EQ_0,
SFN_C_MOD_2_EQ_1,
@@ -133,24 +145,27 @@ typedef struct {
#define MAX_NUM_BWP 2
typedef enum {
- RA_IDLE=0,
- WAIT_RAR=1,
- WAIT_CONTENTION_RESOLUTION=2
+ RA_UE_IDLE = 0,
+ WAIT_RAR = 1,
+ WAIT_CONTENTION_RESOLUTION = 2,
+ RA_SUCCEEDED = 3
} RA_state_t;
+
/*!\brief Top level UE MAC structure */
typedef struct {
NR_ServingCellConfigCommon_t *scc;
- NR_ServingCellConfig_t *scd;
+ NR_CellGroupConfig_t *scg;
+ NR_RACH_ConfigDedicated_t *rach_ConfigDedicated;
int servCellIndex;
//// MAC config
- NR_DRX_Config_t *drx_Config;
+ NR_DRX_Config_t *drx_Config;
NR_SchedulingRequestConfig_t *schedulingRequestConfig;
- NR_BSR_Config_t *bsr_Config;
- NR_TAG_Config_t *tag_Config;
- NR_PHR_Config_t *phr_Config;
- NR_RNTI_Value_t *cs_RNTI;
- NR_MIB_t *mib;
+ NR_BSR_Config_t *bsr_Config;
+ NR_TAG_Config_t *tag_Config;
+ NR_PHR_Config_t *phr_Config;
+ NR_RNTI_Value_t *cs_RNTI;
+ NR_MIB_t *mib;
NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP];
NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP];
@@ -163,14 +178,69 @@ typedef struct {
SFN_C_TYPE type0_pdcch_ss_sfn_c;
uint32_t type0_pdcch_ss_n_c;
uint32_t type0_pdcch_consecutive_slots;
+
+ /* PDUs */
+ /// Outgoing CCCH pdu for PHY
+ CCCH_PDU CCCH_pdu;
+ ULSCH_PDU ulsch_pdu;
+
+ /* Random Access parameters */
/// state of RA procedure
RA_state_t ra_state;
- /// RA-rnti
+ /// RA rx frame offset: compensate RA rx offset introduced by OAI gNB.
+ uint8_t RA_offset;
+ /// RA-rnti
uint16_t ra_rnti;
- /// Temporary CRNTI
+ /// Temporary CRNTI
uint16_t t_crnti;
- /// CRNTI
+ /// CRNTI
uint16_t crnti;
+ /// number of attempt for rach
+ uint8_t RA_attempt_number;
+ /// Random-access procedure flag
+ uint8_t RA_active;
+ /// Random-access window counter
+ int8_t RA_window_cnt;
+ /// Random-access Msg3 size in bytes
+ uint8_t RA_Msg3_size;
+ /// Random-access prachMaskIndex
+ uint8_t RA_prachMaskIndex;
+ /// Flag indicating Preamble set (A,B) used for first Msg3 transmission
+ uint8_t RA_usedGroupA;
+ /// BeamfailurerecoveryConfig
+ NR_BeamFailureRecoveryConfig_t RA_BeamFailureRecoveryConfig;
+ /// Preamble Tx Counter
+ uint8_t RA_PREAMBLE_TRANSMISSION_COUNTER;
+ /// Preamble Power Ramping Counter
+ uint8_t RA_PREAMBLE_POWER_RAMPING_COUNTER;
+ /// Random-access backoff counter
+ int16_t RA_backoff_indicator;
+ /// Random-access backoff counter
+ int16_t RA_backoff_cnt;
+ /// Random-access variable for window calculation (frame of last change in window counter)
+ uint32_t RA_tx_frame;
+ /// Random-access variable for window calculation (subframe of last change in window counter)
+ uint8_t RA_tx_subframe;
+ /// Random-access variable for backoff (frame of last change in backoff counter)
+ uint32_t RA_backoff_frame;
+ /// Random-access variable for backoff (subframe of last change in backoff counter)
+ uint8_t RA_backoff_subframe;
+ /// Random-access Group B maximum path-loss
+ uint16_t RA_maxPL;
+ /// Random-access Contention Resolution Timer active flag
+ uint8_t RA_contention_resolution_timer_active;
+ /// Random-access Contention Resolution Timer count value
+ uint8_t RA_contention_resolution_cnt;
+ /// Msg3 Delta Preamble
+ int8_t deltaPreamble_Msg3;
+ /// Received TPC command (in dB) from RAR
+ int8_t Msg3_TPC;
+ /// Flag to monitor if matching RAPID was received in RAR
+ uint8_t RA_RAPID_found;
+ /// Flag to monitor if BI was received in RAR
+ uint8_t RA_BI_found;
+ /// Flag for the Msg1 generation: enabled at every occurrence of nr prach slot
+ uint8_t generate_nr_prach;
//// FAPI-like interface message
fapi_nr_tx_request_t tx_request;
diff --git a/openair2/LAYER2/NR_MAC_UE/mac_extern.h b/openair2/LAYER2/NR_MAC_UE/mac_extern.h
index 26e0ea26676418d498a18aed4946858deb8a90f3..54cdc4d14931207911f2359766d6ab178b6b7221 100644
--- a/openair2/LAYER2/NR_MAC_UE/mac_extern.h
+++ b/openair2/LAYER2/NR_MAC_UE/mac_extern.h
@@ -90,4 +90,6 @@ extern const int32_t table_38213_10_1_1_c2[5];
// for PUSCH from TS 38.214 subclause 6.1.2.1.1
extern uint8_t table_6_1_2_1_1_2_time_dom_res_alloc_A[16][3];
// for PDSCH from TS 38.214 subclause 5.1.2.1.1
-extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3];
\ No newline at end of file
+extern uint8_t table_5_1_2_1_1_2_time_dom_res_alloc_A[16][3];
+
+extern dci_pdu_rel15_t *def_dci_pdu_rel15;
diff --git a/openair2/LAYER2/NR_MAC_UE/mac_proto.h b/openair2/LAYER2/NR_MAC_UE/mac_proto.h
index 3c625ec2ff11a7932d8c78427d88d2049070a72b..e9d7a97a5da2edc498caab32f8d65416b14de03c 100755
--- a/openair2/LAYER2/NR_MAC_UE/mac_proto.h
+++ b/openair2/LAYER2/NR_MAC_UE/mac_proto.h
@@ -72,7 +72,7 @@ int nr_rrc_mac_config_req_ue(
uint8_t gNB_index,
NR_MIB_t *mibP,
//NR_ServingCellConfigCommon_t *sccP,
- NR_SpCellConfig_t *spCell_ConfigP);
+ NR_CellGroupConfig_t *cell_group_config);
/**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/
NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst);
@@ -84,23 +84,9 @@ NR_UE_MAC_INST_t *get_mac_inst(
/**\brief called at each slot, slot length based on numerology. now use u=0, scs=15kHz, slot=1ms
performs BSR/SR/PHR procedures, random access procedure handler and DLSCH/ULSCH procedures.
- \param module_id module id
- \param gNB_index corresponding gNB index
- \param cc_id component carrier id
- \param rx_frame receive frame number
- \param rx_slot receive slot number
- \param tx_frame transmit frame number
- \param tx_slot transmit slot number*/
-NR_UE_L2_STATE_t nr_ue_scheduler(
- const module_id_t module_id,
- const uint8_t gNB_index,
- const int cc_id,
- const frame_t rx_frame,
- const slot_t rx_slot,
- const int32_t ssb_index,
- const frame_t tx_frame,
- const slot_t tx_slot);
-
+ \param dl_info DL indication
+ \param ul_info UL indication*/
+NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info);
/* \brief Get SR payload (0,1) from UE MAC
@param Mod_id Instance id of UE in machine
@@ -115,7 +101,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
-int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
+int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci);
uint32_t get_ssb_frame(uint32_t test);
@@ -124,8 +110,6 @@ uint32_t get_ssb_slot(uint32_t ssb_index);
uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
-
-
/* \brief Get payload (MAC PDU) from UE PHY
@param module_idP Instance id of UE in machine
@param CC_id Component Carrier index
@@ -154,16 +138,30 @@ void nr_ue_process_mac_pdu(module_id_t module_idP,
uint8_t gNB_index,
NR_UL_TIME_ALIGNMENT_t *ul_time_alignment);
+
+uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload,
+ uint8_t *pdu,
+ uint8_t num_sdus,
+ uint16_t *sdu_lengths,
+ uint8_t *sdu_lcids,
+ uint8_t power_headroom,
+ uint16_t crnti,
+ uint16_t truncated_bsr,
+ uint16_t short_bsr,
+ uint16_t long_bsr,
+ unsigned short post_padding,
+ uint16_t buflen);
+
int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len);
-void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot);
+void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot);
void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
int dci_format,
uint8_t dci_length,
uint16_t rnti,
uint64_t *dci_pdu,
- nr_dci_pdu_rel15_t *nr_pdci_info_extracted);
+ dci_pdu_rel15_t *nr_pdci_info_extracted);
uint8_t
@@ -175,5 +173,96 @@ int set_tdd_config_nr_ue(fapi_nr_config_request_t *cfg, int mu,
int nrofDownlinkSlots, int nrofDownlinkSymbols,
int nrofUplinkSlots, int nrofUplinkSymbols);
+/** \brief Function for UE/PHY to compute PUSCH transmit power in power-control procedure.
+ @param Mod_id Module id of UE
+ @returns Po_NOMINAL_PUSCH (PREAMBLE_RECEIVED_TARGET_POWER+DELTA_PREAMBLE
+*/
+int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t module_idP, uint8_t CC_id);
+
+/** \brief Function to compute DELTA_PREAMBLE from 38.321 subclause 7.3
+ (for RA power ramping procedure and Msg3 PUSCH power control policy)
+ @param Mod_id Module id of UE
+ @returns DELTA_PREAMBLE
+*/
+int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format);
+
+/* Random Access */
+
+/* \brief This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211 tables 6.3.3.2.x
+and fills the PRACH PDU per each FD occasion.
+@param module_idP Index of UE instance
+@param frameP Frame index
+@param slotP Slot index
+@returns void
+*/
+void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP);
+
+/* \brief Function called by PHY to process the received RAR and check that the preamble matches what was sent by the gNB. It provides the timing advance and t-CRNTI.
+@param Mod_id Index of UE instance
+@param CC_id Index to a component carrier
+@param frame Frame index
+@param ra_rnti RA_RNTI value
+@param dlsch_buffer Pointer to dlsch_buffer containing RAR PDU
+@param t_crnti Pointer to PHY variable containing the T_CRNTI
+@param preamble_index Preamble Index used by PHY to transmit the PRACH. This should match the received RAR to trigger the rest of
+random-access procedure
+@param selected_rar_buffer the output buffer for storing the selected RAR header and RAR payload
+@returns timing advance or 0xffff if preamble doesn't match
+*/
+uint16_t nr_ue_process_rar(module_id_t mod_id,
+ int CC_id,
+ frame_t frameP,
+ uint8_t * dlsch_buffer,
+ rnti_t * t_crnti,
+ uint8_t preamble_index,
+ uint8_t * selected_rar_buffer);
+
+void nr_process_rar(nr_downlink_indication_t *dl_info);
+
+void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame);
+
+void nr_ra_failed(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index);
+
+void nr_ra_succeeded(uint8_t Mod_id, uint8_t CC_id, uint8_t gNB_index);
+
+/* \brief Function called by PHY to retrieve information to be transmitted using the RA procedure.
+If the UE is not in PUSCH mode for a particular eNB index, this is assumed to be an Msg3 and MAC
+attempts to retrieves the CCCH message from RRC. If the UE is in PUSCH mode for a particular eNB
+index and PUCCH format 0 (Scheduling Request) is not activated, the MAC may use this resource for
+andom-access to transmit a BSR along with the C-RNTI control element (see 5.1.4 from 36.321)
+@param mod_id Index of UE instance
+@param CC_id Component Carrier Index
+@param frame
+@param gNB_id gNB index
+@param nr_tti_tx slot for PRACH transmission
+@returns indication to generate PRACH to phy */
+uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources,
+ module_id_t mod_id,
+ int CC_id,
+ UE_MODE_t UE_mode,
+ frame_t frame,
+ uint8_t gNB_id,
+ int nr_tti_tx);
+
+/* \brief Function implementing the routine for the selection of Random Access resources (5.1.2 TS 38.321).
+@param module_idP Index of UE instance
+@param CC_id Component Carrier Index
+@param gNB_index gNB index
+@param t_id
+@param rach_ConfigDedicated
+@returns void */
+void nr_get_prach_resources(module_id_t mod_id,
+ int CC_id,
+ uint8_t gNB_id,
+ uint8_t t_id,
+ uint8_t first_Msg3,
+ NR_PRACH_RESOURCES_t *prach_resources,
+ NR_RACH_ConfigDedicated_t * rach_ConfigDedicated);
+
+void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id);
+
+void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id);
+
+void nr_ue_msg2_scheduler(module_id_t mod_id, uint16_t rach_frame, uint16_t rach_slot, uint16_t *msg2_frame, uint16_t *msg2_slot);
#endif
/** @}*/
diff --git a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c
index 61f9ab601e9ac71954e29d912c6f93407af573a1..af9822a5dfa0e160c32ae572c71a9df1e01e08c4 100644
--- a/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c
+++ b/openair2/LAYER2/NR_MAC_UE/main_ue_nr.c
@@ -50,9 +50,9 @@ NR_UE_MAC_INST_t * nr_l2_init_ue(NR_UE_RRC_INST_t* rrc_inst)
//LOG_I(MAC, "[MAIN] init UE MAC functions \n");
//init mac here
- nr_ue_mac_inst = (NR_UE_MAC_INST_t *)malloc(sizeof(NR_UE_MAC_INST_t)*NB_NR_UE_MAC_INST);
+ nr_ue_mac_inst = (NR_UE_MAC_INST_t *)calloc(sizeof(NR_UE_MAC_INST_t),NB_NR_UE_MAC_INST);
if (rrc_inst) {
- nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config->spCellConfig);
+ nr_rrc_mac_config_req_ue(0,0,0,NULL,rrc_inst->cell_group_config);
if (IS_SOFTMODEM_NOS1){
if (rlc_module_init(0) != 0) {
diff --git a/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c
new file mode 100644
index 0000000000000000000000000000000000000000..f8bb1e5f8eae54c7698d613023b61ba3ebb15c7b
--- /dev/null
+++ b/openair2/LAYER2/NR_MAC_UE/nr_l1_helpers.c
@@ -0,0 +1,153 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file nr_l1_helper.c
+* \brief PHY helper functions for PRACH adapted to NR
+* \author Guido Casati
+* \date 2019
+* \version 2.0
+* \email guido.casati@iis.fraunhofer.de
+* @ingroup _mac
+
+*/
+
+#include "PHY/defs_nr_common.h"
+
+#include "mac_defs.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "LAYER2/NR_MAC_UE/mac_proto.h"
+
+/* TS 38.321 subclause 7.3 - return DELTA_PREAMBLE values in dB */
+int8_t nr_get_DELTA_PREAMBLE(module_id_t mod_id, int CC_id, uint16_t prach_format){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ NR_SubcarrierSpacing_t scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing;
+ int prach_sequence_length = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present - 1;
+ uint8_t prachConfigIndex, mu;
+
+ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
+
+ // SCS configuration from msg1_SubcarrierSpacing and table 4.2-1 in TS 38.211
+
+ switch (scs){
+ case NR_SubcarrierSpacing_kHz15:
+ mu = 0;
+ break;
+
+ case NR_SubcarrierSpacing_kHz30:
+ mu = 1;
+ break;
+
+ case NR_SubcarrierSpacing_kHz60:
+ mu = 2;
+ break;
+
+ case NR_SubcarrierSpacing_kHz120:
+ mu = 3;
+ break;
+
+ case NR_SubcarrierSpacing_kHz240:
+ mu = 4;
+ break;
+
+ case NR_SubcarrierSpacing_spare3:
+ mu = 5;
+ break;
+
+ case NR_SubcarrierSpacing_spare2:
+ mu = 6;
+ break;
+
+ case NR_SubcarrierSpacing_spare1:
+ mu = 7;
+ break;
+
+ default:
+ AssertFatal(1 == 0,"Unknown msg1_SubcarrierSpacing %lu\n", scs);
+ }
+
+ // Preamble formats given by prach_ConfigurationIndex and tables 6.3.3.2-2 and 6.3.3.2-2 in TS 38.211
+
+ prachConfigIndex = nr_rach_ConfigCommon->rach_ConfigGeneric.prach_ConfigurationIndex;
+
+ if (prach_sequence_length == 0) {
+ AssertFatal(prach_format < 4, "Illegal PRACH format %d for sequence length 839\n", prach_format);
+ switch (prach_format) {
+
+ // long preamble formats
+ case 0:
+ case 3:
+ return 0;
+
+ case 1:
+ return -3;
+
+ case 2:
+ return -6;
+ }
+ } else {
+ switch (prach_format) { // short preamble formats
+ case 0:
+ case 3:
+ return 8 + 3*mu;
+
+ case 1:
+ case 4:
+ case 8:
+ return 5 + 3*mu;
+
+ case 2:
+ case 5:
+ return 3 + 3*mu;
+
+ case 6:
+ return 3*mu;
+
+ case 7:
+ return 5 + 3*mu;
+
+ default:
+ AssertFatal(1 == 0, "[UE %d] ue_procedures.c: FATAL, Illegal preambleFormat %d, prachConfigIndex %d\n", mod_id, prach_format, prachConfigIndex);
+ }
+ }
+ return 0;
+}
+
+/* TS 38.321 subclause 5.1.3 - RA preamble transmission - ra_PREAMBLE_RECEIVED_TARGET_POWER configuration */
+int nr_get_Po_NOMINAL_PUSCH(NR_PRACH_RESOURCES_t *prach_resources, module_id_t mod_id, uint8_t CC_id){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ int8_t receivedTargerPower, delta_preamble;
+ long preambleReceivedTargetPower;
+
+ AssertFatal(nr_rach_ConfigCommon != NULL, "[UE %d] CCid %d FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id, CC_id);
+
+ preambleReceivedTargetPower = nr_rach_ConfigCommon->rach_ConfigGeneric.preambleReceivedTargetPower;
+ delta_preamble = nr_get_DELTA_PREAMBLE(mod_id, CC_id, prach_resources->prach_format);
+
+ receivedTargerPower = preambleReceivedTargetPower + delta_preamble + (mac->RA_PREAMBLE_POWER_RAMPING_COUNTER - 1) * prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP;
+
+ return receivedTargerPower;
+}
diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
new file mode 100644
index 0000000000000000000000000000000000000000..351bcc292f73cd68852ba775f06a9a7a873333dc
--- /dev/null
+++ b/openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
@@ -0,0 +1,643 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file ra_procedures.c
+ * \brief Routines for UE MAC-layer Random Access procedures (TS 38.321, Release 15)
+ * \author R. Knopp, Navid Nikaein, Guido Casati
+ * \date 2019
+ * \version 0.1
+ * \company Eurecom
+ * \email: knopp@eurecom.fr navid.nikaein@eurecom.fr, guido.casati@iis.fraunhofer.de
+ * \note
+ * \warning
+ */
+
+#include "mac.h"
+
+/*
+#include "common/utils/LOG/vcd_signal_dumper.h"
+#include "PHY_INTERFACE/phy_interface_extern.h"
+#include "SCHED_UE/sched_UE.h"
+#include "COMMON/mac_rrc_primitives.h"
+#include "RRC/LTE/rrc_extern.h"
+#include "RRC/L2_INTERFACE/openair_rrc_L2_interface.h"
+#include "common/utils/LOG/log.h"
+#include "UTIL/OPT/opt.h"
+#include "OCG.h"
+#include "OCG_extern.h"
+#include "PHY/LTE_ESTIMATION/lte_estimation.h"*/
+
+/* Tools */
+#include "SIMULATION/TOOLS/sim.h" // for taus
+
+/* RRC */
+#include "NR_RACH-ConfigCommon.h"
+
+/* PHY */
+#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
+#include "PHY/defs_common.h"
+#include "PHY/defs_nr_common.h"
+#include "PHY/NR_UE_ESTIMATION/nr_estimation.h"
+
+/* MAC */
+#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_COMMON/nr_mac.h"
+#include "LAYER2/NR_MAC_UE/mac_proto.h"
+
+extern int64_t table_6_3_3_2_3_prachConfig_Index [256][9];
+extern const uint8_t nr_slots_per_frame[5];
+
+//extern uint8_t nfapi_mode;
+
+void nr_get_RA_window(NR_UE_MAC_INST_t *mac);
+
+// WIP
+// This routine implements Section 5.1.2 (UE Random Access Resource Selection)
+// and Section 5.1.3 (Random Access Preamble Transmission) from 3GPP TS 38.321
+void nr_get_prach_resources(module_id_t mod_id,
+ int CC_id,
+ uint8_t gNB_id,
+ uint8_t t_id,
+ uint8_t first_Msg3,
+ NR_PRACH_RESOURCES_t *prach_resources,
+ NR_RACH_ConfigDedicated_t * rach_ConfigDedicated){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon;
+ NR_RACH_ConfigGeneric_t *rach_ConfigGeneric;
+
+ // NR_BeamFailureRecoveryConfig_t *beam_failure_recovery_config = &mac->RA_BeamFailureRecoveryConfig; // todo
+
+ int messagePowerOffsetGroupB = 0, messageSizeGroupA, PLThreshold, sizeOfRA_PreamblesGroupA = 0, numberOfRA_Preambles, i, deltaPreamble_Msg3 = 0;
+ uint8_t noGroupB = 0, s_id, f_id, ul_carrier_id, prach_ConfigIndex, SFN_nbr, Msg3_size;
+
+ AssertFatal(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id);
+ nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ rach_ConfigGeneric = &nr_rach_ConfigCommon->rach_ConfigGeneric;
+
+ // NR_RSRP_Range_t rsrp_ThresholdSSB; // todo
+
+ ///////////////////////////////////////////////////////////
+ //////////* UE Random Access Resource Selection *//////////
+ ///////////////////////////////////////////////////////////
+
+ // todo:
+ // - switch initialisation cases
+ // -- RA initiated by beam failure recovery operation (subclause 5.17 TS 38.321)
+ // --- SSB selection, set prach_resources->ra_PreambleIndex
+ // -- RA initiated by PDCCH: ra_preamble_index provided by PDCCH && ra_PreambleIndex != 0b000000
+ // --- set PREAMBLE_INDEX to ra_preamble_index
+ // --- select the SSB signalled by PDCCH
+ // -- RA initiated for SI request:
+ // --- SSB selection, set prach_resources->ra_PreambleIndex
+
+ if (rach_ConfigDedicated) {
+ //////////* Contention free RA *//////////
+ // - the PRACH preamble for the UE to transmit is set through RRC configuration
+ // - this is the default mode in current implementation!
+ // Operation for contention-free RA resources when:
+ // - available SSB with SS-RSRP above rsrp-ThresholdSSB: SSB selection
+ // - available CSI-RS with CSI-RSRP above rsrp-ThresholdCSI-RS: CSI-RS selection
+ // - network controlled Mobility
+ uint8_t cfra_ssb_resource_idx = 0;
+ prach_resources->ra_PreambleIndex = rach_ConfigDedicated->cfra->resources.choice.ssb->ssb_ResourceList.list.array[cfra_ssb_resource_idx]->ra_PreambleIndex;
+ LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-free random access procedure... \n", prach_resources->ra_PreambleIndex);
+ } else {
+ //////////* Contention-based RA preamble selection *//////////
+ // todo:
+ // - selection of SSB with SS-RSRP above rsrp-ThresholdSSB else select any SSB
+ // - todo determine next available PRACH occasion
+
+ // rsrp_ThresholdSSB = *nr_rach_ConfigCommon->rsrp_ThresholdSSB;
+
+ Msg3_size = mac->RA_Msg3_size;
+
+ numberOfRA_Preambles = 64;
+ if(nr_rach_ConfigCommon->totalNumberOfRA_Preambles != NULL)
+ numberOfRA_Preambles = *(nr_rach_ConfigCommon->totalNumberOfRA_Preambles);
+
+ if (!nr_rach_ConfigCommon->groupBconfigured) {
+ noGroupB = 1;
+ } else {
+ // RA preambles group B is configured
+ // - Defining the number of RA preambles in RA Preamble Group A for each SSB */
+ sizeOfRA_PreamblesGroupA = nr_rach_ConfigCommon->groupBconfigured->numberOfRA_PreamblesGroupA;
+ switch (nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA){
+ /* - Threshold to determine the groups of RA preambles */
+ case 0:
+ messageSizeGroupA = 56;
+ break;
+ case 1:
+ messageSizeGroupA = 144;
+ break;
+ case 2:
+ messageSizeGroupA = 208;
+ break;
+ case 3:
+ messageSizeGroupA = 256;
+ break;
+ case 4:
+ messageSizeGroupA = 282;
+ break;
+ case 5:
+ messageSizeGroupA = 480;
+ break;
+ case 6:
+ messageSizeGroupA = 640;
+ break;
+ case 7:
+ messageSizeGroupA = 800;
+ break;
+ case 8:
+ messageSizeGroupA = 1000;
+ break;
+ case 9:
+ messageSizeGroupA = 72;
+ break;
+ default:
+ AssertFatal(1 == 0,"Unknown ra_Msg3SizeGroupA %lu\n", nr_rach_ConfigCommon->groupBconfigured->ra_Msg3SizeGroupA);
+ /* todo cases 10 -15*/
+ }
+
+ /* Power offset for preamble selection in dB */
+ messagePowerOffsetGroupB = -9999;
+ switch (nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB){
+ case 0:
+ messagePowerOffsetGroupB = -9999;
+ break;
+ case 1:
+ messagePowerOffsetGroupB = 0;
+ break;
+ case 2:
+ messagePowerOffsetGroupB = 5;
+ break;
+ case 3:
+ messagePowerOffsetGroupB = 8;
+ break;
+ case 4:
+ messagePowerOffsetGroupB = 10;
+ break;
+ case 5:
+ messagePowerOffsetGroupB = 12;
+ break;
+ case 6:
+ messagePowerOffsetGroupB = 15;
+ break;
+ case 7:
+ messagePowerOffsetGroupB = 18;
+ break;
+ default:
+ AssertFatal(1 == 0,"Unknown messagePowerOffsetGroupB %lu\n", nr_rach_ConfigCommon->groupBconfigured->messagePowerOffsetGroupB);
+ }
+
+ // todo Msg3-DeltaPreamble should be provided from higher layers, otherwise is 0
+ mac->deltaPreamble_Msg3 = 0;
+ deltaPreamble_Msg3 = mac->deltaPreamble_Msg3;
+ }
+
+ PLThreshold = prach_resources->RA_PCMAX - rach_ConfigGeneric->preambleReceivedTargetPower - deltaPreamble_Msg3 - messagePowerOffsetGroupB;
+
+ /* Msg3 has not been transmitted yet */
+ if (first_Msg3 == 1) {
+ if (noGroupB == 1) {
+ // use Group A preamble
+ prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles;
+ mac->RA_usedGroupA = 1;
+ } else if ((Msg3_size < messageSizeGroupA) && (get_nr_PL(mod_id, CC_id, gNB_id) > PLThreshold)) {
+ // Group B is configured and RA preamble Group A is used
+ // - todo add condition on CCCH_sdu_size for initiation by CCCH
+ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA;
+ mac->RA_usedGroupA = 1;
+ } else {
+ // Group B preamble is configured and used
+ // the first sizeOfRA_PreamblesGroupA RA preambles belong to RA Preambles Group A
+ // the remaining belong to RA Preambles Group B
+ prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA);
+ mac->RA_usedGroupA = 0;
+ }
+ } else { // Msg3 is being retransmitted
+ if (mac->RA_usedGroupA == 1 && noGroupB == 1) {
+ prach_resources->ra_PreambleIndex = (taus()) % numberOfRA_Preambles;
+ } else if (mac->RA_usedGroupA == 1 && noGroupB == 0){
+ prach_resources->ra_PreambleIndex = (taus()) % sizeOfRA_PreamblesGroupA;
+ } else {
+ prach_resources->ra_PreambleIndex = sizeOfRA_PreamblesGroupA + (taus()) % (numberOfRA_Preambles - sizeOfRA_PreamblesGroupA);
+ }
+ }
+ LOG_D(MAC, "[RAPROC] - Selected RA preamble index %d for contention-based random access procedure... \n", prach_resources->ra_PreambleIndex);
+ }
+
+ // todo determine next available PRACH occasion
+ // - if RA initiated for SI request and ra_AssociationPeriodIndex and si-RequestPeriod are configured
+ // - else if SSB is selected above
+ // - else if CSI-RS is selected above
+
+ /////////////////////////////////////////////////////////////////////////////
+ //////////* Random Access Preamble Transmission (5.1.3 TS 38.321) *//////////
+ /////////////////////////////////////////////////////////////////////////////
+ // todo:
+ // - condition on notification of suspending power ramping counter from lower layer (5.1.3 TS 38.321)
+ // - check if SSB or CSI-RS have not changed since the selection in the last RA Preamble tranmission
+ // - Extend RA_rnti computation (e.g. f_id selection, ul_carrier_id are hardcoded)
+
+ if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER > 1)
+ mac->RA_PREAMBLE_POWER_RAMPING_COUNTER++;
+
+ prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id);
+
+ // RA-RNTI computation (associated to PRACH occasion in which the RA Preamble is transmitted)
+ // 1) this does not apply to contention-free RA Preamble for beam failure recovery request
+ // 2) getting star_symb, SFN_nbr from table 6.3.3.2-3 (TDD and FR1 scenario)
+
+ prach_ConfigIndex = rach_ConfigGeneric->prach_ConfigurationIndex;
+
+ // ra_RNTI computation
+ // - todo: this is for TDD FR1 only
+ // - ul_carrier_id: UL carrier used for RA preamble transmission, hardcoded for NUL carrier
+ // - f_id: index of the PRACH occasion in the frequency domain
+ // - s_id is starting symbol of the PRACH occasion [0...14]
+ // - t_id is the first slot of the PRACH occasion in a system frame [0...80]
+
+ ul_carrier_id = 0; // NUL
+ f_id = rach_ConfigGeneric->msg1_FrequencyStart;
+ SFN_nbr = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][4];
+ s_id = table_6_3_3_2_3_prachConfig_Index[prach_ConfigIndex][5];
+
+ // Pick the first slot of the PRACH occasion in a system frame
+ for (i = 0; i < 10; i++){
+ if (((SFN_nbr & (1 << i)) >> i) == 1){
+ t_id = 2*i;
+ break;
+ }
+ }
+ prach_resources->ra_RNTI = 1 + s_id + 14 * t_id + 1120 * f_id + 8960 * ul_carrier_id;
+ mac->ra_rnti = prach_resources->ra_RNTI;
+
+ LOG_D(MAC, "Computed ra_RNTI is %x \n", prach_resources->ra_RNTI);
+}
+
+// TbD: RA_attempt_number not used
+void nr_Msg1_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
+ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ mac->ra_state = WAIT_RAR;
+ // Start contention resolution timer
+ mac->RA_attempt_number++;
+}
+
+void nr_Msg3_transmitted(module_id_t mod_id, uint8_t CC_id, frame_t frameP, uint8_t gNB_id){
+ AssertFatal(CC_id == 0, "Transmission on secondary CCs is not supported yet\n");
+ LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Starting contention resolution timer\n", mod_id, frameP);
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ // start contention resolution timer
+ mac->RA_contention_resolution_cnt = 0;
+ mac->RA_contention_resolution_timer_active = 1;
+}
+
+/////////////////////////////////////////////////////////////////////////
+///////* Random Access Preamble Initialization (5.1.1 TS 38.321) *///////
+/////////////////////////////////////////////////////////////////////////
+/// Handling inizialization by PDCCH order, MAC entity or RRC (TS 38.300)
+/// Only one RA procedure is ongoing at any point in time in a MAC entity
+/// the RA procedure on a SCell shall only be initiated by PDCCH order
+/// in the current implementation, RA is contention free only
+
+// WIP
+// todo TS 38.321:
+// - check if carrier to use is explicitly signalled then do (1) RA CARRIER SELECTION (SUL, NUL) (2) set PCMAX
+// - BWP operation (subclause 5.15 TS 38.321)
+// - handle initialization by beam failure recovery
+// - handle initialization by handover
+// - handle transmission on DCCH using PRACH (during handover, or sending SR for example)
+// - take into account MAC CEs in size_sdu (currently hardcoded size to 1 MAC subPDU and 1 padding subheader)
+// - fix rrc data req logic
+// - retrieve TBS
+// - add mac_rrc_nr_data_req_ue, etc ...
+// - add the backoff condition here if we have it from a previous RA reponse which failed (i.e. backoff indicator)
+
+uint8_t nr_ue_get_rach(NR_PRACH_RESOURCES_t *prach_resources,
+ module_id_t mod_id,
+ int CC_id,
+ UE_MODE_t UE_mode,
+ frame_t frame,
+ uint8_t gNB_id,
+ int nr_tti_tx){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ uint8_t mac_sdus[MAX_NR_ULSCH_PAYLOAD_BYTES];
+ uint8_t lcid = UL_SCH_LCID_CCCH_MSG3, *payload;
+ //uint8_t ra_ResponseWindow;
+ uint16_t size_sdu = 0;
+ unsigned short post_padding;
+ //fapi_nr_config_request_t *cfg = &mac->phy_config.config_req;
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric;
+ //NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL;
+ NR_RACH_ConfigDedicated_t *rach_ConfigDedicated = mac->rach_ConfigDedicated;
+
+ // int32_t frame_diff = 0;
+
+ uint8_t sdu_lcids[NB_RB_MAX] = {0};
+ uint16_t sdu_lengths[NB_RB_MAX] = {0};
+ int TBS_bytes = 848, header_length_total=0, num_sdus, offset, preambleTransMax, mac_ce_len;
+
+ AssertFatal(CC_id == 0,"Transmission on secondary CCs is not supported yet\n");
+
+ if (UE_mode < PUSCH && prach_resources->init_msg1) {
+
+ LOG_D(MAC, "nr_ue_get_rach, RA_active value: %d", mac->RA_active);
+
+ AssertFatal(setup != NULL, "[UE %d] FATAL nr_rach_ConfigCommon is NULL !!!\n", mod_id);
+
+ if (mac->RA_active == 0) {
+ /* RA not active - checking if RRC is ready to initiate the RA procedure */
+
+ LOG_I(MAC, "RA not active. Starting RA preamble initialization.\n");
+
+ mac->RA_RAPID_found = 0;
+
+ /* Set RA_PREAMBLE_POWER_RAMPING_STEP */
+ switch (rach_ConfigGeneric->powerRampingStep){ // in dB
+ case 0:
+ prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 0;
+ break;
+ case 1:
+ prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 2;
+ break;
+ case 2:
+ prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 4;
+ break;
+ case 3:
+ prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP = 6;
+ break;
+ }
+
+ prach_resources->RA_PREAMBLE_BACKOFF = 0;
+ prach_resources->RA_SCALING_FACTOR_BI = 1;
+ prach_resources->RA_PCMAX = 0; // currently hardcoded to 0
+
+ payload = (uint8_t*) &mac->CCCH_pdu.payload;
+
+ mac_ce_len = 0;
+ num_sdus = 1;
+ post_padding = 1;
+
+ if (0){
+ // initialisation by RRC
+ // CCCH PDU
+ // size_sdu = (uint16_t) mac_rrc_data_req_ue(mod_id,
+ // CC_id,
+ // frame,
+ // CCCH,
+ // 1,
+ // mac_sdus,
+ // gNB_id,
+ // 0);
+ LOG_D(MAC,"[UE %d] Frame %d: Requested RRCConnectionRequest, got %d bytes\n", mod_id, frame, size_sdu);
+ } else {
+ // fill ulsch_buffer with random data
+ for (int i = 0; i < TBS_bytes; i++){
+ mac_sdus[i] = (unsigned char) (lrand48()&0xff);
+ }
+ //Sending SDUs with size 1
+ //Initialize elements of sdu_lcids and sdu_lengths
+ sdu_lcids[0] = lcid;
+ sdu_lengths[0] = TBS_bytes - 3 - post_padding - mac_ce_len;
+ header_length_total += 2 + (sdu_lengths[0] >= 128);
+ size_sdu += sdu_lengths[0];
+ }
+
+ //mac->RA_tx_frame = frame;
+ //mac->RA_tx_subframe = nr_tti_tx;
+ //mac->RA_backoff_frame = frame;
+ //mac->RA_backoff_subframe = nr_tti_tx;
+
+ if (size_sdu > 0) {
+
+ LOG_I(MAC, "[UE %d] Frame %d: Initialisation Random Access Procedure\n", mod_id, frame);
+
+ mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1;
+ mac->RA_PREAMBLE_POWER_RAMPING_COUNTER = 1;
+ mac->RA_Msg3_size = size_sdu + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT);
+ mac->RA_prachMaskIndex = 0;
+ // todo: add the backoff condition here
+ mac->RA_backoff_cnt = 0;
+ mac->RA_active = 1;
+ prach_resources->Msg3 = payload;
+
+ nr_get_RA_window(mac);
+
+ // Fill in preamble and PRACH resources
+ if (mac->generate_nr_prach == 1)
+ nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 1, prach_resources, rach_ConfigDedicated);
+
+ offset = nr_generate_ulsch_pdu((uint8_t *) mac_sdus, // sdus buffer
+ (uint8_t *) payload, // UL MAC pdu pointer
+ num_sdus, // num sdus
+ sdu_lengths, // sdu length
+ sdu_lcids, // sdu lcid
+ 0, // power headroom
+ 0, // crnti
+ 0, // truncated bsr
+ 0, // short bsr
+ 0, // long_bsr
+ post_padding,
+ 0);
+
+ // Padding: fill remainder with 0
+ if (post_padding > 0){
+ for (int j = 0; j < (TBS_bytes - offset); j++)
+ payload[offset + j] = 0; // mac_pdu[offset + j] = 0;
+ }
+ }
+ } else if (mac->RA_window_cnt != -1) { // RACH is active
+
+ ////////////////////////////////////////////////////////////////
+ /////* Random Access Response reception (5.1.4 TS 38.321) */////
+ ////////////////////////////////////////////////////////////////
+ // Handling ra_responseWindow, RA_PREAMBLE_TRANSMISSION_COUNTER
+ // and RA_backoff_cnt
+ // todo:
+ // - handle beam failure recovery request
+ // - handle DL assignment on PDCCH for RA-RNTI
+ // - handle backoff and raResponseWindow params
+
+ // LOG_D(MAC, "[MAC][UE %d][RAPROC] frame %d, subframe %d: RA Active, window cnt %d (RA_tx_frame %d, RA_tx_subframe %d)\n",
+ // mod_id, frame, nr_tti_tx, mac->RA_window_cnt, mac->RA_tx_frame, mac->RA_tx_subframe);
+
+ if (mac->RA_BI_found){
+ prach_resources->RA_PREAMBLE_BACKOFF = prach_resources->RA_SCALING_FACTOR_BI * mac->RA_backoff_indicator;
+ } else {
+ prach_resources->RA_PREAMBLE_BACKOFF = 0;
+ }
+
+ if (mac->RA_window_cnt >= 0 && mac->RA_RAPID_found == 1) {
+
+ mac->RA_window_cnt = -1;
+ mac->ra_state = RA_SUCCEEDED;
+ LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: nr_tti_tx %d: RAR successfully received \n", mod_id, frame, nr_tti_tx);
+
+ } else if (mac->RA_window_cnt == 0 && !mac->RA_RAPID_found) {
+
+ LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: nr_tti_tx %d: RAR reception failed \n", mod_id, frame, nr_tti_tx);
+
+ mac->ra_state = RA_UE_IDLE;
+ mac->RA_PREAMBLE_TRANSMISSION_COUNTER++;
+
+ preambleTransMax = -1;
+ switch (rach_ConfigGeneric->preambleTransMax) {
+ case 0:
+ preambleTransMax = 3;
+ break;
+ case 1:
+ preambleTransMax = 4;
+ break;
+ case 2:
+ preambleTransMax = 5;
+ break;
+ case 3:
+ preambleTransMax = 6;
+ break;
+ case 4:
+ preambleTransMax = 7;
+ break;
+ case 5:
+ preambleTransMax = 8;
+ break;
+ case 6:
+ preambleTransMax = 10;
+ break;
+ case 7:
+ preambleTransMax = 20;
+ break;
+ case 8:
+ preambleTransMax = 50;
+ break;
+ case 9:
+ preambleTransMax = 100;
+ break;
+ case 10:
+ preambleTransMax = 200;
+ break;
+ }
+
+ // Resetting RA window
+ nr_get_RA_window(mac);
+
+ if (mac->RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax + 1){
+ LOG_D(MAC, "[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n", mod_id, frame, preambleTransMax);
+ mac->RA_backoff_cnt = rand() % (prach_resources->RA_PREAMBLE_BACKOFF + 1);
+ mac->RA_PREAMBLE_TRANSMISSION_COUNTER = 1;
+ prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP += prach_resources->RA_PREAMBLE_POWER_RAMPING_STEP << 1; // 2 dB increment
+ prach_resources->ra_PREAMBLE_RECEIVED_TARGET_POWER = nr_get_Po_NOMINAL_PUSCH(prach_resources, mod_id, CC_id);
+ }
+
+ // compute backoff parameters
+ // if (mac->RA_backoff_cnt > 0){
+ // frame_diff = (sframe_t) frame - mac->RA_backoff_frame;
+ // if (frame_diff < 0) frame_diff = -frame_diff;
+ // mac->RA_backoff_frame = frame;
+ // mac->RA_backoff_subframe = nr_tti_tx;
+ // }
+ // compute RA window parameters
+ // if (mac->RA_window_cnt > 0){
+ // frame_diff = (frame_t) frame - mac->RA_tx_frame;
+ // if (frame_diff < 0) frame_diff = -frame_diff;
+ // mac->RA_window_cnt -= ((10 * frame_diff) + (nr_tti_tx - mac->RA_tx_subframe));
+ // LOG_D(MAC, "[MAC][UE %d][RAPROC] Frame %d, subframe %d: RA Active, adjusted window cnt %d\n", mod_id, frame, nr_tti_tx, mac->RA_window_cnt);
+ // }
+
+ // mac->RA_tx_frame = frame;
+ // mac->RA_tx_subframe = nr_tti_tx;
+
+ // Fill in preamble and PRACH resources
+ if (mac->generate_nr_prach == 1)
+ nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated);
+
+ } else {
+
+ mac->RA_window_cnt--;
+
+ LOG_I(MAC, "[MAC][UE %d][RAPROC] Frame %d: nr_tti_tx %d: RAR reception not successful, (RA window count %d) \n",
+ mod_id,
+ frame,
+ nr_tti_tx,
+ mac->RA_window_cnt);
+
+ // Fill in preamble and PRACH resources
+ if (mac->generate_nr_prach == 1)
+ nr_get_prach_resources(mod_id, CC_id, gNB_id, nr_tti_tx, 0, prach_resources, rach_ConfigDedicated);
+
+ }
+ }
+ } else if (UE_mode == PUSCH) {
+ LOG_D(MAC, "[UE %d] FATAL: Should not have checked for RACH in PUSCH yet ...", mod_id);
+ AssertFatal(1 == 0, "");
+ }
+ return mac->generate_nr_prach;
+}
+
+void nr_get_RA_window(NR_UE_MAC_INST_t *mac){
+
+ uint8_t mu, ra_ResponseWindow;
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric;
+ NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL;
+
+ ra_ResponseWindow = rach_ConfigGeneric->ra_ResponseWindow;
+
+ if (setup->msg1_SubcarrierSpacing)
+ mu = *setup->msg1_SubcarrierSpacing;
+ else
+ mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
+
+ mac->RA_window_cnt = mac->RA_offset*nr_slots_per_frame[mu]; // taking into account the 2 frames gap introduced by OAI gNB
+
+ switch (ra_ResponseWindow) {
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1:
+ mac->RA_window_cnt += 1;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2:
+ mac->RA_window_cnt += 2;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4:
+ mac->RA_window_cnt += 4;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8:
+ mac->RA_window_cnt += 8;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10:
+ mac->RA_window_cnt += 10;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20:
+ mac->RA_window_cnt += 20;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40:
+ mac->RA_window_cnt += 40;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80:
+ mac->RA_window_cnt += 80;
+ break;
+ }
+}
diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
index 396e06ff09071a213c7ac1bd9bfdc930e51c67ce..2285fc5999d77f2258edeade4e0c43ebea753e81 100644
--- a/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
+++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
@@ -21,11 +21,11 @@
/* \file nr_ue_dci_configuration.c
* \brief functions for generating dci search procedures based on RRC Serving Cell Group Configuration
- * \author R. Knopp
+ * \author R. Knopp, G. Casati
* \date 2020
- * \version 0.1
- * \company Eurecom
- * \email: knopp@eurecom.fr
+ * \version 0.2
+ * \company Eurecom, Fraunhofer IIS
+ * \email: knopp@eurecom.fr, guido.casati@iis.fraunhofer.de
* \note
* \warning
*/
@@ -35,6 +35,8 @@
#include "assertions.h"
#include "LAYER2/NR_MAC_UE/mac_extern.h"
#include "mac_defs.h"
+#include "common/utils/nr/nr_common.h"
+#include "executables/softmodem-common.h"
#include <stdio.h>
#ifdef NR_PDCCH_DCI_TOOLS_DEBUG
@@ -44,6 +46,9 @@
#endif
#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a)
+// #define DEBUG_DCI
+
+dci_pdu_rel15_t *def_dci_pdu_rel15;
void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15) {
@@ -59,125 +64,261 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
}
-void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot) {
-
- // check if DL slot
- if (is_nr_DL_slot(mac->scc,slot)==1) {
-
- // get BWP 1, Coreset 0, SearchSpace 0
- if (mac->DLbwp[0]==NULL) {
- AssertFatal(mac->scd->downlinkBWP_ToAddModList!=NULL,"downlinkBWP_ToAddModList is null\n");
- AssertFatal(mac->scd->downlinkBWP_ToAddModList->list.count==1,"downlinkBWP_ToAddModList->list->count is %d\n",
- mac->scd->downlinkBWP_ToAddModList->list.count);
- mac->DLbwp[0] = mac->scd->downlinkBWP_ToAddModList->list.array[0];
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n");
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config!=NULL,"pdcch_Config is null\n");
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,"controlResourceSetToAddModList is null\n");
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count==1,"controlResourceSetToAddModList->list.count=%d\n",
- mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count);
- mac->coreset[0][0] = mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0];
- AssertFatal(mac->coreset[0][0]!=NULL,"coreset[0][0] is null\n");
-
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
- "searchPsacesToAddModList is empty\n");
- NR_SearchSpace_t *ss;
- int ss_id=0;
- AssertFatal(mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count<FAPI_NR_MAX_SS_PER_CORESET,
- "too many searchpaces per coreset %d\n",
- mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count);
- for (int i=0;i<mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
- ss=mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
- AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
- AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
- AssertFatal(*ss->controlResourceSetId == mac->coreset[0][0]->controlResourceSetId,"ss->controlResourceSetId is unknown\n");
- mac->SSpace[0][0][ss_id] = ss;
- ss_id++;
- }
- }
- if (mac->ULbwp[0]==NULL) {
- AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList!=NULL,"uplinkBWP_ToAddModList is null\n");
- AssertFatal(mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count==1,"uplinkBWP_ToAddModList->list->count is %d\n",
- mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.count);
- mac->ULbwp[0] = mac->scd->uplinkConfig->uplinkBWP_ToAddModList->list.array[0];
- AssertFatal(mac->ULbwp[0]->bwp_Dedicated!=NULL,"bwp_Dedicated is null\n");
- }
- // check search spaces
-
- int ss_id=0;
- fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15;
- int sps =mac->DLbwp[0]->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
-
- while(mac->SSpace[0][0][ss_id]!=NULL &&
- ss_id < mac->DLbwp[0]->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count) {
-
- AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
- AssertFatal(mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
-
- ss_id++;
- }
- if (mac->ra_state == WAIT_RAR) {
- // check for RAR
- rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15;
- rel15->rnti = 2;//get_RA_RNTI(mac,frame,slot);
- dl_config->number_pdus = dl_config->number_pdus + 1;
- }
- else if (mac->ra_state == WAIT_CONTENTION_RESOLUTION) {
- rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15;
- rel15->rnti = mac->t_crnti;
- dl_config->number_pdus = dl_config->number_pdus + 1;
- }
- if (mac->crnti>0) {
- rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15;
- rel15->rnti = mac->crnti;
- rel15->BWPSize = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
- rel15->BWPStart = NRRIV2PRBOFFSET(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
- rel15->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing;
- // get UE-specific search space
- for (ss_id=0;ss_id<FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[0][0][ss_id]!=NULL;ss_id++)
- if (mac->SSpace[0][0][ss_id]->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) break;
- AssertFatal(ss_id<FAPI_NR_MAX_SS_PER_CORESET,"couldn't find a UE-specific SS\n");
- // for SPS=14 8 MSBs in positions 13 downto 6,
- uint16_t monitoringSymbolsWithinSlot = (mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
- (mac->SSpace[0][0][ss_id]->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
-
- for (int i=0; i<sps; i++)
- if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
- rel15->coreset.StartSymbolIndex=i;
- break;
- }
- rel15->coreset.duration = mac->coreset[0][0]->duration;
- for (int i=0;i<6;i++)
- rel15->coreset.frequency_domain_resource[i] = mac->coreset[0][0]->frequencyDomainResources.buf[i];
-
- rel15->coreset.CceRegMappingType = mac->coreset[0][0]->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
- FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
- if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) {
- rel15->coreset.RegBundleSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
- rel15->coreset.InterleaverSize = (mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->interleaverSize);
- AssertFatal(mac->scc->physCellId != NULL,"mac->scc->physCellId is null\n");
- rel15->coreset.ShiftIndex = mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *mac->coreset[0][0]->cce_REG_MappingType.choice.interleaved->shiftIndex : *mac->scc->physCellId;
- }
- else {
- rel15->coreset.RegBundleSize = 0;
- rel15->coreset.InterleaverSize = 0;
- rel15->coreset.ShiftIndex = 0;
- }
- rel15->coreset.CoreSetType = 1;
- rel15->coreset.precoder_granularity = mac->coreset[0][0]->precoderGranularity;
- if (mac->coreset[0][0]->pdcch_DMRS_ScramblingID)
- rel15->coreset.pdcch_dmrs_scrambling_id = *mac->coreset[0][0]->pdcch_DMRS_ScramblingID;
- else
- rel15->coreset.pdcch_dmrs_scrambling_id = *mac->scc->physCellId;
- fill_dci_search_candidates(mac->SSpace[0][0][ss_id],rel15);
- rel15->dci_format = NR_DL_DCI_FORMAT_1_0;
- rel15->dci_length = nr_dci_size(rel15->dci_format,NR_RNTI_C,rel15->BWPSize);
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
- dl_config->number_pdus = dl_config->number_pdus + 1;
+void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15, fapi_nr_dl_config_request_t *dl_config, int rnti_type, int ss_id, uint8_t dci_format){
+
+ uint16_t monitoringSymbolsWithinSlot;
+ uint8_t bwp_id = 1, coreset_id = 1;
+ int sps;
+ def_dci_pdu_rel15 = calloc(1,sizeof(dci_pdu_rel15_t));
+ AssertFatal(mac->scc != NULL, "scc is null\n");
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_BWP_DownlinkCommon_t *bwp_Common = mac->DLbwp[bwp_id - 1]->bwp_Common;
+ NR_BWP_DownlinkCommon_t *initialDownlinkBWP = scc->downlinkConfigCommon->initialDownlinkBWP;
+ NR_SearchSpace_t *ss = mac->SSpace[bwp_id - 1][coreset_id - 1][ss_id];
+
+ // DCI format configuration
+ rel15->dci_format = dci_format;
+
+ // CORESET configuration
+ NR_ControlResourceSet_t *coreset = mac->coreset[bwp_id - 1][coreset_id - 1];
+ rel15->coreset.duration = coreset->duration;
+ for (int i = 0; i < 6; i++)
+ rel15->coreset.frequency_domain_resource[i] = coreset->frequencyDomainResources.buf[i];
+ rel15->coreset.CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved ? FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED : FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
+ if (rel15->coreset.CceRegMappingType == FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED) {
+ struct NR_ControlResourceSet__cce_REG_MappingType__interleaved *interleaved = coreset->cce_REG_MappingType.choice.interleaved;
+ rel15->coreset.RegBundleSize = (interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2 + interleaved->reg_BundleSize);
+ rel15->coreset.InterleaverSize = (interleaved->interleaverSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2 + interleaved->interleaverSize);
+ AssertFatal(scc->physCellId != NULL, "mac->scc->physCellId is null\n");
+ rel15->coreset.ShiftIndex = interleaved->shiftIndex != NULL ? *interleaved->shiftIndex : *scc->physCellId;
+ } else {
+ rel15->coreset.RegBundleSize = 0;
+ rel15->coreset.InterleaverSize = 0;
+ rel15->coreset.ShiftIndex = 0;
+ }
+ rel15->coreset.CoreSetType = 1;
+ rel15->coreset.precoder_granularity = coreset->precoderGranularity;
+
+ // Scrambling RNTI
+ if (coreset->pdcch_DMRS_ScramblingID) {
+ rel15->coreset.pdcch_dmrs_scrambling_id = *coreset->pdcch_DMRS_ScramblingID;
+ rel15->coreset.scrambling_rnti = mac->t_crnti;
+ } else {
+ rel15->coreset.pdcch_dmrs_scrambling_id = *scc->physCellId;
+ rel15->coreset.scrambling_rnti = 0;
+ }
+
+ #ifdef DEBUG_DCI
+ LOG_D(MAC, "[DCI_CONFIG] Configure DCI PDU: ss_id %d bwp %p bwp_Id %d controlResourceSetId %d\n", ss_id, mac->DLbwp[bwp_id - 1], mac->DLbwp[bwp_id - 1]->bwp_Id, coreset->controlResourceSetId);
+ #endif
+
+ // loop over RNTI type and configure resource allocation for DCI
+ switch(rnti_type) {
+ case NR_RNTI_C:
+ // we use DL BWP dedicated
+ sps = bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
+ // for SPS=14 8 MSBs in positions 13 down to 6
+ monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
+ rel15->rnti = mac->crnti;
+ rel15->BWPSize = NRRIV2BW(bwp_Common->genericParameters.locationAndBandwidth, 275);
+ rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275);
+ rel15->SubcarrierSpacing = bwp_Common->genericParameters.subcarrierSpacing;
+ rel15->dci_length = nr_dci_size(scc, mac->scg, def_dci_pdu_rel15, rel15->dci_format, NR_RNTI_C, rel15->BWPSize, bwp_id);
+ break;
+ case NR_RNTI_RA:
+ // we use the initial DL BWP
+ sps = initialDownlinkBWP->genericParameters.cyclicPrefix == NULL ? 14 : 12;
+ monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) | (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
+ rel15->rnti = mac->ra_rnti;
+ rel15->BWPSize = NRRIV2BW(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275);
+ rel15->BWPStart = NRRIV2PRBOFFSET(bwp_Common->genericParameters.locationAndBandwidth, 275); //NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275);
+ rel15->SubcarrierSpacing = initialDownlinkBWP->genericParameters.subcarrierSpacing;
+ rel15->dci_length = nr_dci_size(scc, mac->scg, def_dci_pdu_rel15, rel15->dci_format, NR_RNTI_RA, rel15->BWPSize, bwp_id);
+ break;
+ case NR_RNTI_P:
+ break;
+ case NR_RNTI_CS:
+ break;
+ case NR_RNTI_TC:
+ break;
+ case NR_RNTI_SP_CSI:
+ break;
+ case NR_RNTI_SI:
+ break;
+ case NR_RNTI_SFI:
+ break;
+ case NR_RNTI_INT:
+ break;
+ case NR_RNTI_TPC_PUSCH:
+ break;
+ case NR_RNTI_TPC_PUCCH:
+ break;
+ case NR_RNTI_TPC_SRS:
+ break;
+ default:
+ break;
+ }
+ for (int i = 0; i < sps; i++) {
+ if ((monitoringSymbolsWithinSlot >> (sps - 1 - i)) & 1) {
+ rel15->coreset.StartSymbolIndex = i;
+ break;
}
}
+ #ifdef DEBUG_DCI
+ LOG_D(MAC, "[DCI_CONFIG] Configure DCI PDU: rnti_type %d BWPSize %d BWPStart %d rel15->SubcarrierSpacing %d rel15->dci_format %d rel15->dci_length %d sps %d monitoringSymbolsWithinSlot %d \n",
+ rnti_type,
+ rel15->BWPSize,
+ rel15->BWPStart,
+ rel15->SubcarrierSpacing,
+ rel15->dci_format,
+ rel15->dci_length,
+ sps,
+ monitoringSymbolsWithinSlot);
+ #endif
+ // add DCI
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
+ dl_config->number_pdus = dl_config->number_pdus + 1;
}
+void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl_config, frame_t frame, int slot) {
+
+ int ss_id;
+ uint8_t bwp_id = 1, coreset_id = 1;
+ NR_ServingCellConfig_t *scd = mac->scg->spCellConfig->spCellConfigDedicated;
+ NR_BWP_Downlink_t *bwp = mac->DLbwp[bwp_id - 1];
+ #ifdef DEBUG_DCI
+ LOG_D(MAC, "[DCI_CONFIG] ra_rnti %p (%x) crnti %p (%x) t_crnti %p (%x)\n", &mac->ra_rnti, mac->ra_rnti, &mac->crnti, mac->crnti, &mac->t_crnti, mac->t_crnti);
+ #endif
+ // loop over all available SS for BWP ID 1, CORESET ID 1
+ for (ss_id = 0; ss_id < FAPI_NR_MAX_SS_PER_CORESET && mac->SSpace[bwp_id - 1][coreset_id - 1][ss_id] != NULL; ss_id++){
+ NR_SearchSpace_t *ss = mac->SSpace[bwp_id - 1][coreset_id - 1][ss_id];
+ fapi_nr_dl_config_dci_dl_pdu_rel15_t *rel15 = &dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15;
+ NR_BWP_DownlinkCommon_t *bwp_Common = bwp->bwp_Common;
+ NR_SetupRelease_PDCCH_ConfigCommon_t *pdcch_ConfigCommon = bwp_Common->pdcch_ConfigCommon;
+ struct NR_PhysicalCellGroupConfig *phy_cgc = mac->scg->physicalCellGroupConfig;
+ switch (ss->searchSpaceType->present){
+ case NR_SearchSpace__searchSpaceType_PR_common:
+ // this is for CSSs, we use BWP common and pdcch_ConfigCommon
+ // Fetch configuration for searchSpaceZero
+ // note: The search space with the SearchSpaceId = 0 identifies the search space configured via PBCH (MIB) and in ServingCellConfigCommon (searchSpaceZero).
+ if (pdcch_ConfigCommon->choice.setup->searchSpaceZero){
+ LOG_D(MAC, "[DCI_CONFIG] Configure SearchSpace#0 of the initial BWP\n");
+ LOG_W(MAC, "[DCI_CONFIG] This should not be available yet...");
+ }
+ if (ss->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0){
+ // check available SS IDs
+ if (pdcch_ConfigCommon->choice.setup->ra_SearchSpace){
+ if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->ra_SearchSpace){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space\n");
+ switch(mac->ra_state){
+ case WAIT_RAR:
+ config_dci_pdu(mac, rel15, dl_config, NR_RNTI_RA, ss_id, NR_DL_DCI_FORMAT_1_0);
+ fill_dci_search_candidates(ss, rel15);
+ break;
+ case WAIT_CONTENTION_RESOLUTION:
+ rel15->rnti = mac->t_crnti;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ if (pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
+ if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
+ // Configure monitoring of PDCCH candidates in Type0-PDCCH common search space on the MCG
+ LOG_W(MAC, "[DCI_CONFIG] This seach space should not be configured yet...");
+ }
+ }
+ if (pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation){
+ if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation){
+ // Configure monitoring of PDCCH candidates in Type0-PDCCH common search space on the MCG
+ LOG_W(MAC, "[DCI_CONFIG] This seach space should not be configured yet...");
+ }
+ }
+ if (pdcch_ConfigCommon->choice.setup->pagingSearchSpace){
+ if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->pagingSearchSpace){
+ // Configure monitoring of PDCCH candidates in Type2-PDCCH common search space on the MCG
+ LOG_W(MAC, "[DCI_CONFIG] This seach space should not be configured yet...");
+ }
+ }
+ if (phy_cgc){
+ if (phy_cgc->cs_RNTI){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type3-PDCCH common search space for dci_Format0_0_AndFormat1_0 with CRC scrambled by CS-RNTI...\n");
+ LOG_W(MAC, "[DCI_CONFIG] This RNTI should not be configured yet...");
+ }
+ if (phy_cgc->ext1){
+ if (phy_cgc->ext1->mcs_C_RNTI){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in user specific search space for dci_Format0_0_AndFormat1_0 with CRC scrambled by MCS-C-RNTI...\n");
+ LOG_W(MAC, "[DCI_CONFIG] This RNTI should not be configured yet...");
+ }
+ }
+ }
+ } // end DCI 00 and 01
+ // DCI 2_0
+ if (ss->searchSpaceType->choice.common->dci_Format2_0){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type3-PDCCH common search space for DCI format 2_0 with CRC scrambled by SFI-RNTI \n");
+ LOG_W(MAC, "[DCI_CONFIG] This format should not be configured yet...");
+ }
+ // DCI 2_1
+ if (ss->searchSpaceType->choice.common->dci_Format2_1){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type3-PDCCH common search space for DCI format 2_1 with CRC scrambled by INT-RNTI \n");
+ LOG_W(MAC, "[DCI_CONFIG] This format should not be configured yet...");
+ }
+ // DCI 2_2
+ if (ss->searchSpaceType->choice.common->dci_Format2_2){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type3-PDCCH common search space for DCI format 2_2 with CRC scrambled by TPC-RNTI \n");
+ LOG_W(MAC, "[DCI_CONFIG] This format should not be configured yet...");
+ }
+ // DCI 2_3
+ if (ss->searchSpaceType->choice.common->dci_Format2_3){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type3-PDCCH common search space for DCI format 2_3 with CRC scrambled by TPC-SRS-RNTI \n");
+ LOG_W(MAC, "[DCI_CONFIG] This format should not be configured yet...");
+ }
+
+ break;
+ case NR_SearchSpace__searchSpaceType_PR_ue_Specific:
+ // this is an USS
+ if (ss->searchSpaceType->choice.ue_Specific){
+ if(ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_1_And_1_1){
+ // Monitors DCI 01 and 11 scrambled with C-RNTI, or CS-RNTI(s), or SP-CSI-RNTI
+ if (get_softmodem_params()->phy_test == 1 && mac->crnti > 0) {
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in the user specific search space\n");
+ config_dci_pdu(mac, rel15, dl_config, NR_RNTI_C, ss_id, NR_DL_DCI_FORMAT_1_1);
+ fill_dci_search_candidates(ss, rel15);
+
+ #ifdef DEBUG_DCI
+ LOG_D(MAC, "[DCI_CONFIG] ss %d ue_Specific %p searchSpaceType->present %d dci_Formats %d\n",
+ ss_id,
+ ss->searchSpaceType->choice.ue_Specific,
+ ss->searchSpaceType->present,
+ ss->searchSpaceType->choice.ue_Specific->dci_Formats);
+ #endif
+ }
+ if (phy_cgc){
+ if (phy_cgc->cs_RNTI){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in user specific search space for dci_Format0_0_AndFormat1_0 with CRC scrambled by CS-RNTI...\n");
+ LOG_W(MAC, "[DCI_CONFIG] This RNTI should not be configured yet...");
+ }
+ if (phy_cgc->sp_CSI_RNTI){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in user specific search space for dci_Format0_0_AndFormat1_0 with CRC scrambled by SP-CSI-RNTI...\n");
+ LOG_W(MAC, "[DCI_CONFIG] This RNTI should not be configured yet...");
+ }
+ if (phy_cgc->ext1){
+ if (phy_cgc->ext1->mcs_C_RNTI){
+ LOG_D(MAC, "[DCI_CONFIG] Configure monitoring of PDCCH candidates in user specific search space for dci_Format0_0_AndFormat1_0 with CRC scrambled by MCS-C-RNTI...\n");
+ LOG_W(MAC, "[DCI_CONFIG] This RNTI should not be configured yet...");
+ }
+ }
+ }
+ }
+ }
+ break;
+ default:
+ AssertFatal(1 == 0, "[DCI_CONFIG] Unrecognized search space type...");
+ break;
+ }
+ }
+}
diff --git a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
index 860b73276c307aa41041fd34008f2800109c1301..60f331a08627534f34b3d70d7718c83919b11175 100644
--- a/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+++ b/openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
@@ -31,28 +31,38 @@
*/
-/* MAC related headers */
-#include "mac_proto.h"
+#include <stdio.h>
+#include <math.h>
+
+/* exe */
+#include "executables/nr-softmodem.h"
+
+/* RRC*/
+#include "RRC/NR_UE/rrc_proto.h"
+#include "NR_RACH-ConfigCommon.h"
+#include "NR_RACH-ConfigGeneric.h"
+#include "NR_FrequencyInfoDL.h"
+#include "NR_PDCCH-ConfigCommon.h"
+
+/* MAC */
#include "mac_defs.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac.h"
-#include "mac_extern.h"
+#include "NR_MAC_COMMON/nr_mac.h"
+#include "NR_MAC_UE/mac_proto.h"
+#include "NR_MAC_UE/mac_extern.h"
#include "common/utils/nr/nr_common.h"
-//#include "LAYER2/MAC/mac_vars.h" // TODO Note that mac_vars.h is not NR specific and this should be updated
- // also, the use of the same should be updated in nr-softmodem and nr-uesoftmodem
-
-/* PHY UE related headers*/
+/* PHY UE */
#include "SCHED_NR_UE/defs.h"
-
-#include "RRC/NR_UE/rrc_proto.h"
-#include "assertions.h"
#include "PHY/defs_nr_UE.h"
/*Openair Packet Tracer */
#include "UTIL/OPT/opt.h"
#include "OCG.h"
#include "executables/softmodem-common.h"
-/* log utils */
+
+/* utils */
+#include "assertions.h"
+
#include "common/utils/LOG/log.h"
#include "SIMULATION/TOOLS/sim.h" // for taus
#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac.h"
@@ -60,11 +70,14 @@
#include <stdio.h>
#include <math.h>
-//int mbms_rab_id = 2047;
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
#define DEBUG_EXTRACT_DCI 1
+extern int bwp_id;
+extern dci_pdu_rel15_t *def_dci_pdu_rel15;
+extern const uint16_t nr_slots_per_frame[5];
+
extern void mac_rlc_data_ind (
const module_id_t module_idP,
const rnti_t rntiP,
@@ -118,7 +131,7 @@ int8_t nr_ue_process_dlsch(module_id_t module_id,
//fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
nr_phy_config_t *phy_config = &mac->phy_config;
- //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti;
// First we need to verify if DCI ind contains a ul-sch to be perfomred. If it does, we will handle a PUSCH in the UL_CONFIG_REQ.
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
for (int i=0; i<10; i++) {
@@ -128,29 +141,28 @@ int8_t nr_ue_process_dlsch(module_id_t module_id,
}
if (ul_config->ul_config_list[ul_config->number_pdus].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUSCH) {
// fill in the elements in config request inside P5 message
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.bandwidth_part_ind = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.frame_offset = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.pusch_freq_hopping = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.mcs = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.harq_process_nbr = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.accumulated_delta_PUSCH = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.tpmi = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_dmrs_cdm_groups = 0;
- for (int i=0;i<4;i++) ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.dmrs_ports[i]=0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.n_front_load_symb = 0;
- //ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.srs_config = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.csi_reportTriggerSize = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.maxCodeBlockGroupsPerTransportBlock = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.ptrs_dmrs_association_port = 0;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15.beta_offset_ind = 0;
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.bandwidth_part_ind = 0; //FIXME
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rb_size = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rb_start = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.nr_of_symbols = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.start_symbol_index = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.frequency_hopping = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.mcs_index = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.new_data_indicator = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.rv_index = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.pusch_data.harq_process_id = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.absolute_delta_PUSCH = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.nrOfLayers = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.transform_precoding = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.dmrs_ports = 0;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.dmrs_config_type = 0;
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.n_front_load_symb = 0; //FIXME
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.srs_config = 0; //FIXME
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.csi_reportTriggerSize = 0; //FIXME
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.maxCodeBlockGroupsPerTransportBlock = 0; //FIXME
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.ptrs_dmrs_association_port = 0; FIXME
+ //ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.beta_offset_ind = 0; //FIXME
} else { // If DCI ind is not format 0_0 or 0_1, we will handle a PUCCH in the UL_CONFIG_REQ
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUCCH;
// If we handle PUCCH common
@@ -262,7 +274,7 @@ int8_t nr_ue_decode_mib(module_id_t module_id,
uint16_t frame_number_4lsb = 0;
for (int i=0; i<4; i++)
frame_number_4lsb |= ((extra_bits>>i)&1)<<(3-i);
- uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4]
+ //uint8_t half_frame_bit = ( extra_bits >> 4 ) & 0x1; // extra bits[4]
uint8_t ssb_subcarrier_offset_msb = ( extra_bits >> 5 ) & 0x1; // extra bits[5]
uint8_t ssb_subcarrier_offset = (uint8_t)mac->mib->ssb_SubcarrierOffset;
@@ -468,7 +480,6 @@ int8_t nr_ue_decode_mib(module_id_t module_id,
uint32_t number_of_search_space_per_slot=UINT_MAX;
uint32_t first_symbol_index=UINT_MAX;
uint32_t search_space_duration; // element of search space
- uint32_t coreset_duration; // element of coreset
// 38.213 table 10.1-1
/// MUX PATTERN 1
@@ -604,8 +615,8 @@ int8_t nr_ue_decode_mib(module_id_t module_id,
}
AssertFatal(number_of_search_space_per_slot!=UINT_MAX,"");
- coreset_duration = num_symbols * number_of_search_space_per_slot;
/*
+ uint32_t coreset_duration = num_symbols * number_of_search_space_per_slot;
mac->type0_pdcch_dci_config.number_of_candidates[0] = table_38213_10_1_1_c2[0];
mac->type0_pdcch_dci_config.number_of_candidates[1] = table_38213_10_1_1_c2[1];
mac->type0_pdcch_dci_config.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
@@ -643,98 +654,472 @@ uint32_t get_ssb_frame(uint32_t test){
// 1. TODO: Call RRC for link status return to PHY
// 2. TODO: Perform SR/BSR procedures for scheduling feedback
// 3. TODO: Perform PHR procedures
-NR_UE_L2_STATE_t nr_ue_scheduler(const module_id_t module_id,
- const uint8_t gNB_index,
- const int cc_id,
- const frame_t rx_frame,
- const slot_t rx_slot,
- const int32_t ssb_index,
- const frame_t tx_frame,
- const slot_t tx_slot ){
+NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_indication_t *ul_info){
uint32_t search_space_mask = 0;
- NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
-
- // check type0 from 38.213 13 if we have no CellGroupConfig
- if ( mac->scd == NULL) {
- if( ssb_index != -1){
-
- if(mac->type0_pdcch_ss_mux_pattern == 1){
- // 38.213 chapter 13
- if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
- }
- if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
- }
- }
- if(mac->type0_pdcch_ss_mux_pattern == 2){
- // 38.213 Table 13-13, 13-14
- if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
- }
+ if (dl_info){
+
+ module_id_t mod_id = dl_info->module_id;
+ uint32_t gNB_index = dl_info->gNB_index;
+ int cc_id = dl_info->cc_id;
+ frame_t rx_frame = dl_info->frame;
+ slot_t rx_slot = dl_info->slot;
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+
+ fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
+ nr_scheduled_response_t scheduled_response;
+ nr_dcireq_t dcireq;
+
+ // check type0 from 38.213 13 if we have no CellGroupConfig
+ // TODO: implementation to be completed
+ if (mac->scg == NULL) {
+ if(dl_info->ssb_index != -1){
+
+ if(mac->type0_pdcch_ss_mux_pattern == 1){
+ // 38.213 chapter 13
+ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_0) && !(rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ if(mac->type0_pdcch_ss_mux_pattern == 2){
+ // 38.213 Table 13-13, 13-14
+ if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ if(mac->type0_pdcch_ss_mux_pattern == 3){
+ // 38.213 Table 13-15
+ if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
+ search_space_mask = search_space_mask | type0_pdcch;
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
+ }
+ }
+ } // ssb_index != -1
+
+ // Type0 PDCCH search space
+ if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
+ mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
+
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
+
+ /*
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set
+
+ LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n",
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti,
+ dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP);
+ */
+ dl_config->number_pdus = dl_config->number_pdus + 1;
+ mac->scheduled_response.dl_config = dl_config;
}
- if(mac->type0_pdcch_ss_mux_pattern == 3){
- // 38.213 Table 13-15
- if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
- search_space_mask = search_space_mask | type0_pdcch;
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.coreset.duration;
- }
+ } else { // we have an scg
+
+ dcireq.module_id = mod_id;
+ dcireq.gNB_index = gNB_index;
+ dcireq.cc_id = cc_id;
+ dcireq.frame = rx_frame;
+ dcireq.slot = rx_slot;
+ nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
+
+ // we should have received a DL DCI here, so configure DL accordingly
+ scheduled_response.dl_config = &dcireq.dl_config_req;
+ scheduled_response.ul_config = NULL;
+ scheduled_response.tx_request = NULL;
+ scheduled_response.module_id = mod_id;
+ scheduled_response.CC_id = cc_id;
+ scheduled_response.frame = rx_frame;
+ scheduled_response.slot = rx_slot;
+
+ if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){
+ mac->if_module->scheduled_response(&scheduled_response);
}
- } // ssb_index != -1
-
- // Type0 PDCCH search space
- if((search_space_mask & type0_pdcch) || ( mac->type0_pdcch_consecutive_slots != 0 )){
- mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_consecutive_slots - 1;
-
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15 = mac->type0_pdcch_dci_config;
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
-
+
/*
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti = 0xaaaa; // to be set
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = 106; // to be set
-
- LOG_I(MAC,"nr_ue_scheduler Type0 PDCCH with rnti %x, BWP %d\n",
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.rnti,
- dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP);
- */
- dl_config->number_pdus = dl_config->number_pdus + 1;
+ if(search_space_mask & type0a_pdcch){
+ }
+
+ if(search_space_mask & type1_pdcch){
+ }
+
+ if(search_space_mask & type2_pdcch){
+ }
+
+ if(search_space_mask & type3_pdcch){
+ }
+ */
}
- }
- else { // get PDCCH configuration(s) from SCGConfig
-
+ } else if (ul_info) {
+
+ if (get_softmodem_params()->phy_test && ul_info->slot_tx == 8) { // ULSCH is handled only in phy-test mode (consistently with OAI gNB)
+
+ uint8_t nb_dmrs_re_per_rb;
+ uint8_t ulsch_input_buffer[MAX_ULSCH_PAYLOAD_BYTES];
+ uint8_t data_existing = 0;
+ uint16_t TBS_bytes;
+ uint32_t TBS;
+ int i;
+
+ module_id_t mod_id = ul_info->module_id;
+ uint32_t gNB_index = ul_info->gNB_index;
+ int cc_id = ul_info->cc_id;
+ frame_t rx_frame = ul_info->frame_rx;
+ slot_t rx_slot = ul_info->slot_rx;
+ frame_t frame_tx = ul_info->frame_tx;
+ slot_t slot_tx = ul_info->slot_tx;
+ NR_UE_MAC_INST_t *mac = get_mac_inst(mod_id);
+ uint8_t access_mode = SCHEDULED_ACCESS;
+
+ // program PUSCH. this should actually be done upon reception of an UL DCI
+ nr_dcireq_t dcireq;
+ nr_scheduled_response_t scheduled_response;
+ fapi_nr_tx_request_t tx_req;
+ fapi_nr_tx_request_body_t tx_req_body;
+
+ //--------------------------Temporary configuration-----------------------------//
+ uint16_t rnti = 0x1234;
+ uint32_t rb_size = 50;
+ uint32_t rb_start = 0;
+ uint8_t nr_of_symbols = 11;
+ uint8_t start_symbol_index = 0;
+ uint8_t nrOfLayers = 1;
+ uint8_t mcs_index = 9;
+ uint8_t mcs_table = 0;
+ uint8_t harq_process_id = 0;
+ uint8_t rv_index = 0;
+ uint16_t l_prime_mask = get_l_prime(nr_of_symbols, typeB, pusch_dmrs_pos0, pusch_len1);
+ uint8_t dmrs_config_type = 0;
+ uint8_t ptrs_mcs1 = 2;
+ uint8_t ptrs_mcs2 = 4;
+ uint8_t ptrs_mcs3 = 10;
+ uint16_t n_rb0 = 25;
+ uint16_t n_rb1 = 75;
+ uint16_t pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
+ uint8_t ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, mcs_index, mcs_table);
+ uint8_t ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, rb_size);
+ uint8_t no_data_in_dmrs = 1;
+ uint16_t number_dmrs_symbols = 0;
+ uint16_t ul_dmrs_symb_pos = l_prime_mask << start_symbol_index;
+ //------------------------------------------------------------------------------//
+
+ for (i = start_symbol_index; i < start_symbol_index + nr_of_symbols; i++) {
+ if((ul_dmrs_symb_pos >> i) & 0x01)
+ number_dmrs_symbols += 1;
+ }
-
+ if(no_data_in_dmrs)
+ nb_dmrs_re_per_rb = 12;
+ else
+ nb_dmrs_re_per_rb = ((dmrs_config_type == pusch_dmrs_type1) ? 6:4);
+
+ TBS = nr_compute_tbs(nr_get_Qm_ul(mcs_index, 0),
+ nr_get_code_rate_ul(mcs_index, 0),
+ rb_size,
+ nr_of_symbols,
+ nb_dmrs_re_per_rb*number_dmrs_symbols,
+ 0,
+ 0,
+ nrOfLayers);
+ TBS_bytes = TBS/8;
+
+ if (IS_SOFTMODEM_NOS1){
+ // Getting IP traffic to be transmitted
+ data_existing = nr_ue_get_sdu(mod_id,
+ cc_id,
+ frame_tx,
+ slot_tx,
+ 0,
+ ulsch_input_buffer,
+ TBS_bytes,
+ &access_mode);
+ }
- // get Coreset and SearchSpace Information from spCellConfigDedicated
-
-
-
- /*
- if(search_space_mask & type0a_pdcch){
+ //Random traffic to be transmitted if there is no IP traffic available for this Tx opportunity
+ if (!IS_SOFTMODEM_NOS1 || !data_existing) {
+ //Use zeros for the header bytes in noS1 mode, in order to make sure that the LCID is not valid
+ //and block this traffic from being forwarded to the upper layers at the gNB
+ LOG_D(PHY, "Random data to be tranmsitted: \n");
+
+ //Give the first byte a dummy value (a value not corresponding to any valid LCID based on 38.321, Table 6.2.1-2)
+ //in order to distinguish the PHY random packets at the MAC layer of the gNB receiver from the normal packets that should
+ //have a valid LCID (nr_process_mac_pdu function)
+ ulsch_input_buffer[0] = 0x31;
+
+ for (i = 1; i < TBS_bytes; i++) {
+ ulsch_input_buffer[i] = (unsigned char) rand();
+ //printf(" input encoder a[%d]=0x%02x\n",i,harq_process_ul_ue->a[i]);
+ }
+ }
+
+#ifdef DEBUG_MAC_PDU
+
+ LOG_D(PHY, "Is data existing ?: %d \n", data_existing);
+ LOG_I(PHY, "Printing MAC PDU to be encoded, TBS is: %d \n", TBS_bytes);
+ for (i = 0; i < TBS_bytes; i++) {
+ printf("%02x", ulsch_input_buffer[i]);
+ }
+ printf("\n");
+
+#endif
+
+ dcireq.module_id = mod_id;
+ dcireq.gNB_index = gNB_index;
+ dcireq.cc_id = cc_id;
+ dcireq.frame = rx_frame;
+ dcireq.slot = rx_slot;
+
+ scheduled_response.dl_config = NULL;
+ scheduled_response.ul_config = &dcireq.ul_config_req;
+ // Config UL TX PDU
+ tx_req.slot = slot_tx;
+ tx_req.sfn = frame_tx;
+ // tx_req->tx_config // TbD
+ tx_req.number_of_pdus = 1;
+ tx_req_body.pdu_length = TBS_bytes;
+ tx_req_body.pdu_index = 0;
+ tx_req_body.pdu = ulsch_input_buffer;
+
+ scheduled_response.tx_request = &tx_req;
+ scheduled_response.tx_request->tx_request_body = &tx_req_body;
+ scheduled_response.module_id = mod_id;
+ scheduled_response.CC_id = cc_id;
+ scheduled_response.frame = rx_frame;
+ scheduled_response.slot = rx_slot;
+
+ scheduled_response.ul_config->slot = ul_info->slot_tx;
+ scheduled_response.ul_config->number_pdus = 1;
+ scheduled_response.ul_config->ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rnti = rnti;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_size = rb_size;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.rb_start = rb_start;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nr_of_symbols = nr_of_symbols;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.start_symbol_index = start_symbol_index;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.ul_dmrs_symb_pos = ul_dmrs_symb_pos;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.harq_process_id = harq_process_id;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map = pdu_bit_map;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_time_density = ptrs_time_density;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_freq_density = ptrs_freq_density;
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list = (nfapi_nr_ue_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ue_ptrs_ports_t));
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
+
+ if (1 << ptrs_time_density >= nr_of_symbols) {
+ scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS
}
-
- if(search_space_mask & type1_pdcch){
+
+ if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL){
+ mac->if_module->scheduled_response(&scheduled_response);
}
-
- if(search_space_mask & type2_pdcch){
+
+ // TODO: expand
+ // Note: Contention resolution is currently not active
+ if (mac->RA_contention_resolution_timer_active == 1)
+ ue_contention_resolution(mod_id, gNB_index, cc_id, ul_info->frame_tx);
+ }
+ }
+ return UE_CONNECTION_OK;
+}
+
+// This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211, tables 6.3.3.2.x
+// It fills the PRACH PDU per each FD occasion.
+// PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3.
+// - todo:
+// - Partial configuration is actually already stored in (fapi_nr_prach_config_t) &mac->phy_config.config_req->prach_config
+void nr_ue_prach_scheduler(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
+
+ uint8_t config_index, mu, N_dur, N_t_slot, start_symbol;
+ uint16_t format, format0, format1, ncs;
+ int msg1_FDM, is_nr_prach_slot, fdm;
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
+
+ fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
+ fapi_nr_ul_config_prach_pdu *prach_config_pdu;
+ fapi_nr_config_request_t *cfg = &mac->phy_config.config_req;
+ fapi_nr_prach_config_t *prach_config = &cfg->prach_config;
+
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *setup = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+ NR_FrequencyInfoDL_t *frequencyInfoDL = scc->downlinkConfigCommon->frequencyInfoDL;
+ NR_RACH_ConfigGeneric_t *rach_ConfigGeneric = &setup->rach_ConfigGeneric;
+ config_index = rach_ConfigGeneric->prach_ConfigurationIndex;
+
+ mac->RA_offset = 2; // to compensate the rx frame offset at the gNB
+ mac->generate_nr_prach = 0; // Reset flag for PRACH generation
+
+ if (is_nr_UL_slot(scc, slotP)) {
+
+ if (setup->msg1_SubcarrierSpacing)
+ mu = *setup->msg1_SubcarrierSpacing;
+ else
+ mu = frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
+
+ is_nr_prach_slot = get_nr_prach_info_from_index(config_index,
+ (int)frameP,
+ (int)slotP,
+ frequencyInfoDL->absoluteFrequencyPointA,
+ mu,
+ cfg->cell_config.frame_duplex_type,
+ &format,
+ &start_symbol,
+ &N_t_slot,
+ &N_dur);
+
+ if (is_nr_prach_slot && mac->ra_state == RA_UE_IDLE) {
+
+ mac->generate_nr_prach = 1;
+
+ fdm = rach_ConfigGeneric->msg1_FDM;
+
+ switch (fdm){
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ msg1_FDM = 1 << fdm;
+ break;
+ default:
+ AssertFatal(1 == 0, "Unknown msg1_FDM from rach_ConfigGeneric %d\n", fdm);
}
-
- if(search_space_mask & type3_pdcch){
+
+ format0 = format & 0xff; // single PRACH format
+ format1 = (format >> 8) & 0xff; // dual PRACH format
+
+ ul_config->sfn = frameP;
+ ul_config->slot = slotP;
+
+ for (int n = 0; n < msg1_FDM; n++) { // one structure per frequency domain occasion
+
+ ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PRACH;
+ prach_config_pdu = &ul_config->ul_config_list[ul_config->number_pdus].prach_config_pdu;
+ memset(prach_config_pdu, 0, sizeof(fapi_nr_ul_config_prach_pdu));
+ ul_config->number_pdus += 1;
+
+ ncs = get_NCS(rach_ConfigGeneric->zeroCorrelationZoneConfig, format0, setup->restrictedSetConfig);
+
+ // filling PRACH PDU for FAPI config request
+ prach_config_pdu->phys_cell_id = *scc->physCellId;
+ prach_config_pdu->num_prach_ocas = N_t_slot;
+ prach_config_pdu->prach_start_symbol = start_symbol;
+ prach_config_pdu->num_ra = n;
+ prach_config_pdu->num_cs = ncs;
+ prach_config_pdu->root_seq_id = prach_config->num_prach_fd_occasions_list[n].prach_root_sequence_index;
+ prach_config_pdu->restricted_set = prach_config->restricted_set_config;
+ prach_config_pdu->freq_msg1 = prach_config->num_prach_fd_occasions_list[n].k1;
+
+ if (format1 != 0xff) {
+ switch(format0) { // dual PRACH format
+ case 0xa1:
+ prach_config_pdu->prach_format = 9;
+ break;
+ case 0xa2:
+ prach_config_pdu->prach_format = 10;
+ break;
+ case 0xa3:
+ prach_config_pdu->prach_format = 11;
+ break;
+ default:
+ AssertFatal(1 == 0, "Only formats A1/B1 A2/B2 A3/B3 are valid for dual format");
+ }
+ } else {
+ switch(format0) { // single PRACH format
+ case 0xa1:
+ prach_config_pdu->prach_format = 0;
+ break;
+ case 0xa2:
+ prach_config_pdu->prach_format = 1;
+ break;
+ case 0xa3:
+ prach_config_pdu->prach_format = 2;
+ break;
+ case 0xb1:
+ prach_config_pdu->prach_format = 3;
+ break;
+ case 0xb2:
+ prach_config_pdu->prach_format = 4;
+ break;
+ case 0xb3:
+ prach_config_pdu->prach_format = 5;
+ break;
+ case 0xb4:
+ prach_config_pdu->prach_format = 6;
+ break;
+ case 0xc0:
+ prach_config_pdu->prach_format = 7;
+ break;
+ case 0xc2:
+ prach_config_pdu->prach_format = 8;
+ break;
+ case 0:
+ // long formats are handled @ PHY
+ break;
+ case 1:
+ // long formats are handled @ PHY
+ break;
+ case 2:
+ // long formats are handled @ PHY
+ break;
+ case 3:
+ // long formats are handled @ PHY
+ break;
+ default:
+ AssertFatal(1 == 0, "Invalid PRACH format");
+ }
+ }
}
- */
+ } else if (mac->ra_state == RA_SUCCEEDED){
+ mac->generate_nr_prach = 2;
+ }
+ mac->scheduled_response.ul_config = ul_config;
}
+}
+////////////////////////////////////////////////////////////////////////////
+/////////* Random Access Contention Resolution (5.1.35 TS 38.321) */////////
+////////////////////////////////////////////////////////////////////////////
+// Handling contention resolution timer
+// WIP todo:
+// - beam failure recovery
+// - RA completed
- mac->scheduled_response.dl_config = dl_config;
-
-
- return UE_CONNECTION_OK;
+void ue_contention_resolution(module_id_t module_id, uint8_t gNB_index, int cc_id, frame_t tx_frame){
+
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
+ NR_ServingCellConfigCommon_t *scc = mac->scc;
+ NR_RACH_ConfigCommon_t *nr_rach_ConfigCommon = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup;
+
+ if (mac->RA_contention_resolution_timer_active == 1) {
+ if (nr_rach_ConfigCommon){
+ LOG_I(MAC, "Frame %d: Contention resolution timer %d/%ld\n",
+ tx_frame,
+ mac->RA_contention_resolution_cnt,
+ ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3));
+ mac->RA_contention_resolution_cnt++;
+
+ if (mac->RA_contention_resolution_cnt == ((1 + nr_rach_ConfigCommon->ra_ContentionResolutionTimer) << 3)) {
+ mac->t_crnti = 0;
+ mac->RA_active = 0;
+ mac->RA_contention_resolution_timer_active = 0;
+ // Signal PHY to quit RA procedure
+ LOG_E(MAC, "[UE %u] [RAPROC] Contention resolution timer expired, RA failed, discarded TC-RNTI\n", module_id);
+ nr_ra_failed(module_id, cc_id, gNB_index);
+ }
+ }
+ }
}
#if 0
@@ -1669,7 +2054,7 @@ uint8_t table_7_3_2_3_3_4_twoCodeword[6][10] = {
{2,0,1,2,3,6,7,8,0,2},
{2,0,1,2,3,6,7,8,9,2}
};
-int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
+int8_t nr_ue_process_dci_freq_dom_resource_assignment(nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu,
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
@@ -1692,7 +2077,7 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pd
dlsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_DLBWP);
}
- if(ulsch_config_pdu != NULL){
+ if(pusch_config_pdu != NULL){
/*
* TS 38.214 subclause 6.1.2.2 Resource allocation in frequency domain (uplink)
*/
@@ -1703,14 +2088,14 @@ int8_t nr_ue_process_dci_freq_dom_resource_assignment(fapi_nr_ul_config_pusch_pd
* TS 38.214 subclause 6.1.2.2.2 Uplink resource allocation type 1
*/
- ulsch_config_pdu->number_rbs = NRRIV2BW(riv,n_RB_ULBWP);
- ulsch_config_pdu->start_rb = NRRIV2PRBOFFSET(riv,n_RB_ULBWP);
+ pusch_config_pdu->rb_size = NRRIV2BW(riv,n_RB_ULBWP);
+ pusch_config_pdu->rb_start = NRRIV2PRBOFFSET(riv,n_RB_ULBWP);
}
return 0;
}
int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu,
+ nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu,
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu,
uint8_t time_domain_ind
){
@@ -1841,17 +2226,19 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
pdsch_TimeDomainAllocationList = mac->DLbwp[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
if (pdsch_TimeDomainAllocationList) {
- AssertFatal(pdsch_TimeDomainAllocationList->list.count > time_domain_ind,
- "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n",
- time_domain_ind,pdsch_TimeDomainAllocationList->list.count);
+ if (time_domain_ind >= pdsch_TimeDomainAllocationList->list.count) {
+ LOG_E(MAC, "time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d\n",
+ time_domain_ind, pdsch_TimeDomainAllocationList->list.count);
+ dlsch_config_pdu->start_symbol = 0;
+ dlsch_config_pdu->number_symbols = 0;
+ return -1;
+ }
+
int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength;
int S,L;
SLIV2SL(startSymbolAndLength,&S,&L);
dlsch_config_pdu->start_symbol=S;
dlsch_config_pdu->number_symbols=L;
- dlsch_config_pdu->frame_offset = pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0!=NULL ?
- *pdsch_TimeDomainAllocationList->list.array[time_domain_ind]->k0 :
- 0;
}
else {// Default configuration from tables
k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
@@ -1866,14 +2253,13 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
// k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- dlsch_config_pdu->frame_offset = k_offset;
dlsch_config_pdu->number_symbols = sliv_L;
dlsch_config_pdu->start_symbol = sliv_S;
}
} /*
* TS 38.214 subclause 6.1.2.1 Resource allocation in time domain (uplink)
*/
- if(ulsch_config_pdu != NULL){
+ if(pusch_config_pdu != NULL){
NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL;
if (mac->ULbwp[0]->bwp_Dedicated->pusch_Config)
pusch_TimeDomainAllocationList = mac->ULbwp[0]->bwp_Dedicated->pusch_Config->choice.setup->pusch_TimeDomainAllocationList->choice.setup;
@@ -1885,12 +2271,8 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
int startSymbolAndLength = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->startSymbolAndLength;
int S,L;
SLIV2SL(startSymbolAndLength,&S,&L);
- ulsch_config_pdu->start_symbol=S;
- ulsch_config_pdu->number_symbols=L;
- ulsch_config_pdu->frame_offset = pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2!=NULL ?
- *pusch_TimeDomainAllocationList->list.array[time_domain_ind]->k2 :
- mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz60 ? 1 :
- mac->ULbwp[0]->bwp_Common->genericParameters.subcarrierSpacing < NR_SubcarrierSpacing_kHz120 ? 2 : 3;
+ pusch_config_pdu->start_symbol_index=S;
+ pusch_config_pdu->nr_of_symbols=L;
}
else {
k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[time_domain_ind-1][0];
@@ -1899,9 +2281,8 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
// k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
- ulsch_config_pdu->frame_offset = k_offset;
- ulsch_config_pdu->number_symbols = sliv_L;
- ulsch_config_pdu->start_symbol = sliv_S;
+ pusch_config_pdu->nr_of_symbols = sliv_L;
+ pusch_config_pdu->start_symbol_index = sliv_S;
}
}
return 0;
@@ -1910,17 +2291,17 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci) {
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
- nr_dci_pdu_rel15_t dci_pdu_rel15;
LOG_D(MAC,"Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
dci->rnti,dci->dci_format,dci->n_CCE,dci->payloadSize,*(unsigned long long*)dci->payloadBits);
- nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,&dci_pdu_rel15);
- nr_ue_process_dci(module_id, cc_id, gNB_index, &dci_pdu_rel15, dci->rnti, dci->dci_format);
- return 0;
+ nr_extract_dci_info(mac,dci->dci_format,dci->payloadSize,dci->rnti,(uint64_t *)dci->payloadBits,def_dci_pdu_rel15);
+ return (nr_ue_process_dci(module_id, cc_id, gNB_index, def_dci_pdu_rel15, dci->rnti, dci->dci_format));
}
-int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){
+int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format){
+
+ int bwp_id = 1;
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
@@ -1930,7 +2311,7 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
AssertFatal(mac->DLbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n");
AssertFatal(mac->ULbwp[0]!=NULL,"DLbwp[0] should not be zero here!\n");
- const uint16_t n_RB_DLBWP = NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+ const uint16_t n_RB_DLBWP = (mac->ra_state == WAIT_RAR) ? NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, 275) : NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
const uint16_t n_RB_ULBWP = NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
LOG_D(MAC,"nr_ue_process_dci at MAC layer with dci_format=%d (DL BWP %d, UL BWP %d)\n",dci_format,n_RB_DLBWP,n_RB_ULBWP);
@@ -1954,45 +2335,40 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
* 50 SUL_IND_0_0:
*/
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti;
+ nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu_0_0 = &ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu;
/* IDENTIFIER_DCI_FORMATS */
/* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
- nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
+ nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_0,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val);
/* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(mac,
- ulsch_config_pdu_0_0,NULL,
- dci->time_dom_resource_assignment);
-
+ if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_0,NULL,dci->time_domain_assignment.val) < 0)
+ break;
/* FREQ_HOPPING_FLAG */
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
- ulsch_config_pdu_0_0->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
+ pusch_config_pdu_0_0->frequency_hopping = dci->frequency_hopping_flag.val;
+
/* MCS */
- ulsch_config_pdu_0_0->mcs = dci->mcs;
+ pusch_config_pdu_0_0->mcs_index = dci->mcs;
/* NDI */
- ulsch_config_pdu_0_0->ndi = dci->ndi;
+ pusch_config_pdu_0_0->pusch_data.new_data_indicator = dci->ndi;
/* RV */
- ulsch_config_pdu_0_0->rv = dci->rv;
+ pusch_config_pdu_0_0->pusch_data.rv_index = dci->rv;
/* HARQ_PROCESS_NUMBER */
- ulsch_config_pdu_0_0->harq_process_nbr = dci->harq_process_number;
+ pusch_config_pdu_0_0->pusch_data.harq_process_id = dci->harq_pid;
/* TPC_PUSCH */
// according to TS 38.213 Table Table 7.1.1-1
- if (dci->tpc_pusch == 0) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = -1;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = -4;
+ if (dci->tpc == 0) {
+ pusch_config_pdu_0_0->absolute_delta_PUSCH = -4;
}
- if (dci->tpc_pusch == 1) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 0;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = -1;
+ if (dci->tpc == 1) {
+ pusch_config_pdu_0_0->absolute_delta_PUSCH = -1;
}
- if (dci->tpc_pusch == 2) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 1;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = 1;
+ if (dci->tpc == 2) {
+ pusch_config_pdu_0_0->absolute_delta_PUSCH = 1;
}
- if (dci->tpc_pusch == 3) {
- ulsch_config_pdu_0_0->accumulated_delta_PUSCH = 3;
- ulsch_config_pdu_0_0->absolute_delta_PUSCH = 4;
+ if (dci->tpc == 3) {
+ pusch_config_pdu_0_0->absolute_delta_PUSCH = 4;
}
/* SUL_IND_0_0 */ // To be implemented, FIXME!!!
@@ -2029,49 +2405,45 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
* 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
*/
ul_config->ul_config_list[ul_config->number_pdus].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
- ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.rnti = rnti;
- fapi_nr_ul_config_pusch_pdu_rel15_t *ulsch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].ulsch_config_pdu.ulsch_pdu_rel15;
+ ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu.rnti = rnti;
+ nfapi_nr_ue_pusch_pdu_t *pusch_config_pdu_0_1 = &ul_config->ul_config_list[ul_config->number_pdus].pusch_config_pdu;
/* IDENTIFIER_DCI_FORMATS */
/* CARRIER_IND */
/* SUL_IND_0_1 */
/* BANDWIDTH_PART_IND */
- ulsch_config_pdu_0_1->bandwidth_part_ind = dci->bandwidth_part_ind;
+ //pusch_config_pdu_0_1->bandwidth_part_ind = dci->bwp_indicator.val;
/* FREQ_DOM_RESOURCE_ASSIGNMENT_UL */
- nr_ue_process_dci_freq_dom_resource_assignment(ulsch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->freq_dom_resource_assignment_UL);
+ nr_ue_process_dci_freq_dom_resource_assignment(pusch_config_pdu_0_1,NULL,n_RB_ULBWP,0,dci->frequency_domain_assignment.val);
/* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(mac,ulsch_config_pdu_0_1,NULL,
- dci->time_dom_resource_assignment);
+ if (nr_ue_process_dci_time_dom_resource_assignment(mac,pusch_config_pdu_0_1,NULL,dci->time_domain_assignment.val) < 0)
+ break;
/* FREQ_HOPPING_FLAG */
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.resource_allocation != 0) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.frequency_hopping !=0))
- ulsch_config_pdu_0_1->pusch_freq_hopping = (dci->freq_hopping_flag == 0)? pusch_freq_hopping_disabled:pusch_freq_hopping_enabled;
+ pusch_config_pdu_0_1->frequency_hopping = dci->frequency_hopping_flag.val;
/* MCS */
- ulsch_config_pdu_0_1->mcs = dci->mcs;
+ pusch_config_pdu_0_1->mcs_index = dci->mcs;
/* NDI */
- ulsch_config_pdu_0_1->ndi = dci->ndi;
+ pusch_config_pdu_0_1->pusch_data.new_data_indicator = dci->ndi;
/* RV */
- ulsch_config_pdu_0_1->rv = dci->rv;
+ pusch_config_pdu_0_1->pusch_data.rv_index = dci->rv;
/* HARQ_PROCESS_NUMBER */
- ulsch_config_pdu_0_1->harq_process_nbr = dci->harq_process_number;
+ pusch_config_pdu_0_1->pusch_data.harq_process_id = dci->harq_pid;
/* FIRST_DAI */ //To be implemented, FIXME!!!
/* SECOND_DAI */ //To be implemented, FIXME!!!
/* TPC_PUSCH */
// according to TS 38.213 Table Table 7.1.1-1
- if (dci->tpc_pusch == 0) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = -1;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = -4;
+ if (dci->tpc == 0) {
+ pusch_config_pdu_0_1->absolute_delta_PUSCH = -4;
}
- if (dci->tpc_pusch == 1) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 0;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = -1;
+ if (dci->tpc == 1) {
+ pusch_config_pdu_0_1->absolute_delta_PUSCH = -1;
}
- if (dci->tpc_pusch == 2) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 1;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = 1;
+ if (dci->tpc == 2) {
+ pusch_config_pdu_0_1->absolute_delta_PUSCH = 1;
}
- if (dci->tpc_pusch == 3) {
- ulsch_config_pdu_0_1->accumulated_delta_PUSCH = 3;
- ulsch_config_pdu_0_1->absolute_delta_PUSCH = 4;
+ if (dci->tpc == 3) {
+ pusch_config_pdu_0_1->absolute_delta_PUSCH = 4;
}
/* SRS_RESOURCE_IND */
//FIXME!!
@@ -2088,16 +2460,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 3) ||
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 4))){
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][0];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][1];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][0];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][1];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][2];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][3];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][2];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][3];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][4];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][5];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][4];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][5];
}
}
// Table 7.3.1.1.2-3: transformPrecoder= enabled, or transformPrecoder=disabled and maxRank = 1
@@ -2105,16 +2477,16 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
|| (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
&& (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][6];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][7];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][6];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][7];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_partialAndNonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][8];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][9];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][8];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][9];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][10];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][11];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][10];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][11];
}
}
}
@@ -2123,12 +2495,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled)
&& (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 2)){
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][12];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][13];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][12];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][13];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][14];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][15];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][14];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][15];
}
}
// Table 7.3.1.1.2-5: transformPrecoder= enabled, or transformPrecoder= disabled and maxRank = 1
@@ -2136,12 +2508,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
|| (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled))
&& (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1)){
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_fullyAndPartialAndNonCoherent) {
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][16];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][17];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][16];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][17];
}
if (mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.codebook_subset == codebook_subset_nonCoherent){
- ulsch_config_pdu_0_1->n_layers = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][18];
- ulsch_config_pdu_0_1->tpmi = table_7_3_1_1_2_2_3_4_5[dci->precod_nbr_layers][19];
+ pusch_config_pdu_0_1->nrOfLayers = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][18];
+ pusch_config_pdu_0_1->transform_precoding = table_7_3_1_1_2_2_3_4_5[dci->precoding_information.val][19];
}
}
}
@@ -2151,146 +2523,158 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-6
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = dci->antenna_ports;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = dci->antenna_ports.val; //TBC
}
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-7
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 3)?(dci->antenna_ports-4):(dci->antenna_ports);
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 3)?(dci->antenna_ports.val-4):(dci->antenna_ports.val); //TBC
+ //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1; //FIXME
}
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-8/9/10/11
if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports-2):(dci->antenna_ports);
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?2:1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val-2):(dci->antenna_ports.val); //TBC
}
if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?2:1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?0:2):0;
+ //pusch_config_pdu_0_1->dmrs_ports[1] = (dci->antenna_ports > 1)?(dci->antenna_ports > 2 ?2:3):1;
}
if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = 0;
+ //pusch_config_pdu_0_1->dmrs_ports[1] = 1;
+ //pusch_config_pdu_0_1->dmrs_ports[2] = 2;
}
if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
- ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = 0;
+ //pusch_config_pdu_0_1->dmrs_ports[1] = 1;
+ //pusch_config_pdu_0_1->dmrs_ports[2] = 2;
+ //pusch_config_pdu_0_1->dmrs_ports[3] = 3;
}
}
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-12/13/14/15
if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 6)?2:1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?2:1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; //TBC
+ //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 6)?2:1; //FIXME
}
if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?2:1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 3)?2:1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?2:1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_13[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_13[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 3)?2:1; // FIXME
}
if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_14[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_14[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_14[dci->antenna_ports.val][3];
+ //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
}
if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports][4];
- ulsch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports > 1)?2:1;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_15[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_15[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_15[dci->antenna_ports.val][3];
+ //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_15[dci->antenna_ports.val][4];
+ //pusch_config_pdu_0_1->n_front_load_symb = (dci->antenna_ports.val > 1)?2:1; //FIXME
}
}
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 1)) { // tables 7.3.1.1.2-16/17/18/19
if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 1)?((dci->antenna_ports > 5)?3:2):1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = (dci->antenna_ports > 1)?(dci->antenna_ports > 5 ?(dci->antenna_ports-6):(dci->antenna_ports-2)):dci->antenna_ports;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 1)?((dci->antenna_ports.val > 5)?3:2):1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = (dci->antenna_ports.val > 1)?(dci->antenna_ports.val > 5 ?(dci->antenna_ports.val-6):(dci->antenna_ports.val-2)):dci->antenna_ports.val; //TBC
}
if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?((dci->antenna_ports > 2)?3:2):1;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports][2];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?((dci->antenna_ports.val > 2)?3:2):1; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_17[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_17[dci->antenna_ports.val][2];
}
if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = (dci->antenna_ports > 0)?3:2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports][3];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = (dci->antenna_ports.val > 0)?3:2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_18[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_18[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_18[dci->antenna_ports.val][3];
}
if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = dci->antenna_ports + 2;
- ulsch_config_pdu_0_1->dmrs_ports[0] = 0;
- ulsch_config_pdu_0_1->dmrs_ports[1] = 1;
- ulsch_config_pdu_0_1->dmrs_ports[2] = 2;
- ulsch_config_pdu_0_1->dmrs_ports[3] = 3;
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = dci->antenna_ports.val + 2; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = 0;
+ //pusch_config_pdu_0_1->dmrs_ports[1] = 1;
+ //pusch_config_pdu_0_1->dmrs_ports[2] = 2;
+ //pusch_config_pdu_0_1->dmrs_ports[3] = 3;
}
}
if ((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.dmrs_type == 2) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.max_length == 2)) { // tables 7.3.1.1.2-20/21/22/23
if (rank == 1){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_20[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_20[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports][2];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_20[dci->antenna_ports.val][0]; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = table_7_3_1_1_2_20[dci->antenna_ports.val][1]; //TBC
+ //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_20[dci->antenna_ports.val][2]; //FIXME
}
if (rank == 2){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_21[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports][3];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_21[dci->antenna_ports.val][0]; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_21[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_21[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_21[dci->antenna_ports.val][3]; //FIXME
}
if (rank == 3){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_22[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports][4];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_22[dci->antenna_ports.val][0]; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_22[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_22[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_22[dci->antenna_ports.val][3];
+ //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_22[dci->antenna_ports.val][4]; //FIXME
}
if (rank == 4){
- ulsch_config_pdu_0_1->n_dmrs_cdm_groups = table_7_3_1_1_2_23[dci->antenna_ports][0];
- ulsch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports][1];
- ulsch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports][2];
- ulsch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports][3];
- ulsch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports][4];
- ulsch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports][5];
+ pusch_config_pdu_0_1->num_dmrs_cdm_grps_no_data = table_7_3_1_1_2_23[dci->antenna_ports.val][0]; //TBC
+ pusch_config_pdu_0_1->dmrs_ports = 0; //FIXME
+ //pusch_config_pdu_0_1->dmrs_ports[0] = table_7_3_1_1_2_23[dci->antenna_ports.val][1];
+ //pusch_config_pdu_0_1->dmrs_ports[1] = table_7_3_1_1_2_23[dci->antenna_ports.val][2];
+ //pusch_config_pdu_0_1->dmrs_ports[2] = table_7_3_1_1_2_23[dci->antenna_ports.val][3];
+ //pusch_config_pdu_0_1->dmrs_ports[3] = table_7_3_1_1_2_23[dci->antenna_ports.val][4];
+ //pusch_config_pdu_0_1->n_front_load_symb = table_7_3_1_1_2_23[dci->antenna_ports.val][5]; //FIXME
}
}
/* SRS_REQUEST */
// if SUL is supported in the cell, there is an additional bit in thsi field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
- ulsch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
+ //pusch_config_pdu_0_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212 //FIXME
/* CSI_REQUEST */
- ulsch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request;
+ //pusch_config_pdu_0_1->csi_reportTriggerSize = dci->csi_request.val; //FIXME
/* CBGTI */
- ulsch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti;
+ //pusch_config_pdu_0_1->maxCodeBlockGroupsPerTransportBlock = dci->cbgti.val; //FIXME
/* PTRS_DMRS */
if (((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_disabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.dmrs_ul_for_pusch_mapping_type_a.ptrs_uplink_config == 0)) ||
((mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.transform_precoder == transform_precoder_enabled) &&
(mac->phy_config.config_req.ul_bwp_dedicated.pusch_config_dedicated.max_rank == 1))){
} else {
- ulsch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs;
+ //pusch_config_pdu_0_1->ptrs_dmrs_association_port = dci->ptrs_dmrs_association.val; //FIXME
}
/* BETA_OFFSET_IND */
// Table 9.3-3 in [5, TS 38.213]
- ulsch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_ind;
+ //pusch_config_pdu_0_1->beta_offset_ind = dci->beta_offset_indicator.val; //FIXME
/* DMRS_SEQ_INI */
// FIXME!!
/* UL_SCH_IND */
@@ -2360,18 +2744,22 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
dlsch_config_pdu_1_0->SubcarrierSpacing = mac->DLbwp[0]->bwp_Common->genericParameters.subcarrierSpacing;
/* IDENTIFIER_DCI_FORMATS */
/* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
- nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
+ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_0,0,n_RB_DLBWP,dci->frequency_domain_assignment.val);
/* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0,
- dci->time_dom_resource_assignment);
-
+ if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_0,dci->time_domain_assignment.val) < 0)
+ break;
/* dmrs symbol positions*/
dlsch_config_pdu_1_0->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config,
mac->scc->dmrs_TypeA_Position,
dlsch_config_pdu_1_0->number_symbols);
- dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 1 : 2;
+ dlsch_config_pdu_1_0->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
+ /* number of DM-RS CDM groups without data according to subclause 5.1.6.2 of 3GPP TS 38.214 version 15.9.0 Release 15 */
+ if (dlsch_config_pdu_1_0->number_symbols == 2)
+ dlsch_config_pdu_1_0->n_dmrs_cdm_groups = 1;
+ else
+ dlsch_config_pdu_1_0->n_dmrs_cdm_groups = 2;
/* VRB_TO_PRB_MAPPING */
- dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
+ dlsch_config_pdu_1_0->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
/* MCS */
dlsch_config_pdu_1_0->mcs = dci->mcs;
/* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
@@ -2379,9 +2767,9 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
/* RV (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
dlsch_config_pdu_1_0->rv = dci->rv;
/* HARQ_PROCESS_NUMBER (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_process_number;
+ dlsch_config_pdu_1_0->harq_process_nbr = dci->harq_pid;
/* DAI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
- dlsch_config_pdu_1_0->dai = dci ->dai;
+ dlsch_config_pdu_1_0->dai = dci->dai[0].val;
/* TB_SCALING (only if CRC scrambled by P-RNTI or RA-RNTI) */
// according to TS 38.214 Table 5.1.3.2-3
if (dci->tb_scaling == 0) dlsch_config_pdu_1_0->scaling_factor_S = 1;
@@ -2390,32 +2778,32 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
if (dci->tb_scaling == 3) dlsch_config_pdu_1_0->scaling_factor_S = 0; // value not defined in table
/* TPC_PUCCH (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
// according to TS 38.213 Table 7.2.1-1
- if (dci->tpc_pucch == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1;
- if (dci->tpc_pucch == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0;
- if (dci->tpc_pucch == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1;
- if (dci->tpc_pucch == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3;
+ if (dci->tpc == 0) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = -1;
+ if (dci->tpc == 1) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 0;
+ if (dci->tpc == 2) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 1;
+ if (dci->tpc == 3) dlsch_config_pdu_1_0->accumulated_delta_PUCCH = 3;
/* PUCCH_RESOURCE_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
- //if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
- //if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
- //if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
- dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_ind;
+ //if (dci->pucch_resource_indicator == 0) dlsch_config_pdu_1_0->pucch_resource_id = 1; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
+ //if (dci->pucch_resource_indicator == 1) dlsch_config_pdu_1_0->pucch_resource_id = 2; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 2) dlsch_config_pdu_1_0->pucch_resource_id = 3; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 3) dlsch_config_pdu_1_0->pucch_resource_id = 4; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 4) dlsch_config_pdu_1_0->pucch_resource_id = 5; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 5) dlsch_config_pdu_1_0->pucch_resource_id = 6; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 6) dlsch_config_pdu_1_0->pucch_resource_id = 7; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
+ //if (dci->pucch_resource_indicator == 7) dlsch_config_pdu_1_0->pucch_resource_id = 8; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
+ dlsch_config_pdu_1_0->pucch_resource_id = dci->pucch_resource_indicator;
/* PDSCH_TO_HARQ_FEEDBACK_TIME_IND (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI)*/
- dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_time_ind;
+ dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind = dci->pdsch_to_harq_feedback_timing_indicator.val;
- LOG_D(MAC,"(nr_ue_procedures.c) rnti=%d dl_config->number_pdus=%d\n",
+ LOG_D(MAC,"(nr_ue_procedures.c) rnti = %x dl_config->number_pdus = %d\n",
dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti,
dl_config->number_pdus);
LOG_D(MAC,"(nr_ue_procedures.c) frequency_domain_resource_assignment=%d \t number_rbs=%d \t start_rb=%d\n",
- dci->freq_dom_resource_assignment_DL,
+ dci->frequency_domain_assignment.val,
dlsch_config_pdu_1_0->number_rbs,
dlsch_config_pdu_1_0->start_rb);
LOG_D(MAC,"(nr_ue_procedures.c) time_domain_resource_assignment=%d \t number_symbols=%d \t start_symbol=%d\n",
- dci->time_dom_resource_assignment,
+ dci->time_domain_assignment.val,
dlsch_config_pdu_1_0->number_symbols,
dlsch_config_pdu_1_0->start_symbol);
LOG_D(MAC,"(nr_ue_procedures.c) vrb_to_prb_mapping=%d \n>>> mcs=%d\n>>> ndi=%d\n>>> rv=%d\n>>> harq_process_nbr=%d\n>>> dai=%d\n>>> scaling_factor_S=%f\n>>> tpc_pucch=%d\n>>> pucch_res_ind=%d\n>>> pdsch_to_harq_feedback_time_ind=%d\n",
@@ -2430,7 +2818,12 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
dlsch_config_pdu_1_0->pucch_resource_id,
dlsch_config_pdu_1_0->pdsch_to_harq_feedback_time_ind);
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
+ if (mac->RA_window_cnt >= 0 && rnti == mac->ra_rnti){
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH;
+ } else {
+ dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
+ }
+
// dl_config->dl_config_list[dl_config->number_pdus].dci_config_pdu.dci_config_rel15.N_RB_BWP = n_RB_DLBWP;
LOG_D(MAC,"(nr_ue_procedures.c) pdu_type=%d\n\n",dl_config->dl_config_list[dl_config->number_pdus].pdu_type);
@@ -2476,145 +2869,146 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr
/* BANDWIDTH_PART_IND */
// dlsch_config_pdu_1_1->bandwidth_part_ind = dci->bandwidth_part_ind;
/* FREQ_DOM_RESOURCE_ASSIGNMENT_DL */
- nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->freq_dom_resource_assignment_DL);
+ nr_ue_process_dci_freq_dom_resource_assignment(NULL,dlsch_config_pdu_1_1,0,n_RB_DLBWP,dci->frequency_domain_assignment.val);
/* TIME_DOM_RESOURCE_ASSIGNMENT */
- nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1,
- dci->time_dom_resource_assignment);
+ if (nr_ue_process_dci_time_dom_resource_assignment(mac,NULL,dlsch_config_pdu_1_1,dci->time_domain_assignment.val) < 0)
+ break;
+ /* dmrs symbol positions*/
+ dlsch_config_pdu_1_1->dlDmrsSymbPos = fill_dmrs_mask(pdsch_config,
+ mac->scc->dmrs_TypeA_Position,
+ dlsch_config_pdu_1_1->number_symbols);
+ dlsch_config_pdu_1_1->dmrsConfigType = mac->DLbwp[0]->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
+ /* TODO: fix number of DM-RS CDM groups without data according to subclause 5.1.6.2 of 3GPP TS 38.214,
+ using tables 7.3.1.2.2-1, 7.3.1.2.2-2, 7.3.1.2.2-3, 7.3.1.2.2-4 of 3GPP TS 38.212 */
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = 1;
/* VRB_TO_PRB_MAPPING */
if (mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.resource_allocation != 0)
- dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
+ dlsch_config_pdu_1_1->vrb_to_prb_mapping = (dci->vrb_to_prb_mapping.val == 0) ? vrb_to_prb_mapping_non_interleaved:vrb_to_prb_mapping_interleaved;
/* PRB_BUNDLING_SIZE_IND */
- dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_ind;
+ dlsch_config_pdu_1_1->prb_bundling_size_ind = dci->prb_bundling_size_indicator.val;
/* RATE_MATCHING_IND */
- dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_ind;
+ dlsch_config_pdu_1_1->rate_matching_ind = dci->rate_matching_indicator.val;
/* ZP_CSI_RS_TRIGGER */
- dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger;
+ dlsch_config_pdu_1_1->zp_csi_rs_trigger = dci->zp_csi_rs_trigger.val;
/* MCS (for transport block 1)*/
- dlsch_config_pdu_1_1->mcs = dci->tb1_mcs;
+ dlsch_config_pdu_1_1->mcs = dci->mcs;
/* NDI (for transport block 1)*/
- dlsch_config_pdu_1_1->ndi = dci->tb1_ndi;
+ dlsch_config_pdu_1_1->ndi = dci->ndi;
/* RV (for transport block 1)*/
- dlsch_config_pdu_1_1->rv = dci->tb1_rv;
+ dlsch_config_pdu_1_1->rv = dci->rv;
/* MCS (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_mcs = dci->tb2_mcs;
+ dlsch_config_pdu_1_1->tb2_mcs = dci->mcs2.val;
/* NDI (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_ndi = dci->tb2_ndi;
+ dlsch_config_pdu_1_1->tb2_ndi = dci->ndi2.val;
/* RV (for transport block 2)*/
- dlsch_config_pdu_1_1->tb2_rv = dci->tb2_rv;
+ dlsch_config_pdu_1_1->tb2_rv = dci->rv2.val;
/* HARQ_PROCESS_NUMBER */
- dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_process_number;
+ dlsch_config_pdu_1_1->harq_process_nbr = dci->harq_pid;
/* DAI */
- dlsch_config_pdu_1_1->dai = dci ->dai;
+ dlsch_config_pdu_1_1->dai = dci->dai[0].val;
/* TPC_PUCCH */
// according to TS 38.213 Table 7.2.1-1
- if (dci->tpc_pucch == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1;
- if (dci->tpc_pucch == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0;
- if (dci->tpc_pucch == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1;
- if (dci->tpc_pucch == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3;
+ if (dci->tpc == 0) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = -1;
+ if (dci->tpc == 1) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 0;
+ if (dci->tpc == 2) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 1;
+ if (dci->tpc == 3) dlsch_config_pdu_1_1->accumulated_delta_PUCCH = 3;
/* PUCCH_RESOURCE_IND */
- if (dci->pucch_resource_ind == 0) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 1st value of resourceList FIXME!!!
- if (dci->pucch_resource_ind == 1) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 2nd value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 2) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 3rd value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 3) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 4th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 4) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 5th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 5) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 6th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 6) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 7th value of resourceList FIXME!!
- if (dci->pucch_resource_ind == 7) dlsch_config_pdu_1_1->pucch_resource_id = 0; //pucch-ResourceId obtained from the 8th value of resourceList FIXME!!
+ dlsch_config_pdu_1_1->pucch_resource_id = dci->pucch_resource_indicator;
/* PDSCH_TO_HARQ_FEEDBACK_TIME_IND */
// according to TS 38.213 Table 9.2.3-1
- dlsch_config_pdu_1_1-> pdsch_to_harq_feedback_time_ind = mac->phy_config.config_req.ul_bwp_dedicated.pucch_config_dedicated.dl_data_to_ul_ack[dci->pdsch_to_harq_feedback_time_ind];
+ dlsch_config_pdu_1_1->pdsch_to_harq_feedback_time_ind = mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[dci->pdsch_to_harq_feedback_timing_indicator.val][0];
/* ANTENNA_PORTS */
uint8_t n_codewords = 1; // FIXME!!!
if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
// Table 7.3.1.2.2-1: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=1
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_1[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_1[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_1[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_1[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_1[dci->antenna_ports.val][4];
}
if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 1) &&
(mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
// Table 7.3.1.2.2-2: Antenna port(s) (1000 + DMRS port), dmrs-Type=1, maxLength=2
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports][5];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][4];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_oneCodeword[dci->antenna_ports.val][5];
}
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][6];
- dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][7];
- dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][8];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports][9];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][6];
+ dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][7];
+ dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][8];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_2_twoCodeword[dci->antenna_ports.val][9];
}
}
if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
(mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 1)){
// Table 7.3.1.2.2-3: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=1
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports][4];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_oneCodeword[dci->antenna_ports.val][4];
}
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports][6];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_3_twoCodeword[dci->antenna_ports.val][6];
}
}
if ((mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.dmrs_type == 2) &&
(mac->phy_config.config_req.dl_bwp_dedicated.pdsch_config_dedicated.dmrs_dl_for_pdsch_mapping_type_a.max_length == 2)){
// Table 7.3.1.2.2-4: Antenna port(s) (1000 + DMRS port), dmrs-Type=2, maxLength=2
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports][5];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][4];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_oneCodeword[dci->antenna_ports.val][5];
}
if (n_codewords == 1) {
- dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][0];
- dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][1];
- dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][2];
- dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][3];
- dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][4];
- dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][5];
- dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][6];
- dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][7];
- dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][8];
- dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports][9];
+ dlsch_config_pdu_1_1->n_dmrs_cdm_groups = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][0];
+ dlsch_config_pdu_1_1->dmrs_ports[0] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][1];
+ dlsch_config_pdu_1_1->dmrs_ports[1] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][2];
+ dlsch_config_pdu_1_1->dmrs_ports[2] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][3];
+ dlsch_config_pdu_1_1->dmrs_ports[3] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][4];
+ dlsch_config_pdu_1_1->dmrs_ports[4] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][5];
+ dlsch_config_pdu_1_1->dmrs_ports[5] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][6];
+ dlsch_config_pdu_1_1->dmrs_ports[6] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][7];
+ dlsch_config_pdu_1_1->dmrs_ports[7] = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][8];
+ dlsch_config_pdu_1_1->n_front_load_symb = table_7_3_2_3_3_4_twoCodeword[dci->antenna_ports.val][9];
}
}
/* TCI */
if (mac->dl_config_request.dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.tci_present_in_dci == 1){
// 0 bit if higher layer parameter tci-PresentInDCI is not enabled
// otherwise 3 bits as defined in Subclause 5.1.5 of [6, TS38.214]
- dlsch_config_pdu_1_1->tci_state = dci->tci;
+ dlsch_config_pdu_1_1->tci_state = dci->transmission_configuration_indication.val;
}
/* SRS_REQUEST */
// if SUL is supported in the cell, there is an additional bit in this field and the value of this bit represents table 7.1.1.1-1 TS 38.212 FIXME!!!
- dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
+ dlsch_config_pdu_1_1->srs_config.aperiodicSRS_ResourceTrigger = (dci->srs_request.val & 0x11); // as per Table 7.3.1.1.2-24 TS 38.212
/* CBGTI */
- dlsch_config_pdu_1_1->cbgti = dci->cbgti;
+ dlsch_config_pdu_1_1->cbgti = dci->cbgti.val;
/* CBGFI */
- dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi;
+ dlsch_config_pdu_1_1->codeBlockGroupFlushIndicator = dci->cbgfi.val;
/* DMRS_SEQ_INI */
//FIXME!!!
@@ -2677,7 +3071,6 @@ void nr_ue_send_sdu(module_id_t module_idP,
LOG_D(MAC, "Handling PDU frame %d slot %d\n", frameP, slotP);
uint8_t * pduP = pdu;
- NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SEND_SDU, VCD_FUNCTION_IN);
@@ -2714,7 +3107,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
uint8_t dci_size,
uint16_t rnti,
uint64_t *dci_pdu,
- nr_dci_pdu_rel15_t *dci_pdu_rel15) {
+ dci_pdu_rel15_t *dci_pdu_rel15) {
int rnti_type=-1;
if (rnti == mac->ra_rnti) rnti_type = NR_RNTI_RA;
@@ -2726,10 +3119,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
AssertFatal(rnti_type!=-1,"no identified/handled rnti\n");
AssertFatal(mac->DLbwp[0] != NULL, "DLbwp[0] shouldn't be null here!\n");
AssertFatal(mac->ULbwp[0] != NULL, "ULbwp[0] shouldn't be null here!\n");
- int N_RB = (mac->scd != NULL) ?
+ int N_RB = (mac->scg != NULL) ?
NRRIV2BW(mac->DLbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) :
NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth,275);
- int N_RB_UL = (mac->scd != NULL) ?
+ int N_RB_UL = (mac->scg != NULL) ?
NRRIV2BW(mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275) :
NRRIV2BW(mac->scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275);
@@ -2740,25 +3133,26 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
case NR_DL_DCI_FORMAT_1_0:
switch(rnti_type) {
case NR_RNTI_RA:
+ N_RB = NRRIV2BW(mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, 275); // TBR hotfix
// Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize;
- dci_pdu_rel15->freq_dom_resource_assignment_DL = *dci_pdu>>(dci_size-pos)&((1<<fsize)-1);
+ dci_pdu_rel15->frequency_domain_assignment.val = *dci_pdu>>(dci_size-pos)&((1<<fsize)-1);
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,N_RB,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
#endif
// Time domain assignment
pos+=4;
- dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu >> (dci_size-pos))&0xf;
+ dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu >> (dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"time-domain assignment %d (4 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
#endif
// VRB to PRB mapping
pos++;
- dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&0x1;
+ dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&0x1;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
#endif
// MCS
pos+=5;
@@ -2773,28 +3167,28 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
#endif
break;
-
+
case NR_RNTI_C:
// indicating a DL DCI format 1bit
pos++;
- dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->identifier_dci_formats,1,N_RB,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu);
#endif
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
- dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+ dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->freq_dom_resource_assignment_DL,fsize,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
#endif
uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
- if (!((dci_pdu_rel15->freq_dom_resource_assignment_DL>>i)&1)) {
+ if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
is_ra = 0;
break;
}
@@ -2806,7 +3200,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
// UL/SUL indicator 1 bit
pos++;
- dci_pdu_rel15->sul_ind_0_1 = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->ul_sul_indicator.val = (*dci_pdu>>(dci_size-pos))&1;
// SS/PBCH index 6 bits
pos+=6;
@@ -2822,16 +3216,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
// Time domain assignment 4bit
pos+=4;
- dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_dom_resource_assignment,4,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
#endif
// VRB to PRB mapping 1bit
pos++;
- dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
#endif
// MCS 5bit //bit over 32, so dci_pdu ++
@@ -2857,37 +3251,37 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
// HARQ process number 4bit
pos+=4;
- dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_process_number,4,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu);
#endif
// Downlink assignment index 2bit
pos+=2;
- dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3;
+ dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
#endif
// TPC command for scheduled PUCCH 2bit
pos+=2;
- dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3;
+ dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc_pucch,2,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu);
#endif
// PUCCH resource indicator 3bit
pos+=3;
- dci_pdu_rel15->pucch_resource_ind = (*dci_pdu>>(dci_size-pos))&0x7;
+ dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x7;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_ind,3,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu);
#endif
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
- dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&0x7;
+ dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&0x7;
#ifdef DEBUG_EXTRACT_DCI
- LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_time_ind,3,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
#endif
} //end else
@@ -2909,7 +3303,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -2931,7 +3325,7 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -2944,16 +3338,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
case NR_RNTI_TC:
// indicating a DL DCI format 1bit
pos++;
- dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
- dci_pdu_rel15->freq_dom_resource_assignment_DL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+ dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment 4 bit
pos+=4;
- dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
// VRB to PRB mapping 1 bit
- dci_pdu_rel15->vrb_to_prb_mapping = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&1;
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
@@ -2964,16 +3358,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos+=4;
- dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// Downlink assignment index – 2 bits
pos+=2;
- dci_pdu_rel15->dai = (*dci_pdu>>(dci_size-pos))&3;
+ dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&3;
// TPC command for scheduled PUCCH – 2 bits
pos+=2;
- dci_pdu_rel15->tpc_pucch = (*dci_pdu>>(dci_size-pos))&3;
+ dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
pos+=3;
- dci_pdu_rel15->pdsch_to_harq_feedback_time_ind = (*dci_pdu>>(dci_size-pos))&7;
+ dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&7;
break;
}
@@ -2984,17 +3378,17 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
{
case NR_RNTI_C:
// indicating a DL DCI format 1bit
- dci_pdu_rel15->identifier_dci_formats = (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
pos+=fsize;
- dci_pdu_rel15->freq_dom_resource_assignment_UL = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
+ dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<fsize)-1);
// Time domain assignment 4bit
pos+=4;
- dci_pdu_rel15->time_dom_resource_assignment = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&0xf;
// Frequency hopping flag – 1 bit
pos++;
- dci_pdu_rel15->freq_hopping_flag= (*dci_pdu>>(dci_size-pos))&1;
+ dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos+=5;
dci_pdu_rel15->mcs= (*dci_pdu>>(dci_size-pos))&0x1f;
@@ -3006,10 +3400,10 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
dci_pdu_rel15->rv= (*dci_pdu>>(dci_size-pos))&3;
// HARQ process number 4bit
pos+=4;
- dci_pdu_rel15->harq_process_number = (*dci_pdu>>(dci_size-pos))&0xf;
+ dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
// TPC command for scheduled PUSCH – 2 bits
pos+=2;
- dci_pdu_rel15->tpc_pusch = (*dci_pdu>>(dci_size-pos))&3;
+ dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&3;
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
@@ -3056,6 +3450,90 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
}
break;
+
+ case NR_DL_DCI_FORMAT_1_1:
+ // Format indicator
+ pos=1;
+ dci_pdu_rel15->format_indicator = (*dci_pdu>>(dci_size-pos))&1;
+ // Carrier indicator
+ pos+=dci_pdu_rel15->carrier_indicator.nbits;
+ dci_pdu_rel15->carrier_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1);
+ // BWP Indicator
+ pos+=dci_pdu_rel15->bwp_indicator.nbits;
+ dci_pdu_rel15->bwp_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1);
+ // Frequency domain resource assignment
+ pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
+ dci_pdu_rel15->frequency_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1);
+ // Time domain resource assignment
+ pos+=dci_pdu_rel15->time_domain_assignment.nbits;
+ dci_pdu_rel15->time_domain_assignment.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1);
+ // VRB-to-PRB mapping
+ pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
+ dci_pdu_rel15->vrb_to_prb_mapping.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1);
+ // PRB bundling size indicator
+ pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
+ dci_pdu_rel15->prb_bundling_size_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1);
+ // Rate matching indicator
+ pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
+ dci_pdu_rel15->rate_matching_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1);
+ // ZP CSI-RS trigger
+ pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
+ dci_pdu_rel15->zp_csi_rs_trigger.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1);
+ //TB1
+ // MCS 5bit
+ pos+=5;
+ dci_pdu_rel15->mcs = (*dci_pdu>>(dci_size-pos))&0x1f;
+ // New data indicator 1bit
+ pos+=1;
+ dci_pdu_rel15->ndi = (*dci_pdu>>(dci_size-pos))&0x1;
+ // Redundancy version 2bit
+ pos+=2;
+ dci_pdu_rel15->rv = (*dci_pdu>>(dci_size-pos))&0x3;
+ //TB2
+ // MCS 5bit
+ pos+=dci_pdu_rel15->mcs2.nbits;
+ dci_pdu_rel15->mcs2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->mcs2.nbits)-1);
+ // New data indicator 1bit
+ pos+=dci_pdu_rel15->ndi2.nbits;
+ dci_pdu_rel15->ndi2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->ndi2.nbits)-1);
+ // Redundancy version 2bit
+ pos+=dci_pdu_rel15->rv2.nbits;
+ dci_pdu_rel15->rv2.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->rv2.nbits)-1);
+ // HARQ process number 4bit
+ pos+=4;
+ dci_pdu_rel15->harq_pid = (*dci_pdu>>(dci_size-pos))&0xf;
+ // Downlink assignment index
+ pos+=dci_pdu_rel15->dai[0].nbits;
+ dci_pdu_rel15->dai[0].val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->dai[0].nbits)-1);
+ // TPC command for scheduled PUCCH 2bit
+ pos+=2;
+ dci_pdu_rel15->tpc = (*dci_pdu>>(dci_size-pos))&0x3;
+ // PUCCH resource indicator 3bit
+ pos+=3;
+ dci_pdu_rel15->pucch_resource_indicator = (*dci_pdu>>(dci_size-pos))&0x3;
+ // PDSCH-to-HARQ_feedback timing indicator
+ pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
+ dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1);
+ // Antenna ports
+ pos+=dci_pdu_rel15->antenna_ports.nbits;
+ dci_pdu_rel15->antenna_ports.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->antenna_ports.nbits)-1);
+ // TCI
+ pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
+ dci_pdu_rel15->transmission_configuration_indication.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1);
+ // SRS request
+ pos+=dci_pdu_rel15->srs_request.nbits;
+ dci_pdu_rel15->srs_request.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->srs_request.nbits)-1);
+ // CBG transmission information
+ pos+=dci_pdu_rel15->cbgti.nbits;
+ dci_pdu_rel15->cbgti.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgti.nbits)-1);
+ // CBG flushing out information
+ pos+=dci_pdu_rel15->cbgfi.nbits;
+ dci_pdu_rel15->cbgfi.val = (*dci_pdu>>(dci_size-pos))&((1<<dci_pdu_rel15->cbgfi.nbits)-1);
+ // DMRS sequence init
+ pos+=1;
+ dci_pdu_rel15->dmrs_sequence_initialization.val = (*dci_pdu>>(dci_size-pos))&0x1;
+ break;
+
}
}
@@ -3074,6 +3552,7 @@ void nr_ue_process_mac_pdu(module_id_t module_idP,
uint8_t *pdu_ptr = pduP, rx_lcid, done = 0;
int pdu_len = mac_pdu_len;
uint16_t mac_ce_len, mac_subheader_len, mac_sdu_len;
+ NR_UE_MAC_INST_t *mac = get_mac_inst(module_idP);
//NR_UE_MAC_INST_t *UE_mac_inst = get_mac_inst(module_idP);
//uint8_t scs = UE_mac_inst->mib->subCarrierSpacingCommon;
@@ -3234,8 +3713,34 @@ void nr_ue_process_mac_pdu(module_id_t module_idP,
break;
case DL_SCH_LCID_CON_RES_ID:
// 38.321 Ch6.1.3.3
+ // WIP todo: handle CCCH_pdu
mac_ce_len = 6;
-
+
+ LOG_I(MAC, "[UE %d][RAPROC] Frame %d : received contention resolution msg: %x.%x.%x.%x.%x.%x, Terminating RA procedure\n", module_idP, frameP, pdu_ptr[0], pdu_ptr[1], pdu_ptr[2], pdu_ptr[3], pdu_ptr[4], pdu_ptr[5]);
+
+ if (mac->RA_active == 1) {
+ LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Clearing RA_active flag\n", module_idP, frameP);
+ mac->RA_active = 0;
+ // // check if RA procedure has finished completely (no contention)
+ // tx_sdu = &mac->CCCH_pdu.payload[3];
+ // //Note: 3 assumes sizeof(SCH_SUBHEADER_SHORT) + PADDING CE, which is when UL-Grant has TBS >= 9 (64 bits)
+ // // (other possibility is 1 for TBS=7 (SCH_SUBHEADER_FIXED), or 2 for TBS=8 (SCH_SUBHEADER_FIXED+PADDING or // SCH_SUBHEADER_SHORT)
+ // for (i = 0; i < 6; i++)
+ // if (tx_sdu[i] != payload_ptr[i]) {
+ // LOG_E(MAC, "[UE %d][RAPROC] Contention detected, RA failed\n", module_idP);
+ // nr_ra_failed(module_idP, CC_id, eNB_index);
+ // mac->RA_contention_resolution_timer_active = 0;
+ // return;
+ // }
+ LOG_I(MAC, "[UE %d][RAPROC] Frame %d : Cleared contention resolution timer. Set C-RNTI to TC-RNTI\n",
+ module_idP,
+ frameP);
+ mac->RA_contention_resolution_timer_active = 0;
+ nr_ra_succeeded(module_idP, CC_id, gNB_index);
+ mac->crnti = mac->t_crnti;
+ mac->t_crnti = 0;
+ mac->ra_state = RA_SUCCEEDED;
+ }
break;
case DL_SCH_LCID_PADDING:
done = 1;
@@ -3301,71 +3806,181 @@ void nr_ue_process_mac_pdu(module_id_t module_idP,
}
}
-//---------------------------------------------------------------------------------
-
-
-uint16_t
-nr_generate_ulsch_pdu(uint8_t *mac_pdu,
- uint8_t *sdus_payload,
- uint8_t num_sdus,
- uint16_t *sdu_lengths,
- uint8_t *sdu_lcids,
- uint16_t *crnti,
- uint16_t buflen) {
-
- NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu;
- unsigned char * ulsch_buffer_ptr = sdus_payload;
- uint8_t last_size=0;
- uint16_t sdu_length_total=0;
- int i;
- int offset=0;
-
- // 2) Generation of ULSCH MAC SDU subheaders
- for (i = 0; i < num_sdus; i++) {
- LOG_D(MAC, "[gNB] Generate ULSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);
-
- if (sdu_lengths[i] < 128) {
- ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
- ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
- ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i];
- ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i];
- last_size = 2;
- } else {
- ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0;
- ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1;
- ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i];
- ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f;
- ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff;
- last_size = 3;
- }
-
- mac_pdu_ptr += last_size;
-
- // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
- memcpy((void *) mac_pdu_ptr, (void *) ulsch_buffer_ptr, sdu_lengths[i]);
- ulsch_buffer_ptr+= sdu_lengths[i];
- sdu_length_total+= sdu_lengths[i];
- mac_pdu_ptr += sdu_lengths[i];
- }
+////////////////////////////////////////////////////////
+/////* ULSCH MAC PDU generation (6.1.2 TS 38.321) */////
+////////////////////////////////////////////////////////
+
+uint16_t nr_generate_ulsch_pdu(uint8_t *sdus_payload,
+ uint8_t *pdu,
+ uint8_t num_sdus,
+ uint16_t *sdu_lengths,
+ uint8_t *sdu_lcids,
+ uint8_t power_headroom,
+ uint16_t crnti,
+ uint16_t truncated_bsr,
+ uint16_t short_bsr,
+ uint16_t long_bsr,
+ unsigned short post_padding,
+ uint16_t buflen) {
+
+ NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) pdu;
+ unsigned char last_size = 0, i, mac_header_control_elements[16], *ce_ptr, bsr = 0;
+ int mac_ce_size;
+ uint16_t offset = 0;
+
+ LOG_D(MAC, "[UE] Generating ULSCH PDU : num_sdus %d\n", num_sdus);
- offset = ((unsigned char *) mac_pdu_ptr - mac_pdu);
+ #ifdef DEBUG_HEADER_PARSING
- // 4) Compute final offset for padding
- uint16_t padding_bytes = buflen - offset;
- LOG_D(MAC, "Number of padding bytes: %d \n", padding_bytes);
- if (padding_bytes > 0) {
- ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
- ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING;
- mac_pdu_ptr++;
+ for (i = 0; i < num_sdus; i++)
+ LOG_D(MAC, "[UE] MAC subPDU %d (lcid %d length %d bytes \n", i, sdu_lcids[i], sdu_lengths[i]);
- } else {
- // no MAC subPDU with padding
- }
+ #endif
+
+ // Generating UL MAC subPDUs including MAC SDU and subheader
+
+ for (i = 0; i < num_sdus; i++) {
+ LOG_D(MAC, "[UE] Generating UL MAC subPDUs for SDU with lenght %d ( num_sdus %d )\n", sdu_lengths[i], num_sdus);
+
+ if (sdu_lcids[i] != UL_SCH_LCID_CCCH){
+ if (sdu_lengths[i] < 128) {
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = sdu_lcids[i];
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = (unsigned char) sdu_lengths[i];
+ last_size = 2;
+ } else {
+ ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->F = 1;
+ ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->LCID = sdu_lcids[i];
+ ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L1 = ((unsigned short) sdu_lengths[i] >> 8) & 0x7f;
+ ((NR_MAC_SUBHEADER_LONG *) mac_pdu_ptr)->L2 = (unsigned short) sdu_lengths[i] & 0xff;
+ last_size = 3;
+ }
+ } else { // UL CCCH SDU
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = sdu_lcids[i];
+ }
+
+ mac_pdu_ptr += last_size;
+
+ // cycle through SDUs, compute each relevant and place ulsch_buffer in
+ memcpy((void *) mac_pdu_ptr, (void *) sdus_payload, sdu_lengths[i]);
+ sdus_payload += sdu_lengths[i];
+ mac_pdu_ptr += sdu_lengths[i];
+ }
+
+ // Generating UL MAC subPDUs including MAC CEs (MAC CE and subheader)
+
+ ce_ptr = &mac_header_control_elements[0];
+
+ if (power_headroom) {
+ // MAC CE fixed subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = UL_SCH_LCID_SINGLE_ENTRY_PHR;
+ mac_pdu_ptr++;
+
+ // PHR MAC CE (1 octet)
+ ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PH = power_headroom;
+ ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R1 = 0;
+ ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->PCMAX = 0; // todo
+ ((NR_SINGLE_ENTRY_PHR_MAC_CE *) ce_ptr)->R2 = 0;
+
+ mac_ce_size = sizeof(NR_SINGLE_ENTRY_PHR_MAC_CE);
+
+ // Copying bytes for PHR MAC CEs to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
+ ce_ptr += mac_ce_size;
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ if (crnti) {
+ // MAC CE fixed subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = CRNTI;
+ mac_pdu_ptr++;
+
+ // C-RNTI MAC CE (2 octets)
+ * (uint16_t *) ce_ptr = crnti;
+ mac_ce_size = sizeof(uint16_t);
+
+ // Copying bytes for CRNTI MAC CE to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
+ ce_ptr += mac_ce_size;
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ if (truncated_bsr) {
+ // MAC CE fixed subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = UL_SCH_LCID_S_TRUNCATED_BSR;
+ mac_pdu_ptr++;
+
+ // Short truncated BSR MAC CE (1 octet)
+ ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> Buffer_size = truncated_bsr;
+ ((NR_BSR_SHORT_TRUNCATED *) ce_ptr)-> LcgID = 0; // todo
+ mac_ce_size = sizeof(NR_BSR_SHORT_TRUNCATED);
+
+ bsr = 1 ;
+ } else if (short_bsr) {
+ // MAC CE fixed subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = UL_SCH_LCID_S_BSR;
+ mac_pdu_ptr++;
+
+ // Short truncated BSR MAC CE (1 octet)
+ ((NR_BSR_SHORT *) ce_ptr)->Buffer_size = short_bsr;
+ ((NR_BSR_SHORT *) ce_ptr)->LcgID = 0; // todo
+ mac_ce_size = sizeof(NR_BSR_SHORT);
+
+ bsr = 1 ;
+ } else if (long_bsr) {
+ // MAC CE variable subheader
+ // todo ch 6.1.3.1. TS 38.321
+ // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+ // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+ // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = UL_SCH_LCID_L_BSR;
+ // ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = 0;
+ // last_size = 2;
+ // mac_pdu_ptr += last_size;
+
+ // Short truncated BSR MAC CE (1 octet)
+ // ((NR_BSR_LONG *) ce_ptr)->Buffer_size0 = short_bsr;
+ // ((NR_BSR_LONG *) ce_ptr)->LCGID0 = 0;
+ // mac_ce_size = sizeof(NR_BSR_LONG); // size is variable
+ }
+
+ if (bsr){
+ // Copying bytes for BSR MAC CE to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
+ ce_ptr += mac_ce_size;
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ // compute offset before adding padding (if necessary)
+ offset = ((unsigned char *) mac_pdu_ptr - pdu);
+ uint16_t padding_bytes = 0;
+
+ if(buflen > 0) // If the buflen is provided
+ padding_bytes = buflen - offset;
+
+ // Compute final offset for padding
+ if (post_padding > 0 || padding_bytes>0) {
+ ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = UL_SCH_LCID_PADDING;
+ mac_pdu_ptr++;
+ } else {
+ // no MAC subPDU with padding
+ }
+
+ // compute final offset
+ offset = ((unsigned char *) mac_pdu_ptr - pdu);
+
+ //printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - pdu));
return offset;
}
-
uint8_t
nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
sub_frame_t subframe, uint8_t eNB_index,
@@ -3438,13 +4053,6 @@ nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
sdu_length_total += sdu_lengths[num_sdus];
sdu_lcids[num_sdus] = lcid;
-
- //Update total MAC Header size for RLC PDUs
- /*if(sdu_lengths[num_sdus]<128)
- total_rlc_pdu_header_len += 2;
- else
- total_rlc_pdu_header_len += 3;*/
-
total_rlc_pdu_header_len += MAX_RLC_SDU_SUBHEADER_SIZE; //rlc_pdu_header_len_last;
//Update number of SDU
@@ -3469,13 +4077,18 @@ nr_ue_get_sdu(module_id_t module_idP, int CC_id, frame_t frameP,
// Generate ULSCH PDU
if (num_sdus>0) {
- payload_offset = nr_generate_ulsch_pdu(ulsch_buffer, // mac header
- ulsch_sdus,
+ payload_offset = nr_generate_ulsch_pdu(ulsch_sdus,
+ ulsch_buffer, // mac header
num_sdus, // num sdus
sdu_lengths, // sdu length
sdu_lcids, // sdu lcid
- NULL, // crnti
- buflen); // long_bsr
+ 0, // power_headroom
+ 0, // crnti
+ 0, // truncated_bsr
+ 0, // short_bsr
+ 0, // long_bsr
+ 0, // post_padding
+ buflen); // TBS in bytes
}
else
return 0;
diff --git a/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c
new file mode 100644
index 0000000000000000000000000000000000000000..8d52db6747849300881817f0f3b9b8dd39ecf05f
--- /dev/null
+++ b/openair2/LAYER2/NR_MAC_UE/rar_tools_nrUE.c
@@ -0,0 +1,212 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file rar_tools_nrUE.c
+ * \brief RA tools for NR UE
+ * \author Guido Casati
+ * \date 2019
+ * \version 1.0
+ * @ingroup _mac
+
+ */
+
+/* Sim */
+#include "SIMULATION/TOOLS/sim.h"
+
+/* Utils */
+#include "common/utils/LOG/log.h"
+#include "OCG.h"
+#include "OCG_extern.h"
+#include "UTIL/OPT/opt.h"
+
+/* Common */
+#include "common/ran_context.h"
+
+/* MAC */
+#include "NR_MAC_UE/mac.h"
+#include "NR_MAC_UE/mac_proto.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
+#include <common/utils/nr/nr_common.h>
+
+#define DEBUG_RAR
+
+// table 7.2-1 TS 38.321
+uint16_t table_7_2_1[16] = {
+ 5, // row index 0
+ 10, // row index 1
+ 20, // row index 2
+ 30, // row index 3
+ 40, // row index 4
+ 60, // row index 5
+ 80, // row index 6
+ 120, // row index 7
+ 160, // row index 8
+ 240, // row index 9
+ 320, // row index 10
+ 480, // row index 11
+ 960, // row index 12
+ 1920, // row index 13
+};
+
+/////////////////////////////////////
+// Random Access Response PDU //
+// TS 38.213 ch 8.2 //
+// TS 38.321 ch 6.2.3 //
+/////////////////////////////////////
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise
+//| E | T | R A P I D |//
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |//
+//| R | T A |//
+//| T A | UL grant |//
+//| UL grant |//
+//| UL grant |//
+//| UL grant |//
+//| T C - R N T I |//
+//| T C - R N T I |//
+/////////////////////////////////////
+// UL grant (27 bits) //
+/////////////////////////////////////
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise
+//|-------------------|FHF|F_alloc|//
+//| Freq allocation |//
+//| F_alloc |Time allocation|//
+//| MCS | TPC |CSI|//
+/////////////////////////////////////
+// WIP todo:
+// - apply UL grant freq alloc & time alloc as per 8.2 TS 38.213
+// - apply tpc command, csi req, mcs
+uint16_t nr_ue_process_rar(module_id_t mod_id,
+ int CC_id,
+ frame_t frameP,
+ uint8_t * dlsch_buffer,
+ rnti_t * t_crnti,
+ uint8_t preamble_index,
+ uint8_t * selected_rar_buffer){
+
+ NR_UE_MAC_INST_t *ue_mac = get_mac_inst(mod_id);
+ NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer; // RAR subheader pointer
+ NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1); // RAR subPDU pointer
+ uint8_t n_subPDUs = 0; // number of RAR payloads
+ uint8_t n_subheaders = 0; // number of MAC RAR subheaders
+ //uint8_t best_rx_rapid = -1; // the closest RAPID receive from all RARs
+ //unsigned char freq_hopping, msg3_t_alloc, mcs, tpc_command, csi_req; // WIP
+ //uint16_t ta_command = 0, msg3_f_alloc, bwp_size; // WIP
+ uint16_t ta_command = 0;
+ //int f_alloc, mask; // WIP
+
+ AssertFatal(CC_id == 0, "RAR reception on secondary CCs is not supported yet\n");
+
+ while (1) {
+ n_subheaders++;
+ if (rarh->T == 1) {
+ n_subPDUs++;
+ LOG_D(MAC, "[UE %d][RAPROC] Got RAPID RAR subPDU\n", mod_id);
+ } else {
+ n_subPDUs++;
+ ue_mac->RA_backoff_indicator = table_7_2_1[((NR_RA_HEADER_BI *)rarh)->BI];
+ ue_mac->RA_BI_found = 1;
+ LOG_D(MAC, "[UE %d][RAPROC] Got BI RAR subPDU %d\n", mod_id, ue_mac->RA_backoff_indicator);
+ }
+ if (rarh->RAPID == preamble_index) {
+ LOG_D(PHY, "[UE %d][RAPROC] Found RAR with the intended RAPID %d\n", mod_id, rarh->RAPID);
+ rar = (NR_MAC_RAR *) (dlsch_buffer + n_subheaders + (n_subPDUs - 1) * sizeof(NR_MAC_RAR));
+ ue_mac->RA_RAPID_found = 1;
+ break;
+ }
+ if (rarh->E == 0) {
+ LOG_I(PHY, "No RAR found with the intended RAPID. \n");
+ break;
+ } else {
+ rarh += sizeof(NR_MAC_RAR) + 1;
+ }
+ };
+
+ LOG_D(MAC, "number of RAR subheader %d; number of RAR pyloads %d\n", n_subheaders, n_subPDUs);
+
+ // LOG_I(MAC, "[UE %d][RAPROC] Frame %d Received RAR (%02x|%02x.%02x.%02x.%02x.%02x.%02x) for preamble %d/%d\n",
+ // mod_id, frameP, *(uint8_t *) rarh, rar[0], rar[1], rar[2], rar[3], rar[4], rar[5], rarh->RAPID, preamble_index);
+
+ #if 0 // TbD WIP Msg3 development ongoing
+ if (ue_mac->RA_RAPID_found) {
+ // TC-RNTI
+ *t_crnti = rar->TCRNTI_2 + (rar->TCRNTI_1 << 8);
+ ue_mac->t_crnti = *t_crnti;
+ ue_mac->rnti_type = NR_RNTI_TC;
+ // TA command
+ ta_command = rar->TA2 + (rar->TA1 << 5);
+ // CSI
+ csi_req = (unsigned char) (rar->UL_GRANT_4 & 0x01);
+ // TPC
+ tpc_command = (unsigned char) ((rar->UL_GRANT_4 >> 1) & 0x07);
+ switch (tpc_command){
+ case 0:
+ ue_mac->Msg3_TPC = -6;
+ break;
+ case 1:
+ ue_mac->Msg3_TPC = -4;
+ break;
+ case 2:
+ ue_mac->Msg3_TPC = -2;
+ break;
+ case 3:
+ ue_mac->Msg3_TPC = 0;
+ break;
+ case 4:
+ ue_mac->Msg3_TPC = 2;
+ break;
+ case 5:
+ ue_mac->Msg3_TPC = 4;
+ break;
+ case 6:
+ ue_mac->Msg3_TPC = 6;
+ break;
+ case 7:
+ ue_mac->Msg3_TPC = 8;
+ break;
+ }
+ //MCS
+ mcs = (unsigned char) (rar->UL_GRANT_4 >> 4);
+ // time and frequency alloc
+ bwp_size = NRRIV2BW(ue_mac->ULbwp[0]->bwp_Common->genericParameters.locationAndBandwidth,275);
+ msg3_t_alloc = (unsigned char) (rar->UL_GRANT_3 & 0x07);
+ msg3_f_alloc = (uint16_t) ((rar->UL_GRANT_3 >> 4) | (rar->UL_GRANT_2 << 4) | ((rar->UL_GRANT_1 & 0x03) << 12));
+
+ if (bwp_size < 180)
+ mask = (1 << ((int) ceil(log2((bwp_size*(bwp_size+1))>>1)))) - 1;
+ else
+ mask = (1 << (28 - (int)(ceil(log2((bwp_size*(bwp_size+1))>>1))))) - 1;
+
+ f_alloc = msg3_f_alloc & mask;
+
+ // frequency hopping flag
+ freq_hopping = (unsigned char) (rar->UL_GRANT_1 >> 2);
+ } else {
+ ue_mac->t_crnti = 0;
+ ta_command = (0xffff);
+ }
+ #endif
+
+ // move the selected RAR to the front of the RA_PDSCH buffer
+ memcpy((void *) (selected_rar_buffer + 0), (void *) rarh, 1);
+ memcpy((void *) (selected_rar_buffer + 1), (void *) rar, sizeof(NR_MAC_RAR));
+
+ return ta_command;
+}
diff --git a/openair2/LAYER2/NR_MAC_gNB/config.c b/openair2/LAYER2/NR_MAC_gNB/config.c
index c911fbd56a6c6aa5d53048131067815e014b4d0b..36b81927f80e95283b2b2ab339340e9970fcd1ae 100644
--- a/openair2/LAYER2/NR_MAC_gNB/config.c
+++ b/openair2/LAYER2/NR_MAC_gNB/config.c
@@ -44,14 +44,13 @@
#include "SCHED_NR/phy_frame_config_nr.h"
#include "NR_MIB.h"
-#include "nr_mac_common.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h"
extern RAN_CONTEXT_t RC;
//extern int l2_init_gNB(void);
extern void mac_top_init_gNB(void);
extern uint8_t nfapi_mode;
-
void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigCommon_t *scc) {
nfapi_nr_config_request_scf_t *cfg = &RC.nrmac[Mod_idP]->config[0];
@@ -122,13 +121,23 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
}
}
+ lte_frame_type_t frame_type;
+ uint16_t band;
+ int32_t offset;
+
+ get_band((cfg->carrier_config.dl_frequency.value)*1000,
+ &band,
+ &offset,
+ &frame_type);
+
+ RC.nrmac[Mod_idP]->common_channels[0].frame_type = frame_type;
// Cell configuration
cfg->cell_config.phy_cell_id.value = *scc->physCellId;
cfg->cell_config.phy_cell_id.tl.tag = NFAPI_NR_CONFIG_PHY_CELL_ID_TAG;
cfg->num_tlv++;
- cfg->cell_config.frame_duplex_type.value = 1;
+ cfg->cell_config.frame_duplex_type.value = frame_type;
cfg->cell_config.frame_duplex_type.tl.tag = NFAPI_NR_CONFIG_FRAME_DUPLEX_TYPE_TAG;
cfg->num_tlv++;
@@ -144,7 +153,11 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
// PRACH configuration
- cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present;
+ uint8_t nb_preambles = 64;
+ if(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL)
+ nb_preambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles;
+
+ cfg->prach_config.prach_sequence_length.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->prach_RootSequenceIndex.present-1;
cfg->prach_config.prach_sequence_length.tl.tag = NFAPI_NR_CONFIG_PRACH_SEQUENCE_LENGTH_TAG;
cfg->num_tlv++;
@@ -154,7 +167,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
cfg->prach_config.prach_sub_c_spacing.value = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
cfg->prach_config.prach_sub_c_spacing.tl.tag = NFAPI_NR_CONFIG_PRACH_SUB_C_SPACING_TAG;
cfg->num_tlv++;
-
cfg->prach_config.restricted_set_config.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig;
cfg->prach_config.restricted_set_config.tl.tag = NFAPI_NR_CONFIG_RESTRICTED_SET_CONFIG_TAG;
cfg->num_tlv++;
@@ -193,13 +205,17 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig;
cfg->prach_config.num_prach_fd_occasions_list[i].prach_zero_corr_conf.tl.tag = NFAPI_NR_CONFIG_PRACH_ZERO_CORR_CONF_TAG;
cfg->num_tlv++;
+ cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.value = compute_nr_root_seq(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup,
+ nb_preambles, frame_type);
+ cfg->prach_config.num_prach_fd_occasions_list[i].num_root_sequences.tl.tag = NFAPI_NR_CONFIG_NUM_ROOT_SEQUENCES_TAG;
+ cfg->num_tlv++;
//cfg->prach_config.num_prach_fd_occasions_list[i].num_unused_root_sequences.value = ???
}
- cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present;
+ cfg->prach_config.ssb_per_rach.value = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->ssb_perRACH_OccasionAndCB_PreamblesPerSSB->present-1;
cfg->prach_config.ssb_per_rach.tl.tag = NFAPI_NR_CONFIG_SSB_PER_RACH_TAG;
cfg->num_tlv++;
-
+
// SSB Table Configuration
int scs_scaling = 1<<(cfg->ssb_config.scs_common.value);
if (scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA < 600000)
@@ -274,8 +290,7 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots,
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols,
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots,
- scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols
- );
+ scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols);
if (return_tdd !=0){
LOG_E(PHY,"TDD configuration can not be done\n");
@@ -283,7 +298,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
else LOG_I(PHY,"TDD has been properly configurated\n");
}
-
/*
// PDCCH-ConfigCommon
cfg->pdcch_config.controlResourceSetZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero;
@@ -359,6 +373,12 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (add_ue == 1) {
UE_id = add_new_nr_ue(Mod_idP,rnti);
UE_list->secondaryCellGroup[UE_id] = secondaryCellGroup;
+ uint8_t num_preamble = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.count;
+ UE_list->preambles[UE_id].num_preambles = num_preamble;
+ UE_list->preambles[UE_id].preamble_list = (uint8_t *) malloc(num_preamble*sizeof(uint8_t));
+ for (int i=0; i<num_preamble; i++) {
+ UE_list->preambles[UE_id].preamble_list[i] = secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list.array[i]->ra_PreambleIndex;
+ }
LOG_I(PHY,"Added new UE_id %d/%x with initial secondaryCellGroup\n",UE_id,rnti);
}
else { // secondaryCellGroup has been updated
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
index e5840d9cd194c8db84bb7799f3b5c375e2ffc719..e25680e8618462cf70e74e5dce11d50697c72dc6 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
@@ -33,9 +33,9 @@
#include "assertions.h"
#include "LAYER2/MAC/mac.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
#include "LAYER2/MAC/mac_proto.h"
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_gNB/mac_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
@@ -59,6 +59,7 @@
#include "executables/softmodem-common.h"
+const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
@@ -257,18 +258,6 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram
}
*/
-/*
-void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP) {
-
- gNB_MAC_INST *gNB = RC.nrmac[module_idP];
-
- // schedule PRACH for iniital BWP
-
- if (is_initialBWP_prach_subframe(frameP,subframeP)<0) return;
-
- // fill FAPI
-}
-*/
/*
void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
@@ -299,6 +288,64 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
}
*/
+void nr_schedule_pucch(int Mod_idP,
+ int UE_id,
+ frame_t frameP,
+ sub_frame_t slotP) {
+
+ uint16_t O_uci;
+ uint16_t O_ack;
+ uint8_t SR_flag = 0; // no SR in PUCCH implemented for now
+ NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
+ NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
+ AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id);
+
+ NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ int bwp_id=1;
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
+ nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
+
+ NR_sched_pucch *curr_pucch;
+ int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
+ nr_ulmix_slots++;
+
+ for (int k=0; k<nr_ulmix_slots; k++) {
+ curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
+ if ((curr_pucch->dai_c > 0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
+ UL_tti_req->SFN = frameP;
+ UL_tti_req->Slot = slotP;
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t);
+ nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pucch_pdu;
+ memset(pucch_pdu,0,sizeof(nfapi_nr_pucch_pdu_t));
+ UL_tti_req->n_pdus+=1;
+ O_ack = curr_pucch->dai_c;
+ O_uci = O_ack; // for now we are just sending acknacks in pucch
+
+ LOG_I(MAC, "Scheduling pucch reception for frame %d slot %d\n", frameP, slotP);
+
+ nr_configure_pucch(pucch_pdu,
+ scc,
+ ubwp,
+ curr_pucch->resource_indicator,
+ O_uci,
+ O_ack,
+ SR_flag);
+
+ curr_pucch->dai_c = 0;
+ }
+ }
+}
+
+bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){
+
+ if((bitmap>>slot)&0x01)
+ return true;
+ else
+ return false;
+}
+
void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
frame_t frame_rxP,
sub_frame_t slot_rxP,
@@ -309,14 +356,37 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
protocol_ctxt_t ctxt;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, module_idP, ENB_FLAG_YES, NOT_A_RNTI, frame_txP, slot_txP,module_idP);
- int CC_id, UE_id = 0;
+
+ int CC_id;
+ int UE_id;
+ uint64_t *dlsch_in_slot_bitmap=NULL;
+ uint64_t *ulsch_in_slot_bitmap=NULL;
+ int pucch_sched;
+
+ UE_id=0;
+ int bwp_id = 1;
+
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_UE_list_t *UE_list = &gNB->UE_list;
- UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
+ NR_UE_sched_ctrl_t *ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
NR_COMMON_channels_t *cc = gNB->common_channels;
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ int num_slots_per_tdd = (slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
+
+ int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
+ nr_ulmix_slots++;
+
+ if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
+ for (int k=0; k<nr_ulmix_slots; k++) {
+ memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
+ 0,
+ sizeof(NR_sched_pucch));
+ }
+ }
start_meas(&RC.nrmac[module_idP]->eNB_scheduler);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_IN);
pdcp_run(&ctxt);
//rrc_rx_tx(&ctxt, CC_id);
@@ -324,76 +394,116 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
RC.nrmac[module_idP]->frame = frame_rxP;
RC.nrmac[module_idP]->slot = slot_rxP;
+ dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
+ ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
+
+ // hardcoding dlsch to be in slot 1
+ if (!(slot_txP%num_slots_per_tdd)) {
+ if(slot_txP==0)
+ *dlsch_in_slot_bitmap = 0x02;
+ else
+ *dlsch_in_slot_bitmap = 0x00;
+ }
+
+ // hardcoding ulsch to be in slot 8
+ if (!(slot_rxP%num_slots_per_tdd)) {
+ if(slot_rxP==0)
+ *ulsch_in_slot_bitmap = 0x100;
+ else
+ *ulsch_in_slot_bitmap = 0x00;
+ }
+
// Check if there are downlink symbols in the slot,
if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)) {
+ memset(RC.nrmac[module_idP]->cce_list[bwp_id][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
+ memset(RC.nrmac[module_idP]->cce_list[bwp_id][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid 1
+ for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
+ //mbsfn_status[CC_id] = 0;
- memset(RC.nrmac[module_idP]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
- for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
- //mbsfn_status[CC_id] = 0;
-
- // clear vrb_maps
- memset(cc[CC_id].vrb_map, 0, 100);
- memset(cc[CC_id].vrb_map_UL, 0, 100);
+ // clear vrb_maps
+ memset(cc[CC_id].vrb_map, 0, 100);
+ memset(cc[CC_id].vrb_map_UL, 0, 100);
- clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP);
- }
+ clear_nr_nfapi_information(RC.nrmac[module_idP], CC_id, frame_txP, slot_txP);
+ }
- // refresh UE list based on UEs dropped by PHY in previous subframe
- /*
- for (i = 0; i < MAX_MOBILES_PER_GNB; i++) {
- if (UE_list->active[i]) {
+ // refresh UE list based on UEs dropped by PHY in previous subframe
+ /*
+ for (i = 0; i < MAX_MOBILES_PER_GNB; i++) {
+ if (UE_list->active[i]) {
- nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id];
-
+ nfapi_nr_config_request_t *cfg = &RC.nrmac[module_idP]->config[CC_id];
- rnti = 0;//UE_RNTI(module_idP, i);
- CC_id = 0;//UE_PCCID(module_idP, i);
-
- } //END if (UE_list->active[i])
- } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++)
- */
-
- // This schedules MIB
- if((slot_txP == 0) && (frame_txP & 7) == 0){
- schedule_nr_mib(module_idP, frame_txP, slot_txP);
- }
+ rnti = 0;//UE_RNTI(module_idP, i);
+ CC_id = 0;//UE_PCCID(module_idP, i);
- // TbD once RACH is available, start ta_timer when UE is connected
- if (ue_sched_ctl->ta_timer) ue_sched_ctl->ta_timer--;
-
- if (ue_sched_ctl->ta_timer == 0) {
- gNB->ta_command = ue_sched_ctl->ta_update;
- /* if time is up, then set the timer to not send it for 5 frames
- // regardless of the TA value */
- ue_sched_ctl->ta_timer = 100;
- /* reset ta_update */
- ue_sched_ctl->ta_update = 31;
- /* MAC CE flag indicating TA length */
- gNB->ta_len = 2;
- }
+ } //END if (UE_list->active[i])
+ } //END for (i = 0; i < MAX_MOBILES_PER_GNB; i++)
+ */
- // Phytest scheduling
- if (get_softmodem_params()->phy_test && slot_txP==1){
- nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL);
- // resetting ta flag
- gNB->ta_len = 0;
- }
+ // This schedules MIB
+ if((slot_txP == 0) && (frame_txP & 7) == 0){
+ schedule_nr_mib(module_idP, frame_txP, slot_txP);
+ }
- /*
- // Allocate CCEs for good after scheduling is done
- for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++)
- allocate_CCEs(module_idP, CC_id, subframeP, 0);
- */
+ if (get_softmodem_params()->phy_test == 0)
+ nr_schedule_RA(module_idP, frame_txP, slot_txP);
+ else
+ UE_list->fiveG_connected[UE_id] = true;
+
+ // Phytest scheduling
+
+ if (get_softmodem_params()->phy_test) {
+
+ // TbD once RACH is available, start ta_timer when UE is connected
+ if (ue_sched_ctl->ta_timer)
+ ue_sched_ctl->ta_timer--;
+
+ if (ue_sched_ctl->ta_timer == 0) {
+ gNB->ta_command = ue_sched_ctl->ta_update;
+ /* if time is up, then set the timer to not send it for 5 frames
+ // regardless of the TA value */
+ ue_sched_ctl->ta_timer = 100;
+ /* reset ta_update */
+ ue_sched_ctl->ta_update = 31;
+ /* MAC CE flag indicating TA length */
+ gNB->ta_len = 2;
+ }
+ }
+
+ if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
+ ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd;
+ nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched);
+ nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
+ // resetting ta flag
+ gNB->ta_len = 0;
+ }
+
+ /*
+ // Allocate CCEs for good after scheduling is done
+ for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++)
+ allocate_CCEs(module_idP, CC_id, subframeP, 0);
+ */
} //is_nr_DL_slot
if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) {
- if (get_softmodem_params()->phy_test && slot_rxP==8){
- nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
+
+ if (get_softmodem_params()->phy_test == 0) {
+ if (UE_list->fiveG_connected[UE_id])
+ nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
+ schedule_nr_prach(module_idP, (frame_rxP+1)&1023, slot_rxP);
+ nr_schedule_reception_msg3(module_idP, 0, frame_rxP, slot_rxP);
+ }
+ if (get_softmodem_params()->phy_test){
+ nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
+ if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){
+ nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
+ }
}
}
stop_meas(&RC.nrmac[module_idP]->eNB_scheduler);
- VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT);
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ULSCH_SCHEDULER,VCD_FUNCTION_OUT);
}
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
index d74df15eac813bb1137cf299a3c06c25d307684d..e90a69638c47216554b29b01096c5c3adcac9b51 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
@@ -19,44 +19,805 @@
* contact@openairinterface.org
*/
-/*! \file gNB_scheduler_RA.c
- * \brief primitives used for random access
- * \author
- * \date
- * \email:
+/*! \file gNB_scheduler_RA.c
+ * \brief primitives used for random access
+ * \author Guido Casati
+ * \date 2019
+ * \email: guido.casati@iis.fraunhofer.de
* \version
*/
-#include nr_mac_gNB.h
+#include "platform_types.h"
-void
-schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP)
-{
+/* MAC */
+#include "nr_mac_gNB.h"
+#include "NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
- eNB_MAC_INST *mac = RC.mac[module_idP];
- COMMON_channels_t *cc = mac->common_channels;
- RA_t *ra;
- uint8_t i;
+/* Utils */
+#include "common/utils/LOG/log.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
+#include "common/utils/nr/nr_common.h"
+#include "UTIL/OPT/opt.h"
+#include "SIMULATION/TOOLS/sim.h" // for taus
+
+extern RAN_CONTEXT_t RC;
+extern const uint8_t nr_slots_per_frame[5];
+
+uint8_t DELTA[4]= {2,3,4,6};
+
+void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
+
+ gNB_MAC_INST *gNB = RC.nrmac[module_idP];
+ NR_COMMON_channels_t *cc = gNB->common_channels;
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[module_idP]->UL_tti_req[0];
+
+ uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex;
+ uint8_t mu,N_dur,N_t_slot,start_symbol;
+ uint16_t format;
+
+ if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing)
+ mu = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg1_SubcarrierSpacing;
+ else
+ mu = scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing;
+
+ // prach is scheduled according to configuration index and tables 6.3.3.2.2 to 6.3.3.2.4
+ if ( get_nr_prach_info_from_index(config_index,
+ (int)frameP,
+ (int)slotP,
+ scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA,
+ mu,
+ cc->frame_type,
+ &format,
+ &start_symbol,
+ &N_t_slot,
+ &N_dur) ) {
+
+ int fdm = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM;
+ uint16_t format0 = format&0xff; // first column of format from table
+ uint16_t format1 = (format>>8)&0xff; // second column of format from table
+
+ UL_tti_req->SFN = frameP;
+ UL_tti_req->Slot = slotP;
+ for (int n=0; n<(1<<fdm); n++) { // one structure per frequency domain occasion
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE;
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_prach_pdu_t);
+ nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].prach_pdu;
+ memset(prach_pdu,0,sizeof(nfapi_nr_prach_pdu_t));
+ UL_tti_req->n_pdus+=1;
+
+ // filling the prach fapi structure
+ prach_pdu->phys_cell_id = *scc->physCellId;
+ prach_pdu->num_prach_ocas = N_t_slot;
+ prach_pdu->prach_start_symbol = start_symbol;
+ prach_pdu->num_ra = n;
+ prach_pdu->num_cs = get_NCS(scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.zeroCorrelationZoneConfig,
+ format0,
+ scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->restrictedSetConfig);
+ // SCF PRACH PDU format field does not consider A1/B1 etc. possibilities
+ // We added 9 = A1/B1 10 = A2/B2 11 A3/B3
+ if (format1!=0xff) {
+ switch(format0) {
+ case 0xa1:
+ prach_pdu->prach_format = 9;
+ break;
+ case 0xa2:
+ prach_pdu->prach_format = 10;
+ break;
+ case 0xa3:
+ prach_pdu->prach_format = 11;
+ break;
+ default:
+ AssertFatal(1==0,"Only formats A1/B1 A2/B2 A3/B3 are valid for dual format");
+ }
+ }
+ else{
+ switch(format0) {
+ case 0xa1:
+ prach_pdu->prach_format = 0;
+ break;
+ case 0xa2:
+ prach_pdu->prach_format = 1;
+ break;
+ case 0xa3:
+ prach_pdu->prach_format = 2;
+ break;
+ case 0xb1:
+ prach_pdu->prach_format = 3;
+ break;
+ case 0xb2:
+ prach_pdu->prach_format = 4;
+ break;
+ case 0xb3:
+ prach_pdu->prach_format = 5;
+ break;
+ case 0xb4:
+ prach_pdu->prach_format = 6;
+ break;
+ case 0xc0:
+ prach_pdu->prach_format = 7;
+ break;
+ case 0xc2:
+ prach_pdu->prach_format = 8;
+ break;
+ case 0:
+ // long formats are handled @ PHY
+ break;
+ case 1:
+ // long formats are handled @ PHY
+ break;
+ case 2:
+ // long formats are handled @ PHY
+ break;
+ case 3:
+ // long formats are handled @ PHY
+ break;
+ default:
+ AssertFatal(1==0,"Invalid PRACH format");
+ }
+ }
+ }
+ }
+}
+
+
+void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
+ uint16_t *msg2_frame, uint16_t *msg2_slot,
+ NR_ServingCellConfigCommon_t *scc,
+ uint16_t monitoring_slot_period,
+ uint16_t monitoring_offset){
+
+ // preferentially we schedule the msg2 in the mixed slot or in the last dl slot
+ // if they are allowed by search space configuration
+
+ uint8_t mu = *scc->ssbSubcarrierSpacing;
+ uint8_t response_window = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.ra_ResponseWindow;
+ uint8_t slot_window;
+ // number of mixed slot or of last dl slot if there is no mixed slot
+ uint8_t last_dl_slot_period = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
+ // lenght of tdd period in slots
+ uint8_t tdd_period_slot = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots + scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols == 0)
+ last_dl_slot_period--;
+ if ((scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols > 0) || (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols > 0))
+ tdd_period_slot++;
+
+ // computing start of next period
+ uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame[mu];
+ *msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
+ *msg2_frame = (*msg2_slot>(rach_slot))? rach_frame : (rach_frame +1);
+
+ switch(response_window){
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl1:
+ slot_window = 1;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl2:
+ slot_window = 2;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl4:
+ slot_window = 4;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl8:
+ slot_window = 8;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl10:
+ slot_window = 10;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl20:
+ slot_window = 20;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl40:
+ slot_window = 40;
+ break;
+ case NR_RACH_ConfigGeneric__ra_ResponseWindow_sl80:
+ slot_window = 80;
+ break;
+ default:
+ AssertFatal(1==0,"Invalid response window value %d\n",response_window);
+ }
+ AssertFatal(slot_window<=nr_slots_per_frame[mu],"Msg2 response window needs to be lower or equal to 10ms");
+
+ // slot and frame limit to transmit msg2 according to response window
+ uint8_t slot_limit = (rach_slot + slot_window)%nr_slots_per_frame[mu];
+ //uint8_t frame_limit = (slot_limit>(rach_slot))? rach_frame : (rach_frame +1);
+
+
+ // go to previous slot if the current scheduled slot is beyond the response window
+ // and if the slot is not among the PDCCH monitored ones (38.213 10.1)
+ while ((*msg2_slot>slot_limit) || ((*msg2_frame*nr_slots_per_frame[mu]+*msg2_slot-monitoring_offset)%monitoring_slot_period !=0)) {
+ if((*msg2_slot%tdd_period_slot) > 0)
+ (*msg2_slot)--;
+ else
+ AssertFatal(1==0,"No available DL slot to schedule msg2 has been found");
+ }
+}
+
+
+void nr_initiate_ra_proc(module_id_t module_idP,
+ int CC_id,
+ frame_t frameP,
+ sub_frame_t slotP,
+ uint16_t preamble_index,
+ uint8_t freq_index,
+ uint8_t symbol,
+ int16_t timing_offset){
+
+ uint8_t ul_carrier_id = 0; // 0 for NUL 1 for SUL
+ NR_SearchSpace_t *ss;
+ int UE_id = 0;
+ // ra_rnti from 5.1.3 in 38.321
+ uint16_t ra_rnti=1+symbol+(slotP*14)+(freq_index*14*80)+(ul_carrier_id*14*80*8);
+
+ uint16_t msg2_frame, msg2_slot,monitoring_slot_period,monitoring_offset;
+ gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
+ NR_UE_list_t *UE_list = &nr_mac->UE_list;
+ NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ NR_RA_t *ra = &cc->ra[0];
+
+ // if the preamble received correspond to one of the listed
+ // the UE sent a RACH either for starting RA procedure or RA procedure failed and UE retries
+ int pr_found=0;
+ for (int i=0;i<UE_list->preambles[UE_id].num_preambles;i++) {
+ if (preamble_index == UE_list->preambles[UE_id].preamble_list[i]) {
+ pr_found=1;
+ break;
+ }
+ }
+ if (pr_found)
+ UE_list->fiveG_connected[UE_id] = false;
+ else {
+ LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: preamble %d does not correspond to any of the ones in rach_ConfigDedicated for UE_id %d\n",
+ module_idP, preamble_index, UE_id);
+ return; // if the PRACH preamble does not correspond to any of the ones sent through RRC abort RA proc
+ }
+
+ // This should be handled differently when we use the initialBWP for RA
+ ra->bwp_id=1;
+ NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id-1];
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1);
+
+ LOG_I(MAC, "[gNB %d][RAPROC] CC_id %d Frame %d, Slot %d Initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, slotP, preamble_index);
+
+ if (ra->state == RA_IDLE) {
+ int loop = 0;
+ LOG_D(MAC, "Frame %d, Slot %d: Activating RA process \n", frameP, slotP);
+ ra->state = Msg2;
+ ra->timing_offset = timing_offset;
+ ra->preamble_slot = slotP;
+
+ struct NR_PDCCH_ConfigCommon__commonSearchSpaceList *commonSearchSpaceList = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList;
+ AssertFatal(commonSearchSpaceList->list.count>0,
+ "common SearchSpace list has 0 elements\n");
+ // Common searchspace list
+ for (int i=0;i<commonSearchSpaceList->list.count;i++) {
+ ss=commonSearchSpaceList->list.array[i];
+ if(ss->searchSpaceId == *bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->ra_SearchSpace)
+ ra->ra_ss=ss;
+ }
+
+ // retrieving ra pdcch monitoring period and offset
+ find_monitoring_periodicity_offset_common(ra->ra_ss,
+ &monitoring_slot_period,
+ &monitoring_offset);
+
+ nr_schedule_msg2(frameP, slotP, &msg2_frame, &msg2_slot, scc, monitoring_slot_period, monitoring_offset);
+
+ ra->Msg2_frame = msg2_frame;
+ ra->Msg2_slot = msg2_slot;
+
+ LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP);
+
+ do {
+ ra->rnti = (taus() % 65518) + 1;
+ loop++;
+ }
+ while (loop != 100 && !(find_nr_UE_id(module_idP, ra->rnti) == -1 && ra->rnti >= 1 && ra->rnti <= 65519));
+ if (loop == 100) {
+ LOG_E(MAC,"%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__);
+ abort();
+ }
+
+ ra->RA_rnti = ra_rnti;
+ ra->preamble_index = preamble_index;
+ UE_list->tc_rnti[UE_id] = ra->rnti;
+
+ LOG_I(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x\n",
+ module_idP,
+ CC_id,
+ frameP,
+ ra->Msg2_frame,
+ ra->Msg2_slot,
+ ra->RA_rnti);
+
+ return;
+ }
+ LOG_E(MAC, "[gNB %d][RAPROC] FAILURE: CC_id %d Frame %d initiating RA procedure for preamble index %d\n", module_idP, CC_id, frameP, preamble_index);
+
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0);
+}
+
+void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
+
+ //uint8_t i = 0;
+ int CC_id = 0;
+ gNB_MAC_INST *mac = RC.nrmac[module_idP];
+ NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
+ NR_RA_t *ra = &cc->ra[0];
start_meas(&mac->schedule_ra);
+ //for (i = 0; i < NR_NB_RA_PROC_MAX; i++) {
+ LOG_D(MAC,"RA[state:%d]\n",ra->state);
+ switch (ra->state){
+ case Msg2:
+ nr_generate_Msg2(module_idP, CC_id, frameP, slotP);
+ break;
+ case Msg4:
+ //generate_Msg4(module_idP, CC_id, frameP, slotP, ra);
+ break;
+ case WAIT_Msg4_ACK:
+ //check_Msg4_retransmission(module_idP, CC_id, frameP, slotP, ra);
+ break;
+ default:
+ break;
+ }
+ //}
+ stop_meas(&mac->schedule_ra);
+}
+
+void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Uplink_t *ubwp,
+ sub_frame_t current_slot,
+ frame_t current_frame,
+ NR_RA_t *ra) {
+
+ // msg3 is schedulend in mixed slot in the following TDD period
+ // for now we consider a TBS of 18 bytes
+
+ int mu = ubwp->bwp_Common->genericParameters.subcarrierSpacing;
+ int StartSymbolIndex, NrOfSymbols, startSymbolAndLength, temp_slot;
+ ra->Msg3_tda_id = 16; // initialization to a value above limit
+
+ for (int i=0; i<ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; i++) {
+ startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
+ SLIV2SL(startSymbolAndLength, &StartSymbolIndex, &NrOfSymbols);
+ // we want to transmit in the uplink symbols of mixed slot
+ if (NrOfSymbols == scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols) {
+ ra->Msg3_tda_id = i;
+ break;
+ }
+ }
+ AssertFatal(ra->Msg3_tda_id<16,"Unable to find Msg3 time domain allocation in list\n");
+
+ uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2;
+
+ temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213
+ ra->Msg3_slot = temp_slot%nr_slots_per_frame[mu];
+ if (nr_slots_per_frame[mu]>temp_slot)
+ ra->Msg3_frame = current_frame;
+ else
+ ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame[mu]);
+
+ ra->msg3_nb_rb = 18;
+ ra->msg3_first_rb = 0;
+}
+
+
+void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){
+ gNB_MAC_INST *mac = RC.nrmac[module_idP];
+ nfapi_nr_ul_tti_request_t *ul_req = &mac->UL_tti_req[0];
+ NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
+ NR_RA_t *ra = &cc->ra[0];
+
+ if (ra->state == WAIT_Msg3) {
+ if ((frameP == ra->Msg3_frame) && (slotP == ra->Msg3_slot) ){
+ ul_req->SFN = ra->Msg3_frame;
+ ul_req->Slot = ra->Msg3_slot;
+ ul_req->pdus_list[ul_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
+ ul_req->pdus_list[ul_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
+ ul_req->pdus_list[ul_req->n_pdus].pusch_pdu = ra->pusch_pdu;
+ ul_req->n_pdus+=1;
+ ra->state = RA_IDLE;
+ }
+ }
+}
+
+void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP){
+
+ gNB_MAC_INST *mac = RC.nrmac[module_idP];
+ NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ NR_RA_t *ra = &cc->ra[0];
+ NR_UE_list_t *UE_list = &mac->UE_list;
+ int UE_id = 0;
+
+ AssertFatal(ra->state != RA_IDLE, "RA is not active for RA %X\n", ra->rnti);
+
+ LOG_D(MAC, "[gNB %d][RAPROC] Frame %d, Subframe %d : CC_id %d RA is active, Msg3 in (%d,%d)\n", module_idP, frameP, slotP, CC_id, ra->Msg3_frame, ra->Msg3_slot);
+
+ nfapi_nr_pusch_pdu_t *pusch_pdu = &ra->pusch_pdu;
+ memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
+
+
+ AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n", UE_id);
+
+ NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
+ "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1];
+ LOG_D(MAC, "Frame %d, Subframe %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n",
+ frameP,
+ slotP,
+ ra->Msg3_frame,
+ ra->Msg3_slot,
+ ra->msg3_nb_rb,
+ ra->msg3_first_rb,
+ ra->msg3_round,
+ ra->rnti);
+
+ int startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->startSymbolAndLength;
+ int start_symbol_index,nr_of_symbols;
+ SLIV2SL(startSymbolAndLength, &start_symbol_index, &nr_of_symbols);
+
+ pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
+ pusch_pdu->rnti = ra->rnti;
+ pusch_pdu->handle = 0;
+ int abwp_size = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ int abwp_start = NRRIV2PRBOFFSET(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275);
+ int ibwp_start = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth,275);
+ if ((ibwp_start < abwp_start) || (ibwp_size > abwp_size))
+ pusch_pdu->bwp_start = abwp_start;
+ else
+ pusch_pdu->bwp_start = ibwp_start;
+ pusch_pdu->bwp_size = ibwp_size;
+ pusch_pdu->subcarrier_spacing = ubwp->bwp_Common->genericParameters.subcarrierSpacing;
+ pusch_pdu->cyclic_prefix = 0;
+ pusch_pdu->mcs_index = 0;
+ pusch_pdu->mcs_table = 0;
+ pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
+ pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table);
+ if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL)
+ pusch_pdu->transform_precoding = 1;
+ else
+ pusch_pdu->transform_precoding = 0;
+ pusch_pdu->data_scrambling_id = *scc->physCellId;
+ pusch_pdu->nrOfLayers = 1;
+ pusch_pdu->ul_dmrs_symb_pos = 1<<start_symbol_index; // ok for now but use fill dmrs mask later
+ pusch_pdu->dmrs_config_type = 0;
+ pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id.
+ pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0.
+ pusch_pdu->dmrs_ports = 1; // 6.2.2 in 38.214 only port 0 to be used
+ pusch_pdu->num_dmrs_cdm_grps_no_data = 2; // no data in dmrs symbols as in 6.2.2 in 38.214
+ pusch_pdu->resource_alloc = 1; //type 1
+ pusch_pdu->rb_start = ra->msg3_first_rb + ibwp_start - abwp_start; // as for 6.3.1.7 in 38.211
+ if (ra->msg3_nb_rb > pusch_pdu->bwp_size)
+ AssertFatal(1==0,"MSG3 allocated number of RBs exceed the BWP size\n");
+ else
+ pusch_pdu->rb_size = ra->msg3_nb_rb;
+ pusch_pdu->vrb_to_prb_mapping = 0;
+ if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->frequencyHopping == NULL)
+ pusch_pdu->frequency_hopping = 0;
+ else
+ pusch_pdu->frequency_hopping = 1;
+ //pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE]
+ pusch_pdu->uplink_frequency_shift_7p5khz = 0;
+ //Resource Allocation in time domain
+ pusch_pdu->start_symbol_index = start_symbol_index;
+ pusch_pdu->nr_of_symbols = nr_of_symbols;
+ //Optional Data only included if indicated in pduBitmap
+ pusch_pdu->pusch_data.rv_index = 0; // 8.3 in 38.213
+ pusch_pdu->pusch_data.harq_process_id = 0;
+ pusch_pdu->pusch_data.new_data_indicator = 1; // new data
+ pusch_pdu->pusch_data.num_cb = 0;
+ pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order,
+ pusch_pdu->target_code_rate,
+ pusch_pdu->rb_size,
+ pusch_pdu->nr_of_symbols,
+ 12, // nb dmrs set for no data in dmrs symbol
+ 0, //nb_rb_oh
+ 0, // to verify tb scaling
+ pusch_pdu->nrOfLayers = 1)>>3;
+
+ // calling function to fill rar message
+ nr_fill_rar(module_idP, ra, cc->RAR_pdu.payload, pusch_pdu);
+
+}
+
+// WIP
+// todo:
+// - fix me
+// - get msg3 alloc (see nr_process_rar)
+void nr_generate_Msg2(module_id_t module_idP,
+ int CC_id,
+ frame_t frameP,
+ sub_frame_t slotP){
+
+ int UE_id = 0, dci_formats[2], rnti_types[2], mcsIndex;
+ int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment;
+ gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
+ NR_COMMON_channels_t *cc = &nr_mac->common_channels[0];
+ NR_RA_t *ra = &cc->ra[0];
+ NR_UE_list_t *UE_list = &nr_mac->UE_list;
+ NR_SearchSpace_t *ss = ra->ra_ss;
+
+ uint16_t RA_rnti = ra->RA_rnti;
+ long locationAndBandwidth;
+ // uint8_t *vrb_map = cc[CC_id].vrb_map, CC_id;
+
+ // check if UE is doing RA on CORESET0 , InitialBWP or configured BWP from SCD
+ // get the BW of the PDCCH for PDCCH size and RAR PDSCH size
+
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ int dci10_bw;
+
+ if (ra->coreset0_configured == 1) {
+ AssertFatal(1==0,"This is a standalone condition\n");
+ }
+ else { // on configured BWP or initial LDBWP, bandwidth parameters in DCI correspond size of initialBWP
+ locationAndBandwidth = scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth;
+ dci10_bw = NRRIV2BW(locationAndBandwidth,275);
+ }
+
+ if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
+
+ nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
+ nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
+
+ nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
+ memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
+ dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
+ dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
+
+ nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs+1];
+ memset((void *)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
+ dl_tti_pdsch_pdu->PDUType = NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE;
+ dl_tti_pdsch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdsch_pdu));
+
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
+ nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
+
+ // Checking if the DCI allocation is feasible in current subframe
+ if (dl_req->nPDUs == NFAPI_NR_MAX_DL_TTI_PDUS) {
+ LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, RA_rnti);
+ return;
+ }
+
+ LOG_I(MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RAR DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state);
+
+ // This code from this point on will not work on initialBWP or CORESET0
+ AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n");
+
+ NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
+ "downlinkBWP_ToAddModList has %d BWP!\n", secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
+ NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[ra->bwp_id - 1];
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1];
+
+ LOG_D(MAC, "[RAPROC] Scheduling common search space DCI type 1 dlBWP BW %d\n", dci10_bw);
+
+ // Qm>2 not allowed for RAR
+ if (get_softmodem_params()->do_ra)
+ mcsIndex = 9;
+ else
+ mcsIndex = 0;
+
+ pdsch_pdu_rel15->pduBitmap = 0;
+ pdsch_pdu_rel15->rnti = RA_rnti;
+ pdsch_pdu_rel15->pduIndex = 0;
+
+
+ pdsch_pdu_rel15->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
+ pdsch_pdu_rel15->CyclicPrefix = 0;
+ pdsch_pdu_rel15->NrOfCodewords = 1;
+ pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
+ pdsch_pdu_rel15->qamModOrder[0] = 2;
+ pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
+ if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == NULL)
+ pdsch_pdu_rel15->mcsTable[0] = 0;
+ else{
+ if (*bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == 0)
+ pdsch_pdu_rel15->mcsTable[0] = 1;
+ else
+ pdsch_pdu_rel15->mcsTable[0] = 2;
+ }
+ pdsch_pdu_rel15->rvIndex[0] = 0;
+ pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
+ pdsch_pdu_rel15->nrOfLayers = 1;
+ pdsch_pdu_rel15->transmissionScheme = 0;
+ pdsch_pdu_rel15->refPoint = 0;
+ pdsch_pdu_rel15->dmrsConfigType = 0;
+ pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
+ pdsch_pdu_rel15->SCID = 0;
+ pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 2;
+ pdsch_pdu_rel15->dmrsPorts = 1;
+ pdsch_pdu_rel15->resourceAlloc = 1;
+ pdsch_pdu_rel15->rbStart = 0;
+ pdsch_pdu_rel15->rbSize = 6;
+ pdsch_pdu_rel15->VRBtoPRBMapping = 0; // non interleaved
+
+ for (int i=0; i<bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) {
+ startSymbolAndLength = bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
+ SLIV2SL(startSymbolAndLength, &StartSymbolIndex_tmp, &NrOfSymbols_tmp);
+ if (NrOfSymbols_tmp < NrOfSymbols) {
+ NrOfSymbols = NrOfSymbols_tmp;
+ StartSymbolIndex = StartSymbolIndex_tmp;
+ time_domain_assignment = i; // this is short PDSCH added to the config to fit mixed slot
+ }
+ }
+
+ AssertFatal(StartSymbolIndex >= 0, "StartSymbolIndex is negative\n");
+
+ pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex;
+ pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
+ pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL, scc->dmrs_TypeA_Position, NrOfSymbols);
+
+ dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
+ dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
+ pdsch_pdu_rel15->rbStart,dci10_bw);
+ dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment;
+ dci_pdu_rel15[0].vrb_to_prb_mapping.val = 0;
+ dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
+ dci_pdu_rel15[0].tb_scaling = 0;
+
+ LOG_I(MAC, "[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d \n",
+ dci_pdu_rel15[0].frequency_domain_assignment.val,
+ pdsch_pdu_rel15->rbStart,
+ pdsch_pdu_rel15->rbSize,
+ dci10_bw,
+ dci_pdu_rel15[0].time_domain_assignment.val,
+ dci_pdu_rel15[0].vrb_to_prb_mapping.val,
+ dci_pdu_rel15[0].mcs,
+ dci_pdu_rel15[0].tb_scaling);
+
+ nr_configure_pdcch(nr_mac, pdcch_pdu_rel15, RA_rnti, 0, ss, scc, bwp);
+
+ LOG_I(MAC, "Frame %d: Subframe %d : Adding common DL DCI for RA_RNTI %x\n", frameP, slotP, RA_rnti);
+
+ dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
+ rnti_types[0] = NR_RNTI_RA;
+
+ LOG_D(MAC, "[RAPROC] DCI params: rnti %d, rnti_type %d, dci_format %d coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
+ pdcch_pdu_rel15->dci_pdu.RNTI[0],
+ rnti_types[0],
+ dci_formats[0],
+ (unsigned long long)pdcch_pdu_rel15->FreqDomainResource,
+ pdcch_pdu_rel15->StartSymbolIndex,
+ pdcch_pdu_rel15->DurationSymbols);
+
+ fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types,dci10_bw,ra->bwp_id);
+
+ dl_req->nPDUs+=2;
+
+ // Program UL processing for Msg3
+ nr_get_Msg3alloc(scc, ubwp, slotP, frameP, ra);
+ LOG_I(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot);
+ nr_add_msg3(module_idP, CC_id, frameP, slotP);
+ ra->state = WAIT_Msg3;
+ LOG_D(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
+
+ x_Overhead = 0;
+ nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_pdu_rel15[0].tb_scaling);
+
+ // DL TX request
+ tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0];
+ tx_req->PDU_index = nr_mac->pdu_index[CC_id]++;
+ tx_req->num_TLV = 1;
+ tx_req->TLVs[0].length = 8;
+ nr_mac->TX_req[CC_id].SFN = frameP;
+ nr_mac->TX_req[CC_id].Number_of_PDUs++;
+ nr_mac->TX_req[CC_id].Slot = slotP;
+ memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length);
+ }
+}
+
+void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP){
+ NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[CC_id].ra[0];
+ LOG_D(MAC,"[gNB %d][RAPROC] CC_id %d Frame %d Clear Random access information rnti %x\n", module_idP, CC_id, frameP, ra->rnti);
+ ra->state = IDLE;
+ ra->timing_offset = 0;
+ ra->RRC_timer = 20;
+ ra->rnti = 0;
+ ra->msg3_round = 0;
+}
+
+
+/////////////////////////////////////
+// Random Access Response PDU //
+// TS 38.213 ch 8.2 //
+// TS 38.321 ch 6.2.3 //
+/////////////////////////////////////
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise
+//| E | T | R A P I D |//
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |//
+//| R | T A |//
+//| T A | UL grant |//
+//| UL grant |//
+//| UL grant |//
+//| UL grant |//
+//| T C - R N T I |//
+//| T C - R N T I |//
+/////////////////////////////////////
+// UL grant (27 bits) //
+/////////////////////////////////////
+//| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |// bit-wise
+//|-------------------|FHF|F_alloc|//
+//| Freq allocation |//
+//| F_alloc |Time allocation|//
+//| MCS | TPC |CSI|//
+/////////////////////////////////////
+// WIP
+// todo:
+// - handle MAC RAR BI subheader
+// - sending only 1 RAR subPDU
+// - UL Grant: hardcoded CSI, TPC, time alloc
+// - padding
+void nr_fill_rar(uint8_t Mod_idP,
+ NR_RA_t * ra,
+ uint8_t * dlsch_buffer,
+ nfapi_nr_pusch_pdu_t *pusch_pdu){
+
+ LOG_D(MAC, "[gNB] Generate RAR MAC PDU frame %d slot %d ", ra->Msg2_frame, ra-> Msg2_slot);
+ NR_RA_HEADER_RAPID *rarh = (NR_RA_HEADER_RAPID *) dlsch_buffer;
+ NR_MAC_RAR *rar = (NR_MAC_RAR *) (dlsch_buffer + 1);
+ unsigned char csi_req = 0, tpc_command;
+ //uint8_t N_UL_Hop;
+ uint8_t valid_bits;
+ uint32_t ul_grant;
+ uint16_t f_alloc, prb_alloc, bwp_size, truncation=0;
+
+ tpc_command = 3; // this is 0 dB
+
+ /// E/T/RAPID subheader ///
+ // E = 0, one only RAR, first and last
+ // T = 1, RAPID
+ rarh->E = 0;
+ rarh->T = 1;
+ rarh->RAPID = ra->preamble_index;
+
+ /// RAR MAC payload ///
+ rar->R = 0;
+
+ // TA command
+ rar->TA1 = (uint8_t) (ra->timing_offset >> 5); // 7 MSBs of timing advance
+ rar->TA2 = (uint8_t) (ra->timing_offset & 0x1f); // 5 LSBs of timing advance
+
+ // TC-RNTI
+ rar->TCRNTI_1 = (uint8_t) (ra->rnti >> 8); // 8 MSBs of rnti
+ rar->TCRNTI_2 = (uint8_t) (ra->rnti & 0xff); // 8 LSBs of rnti
+
+ // UL grant
- for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
+ ra->msg3_TPC = tpc_command;
- for (i = 0; i < NB_RA_PROC_MAX; i++) {
+ bwp_size = pusch_pdu->bwp_size;
+ prb_alloc = PRBalloc_to_locationandbandwidth0(ra->msg3_nb_rb, ra->msg3_first_rb, bwp_size);
+ if (bwp_size>180) {
+ AssertFatal(1==0,"Initial UBWP larger than 180 currently not supported");
+ }
+ else {
+ valid_bits = (uint8_t)ceil(log2(bwp_size*(bwp_size+1)>>1));
+ }
- ra = (RA_t *) & cc[CC_id].ra[i];
- //LOG_D(MAC,"RA[state:%d]\n",ra->state);
+ if (pusch_pdu->frequency_hopping){
+ AssertFatal(1==0,"PUSCH with frequency hopping currently not supported");
+ } else {
+ for (int i=0; i<valid_bits; i++)
+ truncation |= (1<<i);
+ f_alloc = (prb_alloc&truncation);
+ }
- if (ra->state == MSG2)
- generate_Msg2(module_idP, CC_id, frameP, subframeP, ra);
- else if (ra->state == MSG4)
- generate_Msg4(module_idP, CC_id, frameP, subframeP, ra);
- else if (ra->state == WAITMSG4ACK)
- check_Msg4_retransmission(module_idP, CC_id, frameP, subframeP, ra);
+ ul_grant = csi_req | (tpc_command << 1) | (pusch_pdu->mcs_index << 4) | (ra->Msg3_tda_id << 8) | (f_alloc << 12) | (pusch_pdu->frequency_hopping << 26);
- } // for i=0 .. N_RA_PROC-1
- } // CC_id
+ rar->UL_GRANT_1 = (uint8_t) (ul_grant >> 24) & 0x07;
+ rar->UL_GRANT_2 = (uint8_t) (ul_grant >> 16) & 0xff;
+ rar->UL_GRANT_3 = (uint8_t) (ul_grant >> 8) & 0xff;
+ rar->UL_GRANT_4 = (uint8_t) ul_grant & 0xff;
- stop_meas(&mac->schedule_ra);
}
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
index 2a36425faef5d5275eaea61eb0b586a2ff5d6662..5fa77c6ca7a409534ef0f88b34e2c34fa013a657 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
@@ -31,9 +31,9 @@
*/
#include "assertions.h"
-#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_gNB/nr_mac_gNB.h"
+#include "NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "UTIL/OPT/opt.h"
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
index 52332701499d2868dc5c7c5cd13298439eb634d4..cf2323f5711574256739356ac3c48b4a8db8c9e5 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
@@ -34,9 +34,9 @@
#include "PHY/defs_nr_common.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
/*MAC*/
-#include "LAYER2/NR_MAC_COMMON/nr_mac.h"
-#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_COMMON/nr_mac.h"
+#include "NR_MAC_gNB/nr_mac_gNB.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
#include "LAYER2/MAC/mac.h"
/*NFAPI*/
@@ -44,6 +44,13 @@
/*TAG*/
#include "NR_TAG-Id.h"
+////////////////////////////////////////////////////////
+/////* DLSCH MAC PDU generation (6.1.2 TS 38.321) */////
+////////////////////////////////////////////////////////
+#define OCTET 8
+#define HALFWORD 16
+#define WORD 32
+//#define SIZE_OF_POINTER sizeof (void *)
int nr_generate_dlsch_pdu(module_id_t module_idP,
unsigned char *sdus_payload,
@@ -53,20 +60,23 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
unsigned char *sdu_lcids,
unsigned char drx_cmd,
unsigned char *ue_cont_res_id,
- unsigned short post_padding){
-
+ unsigned short post_padding) {
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
-
NR_MAC_SUBHEADER_FIXED *mac_pdu_ptr = (NR_MAC_SUBHEADER_FIXED *) mac_pdu;
- unsigned char * dlsch_buffer_ptr = sdus_payload;
+ unsigned char *dlsch_buffer_ptr = sdus_payload;
uint8_t last_size = 0;
int offset = 0, mac_ce_size, i, timing_advance_cmd, tag_id = 0;
-
- // MAC CEs
+ // MAC CEs
uint8_t mac_header_control_elements[16], *ce_ptr;
ce_ptr = &mac_header_control_elements[0];
+ uint16_t UE_id = 0; //TODO need to get as a function parameter or need to invoke api to UE_id using module Id and RNTI
+ gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
+ NR_UE_list_t *UE_list = &gNB_mac->UE_list;
+ NR_UE_sched_ctrl_t *ue_sched_ctl = NULL;
+ //NR_CellGroupConfig_t *config = UE_list->secondaryCellGroup[UE_id];
+ ue_sched_ctl = &(UE_list->UE_sched_ctrl[UE_id]);
- // 1) Compute MAC CE and related subheaders
+ // 1) Compute MAC CE and related subheaders
// DRX command subheader (MAC CE size 0)
if (drx_cmd != 255) {
@@ -81,57 +91,216 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
// now TA is always send when ta_timer resets regardless of its value
// this is done to avoid issues with the timeAlignmentTimer which is
// supposed to monitor if the UE received TA or not */
- if (gNB->ta_len){
+ if (gNB->ta_len) {
mac_pdu_ptr->R = 0;
mac_pdu_ptr->LCID = DL_SCH_LCID_TA_COMMAND;
//last_size = 1;
mac_pdu_ptr++;
-
// TA MAC CE (1 octet)
timing_advance_cmd = gNB->ta_command;
- AssertFatal(timing_advance_cmd < 64,"timing_advance_cmd %d > 63\n", timing_advance_cmd);
+ AssertFatal(timing_advance_cmd < 64, "timing_advance_cmd %d > 63\n", timing_advance_cmd);
((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND = timing_advance_cmd; //(timing_advance_cmd+31)&0x3f;
- if (gNB->tag->tag_Id != 0){
- tag_id = gNB->tag->tag_Id;
+
+ if (gNB->tag->tag_Id != 0) {
+ tag_id = gNB->tag->tag_Id;
((NR_MAC_CE_TA *) ce_ptr)->TAGID = tag_id;
}
LOG_D(MAC, "NR MAC CE timing advance command = %d (%d) TAG ID = %d\n", timing_advance_cmd, ((NR_MAC_CE_TA *) ce_ptr)->TA_COMMAND, tag_id);
mac_ce_size = sizeof(NR_MAC_CE_TA);
-
// Copying bytes for MAC CEs to the mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
ce_ptr += mac_ce_size;
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
-
// Contention resolution fixed subheader and MAC CE
if (ue_cont_res_id) {
mac_pdu_ptr->R = 0;
- mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID;
+ mac_pdu_ptr->LCID = DL_SCH_LCID_CON_RES_ID;
mac_pdu_ptr++;
//last_size = 1;
-
// contention resolution identity MAC ce has a fixed 48 bit size
- // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits,
+ // this contains the UL CCCH SDU. If UL CCCH SDU is longer than 48 bits,
// it contains the first 48 bits of the UL CCCH SDU
LOG_T(MAC, "[gNB ][RAPROC] Generate contention resolution msg: %x.%x.%x.%x.%x.%x\n",
- ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2],
- ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]);
-
+ ue_cont_res_id[0], ue_cont_res_id[1], ue_cont_res_id[2],
+ ue_cont_res_id[3], ue_cont_res_id[4], ue_cont_res_id[5]);
// Copying bytes (6 octects) to CEs pointer
mac_ce_size = 6;
memcpy(ce_ptr, ue_cont_res_id, mac_ce_size);
-
// Copying bytes for MAC CEs to mac pdu pointer
memcpy((void *) mac_pdu_ptr, (void *) ce_ptr, mac_ce_size);
ce_ptr += mac_ce_size;
mac_pdu_ptr += (unsigned char) mac_ce_size;
}
+ //TS 38.321 Sec 6.1.3.15 TCI State indication for UE Specific PDCCH MAC CE SubPDU generation
+ if (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.is_scheduled) {
+ //filling subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = DL_SCH_LCID_TCI_STATE_IND_UE_SPEC_PDCCH;
+ mac_pdu_ptr++;
+ //Creating the instance of CE structure
+ NR_TCI_PDCCH nr_UESpec_TCI_StateInd_PDCCH;
+ //filling the CE structre
+ nr_UESpec_TCI_StateInd_PDCCH.CoresetId1 = ((ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0xF) >> 1; //extracting MSB 3 bits from LS nibble
+ nr_UESpec_TCI_StateInd_PDCCH.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.servingCellId) & 0x1F; //extracting LSB 5 Bits
+ nr_UESpec_TCI_StateInd_PDCCH.TciStateId = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId) & 0x7F; //extracting LSB 7 bits
+ nr_UESpec_TCI_StateInd_PDCCH.CoresetId2 = (ue_sched_ctl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId) & 0x1; //extracting LSB 1 bit
+ LOG_D(MAC, "NR MAC CE TCI state indication for UE Specific PDCCH = %d \n", nr_UESpec_TCI_StateInd_PDCCH.TciStateId);
+ mac_ce_size = sizeof(NR_TCI_PDCCH);
+ // Copying bytes for MAC CEs to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *)&nr_UESpec_TCI_StateInd_PDCCH, mac_ce_size);
+ //incrementing the PDU pointer
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ //TS 38.321 Sec 6.1.3.16, SP CSI reporting on PUCCH Activation/Deactivation MAC CE
+ if (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.is_scheduled) {
+ //filling the subheader
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_REP_PUCCH_ACT;
+ mac_pdu_ptr++;
+ //creating the instance of CE structure
+ NR_PUCCH_CSI_REPORTING nr_PUCCH_CSI_reportingActDeact;
+ //filling the CE structure
+ nr_PUCCH_CSI_reportingActDeact.BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.bwpId) & 0x3; //extracting LSB 2 bibs
+ nr_PUCCH_CSI_reportingActDeact.ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.servingCellId) & 0x1F; //extracting LSB 5 bits
+ nr_PUCCH_CSI_reportingActDeact.S0 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[0];
+ nr_PUCCH_CSI_reportingActDeact.S1 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[1];
+ nr_PUCCH_CSI_reportingActDeact.S2 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[2];
+ nr_PUCCH_CSI_reportingActDeact.S3 = ue_sched_ctl->UE_mac_ce_ctrl.SP_CSI_reporting_pucch.s0tos3_actDeact[3];
+ nr_PUCCH_CSI_reportingActDeact.R2 = 0;
+ mac_ce_size = sizeof(NR_PUCCH_CSI_REPORTING);
+ // Copying MAC CE data to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *)&nr_PUCCH_CSI_reportingActDeact, mac_ce_size);
+ //incrementing the PDU pointer
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ //TS 38.321 Sec 6.1.3.14, TCI State activation/deactivation for UE Specific PDSCH MAC CE
+ if (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.is_scheduled) {
+ //Computing the number of octects to be allocated for Flexible array member
+ //of MAC CE structure
+ uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.highestTciStateActivated) / 8 + 1; //Calculating the number of octects for allocating the memory
+ //filling the subheader
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_TCI_STATE_ACT_UE_SPEC_PDSCH;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+ last_size = 2;
+ //Incrementing the PDU pointer
+ mac_pdu_ptr += last_size;
+ //allocating memory for CE Structure
+ NR_TCI_PDSCH_APERIODIC_CSI *nr_UESpec_TCI_StateInd_PDSCH = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+ //initializing to zero
+ memset((void *)nr_UESpec_TCI_StateInd_PDSCH, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+ //filling the CE Structure
+ nr_UESpec_TCI_StateInd_PDSCH->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.bwpId) & 0x3; //extracting LSB 2 Bits
+ nr_UESpec_TCI_StateInd_PDSCH->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.servingCellId) & 0x1F; //extracting LSB 5 bits
+
+ for(i = 0; i < (num_octects * 8); i++) {
+ if(ue_sched_ctl->UE_mac_ce_ctrl.pdsch_TCI_States_ActDeact.tciStateActDeact[i])
+ nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] = nr_UESpec_TCI_StateInd_PDSCH->T[i / 8] | (1 << (i % 8));
+ }
+
+ mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+ //Copying bytes for MAC CEs to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *)nr_UESpec_TCI_StateInd_PDSCH, mac_ce_size);
+ //incrementing the mac pdu pointer
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ //freeing the allocated memory
+ free(nr_UESpec_TCI_StateInd_PDSCH);
+ }
+
+ //TS38.321 Sec 6.1.3.13 Aperiodic CSI Trigger State Subselection MAC CE
+ if (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.is_scheduled) {
+ //Computing the number of octects to be allocated for Flexible array member
+ //of MAC CE structure
+ uint8_t num_octects = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.highestTriggerStateSelected) / 8 + 1; //Calculating the number of octects for allocating the memory
+ //filling the subheader
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->F = 0;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->LCID = DL_SCH_LCID_APERIODIC_CSI_TRI_STATE_SUBSEL;
+ ((NR_MAC_SUBHEADER_SHORT *) mac_pdu_ptr)->L = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+ last_size = 2;
+ //Incrementing the PDU pointer
+ mac_pdu_ptr += last_size;
+ //allocating memory for CE structure
+ NR_TCI_PDSCH_APERIODIC_CSI *nr_Aperiodic_CSI_Trigger = (NR_TCI_PDSCH_APERIODIC_CSI *)malloc(sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+ //initializing to zero
+ memset((void *)nr_Aperiodic_CSI_Trigger, 0, sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t));
+ //filling the CE Structure
+ nr_Aperiodic_CSI_Trigger->BWP_Id = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.bwpId) & 0x3; //extracting LSB 2 bits
+ nr_Aperiodic_CSI_Trigger->ServingCellId = (ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.servingCellId) & 0x1F; //extracting LSB 5 bits
+ nr_Aperiodic_CSI_Trigger->R = 0;
+
+ for(i = 0; i < (num_octects * 8); i++) {
+ if(ue_sched_ctl->UE_mac_ce_ctrl.aperi_CSI_trigger.triggerStateSelection[i])
+ nr_Aperiodic_CSI_Trigger->T[i / 8] = nr_Aperiodic_CSI_Trigger->T[i / 8] | (1 << (i % 8));
+ }
+
+ mac_ce_size = sizeof(NR_TCI_PDSCH_APERIODIC_CSI) + num_octects * sizeof(uint8_t);
+ // Copying bytes for MAC CEs to the mac pdu pointer
+ memcpy((void *) mac_pdu_ptr, (void *)nr_Aperiodic_CSI_Trigger, mac_ce_size);
+ //incrementing the mac pdu pointer
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ //freeing the allocated memory
+ free(nr_Aperiodic_CSI_Trigger);
+ }
- // 2) Generation of DLSCH MAC SDU subheaders
+ if (ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.is_scheduled) {
+ ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
+ ((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_SP_ZP_CSI_RS_RES_SET_ACT;
+ mac_pdu_ptr++;
+ ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->A_D = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.act_deact;
+ ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CELLID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id & 0x1F; //5 bits
+ ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->BWPID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid & 0x3; //2 bits
+ ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->CSIRS_RSC_ID = ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id & 0xF; //4 bits
+ ((NR_MAC_CE_SP_ZP_CSI_RS_RES_SET *) mac_pdu_ptr)->R = 0;
+ LOG_D(MAC, "NR MAC CE of ZP CSIRS Serv cell ID = %d BWPID= %d Rsc set ID = %d\n", ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.serv_cell_id, ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.bwpid,
+ ue_sched_ctl->UE_mac_ce_ctrl.sp_zp_csi_rs.rsc_id);
+ mac_ce_size = sizeof(NR_MAC_CE_SP_ZP_CSI_RS_RES_SET);
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+
+ if (ue_sched_ctl->UE_mac_ce_ctrl.csi_im.is_scheduled) {
+ mac_pdu_ptr->R = 0;
+ mac_pdu_ptr->LCID = DL_SCH_LCID_SP_CSI_RS_CSI_IM_RES_SET_ACT;
+ mac_pdu_ptr++;
+ CSI_RS_CSI_IM_ACT_DEACT_MAC_CE csi_rs_im_act_deact_ce;
+ csi_rs_im_act_deact_ce.A_D = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.act_deact;
+ csi_rs_im_act_deact_ce.SCID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.serv_cellid & 0x3F;//gNB_PHY -> ssb_pdu.ssb_pdu_rel15.PhysCellId;
+ csi_rs_im_act_deact_ce.BWP_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.bwp_id;
+ csi_rs_im_act_deact_ce.R1 = 0;
+ csi_rs_im_act_deact_ce.IM = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.im;// IF set CSI IM Rsc id will presesent else CSI IM RSC ID is abscent
+ csi_rs_im_act_deact_ce.SP_CSI_RSID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nzp_csi_rsc_id;
+
+ if ( csi_rs_im_act_deact_ce.IM ) { //is_scheduled if IM is 1 else this field will not present
+ csi_rs_im_act_deact_ce.R2 = 0;
+ csi_rs_im_act_deact_ce.SP_CSI_IMID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.csi_im_rsc_id;
+ mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE );
+ } else {
+ mac_ce_size = sizeof ( csi_rs_im_act_deact_ce ) - sizeof ( csi_rs_im_act_deact_ce.TCI_STATE ) - 1;
+ }
+
+ memcpy ((void *) mac_pdu_ptr, (void *) & ( csi_rs_im_act_deact_ce), mac_ce_size);
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+
+ if (csi_rs_im_act_deact_ce.A_D ) { //Following IE is_scheduled only if A/D is 1
+ mac_ce_size = sizeof ( struct TCI_S);
+
+ for ( i = 0; i < ue_sched_ctl->UE_mac_ce_ctrl.csi_im.nb_tci_resource_set_id; i++) {
+ csi_rs_im_act_deact_ce.TCI_STATE.R = 0;
+ csi_rs_im_act_deact_ce.TCI_STATE.TCI_STATE_ID = ue_sched_ctl->UE_mac_ce_ctrl.csi_im.tci_state_id [i] & 0x7F;
+ memcpy ((void *) mac_pdu_ptr, (void *) & (csi_rs_im_act_deact_ce.TCI_STATE), mac_ce_size);
+ mac_pdu_ptr += (unsigned char) mac_ce_size;
+ }
+ }
+ }
+
+ // 2) Generation of DLSCH MAC subPDUs including subheaders and MAC SDUs
for (i = 0; i < num_sdus; i++) {
LOG_D(MAC, "[gNB] Generate DLSCH header num sdu %d len sdu %d\n", num_sdus, sdu_lengths[i]);
@@ -151,31 +320,27 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
}
mac_pdu_ptr += last_size;
-
- // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
+ // 3) cycle through SDUs, compute each relevant and place dlsch_buffer in
memcpy((void *) mac_pdu_ptr, (void *) dlsch_buffer_ptr, sdu_lengths[i]);
- dlsch_buffer_ptr+= sdu_lengths[i];
+ dlsch_buffer_ptr += sdu_lengths[i];
mac_pdu_ptr += sdu_lengths[i];
}
// 4) Compute final offset for padding
- if (post_padding > 0) {
+ if (post_padding > 0) {
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->R = 0;
((NR_MAC_SUBHEADER_FIXED *) mac_pdu_ptr)->LCID = DL_SCH_LCID_PADDING;
mac_pdu_ptr++;
-
- } else {
+ } else {
// no MAC subPDU with padding
}
// compute final offset
offset = ((unsigned char *) mac_pdu_ptr - mac_pdu);
-
//printf("Offset %d \n", ((unsigned char *) mac_pdu_ptr - mac_pdu));
-
return offset;
}
/* functionalities of this function have been moved to nr_schedule_uss_dlsch_phytest */
-void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP){
+void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slotP) {
}
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
index 6aba6e7e63c401bbdd521d7e62c261c6b3687837..9f5d4f5ec747cd4a7dd1535ede8fcb180ffb5a8a 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
@@ -30,8 +30,8 @@
#include "nr_mac_gNB.h"
#include "SCHED_NR/sched_nr.h"
-#include "mac_proto.h"
-#include "nr_mac_common.h"
+#include "NR_MAC_gNB/mac_proto.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_TRANSPORT/nr_dci.h"
#include "executables/nr-softmodem.h"
@@ -249,23 +249,28 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
}
}
+
int configure_fapi_dl_pdu(int Mod_idP,
- int *CCEIndex,
nfapi_nr_dl_tti_request_body_t *dl_req,
+ NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
uint16_t *rbSize,
uint16_t *rbStart) {
+
gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
-
+
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu;
- int TBS, bwp_id = 1, UE_id = 0;
- NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
+ int TBS;
+ int bwp_id=1;
+ int UE_id = 0;
+
+ NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
@@ -273,6 +278,9 @@ int configure_fapi_dl_pdu(int Mod_idP,
secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
+ "searchPsacesToAddModList is empty\n");
dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
@@ -301,11 +309,12 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdsch_pdu_rel15->NrOfCodewords = 1;
int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9;
+ int current_harq_pid = UE_list->UE_sched_ctrl[UE_id].current_harq_pid;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcs;
pdsch_pdu_rel15->mcsTable[0] = 0;
- pdsch_pdu_rel15->rvIndex[0] = 0;
+ pdsch_pdu_rel15->rvIndex[0] = (get_softmodem_params()->phy_test==1) ? 0 : UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
pdsch_pdu_rel15->nrOfLayers = 1;
pdsch_pdu_rel15->transmissionScheme = 0;
@@ -320,7 +329,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0;
pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize;
pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP
- // choose shortest PDSCH
+
int startSymbolAndLength=0;
int time_domain_assignment=2;
int StartSymbolIndex,NrOfSymbols;
@@ -336,62 +345,104 @@ int configure_fapi_dl_pdu(int Mod_idP,
scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols);
- dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
+ dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t));
- dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
- pdsch_pdu_rel15->rbStart,
- NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
- dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
- dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
+ // bwp indicator
+ int n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
+ if (n_dl_bwp < 4)
+ dci_pdu_rel15[0].bwp_indicator.val = bwp_id;
+ else
+ dci_pdu_rel15[0].bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212
+ // frequency domain assignment
+ if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation==NR_PDSCH_Config__resourceAllocation_resourceAllocationType1)
+ dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
+ pdsch_pdu_rel15->rbStart,
+ NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
+ else
+ AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n");
+ // time domain assignment
+ dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
+ // mcs and rv
dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
- dci_pdu_rel15[0].tb_scaling = 1;
-
- dci_pdu_rel15[0].ra_preamble_index = 25;
- dci_pdu_rel15[0].format_indicator = 1;
- dci_pdu_rel15[0].ndi = 1;
- dci_pdu_rel15[0].rv = 0;
- dci_pdu_rel15[0].harq_pid = 0;
- dci_pdu_rel15[0].dai = 2;
- dci_pdu_rel15[0].tpc = 2;
- dci_pdu_rel15[0].pucch_resource_indicator = 7;
- dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7;
-
+ dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0];
+ // harq pid and ndi
+ dci_pdu_rel15[0].harq_pid = current_harq_pid;
+ dci_pdu_rel15[0].ndi = UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].ndi;
+ // DAI
+ dci_pdu_rel15[0].dai[0].val = (pucch_sched->dai_c-1)&3;
+
+ // TPC for PUCCH
+ dci_pdu_rel15[0].tpc = 1; // table 7.2.1-1 in 38.213
+ // PUCCH resource indicator
+ dci_pdu_rel15[0].pucch_resource_indicator = pucch_sched->resource_indicator;
+ // PDSCH to HARQ TI
+ dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = pucch_sched->timing_indicator;
+ UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].feedback_slot = pucch_sched->ul_slot;
+ UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].is_waiting = 1;
+ // antenna ports
+ dci_pdu_rel15[0].antenna_ports.val = 0; // nb of cdm groups w/o data 1 and dmrs port 0
+ // dmrs sequence initialization
+ dci_pdu_rel15[0].dmrs_sequence_initialization.val = pdsch_pdu_rel15->SCID;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
- dci_pdu_rel15[0].frequency_domain_assignment,
+ dci_pdu_rel15[0].frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
- dci_pdu_rel15[0].time_domain_assignment,
- dci_pdu_rel15[0].vrb_to_prb_mapping,
+ dci_pdu_rel15[0].time_domain_assignment.val,
+ dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs,
dci_pdu_rel15[0].tb_scaling,
dci_pdu_rel15[0].ndi,
dci_pdu_rel15[0].rv);
-
- nr_configure_pdcch(pdcch_pdu_rel15,
- 1, // ue-specific
- scc,
- bwp);
-
- pdcch_pdu_rel15->numDlDci = 1;
- pdcch_pdu_rel15->AggregationLevel[0] = 4;
- pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0];
- pdcch_pdu_rel15->CceIndex[0] = CCEIndex[0];
- pdcch_pdu_rel15->beta_PDCCH_1_0[0]=0;
- pdcch_pdu_rel15->powerControlOffsetSS[0]=1;
-
+
+ NR_SearchSpace_t *ss;
+ int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
+
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
+ "searchPsacesToAddModList is empty\n");
+
+ int found=0;
+
+ for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
+ ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
+ AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
+ AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
+ if (ss->searchSpaceType->present == target_ss) {
+ found=1;
+ break;
+ }
+ }
+ AssertFatal(found==1,"Couldn't find an adequate searchspace\n");
+
+ int ret = nr_configure_pdcch(nr_mac,
+ pdcch_pdu_rel15,
+ UE_list->rnti[UE_id],
+ 1, // ue-specific
+ ss,
+ scc,
+ bwp);
+ if (ret < 0) {
+ LOG_I(MAC,"CCE list not empty, couldn't schedule PDSCH\n");
+ free(dci_pdu_rel15);
+ return (0);
+ }
+
int dci_formats[2];
int rnti_types[2];
- dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
+ if (ss->searchSpaceType->choice.ue_Specific->dci_Formats)
+ dci_formats[0] = NR_DL_DCI_FORMAT_1_1;
+ else
+ dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
+
rnti_types[0] = NR_RNTI_C;
- pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
- fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
+ fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pdsch_pdu_rel15->BWPSize,bwp_id);
- LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
+ LOG_D(MAC, "DCI params: rnti %x, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
- pdcch_pdu_rel15->RNTI[0],
+ pdcch_pdu_rel15->dci_pdu.RNTI[0],
rnti_types[0],
dci_formats[0],
(unsigned long long)pdcch_pdu_rel15->FreqDomainResource,
@@ -399,7 +450,7 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdcch_pdu_rel15->DurationSymbols);
int x_Overhead = 0; // should be 0 for initialBWP
- nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead);
+ nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu,x_Overhead,pdsch_pdu_rel15->numDmrsCdmGrpsNoData,0);
// Hardcode it for now
TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0];
@@ -414,38 +465,83 @@ int configure_fapi_dl_pdu(int Mod_idP,
pdsch_pdu_rel15->mcsIndex[0],
TBS);
+ free(dci_pdu_rel15);
return TBS; //Return TBS in bytes
}
-void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
-
- dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
- pusch_pdu->rb_start,
- NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
+void config_uldci(NR_BWP_Uplink_t *ubwp,
+ nfapi_nr_pusch_pdu_t *pusch_pdu,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
+ dci_pdu_rel15_t *dci_pdu_rel15,
+ int *dci_formats, int *rnti_types,
+ int time_domain_assignment,
+ int n_ubwp, int bwp_id) {
+
+ switch(dci_formats[(pdcch_pdu_rel15->numDlDci)-1]) {
+ case NR_UL_DCI_FORMAT_0_0:
+ dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
+ pusch_pdu->rb_start,
+ NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
+
+ dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
+ dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
+ dci_pdu_rel15->mcs = 9;
+
+ dci_pdu_rel15->format_indicator = 0;
+ dci_pdu_rel15->ndi = 1;
+ dci_pdu_rel15->rv = 0;
+ dci_pdu_rel15->harq_pid = 0;
+ dci_pdu_rel15->tpc = 2;
+ break;
+ case NR_UL_DCI_FORMAT_0_1:
+ dci_pdu_rel15->ndi = pusch_pdu->pusch_data.new_data_indicator;
+ dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index;
+ dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id;
+ dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
+ dci_pdu_rel15->dai[0].val = 0; //TODO
+ // bwp indicator
+ if (n_ubwp < 4)
+ dci_pdu_rel15->bwp_indicator.val = bwp_id;
+ else
+ dci_pdu_rel15->bwp_indicator.val = bwp_id - 1; // as per table 7.3.1.1.2-1 in 38.212
+ // frequency domain assignment
+ if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1)
+ dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
+ pusch_pdu->rb_start,
+ NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
+ else
+ AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n");
+ // time domain assignment
+ dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
+ // mcs
+ dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
+ // tpc command for pusch
+ dci_pdu_rel15->tpc = 2; //TODO
+ // SRS resource indicator
+ if (ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig != NULL) {
+ if (*ubwp->bwp_Dedicated->pusch_Config->choice.setup->txConfig == NR_PUSCH_Config__txConfig_codebook)
+ dci_pdu_rel15->srs_resource_indicator.val = 0; // taking resource 0 for SRS
+ else
+ AssertFatal(1==0,"Non Codebook configuration non supported\n");
+ }
+ // Antenna Ports
+ dci_pdu_rel15->antenna_ports.val = 0; // TODO for now it is hardcoded, it should depends on cdm group no data and rank
+ // DMRS sequence initialization
+ dci_pdu_rel15->dmrs_sequence_initialization.val = pusch_pdu->scid;
+ break;
+ default :
+ AssertFatal(1==0,"Valid UL formats are 0_0 and 0_1 \n");
+ }
- dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
- dci_pdu_rel15->frequency_hopping_flag = 0;
- dci_pdu_rel15->mcs = 9;
-
- dci_pdu_rel15->format_indicator = 0;
- dci_pdu_rel15->ndi = 1;
- dci_pdu_rel15->rv = 0;
- dci_pdu_rel15->harq_pid = 0;
- dci_pdu_rel15->tpc = 2;
-
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
- pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
- dci_pdu_rel15->frequency_domain_assignment,
- dci_pdu_rel15->time_domain_assignment,
- dci_pdu_rel15->frequency_hopping_flag,
+ pdcch_pdu_rel15->dci_pdu.CceIndex[pdcch_pdu_rel15->numDlDci],
+ dci_pdu_rel15->frequency_domain_assignment.val,
+ dci_pdu_rel15->time_domain_assignment.val,
+ dci_pdu_rel15->frequency_hopping_flag.val,
dci_pdu_rel15->mcs,
dci_pdu_rel15->tpc,
dci_pdu_rel15->ndi,
dci_pdu_rel15->rv);
-
- dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0;
- rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C;
- pdcch_pdu_rel15->numDlDci++;
}
@@ -481,7 +577,7 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP,
tx_req->num_TLV = 1;
tx_req->TLVs[0].length = tbs_bytes +2;
- memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes);;
+ memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&nr_mac->UE_list.DLSCH_pdu[0][0].payload[0], tbs_bytes);
nr_mac->TX_req[CC_id].Number_of_PDUs++;
nr_mac->TX_req[CC_id].SFN = frameP;
@@ -491,13 +587,14 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP,
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP,
+ NR_sched_pucch *pucch_sched,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config){
- LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n");
+ LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest frame %d slot %d\n",frameP,slotP);
int post_padding = 0, ta_len = 0, header_length_total = 0, sdu_length_total = 0, num_sdus = 0;
int lcid, offset, i, header_length_last, TBS_bytes;
- int UE_id = 0, CCEIndex = -1, CC_id = 0;
+ int UE_id = 0, CC_id = 0;
gNB_MAC_INST *gNB_mac = RC.nrmac[module_idP];
//NR_COMMON_channels_t *cc = nr_mac->common_channels;
@@ -521,26 +618,15 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
ta_len = gNB_mac->ta_len;
- CCEIndex = allocate_nr_CCEs(gNB_mac,
- 1, // bwp_id
- 0, // coreset_id
- 4, // aggregation,
- 1, // search_space, 0 common, 1 ue-specific
- UE_id,
- 0); // m
-
- if (CCEIndex == -1) return;
-
- AssertFatal(CCEIndex>0,"CCEIndex is negative\n");
- int CCEIndices[2];
- CCEIndices[0] = CCEIndex;
-
TBS_bytes = configure_fapi_dl_pdu(module_idP,
- CCEIndices,
- dl_req,
+ dl_req,
+ pucch_sched,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
+
+ if (TBS_bytes == 0)
+ return;
//The --NOS1 use case currently schedules DLSCH transmissions only when there is IP traffic arriving
//through the LTE stack
@@ -609,13 +695,12 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
// fill dlsch_buffer with random data
for (i = 0; i < TBS_bytes; i++){
- //mac_sdus[i] = (unsigned char) rand();
- ((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff);
+ mac_sdus[i] = (unsigned char) (lrand48()&0xff);
+ //((uint8_t *)gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) (lrand48()&0xff);
}
-
//Sending SDUs with size 1
//Initialize elements of sdu_lcids and sdu_lengths
- sdu_lcids[0] = 0x05; // DRB
+ sdu_lcids[0] = 0x3f; // DRB
sdu_lengths[0] = TBS_bytes - ta_len - 3;
header_length_total += 2 + (sdu_lengths[0] >= 128);
sdu_length_total += sdu_lengths[0];
@@ -649,7 +734,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
offset = nr_generate_dlsch_pdu(module_idP,
(unsigned char *) mac_sdus,
- (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0], //(unsigned char *) mac_pdu,
+ (unsigned char *) gNB_mac->UE_list.DLSCH_pdu[0][0].payload[0],
num_sdus, //num_sdus
sdu_lengths,
sdu_lcids,
@@ -698,7 +783,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int bwp_id=1;
-
+ int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
int UE_id = 0;
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id);
@@ -708,38 +793,51 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
"downlinkBWP_ToAddModList has %d BWP!\n",
secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
+ int n_ubwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.count;
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+ NR_PUSCH_Config_t *pusch_Config = ubwp->bwp_Dedicated->pusch_Config->choice.setup;
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
nfapi_nr_ul_dci_request_t *UL_dci_req = &RC.nrmac[Mod_idP]->UL_dci_req[0];
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
+ "searchPsacesToAddModList is empty\n");
uint16_t rnti = UE_list->rnti[UE_id];
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu;
UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP;
- UL_tti_req->n_pdus = 1;
- UL_tti_req->pdus_list[0].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
- UL_tti_req->pdus_list[0].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
- nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
+ UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
+ nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t));
-
+ UL_tti_req->n_pdus+=1;
+
LOG_D(MAC, "Scheduling UE specific PUSCH\n");
//UL_tti_req = &nr_mac->UL_tti_req[CC_id];
- /*
- // original configuration
- rel15_ul->rnti = 0x1234;
- rel15_ul->ulsch_pdu_rel15.start_rb = 30;
- rel15_ul->ulsch_pdu_rel15.number_rbs = 50;
- rel15_ul->ulsch_pdu_rel15.start_symbol = 2;
- rel15_ul->ulsch_pdu_rel15.number_symbols = 12;
- rel15_ul->ulsch_pdu_rel15.nb_re_dmrs = 6;
- rel15_ul->ulsch_pdu_rel15.length_dmrs = 1;
- rel15_ul->ulsch_pdu_rel15.Qm = 2;
- rel15_ul->ulsch_pdu_rel15.mcs = 9;
- rel15_ul->ulsch_pdu_rel15.rv = 0;
- rel15_ul->ulsch_pdu_rel15.n_layers = 1;
- */
+
+ //Resource Allocation in time domain
+ int startSymbolAndLength=0;
+ int time_domain_assignment=1;
+ int StartSymbolIndex,NrOfSymbols,K2,mapping_type;
+
+ AssertFatal(time_domain_assignment<ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count,
+ "time_domain_assignment %d>=%d\n",time_domain_assignment,ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count);
+ startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
+ SLIV2SL(startSymbolAndLength,&StartSymbolIndex,&NrOfSymbols);
+ pusch_pdu->start_symbol_index = StartSymbolIndex;
+ pusch_pdu->nr_of_symbols = NrOfSymbols;
+
+ mapping_type = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->mappingType;
+ if (ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2 != NULL)
+ K2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[time_domain_assignment]->k2;
+ else {
+ if (mu<2) K2=1;
+ else if(mu==2) K2=2;
+ else K2=3;
+ }
+
pusch_pdu->pdu_bit_map = PUSCH_PDU_BITMAP_PUSCH_DATA;
pusch_pdu->rnti = rnti;
pusch_pdu->handle = 0; //not yet used
@@ -754,39 +852,146 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
pusch_pdu->mcs_table = 0; //0: notqam256 [TS38.214, table 5.1.3.1-1] - corresponds to nr_target_code_rate_table1 in PHY
pusch_pdu->target_code_rate = nr_get_code_rate_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ;
pusch_pdu->qam_mod_order = nr_get_Qm_ul(pusch_pdu->mcs_index,pusch_pdu->mcs_table) ;
- pusch_pdu->transform_precoding = 0;
- pusch_pdu->data_scrambling_id = 0; //It equals the higher-layer parameter Data-scrambling-Identity if configured and the RNTI equals the C-RNTI, otherwise L2 needs to set it to physical cell id.;
+ if (pusch_Config->transformPrecoder == NULL) {
+ if (scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->msg3_transformPrecoder == NULL)
+ pusch_pdu->transform_precoding = 1;
+ else
+ pusch_pdu->transform_precoding = 0;
+ }
+ else
+ pusch_pdu->transform_precoding = *pusch_Config->transformPrecoder;
+ if (pusch_Config->dataScramblingIdentityPUSCH != NULL)
+ pusch_pdu->data_scrambling_id = *pusch_Config->dataScramblingIdentityPUSCH;
+ else
+ pusch_pdu->data_scrambling_id = *scc->physCellId;
+
pusch_pdu->nrOfLayers = 1;
- //DMRS
- pusch_pdu->ul_dmrs_symb_pos = 1<<2; //for now the gnb assumes dmrs in the first symbol of the scheduled pusch resource
- pusch_pdu->dmrs_config_type = 0; //dmrs-type 1 (the one with a single DMRS symbol in the beginning)
- pusch_pdu->ul_dmrs_scrambling_id = 0; //If provided and the PUSCH is not a msg3 PUSCH, otherwise, L2 should set this to physical cell id.
- pusch_pdu->scid = 0; //DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]. Should match what is sent in DCI 0_1, otherwise set to 0.
- //pusch_pdu->num_dmrs_cdm_grps_no_data;
- //pusch_pdu->dmrs_ports; //DMRS ports. [TS38.212 7.3.1.1.2] provides description between DCI 0-1 content and DMRS ports. Bitmap occupying the 11 LSBs with: bit 0: antenna port 1000 bit 11: antenna port 1011 and for each bit 0: DMRS port not used 1: DMRS port used
+
//Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
- pusch_pdu->resource_alloc = 1; //type 1
- //pusch_pdu->rb_bitmap;// for ressource alloc type 0
- pusch_pdu->rb_start = 0;
- pusch_pdu->rb_size = 50;
+ if (pusch_Config->resourceAllocation==NR_PUSCH_Config__resourceAllocation_resourceAllocationType1) {
+ pusch_pdu->resource_alloc = 1; //type 1
+ pusch_pdu->rb_start = 0;
+ pusch_pdu->rb_size = 50;
+ }
+ else
+ AssertFatal(1==0,"Only frequency resource allocation type 1 is currently supported\n");
+
pusch_pdu->vrb_to_prb_mapping = 0;
- pusch_pdu->frequency_hopping = 0;
+
+ if (pusch_Config->frequencyHopping==NULL)
+ pusch_pdu->frequency_hopping = 0;
+ else
+ pusch_pdu->frequency_hopping = 1;
+
//pusch_pdu->tx_direct_current_location;//The uplink Tx Direct Current location for the carrier. Only values in the value range of this field between 0 and 3299, which indicate the subcarrier index within the carrier corresponding 1o the numerology of the corresponding uplink BWP and value 3300, which indicates "Outside the carrier" and value 3301, which indicates "Undetermined position within the carrier" are used. [TS38.331, UplinkTxDirectCurrentBWP IE]
- pusch_pdu->uplink_frequency_shift_7p5khz = 0;
- //Resource Allocation in time domain
- pusch_pdu->start_symbol_index = 2;
- pusch_pdu->nr_of_symbols = 12;
+ //pusch_pdu->uplink_frequency_shift_7p5khz = 0;
+
+
+ // --------------------
+ // ------- DMRS -------
+ // --------------------
+ NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig;
+ if (mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA)
+ NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup;
+ else
+ NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup;
+ if (NR_DMRS_UplinkConfig->dmrs_Type == NULL)
+ pusch_pdu->dmrs_config_type = 0;
+ else
+ pusch_pdu->dmrs_config_type = 1;
+ pusch_pdu->scid = 0; // DMRS sequence initialization [TS38.211, sec 6.4.1.1.1]
+ if (pusch_pdu->transform_precoding) { // transform precoding disabled
+ long *scramblingid;
+ if (pusch_pdu->scid == 0)
+ scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID0;
+ else
+ scramblingid = NR_DMRS_UplinkConfig->transformPrecodingDisabled->scramblingID1;
+ if (scramblingid == NULL)
+ pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
+ else
+ pusch_pdu->ul_dmrs_scrambling_id = *scramblingid;
+ }
+ else {
+ pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
+ if (NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity != NULL)
+ pusch_pdu->pusch_identity = *NR_DMRS_UplinkConfig->transformPrecodingEnabled->nPUSCH_Identity;
+ else
+ pusch_pdu->pusch_identity = *scc->physCellId;
+ }
+ pusch_dmrs_AdditionalPosition_t additional_pos;
+ if (NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL)
+ additional_pos = 2;
+ else {
+ if (*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos3)
+ additional_pos = 3;
+ else
+ additional_pos = *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition;
+ }
+ pusch_maxLength_t pusch_maxLength;
+ if (NR_DMRS_UplinkConfig->maxLength == NULL)
+ pusch_maxLength = 1;
+ else
+ pusch_maxLength = 2;
+ uint16_t l_prime_mask = get_l_prime(pusch_pdu->nr_of_symbols, mapping_type, additional_pos, pusch_maxLength);
+ pusch_pdu->ul_dmrs_symb_pos = l_prime_mask << pusch_pdu->start_symbol_index;
+
+ pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
+ pusch_pdu->dmrs_ports = 1;
+ // --------------------------------------------------------------------------------------------------------------------------------------------
+
+ // --------------------
+ // ------- PTRS -------
+ // --------------------
+ if (NR_DMRS_UplinkConfig->phaseTrackingRS != NULL) {
+ // TODO to be fixed from RRC config
+ uint8_t ptrs_mcs1 = 2; // higher layer parameter in PTRS-UplinkConfig
+ uint8_t ptrs_mcs2 = 4; // higher layer parameter in PTRS-UplinkConfig
+ uint8_t ptrs_mcs3 = 10; // higher layer parameter in PTRS-UplinkConfig
+ uint16_t n_rb0 = 25; // higher layer parameter in PTRS-UplinkConfig
+ uint16_t n_rb1 = 75; // higher layer parameter in PTRS-UplinkConfig
+ pusch_pdu->pusch_ptrs.ptrs_time_density = get_L_ptrs(ptrs_mcs1, ptrs_mcs2, ptrs_mcs3, pusch_pdu->mcs_index, pusch_pdu->mcs_table);
+ pusch_pdu->pusch_ptrs.ptrs_freq_density = get_K_ptrs(n_rb0, n_rb1, pusch_pdu->rb_size);
+ pusch_pdu->pusch_ptrs.ptrs_ports_list = (nfapi_nr_ptrs_ports_t *) malloc(2*sizeof(nfapi_nr_ptrs_ports_t));
+ pusch_pdu->pusch_ptrs.ptrs_ports_list[0].ptrs_re_offset = 0;
+
+ pusch_pdu->pdu_bit_map |= PUSCH_PDU_BITMAP_PUSCH_PTRS; // enable PUSCH PTRS
+ }
+ else{
+ pusch_pdu->pdu_bit_map &= ~PUSCH_PDU_BITMAP_PUSCH_PTRS; // disable PUSCH PTRS
+ }
+
+ // --------------------------------------------------------------------------------------------------------------------------------------------
+
+ //Pusch Allocation in frequency domain [TS38.214, sec 6.1.2.2]
//Optional Data only included if indicated in pduBitmap
+ // TODO from harq function as in pdsch
pusch_pdu->pusch_data.rv_index = 0;
pusch_pdu->pusch_data.harq_process_id = 0;
- pusch_pdu->pusch_data.new_data_indicator = 0;
+ pusch_pdu->pusch_data.new_data_indicator = 1;
+
+ uint8_t num_dmrs_symb = 0;
+
+ for(int dmrs_counter = pusch_pdu->start_symbol_index; dmrs_counter < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; dmrs_counter++)
+ num_dmrs_symb += ((pusch_pdu->ul_dmrs_symb_pos >> dmrs_counter) & 1);
+
+ uint8_t N_PRB_DMRS;
+ if (pusch_pdu->dmrs_config_type == 0) {
+ N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*6;
+ }
+ else {
+ N_PRB_DMRS = pusch_pdu->num_dmrs_cdm_grps_no_data*4;
+ }
+
pusch_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
- 6, //nb_re_dmrs - not sure where this is coming from - its not in the FAPI
+ N_PRB_DMRS * num_dmrs_symb,
0, //nb_rb_oh
+ 0,
pusch_pdu->nrOfLayers)>>3;
+
+
pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
//pusch_pdu->pusch_data.cb_present_and_position;
//pusch_pdu->pusch_uci;
@@ -805,34 +1010,52 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
int dci_formats[2];
int rnti_types[2];
- int CCEIndex = allocate_nr_CCEs(nr_mac,
- 1, // bwp_id
- 0, // coreset_id
- 4, // aggregation,
- 1, // search_space, 0 common, 1 ue-specific
- UE_id,
- 0); // m
+ NR_SearchSpace_t *ss;
+ int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
- dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
- rnti_types[0] = NR_RNTI_C;
- LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
- nr_configure_pdcch(pdcch_pdu_rel15,
- 1, // ue-specific,
- scc,
- bwp);
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
+ AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
+ "searchPsacesToAddModList is empty\n");
-
- dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
+ int found=0;
- AssertFatal(CCEIndex>=0,"CCEIndex is negative \n");
- pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex;
+ for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
+ ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
+ AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
+ AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
+ if (ss->searchSpaceType->present == target_ss) {
+ found=1;
+ break;
+ }
+ }
+ AssertFatal(found==1,"Couldn't find an adequate searchspace\n");
- LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]);
+ if (ss->searchSpaceType->choice.ue_Specific->dci_Formats)
+ dci_formats[0] = NR_UL_DCI_FORMAT_0_1;
+ else
+ dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
- config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
-
- pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
- fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
-
+ rnti_types[0] = NR_RNTI_C;
+ LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
+
+ int ret = nr_configure_pdcch(nr_mac,
+ pdcch_pdu_rel15,
+ UE_list->rnti[UE_id],
+ 1, // ue-specific,
+ ss,
+ scc,
+ bwp);
+
+ if (ret < 0) {
+ LOG_I(MAC,"CCE list not empty, couldn't schedule PUSCH\n");
+ UL_tti_req->n_pdus-=1;
+ return;
+ }
+ else {
+ dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15_t));
+ config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types,time_domain_assignment,n_ubwp,bwp_id);
+ fill_dci_pdu_rel15(scc,secondaryCellGroup,pdcch_pdu_rel15,dci_pdu_rel15,dci_formats,rnti_types,pusch_pdu->bwp_size,bwp_id);
+ free(dci_pdu_rel15);
+ }
}
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
index b7fddf9b733fba3d9bc74d66af550b825a027cdc..acb239ee39e59ba4ebb98160e55cacf62bd847c3 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
@@ -33,10 +33,10 @@
#include "assertions.h"
#include "LAYER2/MAC/mac.h"
-#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_gNB/nr_mac_gNB.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
-#include "LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_gNB/mac_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "common/utils/nr/nr_common.h"
@@ -68,8 +68,6 @@
extern RAN_CONTEXT_t RC;
-extern int n_active_slices;
-
// Note the 2 scs values in the table names represent resp. scs_common and pdcch_scs
/// LUT for the number of symbols in the coreset indexed by coreset index (4 MSB rmsi_pdcch_config)
uint8_t nr_coreset_nsymb_pdcch_type_0_scs_15_15[15] = {2,2,2,3,3,3,1,1,2,2,3,3,1,2,3};
@@ -131,12 +129,11 @@ static inline uint8_t get_max_cces(uint8_t scs) {
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int bwp_id,
- int coreset_id,
+ int list_id,
int aggregation,
int search_space, // 0 common, 1 ue-specific
int UE_id,
- int m
- ) {
+ int m) {
// uncomment these when we allocate for common search space
// NR_COMMON_channels_t *cc = nr_mac->common_channels;
// NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
@@ -148,19 +145,20 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
NR_ControlResourceSet_t *coreset;
+ AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id);
+ secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+
if (search_space == 1) {
- AssertFatal(UE_list->active[UE_id] >=0,"UE_id %d is not active\n",UE_id);
- secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
- bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
- coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[coreset_id];
+ coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[list_id];
}
else {
- AssertFatal(1==0,"Add code for common search space\n");
+ coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet;
}
+ int coreset_id = coreset->controlResourceSetId;
int *cce_list = nr_mac->cce_list[bwp_id][coreset_id];
-
int n_rb=0;
for (int i=0;i<6;i++)
for (int j=0;j<8;j++) {
@@ -182,7 +180,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
}
int first_cce = aggregation * (( Y + (m*N_cce)/(aggregation*M_s_max) + n_CI ) % CEILIDIV(N_cce,aggregation));
- for (int i=0;i<aggregation;i++)
+ for (int i=0;i<aggregation;i++)
if (cce_list[first_cce+i] != 0) return(-1);
for (int i=0;i<aggregation;i++) cce_list[first_cce+i] = 1;
@@ -409,65 +407,82 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
}
-void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
- int ss_type,
- NR_ServingCellConfigCommon_t *scc,
- NR_BWP_Downlink_t *bwp){
-
+int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
+ uint16_t rnti,
+ int ss_type,
+ NR_SearchSpace_t *ss,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Downlink_t *bwp){
+
+ int CCEIndex = -1;
+ int cid = 0;
+ NR_ControlResourceSet_t *coreset = NULL;
+
if (bwp) { // This is not the InitialBWP
- /// coreset
-
- //ControlResourceSetId
- // pdcch_pdu->config_type = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG;
- AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList!=NULL,
- "controlResourceSetToAddModList is null\n");
- AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count>0,
- "controlResourceSetToAddModList is empty\n");
- NR_ControlResourceSet_t *coreset0 = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0];
-
+ NR_ControlResourceSet_t *temp_coreset;
+ NR_ControlResourceSetId_t coresetid = *ss->controlResourceSetId;
+ if (ss_type == 0) { // common search space
+ if (coresetid == 0){
+ AssertFatal(1==0,"coreset0 currently not supported\n");
+ }
+ else {
+ coreset = bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet;
+ AssertFatal(coresetid==coreset->controlResourceSetId,"ID of common ss coreset does not correspond to id set in the search space\n");
+ }
+ }
+ else {
+ int n_list = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.count;
+ for (int i=0; i<n_list; i++) {
+ temp_coreset = bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[i];
+ if (coresetid==temp_coreset->controlResourceSetId) {
+ coreset = temp_coreset;
+ cid = i;
+ break;
+ }
+ }
+ if(coreset==NULL)
+ AssertFatal(1==0,"Couldn't find coreset with id %ld\n",coresetid);
+ }
pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix;
+
+ // first symbol
+ //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
+ int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
+
+ AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
+ AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
- pdcch_pdu->DurationSymbols = coreset0->duration;
-
- //frequencyDomainResources
- /* uint8_t count=0, start=0, start_set=0;
- // find coreset descriptor
+ // for SPS=14 8 MSBs in positions 13 downto 6
+ uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
+ (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
+
+ for (int i=0; i<sps; i++) {
+ if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
+ pdcch_pdu->StartSymbolIndex=i;
+ break;
+ }
+ }
+
+ pdcch_pdu->DurationSymbols = coreset->duration;
- uint64_t bitmap = (((uint64_t)coreset0->frequencyDomainResources.buf[0])<<37)|
- (((uint64_t)coreset0->frequencyDomainResources.buf[1])<<29)|
- (((uint64_t)coreset0->frequencyDomainResources.buf[2])<<21)|
- (((uint64_t)coreset0->frequencyDomainResources.buf[3])<<13)|
- (((uint64_t)coreset0->frequencyDomainResources.buf[4])<<5)|
- (((uint64_t)coreset0->frequencyDomainResources.buf[5])>>3);
-
- for (int i=0; i<45; i++)
- if ((bitmap>>(44-i))&1) {
- count++;
- if (!start_set) {
- start = i;
- start_set = 1;
- }
- }
- pdcch_pdu->rb_offset = 6*start;
- pdcch_pdu->n_rb = 6*count;
- */
for (int i=0;i<6;i++)
- pdcch_pdu->FreqDomainResource[i] = coreset0->frequencyDomainResources.buf[i];
- //duration
-
+ pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i];
+
//cce-REG-MappingType
- pdcch_pdu->CceRegMappingType = coreset0->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
+ pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
+
if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
- pdcch_pdu->RegBundleSize = (coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
- pdcch_pdu->InterleaverSize = (coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset0->cce_REG_MappingType.choice.interleaved->interleaverSize);
+ pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
+ pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize);
AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n");
- pdcch_pdu->ShiftIndex = coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset0->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
+ pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
}
else {
pdcch_pdu->RegBundleSize = 0;
@@ -478,89 +493,333 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
pdcch_pdu->CoreSetType = 1;
//precoderGranularity
- pdcch_pdu->precoderGranularity = coreset0->precoderGranularity;
-
- //TCI states
- //
- /*
- //TCI present
- if (coreset0->tci_PresentInDCI != NULL) {
- AssertFatal(coreset0->tci_StatesPDCCH_ToAddList != NULL,"tci_StatesPDCCH_ToAddList is null\n");
- AssertFatal(coreset0->tci_StatesPDCCH_ToAddList->list.count>0,"TCI state list is empty\n");
- for (int i=0;i<coreset0->tci_StatesPDCCH_ToAddList->list.count;i++) {
-
+ pdcch_pdu->precoderGranularity = coreset->precoderGranularity;
+
+ pdcch_pdu->dci_pdu.RNTI[pdcch_pdu->numDlDci]=rnti;
+
+ if (coreset->pdcch_DMRS_ScramblingID != NULL &&
+ ss->searchSpaceType->present == NR_SearchSpace__searchSpaceType_PR_ue_Specific) {
+ pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *coreset->pdcch_DMRS_ScramblingID;
+ pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=rnti;
}
- */
-
- for (int i=0;i<pdcch_pdu->numDlDci;i++) {
- //pdcch-DMRS-ScramblingID
- AssertFatal(coreset0->pdcch_DMRS_ScramblingID != NULL,"coreset0->pdcch_DMRS_ScramblingID is null\n");
- pdcch_pdu->ScramblingId[i] = *coreset0->pdcch_DMRS_ScramblingID;
- }
-
- /// SearchSpace
-
- // first symbol
- //AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
- int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
-
- AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList!=NULL,"searchPsacesToAddModList is null\n");
- AssertFatal(bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count>0,
- "searchPsacesToAddModList is empty\n");
- NR_SearchSpace_t *ss=NULL;
- int found=0;
- int target_ss = NR_SearchSpace__searchSpaceType_PR_common;
- if (ss_type == 1) {
- target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
- }
-
- for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
- ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
- AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
- AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
- if (*ss->controlResourceSetId == coreset0->controlResourceSetId &&
- ss->searchSpaceType->present == target_ss) {
- found=1;
- break;
+ else {
+ pdcch_pdu->dci_pdu.ScramblingId[pdcch_pdu->numDlDci] = *scc->physCellId;
+ pdcch_pdu->dci_pdu.ScramblingRNTI[pdcch_pdu->numDlDci]=0;
+ }
+
+ uint8_t nr_of_candidates,aggregation_level;
+ find_aggregation_candidates(&aggregation_level,
+ &nr_of_candidates,
+ ss);
+
+ CCEIndex = allocate_nr_CCEs(nr_mac,
+ 1, // bwp_id
+ cid,
+ aggregation_level,
+ ss->searchSpaceType->present-1, // search_space, 0 common, 1 ue-specific
+ 0, // UE-id
+ 0); // m
+
+ if (CCEIndex<0)
+ return (CCEIndex);
+
+ pdcch_pdu->dci_pdu.AggregationLevel[pdcch_pdu->numDlDci] = aggregation_level;
+ pdcch_pdu->dci_pdu.CceIndex[pdcch_pdu->numDlDci] = CCEIndex;
+
+ if (ss->searchSpaceType->choice.ue_Specific->dci_Formats==NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0)
+ pdcch_pdu->dci_pdu.beta_PDCCH_1_0[pdcch_pdu->numDlDci]=0;
+
+ pdcch_pdu->dci_pdu.powerControlOffsetSS[pdcch_pdu->numDlDci]=1;
+ pdcch_pdu->numDlDci++;
+ return (0);
+ }
+ else { // this is for InitialBWP
+ AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n");
+ }
+}
+
+
+// This function configures pucch pdu fapi structure
+void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Uplink_t *bwp,
+ uint8_t pucch_resource,
+ uint16_t O_uci,
+ uint16_t O_ack,
+ uint8_t SR_flag) {
+
+ NR_PUCCH_Config_t *pucch_Config;
+ NR_PUCCH_Resource_t *pucchres;
+ NR_PUCCH_ResourceSet_t *pucchresset;
+ NR_PUCCH_FormatConfig_t *pucchfmt;
+ NR_PUCCH_ResourceId_t *resource_id = NULL;
+
+ long *id0 = NULL;
+ int n_list, n_set;
+ uint16_t N2,N3;
+ int res_found = 0;
+
+ pucch_pdu->bit_len_harq = O_ack;
+
+ if (bwp) { // This is not the InitialBWP
+
+ NR_PUSCH_Config_t *pusch_Config = bwp->bwp_Dedicated->pusch_Config->choice.setup;
+ long *pusch_id = pusch_Config->dataScramblingIdentityPUSCH;
+
+ if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA != NULL)
+ id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup->transformPrecodingDisabled->scramblingID0;
+ if (pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB != NULL)
+ id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup->transformPrecodingDisabled->scramblingID0;
+
+ // hop flags and hopping id are valid for any BWP
+ switch (bwp->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping){
+ case 0 :
+ // if neither, both disabled
+ pucch_pdu->group_hop_flag = 0;
+ pucch_pdu->sequence_hop_flag = 0;
+ break;
+ case 1 :
+ // if enable, group enabled
+ pucch_pdu->group_hop_flag = 1;
+ pucch_pdu->sequence_hop_flag = 0;
+ break;
+ case 2 :
+ // if disable, sequence disabled
+ pucch_pdu->group_hop_flag = 0;
+ pucch_pdu->sequence_hop_flag = 1;
+ break;
+ default:
+ AssertFatal(1==0,"Group hopping flag %ld undefined (0,1,2) \n", bwp->bwp_Common->pucch_ConfigCommon->choice.setup->pucch_GroupHopping);
+ }
+
+ if (bwp->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId != NULL)
+ pucch_pdu->hopping_id = *bwp->bwp_Common->pucch_ConfigCommon->choice.setup->hoppingId;
+ else
+ pucch_pdu->hopping_id = *scc->physCellId;
+
+ pucch_pdu->bwp_size = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ pucch_pdu->bwp_start = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
+ pucch_pdu->subcarrier_spacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
+ pucch_pdu->cyclic_prefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix;
+
+ pucch_Config = bwp->bwp_Dedicated->pucch_Config->choice.setup;
+
+ AssertFatal(pucch_Config->resourceSetToAddModList!=NULL,
+ "PUCCH resourceSetToAddModList is null\n");
+
+ n_set = pucch_Config->resourceSetToAddModList->list.count;
+ AssertFatal(n_set>0,"PUCCH resourceSetToAddModList is empty\n");
+
+ N2 = 2;
+ // procedure to select pucch resource id from resource sets according to
+ // number of uci bits and pucch resource indicator pucch_resource
+ // ( see table 9.2.3.2 in 38.213)
+ for (int i=0; i<n_set; i++) {
+ pucchresset = pucch_Config->resourceSetToAddModList->list.array[i];
+ n_list = pucchresset->resourceList.list.count;
+ if (pucchresset->pucch_ResourceSetId == 0 && O_uci<3) {
+ if (pucch_resource < n_list)
+ resource_id = pucchresset->resourceList.list.array[pucch_resource];
+ else
+ AssertFatal(1==0,"Couldn't fine pucch resource indicator %d in PUCCH resource set %d for %d UCI bits",pucch_resource,i,O_uci);
+ }
+ else {
+ N3 = pucchresset->maxPayloadMinus1!= NULL ? *pucchresset->maxPayloadMinus1 : 1706;
+ if (N2<O_uci && N3>O_uci) {
+ if (pucch_resource < n_list)
+ resource_id = pucchresset->resourceList.list.array[pucch_resource];
+ else
+ AssertFatal(1==0,"Couldn't fine pucch resource indicator %d in PUCCH resource set %d for %d UCI bits",pucch_resource,i,O_uci);
+ }
+ else N2 = N3;
}
}
- AssertFatal(found==1,"Couldn't find a searchspace corresponding to coreset0\n");
- AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
- AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
-
- // for SPS=14 8 MSBs in positions 13 downto 6,
- uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
- (ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
-
- for (int i=0; i<sps; i++)
- if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
- pdcch_pdu->StartSymbolIndex=i;
- break;
+
+ AssertFatal(resource_id!=NULL,"Couldn-t find any matching PUCCH resource in the PUCCH resource sets");
+
+ AssertFatal(pucch_Config->resourceToAddModList!=NULL,
+ "PUCCH resourceToAddModList is null\n");
+
+ n_list = pucch_Config->resourceToAddModList->list.count;
+ AssertFatal(n_list>0,"PUCCH resourceToAddModList is empty\n");
+
+ // going through the list of PUCCH resources to find the one indexed by resource_id
+ for (int i=0; i<n_list; i++) {
+ pucchres = pucch_Config->resourceToAddModList->list.array[i];
+ if (pucchres->pucch_ResourceId == *resource_id) {
+ res_found = 1;
+ pucch_pdu->prb_start = pucchres->startingPRB;
+ // FIXME why there is only one frequency hopping flag
+ // what about inter slot frequency hopping?
+ pucch_pdu->freq_hop_flag = pucchres->intraSlotFrequencyHopping!= NULL ? 1 : 0;
+ pucch_pdu->second_hop_prb = pucchres->secondHopPRB!= NULL ? *pucchres->secondHopPRB : 0;
+ switch(pucchres->format.present) {
+ case NR_PUCCH_Resource__format_PR_format0 :
+ pucch_pdu->format_type = 0;
+ pucch_pdu->initial_cyclic_shift = pucchres->format.choice.format0->initialCyclicShift;
+ pucch_pdu->nr_of_symbols = pucchres->format.choice.format0->nrofSymbols;
+ pucch_pdu->start_symbol_index = pucchres->format.choice.format0->startingSymbolIndex;
+ pucch_pdu->sr_flag = SR_flag;
+ break;
+ case NR_PUCCH_Resource__format_PR_format1 :
+ pucch_pdu->format_type = 1;
+ pucch_pdu->initial_cyclic_shift = pucchres->format.choice.format1->initialCyclicShift;
+ pucch_pdu->nr_of_symbols = pucchres->format.choice.format1->nrofSymbols;
+ pucch_pdu->start_symbol_index = pucchres->format.choice.format1->startingSymbolIndex;
+ pucch_pdu->time_domain_occ_idx = pucchres->format.choice.format1->timeDomainOCC;
+ pucch_pdu->sr_flag = SR_flag;
+ break;
+ case NR_PUCCH_Resource__format_PR_format2 :
+ pucch_pdu->format_type = 2;
+ pucch_pdu->nr_of_symbols = pucchres->format.choice.format2->nrofSymbols;
+ pucch_pdu->start_symbol_index = pucchres->format.choice.format2->startingSymbolIndex;
+ pucch_pdu->prb_size = pucchres->format.choice.format2->nrofPRBs;
+ pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId;
+ pucch_pdu->dmrs_scrambling_id = id0!= NULL ? *id0 : *scc->physCellId;
+ break;
+ case NR_PUCCH_Resource__format_PR_format3 :
+ pucch_pdu->format_type = 3;
+ pucch_pdu->nr_of_symbols = pucchres->format.choice.format3->nrofSymbols;
+ pucch_pdu->start_symbol_index = pucchres->format.choice.format3->startingSymbolIndex;
+ pucch_pdu->prb_size = pucchres->format.choice.format3->nrofPRBs;
+ pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId;
+ if (pucch_Config->format3 == NULL) {
+ pucch_pdu->pi_2bpsk = 0;
+ pucch_pdu->add_dmrs_flag = 0;
+ }
+ else {
+ pucchfmt = pucch_Config->format3->choice.setup;
+ pucch_pdu->pi_2bpsk = pucchfmt->pi2BPSK!= NULL ? 1 : 0;
+ pucch_pdu->add_dmrs_flag = pucchfmt->additionalDMRS!= NULL ? 1 : 0;
+ }
+ break;
+ case NR_PUCCH_Resource__format_PR_format4 :
+ pucch_pdu->format_type = 4;
+ pucch_pdu->nr_of_symbols = pucchres->format.choice.format4->nrofSymbols;
+ pucch_pdu->start_symbol_index = pucchres->format.choice.format4->startingSymbolIndex;
+ pucch_pdu->pre_dft_occ_len = pucchres->format.choice.format4->occ_Length;
+ pucch_pdu->pre_dft_occ_idx = pucchres->format.choice.format4->occ_Index;
+ pucch_pdu->data_scrambling_id = pusch_id!= NULL ? *pusch_id : *scc->physCellId;
+ if (pucch_Config->format3 == NULL) {
+ pucch_pdu->pi_2bpsk = 0;
+ pucch_pdu->add_dmrs_flag = 0;
+ }
+ else {
+ pucchfmt = pucch_Config->format3->choice.setup;
+ pucch_pdu->pi_2bpsk = pucchfmt->pi2BPSK!= NULL ? 1 : 0;
+ pucch_pdu->add_dmrs_flag = pucchfmt->additionalDMRS!= NULL ? 1 : 0;
+ }
+ break;
+ default :
+ AssertFatal(1==0,"Undefined PUCCH format \n");
+ }
}
+ }
+ AssertFatal(res_found==1,"No PUCCH resource found corresponding to id %ld\n",*resource_id);
+ }
+ else { // this is for InitialBWP
+ AssertFatal(1==0,"Fill in InitialBWP PUCCH configuration\n");
}
- else { // this is for InitialBWP
- AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n");
+}
+
+
+void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
+ dci_pdu_rel15_t *dci_pdu_rel15,
+ nr_dci_format_t format,
+ int bwp_id) {
+
+ NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+
+ switch(format) {
+ case NR_UL_DCI_FORMAT_0_1:
+ // format indicator
+ dci_pdu_rel15->format_indicator = 0;
+ // carrier indicator
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL)
+ AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n");
+ // supplementary uplink
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink != NULL)
+ AssertFatal(1==0,"Supplementary Uplink currently not supported\n");
+ // SRS request
+ dci_pdu_rel15->srs_request.val = 0;
+ dci_pdu_rel15->ulsch_indicator = 1;
+ break;
+ case NR_DL_DCI_FORMAT_1_1:
+ // format indicator
+ dci_pdu_rel15->format_indicator = 1;
+ // carrier indicator
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL)
+ AssertFatal(1==0,"Cross Carrier Scheduling Config currently not supported\n");
+ //vrb to prb mapping
+ if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver==NULL)
+ dci_pdu_rel15->vrb_to_prb_mapping.val = 0;
+ else
+ dci_pdu_rel15->vrb_to_prb_mapping.val = 1;
+ //bundling size indicator
+ if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->prb_BundlingType.present == NR_PDSCH_Config__prb_BundlingType_PR_dynamicBundling)
+ AssertFatal(1==0,"Dynamic PRB bundling type currently not supported\n");
+ //rate matching indicator
+ uint16_t msb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup1==NULL)?0:1;
+ uint16_t lsb = (bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternGroup2==NULL)?0:1;
+ dci_pdu_rel15->rate_matching_indicator.val = lsb | (msb<<1);
+ // aperiodic ZP CSI-RS trigger
+ if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL)
+ AssertFatal(1==0,"Aperiodic ZP CSI-RS currently not supported\n");
+ // transmission configuration indication
+ if (bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[bwp_id-1]->tci_PresentInDCI != NULL)
+ AssertFatal(1==0,"TCI in DCI currently not supported\n");
+ //srs resource set
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching!=NULL) {
+ NR_SRS_CarrierSwitching_t *cs = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching->choice.setup;
+ if (cs->srs_TPC_PDCCH_Group!=NULL){
+ switch(cs->srs_TPC_PDCCH_Group->present) {
+ case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_NOTHING:
+ dci_pdu_rel15->srs_request.val = 0;
+ break;
+ case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeA:
+ AssertFatal(1==0,"SRS TPC PRCCH group type A currently not supported\n");
+ break;
+ case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_typeB:
+ AssertFatal(1==0,"SRS TPC PRCCH group type B currently not supported\n");
+ break;
+ }
+ }
+ else
+ dci_pdu_rel15->srs_request.val = 0;
+ }
+ else
+ dci_pdu_rel15->srs_request.val = 0;
+ // CBGTI and CBGFI
+ if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission != NULL)
+ AssertFatal(1==0,"CBG transmission currently not supported\n");
+ break;
+ default :
+ AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 and 0_1 \n");
}
}
+void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc,
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
+ dci_pdu_rel15_t *dci_pdu_rel15,
+ int *dci_formats,
+ int *rnti_types,
+ int N_RB,
+ int bwp_id) {
-void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
- dci_pdu_rel15_t *dci_pdu_rel15,
- int *dci_formats,
- int *rnti_types
- ) {
-
- uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
uint8_t fsize=0, pos=0;
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
- uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->Payload[d];
- AssertFatal(pdcch_pdu_rel15->PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
+ uint64_t *dci_pdu = (uint64_t *)pdcch_pdu_rel15->dci_pdu.Payload[d];
+ int dci_size = nr_dci_size(scc,secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],rnti_types[d],N_RB,bwp_id);
+ pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = dci_size;
+ AssertFatal(pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d]<=64, "DCI sizes above 64 bits not yet supported");
- int dci_size = pdcch_pdu_rel15->PayloadSizeBits[d];
+ if(dci_formats[d]==NR_DL_DCI_FORMAT_1_1 || dci_formats[d]==NR_UL_DCI_FORMAT_0_1)
+ prepare_dci(secondaryCellGroup,&dci_pdu_rel15[d],dci_formats[d],bwp_id);
/// Payload generation
switch(dci_formats[d]) {
@@ -570,25 +829,29 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize;
- *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
- LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
+ LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
// Time domain assignment
pos+=4;
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
- LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
+ LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
// VRB to PRB mapping
pos++;
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos);
- LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos);
+ LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
// MCS
pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
- LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
+#ifdef DEBUG_FILL_DCI
+ LOG_I(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu);
+#endif
// TB scaling
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos);
- LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
+#ifdef DEBUG_FILL_DCI
+ LOG_I(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu);
+#endif
break;
case NR_RNTI_C:
@@ -601,13 +864,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos));
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
- LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu);
+ LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
uint16_t is_ra = 1;
for (int i=0; i<fsize; i++)
- if (!((dci_pdu_rel15->frequency_domain_assignment>>i)&1)) {
+ if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
is_ra = 0;
break;
}
@@ -619,7 +882,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// UL/SUL indicator 1 bit
pos++;
- *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos);
+ *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos);
// SS/PBCH index 6 bits
pos+=6;
@@ -636,13 +899,13 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Time domain assignment 4bit
pos+=4;
- *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos));
- LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu);
+ *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
+ LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
// VRB to PRB mapping 1bit
pos++;
- *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
- LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu);
+ *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos);
+ LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
// MCS 5bit //bit over 32, so dci_pdu ++
pos+=5;
@@ -666,8 +929,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Downlink assignment index 2bit
pos+=2;
- *dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos));
- LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu);
+ *dci_pdu |= ((dci_pdu_rel15->dai[0].val&3)<<(dci_size-pos));
+ LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai[0].val,2,dci_size-pos,*dci_pdu);
// TPC command for scheduled PUCCH 2bit
pos+=2;
@@ -681,8 +944,8 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
- *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos));
- LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu);
+ *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos));
+ LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
} //end else
break;
@@ -698,12 +961,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -719,12 +982,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
- *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -740,12 +1003,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -760,7 +1023,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Downlink assignment index – 2 bits
for (int i=0; i<2; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai[0].val>>(1-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++)
@@ -773,7 +1036,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++);
break;
}
@@ -788,12 +1051,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
- *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit
for (int i=0; i<4; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -817,7 +1080,7 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/
break;
@@ -828,12 +1091,12 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
- *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++);
+ *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit
for (int i=0; i<4; i++)
- *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++);
+ *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++);
@@ -858,12 +1121,223 @@ void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
/*
commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
- *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++);
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/
break;
}
break;
+
+ case NR_UL_DCI_FORMAT_0_1:
+ switch(rnti_types[d])
+ {
+ case NR_RNTI_C:
+ // Indicating a DL DCI format 1bit
+ pos=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos);
+
+ // Carrier indicator
+ pos+=dci_pdu_rel15->carrier_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1))<<(dci_size-pos);
+
+ // UL/SUL Indicator
+ pos+=dci_pdu_rel15->ul_sul_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&((1<<dci_pdu_rel15->ul_sul_indicator.nbits)-1))<<(dci_size-pos);
+
+ // BWP indicator
+ pos+=dci_pdu_rel15->bwp_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1))<<(dci_size-pos);
+
+ // Frequency domain resource assignment
+ pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1)) << (dci_size-pos);
+
+ // Time domain resource assignment
+ pos+=dci_pdu_rel15->time_domain_assignment.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1)) << (dci_size-pos);
+
+ // Frequency hopping
+ pos+=dci_pdu_rel15->frequency_hopping_flag.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&((1<<dci_pdu_rel15->frequency_hopping_flag.nbits)-1)) << (dci_size-pos);
+
+ // MCS 5bit
+ pos+=5;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
+
+ // New data indicator 1bit
+ pos+=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos);
+
+ // Redundancy version 2bit
+ pos+=2;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
+
+ // HARQ process number 4bit
+ pos+=4;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
+
+ // 1st Downlink assignment index
+ pos+=dci_pdu_rel15->dai[0].nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<<dci_pdu_rel15->dai[0].nbits)-1))<<(dci_size-pos);
+
+ // 2nd Downlink assignment index
+ pos+=dci_pdu_rel15->dai[1].nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[1].val&((1<<dci_pdu_rel15->dai[1].nbits)-1))<<(dci_size-pos);
+
+ // TPC command for scheduled PUSCH 2bit
+ pos+=2;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos);
+
+ // SRS resource indicator
+ pos+=dci_pdu_rel15->srs_resource_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_resource_indicator.val&((1<<dci_pdu_rel15->srs_resource_indicator.nbits)-1))<<(dci_size-pos);
+
+ // Precoding info and n. of layers
+ pos+=dci_pdu_rel15->precoding_information.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->precoding_information.val&((1<<dci_pdu_rel15->precoding_information.nbits)-1))<<(dci_size-pos);
+
+ // Antenna ports
+ pos+=dci_pdu_rel15->antenna_ports.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<<dci_pdu_rel15->antenna_ports.nbits)-1))<<(dci_size-pos);
+
+ // SRS request
+ pos+=dci_pdu_rel15->srs_request.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<<dci_pdu_rel15->srs_request.nbits)-1))<<(dci_size-pos);
+
+ // CSI request
+ pos+=dci_pdu_rel15->csi_request.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->csi_request.val&((1<<dci_pdu_rel15->csi_request.nbits)-1))<<(dci_size-pos);
+
+ // CBG transmission information
+ pos+=dci_pdu_rel15->cbgti.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<<dci_pdu_rel15->cbgti.nbits)-1))<<(dci_size-pos);
+
+ // PTRS DMRS association
+ pos+=dci_pdu_rel15->ptrs_dmrs_association.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ptrs_dmrs_association.val&((1<<dci_pdu_rel15->ptrs_dmrs_association.nbits)-1))<<(dci_size-pos);
+
+ // Beta offset indicator
+ pos+=dci_pdu_rel15->beta_offset_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->beta_offset_indicator.val&((1<<dci_pdu_rel15->beta_offset_indicator.nbits)-1))<<(dci_size-pos);
+
+ // DMRS sequence initialization
+ pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<<dci_pdu_rel15->dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos);
+
+ // UL-SCH indicator
+ pos+=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ulsch_indicator&0x1)<<(dci_size-pos);
+
+ break;
+ }
+ break;
+
+ case NR_DL_DCI_FORMAT_1_1:
+ // Indicating a DL DCI format 1bit
+ pos=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&0x1)<<(dci_size-pos);
+
+ // Carrier indicator
+ pos+=dci_pdu_rel15->carrier_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1))<<(dci_size-pos);
+
+ // BWP indicator
+ pos+=dci_pdu_rel15->bwp_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1))<<(dci_size-pos);
+
+ // Frequency domain resource assignment
+ pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1)) << (dci_size-pos);
+
+ // Time domain resource assignment
+ pos+=dci_pdu_rel15->time_domain_assignment.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1)) << (dci_size-pos);
+
+ // VRB-to-PRB mapping
+ pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos);
+
+ // PRB bundling size indicator
+ pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos);
+
+ // Rate matching indicator
+ pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1))<<(dci_size-pos);
+
+ // ZP CSI-RS trigger
+ pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos);
+
+ //TB1
+ // MCS 5bit
+ pos+=5;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos);
+
+ // New data indicator 1bit
+ pos+=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&0x1)<<(dci_size-pos);
+
+ // Redundancy version 2bit
+ pos+=2;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos);
+
+ //TB2
+ // MCS 5bit
+ pos+=dci_pdu_rel15->mcs2.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs2.val&((1<<dci_pdu_rel15->mcs2.nbits)-1))<<(dci_size-pos);
+
+ // New data indicator 1bit
+ pos+=dci_pdu_rel15->ndi2.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi2.val&((1<<dci_pdu_rel15->ndi2.nbits)-1))<<(dci_size-pos);
+
+ // Redundancy version 2bit
+ pos+=dci_pdu_rel15->rv2.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv2.val&((1<<dci_pdu_rel15->rv2.nbits)-1))<<(dci_size-pos);
+
+ // HARQ process number 4bit
+ pos+=4;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos);
+
+ // Downlink assignment index
+ pos+=dci_pdu_rel15->dai[0].nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai[0].val&((1<<dci_pdu_rel15->dai[0].nbits)-1))<<(dci_size-pos);
+
+ // TPC command for scheduled PUCCH 2bit
+ pos+=2;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos);
+
+ // PUCCH resource indicator 3bit
+ pos+=3;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos);
+
+ // PDSCH-to-HARQ_feedback timing indicator
+ pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos);
+
+ // Antenna ports
+ pos+=dci_pdu_rel15->antenna_ports.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<<dci_pdu_rel15->antenna_ports.nbits)-1))<<(dci_size-pos);
+
+ // TCI
+ pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1))<<(dci_size-pos);
+
+ // SRS request
+ pos+=dci_pdu_rel15->srs_request.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<<dci_pdu_rel15->srs_request.nbits)-1))<<(dci_size-pos);
+
+ // CBG transmission information
+ pos+=dci_pdu_rel15->cbgti.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<<dci_pdu_rel15->cbgti.nbits)-1))<<(dci_size-pos);
+
+ // CBG flushing out information
+ pos+=dci_pdu_rel15->cbgfi.nbits;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos);
+
+ // DMRS sequence init
+ pos+=1;
+ *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&0x1)<<(dci_size-pos);
}
}
}
@@ -905,7 +1379,6 @@ int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot) {
}
-
int extract_startSymbol(int startSymbolAndLength) {
int tmp = startSymbolAndLength/14;
int tmp2 = startSymbolAndLength%14;
@@ -969,6 +1442,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
int UE_id;
int i;
NR_UE_list_t *UE_list = &RC.nrmac[mod_idP]->UE_list;
+ NR_COMMON_channels_t *cc = RC.nrmac[mod_idP]->common_channels;
+ NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
+ int num_slots_ul = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols>0)
+ num_slots_ul++;
LOG_I(MAC, "[gNB %d] Adding UE with rnti %x (next avail %d, num_UEs %d)\n",
mod_idP,
rntiP,
@@ -987,6 +1465,7 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
memset((void *) &UE_list->UE_sched_ctrl[UE_id],
0,
sizeof(NR_UE_sched_ctrl_t));
+ UE_list->UE_sched_ctrl[UE_id].sched_pucch = (NR_sched_pucch *)malloc(num_slots_ul*sizeof(NR_sched_pucch));
LOG_I(MAC, "gNB %d] Add NR UE_id %d : rnti %x\n",
mod_idP,
UE_id,
@@ -1003,6 +1482,134 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP){
return -1;
}
+void get_pdsch_to_harq_feedback(int Mod_idP,
+ int UE_id,
+ NR_SearchSpace__searchSpaceType_PR ss_type,
+ uint8_t *pdsch_to_harq_feedback) {
+
+ int bwp_id=1;
+ NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
+ NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
+ NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
+ NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
+
+ NR_SearchSpace_t *ss;
+
+ // common search type uses DCI format 1_0
+ if (ss_type == NR_SearchSpace__searchSpaceType_PR_common) {
+ for (int i=0; i<8; i++)
+ pdsch_to_harq_feedback[i] = i+1;
+ }
+ else {
+
+ // searching for a ue specific search space
+ int found=0;
+
+ for (int i=0;i<bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.count;i++) {
+ ss=bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list.array[i];
+ AssertFatal(ss->controlResourceSetId != NULL,"ss->controlResourceSetId is null\n");
+ AssertFatal(ss->searchSpaceType != NULL,"ss->searchSpaceType is null\n");
+ if (ss->searchSpaceType->present == ss_type) {
+ found=1;
+ break;
+ }
+ }
+ AssertFatal(found==1,"Couldn't find a ue specific searchspace\n");
+
+
+ if (ss->searchSpaceType->choice.ue_Specific->dci_Formats == NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0) {
+ for (int i=0; i<8; i++)
+ pdsch_to_harq_feedback[i] = i+1;
+ }
+ else {
+ if(ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK != NULL) {
+ for (int i=0; i<8; i++)
+ pdsch_to_harq_feedback[i] = *ubwp->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.array[i];
+ }
+ else
+ AssertFatal(0==1,"There is no allocated dl_DataToUL_ACK for pdsch to harq feedback\n");
+ }
+ }
+}
+
+// function to update pucch scheduling parameters in UE list when a USS DL is scheduled
+void nr_update_pucch_scheduling(int Mod_idP,
+ int UE_id,
+ frame_t frameP,
+ sub_frame_t slotP,
+ int slots_per_tdd,
+ int *pucch_id) {
+
+ NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
+ NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
+ NR_sched_pucch *curr_pucch;
+ int first_ul_slot_tdd,k,i;
+ uint8_t pdsch_to_harq_feedback[8];
+ int found = 0;
+ int nr_ulmix_slots = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots;
+ if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
+ nr_ulmix_slots++;
+
+ // this is hardcoded for now as ue specific
+ NR_SearchSpace__searchSpaceType_PR ss_type = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
+ get_pdsch_to_harq_feedback(Mod_idP,UE_id,ss_type,pdsch_to_harq_feedback);
+
+ // for each possible ul or mixed slot
+ for (k=0; k<nr_ulmix_slots; k++) {
+ curr_pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k];
+ // if there is free room in current pucch structure
+ if (curr_pucch->dai_c<MAX_ACK_BITS) {
+ curr_pucch->frame = frameP;
+ curr_pucch->dai_c++;
+ curr_pucch->resource_indicator = 0; // in phytest with only 1 UE we are using just the 1st resource
+ // first pucch occasion in first UL or MIXED slot
+ first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
+ i = 0;
+ while (i<8 && found == 0) { // look if timing indicator is among allowed values
+ if (pdsch_to_harq_feedback[i]==(first_ul_slot_tdd+k)-(slotP % slots_per_tdd))
+ found = 1;
+ if (found == 0) i++;
+ }
+ if (found == 1) {
+ // computing slot in which pucch is scheduled
+ curr_pucch->ul_slot = first_ul_slot_tdd + k + (slotP - (slotP % slots_per_tdd));
+ curr_pucch->timing_indicator = i; // index in the list of timing indicators
+ *pucch_id = k;
+ return;
+ }
+ }
+ }
+ AssertFatal(1==0,"No Uplink slot available in accordance to allowed timing indicator\n");
+}
+
+
+void find_aggregation_candidates(uint8_t *aggregation_level,
+ uint8_t *nr_of_candidates,
+ NR_SearchSpace_t *ss) {
+
+ if (ss->nrofCandidates->aggregationLevel1 != NR_SearchSpace__nrofCandidates__aggregationLevel1_n0) {
+ *aggregation_level = 1;
+ *nr_of_candidates = ss->nrofCandidates->aggregationLevel1;
+ }
+ if (ss->nrofCandidates->aggregationLevel2 != NR_SearchSpace__nrofCandidates__aggregationLevel2_n0) {
+ *aggregation_level = 2;
+ *nr_of_candidates = ss->nrofCandidates->aggregationLevel2;
+ }
+ if (ss->nrofCandidates->aggregationLevel4 != NR_SearchSpace__nrofCandidates__aggregationLevel4_n0) {
+ *aggregation_level = 4;
+ *nr_of_candidates = ss->nrofCandidates->aggregationLevel4;
+ }
+ if (ss->nrofCandidates->aggregationLevel8 != NR_SearchSpace__nrofCandidates__aggregationLevel8_n0) {
+ *aggregation_level = 8;
+ *nr_of_candidates = ss->nrofCandidates->aggregationLevel8;
+ }
+ if (ss->nrofCandidates->aggregationLevel16 != NR_SearchSpace__nrofCandidates__aggregationLevel16_n0) {
+ *aggregation_level = 16;
+ *nr_of_candidates = ss->nrofCandidates->aggregationLevel16;
+ }
+}
+
+
/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg,
nfapi_nr_coreset_t *coreset,
nfapi_nr_search_space_t *search_space) {
diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
index 2fcccd682b3dbd1c6724d79be0fdb3f5ef218098..89c3fe69fe00c0b7f1cd628374ba28054074d36a 100644
--- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
@@ -28,10 +28,12 @@
* @ingroup _mac
*/
+
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "executables/softmodem-common.h"
//#define ENABLE_MAC_PAYLOAD_DEBUG 1
+
void nr_process_mac_pdu(
module_id_t module_idP,
uint8_t CC_id,
@@ -87,7 +89,13 @@ void nr_process_mac_pdu(
/*#ifdef DEBUG_HEADER_PARSING
LOG_D(MAC, "[UE] LCID %d, PDU length %d\n", ((NR_MAC_SUBHEADER_FIXED *)pdu_ptr)->LCID, pdu_len);
#endif*/
-
+ case UL_SCH_LCID_RECOMMENDED_BITRATE_QUERY:
+ // 38.321 Ch6.1.3.20
+ mac_ce_len = 2;
+ break;
+ case UL_SCH_LCID_CONFIGURED_GRANT_CONFIRMATION:
+ // 38.321 Ch6.1.3.7
+ break;
case UL_SCH_LCID_S_BSR:
//38.321 section 6.1.3.1
//fixed length
@@ -170,6 +178,24 @@ void nr_process_mac_pdu(
// end of MAC PDU, can ignore the rest.
break;
+ // MAC SDUs
+ case UL_SCH_LCID_SRB1:
+ // todo
+ break;
+ case UL_SCH_LCID_SRB2:
+ // todo
+ break;
+ case UL_SCH_LCID_SRB3:
+ // todo
+ break;
+ case UL_SCH_LCID_CCCH_MSG3:
+ // todo
+ break;
+ case UL_SCH_LCID_CCCH:
+ // todo
+ mac_subheader_len = 2;
+ break;
+
case UL_SCH_LCID_DTCH:
// check if LCID is valid at current time.
if(((NR_MAC_SUBHEADER_SHORT *)pdu_ptr)->F){
@@ -183,7 +209,7 @@ void nr_process_mac_pdu(
mac_subheader_len = 2;
}
- LOG_D(MAC, "[UE %d] Frame %d : DLSCH -> DL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len);
+ LOG_D(MAC, "[UE %d] Frame %d : ULSCH -> UL-DTCH %d (gNB %d, %d bytes)\n", module_idP, frameP, rx_lcid, module_idP, mac_sdu_len);
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
LOG_T(MAC, "[UE %d] First 32 bytes of DLSCH : \n", module_idP);
@@ -223,13 +249,12 @@ void nr_process_mac_pdu(
pdu_len -= ( mac_subheader_len + mac_ce_len + mac_sdu_len );
if (pdu_len < 0) {
- LOG_E(MAC, "%s() residual mac pdu length < 0!\n", __func__);
+ LOG_E(MAC, "%s() residual mac pdu length < 0!, pdu_len: %d\n", __func__, pdu_len);
return;
}
}
}
-
/*
* When data are received on PHY and transmitted to MAC
*/
@@ -245,7 +270,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
int current_rnti = 0, UE_id = -1, harq_pid = 0;
gNB_MAC_INST *gNB_mac = NULL;
NR_UE_list_t *UE_list = NULL;
- UE_sched_ctrl_t *UE_scheduling_control = NULL;
+ NR_UE_sched_ctrl_t *UE_scheduling_control = NULL;
current_rnti = rntiP;
UE_id = find_nr_UE_id(gnb_mod_idP, current_rnti);
@@ -255,13 +280,12 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
if (UE_id != -1) {
UE_scheduling_control = &(UE_list->UE_sched_ctrl[UE_id]);
- LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu round %d from PHY (rnti %x, UE_id %d) ul_cqi %d\n",
+ LOG_D(MAC, "[gNB %d][PUSCH %d] CC_id %d %d.%d Received ULSCH sdu from PHY (rnti %x, UE_id %d) ul_cqi %d\n",
gnb_mod_idP,
harq_pid,
CC_idP,
frameP,
slotP,
- UE_scheduling_control->round_UL[CC_idP][harq_pid],
current_rnti,
UE_id,
ul_cqi);
@@ -282,4 +306,20 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
nr_process_mac_pdu(gnb_mod_idP, CC_idP, frameP, sduP, sdu_lenP);
}
}
+ else {
+ // random access pusch with TC-RNTI
+ if (sduP != NULL) { // if the CRC passed
+ for (int i = 0; i < MAX_MOBILES_PER_GNB; i++) {
+ if (UE_list->active[i] == TRUE) {
+ if (UE_list->tc_rnti[i] == current_rnti) {
+ // for now the only thing we are doing is set the UE as 5G connected
+ UE_list->fiveG_connected[i] = true;
+ LOG_I(MAC, "[gNB %d][RAPROC] PUSCH with TC_RNTI %x received correctly and UE_id %d is now 5G connected\n",
+ gnb_mod_idP, current_rnti, i);
+ }
+ }
+ }
+ }
+ }
}
+
diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
index d55a188817d5cab9c0b0bcb1586cff73108b4ada..74c6841a3a370205726d947e569ffb6ad394be77 100644
--- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h
@@ -31,10 +31,13 @@
#ifndef __LAYER2_NR_MAC_PROTO_H__
#define __LAYER2_NR_MAC_PROTO_H__
-#include "nr_mac_gNB.h"
#include "PHY/defs_gNB.h"
+
+#include "LAYER2/NR_MAC_gNB/nr_mac_gNB.h"
#include "NR_TAG-Id.h"
+#define MAX_ACK_BITS 2 //only format 0 is available for now
+
void set_cset_offset(uint16_t);
void mac_top_init_gNB(void);
@@ -76,18 +79,66 @@ void nr_schedule_ue_spec(module_id_t module_idP, frame_t frameP, sub_frame_t slo
void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP);
+/////// Random Access MAC-PHY interface functions and primitives ///////
+
+void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP);
+
+/* \brief Function to indicate a received preamble on PRACH. It initiates the RA procedure.
+@param module_idP Instance ID of gNB
+@param preamble_index index of the received RA request
+@param slotP Slot number on which to act
+@param timing_offset Offset in samples of the received PRACH w.r.t. eNB timing. This is used to
+@param rnti RA rnti corresponding to this PRACH preamble
+@param rach_resource type (0=non BL/CE,1 CE level 0,2 CE level 1, 3 CE level 2,4 CE level 3)
+*/
+void nr_initiate_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP,
+ uint16_t preamble_index, uint8_t freq_index, uint8_t symbol, int16_t timing_offset);
+
+void nr_clear_ra_proc(module_id_t module_idP, int CC_id, frame_t frameP);
+
+int nr_allocate_CCEs(int module_idP, int CC_idP, frame_t frameP, sub_frame_t slotP, int test_only);
+
+void nr_get_Msg3alloc(NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Uplink_t *ubwp,
+ sub_frame_t current_subframe,
+ frame_t current_frame,
+ NR_RA_t *ra);
+
+/* \brief Function in gNB to fill RAR pdu when requested by PHY.
+@param ra Instance of RA resources of gNB
+@param dlsch_buffer Pointer to RAR input buffer
+@param N_RB_UL Number of UL resource blocks
+*/
+void nr_fill_rar(uint8_t Mod_idP,
+ NR_RA_t * ra,
+ uint8_t * dlsch_buffer,
+ nfapi_nr_pusch_pdu_t *pusch_pdu);
+
+
+void schedule_nr_prach(module_id_t module_idP, frame_t frameP, sub_frame_t slotP);
+
+uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs);
+
+/////// Phy test scheduler ///////
+
void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t subframeP);
int configure_fapi_dl_pdu(int Mod_id,
- int *CCEIndeces,
nfapi_nr_dl_tti_request_body_t *dl_req,
+ NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
uint16_t *rbSize,
uint16_t *rbStart);
-void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types);
+void config_uldci(NR_BWP_Uplink_t *ubwp,
+ nfapi_nr_pusch_pdu_t *pusch_pdu,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
+ dci_pdu_rel15_t *dci_pdu_rel15,
+ int *dci_formats, int *rnti_types,
+ int time_domain_assignment,
+ int n_ubwp, int bwp_id);
void configure_fapi_dl_Tx(module_id_t Mod_idP,
frame_t frameP,
@@ -100,11 +151,24 @@ void configure_fapi_dl_Tx(module_id_t Mod_idP,
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP,
+ NR_sched_pucch *pucch_sched,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_config);
void nr_schedule_uss_ulsch_phytest(int Mod_idP,
frame_t frameP,
sub_frame_t slotP);
+
+void nr_update_pucch_scheduling(int Mod_idP,
+ int UE_id,
+ frame_t frameP,
+ sub_frame_t slotP,
+ int slots_per_tdd,
+ int *pucch_id);
+
+void get_pdsch_to_harq_feedback(int Mod_idP,
+ int UE_id,
+ NR_SearchSpace__searchSpaceType_PR ss_type,
+ uint8_t *pdsch_to_harq_feedback);
void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
nr_scs_e scs_common,
@@ -125,24 +189,52 @@ int nr_is_dci_opportunity(nfapi_nr_search_space_t search_space,
nfapi_nr_config_request_scf_t cfg);
*/
-void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
- int ss_type,
- NR_ServingCellConfigCommon_t *scc,
- NR_BWP_Downlink_t *bwp);
-
-void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
+void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Uplink_t *bwp,
+ uint8_t pucch_resource,
+ uint16_t O_uci,
+ uint16_t O_ack,
+ uint8_t SR_flag);
+
+void find_search_space(int ss_type,
+ NR_BWP_Downlink_t *bwp,
+ NR_SearchSpace_t *ss);
+
+int nr_configure_pdcch(gNB_MAC_INST *nr_mac,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
+ uint16_t rnti,
+ int ss_type,
+ NR_SearchSpace_t *ss,
+ NR_ServingCellConfigCommon_t *scc,
+ NR_BWP_Downlink_t *bwp);
+
+void fill_dci_pdu_rel15(NR_ServingCellConfigCommon_t *scc,
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
- int *rnti_types);
+ int *rnti_types,
+ int N_RB,
+ int bwp_id);
+
+void prepare_dci(NR_CellGroupConfig_t *secondaryCellGroup,
+ dci_pdu_rel15_t *dci_pdu_rel15,
+ nr_dci_format_t format,
+ int bwp_id);
+
+void find_aggregation_candidates(uint8_t *aggregation_level,
+ uint8_t *nr_of_candidates,
+ NR_SearchSpace_t *ss);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
int to_absslot(nfapi_nr_config_request_scf_t *cfg,int frame,int slot);
-void get_band(uint64_t downlink_frequency, uint16_t *current_band, int32_t *current_offset, lte_frame_type_t *current_type);
-
void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
- int x_overhead);
+ int x_overhead,
+ uint8_t numdmrscdmgroupnodata,
+ uint8_t tb_scaling);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
@@ -161,12 +253,6 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP);
int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP);
-int get_num_dmrs(uint16_t dmrs_mask );
-
-uint16_t nr_dci_size(nr_dci_format_t format,
- nr_rnti_type_t rnti_type,
- uint16_t N_RB);
-
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int bwp_id,
int coreset_id,
@@ -176,9 +262,6 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int m
);
-int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
-int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
-
int get_dlscs(nfapi_nr_config_request_t *cfg);
int get_ulscs(nfapi_nr_config_request_t *cfg);
@@ -198,6 +281,14 @@ void config_nr_mib(int Mod_idP,
int intraFreqReselection);
+void nr_generate_Msg2(module_id_t module_idP,
+ int CC_id,
+ frame_t frameP,
+ sub_frame_t slotP);
+
+void nr_schedule_reception_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP);
+
+
void nr_process_mac_pdu(
module_id_t module_idP,
uint8_t CC_id,
@@ -205,6 +296,9 @@ void nr_process_mac_pdu(
uint8_t *pduP,
uint16_t mac_pdu_len);
+int binomial(int n, int k);
+
+
/* \brief Function to indicate a received SDU on ULSCH.
@param Mod_id Instance ID of gNB
@param CC_id Component carrier index
diff --git a/openair2/LAYER2/NR_MAC_gNB/main.c b/openair2/LAYER2/NR_MAC_gNB/main.c
index 9e8415776b641e9675a42efb320541c0e169f6cb..56e020838d267847670fce5b0b9b5b864b439219 100644
--- a/openair2/LAYER2/NR_MAC_gNB/main.c
+++ b/openair2/LAYER2/NR_MAC_gNB/main.c
@@ -30,8 +30,8 @@
*/
-#include "mac_proto.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
+#include "NR_MAC_gNB/mac_proto.h"
+#include "NR_MAC_COMMON/nr_mac_extern.h"
#include "assertions.h"
#include "LAYER2/PDCP_v10.1.0/pdcp.h"
@@ -113,6 +113,11 @@ void mac_top_init_gNB(void)
UE_list->next[list_el] = list_el + 1;
UE_list->next_ul[list_el] = list_el + 1;
UE_list->active[list_el] = FALSE;
+ for (int list_harq = 0; list_harq < NR_MAX_NB_HARQ_PROCESSES; list_harq++) {
+ UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].round = 0;
+ UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].ndi = 0;
+ UE_list->UE_sched_ctrl[list_el].harq_processes[list_harq].is_waiting = 0;
+ }
}
UE_list->next[list_el] = -1;
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
index e4e3ac05df9239d9b277581af49e05257df250e8..df23b64e07b28ec8a9cf07d52064bb60a515835f 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
@@ -39,6 +39,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t nb_symb_sch,
uint16_t nb_dmrs_prb,
uint16_t nb_rb_oh,
+ uint8_t tb_scaling,
uint8_t Nl)
{
@@ -54,7 +55,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
scale = (R>1024)?11:10;
// Intermediate number of information bits
- Ninfo = (nb_re * R * Qm * Nl)>>scale;
+ Ninfo = ((nb_re * R * Qm * Nl)>>scale)>>tb_scaling;
if (Ninfo <=3824) {
n = max(3, floor(log2(Ninfo)) - 6);
diff --git a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
index 5bc320d5e2ee67ec8d0e76e12fb5f07d3b4b716f..f84e7a900c95eeb53e485dcf39dcc33d465f696b 100644
--- a/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+++ b/openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
@@ -42,30 +42,106 @@
#include <stdlib.h>
#include <string.h>
+/* Commmon */
+#include "targets/ARCH/COMMON/common_lib.h"
+#include "COMMON/platform_constants.h"
+#include "common/ran_context.h"
+
+/* RRC */
#include "NR_BCCH-BCH-Message.h"
#include "NR_CellGroupConfig.h"
#include "NR_ServingCellConfigCommon.h"
#include "NR_MeasConfig.h"
+/* PHY */
+#include "PHY/defs_gNB.h"
+#include "PHY/TOOLS/time_meas.h"
+
+/* Interface */
#include "nfapi_nr_interface_scf.h"
#include "NR_PHY_INTERFACE/NR_IF_Module.h"
-#include "COMMON/platform_constants.h"
-#include "common/ran_context.h"
+/* MAC */
#include "LAYER2/MAC/mac.h"
#include "LAYER2/MAC/mac_proto.h"
#include "LAYER2/NR_MAC_COMMON/nr_mac_extern.h"
-#include "PHY/defs_gNB.h"
-#include "PHY/TOOLS/time_meas.h"
-#include "targets/ARCH/COMMON/common_lib.h"
-
-#include "nr_mac_common.h"
+#include "LAYER2/NR_MAC_COMMON/nr_mac_common.h"
+#include "NR_TAG.h"
+/* Defs */
#define MAX_NUM_BWP 2
#define MAX_NUM_CORESET 2
#define MAX_NUM_CCE 90
-
-#include "NR_TAG.h"
+/*!\brief Maximum number of random access process */
+#define NR_NB_RA_PROC_MAX 4
+
+typedef enum {
+ RA_IDLE = 0,
+ Msg2 = 1,
+ WAIT_Msg3 = 2,
+ Msg4 = 3,
+ WAIT_Msg4_ACK = 4
+} RA_gNB_state_t;
+
+/*! \brief gNB template for the Random access information */
+typedef struct {
+ /// Flag to indicate this process is active
+ RA_gNB_state_t state;
+ /// BWP id of RA process
+ int bwp_id;
+ /// CORESET0 configured flag
+ int coreset0_configured;
+ /// Slot where preamble was received
+ uint8_t preamble_slot;
+ /// Subframe where Msg2 is to be sent
+ uint8_t Msg2_slot;
+ /// Frame where Msg2 is to be sent
+ frame_t Msg2_frame;
+ /// Subframe where Msg3 is to be sent
+ sub_frame_t Msg3_slot;
+ /// Frame where Msg3 is to be sent
+ frame_t Msg3_frame;
+ /// Msg3 time domain allocation index
+ uint8_t Msg3_tda_id;
+ /// Subframe where Msg4 is to be sent
+ sub_frame_t Msg4_slot;
+ /// Frame where Msg4 is to be sent
+ frame_t Msg4_frame;
+ /// harq_pid used for Msg4 transmission
+ uint8_t harq_pid;
+ /// UE RNTI allocated during RAR
+ rnti_t rnti;
+ /// RA RNTI allocated from received PRACH
+ uint16_t RA_rnti;
+ /// Received preamble_index
+ uint8_t preamble_index;
+ /// Received UE Contention Resolution Identifier
+ uint8_t cont_res_id[6];
+ /// Timing offset indicated by PHY
+ int16_t timing_offset;
+ /// Timeout for RRC connection
+ int16_t RRC_timer;
+ /// Msg3 first RB
+ uint8_t msg3_first_rb;
+ /// Msg3 number of RB
+ uint8_t msg3_nb_rb;
+ /// Msg3 TPC command
+ uint8_t msg3_TPC;
+ /// Msg3 ULdelay command
+ uint8_t msg3_ULdelay;
+ /// Msg3 cqireq command
+ uint8_t msg3_cqireq;
+ /// Round of Msg3 HARQ
+ uint8_t msg3_round;
+ /// Msg3 pusch pdu
+ nfapi_nr_pusch_pdu_t pusch_pdu;
+ /// TBS used for Msg4
+ int msg4_TBsize;
+ /// MCS used for Msg4
+ int msg4_mcs;
+ /// RA search space
+ NR_SearchSpace_t *ra_ss;
+} NR_RA_t;
/*! \brief gNB common channels */
typedef struct {
@@ -73,6 +149,7 @@ typedef struct {
int p_gNB;
int Ncp;
int nr_band;
+ lte_frame_type_t frame_type;
uint64_t dl_CarrierFreq;
NR_BCCH_BCH_Message_t *mib;
NR_ServingCellConfigCommon_t *ServingCellConfigCommon;
@@ -93,7 +170,7 @@ typedef struct {
/// Outgoing RAR pdu for PHY
RAR_PDU RAR_pdu;
/// Template for RA computations
- RA_t ra[NB_RA_PROC_MAX];
+ NR_RA_t ra[NR_NB_RA_PROC_MAX];
/// VRB map for common channels
uint8_t vrb_map[100];
/// VRB map for common channels and retransmissions by PHICH
@@ -102,17 +179,110 @@ typedef struct {
uint8_t num_sf_allocation_pattern;
} NR_COMMON_channels_t;
-/*! \brief scheduling control information set through an API (not used)*/
+
+// SP ZP CSI-RS Resource Set Activation/Deactivation MAC CE
+typedef struct sp_zp_csirs {
+ bool is_scheduled; //ZP CSI-RS ACT/Deact MAC CE is scheduled
+ bool act_deact; //Activation/Deactivation indication
+ uint8_t serv_cell_id; //Identity of Serving cell for which MAC CE applies
+ uint8_t bwpid; //Downlink BWP id
+ uint8_t rsc_id; //SP ZP CSI-RS resource set
+} sp_zp_csirs_t;
+
+//SP CSI-RS / CSI-IM Resource Set Activation/Deactivation MAC CE
+#define MAX_CSI_RESOURCE_SET 64
+typedef struct csi_rs_im {
+ bool is_scheduled;
+ bool act_deact;
+ uint8_t serv_cellid;
+ uint8_t bwp_id;
+ bool im;
+ uint8_t csi_im_rsc_id;
+ uint8_t nzp_csi_rsc_id;
+ uint8_t nb_tci_resource_set_id;
+ uint8_t tci_state_id [ MAX_CSI_RESOURCE_SET ];
+} csi_rs_im_t;
+
+typedef struct pdcchStateInd {
+ bool is_scheduled;
+ uint8_t servingCellId;
+ uint8_t coresetId;
+ uint8_t tciStateId;
+} pdcchStateInd_t;
+
+typedef struct SPCSIReportingpucch {
+ bool is_scheduled;
+ uint8_t servingCellId;
+ uint8_t bwpId;
+ bool s0tos3_actDeact[4];
+} SPCSIReportingpucch_t;
+
+#define MAX_APERIODIC_TRIGGER_STATES 128 //38.331
+typedef struct aperiodicCSI_triggerStateSelection {
+ bool is_scheduled;
+ uint8_t servingCellId;
+ uint8_t bwpId;
+ uint8_t highestTriggerStateSelected;
+ bool triggerStateSelection[MAX_APERIODIC_TRIGGER_STATES];
+} aperiodicCSI_triggerStateSelection_t;
+
+#define MAX_TCI_STATES 128 //38.331
+typedef struct pdschTciStatesActDeact {
+ bool is_scheduled;
+ uint8_t servingCellId;
+ uint8_t bwpId;
+ uint8_t highestTciStateActivated;
+ bool tciStateActDeact[MAX_TCI_STATES];
+} pdschTciStatesActDeact_t;
+
+typedef struct UE_info {
+ sp_zp_csirs_t sp_zp_csi_rs;
+ csi_rs_im_t csi_im;
+ pdcchStateInd_t pdcch_state_ind;
+ SPCSIReportingpucch_t SP_CSI_reporting_pucch;
+ aperiodicCSI_triggerStateSelection_t aperi_CSI_trigger;
+ pdschTciStatesActDeact_t pdsch_TCI_States_ActDeact;
+} NR_UE_mac_ce_ctrl_t;
+
+
+typedef struct NR_sched_pucch {
+ int frame;
+ int ul_slot;
+ uint8_t dai_c;
+ uint8_t timing_indicator;
+ uint8_t resource_indicator;
+} NR_sched_pucch;
+
+typedef struct NR_UE_harq {
+ uint8_t is_waiting;
+ uint8_t ndi;
+ uint8_t round;
+ uint16_t feedback_slot;
+} NR_UE_harq_t;
+
+/*! \brief scheduling control information set through an API */
typedef struct {
+ uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
+ uint64_t ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
+ NR_sched_pucch *sched_pucch;
+ uint16_t ta_timer;
+ int16_t ta_update;
+ uint8_t current_harq_pid;
+ NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES];
int dummy;
+ NR_UE_mac_ce_ctrl_t UE_mac_ce_ctrl;// MAC CE related information
} NR_UE_sched_ctrl_t;
-/*! \brief UE list used by eNB to order UEs/CC for scheduling*/
-typedef struct {
+typedef struct NR_preamble_ue {
+ uint8_t num_preambles;
+ uint8_t *preamble_list;
+} NR_preamble_ue;
+/*! \brief UE list used by gNB to order UEs/CC for scheduling*/
+typedef struct {
DLSCH_PDU DLSCH_pdu[4][MAX_MOBILES_PER_GNB];
/// scheduling control info
- UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB];
+ NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB];
int next[MAX_MOBILES_PER_GNB];
int head;
int next_ul[MAX_MOBILES_PER_GNB];
@@ -120,7 +290,10 @@ typedef struct {
int avail;
int num_UEs;
boolean_t active[MAX_MOBILES_PER_GNB];
+ boolean_t fiveG_connected[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB];
+ rnti_t tc_rnti[MAX_MOBILES_PER_GNB];
+ NR_preamble_ue preambles[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
} NR_UE_list_t;
@@ -165,7 +338,7 @@ typedef struct gNB_MAC_INST_s {
/// UL handle
uint32_t ul_handle;
- // MAC function execution peformance profiler
+ // MAC function execution peformance profiler
/// processing time of eNB scheduler
time_stats_t eNB_scheduler;
/// processing time of eNB scheduler for SI
@@ -190,68 +363,4 @@ typedef struct gNB_MAC_INST_s {
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
} gNB_MAC_INST;
-typedef struct {
-
-
-uint8_t format_indicator; //1 bit
-uint16_t frequency_domain_assignment; //up to 16 bits
-uint8_t time_domain_assignment; // 4 bits
-uint8_t frequency_hopping_flag; //1 bit
-
-uint8_t ra_preamble_index; //6 bits
-uint8_t ss_pbch_index; //6 bits
-uint8_t prach_mask_index; //4 bits
-
-uint8_t vrb_to_prb_mapping; //0 or 1 bit
-uint8_t mcs; //5 bits
-uint8_t ndi; //1 bit
-uint8_t rv; //2 bits
-uint8_t harq_pid; //4 bits
-uint8_t dai; //0, 2 or 4 bits
-uint8_t dai1; //1 or 2 bits
-uint8_t dai2; //0 or 2 bits
-uint8_t tpc; //2 bits
-uint8_t pucch_resource_indicator; //3 bits
-uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
-
-uint8_t short_messages_indicator; //2 bits
-uint8_t short_messages; //8 bits
-uint8_t tb_scaling; //2 bits
-
-uint8_t carrier_indicator; //0 or 3 bits
-uint8_t bwp_indicator; //0, 1 or 2 bits
-uint8_t prb_bundling_size_indicator; //0 or 1 bits
-uint8_t rate_matching_indicator; //0, 1 or 2 bits
-uint8_t zp_csi_rs_trigger; //0, 1 or 2 bits
-uint8_t transmission_configuration_indication; //0 or 3 bits
-uint8_t srs_request; //2 bits
-uint8_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
-uint8_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
-uint8_t dmrs_sequence_initialization; //0 or 1 bit
-
-uint8_t srs_resource_indicator;
-uint8_t precoding_information;
-uint8_t csi_request;
-uint8_t ptrs_dmrs_association;
-uint8_t beta_offset_indicator; //0 or 2 bits
-
-uint8_t slot_format_indicator_count;
-uint8_t *slot_format_indicators;
-
-uint8_t pre_emption_indication_count;
-uint16_t *pre_emption_indications; //14 bit
-
-uint8_t block_number_count;
-uint8_t *block_numbers;
-
-uint8_t ul_sul_indicator; //0 or 1 bit
-uint8_t antenna_ports;
-
-uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
-uint16_t padding;
-
-} dci_pdu_rel15_t;
-
-
-
#endif /*__LAYER2_NR_MAC_GNB_H__ */
diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c
index b0e6143de1e9074cc1bd0162aa35aeba857c341d..3667af26984326071cc20b7d33fd55c3cc4b5ae7 100644
--- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.c
+++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.c
@@ -503,8 +503,6 @@ pdcp_data_ind(
//-----------------------------------------------------------------------------
{
pdcp_t *pdcp_p = NULL;
- list_t *sdu_list_p = NULL;
- mem_block_t *new_sdu_p = NULL;
uint8_t pdcp_header_len = 0;
uint8_t pdcp_tailer_len = 0;
pdcp_sn_t sequence_number = 0;
@@ -576,7 +574,6 @@ pdcp_data_ind(
}
}
- sdu_list_p = &pdcp_sdu_list;
if (sdu_buffer_sizeP == 0) {
LOG_W(PDCP, "SDU buffer size is zero! Ignoring this chunk!\n");
@@ -974,9 +971,8 @@ pdcp_data_ind(
#endif
if (FALSE == packet_forwarded) {
- new_sdu_p = get_free_mem_block(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), __func__);
+ notifiedFIFO_elt_t * new_sdu_p = newNotifiedFIFO_elt(sdu_buffer_sizeP - payload_offset + sizeof (pdcp_data_ind_header_t), 0, NULL, NULL);
- if (new_sdu_p) {
if ((MBMS_flagP == 0) && (pdcp_p->rlc_mode == RLC_MODE_AM)) {
pdcp_p->last_submitted_pdcp_rx_sn = sequence_number;
}
@@ -984,14 +980,15 @@ pdcp_data_ind(
/*
* Prepend PDCP indication header which is going to be removed at pdcp_fifo_flush_sdus()
*/
- memset(new_sdu_p->data, 0, sizeof (pdcp_data_ind_header_t));
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size = sdu_buffer_sizeP - payload_offset;
+ pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(new_sdu_p);
+ memset(pdcpHead, 0, sizeof (pdcp_data_ind_header_t));
+ pdcpHead->data_size = sdu_buffer_sizeP - payload_offset;
AssertFatal((sdu_buffer_sizeP - payload_offset >= 0), "invalid PDCP SDU size!");
// Here there is no virtualization possible
// set ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst for IP layer here
if (ctxt_pP->enb_flag == ENB_FLAG_NO) {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id;
+ pdcpHead->rb_id = rb_id;
if (EPC_MODE_ENABLED) {
/* for the UE compiled in S1 mode, we need 1 here
@@ -1002,45 +999,40 @@ pdcp_data_ind(
#ifdef UESIM_EXPANSION
if (UE_NAS_USE_TUN) {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id;
+ pdcpHead->inst = ctxt_pP->module_id;
} else {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 0;
+ pdcpHead->inst = 0;
}
#else
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id;
+ pdcpHead->inst = ctxt_pP->module_id;
#endif
} else { // nfapi_mode
if (UE_NAS_USE_TUN) {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id;
+ pdcpHead->inst = ctxt_pP->module_id;
} else {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = 1;
+ pdcpHead->inst = 1;
}
} // nfapi_mode
}
} else {
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB);
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = ctxt_pP->module_id;
+ pdcpHead->rb_id = rb_id + (ctxt_pP->module_id * LTE_maxDRB);
+ pdcpHead->inst = ctxt_pP->module_id;
}
if( LOG_DEBUGFLAG(DEBUG_PDCP) ) {
static uint32_t pdcp_inst = 0;
- ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst = pdcp_inst++;
- LOG_D(PDCP, "inst=%d size=%d\n", ((pdcp_data_ind_header_t *) new_sdu_p->data)->inst, ((pdcp_data_ind_header_t *) new_sdu_p->data)->data_size);
+ pdcpHead->inst = pdcp_inst++;
+ LOG_D(PDCP, "inst=%d size=%d\n", pdcpHead->inst, pdcpHead->data_size);
}
- memcpy(&new_sdu_p->data[sizeof (pdcp_data_ind_header_t)],
+ memcpy(pdcpHead+1,
&sdu_buffer_pP->data[payload_offset],
sdu_buffer_sizeP - payload_offset);
-
- #if defined(ENABLE_PDCP_PAYLOAD_DEBUG)
- LOG_I(PDCP, "Printing first bytes of PDCP SDU before adding it to the list: \n");
- for (int i=0; i<30; i++){
- LOG_I(PDCP, "%x", sdu_buffer_pP->data[i]);
- }
- #endif
- list_add_tail_eurecom (new_sdu_p, sdu_list_p);
- }
+ if( LOG_DEBUGFLAG(DEBUG_PDCP) )
+ log_dump(PDCP, pdcpHead+1, min(sdu_buffer_sizeP - payload_offset,30) , LOG_DUMP_CHAR,
+ "Printing first bytes of PDCP SDU before adding it to the list: \n");
+ pushNotifiedFIFO(&pdcp_sdu_list, new_sdu_p);
/* Print octets of incoming data in hexadecimal form */
LOG_D(PDCP, "Following content has been received from RLC (%d,%d)(PDCP header has already been removed):\n",
@@ -2390,7 +2382,7 @@ void nr_ip_over_LTE_DRB_preconfiguration(void){
// 1 + drb_identiy_index;
DRB_config->drb_Identity = 1;
DRB_config->logicalChannelIdentity = CALLOC(1, sizeof(long));
- *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 2; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2
+ *(DRB_config->logicalChannelIdentity) = DRB_config->drb_Identity + 3; //(long) (ue_context_pP->ue_context.e_rab[i].param.e_rab_id + 2); // value : x+2
DRB_rlc_config = CALLOC(1, sizeof(*DRB_rlc_config));
DRB_config->rlc_Config = DRB_rlc_config;
@@ -2467,7 +2459,7 @@ void pdcp_layer_init(void)
/*
* Initialize SDU list
*/
- list_init(&pdcp_sdu_list, NULL);
+ initNotifiedFIFO(&pdcp_sdu_list);
pdcp_coll_p = hashtable_create ((LTE_maxDRB + 2) * NUMBER_OF_UE_MAX, NULL, pdcp_free);
AssertFatal(pdcp_coll_p != NULL, "UNRECOVERABLE error, PDCP hashtable_create failed");
@@ -2540,7 +2532,8 @@ void pdcp_layer_init(void)
void pdcp_layer_cleanup (void)
//-----------------------------------------------------------------------------
{
- list_free (&pdcp_sdu_list);
+ //list_free (&pdcp_sdu_list);
+ while(pollNotifiedFIFO(&pdcp_sdu_list)) {};
hashtable_destroy(&pdcp_coll_p);
#ifdef MBMS_MULTICAST_OUT
diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h
index e9ac85866cec5d73e2b0e7dd7efe658981cf7e5e..de8a1b385b59bea9392af83ff2b719991ff9da3c 100644
--- a/openair2/LAYER2/PDCP_v10.1.0/pdcp.h
+++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp.h
@@ -34,10 +34,6 @@
#ifndef __PDCP_H__
# define __PDCP_H__
//-----------------------------------------------------------------------------
-#ifndef NON_ACCESS_STRATUM
- #include "UTIL/MEM/mem_block.h"
- #include "UTIL/LISTS/list.h"
-#endif //NON_ACCESS_STRATUM
//-----------------------------------------------------------------------------
#include "RRC/LTE/rrc_defs.h"
#include "COMMON/platform_constants.h"
@@ -522,7 +518,7 @@ pdcp_mbms_t pdcp_mbms_array_eNB[NUMBER_OF_eNB_MAX][LTE_maxServiceC
sdu_size_t pdcp_output_sdu_bytes_to_write;
sdu_size_t pdcp_output_header_bytes_to_write;
-list_t pdcp_sdu_list;
+notifiedFIFO_t pdcp_sdu_list;
int pdcp_sent_a_sdu;
pdcp_data_req_header_t pdcp_input_header;
unsigned char pdcp_input_sdu_buffer[MAX_IP_PACKET_SIZE];
diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c
index d203408e5506ca01d51bf32869c042ccecebc545..c9a62d573b5b78decde8c5af19a814a526151741 100644
--- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c
+++ b/openair2/LAYER2/PDCP_v10.1.0/pdcp_fifo.c
@@ -55,7 +55,6 @@ extern int otg_enabled;
#include "common/utils/LOG/log.h"
#include "UTIL/OTG/otg_tx.h"
#include "nfapi/oai_integration/vendor_ext.h"
-#include "UTIL/FIFO/pad_list.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "platform_constants.h"
#include "msc.h"
@@ -91,7 +90,6 @@ extern struct msghdr nas_msg_rx;
extern uint16_t inst_pdcp_list[NUMBER_OF_UE_MAX];
#endif
-extern Packet_OTG_List_t *otg_pdcp_buffer;
# include "gtpv1u_eNB_task.h"
@@ -111,69 +109,60 @@ void debug_pdcp_pc5s_sdu(sidelink_pc5s_element *sl_pc5s_msg, char *title) {
}
//-----------------------------------------------------------------------------
int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) {
- mem_block_t *sdu_p;
+ notifiedFIFO_elt_t *sdu_p;
int pdcp_nb_sdu_sent = 0;
int ret=0;
+ while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) {
+ pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p);
- while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) {
- ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0;
- int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id;
- int sizeToWrite= sizeof (pdcp_data_ind_header_t) +
- ((pdcp_data_ind_header_t *) sdu_p->data)->data_size;
+ /* Note: we ignore the instance ID in the context and use the one in the
+ * PDCP packet to pick the right socket below */
+ int rb_id = pdcpHead->rb_id;
+ int sizeToWrite= sizeof (pdcp_data_ind_header_t) +
+ pdcpHead->data_size;
+ void * pdcpData=(void*)(pdcpHead+1);
if (rb_id == 10) { //hardcoded for PC5-Signaling
if( LOG_DEBUGFLAG(DEBUG_PDCP) ) {
- debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)&(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),
+ debug_pdcp_pc5s_sdu((sidelink_pc5s_element *)pdcpData,
"pdcp_fifo_flush_sdus sends a aPC5S message");
}
- ret = sendto(pdcp_pc5_sockfd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),
+ ret = sendto(pdcp_pc5_sockfd, pdcpData,
sizeof(sidelink_pc5s_element), 0, (struct sockaddr *)&prose_pdcp_addr,sizeof(prose_pdcp_addr) );
} else if (UE_NAS_USE_TUN) {
- //ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite );
+ //ret = write(nas_sock_fd[pdcpHead->inst], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite );
if(rb_id == mbms_rab_id){
- ret = write(nas_sock_mbms_fd, &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite );
- LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite);
+ ret = write(nas_sock_mbms_fd, pdcpData,sizeToWrite );
+ LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH MBMS DATA TO rb_id %d handle %d sizeToWrite %d\n",
+ ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite);
}
else
{
- #if defined(ENABLE_PDCP_PAYLOAD_DEBUG)
- LOG_I(PHY, "PDCP output to be sent to TUN interface: \n");
- for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) {
- printf("%02x ",(unsigned char)sdu_p->data[i]);
- }
- printf("\n");
- #endif
- ret = write(nas_sock_fd[ctxt_pP->module_id], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]),sizeToWrite );
- //LOG_I(PDCP,"[PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[ctxt_pP->module_id],sizeToWrite);
+ if( LOG_DEBUGFLAG(DEBUG_PDCP) )
+ log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n");
+ ret = write(nas_sock_fd[pdcpHead->inst], pdcpData,sizeToWrite );
+ LOG_T(PDCP,"[UE PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",
+ ret,rb_id,nas_sock_fd[pdcpHead->inst],sizeToWrite);
}
} else if (ENB_NAS_USE_TUN) {
- #if defined(ENABLE_PDCP_PAYLOAD_DEBUG)
- LOG_I(PHY, "PDCP output to be sent to TUN interface: \n");
- for (int i = sizeof(pdcp_data_ind_header_t); i < sizeToWrite; i++) {
- printf("%02x ",(unsigned char)sdu_p->data[i]);
- }
- printf("\n");
- #endif
- ret = write(nas_sock_fd[0], &(sdu_p->data[sizeof(pdcp_data_ind_header_t)]), sizeToWrite);
-
+ if( LOG_DEBUGFLAG(DEBUG_PDCP) )
+ log_dump(PDCP, pdcpData, sizeToWrite, LOG_DUMP_CHAR,"PDCP output to be sent to TUN interface: \n");
+ ret = write(nas_sock_fd[0], pdcpData, sizeToWrite);
+ LOG_T(PDCP,"[NB PDCP_FIFOS] ret %d TRIED TO PUSH DATA TO rb_id %d handle %d sizeToWrite %d\n",ret,rb_id,nas_sock_fd[0],sizeToWrite);
} else if (PDCP_USE_NETLINK) {
- memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) sdu_p->data, sizeToWrite);
+ memcpy(NLMSG_DATA(nas_nlh_tx), (uint8_t *) pdcpHead, sizeToWrite);
nas_nlh_tx->nlmsg_len = sizeToWrite;
ret = sendmsg(nas_sock_fd[0],&nas_msg_tx,0);
} // PDCP_USE_NETLINK
AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s), nas_sock_fd[0]: %d\n", errno, strerror(errno), nas_sock_fd[0]);
- #if defined(ENABLE_PDCP_PAYLOAD_DEBUG)
- LOG_I(PDCP, "Printing first bytes of PDCP SDU before removing it from the list: \n");
- for (int i=0; i<30; i++){
- LOG_I(PDCP, "%x", sdu_p->data[i]);
- }
- #endif
- list_remove_head (&pdcp_sdu_list);
- free_mem_block (sdu_p, __func__);
+ if( LOG_DEBUGFLAG(DEBUG_PDCP) )
+ log_dump(PDCP, pdcpData, min(sizeToWrite,30) , LOG_DUMP_CHAR,
+ "Printing first bytes of PDCP SDU before removing it from the list: \n");
+ delNotifiedFIFO_elt (sdu_p);
pdcp_nb_sdu_sent ++;
}
@@ -181,12 +170,13 @@ int pdcp_fifo_flush_sdus(const protocol_ctxt_t *const ctxt_pP) {
}
int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) {
- mem_block_t *sdu_p;
+ notifiedFIFO_elt_t *sdu_p;
int pdcp_nb_sdu_sent = 0;
//int ret=0;
- while ((sdu_p = list_get_head (&pdcp_sdu_list)) != NULL && ((pdcp_data_ind_header_t *)(sdu_p->data))->inst == ctxt_pP->module_id) {
- ((pdcp_data_ind_header_t *)(sdu_p->data))->inst = 0;
+ while ((sdu_p = pollNotifiedFIFO(&pdcp_sdu_list)) != NULL ) {
+ pdcp_data_ind_header_t * pdcpHead=(pdcp_data_ind_header_t *)NotifiedFifoData(sdu_p);
+ AssertFatal(pdcpHead->inst==ctxt_pP->module_id, "To implement correctly multi module id\n");
//int rb_id = ((pdcp_data_ind_header_t *)(sdu_p->data))->rb_id;
//int sizeToWrite= sizeof (pdcp_data_ind_header_t) +
//((pdcp_data_ind_header_t *) sdu_p->data)->data_size;
@@ -212,8 +202,8 @@ int pdcp_fifo_flush_mbms_sdus(const protocol_ctxt_t *const ctxt_pP) {
//} // PDCP_USE_NETLINK
//AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno));
- list_remove_head (&pdcp_sdu_list);
- free_mem_block (sdu_p, __func__);
+ //AssertFatal(ret >= 0,"[PDCP_FIFOS] pdcp_fifo_flush_sdus (errno: %d %s)\n", errno, strerror(errno));
+ delNotifiedFIFO_elt (sdu_p);
pdcp_nb_sdu_sent ++;
}
@@ -320,7 +310,7 @@ int pdcp_fifo_read_input_mbms_sdus_fromtun (const protocol_ctxt_t *const ctxt_p
ctxt.module_id, ctxt.rnti, ctxt.enb_flag);
if (h_rc == HASH_TABLE_OK) {
- LOG_I(PDCP, "[FRAME %5u][UE][NETLINK][IP->PDCP] INST %d: Received socket with length %d on Rab %ld \n",
+ LOG_D(PDCP, "[FRAME %5u][UE][NETLINK][IP->PDCP] INST %d: Received socket with length %d on Rab %ld \n",
ctxt.frame, ctxt.instance, len, rab_id);
LOG_D(PDCP, "[FRAME %5u][UE][IP][INSTANCE %u][RB %ld][--- PDCP_DATA_REQ / %d Bytes --->][PDCP][MOD %u][UE %04x][RB %ld]\n",
ctxt.frame, ctxt.instance, rab_id, len, ctxt.module_id,
diff --git a/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h b/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h
deleted file mode 100644
index b9f62acc3c96b91eb14b462196eeb7d18e2a1607..0000000000000000000000000000000000000000
--- a/openair2/LAYER2/PDCP_v10.1.0/pdcp_proto_extern.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.
- * The OpenAirInterface Software Alliance licenses this file to You under
- * the OAI Public License, Version 1.1 (the "License"); you may not use this file
- * except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.openairinterface.org/?page_id=698
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *-------------------------------------------------------------------------------
- * For more information about the OpenAirInterface (OAI) Software Alliance:
- * contact@openairinterface.org
- */
-
-/*
- pdcp_proto_extern.h
- -------------------
- AUTHOR : Lionel GAUTHIER
- COMPANY : EURECOM
- EMAIL : Lionel.Gauthier@eurecom.fr
-
- ***************************************************************************/
-#ifndef __PDCP_PROTO_EXTERN_H__
-# define __PDCP_PROTO_EXTERN_H__
-
-//# include "pdcp_entity.h"
-//# include "rb_mux.h"
-# include "mem_block.h"
-
-#ifdef ROHC
-extern void pdcp_data_ind (module_id_t module_idP, rb_id_t rab_idP, sdu_size_t data_sizeP, mem_block_t *sduP);
-extern void pdcp_data_req (struct pdcp_entity *pdcpP, mem_block *sduP);
-extern void send_pdcp_control_primitive (struct pdcp_entity *pdcpP, mem_block *cprimitiveP);
-extern void control_pdcp (struct pdcp_entity *pdcpP);
-extern void pdcp_process_input_sdus_high(struct pdcp_entity *pdcpP);
-extern void pdcp_process_input_sdus_am (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP);
-extern void pdcp_process_output_sdus (struct pdcp_entity *pdcpP, mem_block *sduP, uint8_t rb_idP);
-extern void pdcp_process_output_sdus_high (struct pdcp_entity *pdcpP, mem_block *sduP, uint16_t data_sizeP, uint16_t rb_idP);
-extern void pdcp_process_input_sdus_um (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP);
-extern void pdcp_process_input_sdus_tr (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP);
-extern void init_pdcp (struct pdcp_entity *pdcpP, struct rb_dispatcher *rbP, uint8_t rb_idP);
-extern void *pdcp_tx (struct pdcp_entity *pdcpP, uint16_t data_sizeP, mem_block *sduP);
-extern int reception_from_rohc_mt(void);
-extern int reception_from_rohc_bs(void);
-#else
-extern BOOL pdcp_data_ind (module_id_t module_idP, rb_id_t rab_idP, sdu_size_t data_sizeP, mem_block_t *sduP, uint8_t is_data_plane);
-extern BOOL pdcp_data_req (module_id_t module_id, uint32_t frame, uint8_t eNB_flag, rb_id_t rab_id, uint32_t muiP, uint32_t confirmP, sdu_size_t sdu_buffer_size, unsigned char *sdu_buffer,
- uint8_t is_data_pdu,const uint32_t *const sourceL2Id,const uint32_t *const destinationL2Id
- );
-//extern BOOL pdcp_data_req (struct pdcp_entity *pdcpP, mem_block * sduP);
-extern void send_pdcp_control_primitive (struct pdcp_entity *pdcpP, mem_block *cprimitiveP);
-extern void control_pdcp (struct pdcp_entity *pdcpP);
-extern void pdcp_process_input_sdus_am (struct pdcp_entity *pdcpP);
-extern void pdcp_process_output_sdus (struct pdcp_entity *pdcpP, mem_block *sduP, uint8_t rb_idP);
-extern void pdcp_process_input_sdus_um (struct pdcp_entity *pdcpP);
-extern void pdcp_process_input_sdus_tr (struct pdcp_entity *pdcpP);
-extern void init_pdcp (struct pdcp_entity *pdcpP, struct rb_dispatcher *rbP, uint8_t rb_idP);
-extern void *pdcp_tx (void *argP);
-#endif
-
-extern void pdcp_pc5_socket_init(void);
-
-#endif
diff --git a/openair2/LAYER2/RLC/rlc.c b/openair2/LAYER2/RLC/rlc.c
index 2fb844f05a8b5d567cc559896e19a71643a1fe56..98c8c3e252da05ebe81b4f237b2078f07ffe39d7 100644
--- a/openair2/LAYER2/RLC/rlc.c
+++ b/openair2/LAYER2/RLC/rlc.c
@@ -519,7 +519,7 @@ rlc_op_status_t rlc_data_req (const protocol_ctxt_t *const ctxt_pP,
// LOG_I(RLC,"DUY rlc_data_req: mbms_rb_id in RLC instant is: %d\n", mbms_rb_id);
if (sdu_pP != NULL) {
if (sdu_sizeP > 0) {
- LOG_I(RLC,"received a packet with size %d for MBMS \n", sdu_sizeP);
+ LOG_D(RLC,"received a packet with size %d for MBMS \n", sdu_sizeP);
new_sdu_p = get_free_mem_block (sdu_sizeP + sizeof (struct rlc_um_data_req_alloc), __func__);
if (new_sdu_p != NULL) {
diff --git a/openair2/LAYER2/RLC/rlc_rrc.c b/openair2/LAYER2/RLC/rlc_rrc.c
index 85ee4e05719f845a6702edc246bd605e4772baa4..4313f379fe0f9e5475dbd8053215f0c73567f5d8 100644
--- a/openair2/LAYER2/RLC/rlc_rrc.c
+++ b/openair2/LAYER2/RLC/rlc_rrc.c
@@ -640,7 +640,8 @@ rlc_union_t *rrc_rlc_add_rlc (
} else if (h_rc == HASH_TABLE_KEY_NOT_EXISTS) {
rlc_union_p = calloc(1, sizeof(rlc_union_t));
h_rc = hashtable_insert(rlc_coll_p, key, rlc_union_p);
- h_lcid_rc = hashtable_insert(rlc_coll_p, key_lcid, rlc_union_p);
+ if(MBMS_flagP != TRUE)
+ h_lcid_rc = hashtable_insert(rlc_coll_p, key_lcid, rlc_union_p);
if ((h_rc == HASH_TABLE_OK) && (h_lcid_rc == HASH_TABLE_OK)) {
if (MBMS_flagP == TRUE) {
diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c
index 09f29ebe6784a7b190cd5147ffe533be29d660b3..4ef952667dc84be0c6de1b219c5cf5f37833558e 100644
--- a/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c
+++ b/openair2/LAYER2/nr_rlc/nr_rlc_entity_um.c
@@ -588,9 +588,10 @@ static void check_t_reassembly(nr_rlc_entity_um_t *entity)
cur = entity->rx_list;
while (cur != NULL &&
sn_compare_rx(entity, cur->sn, entity->rx_next_reassembly) < 0) {
- nr_rlc_free_pdu(cur);
+ nr_rlc_pdu_t *p = cur;
cur = cur->next;
entity->rx_list = cur;
+ nr_rlc_free_pdu(p);
}
if (sn_compare_rx(entity, entity->rx_next_highest,
diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c
index ff0d446e3f0e4004b45048cdb3eab6a6a9a2b2c6..bbc4acbd56d3624adfe92241e0b17531701f9c0a 100644
--- a/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c
+++ b/openair2/LAYER2/nr_rlc/nr_rlc_oai_api.c
@@ -72,8 +72,8 @@ void mac_rlc_data_ind (
LOG_I(RLC, "RLC instance for the given UE was not found \n");
switch (channel_idP) {
- case 1 ... 2: rb = ue->srb[channel_idP - 1]; break;
- case 3 ... 7: rb = ue->drb[channel_idP - 3]; break;
+ case 1 ... 3: rb = ue->srb[channel_idP - 1]; break;
+ case 4 ... 8: rb = ue->drb[channel_idP - 4]; break;
default: rb = NULL; break;
}
@@ -113,8 +113,8 @@ tbs_size_t mac_rlc_data_req(
ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP);
switch (channel_idP) {
- case 1 ... 2: rb = ue->srb[channel_idP - 1]; break;
- case 3 ... 7: rb = ue->drb[channel_idP - 3]; break;
+ case 1 ... 3: rb = ue->srb[channel_idP - 1]; break;
+ case 4 ... 8: rb = ue->drb[channel_idP - 4]; break;
default: rb = NULL; break;
}
@@ -123,7 +123,7 @@ tbs_size_t mac_rlc_data_req(
maxsize = tb_sizeP;
ret = rb->generate_pdu(rb, buffer_pP, maxsize);
} else {
- LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB\n", __FILE__, __LINE__, __FUNCTION__);
+ LOG_E(RLC, "%s:%d:%s: fatal: data req for unknown RB, channel_idP: %d\n", __FILE__, __LINE__, __FUNCTION__, channel_idP);
exit(1);
ret = 0;
}
@@ -166,8 +166,8 @@ mac_rlc_status_resp_t mac_rlc_status_ind(
ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP);
switch (channel_idP) {
- case 1 ... 2: rb = ue->srb[channel_idP - 1]; break;
- case 3 ... 7: rb = ue->drb[channel_idP - 3]; break;
+ case 1 ... 3: rb = ue->srb[channel_idP - 1]; break;
+ case 4 ... 8: rb = ue->drb[channel_idP - 4]; break;
default: rb = NULL; break;
}
@@ -227,8 +227,8 @@ rlc_buffer_occupancy_t mac_rlc_get_buffer_occupancy_ind(
ue = nr_rlc_manager_get_ue(nr_rlc_ue_manager, rntiP);
switch (channel_idP) {
- case 1 ... 2: rb = ue->srb[channel_idP - 1]; break;
- case 3 ... 7: rb = ue->drb[channel_idP - 3]; break;
+ case 1 ... 3: rb = ue->srb[channel_idP - 1]; break;
+ case 4 ... 8: rb = ue->drb[channel_idP - 4]; break;
default: rb = NULL; break;
}
@@ -654,7 +654,7 @@ static void add_drb_am(int rnti, struct LTE_DRB_ToAddMod *s)
exit(1);
}
- if (channel_id != drb_id + 2) {
+ if (channel_id != drb_id + 3) {
LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n",
__FILE__, __LINE__, __FUNCTION__);
exit(1);
@@ -737,7 +737,7 @@ static void add_drb_um(int rnti, struct LTE_DRB_ToAddMod *s)
exit(1);
}
- if (channel_id != drb_id + 2) {
+ if (channel_id != drb_id + 3) {
LOG_E(RLC, "%s:%d:%s: todo, remove this limitation\n",
__FILE__, __LINE__, __FUNCTION__);
exit(1);
diff --git a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h
index 464cf3d083d774bc1286520a8e00f382196383f5..f578faaf380f4ae6712c04ceeee3a80de2ae476b 100644
--- a/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h
+++ b/openair2/LAYER2/nr_rlc/nr_rlc_ue_manager.h
@@ -28,7 +28,7 @@ typedef void nr_rlc_ue_manager_t;
typedef struct nr_rlc_ue_t {
int rnti;
- nr_rlc_entity_t *srb[2];
+ nr_rlc_entity_t *srb[3];
nr_rlc_entity_t *drb[5];
} nr_rlc_ue_t;
diff --git a/openair2/LAYER2/rlc_v2/rlc_entity_um.c b/openair2/LAYER2/rlc_v2/rlc_entity_um.c
index f0fe33789b4fecc1f5673edf30355422568c4460..54707875a0b25f7c91086131f4515d75dea9f5c9 100644
--- a/openair2/LAYER2/rlc_v2/rlc_entity_um.c
+++ b/openair2/LAYER2/rlc_v2/rlc_entity_um.c
@@ -360,6 +360,7 @@ static tx_pdu_size_t tx_pdu_size(rlc_entity_um_t *entity, int maxsize)
ret.data_size = 0;
ret.header_size = 0;
ret.last_sdu_is_full = 1;
+ ret.first_sdu_length = 0;
/* TX PDU - let's make the biggest PDU we can with the SDUs we have */
sdu_count = 0;
diff --git a/openair2/LAYER2/rlc_v2/rlc_oai_api.c b/openair2/LAYER2/rlc_v2/rlc_oai_api.c
index c81cc6ff5ebc47b2d40e3116a2d405858f214f61..bd3eebe6355f487690178f08f31246627b444438 100644
--- a/openair2/LAYER2/rlc_v2/rlc_oai_api.c
+++ b/openair2/LAYER2/rlc_v2/rlc_oai_api.c
@@ -134,7 +134,10 @@ tbs_size_t mac_rlc_data_req(
}
if (MBMS_flagP == MBMS_FLAG_YES) {
- rb = ue->drb[channel_idP - 1];
+ if (channel_idP >= 1 && channel_idP <= 5)
+ rb = ue->drb[channel_idP - 1];
+ else
+ rb = NULL;
}
@@ -192,7 +195,10 @@ mac_rlc_status_resp_t mac_rlc_status_ind(
}
if (MBMS_flagP == MBMS_FLAG_YES) {
- rb = ue->drb[channel_idP - 1];
+ if (channel_idP >= 1 && channel_idP <= 5)
+ rb = ue->drb[channel_idP - 1];
+ else
+ rb = NULL;
}
if (rb != NULL) {
@@ -316,7 +322,9 @@ rlc_op_status_t rlc_data_req (const protocol_ctxt_t *const ctxt_pP,
if (rb_idP >= 1 && rb_idP <= 5)
rb = ue->drb[rb_idP - 1];
}
+
if( MBMS_flagP == MBMS_FLAG_YES) {
+ if (rb_idP >= 1 && rb_idP <= 5)
rb = ue->drb[rb_idP - 1];
}
@@ -875,12 +883,19 @@ rlc_op_status_t rrc_rlc_config_asn1_req (const protocol_ctxt_t * const ctxt_pP
mbms_service_id = MBMS_SessionInfo_p->tmgi_r9.serviceId_r9.buf[2]; //serviceId is 3-octet string
// mbms_service_id = j;
+#if 0
+ /* TODO: check if this code should stay there
+ * as it is both enb and ue cases do the same thing
+ */
// can set the mch_id = i
if (ctxt_pP->enb_flag) {
drb_id = (mbms_service_id * LTE_maxSessionPerPMCH ) + mbms_session_id;//+ (LTE_maxDRB + 3) * MAX_MOBILES_PER_ENB; // 1
} else {
drb_id = (mbms_service_id * LTE_maxSessionPerPMCH ) + mbms_session_id; // + (LTE_maxDRB + 3); // 15
}
+#endif
+
+ drb_id = (mbms_service_id * LTE_maxSessionPerPMCH ) + mbms_session_id;
LOG_I(RLC, PROTOCOL_CTXT_FMT" CONFIG REQ MBMS ASN1 LC ID %u RB ID %u SESSION ID %u SERVICE ID %u, mbms_rnti %x\n",
PROTOCOL_CTXT_ARGS(ctxt_pP),
diff --git a/openair2/M2AP/m2ap_MCE_handler.h b/openair2/M2AP/m2ap_MCE_handler.h
index e9faae8f5d972c06655650583492914b92897e25..68cab5c8ac9abfcf40a3f43ad39affff3593ae27 100644
--- a/openair2/M2AP/m2ap_MCE_handler.h
+++ b/openair2/M2AP/m2ap_MCE_handler.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M2AP_MCE_HANDLERS_H_
-#define M2AP_MCE_HANDLERS_H_
+#ifndef __M2AP_MCE_HANDLERS__H__
+#define __M2AP_MCE_HANDLERS__H__
#include "m2ap_MCE_defs.h"
@@ -40,4 +40,4 @@ int m2ap_MCE_handle_message(instance_t instance, uint32_t assoc_id, int32_t stre
//const uint8_t * const data, const uint32_t data_length);
-#endif /* M2AP_MCE_HANDLERS_H_ */
+#endif /* __M2AP_MCE_HANDLERS__H__ */
diff --git a/openair2/M2AP/m2ap_MCE_interface_management.c b/openair2/M2AP/m2ap_MCE_interface_management.c
index 1bef8341794aea861c475fe077e850cbc3456f7b..e162c9a5de907d2e82559d499d229287e16d6802 100644
--- a/openair2/M2AP/m2ap_MCE_interface_management.c
+++ b/openair2/M2AP/m2ap_MCE_interface_management.c
@@ -521,6 +521,7 @@ int MCE_send_MBMS_SCHEDULING_INFORMATION(instance_t instance, /*uint32_t assoc_i
mbsfn_subframe_configuration->radioframeAllocationPeriod = m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period;
mbsfn_subframe_configuration->radioframeAllocationOffset = m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset;
if(m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf){
+ LOG_I(M2AP,"is_four_sf\n");
mbsfn_subframe_configuration->subframeAllocation.present = M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_fourFrames;
mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf = MALLOC(3);
mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation) & 0xFF);
@@ -530,6 +531,7 @@ int MCE_send_MBMS_SCHEDULING_INFORMATION(instance_t instance, /*uint32_t assoc_i
mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.bits_unused = 0;
}else{
+ LOG_I(M2AP,"is_one_sf\n");
mbsfn_subframe_configuration->subframeAllocation.present = M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_oneFrame;
mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.buf = MALLOC(1);
mbsfn_subframe_configuration->subframeAllocation.choice.oneFrame.size = 1;
@@ -1357,11 +1359,10 @@ int MCE_handle_MBMS_SESSION_UPDATE_RESPONSE(instance_t instance,
-int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,
- uint32_t assoc_id,
- uint32_t stream,
- M2AP_M2AP_PDU_t *pdu){
+int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,module_id_t du_mod_idP){
+
AssertFatal(1==0,"Not implemented yet\n");
+
}
/*
@@ -1378,16 +1379,138 @@ int MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE(instance_t instance,
uint32_t assoc_id,
uint32_t stream,
M2AP_M2AP_PDU_t *pdu){
- AssertFatal(1==0,"Not implemented yet\n");
+ //int i;
+ //AssertFatal(1==0,"Not implemented yet\n");
+ LOG_D(M2AP, "MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE\n");
+
+ AssertFatal(pdu->present == M2AP_M2AP_PDU_PR_successfulOutcome,
+ "pdu->present != M2AP_M2AP_PDU_PR_successfulOutcome\n");
+ AssertFatal(pdu->choice.successfulOutcome.procedureCode == M2AP_ProcedureCode_id_mbmsServiceCounting,
+ "pdu->choice.successfulOutcome->procedureCode != M2AP_ProcedureCode_id_mbmsServiceCounting\n");
+ AssertFatal(pdu->choice.successfulOutcome.criticality == M2AP_Criticality_reject,
+ "pdu->choice.successfulOutcome->criticality != M2AP_Criticality_reject\n");
+ AssertFatal(pdu->choice.successfulOutcome.value.present == M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse,
+ "pdu->choice.successfulOutcome.value.present != M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse\n");
+
+
+ M2AP_MbmsServiceCountingResponse_t *in = &pdu->choice.successfulOutcome.value.choice.MbmsServiceCountingResponse;
+ //M2AP_MbmsServiceCountingResponse_Ies_t *ie;
+ //int MCE_MBMS_M2AP_ID=-1;
+ //int ENB_MBMS_M2AP_ID=-1;
+
+
+ MessageDef *msg_g = itti_alloc_new_message(TASK_M2AP_MCE,M2AP_MBMS_SERVICE_COUNTING_RESP); //TODO
+
+ LOG_D(M2AP, "M2AP: MbmsServiceCounting-Resp: protocolIEs.list.count %d\n",
+ in->protocolIEs.list.count);
+ for (int i=0;i < in->protocolIEs.list.count; i++) {
+ //ie = in->protocolIEs.list.array[i];
+ // switch (ie->id) {
+ // case M2AP_ProtocolIE_ID_id_MCE_MBMS_M2AP_ID:
+ // AssertFatal(ie->criticality == M2AP_Criticality_reject,
+ // "ie->criticality != M2AP_Criticality_reject\n");
+ // AssertFatal(ie->value.present == M2AP_SessionStartResponse_Ies__value_PR_MCE_MBMS_M2AP_ID,
+ // "ie->value.present != M2AP_sessionStartResponse_IEs__value_PR_MCE_MBMS_M2AP_ID\n");
+ // MCE_MBMS_M2AP_ID=ie->value.choice.MCE_MBMS_M2AP_ID;
+ // LOG_D(M2AP, "M2AP: SessionStart-Resp: MCE_MBMS_M2AP_ID %d\n",
+ // MCE_MBMS_M2AP_ID);
+ // break;
+ // case M2AP_ProtocolIE_ID_id_ENB_MBMS_M2AP_ID:
+ // AssertFatal(ie->criticality == M2AP_Criticality_reject,
+ // "ie->criticality != M2AP_Criticality_reject\n");
+ // AssertFatal(ie->value.present == M2AP_SessionStartResponse_Ies__value_PR_ENB_MBMS_M2AP_ID,
+ // "ie->value.present != M2AP_sessionStartResponse_Ies__value_PR_ENB_MBMS_M2AP_ID\n");
+ // ENB_MBMS_M2AP_ID=ie->value.choice.ENB_MBMS_M2AP_ID;
+ // LOG_D(M2AP, "M2AP: SessionStart-Resp: ENB_MBMS_M2AP_ID %d\n",
+ // ENB_MBMS_M2AP_ID);
+ // break;
+ // }
+ }
+
+ //AssertFatal(MCE_MBMS_M2AP_ID!=-1,"MCE_MBMS_M2AP_ID was not sent\n");
+ //AssertFatal(ENB_MBMS_M2AP_ID!=-1,"ENB_MBMS_M2AP_ID was not sent\n");
+ //M2AP_SESSION_START_RESP(msg_p).
+// MSC_LOG_RX_MESSAGE(
+// MSC_M2AP_MCE,
+// MSC_M2AP_ENB,
+ //return 0;
+// 0,
+// 0,
+// MSC_AS_TIME_FMT" MCE_handle_M2_SESSION_START_RESPONSE successfulOutcome assoc_id %d",
+// 0,0,//MSC_AS_TIME_ARGS(ctxt_pP),
+// assoc_id);
+//
+ //LOG_D(M2AP, "Sending ITTI message to ENB_APP with assoc_id (%d->%d)\n",
+ //assoc_id,ENB_MODULE_ID_TO_INSTANCE(assoc_id));
+
+ itti_send_msg_to_task(TASK_MCE_APP, ENB_MODULE_ID_TO_INSTANCE(assoc_id), msg_g);
+ return 0;
+
}
-int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance,
- uint32_t assoc_id,
- uint32_t stream,
- M2AP_M2AP_PDU_t *pdu){
- AssertFatal(1==0,"Not implemented yet\n");
+int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, module_id_t du_mod_idP){
+
+ M2AP_M2AP_PDU_t pdu;
+ M2AP_MbmsServiceCountingRequest_t *out;
+ M2AP_MbmsServiceCountingRequest_Ies_t *ie;
+
+ uint8_t *buffer;
+ uint32_t len;
+ //int i=0;
+ //int j=0;
+
+ /* Create */
+ /* 0. pdu Type */
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage;
+ //pdu.choice.initiatingMessage = (M2AP_InitiatingMessage_t *)calloc(1, sizeof(M2AP_InitiatingMessage_t));
+ pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting;
+ pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject;
+ pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingRequest;
+ out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingRequest;
+
+ /* mandatory */
+ /* c1. MCCH_Update_Time */ //long
+ ie=(M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1,sizeof(M2AP_MbmsSchedulingInformation_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_MCCH_Update_Time;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time;
+ //ie->value.choice.MCCH_Update_Time = ;
+ //ie->value.choice.MCCH_Update_Time = m2ap_mbms_scheduling_information->mcch_update_time;
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+
+ /* mandatory */
+ /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long
+ ie = (M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingRequest_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_MBSFN_Area_ID;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID;
+ //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //?
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ /* mandatory */
+ /* c2. TMGI (integrer value) */
+ ie = (M2AP_MbmsServiceCountingRequest_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingRequest_Ies_t ));
+ ie->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Request_Session;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session;
+
+ //M2AP_MBMS_Counting_Request_Session_t * m2ap_mbms_counting_request_session = &ie->value.choice.MBMS_Counting_Request_Session;
+
+ //&ie->choice.TMGI.pLMN_Identity);
+ //INT16_TO_OCTET_STRING(0,&ie->choice.TMGI.serviceId);
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) {
+ LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n");
+ return -1;
+ }
+
+ return 0;
}
diff --git a/openair2/M2AP/m2ap_MCE_interface_management.h b/openair2/M2AP/m2ap_MCE_interface_management.h
index 6b899e9ea275e8646fbf73c6adf9f8ff0ec5c231..2b1d5824af0d224ff2bbbf06fd94b6c61ec904cc 100644
--- a/openair2/M2AP/m2ap_MCE_interface_management.h
+++ b/openair2/M2AP/m2ap_MCE_interface_management.h
@@ -150,10 +150,7 @@ int MCE_handle_MBMS_SESSION_UPDATE_RESPONSE(instance_t instance,
uint32_t stream,
M2AP_M2AP_PDU_t *pdu);
-int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,
- uint32_t assoc_id,
- uint32_t stream,
- M2AP_M2AP_PDU_t *pdu);
+int MCE_handle_MBMS_SESSION_UPDATE_FAILURE(instance_t instance,module_id_t du_mod_idP);
/*
* Service Counting Request
@@ -165,10 +162,7 @@ int MCE_handle_MBMS_SERVICE_COUNTING_RESPONSE(instance_t instance,
uint32_t stream,
M2AP_M2AP_PDU_t *pdu);
-int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance,
- uint32_t assoc_id,
- uint32_t stream,
- M2AP_M2AP_PDU_t *pdu);
+int MCE_handle_MBMS_SESSION_COUNTING_FAILURE(instance_t instance, module_id_t du_mod_idP);
/*
* Service Counting Results Report
*/
diff --git a/openair2/M2AP/m2ap_MCE_management_procedures.h b/openair2/M2AP/m2ap_MCE_management_procedures.h
index 9e13e723c966de7ce2da6c76858562fa93d48854..4e8997dbc5108b233a606d296692f3a4e3869921 100644
--- a/openair2/M2AP/m2ap_MCE_management_procedures.h
+++ b/openair2/M2AP/m2ap_MCE_management_procedures.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M2AP_MCE_MANAGEMENT_PROCEDURES_H_
-#define M2AP_MCE_MANAGEMENT_PROCEDURES_H
+#ifndef __M2AP_MCE_MANAGEMENT_PROCEDURES__H__
+#define __M2AP_MCE_MANAGEMENT_PROCEDURES__H__
void m2ap_MCE_prepare_internal_data(void);
@@ -51,4 +51,4 @@ struct m2ap_MCE_data_s *m2ap_get_MCE(m2ap_MCE_instance_t *instance_p,
int32_t assoc_id,
uint16_t cnx_id);
-#endif /* M2AP_MCE_MANAGEMENT_PROCEDURES_H_ */
+#endif /* __M2AP_MCE_MANAGEMENT_PROCEDURES__H__ */
diff --git a/openair2/M2AP/m2ap_eNB.c b/openair2/M2AP/m2ap_eNB.c
index 206b7cf8ca7e6b34f75c9064ba79d01c9bb27a66..39c769a43d67ae25e602fc980b84483fbff46951 100644
--- a/openair2/M2AP/m2ap_eNB.c
+++ b/openair2/M2AP/m2ap_eNB.c
@@ -142,6 +142,22 @@ void m2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa
sctp_new_association_resp->ulp_cnx_id);
//m2ap_handle_m2_setup_message(instance_p, m2ap_enb_data_p,
// sctp_new_association_resp->sctp_state == SCTP_STATE_SHUTDOWN);
+
+ sleep(4);
+ int index;
+ /* Trying to connect to the provided list of eNB ip address */
+ for (index = 0; index < instance_p->nb_m2; index++) {
+ //M2AP_INFO("eNB[%d] eNB id %u acting as an initiator (client)\n",
+ // instance_id, instance->eNB_id);
+ m2ap_eNB_register_eNB(instance_p,
+ &instance_p->target_mce_m2_ip_address[index],
+ &instance_p->enb_m2_ip_address,
+ instance_p->sctp_in_streams,
+ instance_p->sctp_out_streams,
+ instance_p->enb_port_for_M2C,
+ instance_p->multi_sd);
+ }
+
return;
}
@@ -304,6 +320,8 @@ void m2ap_eNB_handle_register_eNB(instance_t instance,
DevCheck(new_instance->mcc == m2ap_register_eNB->mcc, new_instance->mcc, m2ap_register_eNB->mcc, 0);
DevCheck(new_instance->mnc == m2ap_register_eNB->mnc, new_instance->mnc, m2ap_register_eNB->mnc, 0);
M2AP_WARN("eNB[%d] already registered\n", instance);
+
+
} else {
new_instance = calloc(1, sizeof(m2ap_eNB_instance_t));
DevAssert(new_instance != NULL);
diff --git a/openair2/M2AP/m2ap_eNB_generate_messages.h b/openair2/M2AP/m2ap_eNB_generate_messages.h
index 49247405f788d8e681ac928ff8117df846fe627f..793f7f18cf18cc0e14dda3979ad1b7fdcde9930e 100644
--- a/openair2/M2AP/m2ap_eNB_generate_messages.h
+++ b/openair2/M2AP/m2ap_eNB_generate_messages.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M2AP_ENB_GENERATE_MESSAGES_H_
-#define M2AP_ENB_GENERATE_MESSAGES_H_
+#ifndef __M2AP_ENB_GENERATE_MESSAGES__H__
+#define __M2AP_ENB_GENERATE_MESSAGES__H__
#include "m2ap_eNB_defs.h"
#include "m2ap_common.h"
@@ -60,4 +60,4 @@ int m2ap_eNB_set_cause (M2AP_Cause_t * cause_p,
// int m2_ue_id,
// m2ap_handover_cancel_cause_t cause);
-#endif /* M2AP_ENB_GENERATE_MESSAGES_H_ */
+#endif /* __M2AP_ENB_GENERATE_MESSAGES__H__ */
diff --git a/openair2/M2AP/m2ap_eNB_interface_management.c b/openair2/M2AP/m2ap_eNB_interface_management.c
index 95b83720258dead917526f44f08b9b9f242f8bf7..9649d919c3bf57d380cd28bac0d64d43786d6819 100644
--- a/openair2/M2AP/m2ap_eNB_interface_management.c
+++ b/openair2/M2AP/m2ap_eNB_interface_management.c
@@ -163,8 +163,12 @@ int eNB_handle_MBMS_SCHEDULING_INFORMATION(instance_t instance,
M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period = m2ap_mbsfn_sf_configuration->radioframeAllocationPeriod;
M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset = m2ap_mbsfn_sf_configuration->radioframeAllocationOffset;
if( m2ap_mbsfn_sf_configuration->subframeAllocation.present == M2AP_MBSFN_Subframe_Configuration__subframeAllocation_PR_fourFrames ) {
+ LOG_I(RRC,"is_four_sf\n");
+ M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf = 1;
M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation = m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0] | (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[1]<<8) | (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0]<<16);
}else{
+ LOG_I(RRC,"is_one_sf\n");
+ M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf = 0;
M2AP_MBMS_SCHEDULING_INFORMATION(message_p).mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation = (m2ap_mbsfn_sf_configuration->subframeAllocation.choice.oneFrame.buf[0] >> 2) & 0x3F;
}
}
@@ -1262,46 +1266,226 @@ int eNB_handle_MBMS_SERVICE_COUNTING_REQ(instance_t instance,
uint32_t stream,
M2AP_M2AP_PDU_t *pdu)
{
- LOG_D(M2AP, "eNB_handle_MBMS_SERVICE_COUNTING_REQUEST assoc_id %d\n",assoc_id);
- MessageDef *message_p;
+ LOG_D(M2AP, "eNB_handle_MBMS_SERVICE_COUNTING_REQUEST assoc_id %d\n",assoc_id);
+
+ //MessageDef *message_p;
//M2AP_MbmsServiceCountingRequest_t *container;
//M2AP_MbmsServiceCountingRequest_Ies_t *ie;
+ M2AP_MbmsServiceCountingRequest_t *in;
+ M2AP_MbmsServiceCountingRequest_Ies_t *ie;
//int i = 0;
+ int j;
DevAssert(pdu != NULL);
// container = &pdu->choice.initiatingMessage.value.choice.MbmsServiceCountingRequest;
+ in = &pdu->choice.initiatingMessage.value.choice.MbmsServiceCountingRequest;
/* M2 Setup Request == Non UE-related procedure -> stream 0 */
if (stream != 0) {
- LOG_D(M2AP, "[SCTP %d] Received MMBS session start request on stream != 0 (%d)\n",
+ LOG_D(M2AP, "[SCTP %d] Received MMBS service Counting Request on stream != 0 (%d)\n",
assoc_id, stream);
}
- message_p = itti_alloc_new_message (TASK_M2AP_ENB, M2AP_MBMS_SERVICE_COUNTING_REQ);
+ for (j=0;j < in->protocolIEs.list.count; j++) {
+ ie = in->protocolIEs.list.array[j];
+ switch (ie->id) {
+ case M2AP_ProtocolIE_ID_id_MCCH_Update_Time:
+ AssertFatal(ie->criticality == M2AP_Criticality_reject,
+ "ie->criticality != M2AP_Criticality_reject\n");
+ AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time,
+ "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MCCH_Update_Time\n");
+ LOG_D(M2AP, "M2AP: : MCCH_Update_Time \n");
+ break;
+ case M2AP_ProtocolIE_ID_id_MBSFN_Area_ID:
+ AssertFatal(ie->criticality == M2AP_Criticality_reject,
+ "ie->criticality != M2AP_Criticality_reject\n");
+ AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID,
+ "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBSFN_Area_ID\n");
+ LOG_D(M2AP, "M2AP: : MBSFN_Area_ID \n");
+ break;
+ case M2AP_ProtocolIE_ID_id_MBMS_Counting_Request_Session:
+ AssertFatal(ie->criticality == M2AP_Criticality_reject,
+ "ie->criticality != M2AP_Criticality_reject\n");
+ AssertFatal(ie->value.present == M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session,
+ "ie->value.present != M2AP_MbmsServiceCountingRequest_Ies__value_PR_MBMS_Counting_Request_Session\n");
+ LOG_D(M2AP, "M2AP: : MBMS_Counting_Request_Session \n");
+ //ie->value.choice.MBMS_Counting_Request_Session.list.count;
- itti_send_msg_to_task(TASK_ENB_APP, ENB_MODULE_ID_TO_INSTANCE(instance), message_p);
+ break;
+
+ }
+ }
+ //message_p = itti_alloc_new_message (TASK_M2AP_ENB, M2AP_MBMS_SERVICE_COUNTING_REQ);
+
return 0;
}
int eNB_send_MBMS_SERVICE_COUNTING_REPORT(instance_t instance, m2ap_mbms_service_counting_report_t * m2ap_mbms_service_counting_report)
{
- AssertFatal(1==0,"Not implemented yet\n");
+ M2AP_M2AP_PDU_t pdu;
+ M2AP_MbmsServiceCountingResultsReport_t *out;
+ M2AP_MbmsServiceCountingResultsReport_Ies_t *ie;
+
+ uint8_t *buffer;
+ uint32_t len;
+ //int i = 0;
+ //
+ // memset(&pdu, 0, sizeof(pdu));
+ pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage;
+ //pdu.choice.initiatingMessage = (M2AP_InitiatingMessage_t *)calloc(1, sizeof(M2AP_InitiatingMessage_t));
+ pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCountingResultsReport;
+ pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject;
+ pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingResultsReport;
+ out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingResultsReport;
+
+
+ /* Create */
+ /* 0. Message Type */
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = M2AP_M2AP_PDU_PR_initiatingMessage;
+ //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t));
+ pdu.choice.initiatingMessage.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCountingResultsReport;
+ pdu.choice.initiatingMessage.criticality = M2AP_Criticality_reject;
+ pdu.choice.initiatingMessage.value.present = M2AP_InitiatingMessage__value_PR_MbmsServiceCountingResultsReport;
+ out = &pdu.choice.initiatingMessage.value.choice.MbmsServiceCountingResultsReport;
+
+ /* mandatory */
+ /* c1. MBSFN_Area_ID (integer value) */ //long
+ ie = (M2AP_MbmsServiceCountingResultsReport_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingResultsReport_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_MBSFN_Area_ID;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingResultsReport_Ies__value_PR_MBSFN_Area_ID;
+ //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //?
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ /* mandatory */
+ /* c1. MBSFN_Area_ID (integer value) */ //long
+ ie = (M2AP_MbmsServiceCountingResultsReport_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingResultsReport_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Result_List;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingResultsReport_Ies__value_PR_MBMS_Counting_Result_List;
+ //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //?
+ M2AP_MBMS_Counting_Result_List_t * m2ap_mbms_counting_result_list = &ie->value.choice.MBMS_Counting_Result_List;
+
+ M2AP_MBMS_Counting_Result_Item_t * m2ap_mbms_counting_result_item = (M2AP_MBMS_Counting_Result_Item_t*)calloc(1,sizeof(M2AP_MBMS_Counting_Result_Item_t));
+ m2ap_mbms_counting_result_item->id = M2AP_ProtocolIE_ID_id_MBMS_Counting_Result_Item;
+ m2ap_mbms_counting_result_item->criticality = M2AP_Criticality_reject;
+ m2ap_mbms_counting_result_item->value.present = M2AP_MBMS_Counting_Result_Item__value_PR_MBMS_Counting_Result;
+ M2AP_MBMS_Counting_Result_t * m2ap_mbms_counting_result = &m2ap_mbms_counting_result_item->value.choice.MBMS_Counting_Result;
+
+ M2AP_TMGI_t * tmgi = &m2ap_mbms_counting_result->tmgi;
+ MCC_MNC_TO_PLMNID(0,0,3,&tmgi->pLMNidentity);/*instance_p->mcc, instance_p->mnc, instance_p->mnc_digit_length,*/
+ uint8_t TMGI[5] = {4,3,2,1,0};
+ OCTET_STRING_fromBuf(&tmgi->serviceID,(const char*)&TMGI[2],3);
+
+ //M2AP_CountingResult_t * m2ap_counting_result = &m2ap_mbms_counting_result->countingResult;
+
+ ASN_SEQUENCE_ADD(&m2ap_mbms_counting_result_list->list,m2ap_mbms_counting_result_item);
+
+
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) {
+ LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n");
+ return -1;
+ }
return 0;
}
+
int eNB_send_MBMS_SERVICE_COUNTING_RESP(instance_t instance, m2ap_mbms_service_counting_resp_t * m2ap_mbms_service_counting_resp)
{
AssertFatal(1==0,"Not implemented yet\n");
+ M2AP_M2AP_PDU_t pdu;
+ M2AP_MbmsServiceCountingResponse_t *out;
+ M2AP_MbmsServiceCountingResponse_Ies_t *ie;
+
+ uint8_t *buffer;
+ uint32_t len;
+ //int i = 0;
+
+ /* Create */
+ /* 0. Message Type */
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = M2AP_M2AP_PDU_PR_successfulOutcome;
+ //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t));
+ pdu.choice.successfulOutcome.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting;
+ pdu.choice.successfulOutcome.criticality = M2AP_Criticality_reject;
+ pdu.choice.successfulOutcome.value.present = M2AP_SuccessfulOutcome__value_PR_MbmsServiceCountingResponse;
+ out = &pdu.choice.successfulOutcome.value.choice.MbmsServiceCountingResponse;
+
+
+ /* mandatory */
+ /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long
+ ie = (M2AP_MbmsServiceCountingResponse_Ies_t*)calloc(1, sizeof(M2AP_MbmsServiceCountingResponse_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_MCE_MBMS_M2AP_ID;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingResponse_Ies__value_PR_CriticalityDiagnostics;
+ //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //?
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) {
+ LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n");
+ return -1;
+ }
+
+ return 0;
return 0;
}
+
int eNB_send_MBMS_SERVICE_COUNTING_FAILURE(instance_t instance, m2ap_mbms_service_counting_failure_t * m2ap_mbms_service_counting_failure)
{
- AssertFatal(1==0,"Not implemented yet\n");
+ M2AP_M2AP_PDU_t pdu;
+ M2AP_MbmsServiceCountingFailure_t *out;
+ M2AP_MbmsServiceCountingFailure_Ies_t *ie;
+
+ uint8_t *buffer;
+ uint32_t len;
+ //int i = 0;
+
+ /* Create */
+ /* 0. Message Type */
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = M2AP_M2AP_PDU_PR_unsuccessfulOutcome;
+ //pdu.choice.successfulOutcome = (M2AP_SuccessfulOutcome_t *)calloc(1, sizeof(M2AP_SuccessfulOutcome_t));
+ pdu.choice.unsuccessfulOutcome.procedureCode = M2AP_ProcedureCode_id_mbmsServiceCounting;
+ pdu.choice.unsuccessfulOutcome.criticality = M2AP_Criticality_reject;
+ pdu.choice.unsuccessfulOutcome.value.present = M2AP_UnsuccessfulOutcome__value_PR_MbmsServiceCountingFailure;
+ out = &pdu.choice.unsuccessfulOutcome.value.choice.MbmsServiceCountingFailure;
+
+
+ /* mandatory */
+ /* c1. MCE_MBMS_M2AP_ID (integer value) */ //long
+ ie = (M2AP_MbmsServiceCountingFailure_Ies_t*)calloc(1, sizeof(M2AP_MbmsServiceCountingFailure_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_ENB_MBMS_M2AP_ID;
+ ie->criticality = M2AP_Criticality_reject;
+ ie->value.present = M2AP_MbmsServiceCountingFailure_Ies__value_PR_CriticalityDiagnostics;
+ //ie->value.choice.MCE_MBMS_M2AP_ID = /*F1AP_get_next_transaction_identifier(enb_mod_idP, du_mod_idP);*/ //?
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ /* mandatory */
+ /* c2. Cause */
+ ie = (M2AP_MbmsServiceCountingFailure_Ies_t *)calloc(1, sizeof(M2AP_MbmsServiceCountingFailure_Ies_t));
+ ie->id = M2AP_ProtocolIE_ID_id_Cause;
+ ie->criticality = M2AP_Criticality_ignore;
+ ie->value.present = M2AP_MbmsServiceCountingFailure_Ies__value_PR_Cause;
+ ie->value.choice.Cause.present = M2AP_Cause_PR_radioNetwork;
+ ie->value.choice.Cause.choice.radioNetwork = M2AP_CauseRadioNetwork_unspecified;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+
+ if (m2ap_encode_pdu(&pdu, &buffer, &len) < 0) {
+ LOG_E(M2AP, "Failed to encode MBMS Service Counting Results Report\n");
+ return -1;
+ }
+
+
return 0;
}
diff --git a/openair2/M2AP/m2ap_eNB_management_procedures.h b/openair2/M2AP/m2ap_eNB_management_procedures.h
index fbc49d01698f3883f27761eea86dd2b2c039b8fa..2b1dc4a44bcdfe3daebc6f5f3e51cfe28b673dfa 100644
--- a/openair2/M2AP/m2ap_eNB_management_procedures.h
+++ b/openair2/M2AP/m2ap_eNB_management_procedures.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M2AP_ENB_MANAGEMENT_PROCEDURES_H_
-#define M2AP_ENB_MANAGEMENT_PROCEDURES_H
+#ifndef __M2AP_ENB_MANAGEMENT_PROCEDURES__H__
+#define __M2AP_ENB_MANAGEMENT_PROCEDURES__H__
void m2ap_eNB_prepare_internal_data(void);
@@ -51,4 +51,4 @@ struct m2ap_eNB_data_s *m2ap_get_eNB(m2ap_eNB_instance_t *instance_p,
int32_t assoc_id,
uint16_t cnx_id);
-#endif /* M2AP_ENB_MANAGEMENT_PROCEDURES_H_ */
+#endif /* __M2AP_ENB_MANAGEMENT_PROCEDURES__H__ */
diff --git a/openair2/MCE_APP/mce_app.c b/openair2/MCE_APP/mce_app.c
index 6f7454c321a7a3fd9e22b480f42e0082b8792348..817c863f7b31052ccd5bf2da90e9910746f23032 100644
--- a/openair2/MCE_APP/mce_app.c
+++ b/openair2/MCE_APP/mce_app.c
@@ -372,7 +372,8 @@ void *MCE_app_task(void *args_p) {
// /* Try to register each MCE with MCE each other */
if (is_m3ap_MCE_enabled() /*&& !NODE_IS_DU(RC.rrc[0]->node_type)*/) {
- ///*m3_register_mce_pending =*/ MCE_app_register_m3 (mce_id_start, mce_id_end);
+ ///*m3_register_mce_pending =*/
+ MCE_app_register_m3 (mce_id_start, mce_id_end);
}
do {
@@ -627,7 +628,7 @@ void *MCE_app_task(void *args_p) {
//}
- /*m3_register_mce_pending =*/ MCE_app_register_m3 (mce_id_start, mce_id_end);
+ /*m3_register_mce_pending =*/ //MCE_app_register_m3 (mce_id_start, mce_id_end);
//MCE_app_send_m2ap_session_start_req(0);
break;
diff --git a/openair2/NETWORK_DRIVER/LITE/proto_extern.h b/openair2/NETWORK_DRIVER/LITE/proto_extern.h
index f07083921f3f81adc07a34c25aea4358609eb04c..d4289ca1f2d8d8519d1eb69b405a5c8cef0ac198 100644
--- a/openair2/NETWORK_DRIVER/LITE/proto_extern.h
+++ b/openair2/NETWORK_DRIVER/LITE/proto_extern.h
@@ -30,8 +30,8 @@
***************************************************************************/
-#ifndef _NAS_PROTO_H
-#define _NAS_PROTO_H
+#ifndef __NETWORK_DRIVER_LITE_PROTO_EXTERN__H__
+#define __NETWORK_DRIVER_LITE_PROTO_EXTERN__H__
#include <linux/if_arp.h>
#include <linux/types.h>
diff --git a/openair2/NETWORK_DRIVER/MESH/proto_extern.h b/openair2/NETWORK_DRIVER/MESH/proto_extern.h
index 2eae034257f291610ad0f765af37c5bda116b5cd..ac92b2f8bdceec295bb94d0cffd0ca83038f5c2b 100644
--- a/openair2/NETWORK_DRIVER/MESH/proto_extern.h
+++ b/openair2/NETWORK_DRIVER/MESH/proto_extern.h
@@ -29,8 +29,8 @@
***************************************************************************/
-#ifndef _NAS_PROTO_H
-#define _NAS_PROTO_H
+#ifndef __NETWORK_DRIVER_MESH_PROTO_EXTERN__H__
+#define __NETWORK_DRIVER_MESH_PROTO_EXTERN__H__
#include <linux/if_arp.h>
#include <linux/types.h>
diff --git a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c
index 4dacef3dbb885be77fad003e260f51157025baa6..ec969c674128694cf39bfcd412c805862258a70e 100644
--- a/openair2/NR_PHY_INTERFACE/NR_IF_Module.c
+++ b/openair2/NR_PHY_INTERFACE/NR_IF_Module.c
@@ -38,6 +38,7 @@
#include "LAYER2/MAC/mac_proto.h"
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "common/ran_context.h"
+#include "executables/softmodem-common.h"
#define MAX_IF_MODULES 100
@@ -62,90 +63,74 @@ void handle_nr_rach(NR_UL_IND_t *UL_info) {
if (UL_info->rach_ind.pdu_list[0].num_preamble>0)
AssertFatal(UL_info->rach_ind.pdu_list[0].num_preamble==1,
"More than 1 preamble not supported\n");
-
- /*nr_initiate_ra_proc(UL_info->module_id,
+
+ nr_initiate_ra_proc(UL_info->module_id,
UL_info->CC_id,
UL_info->rach_ind.sfn,
UL_info->rach_ind.slot,
UL_info->rach_ind.pdu_list[0].preamble_list[0].preamble_index,
UL_info->rach_ind.pdu_list[0].freq_index,
UL_info->rach_ind.pdu_list[0].symbol_index,
- UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance);*/
+ UL_info->rach_ind.pdu_list[0].preamble_list[0].timing_advance);
}
}
-void handle_nr_sr(NR_UL_IND_t *UL_info) {
-
+void handle_nr_uci(NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl) {
+ // TODO
+ int max_harq_rounds = 4; // TODO define macro
+ int num_ucis = UL_info->uci_ind.num_ucis;
+ nfapi_nr_uci_t *uci_list = UL_info->uci_ind.uci_list;
+
+ for (int i = 0; i < num_ucis; i++) {
+ switch (uci_list[i].pdu_type) {
+ case NFAPI_NR_UCI_PDCCH_PDU_TYPE: break;
+
+ case NFAPI_NR_UCI_FORMAT_0_1_PDU_TYPE: {
+ if (get_softmodem_params()->phy_test == 0) {
+ nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_pdu = &uci_list[i].pucch_pdu_format_0_1;
+ // handle harq
+ int harq_idx_s = 0;
+ // iterate over received harq bits
+ for (int harq_bit = 0; harq_bit < uci_pdu->harq->num_harq; harq_bit++) {
+ // search for the right harq process
+ for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) {
+ if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
+ if (uci_pdu->harq->harq_list[harq_bit].harq_value == 0)
+ sched_ctrl->harq_processes[harq_idx].round++;
+ if ((uci_pdu->harq->harq_list[harq_bit].harq_value == 1) ||
+ (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds)) {
+ sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
+ sched_ctrl->harq_processes[harq_idx].round = 0;
+ }
+ sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
+ harq_idx_s = harq_idx + 1;
+ break;
+ }
+ // if gNB fails to receive a ACK/NACK
+ else if (((UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot) &&
+ (sched_ctrl->harq_processes[harq_idx].is_waiting)) {
+ sched_ctrl->harq_processes[harq_idx].round++;
+ if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
+ sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
+ sched_ctrl->harq_processes[harq_idx].round = 0;
+ }
+ sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
+ }
+ }
+ }
+ }
+ break;
+ }
- /* if (nfapi_mode == 1) // PNF
- {
- if (UL_info->sr_ind.sr_indication_body.number_of_srs>0)
- {
- // oai_nfapi_sr_indication(&UL_info->sr_ind);
+ case NFAPI_NR_UCI_FORMAT_2_3_4_PDU_TYPE: break;
}
- }
- else
- {
-
-
- for (int i=0;i<UL_info->sr_ind.sr_indication_body.number_of_srs;i++)
- SR_indication(UL_info->module_id,
- UL_info->CC_id,
- UL_info->frame,
- UL_info->slot,
- UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].rx_ue_information.rnti,
- UL_info->sr_ind.sr_indication_body.sr_pdu_list[i].ul_cqi_information.ul_cqi);
-
-
-
}
- UL_info->sr_ind.sr_indication_body.number_of_srs=0;*/
+ UL_info->uci_ind.num_ucis = 0;
}
-void handle_nr_cqi(NR_UL_IND_t *UL_info) {
-
- /*
- for (int i=0;i<UL_info->cqi_ind.number_of_cqis;i++)
- cqi_indication(UL_info->module_id,
- UL_info->CC_id,
- UL_info->frame,
- UL_info->slot,
- UL_info->cqi_ind.cqi_pdu_list[i].rx_ue_information.rnti,
- &UL_info->cqi_ind.cqi_pdu_list[i].cqi_indication_rel9,
- UL_info->cqi_ind.cqi_raw_pdu_list[i].pdu,
- &UL_info->cqi_ind.cqi_pdu_list[i].ul_cqi_information);
-
- UL_info->cqi_ind.number_of_cqis=0;*/
-
-}
-
-void handle_nr_harq(NR_UL_IND_t *UL_info) {
- /* if (nfapi_mode == 1 && UL_info->harq_ind.harq_indication_body.number_of_harqs>0) { // PNF
- //LOG_D(PHY, "UL_info->harq_ind.harq_indication_body.number_of_harqs:%d Send to VNF\n", UL_info->harq_ind.harq_indication_body.number_of_harqs);
- int retval = oai_nfapi_harq_indication(&UL_info->harq_ind);
-
- if (retval!=0) {
- LOG_E(PHY, "Failed to encode NFAPI HARQ_IND retval:%d\n", retval);
- }
-
- UL_info->harq_ind.harq_indication_body.number_of_harqs = 0;
- }
- else
- {
-
- for (int i=0;i<UL_info->harq_ind.harq_indication_body.number_of_harqs;i++)
- harq_indication(UL_info->module_id,
- UL_info->CC_id,
- NFAPI_SFNSF2SFN(UL_info->harq_ind.sfn_sf),
- NFAPI_SFNSF2SF(UL_info->harq_ind.sfn_sf),
- &UL_info->harq_ind.harq_indication_body.harq_pdu_list[i]);
-
- UL_info->harq_ind.harq_indication_body.number_of_harqs=0;
- }*/
-}
void handle_nr_ulsch(NR_UL_IND_t *UL_info) {
if(nfapi_mode == 1) {
@@ -224,9 +209,10 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
NR_Sched_Rsp_t *sched_info = &Sched_INFO[module_id][CC_id];
NR_IF_Module_t *ifi = if_inst[module_id];
gNB_MAC_INST *mac = RC.nrmac[module_id];
- LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rx_ind:%d crcs:%d]\n",
+
+ LOG_D(PHY,"SFN/SF:%d%d module_id:%d CC_id:%d UL_info[rach_pdus:%d rx_ind:%d crcs:%d]\n",
UL_info->frame,UL_info->slot,
- module_id,CC_id,
+ module_id,CC_id, UL_info->rach_ind.number_of_pdus,
UL_info->rx_ind.number_of_pdus, UL_info->crc_ind.number_crcs);
if (nfapi_mode != 1) {
@@ -244,9 +230,7 @@ void NR_UL_indication(NR_UL_IND_t *UL_info) {
// clear DL/UL info for new scheduling round
clear_nr_nfapi_information(mac,CC_id,UL_info->frame,UL_info->slot);
handle_nr_rach(UL_info);
- handle_nr_sr(UL_info);
- handle_nr_cqi(UL_info);
- handle_nr_harq(UL_info);
+ handle_nr_uci(UL_info, &mac->UE_list.UE_sched_ctrl[0]);
// clear HI prior to handling ULSCH
mac->UL_dci_req[CC_id].numPdus = 0;
handle_nr_ulsch(UL_info);
diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
index 64a814bcdb9ef2358082910fe65420d3381efa58..e63f93b02819877c6bb70919850a3680d1547729 100644
--- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
@@ -32,9 +32,9 @@
#include "PHY/defs_nr_UE.h"
#include "NR_IF_Module.h"
-#include "mac_proto.h"
+#include "NR_MAC_UE/mac_proto.h"
#include "assertions.h"
-#include "LAYER2/NR_MAC_UE/mac_extern.h"
+#include "NR_MAC_UE/mac_extern.h"
#include "SCHED_NR_UE/fapi_nr_ue_l1.h"
#include "executables/softmodem-common.h"
@@ -93,6 +93,14 @@ int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_n
*/
}
+int8_t handle_rar (nr_downlink_indication_t *dl_info){
+
+ LOG_D(MAC, "handling RAR at MAC layer \n");
+ nr_process_rar (dl_info);
+ return 0;
+
+}
+
int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){
NR_UE_L2_STATE_t ret;
@@ -105,14 +113,11 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){
mac->dl_config_request.number_pdus = 0;
// clean previous FAPI messages
- ret = nr_ue_scheduler(
- ul_info->module_id,
- ul_info->gNB_index,
- ul_info->cc_id,
- ul_info->frame,
- ul_info->slot,
- ul_info->ssb_index,
- 0, 0); // TODO check tx/rx frame/slot is need for NR version
+ ret = nr_ue_scheduler(NULL, ul_info);
+
+ if (is_nr_UL_slot(mac->scc, ul_info->slot_tx) && get_softmodem_params()->do_ra){
+ nr_ue_prach_scheduler(module_id, ul_info->frame_tx, ul_info->slot_tx);
+ }
switch(ret){
case UE_CONNECTION_OK:
@@ -127,14 +132,13 @@ int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){
break;
}
-
mac->if_module->scheduled_response(&mac->scheduled_response);
return 0;
}
int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_t *ul_time_alignment){
-
+
int32_t i;
uint32_t ret_mask = 0x0;
module_id_t module_id = dl_info->module_id;
@@ -142,132 +146,98 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_
fapi_nr_dl_config_request_t *dl_config = &mac->dl_config_request;
fapi_nr_ul_config_request_t *ul_config = &mac->ul_config_request;
- dl_config->number_pdus = 0;
- ul_config->number_pdus = 0;
- //hook up pointers
- mac->scheduled_response.dl_config = dl_config;
- mac->scheduled_response.ul_config = ul_config;
- mac->scheduled_response.tx_request = &mac->tx_request;
- mac->scheduled_response.module_id = dl_info->module_id;
- mac->scheduled_response.CC_id = dl_info->cc_id;
- mac->scheduled_response.frame = dl_info->frame;
- mac->scheduled_response.slot = dl_info->slot;
-
- if(dl_info->dci_ind != NULL){
- LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
- for(i=0; i<dl_info->dci_ind->number_of_dcis; ++i){
- LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis);
- // fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci;
-
- ret_mask |= (handle_dci(dl_info->module_id,
- dl_info->cc_id,
- dl_info->gNB_index,
- dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND);
-
- AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
- nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
-
-
- /*switch((dl_info->dci_ind->dci_list+i)->dci_type){
- case FAPI_NR_DCI_TYPE_0_0:
- case FAPI_NR_DCI_TYPE_0_1:
- case FAPI_NR_DCI_TYPE_1_1:
- case FAPI_NR_DCI_TYPE_2_0:
- case FAPI_NR_DCI_TYPE_2_1:
- case FAPI_NR_DCI_TYPE_2_2:
- case FAPI_NR_DCI_TYPE_2_3:
- AssertFatal(1==0, "Not yet support at this moment!\n");
- break;
-
- case FAPI_NR_DCI_TYPE_1_0:
-
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
-
- // mapping into DL_CONFIG_REQ for DL-SCH
- fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.dlsch_config_rel15;
-
- dl_config->dl_config_list[dl_config->number_pdus].dlsch_config_pdu.rnti = 0x0000; // TX RNTI: UE-spec
- memcpy(dlsch_config_pdu, dci, sizeof(fapi_nr_dci_pdu_rel15_t));
-
- dl_config->number_pdus = dl_config->number_pdus + 1;
-
- ret_mask |= (handle_dci(
- dl_info->module_id,
- dl_info->cc_id,
- dl_info->gNB_index,
- dci,
- (dl_info->dci_ind->dci_list+i)->rnti,
- (dl_info->dci_ind->dci_list+i)->dci_type)) << FAPI_NR_DCI_IND;
-
-
-
- break;
-
- default:
- break;
- }*/
-
- //(dl_info->dci_list+i)->rnti
+ if (!dl_info->dci_ind && !dl_info->rx_ind) {
+ // UL indication to schedule DCI reception
+ nr_ue_scheduler(dl_info, NULL);
+ } else {
+ // UL indication after reception of DCI or DL PDU
+ dl_config->number_pdus = 0;
+ ul_config->number_pdus = 0;
+ //hook up pointers
+ mac->scheduled_response.dl_config = dl_config;
+ mac->scheduled_response.ul_config = ul_config;
+ mac->scheduled_response.tx_request = &mac->tx_request;
+ mac->scheduled_response.module_id = dl_info->module_id;
+ mac->scheduled_response.CC_id = dl_info->cc_id;
+ mac->scheduled_response.frame = dl_info->frame;
+ mac->scheduled_response.slot = dl_info->slot;
+
+ if(dl_info->dci_ind != NULL){
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
+ for(i=0; i<dl_info->dci_ind->number_of_dcis; ++i){
+ LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis);
+
+ ret_mask |= (handle_dci(dl_info->module_id,
+ dl_info->cc_id,
+ dl_info->gNB_index,
+ dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND);
+
+ AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
+ nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
+ }
}
- }
- if(dl_info->rx_ind != NULL){
- LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
- for(i=0; i<dl_info->rx_ind->number_pdus; ++i){
- switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){
- case FAPI_NR_RX_PDU_TYPE_MIB:
- ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
- (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu,
- (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits,
- (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index,
- (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length,
- (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;
- LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
- /*ret_mask |= (handle_bcch_bch( dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
- dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu,
- dl_info->rx_ind->rx_indication_body[i].mib_pdu.additional_bits,
- dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_index,
- dl_info->rx_ind->rx_indication_body[i].mib_pdu.ssb_length,
- dl_info->rx_ind->rx_indication_body[i].mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;*/
- break;
- case FAPI_NR_RX_PDU_TYPE_SIB:
- ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
- (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask,
- (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu,
- (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length )) << FAPI_NR_RX_PDU_TYPE_SIB;
- break;
- case FAPI_NR_RX_PDU_TYPE_DLSCH:
- // ret_mask |= (0) << FAPI_NR_RX_PDU_TYPE_DLSCH;
- ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind,
- (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu,
- (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot, ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
-
- LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
-
- /*
- // dl_config structure just stores what was received - not really needed
- dl_config->dl_config_list[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
- dl_config->number_pdus = dl_config->number_pdus + 1;
- */
-
- /*ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index, dl_info->dci_ind,
- dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu,
- dl_info->rx_ind->rx_indication_body[i].pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
-
- */
- break;
- default:
-
- break;
+ if(dl_info->rx_ind != NULL){
+
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+
+ for(i=0; i<dl_info->rx_ind->number_pdus; ++i){
+
+ switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){
+
+ case FAPI_NR_RX_PDU_TYPE_MIB:
+ ret_mask |= (handle_bcch_bch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
+ (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.pdu,
+ (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.additional_bits,
+ (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index,
+ (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length,
+ (dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id)) << FAPI_NR_RX_PDU_TYPE_MIB;
+
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+
+ break;
+ case FAPI_NR_RX_PDU_TYPE_SIB:
+
+ ret_mask |= (handle_bcch_dlsch(dl_info->module_id,
+ dl_info->cc_id, dl_info->gNB_index,
+ (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.sibs_mask,
+ (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu,
+ (dl_info->rx_ind->rx_indication_body+i)->sib_pdu.pdu_length)) << FAPI_NR_RX_PDU_TYPE_SIB;
+
+ break;
+
+ case FAPI_NR_RX_PDU_TYPE_DLSCH:
+
+ ret_mask |= (handle_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
+ dl_info->dci_ind,
+ (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu,
+ (dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length,
+ dl_info->frame,
+ dl_info->slot,
+ ul_time_alignment)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
+
+ LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
+
+ break;
+
+ case FAPI_NR_RX_PDU_TYPE_RAR:
+
+ ret_mask |= (handle_rar(dl_info)) << FAPI_NR_RX_PDU_TYPE_RAR;
+
+ break;
+
+ default:
+ break;
+ }
}
}
- }
- //clean up nr_downlink_indication_t *dl_info
- dl_info->rx_ind = NULL;
- dl_info->dci_ind = NULL;
+ //clean up nr_downlink_indication_t *dl_info
+ dl_info->rx_ind = NULL;
+ dl_info->dci_ind = NULL;
+ }
return 0;
}
@@ -305,7 +275,12 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
dl_config->sfn=UE_mac->dl_config_request.sfn;
dl_config->slot=UE_mac->dl_config_request.slot;
dl_config->number_pdus=0;
-
- ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot);
+
+ //printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot);
+
+ LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot);
+
+ ue_dci_configuration(UE_mac, dl_config, dcireq->frame, dcireq->slot);
+
return 0;
}
diff --git a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
index 0784e715846029bf68f7c99cf8e6f2791d5a04ec..df2d78f0cb35ef7e6a9564f38f6226e839fe863a 100755
--- a/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
+++ b/openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
@@ -72,7 +72,8 @@ typedef struct {
/// NR UE FAPI-like P7 message, direction: L1 to L2
/// data reception indication structure
fapi_nr_rx_indication_t *rx_ind;
-
+ /// ssb_index, if ssb is not present in current TTI, value set to -1
+ int ssb_index;
/// dci reception indication structure
fapi_nr_dci_indication_t *dci_ind;
@@ -87,11 +88,13 @@ typedef struct {
/// component carrier id
int cc_id;
/// frame
- frame_t frame;
- /// slot
- uint32_t slot;
- /// ssb_index, if ssb is not present in current TTI, thie value set to -1
- int ssb_index;
+ frame_t frame_rx;
+ /// slot rx
+ uint32_t slot_rx;
+ /// frame tx
+ frame_t frame_tx;
+ /// slot tx
+ uint32_t slot_tx;
/// dci reception indication structure
fapi_nr_dci_indication_t *dci_ind;
} nr_uplink_indication_t;
diff --git a/openair2/PHY_INTERFACE/phy_stub_UE.c b/openair2/PHY_INTERFACE/phy_stub_UE.c
index 41fb3ddc3a7eebfcdd376c32a3009e75aa602eb4..de42d676248706f90b6409406c6d13a65b69cdd7 100644
--- a/openair2/PHY_INTERFACE/phy_stub_UE.c
+++ b/openair2/PHY_INTERFACE/phy_stub_UE.c
@@ -800,7 +800,37 @@ void dl_config_req_UE_MAC_dci(int sfn,
UE_mac_inst[ue_id].first_ULSCH_Tx = 1;
}
}
- } else {
+ }
+ //else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_BCH_PDU_TYPE) {
+ // // BCH case: Last parameter is 1 if first time synchronization and zero
+ // // otherwise. Not sure which value to put for our case.
+ // if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED){
+ // dl_phy_sync_success(Mod_id, sfn, 0, 1);
+ // LOG_E(MAC,
+ // "%s(): Received MIB: UE_mode: %d, sfn/sf: %d.%d\n",
+ // __func__,
+ // UE_mac_inst[Mod_id].UE_mode[0],
+ // sfn,
+ // sf);
+ // UE_mac_inst[Mod_id].UE_mode[0] = PRACH;
+ // } else {
+ // dl_phy_sync_success(Mod_id, sfn, 0, 0);
+ // }
+ //} else if (dl_config_pdu_list[i].pdu_type == NFAPI_DL_CONFIG_MCH_PDU_TYPE){
+ // if (UE_mac_inst[Mod_id].UE_mode[0] == NOT_SYNCHED) {
+ // /* this check is in the code before refactoring, but I don't know
+ // * why. Leave it in here for the moment */
+ // continue;
+ // }
+ // nfapi_dl_config_request_pdu_t *dl_config_pdu_tmp = &dl_config_pdu_list[i];
+ // const int pdu_index = dl_config_pdu_tmp->dlsch_pdu.dlsch_pdu_rel8.pdu_index;
+ // ue_send_mch_sdu(Mod_id, 0, sfn,
+ // tx_request_pdu_list[pdu_index].segments[0].segment_data,
+ // tx_request_pdu_list[pdu_index].segments[0].segment_length,
+ // 0,0);
+
+ //}
+ else {
LOG_W(MAC, "can not handle special RNTI %x\n", rnti);
}
}
diff --git a/openair2/RRC/LTE/L2_interface.c b/openair2/RRC/LTE/L2_interface.c
index 68017be85bba9f51b06995116a5721df1307e306..d9682b466f2f98148bc920ac221c26d63a93097a 100644
--- a/openair2/RRC/LTE/L2_interface.c
+++ b/openair2/RRC/LTE/L2_interface.c
@@ -28,6 +28,15 @@
* \email: raymond.knopp@eurecom.fr
*/
+/*! \file l2_interface.c
+ * \brief layer 2 interface, added support for FeMBMS RRC sublayer
+ * \author Javier Morgade
+ * \date 2020
+ * \version 1.0
+ * \email: javier.morgade@ieee.org
+ */
+
+
#include "platform_types.h"
#include "rrc_defs.h"
#include "rrc_extern.h"
@@ -65,6 +74,9 @@ mac_rrc_data_req(
uint8_t Sdu_size = 0;
uint8_t sfn = (uint8_t)((frameP>>2)&0xff);
+ uint8_t sfn_fembms = (uint8_t)((frameP>>4)&0xff);
+ sfn_fembms = sfn_fembms<<2;
+
if (LOG_DEBUGFLAG(DEBUG_RRC)) {
LOG_D(RRC,"[eNB %d] mac_rrc_data_req to SRB ID=%ld\n",Mod_idP,Srb_id);
}
@@ -72,12 +84,14 @@ mac_rrc_data_req(
eNB_RRC_INST *rrc;
rrc_eNB_carrier_data_t *carrier;
LTE_BCCH_BCH_Message_t *mib;
+ LTE_BCCH_BCH_Message_MBMS_t *mib_fembms;
rrc = RC.rrc[Mod_idP];
carrier = &rrc->carrier[0];
mib = &carrier->mib;
+ mib_fembms = &carrier->mib_fembms;
if((Srb_id & RAB_OFFSET) == BCCH_SI_MBMS){
- if (frameP%4 == 0) {
+ if (frameP%8 == 0) {
memcpy(&buffer_pP[0],
RC.rrc[Mod_idP]->carrier[CC_id].SIB1_MBMS,
RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB1_MBMS);
@@ -159,6 +173,22 @@ mac_rrc_data_req(
return(3);
}
+ if( (Srb_id & RAB_OFFSET ) == MIBCH_MBMS) {
+ mib_fembms->message.systemFrameNumber_r14.buf = &sfn_fembms;
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_BCH_Message_MBMS,
+ NULL,
+ (void *)mib_fembms,
+ carrier->MIB_FeMBMS,
+ 24);
+ LOG_I(RRC,"Encoded MIB MBMS for frame %d (%p), bits %lu %x,%x,%x %x bits_unused %d\n",sfn_fembms>>2,carrier->MIB_FeMBMS,enc_rval.encoded,carrier->MIB_FeMBMS[0],carrier->MIB_FeMBMS[1],carrier->MIB_FeMBMS[2],mib_fembms->message.systemFrameNumber_r14.buf[0],mib_fembms->message.systemFrameNumber_r14.bits_unused);
+ buffer_pP[0]=carrier->MIB_FeMBMS[0];
+ buffer_pP[1]=carrier->MIB_FeMBMS[1];
+ buffer_pP[2]=carrier->MIB_FeMBMS[2];
+ AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ return(3);
+ }
+
if( (Srb_id & RAB_OFFSET ) == CCCH) {
struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti);
@@ -203,8 +233,10 @@ mac_rrc_data_req(
RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESSAGE[mbsfn_sync_area],
RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]);
+ LOG_D(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP);
+
if (LOG_DEBUGFLAG(DEBUG_RRC)) {
- LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP);
+ LOG_D(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE \n",Mod_idP,frameP);
for (int i=0; i<RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]; i++) {
LOG_T(RRC,"%x.",buffer_pP[i]);
@@ -216,6 +248,29 @@ mac_rrc_data_req(
return (RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[mbsfn_sync_area]);
}
+ if((Srb_id & RAB_OFFSET) == MCCH_COUNTING) {
+ if(RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESS_COUNTING[mbsfn_sync_area].Active==0) {
+ return 0; // this parameter is set in function init_mcch in rrc_eNB.c
+ }
+
+ memcpy(&buffer_pP[0],
+ RC.rrc[Mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[mbsfn_sync_area],
+ RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]);
+
+ if (LOG_DEBUGFLAG(DEBUG_RRC)) {
+ LOG_W(RRC,"[eNB %d] Frame %d : MCCH request => MCCH_MESSAGE_COUNTING \n",Mod_idP,frameP);
+
+ for (int i=0; i<RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]; i++) {
+ LOG_T(RRC,"%x.",buffer_pP[i]);
+ }
+
+ LOG_T(RRC,"\n");
+ } /* LOG_DEBUGFLAG(DEBUG_RRC) */
+
+ return (RC.rrc[Mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[mbsfn_sync_area]);
+ }
+
+
if ((Srb_id & RAB_OFFSET) == BCCH_SIB1_BR) {
memcpy(&buffer_pP[0],
RC.rrc[Mod_idP]->carrier[CC_id].SIB1_BR,
diff --git a/openair2/RRC/LTE/L2_interface_ue.c b/openair2/RRC/LTE/L2_interface_ue.c
index 61ab63955dd529f6d492b3a837383732701521a7..8c55dbaeb50030fa4e1acdf1ec5038584317a381 100644
--- a/openair2/RRC/LTE/L2_interface_ue.c
+++ b/openair2/RRC/LTE/L2_interface_ue.c
@@ -19,7 +19,7 @@
* contact@openairinterface.org
*/
-/*! \file l2_interface.c
+/*! \file l2_interface_ue.c
* \brief layer 2 interface, used to support different RRC sublayer
* \author Raymond Knopp and Navid Nikaein
* \date 2010-2014
@@ -28,6 +28,16 @@
* \email: raymond.knopp@eurecom.fr
*/
+
+/*! \file l2_interface_ue.c
+ * \brief layer 2 interface, added support for FeMBMS RRC sublayer
+ * \author J. Morgade
+ * \date 2020
+ * \version 1.0
+ * \email: javier.morgade@ieee.org
+ */
+
+
#include "platform_types.h"
#include "rrc_defs.h"
#include "rrc_extern.h"
@@ -219,6 +229,7 @@ mac_rrc_data_ind_ue(
if ((srb_idP & RAB_OFFSET) == MCCH) {
LOG_T(RRC,"[UE %d] Frame %d: Received SDU on MBSFN sync area %d for MCCH on SRB %ld from eNB %d\n",
module_idP,frameP, mbsfn_sync_areaP, srb_idP & RAB_OFFSET,eNB_indexP);
+
{
MessageDef *message_p;
int msg_sdu_size = sizeof(RRC_MAC_MCCH_DATA_IND (message_p).sdu);
diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.c b/openair2/RRC/LTE/MESSAGES/asn1_msg.c
index 583e10da94eedf7dfadc24722335425a68643f9e..09e6245fec1e0c6d75df85989f9a30b02241cbcd 100644
--- a/openair2/RRC/LTE/MESSAGES/asn1_msg.c
+++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.c
@@ -28,6 +28,14 @@
* \email: raymond.knopp@eurecom.fr and navid.nikaein@eurecom.fr
*/
+/*! \file asn1_msg.c
+ * \brief added primitives to build the asn1 messages for FeMBMS
+ * \author Javier Morgade
+ * \date 2019-2020
+ * \version 1.0
+ * \email: javier.morgade@ieee.org
+ */
+
#include <stdio.h>
#include <sys/types.h>
#include <stdlib.h> /* for atoi(3) */
@@ -185,7 +193,8 @@ uint8_t get_adjacent_cell_mod_id(uint16_t phyCellId) {
uint8_t do_MIB_FeMBMS(rrc_eNB_carrier_data_t *carrier, uint32_t N_RB_DL, uint32_t additionalNonMBSFN, uint32_t frame) {
asn_enc_rval_t enc_rval;
LTE_BCCH_BCH_Message_MBMS_t *mib_fembms=&carrier->mib_fembms;
- uint8_t sfn = (uint8_t)((frame>>2)&0xff);
+ frame=198;
+ uint8_t sfn = (uint8_t)((frame>>4)&0xff);
uint16_t *spare = calloc(1,sizeof(uint16_t));
if( spare == NULL ) abort();
@@ -223,15 +232,16 @@ uint8_t do_MIB_FeMBMS(rrc_eNB_carrier_data_t *carrier, uint32_t N_RB_DL, uint32_
(uint32_t)mib_fembms->message.dl_Bandwidth_MBMS_r14,
(uint32_t)additionalNonMBSFN,
(uint32_t)sfn);
+ sfn = sfn<<2;
mib_fembms->message.systemFrameNumber_r14.buf = &sfn;
mib_fembms->message.systemFrameNumber_r14.size = 1;
- mib_fembms->message.systemFrameNumber_r14.bits_unused=0;
+ mib_fembms->message.systemFrameNumber_r14.bits_unused=2;
mib_fembms->message.spare.buf = (uint8_t *)spare;
mib_fembms->message.spare.size = 2;
- mib_fembms->message.spare.bits_unused = 6; // This makes a spare of 10 bits
+ mib_fembms->message.spare.bits_unused = 3; // This makes a spare of 10 bits
//TODO additionalNonBMSFNSubframes-r14 INTEGER (0..3) ?
//if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
- //xer_fprint(stdout, &asn_DEF_LTE_BCCH_BCH_Message_MBMS, (void *)mib_fembms);
+ xer_fprint(stdout, &asn_DEF_LTE_BCCH_BCH_Message_MBMS, (void *)mib_fembms);
//}
enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_BCH_Message_MBMS,
NULL,
@@ -387,7 +397,11 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier,
// SystemInformation_t systemInformation;
int num_plmn = configuration->num_plmn;
- LTE_PLMN_IdentityInfo_t *PLMN_identity_info;
+ //LTE_PLMN_IdentityInfo_t *PLMN_identity_info;
+ LTE_PLMN_IdentityInfo_t * PLMN_identity_info = &carrier->PLMN_identity_info_MBMS[0];
+ //LTE_MCC_MNC_Digit_t dummy_mcc[num_plmn][3], dummy_mnc[num_plmn][3];
+ //LTE_MCC_MNC_Digit_t *dummy_mcc = &carrier->dummy_mcc_MBMS[0][0];
+ //LTE_MCC_MNC_Digit_t *dummy_mnc = &carrier->dummy_mnc_MBMS[0][0];
LTE_MCC_MNC_Digit_t *dummy_mcc_0;
LTE_MCC_MNC_Digit_t *dummy_mcc_1;
LTE_MCC_MNC_Digit_t *dummy_mcc_2;
@@ -395,7 +409,9 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier,
LTE_MCC_MNC_Digit_t *dummy_mnc_1;
LTE_MCC_MNC_Digit_t *dummy_mnc_2;
asn_enc_rval_t enc_rval;
- LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo;
+ //LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo;
+ //LTE_SchedulingInfo_MBMS_r14_t schedulingInfo;
+ LTE_SchedulingInfo_MBMS_r14_t *schedulingInfo = &carrier->schedulingInfo_MBMS;
LTE_SIB_Type_t *sib_type;
uint8_t *buffer = carrier->SIB1_MBMS;
LTE_BCCH_DL_SCH_Message_MBMS_t *bcch_message = &carrier->siblock1_MBMS;
@@ -408,6 +424,8 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier,
// memcpy(&bcch_message.message.choice.c1.choice.systemInformationBlockType1,sib1,sizeof(SystemInformationBlockType1_t));
*sib1_MBMS = &bcch_message->message.choice.c1.choice.systemInformationBlockType1_MBMS_r14;
PLMN_identity_info = CALLOC(1, sizeof(LTE_PLMN_IdentityInfo_t) * num_plmn);
+ //memset(&schedulingInfo,0,sizeof(LTE_SchedulingInfo_MBMS_r14_t));
+ memset(schedulingInfo,0,sizeof(LTE_SchedulingInfo_MBMS_r14_t));
if (PLMN_identity_info == NULL)
exit(1);
@@ -528,7 +546,7 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier,
MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1;
MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=0x20<<2; // FDD: SF1
MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2;
- MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__signallingMCS_r9_n7;
+ MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__signallingMCS_r9_n2;
(MBSFN_Area1)->ext1 = CALLOC (1, sizeof(*(MBSFN_Area1)->ext1));
memset((MBSFN_Area1)->ext1,0,sizeof(*(MBSFN_Area1)->ext1));
MBSFN_Area1->ext1->subcarrierSpacingMBMS_r14 = CALLOC(1,sizeof(*( MBSFN_Area1->ext1)->subcarrierSpacingMBMS_r14));
@@ -541,18 +559,18 @@ uint8_t do_SIB1_MBMS(rrc_eNB_carrier_data_t *carrier,
if(1) {
(*sib1_MBMS)->nonMBSFN_SubframeConfig_r14 = CALLOC(1,sizeof(struct LTE_NonMBSFN_SubframeConfig_r14));
memset((*sib1_MBMS)->nonMBSFN_SubframeConfig_r14,0,sizeof(struct LTE_NonMBSFN_SubframeConfig_r14));
- (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationPeriod_r14 = LTE_NonMBSFN_SubframeConfig_r14__radioFrameAllocationPeriod_r14_rf8;
+ (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationPeriod_r14 = LTE_NonMBSFN_SubframeConfig_r14__radioFrameAllocationPeriod_r14_rf4;
(*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->radioFrameAllocationOffset_r14 = 0;
(*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf = MALLOC(2);
//100000001 byte(0)=10000000 byte(1)=xxxxxxx1
- (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[0] = 0x80<<0;
- (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[1] = 0x1<<7;
+ (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[0] = 0x8<<0;
+ (*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf[1] = 0;
(*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.size = 2;
(*sib1_MBMS)->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.bits_unused = 7;
}
//if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
- //xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, (void *)bcch_message);
+ xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS, (void *)bcch_message);
//}
enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS,
NULL,
@@ -2310,7 +2328,7 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destin
return((enc_rval.encoded+7)/8);
}
-uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) {
+uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, uint8_t sel_plmn_id, const int dedicatedInfoNASLength, const char *dedicatedInfoNAS) {
asn_enc_rval_t enc_rval;
LTE_UL_DCCH_Message_t ul_dcch_msg;
LTE_RRCConnectionSetupComplete_t *rrcConnectionSetupComplete;
@@ -2323,7 +2341,7 @@ uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uin
rrcConnectionSetupComplete->criticalExtensions.choice.c1.present = LTE_RRCConnectionSetupComplete__criticalExtensions__c1_PR_rrcConnectionSetupComplete_r8;
rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension=CALLOC(1,
sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.nonCriticalExtension));
- rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= 1;
+ rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.selectedPLMN_Identity= sel_plmn_id;
rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME =
NULL;//calloc(1,sizeof(*rrcConnectionSetupComplete->criticalExtensions.choice.c1.choice.rrcConnectionSetupComplete_r8.registeredMME));
/*
@@ -3198,6 +3216,42 @@ uint8_t do_UECapabilityEnquiry( const protocol_ctxt_t *const ctxt_pP,
ASN_SEQUENCE_ADD(&dl_dcch_msg.message.choice.c1.choice.ueCapabilityEnquiry.criticalExtensions.choice.c1.choice.ueCapabilityEnquiry_r8.ue_CapabilityRequest.list,
&rat);
+ /* request NR configuration */
+ LTE_UECapabilityEnquiry_r8_IEs_t *r8 = &dl_dcch_msg.message.choice.c1.choice.ueCapabilityEnquiry.criticalExtensions.choice.c1.choice.ueCapabilityEnquiry_r8;
+ LTE_UECapabilityEnquiry_v8a0_IEs_t r8_a0;
+ LTE_UECapabilityEnquiry_v1180_IEs_t r11_80;
+ LTE_UECapabilityEnquiry_v1310_IEs_t r13_10;
+ LTE_UECapabilityEnquiry_v1430_IEs_t r14_30;
+ LTE_UECapabilityEnquiry_v1510_IEs_t r15_10;
+
+ memset(&r8_a0, 0, sizeof(r8_a0));
+ memset(&r11_80, 0, sizeof(r11_80));
+ memset(&r13_10, 0, sizeof(r13_10));
+ memset(&r14_30, 0, sizeof(r14_30));
+ memset(&r15_10, 0, sizeof(r15_10));
+
+ r8->nonCriticalExtension = &r8_a0;
+ r8_a0.nonCriticalExtension = &r11_80;
+ r11_80.nonCriticalExtension = &r13_10;
+ r13_10.nonCriticalExtension = &r14_30;
+ r14_30.nonCriticalExtension = &r15_10;
+
+ /* TODO: no hardcoded values here */
+
+ OCTET_STRING_t req_freq;
+ unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78
+ //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x08, 0x18 }; // bands 7 & nr260
+
+ //unsigned char req_freq_buf[13] = { 0x00, 0xc0, 0x18, 0x01, 0x01, 0x30, 0x4b, 0x04, 0x0e, 0x08, 0x24, 0x04, 0xd0 };
+// unsigned char req_freq_buf[21] = {
+//0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a
+// };
+
+ req_freq.buf = req_freq_buf;
+ req_freq.size = 5;
+// req_freq.size = 21;
+
+ r15_10.requestedFreqBandsNR_MRDC_r15 = &req_freq;
if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
xer_fprint(stdout, &asn_DEF_LTE_DL_DCCH_Message, (void *)&dl_dcch_msg);
}
@@ -3276,17 +3330,17 @@ uint8_t do_NR_UECapabilityEnquiry( const protocol_ctxt_t *const ctxt_pP,
/* TODO: no hardcoded values here */
OCTET_STRING_t req_freq;
- //unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78
+ unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x02, 0x68 }; // bands 7 & nr78
//unsigned char req_freq_buf[5] = { 0x00, 0x20, 0x1a, 0x08, 0x18 }; // bands 7 & nr260
//unsigned char req_freq_buf[13] = { 0x00, 0xc0, 0x18, 0x01, 0x01, 0x30, 0x4b, 0x04, 0x0e, 0x08, 0x24, 0x04, 0xd0 };
- unsigned char req_freq_buf[21] = {
-0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a
- };
+// unsigned char req_freq_buf[21] = {
+//0x01, 0x60, 0x18, 0x05, 0x80, 0xc0, 0x04, 0x04, 0xc1, 0x2c, 0x10, 0x08, 0x20, 0x30, 0x40, 0xe0, 0x82, 0x40, 0x28, 0x80, 0x9a
+// };
req_freq.buf = req_freq_buf;
req_freq.size = 5;
- req_freq.size = 21;
+// req_freq.size = 21;
r15_10.requestedFreqBandsNR_MRDC_r15 = &req_freq;
diff --git a/openair2/RRC/LTE/MESSAGES/asn1_msg.h b/openair2/RRC/LTE/MESSAGES/asn1_msg.h
index dda23406100c0d1652ca0d096bff624c441fbf1c..640d18a61f92942a6fcb66c0d52981c2d29e0c75 100644
--- a/openair2/RRC/LTE/MESSAGES/asn1_msg.h
+++ b/openair2/RRC/LTE/MESSAGES/asn1_msg.h
@@ -142,7 +142,11 @@ uint8_t do_SidelinkUEInformation(uint8_t Mod_id, uint8_t *buffer, LTE_SL_Destina
/** \brief Generate an RRCConnectionSetupComplete UL-DCCH-Message (UE)
@param buffer Pointer to PER-encoded ASN.1 description of UL-DCCH-Message PDU
@returns Size of encoded bit stream in bytes*/
-uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id, uint8_t *buffer, const uint8_t Transaction_id, const int dedicatedInfoNASLength,
+uint8_t do_RRCConnectionSetupComplete(uint8_t Mod_id,
+ uint8_t *buffer,
+ const uint8_t Transaction_id,
+ uint8_t sel_plmn_id,
+ const int dedicatedInfoNASLength,
const char *dedicatedInfoNAS);
/** \brief Generate an RRCConnectionReconfigurationComplete UL-DCCH-Message (UE)
diff --git a/openair2/RRC/LTE/rrc_UE.c b/openair2/RRC/LTE/rrc_UE.c
index 4116f5367eae3e8eed143df266502f6ce9ad69c3..c5aa2bc0f8415f748cf6eeb4a5abb3fa4117a17c 100644
--- a/openair2/RRC/LTE/rrc_UE.c
+++ b/openair2/RRC/LTE/rrc_UE.c
@@ -128,8 +128,13 @@ static int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t
* \param ctxt_pP Running context
* \param eNB_index Index of corresponding eNB/CH
* \param Transaction_id Transaction identifier
+ * \param sel_plmn_id selected PLMN Identity
*/
-static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id );
+static void rrc_ue_generate_RRCConnectionSetupComplete(
+ const protocol_ctxt_t *const ctxt_pP,
+ const uint8_t eNB_index,
+ const uint8_t Transaction_id,
+ uint8_t sel_plmn_id);
/** \brief Generates/Encodes RRCConnectionReconfigurationComplete message at UE
* \param ctxt_pP Running context
@@ -150,14 +155,19 @@ static uint8_t check_trigger_meas_event(
LTE_Q_OffsetRange_t ofs, LTE_Q_OffsetRange_t ocs, long a3_offset, LTE_TimeToTrigger_t ttt);
static void decode_MBSFNAreaConfiguration(module_id_t module_idP, uint8_t eNB_index, frame_t frameP,uint8_t mbsfn_sync_area);
+static void decode_MBMSCountingRequest(module_id_t module_idP, uint8_t eNB_index, frame_t frameP,uint8_t mbsfn_sync_area);
+
uint8_t rrc_ue_generate_SidelinkUEInformation( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,LTE_SL_DestinationInfoList_r12_t *destinationInfoList, long *discTxResourceReq,
SL_TRIGGER_t mode);
-
-
-
-
-
+void
+rrc_ue_process_MBMSCountingRequest(
+ const protocol_ctxt_t *const ctxt_pP,
+ LTE_MBMSCountingRequest_r10_t *MBMSCountingRequest,
+ uint8_t eNB_index
+ );
+
+protocol_ctxt_t ctxt_pP_local;
/*------------------------------------------------------------------------------*/
@@ -367,6 +377,7 @@ char openair_rrc_ue_init( const module_id_t ue_mod_idP, const unsigned char eNB_
rrc_set_state (ue_mod_idP, RRC_STATE_INACTIVE);
rrc_set_sub_state (ue_mod_idP, RRC_SUB_STATE_INACTIVE);
LOG_I(RRC,"[UE %d] INIT State = RRC_IDLE (eNB %d)\n",ctxt.module_id,eNB_index);
+ UE_rrc_inst[ctxt.module_id].selected_plmn_identity = 1;
UE_rrc_inst[ctxt.module_id].Info[eNB_index].State=RRC_IDLE;
UE_rrc_inst[ctxt.module_id].Info[eNB_index].T300_active = 0;
UE_rrc_inst[ctxt.module_id].Info[eNB_index].T304_active = 0;
@@ -490,7 +501,11 @@ rrc_t310_expiration(
}
//-----------------------------------------------------------------------------
-static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index, const uint8_t Transaction_id ) {
+static void rrc_ue_generate_RRCConnectionSetupComplete(
+ const protocol_ctxt_t *const ctxt_pP,
+ const uint8_t eNB_index,
+ const uint8_t Transaction_id,
+ uint8_t sel_plmn_id) {
uint8_t buffer[100];
uint8_t size;
const char *nas_msg;
@@ -504,12 +519,13 @@ static void rrc_ue_generate_RRCConnectionSetupComplete( const protocol_ctxt_t *c
nas_msg_length = sizeof(nas_attach_req_imsi);
}
- size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, nas_msg_length, nas_msg);
+ size = do_RRCConnectionSetupComplete(ctxt_pP->module_id, buffer, Transaction_id, sel_plmn_id, nas_msg_length, nas_msg);
LOG_I(RRC,"[UE %d][RAPROC] Frame %d : Logical Channel UL-DCCH (SRB1), Generating RRCConnectionSetupComplete (bytes%d, eNB %d)\n",
ctxt_pP->module_id,ctxt_pP->frame, size, eNB_index);
LOG_D(RLC,
"[FRAME %05d][RRC_UE][MOD %02d][][--- PDCP_DATA_REQ/%d Bytes (RRCConnectionSetupComplete to eNB %d MUI %d) --->][PDCP][MOD %02d][RB %02d]\n",
ctxt_pP->frame, ctxt_pP->module_id+NB_eNB_INST, size, eNB_index, rrc_mui, ctxt_pP->module_id+NB_eNB_INST, DCCH);
+ ctxt_pP_local.rnti = ctxt_pP->rnti;
rrc_data_req_ue (
ctxt_pP,
DCCH,
@@ -624,7 +640,8 @@ int rrc_ue_decode_ccch( const protocol_ctxt_t *const ctxt_pP, const SRB_INFO *co
rrc_ue_generate_RRCConnectionSetupComplete(
ctxt_pP,
eNB_index,
- dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier);
+ dl_ccch_msg->message.choice.c1.choice.rrcConnectionSetup.rrc_TransactionIdentifier,
+ UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity);
rval = 0;
break;
@@ -1561,6 +1578,65 @@ rrc_ue_process_securityModeCommand(
securityModeCommand->criticalExtensions.present);
}
+void
+rrc_ue_process_MBMSCountingRequest(
+ const protocol_ctxt_t *const ctxt_pP,
+ LTE_MBMSCountingRequest_r10_t *MBMSCountingRequest,
+ uint8_t eNB_index
+)
+{
+ asn_enc_rval_t enc_rval;
+ LTE_UL_DCCH_Message_t ul_dcch_msg;
+ struct LTE_CountingResponseInfo_r10 CountingResponse;
+ uint8_t buffer[200];
+ //int i;
+ LOG_I(RRC,"[UE %d] Frame %d: Receiving from (MCCH), Processing MBMSCoutingRequest (eNB %d)\n",
+ ctxt_pP->module_id,
+ ctxt_pP->frame,
+ eNB_index);
+ memset((void *)&ul_dcch_msg,0,sizeof(LTE_UL_DCCH_Message_t));
+ memset((void *)&CountingResponse,0,sizeof(struct LTE_CountingResponseInfo_r10));
+
+
+ ul_dcch_msg.message.present = LTE_UL_DCCH_MessageType_PR_c1;
+ ul_dcch_msg.message.choice.c1.present = LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10;
+ LTE_MBMSCountingResponse_r10_t *MBMSCountingResponse = &ul_dcch_msg.message.choice.c1.choice.mbmsCountingResponse_r10;
+
+ MBMSCountingResponse->criticalExtensions.present = LTE_MBMSCountingResponse_r10__criticalExtensions_PR_c1;
+ MBMSCountingResponse->criticalExtensions.choice.c1.present = LTE_MBMSCountingResponse_r10__criticalExtensions__c1_PR_countingResponse_r10;
+ LTE_MBMSCountingResponse_r10_IEs_t *MBMSCountingResponse_r10_IEs = &MBMSCountingResponse->criticalExtensions.choice.c1.choice.countingResponse_r10;
+
+ MBMSCountingResponse_r10_IEs->mbsfn_AreaIndex_r10 = calloc(1,sizeof(long));
+ // MBMSCountingResponse_r10_IEs->countingResponseList_r10 = calloc(1,sizeof(struct LTE_CountingResponseList_r10));
+//
+// ASN_SEQUENCE_ADD(
+// &MBMSCountingResponse->criticalExtensions.choice.c1.choice.countingResponse_r10.countingResponseList_r10.list,
+// &CountingResponse);
+//
+
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UL_DCCH_Message, NULL, (void *) &ul_dcch_msg, buffer, 100);
+ AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+
+ if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
+ xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)&ul_dcch_msg);
+ }
+ xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)&ul_dcch_msg);
+
+
+ LOG_I(RRC,"MBMSCountingResponse Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8);
+ rrc_data_req_ue (
+ &ctxt_pP_local,
+ DCCH,
+ rrc_mui++,
+ SDU_CONFIRM_NO,
+ (enc_rval.encoded + 7) / 8,
+ buffer,
+ PDCP_TRANSMISSION_MODE_CONTROL);
+
+}
+
+
//-----------------------------------------------------------------------------
void
rrc_ue_process_ueCapabilityEnquiry(
@@ -2178,8 +2254,8 @@ rrc_ue_decode_dcch(
#endif
}
-const char siWindowLength[8][5] = {"1ms","2ms","5ms","10ms","15ms","20ms","40ms","ERR"};
-const char siWindowLength_int[7] = {1,2,5,10,15,20,40};
+const char siWindowLength[9][5] = {"1ms","2ms","5ms","10ms","15ms","20ms","40ms","80ms","ERR"};
+const char siWindowLength_int[8] = {1,2,5,10,15,20,40,80};
const char SIBType[12][6] = {"SIB3","SIB4","SIB5","SIB6","SIB7","SIB8","SIB9","SIB10","SIB11","SIB12","SIB13","Spare"};
const char SIBPeriod[8][6]= {"rf8","rf16","rf32","rf64","rf128","rf256","rf512","ERR"};
@@ -2689,7 +2765,7 @@ int decode_SIB1_MBMS( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_in
//LOG_I( RRC, "TDD subframeAssignment : %ld\n", sib1_MBMS->tdd_Config->subframeAssignment );
//LOG_I( RRC, "TDD specialSubframePatterns : %ld\n", sib1_MBMS->tdd_Config->specialSubframePatterns );
//}
- LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1_MBMS->si_WindowLength_r14,7)] );
+ LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1_MBMS->si_WindowLength_r14,8)] );
LOG_I( RRC, "systemInfoValueTag : %ld\n", sib1_MBMS->systemInfoValueTag_r14 );
UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIperiod_MBMS = siPeriod_int[sib1_MBMS->schedulingInfoList_MBMS_r14.list.array[0]->si_Periodicity_r14];
UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIwindowsize_MBMS = siWindowLength_int[sib1_MBMS->si_WindowLength_r14];
@@ -2794,44 +2870,43 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,
LTE_SystemInformationBlockType1_t *sib1 = UE_rrc_inst[ctxt_pP->module_id].sib1[eNB_index];
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_UE_DECODE_SIB1, VCD_FUNCTION_IN );
LOG_I( RRC, "[UE %d] : Dumping SIB 1\n", ctxt_pP->module_id );
- LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->plmn_Identity;
- int mccdigits = PLMN_identity->mcc->list.count;
- int mncdigits = PLMN_identity->mnc.list.count;
- int mcc;
+ const int n = sib1->cellAccessRelatedInfo.plmn_IdentityList.list.count;
+ for (int i = 0; i < n; ++i) {
+ LTE_PLMN_Identity_t *PLMN_identity = &sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[i]->plmn_Identity;
+ int mccdigits = PLMN_identity->mcc->list.count;
+ int mncdigits = PLMN_identity->mnc.list.count;
+
+ int mcc;
+ if (mccdigits == 2) {
+ mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1];
+ } else {
+ mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2];
+ }
- if (mccdigits == 2) {
- mcc = *PLMN_identity->mcc->list.array[0]*10 + *PLMN_identity->mcc->list.array[1];
- } else {
- mcc = *PLMN_identity->mcc->list.array[0]*100 + *PLMN_identity->mcc->list.array[1]*10 + *PLMN_identity->mcc->list.array[2];
- }
+ int mnc;
+ if (mncdigits == 2) {
+ mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1];
+ } else {
+ mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2];
+ }
- int mnc;
+ LOG_I( RRC, "PLMN %d MCC %0*d, MNC %0*d\n", i + 1, mccdigits, mcc, mncdigits, mnc);
+ // search internal table for provider name
+ int plmn_ind = 0;
- if (mncdigits == 2) {
- mnc = *PLMN_identity->mnc.list.array[0]*10 + *PLMN_identity->mnc.list.array[1];
- } else {
- mnc = *PLMN_identity->mnc.list.array[0]*100 + *PLMN_identity->mnc.list.array[1]*10 + *PLMN_identity->mnc.list.array[2];
- }
+ while (plmn_data[plmn_ind].mcc > 0) {
+ if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) {
+ LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short );
+ break;
+ }
- LOG_I( RRC, "PLMN MCC %0*d, MNC %0*d, TAC 0x%04x\n", mccdigits, mcc, mncdigits, mnc,
+ plmn_ind++;
+ }
+ }
+ LOG_I( RRC, "TAC 0x%04x\n",
((sib1->cellAccessRelatedInfo.trackingAreaCode.size == 2)?((sib1->cellAccessRelatedInfo.trackingAreaCode.buf[0]<<8) + sib1->cellAccessRelatedInfo.trackingAreaCode.buf[1]):0));
LOG_I( RRC, "cellReservedForOperatorUse : raw:%ld decoded:%s\n", sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse,
SIBreserved(sib1->cellAccessRelatedInfo.plmn_IdentityList.list.array[0]->cellReservedForOperatorUse) );
- // search internal table for provider name
- int plmn_ind = 0;
-
- while (plmn_data[plmn_ind].mcc > 0) {
- if ((plmn_data[plmn_ind].mcc == mcc) && (plmn_data[plmn_ind].mnc == mnc)) {
- LOG_I( RRC, "Found %s (name from internal table)\n", plmn_data[plmn_ind].oper_short );
- break;
- }
-
- plmn_ind++;
- }
-
- if (plmn_data[plmn_ind].mcc < 0) {
- LOG_I( RRC, "Found Unknown operator (no entry in internal table)\n" );
- }
LOG_I( RRC, "cellAccessRelatedInfo.cellIdentity : raw:%"PRIu32" decoded:%02x.%02x.%02x.%02x\n",
BIT_STRING_to_uint32( &sib1->cellAccessRelatedInfo.cellIdentity ),
@@ -2888,7 +2963,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,
LOG_I( RRC, "TDD specialSubframePatterns : %ld\n", sib1->tdd_Config->specialSubframePatterns );
}
- LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1->si_WindowLength,7)] );
+ LOG_I( RRC, "siWindowLength : %s\n", siWindowLength[min(sib1->si_WindowLength,8)] );
LOG_I( RRC, "systemInfoValueTag : %ld\n", sib1->systemInfoValueTag );
UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIperiod = siPeriod_int[sib1->schedulingInfoList.list.array[0]->si_Periodicity];
UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].SIwindowsize = siWindowLength_int[sib1->si_WindowLength];
@@ -2970,6 +3045,7 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,
NAS_CELL_SELECTION_CNF (msg_p).rsrp = rsrp;
itti_send_msg_to_task(TASK_NAS_UE, ctxt_pP->instance, msg_p);
cell_valid = 1;
+ UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity = plmn + 1;
break;
}
}
@@ -2980,7 +3056,11 @@ int decode_SIB1( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB_index,
MessageDef *msg_p;
msg_p = itti_alloc_new_message(TASK_RRC_UE, PHY_FIND_NEXT_CELL_REQ);
itti_send_msg_to_task(TASK_PHY_UE, ctxt_pP->instance, msg_p);
- LOG_E(RRC, "Synched with a cell, but PLMN doesn't match our SIM, the message PHY_FIND_NEXT_CELL_REQ is sent but lost in current UE implementation! \n");
+ LOG_E(RRC,
+ "Synched with a cell, but PLMN doesn't match our SIM "
+ "(selected_plmn_identity %d), the message PHY_FIND_NEXT_CELL_REQ "
+ "is sent but lost in current UE implementation!\n",
+ UE_rrc_inst[ctxt_pP->module_id].selected_plmn_identity);
}
}
@@ -4210,7 +4290,7 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB
ctxt_pP->frame,
mbsfn_sync_area);
return 0; // avoid decoding to prevent memory bloating
- } else if(UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State >= RRC_CONNECTED /*|| UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State == RRC_RECONFIGURED*/){
+ } else if(1/*UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State >= RRC_CONNECTED*/ /*|| UE_rrc_inst[ctxt_pP->module_id].Info[eNB_index].State == RRC_RECONFIGURED*/){
dec_rval = uper_decode_complete(NULL,
&asn_DEF_LTE_MCCH_Message,
(void **)&mcch,
@@ -4229,6 +4309,7 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB
if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
xer_fprint(stdout, &asn_DEF_LTE_MCCH_Message, (void *)mcch);
}
+ xer_fprint(stdout, &asn_DEF_LTE_MCCH_Message, (void *)mcch);
if (mcch->message.present == LTE_MCCH_MessageType_PR_c1) {
LOG_D(RRC,"[UE %d] Found mcch message \n",
@@ -4250,7 +4331,29 @@ int decode_MCCH_Message( const protocol_ctxt_t *const ctxt_pP, const uint8_t eNB
ctxt_pP->frame,
mbsfn_sync_area);
}
+ }else if(mcch->message.present == LTE_MCCH_MessageType_PR_later){
+ LOG_D(RRC,"[UE %d] Found mcch message \n",
+ ctxt_pP->module_id);
+ if(mcch->message.choice.later.present == LTE_MCCH_MessageType__later_PR_c2){
+ if(mcch->message.choice.later.choice.c2.present == LTE_MCCH_MessageType__later__c2_PR_mbmsCountingRequest_r10){
+ LOG_I(RRC,"[UE %d] Frame %d : Found MBMSCountingRequest from eNB %d %p\n",
+ ctxt_pP->module_id,
+ ctxt_pP->frame,
+ eNB_index,&mcch->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10);
+
+ rrc_ue_process_MBMSCountingRequest(ctxt_pP,&mcch->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10,eNB_index);
+
+ decode_MBMSCountingRequest(
+ ctxt_pP->module_id,
+ eNB_index,
+ ctxt_pP->frame,
+ mbsfn_sync_area);
+
+
+ }
+ }
}
+
}
return 0;
@@ -4308,7 +4411,7 @@ void decode_MBSFNAreaConfiguration( module_id_t ue_mod_idP, uint8_t eNB_index, f
(struct LTE_NonMBSFN_SubframeConfig_r14 *)NULL,
(LTE_MBSFN_AreaInfoList_r9_t *)NULL
);
- if(UE_rrc_inst[ue_mod_idP].Info[eNB_index].State >= RRC_CONNECTED /*|| UE_rrc_inst[ue_mod_idP].Info[eNB_index].State == RRC_RECONFIGURED*/)
+ if(1/*UE_rrc_inst[ue_mod_idP].Info[eNB_index].State >= RRC_CONNECTED*/ /*|| UE_rrc_inst[ue_mod_idP].Info[eNB_index].State == RRC_RECONFIGURED*/)
UE_rrc_inst[ue_mod_idP].Info[eNB_index].MCCHStatus[mbsfn_sync_area] = 1;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, ue_mod_idP, ENB_FLAG_NO, UE_rrc_inst[ue_mod_idP].Info[eNB_index].rnti, frameP, 0,eNB_index);
// Config Radio Bearer for MBMS user data (similar way to configure for eNB side in init_MBMS function)
@@ -4332,6 +4435,13 @@ void decode_MBSFNAreaConfiguration( module_id_t ue_mod_idP, uint8_t eNB_index, f
// */
}
+void decode_MBMSCountingRequest( module_id_t ue_mod_idP, uint8_t eNB_index, frame_t frameP, uint8_t mbsfn_sync_area ) {
+ //uint8_t i;
+ //protocol_ctxt_t ctxt;
+
+
+
+}
//-----------------------------------------------------------------------------
void *rrc_ue_task( void *args_p ) {
diff --git a/openair2/RRC/LTE/rrc_defs.h b/openair2/RRC/LTE/rrc_defs.h
index f050733a13f1352c053ec7a3c423665e0ce6f94e..c498e3c6fe369ede99649040b4993ba527dd8c00 100644
--- a/openair2/RRC/LTE/rrc_defs.h
+++ b/openair2/RRC/LTE/rrc_defs.h
@@ -40,6 +40,10 @@
#include "rrc_types.h"
//#include "PHY/phy_defs.h"
#include "LAYER2/RLC/rlc.h"
+#include "RRC/NR/nr_rrc_types.h"
+#include "NR_UE-MRDC-Capability.h"
+#include "NR_UE-NR-Capability.h"
+
#include "COMMON/platform_constants.h"
#include "COMMON/platform_types.h"
@@ -267,6 +271,7 @@ typedef enum UE_STATE_e {
RRC_RECONFIGURED,
RRC_HO_EXECUTION,
RRC_NR_NSA,
+ RRC_NR_NSA_RECONFIGURED
} UE_STATE_t;
typedef enum HO_STATE_e {
@@ -382,6 +387,7 @@ typedef enum e_rab_satus_e {
E_RAB_STATUS_DONE, // from the eNB perspective
E_RAB_STATUS_ESTABLISHED, // get the reconfigurationcomplete form UE
E_RAB_STATUS_REESTABLISHED, // after HO
+ E_RAB_STATUS_TOMODIFY, // ENDC NSA
E_RAB_STATUS_FAILED,
E_RAB_STATUS_TORELEASE // to release DRB between eNB and UE
} e_rab_status_t;
@@ -568,6 +574,10 @@ typedef struct eNB_RRC_UE_s {
LTE_UE_EUTRA_Capability_t *UE_Capability;
int UE_Capability_size;
+ NR_UE_MRDC_Capability_t *UE_Capability_MRDC;
+ int UE_MRDC_Capability_size;
+ NR_UE_NR_Capability_t *UE_Capability_nr;
+ int UE_NR_Capability_size;
ImsiMobileIdentity_t imsi;
/* KeNB as derived from KASME received from EPC */
@@ -613,6 +623,7 @@ typedef struct eNB_RRC_UE_s {
/* Number of e_rab to be modified in the list */
uint8_t nb_of_modify_e_rabs;
uint8_t nb_of_failed_e_rabs;
+ uint8_t nb_of_modify_endc_e_rabs;
e_rab_param_t modify_e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB];
/* list of e_rab to be setup by RRC layers */
e_rab_param_t e_rab[NB_RB_MAX];//[S1AP_MAX_E_RAB];
@@ -627,6 +638,10 @@ typedef struct eNB_RRC_UE_s {
uint32_t enb_gtp_teid[S1AP_MAX_E_RAB];
transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB];
rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB];
+ // LG: For GTPV1 TUNNELS ENDC
+ uint32_t gnb_gtp_endc_teid[S1AP_MAX_E_RAB];
+ transport_layer_addr_t gnb_gtp_endc_addrs[S1AP_MAX_E_RAB];
+ rb_id_t gnb_gtp_endc_ebi[S1AP_MAX_E_RAB];
/* Total number of e_rab already setup in the list */
uint8_t nb_x2u_e_rabs;
// LG: For GTPV1 TUNNELS(X2U)
@@ -701,6 +716,9 @@ typedef struct {
LTE_BCCH_BCH_Message_MBMS_t mib_fembms;
LTE_BCCH_DL_SCH_Message_MBMS_t siblock1_MBMS;
LTE_BCCH_DL_SCH_Message_MBMS_t systemInformation_MBMS;
+ LTE_SchedulingInfo_MBMS_r14_t schedulingInfo_MBMS;
+ LTE_PLMN_IdentityInfo_t PLMN_identity_info_MBMS[6];
+ LTE_MCC_MNC_Digit_t dummy_mcc_MBMS[6][3], dummy_mnc_MBMS[6][3];
LTE_SystemInformationBlockType1_t *sib1;
LTE_SystemInformationBlockType2_t *sib2;
LTE_SystemInformationBlockType3_t *sib3;
@@ -717,6 +735,12 @@ typedef struct {
LTE_MCCH_Message_t mcch;
LTE_MBSFNAreaConfiguration_r9_t *mcch_message;
SRB_INFO MCCH_MESS[8];// MAX_MBSFN_AREA
+ uint8_t **MCCH_MESSAGE_COUNTING; // MAX_MBSFN_AREA
+ uint8_t sizeof_MCCH_MESSAGE_COUNTING[8];// MAX_MBSFN_AREA
+ LTE_MCCH_Message_t mcch_counting;
+ LTE_MBMSCountingRequest_r10_t *mcch_message_counting;
+ SRB_INFO MCCH_MESS_COUNTING[8];// MAX_MBSFN_AREA
+
//TTN - SIB 18,19,21 for D2D
LTE_SystemInformationBlockType18_r12_t *sib18;
LTE_SystemInformationBlockType19_r12_t *sib19;
@@ -794,6 +818,7 @@ typedef struct UE_RRC_INST_s {
Rrc_Sub_State_t RrcSubState;
plmn_t plmnID;
Byte_t rat;
+ uint8_t selected_plmn_identity;
as_nas_info_t initialNasMsg;
OAI_UECapability_t *UECap;
uint8_t *UECapability;
diff --git a/openair2/RRC/LTE/rrc_eNB.c b/openair2/RRC/LTE/rrc_eNB.c
index 456496af637099d8740eb44882809fa2fb95cc21..b6062df2c4a0b60d436784649fcd34ce5808ffe4 100644
--- a/openair2/RRC/LTE/rrc_eNB.c
+++ b/openair2/RRC/LTE/rrc_eNB.c
@@ -96,6 +96,10 @@
#include "SIMULATION/TOOLS/sim.h" // for taus
+#define ASN_MAX_ENCODE_SIZE 4096
+#define NUMBEROF_DRBS_TOBE_ADDED 1
+static int encode_CG_ConfigInfo(char *buffer,int buffer_size,rrc_eNB_ue_context_t *const ue_context_pP,int *enc_size);
+static int is_en_dc_supported(LTE_UE_EUTRA_Capability_t *c);
extern RAN_CONTEXT_t RC;
@@ -113,8 +117,9 @@ extern uint32_t to_earfcn_DL(int eutra_bandP, uint32_t dl_CarrierFreq, uint32_t
extern int rrc_eNB_process_security(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, security_capabilities_t *security_capabilities_pP);
extern void process_eNB_security_key (const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP, uint8_t *security_key_pP);
extern int derive_keNB_star(const uint8_t *kenb_32, const uint16_t pci, const uint32_t earfcn_dl, const bool is_rel8_only, uint8_t *kenb_star);
-extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config, OCTET_STRING_t *scg_RB_config);
-extern struct rrc_eNB_ue_context_s * get_first_ue_context(eNB_RRC_INST *rrc_instance_pP);
+extern int rrc_eNB_generate_RRCConnectionReconfiguration_endc(protocol_ctxt_t *ctxt, rrc_eNB_ue_context_t *ue_context, unsigned char *buffer, int buffer_size, OCTET_STRING_t *scg_group_config,
+ OCTET_STRING_t *scg_RB_config);
+extern struct rrc_eNB_ue_context_s *get_first_ue_context(eNB_RRC_INST *rrc_instance_pP);
pthread_mutex_t rrc_release_freelist;
RRC_release_list_t rrc_release_info;
@@ -150,6 +155,7 @@ init_SI(
LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__);
if(configuration->radioresourceconfig[CC_id].mbms_dedicated_serving_cell == TRUE) {
+
LOG_I(RRC, "Configuring MIB FeMBMS (N_RB_DL %d)\n",
(int)configuration->N_RB_DL[CC_id]);
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].MIB_FeMBMS = (uint8_t *) malloc16(4);
@@ -162,7 +168,7 @@ init_SI(
AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].SIB1_MBMS!=NULL,PROTOCOL_RRC_CTXT_FMT" init_SI: FATAL, no memory for SIB1_MBMS allocated\n",
PROTOCOL_RRC_CTXT_ARGS(ctxt_pP));
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1_MBMS = do_SIB1_MBMS(&RC.rrc[ctxt_pP->module_id]->carrier[CC_id],ctxt_pP->module_id,CC_id,
- configuration
+ configuration
);
LOG_I(RRC, PROTOCOL_RRC_CTXT_FMT" Contents of SIB1-MBMS\n",
PROTOCOL_RRC_CTXT_ARGS(ctxt_pP)
@@ -226,6 +232,7 @@ init_SI(
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sib1_MBMS->nonMBSFN_SubframeConfig_r14->subframeAllocation_r14.buf);
}
+ RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag=1;
//AssertFatal(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB1 != 255,"FATAL, RC.rrc[enb_mod_idP].carrier[CC_id].sizeof_SIB1 == 255");
}
@@ -491,12 +498,15 @@ init_SI(
(LTE_PMCH_InfoList_r9_t *) NULL,
sib1_v13ext,
RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag,
- (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL,
+ (carrier->sib1_MBMS==NULL?(LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL:(LTE_BCCH_DL_SCH_Message_MBMS_t *)carrier->sib1_MBMS),//(LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL,
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
- (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
- (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
- );
+ (carrier->sib1_MBMS==NULL?(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL:(struct LTE_NonMBSFN_SubframeConfig_r14 *)carrier->sib1_MBMS->nonMBSFN_SubframeConfig_r14),//(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
+ (carrier->sib1_MBMS==NULL?(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL:(LTE_SystemInformationBlockType1_MBMS_r14_t *)carrier->sib1_MBMS->systemInformationBlockType13_r14),//(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
+ (carrier->sib1_MBMS==NULL?(LTE_MBSFN_AreaInfoList_r9_t *) NULL:(LTE_MBSFN_AreaInfoList_r9_t *)&carrier->sib1_MBMS->systemInformationBlockType13_r14->mbsfn_AreaInfoList_r9)//(LTE_MBSFN_AreaInfoList_r9_t *) NULL
+
+ ,(LTE_MBSFNAreaConfiguration_r9_t*) NULL
+
+ );
}
/* set flag to indicate that cell information is configured. This is required
@@ -579,7 +589,8 @@ init_MCCH(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
@@ -989,11 +1000,14 @@ void put_UE_in_freelist(module_id_t mod_id, rnti_t rnti, boolean_t removeFlag) {
pthread_mutex_unlock(&lock_ue_freelist);
}
+extern int16_t find_dlsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type);
+extern int16_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type);
+extern void clean_eNb_ulsch(LTE_eNB_ULSCH_t *ulsch);
+extern void clean_eNb_dlsch(LTE_eNB_DLSCH_t *dlsch);
+
void release_UE_in_freeList(module_id_t mod_id) {
int i, j, CC_id, pdu_number;
protocol_ctxt_t ctxt;
- LTE_eNB_ULSCH_t *ulsch = NULL;
- LTE_eNB_DLSCH_t *dlsch = NULL;
nfapi_ul_config_request_body_t *ul_req_tmp = NULL;
PHY_VARS_eNB *eNB_PHY = NULL;
struct rrc_eNB_ue_context_s *ue_context_pP = NULL;
@@ -1027,6 +1041,25 @@ void release_UE_in_freeList(module_id_t mod_id) {
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
eNB_PHY = RC.eNB[mod_id][CC_id];
+ int id;
+
+ // clean ULSCH entries for rnti
+ id = find_ulsch(rnti,eNB_PHY,SEARCH_EXIST);
+ if (id>=0) clean_eNb_ulsch(eNB_PHY->ulsch[id]);
+
+ // clean DLSCH entries for rnti
+ id = find_dlsch(rnti,eNB_PHY,SEARCH_EXIST);
+ if (id>=0) clean_eNb_dlsch(eNB_PHY->dlsch[id][0]);
+
+ // clean UCI entries for rnti
+ for (i=0; i<NUMBER_OF_UCI_VARS_MAX; i++) {
+ if(eNB_PHY->uci_vars[i].rnti == rnti) {
+ LOG_I(MAC, "clean eNb uci_vars[%d] UE %x \n",i, rnti);
+ memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI));
+ }
+ }
+
+ /*
for (i=0; i<MAX_MOBILES_PER_ENB; i++) {
ulsch = eNB_PHY->ulsch[i];
@@ -1059,6 +1092,7 @@ void release_UE_in_freeList(module_id_t mod_id) {
memset(&eNB_PHY->uci_vars[i],0,sizeof(LTE_eNB_UCI));
}
}
+ */
if (flexran_agent_get_rrc_xface(mod_id)) {
flexran_agent_get_rrc_xface(mod_id)->flexran_agent_notify_ue_state_change(
@@ -1453,7 +1487,8 @@ rrc_eNB_generate_RRCConnectionReestablishment(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
break;
}
@@ -2119,7 +2154,27 @@ rrc_eNB_generate_RRCConnectionReestablishmentReject(
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
ue_p->Srb0.Tx_buffer.payload_size);
}
-
+#if 0
+void rrc_generate_SgNBReleaseRequest(
+ const protocol_ctxt_t *const ctxt_pP,
+ rrc_eNB_ue_context_t *const ue_context_pP
+)
+//-----------------------------------------------------------------------------
+{
+ MessageDef *msg;
+ msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_RELEASE_REQ);
+ memset(&(X2AP_ENDC_SGNB_RELEASE_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_release_req_t));
+ // X2AP_ENDC_SGNB_RELEASE_REQ(msg).MeNB_ue_x2_id = ;
+ // X2AP_ENDC_SGNB_RELEASE_REQ(msg).SgNB_ue_x2_id = ;
+ // X2AP_ENDC_SGNB_RELEASE_REQ(msg).cause = ;
+ // X2AP_ENDC_SGNB_RELEASE_REQ(msg).target_physCellId = ;
+ LOG_I(RRC,
+ "[eNB %d] frame %d UE rnti %x transmitting sgnb release request to sgnb \n",
+ ctxt_pP->module_id,ctxt_pP->frame,ctxt_pP->rnti);
+ itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg);
+ return;
+}
+#endif
//-----------------------------------------------------------------------------
/*
* Generate the RRC Connection Release to UE.
@@ -2139,6 +2194,15 @@ rrc_eNB_generate_RRCConnectionRelease(
memset(buffer, 0, RRC_BUF_SIZE);
T(T_ENB_RRC_CONNECTION_RELEASE, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame),
T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti));
+#if 0
+
+ if(ue_context_pP != NULL) {
+ if(ue_context_pP->ue_context.Status == RRC_NR_NSA) {
+ //rrc_eNB_generate_SgNBReleaseRequest(ctxt_pP,ue_context_pP);
+ }
+ }
+
+#endif
size = do_RRCConnectionRelease(ctxt_pP->module_id, buffer,rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id));
ue_context_pP->ue_context.ue_reestablishment_timer = 0;
ue_context_pP->ue_context.ue_release_timer = 0;
@@ -2837,7 +2901,6 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
uint16_t size;
int i;
MessageDef *message_p = NULL;
-
/* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */
eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id];
struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated;
@@ -3029,7 +3092,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
module_id_t module_id = ctxt_pP->module_id;
LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n");
- /* Process the IE drx_Config */
+ /* Process the IE drx_Config */
if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) {
mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE
@@ -3044,8 +3107,8 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n");
}
}
- /* End of CDRX configuration */
+ /* End of CDRX configuration */
sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long));
*sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR
mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1));
@@ -3153,7 +3216,9 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
if (ue_context_pP->ue_context.does_nr) {
MeasId6 = calloc(1, sizeof(LTE_MeasIdToAddMod_t));
+
if (MeasId6 == NULL) exit(1);
+
MeasId6->measId = 7;
MeasId6->measObjectId = 2;
MeasId6->reportConfigId = 7;
@@ -3211,22 +3276,27 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
if (ue_context_pP->ue_context.does_nr) {
MeasObj2 = calloc(1, sizeof(LTE_MeasObjectToAddMod_t));
+
if (MeasObj2 == NULL) exit(1);
+
MeasObj2->measObjectId = 2;
MeasObj2->measObject.present = LTE_MeasObjectToAddMod__measObject_PR_measObjectNR_r15;
- MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 = 642256; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016)
+ MeasObj2->measObject.choice.measObjectNR_r15.carrierFreq_r15 =641272; //634000; //(634000 = 3.51GHz) (640000 = 3.6GHz) (641272 = 3619.08MHz = 3600 + 30/1000*106*12/2) (642256 is for 3.6GHz and absoluteFrequencySSB = 642016)
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.present = LTE_MTC_SSB_NR_r15__periodicityAndOffset_r15_PR_sf20_r15;
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.periodicityAndOffset_r15.choice.sf20_r15 = 0;
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.measTimingConfig_r15.ssb_Duration_r15 = LTE_MTC_SSB_NR_r15__ssb_Duration_r15_sf4;
MeasObj2->measObject.choice.measObjectNR_r15.rs_ConfigSSB_r15.subcarrierSpacingSSB_r15 = LTE_RS_ConfigSSB_NR_r15__subcarrierSpacingSSB_r15_kHz30;
MeasObj2->measObject.choice.measObjectNR_r15.quantityConfigSet_r15 = 1;
MeasObj2->measObject.choice.measObjectNR_r15.ext1 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1));
+
if (MeasObj2->measObject.choice.measObjectNR_r15.ext1 == NULL) exit(1);
+
MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 = calloc(1, sizeof(struct LTE_MeasObjectNR_r15__ext1__bandNR_r15));
+
if (MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15 == NULL) exit(1);
+
MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->present = LTE_MeasObjectNR_r15__ext1__bandNR_r15_PR_setup;
MeasObj2->measObject.choice.measObjectNR_r15.ext1->bandNR_r15->choice.setup = 78;
-
ASN_SEQUENCE_ADD(&MeasObj_list->list, MeasObj2);
}
@@ -3242,9 +3312,11 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
ReportConfig_A3 = CALLOC(1, sizeof(*ReportConfig_A3));
ReportConfig_A4 = CALLOC(1, sizeof(*ReportConfig_A4));
ReportConfig_A5 = CALLOC(1, sizeof(*ReportConfig_A5));
+
if (ue_context_pP->ue_context.does_nr) {
ReportConfig_NR = CALLOC(1, sizeof(*ReportConfig_NR));
}
+
ReportConfig_per->reportConfigId = 1;
ReportConfig_per->reportConfig.present = LTE_ReportConfigToAddMod__reportConfig_PR_reportConfigEUTRA;
ReportConfig_per->reportConfig.choice.reportConfigEUTRA.triggerType.present =
@@ -3357,7 +3429,7 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.present = LTE_ReportConfigInterRAT__triggerType_PR_event;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.present = LTE_ReportConfigInterRAT__triggerType__event__eventId_PR_eventB1_NR_r15;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.present = LTE_ThresholdNR_r15_PR_nr_RSRP_r15;
- ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 46;
+ ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.b1_ThresholdNR_r15.choice.nr_RSRP_r15 = 0;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.eventId.choice.eventB1_NR_r15.reportOnLeave_r15 = FALSE;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.hysteresis = 2;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.triggerType.choice.event.timeToTrigger = LTE_TimeToTrigger_ms80;
@@ -3365,9 +3437,13 @@ void rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt_t
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportInterval = LTE_ReportInterval_ms120;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.reportAmount = LTE_ReportConfigInterRAT__reportAmount_infinity;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 = calloc(1, sizeof(struct LTE_ReportConfigInterRAT__ext7));
+
if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7 == NULL) exit(1);
+
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 = calloc(1, sizeof(struct LTE_ReportQuantityNR_r15));
+
if (ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15 == NULL) exit(1);
+
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrp = TRUE;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_rsrq = TRUE;
ReportConfig_NR->reportConfig.choice.reportConfigInterRAT.ext7->reportQuantityCellNR_r15->ss_sinr = TRUE;
@@ -3569,7 +3645,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
uint16_t size;
int i;
MessageDef *message_p = NULL;
-
/* Configure SRB1/SRB2, PhysicalConfigDedicated, LTE_MAC_MainConfig for UE */
eNB_RRC_INST *rrc_inst = RC.rrc[ctxt_pP->module_id];
struct LTE_PhysicalConfigDedicated **physicalConfigDedicated = &ue_context_pP->ue_context.physicalConfigDedicated;
@@ -3615,7 +3690,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
LTE_C_RNTI_t *cba_RNTI = NULL;
int measurements_enabled;
uint8_t xid = rrc_eNB_get_next_transaction_identifier(ctxt_pP->module_id); //Transaction_id,
-
#ifdef CBA // Contention Based Access
uint8_t *cba_RNTI_buf;
cba_RNTI = CALLOC(1, sizeof(LTE_C_RNTI_t));
@@ -3641,8 +3715,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
frameP,
ue_mod_idP);
}
-#endif
+#endif
T(T_ENB_RRC_CONNECTION_RECONFIGURATION,
T_INT(ctxt_pP->module_id),
T_INT(ctxt_pP->frame),
@@ -3777,7 +3851,6 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
mac_MainConfig->phr_Config->choice.setup.prohibitPHR_Timer =
LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf200; // sf20 = 20 subframes // LTE_MAC_MainConfig__phr_Config__setup__prohibitPHR_Timer_sf1000
mac_MainConfig->phr_Config->choice.setup.dl_PathlossChange = LTE_MAC_MainConfig__phr_Config__setup__dl_PathlossChange_dB3; // Value dB1 =1 dB, dB3 = 3 dB
-
/* CDRX Configuration */
mac_MainConfig->drx_Config = NULL;
rnti_t rnti = ue_context_pP->ue_id_rnti;
@@ -3785,11 +3858,11 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
uint8_t cc_id = ue_context_pP->ue_context.primaryCC_id;
LTE_UE_EUTRA_Capability_t *UEcap = ue_context_pP->ue_context.UE_Capability;
LOG_D(RRC, "Processing the DRX configuration in RRC Connection Reconfiguration\n");
-
+
/* Process the IE drx_Config */
if (NODE_IS_MONOLITHIC(rrc_inst->node_type)) {
mac_MainConfig->drx_Config = do_DrxConfig(cc_id, &rrc_inst->configuration, UEcap); // drx_Config IE
-
+
if (mac_MainConfig->drx_Config == NULL) {
LOG_W(RRC, "drx_Configuration parameter is NULL, cannot configure local UE parameters or CDRX is deactivated\n");
} else {
@@ -3801,8 +3874,8 @@ flexran_rrc_eNB_generate_defaultRRCConnectionReconfiguration(const protocol_ctxt
LOG_D(RRC, "DRX configured in MAC Main Configuration for RRC Connection Reconfiguration\n");
}
}
- /* End of CDRX configuration */
+ /* End of CDRX configuration */
sr_ProhibitTimer_r9 = CALLOC(1, sizeof(long));
*sr_ProhibitTimer_r9 = 0; // SR tx on PUCCH, Value in number of SR period(s). Value 0 = no timer for SR, Value 2 = 2*SR
mac_MainConfig->ext1 = CALLOC(1, sizeof(struct LTE_MAC_MainConfig__ext1));
@@ -4319,6 +4392,182 @@ rrc_eNB_generate_RRCConnectionReconfiguration_SCell(
}
+
+//-----------------------------------------------------------------------------
+/**
+ * @fn :encode_CG_ConfigInfo
+ * @param :enc_buf to store the encoded bits
+ * @param :ue_context_pP ue context used to fill CG-ConfigInfo
+ * @param :enc_size to store thre size of encoded size
+ * this api is to fill and encode CG-ConfigInfo
+ */
+static int encode_CG_ConfigInfo(
+ char *buffer,
+ int buffer_size,
+ rrc_eNB_ue_context_t *const ue_context_pP,
+ int *enc_size
+) {
+ struct NR_CG_ConfigInfo *cg_configinfo = NULL;
+ struct NR_RadioBearerConfig *rb_config = NULL;
+ asn_enc_rval_t enc_rval;
+ int RRC_OK = 1;
+ int index = 0;
+ char temp_buff[ASN_MAX_ENCODE_SIZE];
+ LTE_UE_CapabilityRAT_ContainerList_t *ue_cap_rat_container_list = NULL;
+ LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_MRDC;
+ LTE_UE_CapabilityRAT_Container_t ue_cap_rat_container_nr;
+ int RAT_Container_count = 0;
+ rb_config = calloc(1,sizeof(struct NR_RadioBearerConfig));
+ AssertFatal(rb_config != NULL,"failed to allocate memory for rb_config");
+
+ if(ue_context_pP->ue_context.DRB_configList->list.count != 0) {
+ rb_config->drb_ToAddModList = calloc(1,sizeof(struct NR_DRB_ToAddModList ));
+ AssertFatal(rb_config->drb_ToAddModList != NULL,"failed to allocated memory for drbtoaddmodlist");
+ rb_config->drb_ToAddModList->list.count = NUMBEROF_DRBS_TOBE_ADDED;
+ rb_config->drb_ToAddModList->list.array
+ = calloc(NUMBEROF_DRBS_TOBE_ADDED, sizeof(struct NR_DRB_ToAddMod *));
+ AssertFatal( rb_config->drb_ToAddModList->list.array != NULL,
+ "falied to allocate memory for list.array");
+
+ for(index = 0; index < NUMBEROF_DRBS_TOBE_ADDED; index++) {
+ rb_config->drb_ToAddModList->list.array[index]
+ = calloc(1,sizeof(struct NR_DRB_ToAddMod));
+ AssertFatal(rb_config->drb_ToAddModList->list.array[index] != NULL,
+ "failed to allocate memory for drb_toaddmod");
+ rb_config->drb_ToAddModList->list.array[index]->drb_Identity
+ = ue_context_pP->ue_context.DRB_configList->list.array[index]->drb_Identity;
+
+ if(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity) {
+ rb_config->drb_ToAddModList->list.array[index]->cnAssociation
+ = calloc(1,sizeof(struct NR_DRB_ToAddMod__cnAssociation));
+ AssertFatal(rb_config->drb_ToAddModList->list.array[index]->cnAssociation != NULL,
+ "failed to allocate memory cnAssociation");
+ rb_config->drb_ToAddModList->list.array[index]->cnAssociation->present
+ = NR_DRB_ToAddMod__cnAssociation_PR_eps_BearerIdentity;
+ rb_config->drb_ToAddModList->list.array[index]->cnAssociation->choice.eps_BearerIdentity
+ = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->eps_BearerIdentity);
+ }
+
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config = calloc(1,sizeof(struct NR_PDCP_Config));
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb = calloc(1,sizeof(struct NR_PDCP_Config__drb));
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer = calloc(1,sizeof(long));
+ *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->discardTimer
+ = *(ue_context_pP->ue_context.DRB_configList->list.array[index]->pdcp_Config->discardTimer);
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL = calloc(1,sizeof(long));
+ *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeUL
+ = NR_PDCP_Config__drb__pdcp_SN_SizeUL_len18bits;
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL = calloc(1,sizeof(long));
+ *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->pdcp_SN_SizeDL
+ = NR_PDCP_Config__drb__pdcp_SN_SizeDL_len18bits;
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.present
+ = NR_PDCP_Config__drb__headerCompression_PR_notUsed;
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->drb->headerCompression.choice.notUsed = 0;
+ rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering = calloc(1,sizeof(long));
+ *rb_config->drb_ToAddModList->list.array[index]->pdcp_Config->t_Reordering
+ = NR_PDCP_Config__t_Reordering_ms0;
+ }
+
+ rb_config->securityConfig = calloc(1,sizeof(struct NR_SecurityConfig ));
+ rb_config->securityConfig->securityAlgorithmConfig = calloc(1,sizeof(struct NR_SecurityAlgorithmConfig));
+ rb_config->securityConfig->securityAlgorithmConfig->cipheringAlgorithm = NR_CipheringAlgorithm_nea0;
+ rb_config->securityConfig->securityAlgorithmConfig->integrityProtAlgorithm = NULL;
+ rb_config->securityConfig->keyToUse = calloc(1,sizeof(long));
+ *rb_config->securityConfig->keyToUse = NR_SecurityConfig__keyToUse_master;
+ }
+
+ cg_configinfo = calloc(1,sizeof(struct NR_CG_ConfigInfo));
+ AssertFatal(cg_configinfo != NULL,"failed to allocate memory for cg_configinfo");
+ cg_configinfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1;
+ cg_configinfo->criticalExtensions.choice.c1
+ = calloc(1, sizeof(struct NR_CG_ConfigInfo__criticalExtensions__c1));
+ AssertFatal(cg_configinfo->criticalExtensions.choice.c1 != NULL,
+ "failed to allocate memory for cg_configinfo->criticalExtensions.choice.c1");
+ cg_configinfo->criticalExtensions.choice.c1->present
+ = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo;
+ cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo
+ = calloc(1,sizeof(struct NR_CG_ConfigInfo_IEs));
+ AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo != NULL,
+ "failed to allocate memory for cg_configinfo_IEs");
+ cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo
+ = calloc(1,sizeof( OCTET_STRING_t));
+ AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->
+ ue_CapabilityInfo != NULL, "failed to allocate memory for ue_capabilityinfo");
+
+ if(ue_context_pP->ue_context.UE_Capability_MRDC) {
+ RAT_Container_count++;
+ enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_MRDC_Capability,NULL,
+ (void *)ue_context_pP->ue_context.UE_Capability_MRDC,temp_buff,ASN_MAX_ENCODE_SIZE);
+ AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ ue_cap_rat_container_MRDC.rat_Type = LTE_RAT_Type_eutra_nr;
+ OCTET_STRING_fromBuf(&ue_cap_rat_container_MRDC.ueCapabilityRAT_Container,
+ (const char *)temp_buff,(enc_rval.encoded+7)>>3);
+ memset((void *)temp_buff,0,sizeof(temp_buff));
+ }
+
+ if(ue_context_pP->ue_context.UE_Capability_nr) {
+ RAT_Container_count++;
+ enc_rval = uper_encode_to_buffer(&asn_DEF_NR_UE_NR_Capability,NULL,
+ (void *)ue_context_pP->ue_context.UE_Capability_nr,temp_buff,ASN_MAX_ENCODE_SIZE);
+ AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ ue_cap_rat_container_nr.rat_Type = LTE_RAT_Type_nr;
+ OCTET_STRING_fromBuf(&ue_cap_rat_container_nr.ueCapabilityRAT_Container,
+ (const char *)temp_buff,(enc_rval.encoded+7)>>3);
+ memset((void *)temp_buff,0,sizeof(temp_buff));
+ }
+
+ ue_cap_rat_container_list = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t));
+ ue_cap_rat_container_list->list.count = RAT_Container_count;
+ ue_cap_rat_container_list->list.size = RAT_Container_count * sizeof(LTE_UE_CapabilityRAT_Container_t);
+ ue_cap_rat_container_list->list.array = calloc(RAT_Container_count,sizeof(LTE_UE_CapabilityRAT_Container_t *));
+
+ if(ue_context_pP->ue_context.UE_Capability_MRDC) {
+ ue_cap_rat_container_list->list.array[0] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t));
+ memcpy(ue_cap_rat_container_list->list.array[0],&ue_cap_rat_container_MRDC,sizeof(LTE_UE_CapabilityRAT_Container_t));
+ }
+
+ if(ue_context_pP->ue_context.UE_Capability_nr) {
+ ue_cap_rat_container_list->list.array[1] = calloc(1,sizeof(LTE_UE_CapabilityRAT_Container_t));
+ memcpy(ue_cap_rat_container_list->list.array[1],&ue_cap_rat_container_nr,sizeof(LTE_UE_CapabilityRAT_Container_t));
+ }
+
+ //this xer_fprint logs can be enabled for additional debugging logs
+ //xer_fprint(stdout,&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list);
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,
+ (void *)ue_cap_rat_container_list,temp_buff,ASN_MAX_ENCODE_SIZE);
+ AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->ue_CapabilityInfo,
+ (const char *)temp_buff, (enc_rval.encoded+7)>>3);
+ cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config
+ = calloc(1,sizeof(OCTET_STRING_t));
+ AssertFatal(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->
+ mcg_RB_Config != NULL, "failed to allocate memory for mcg_rb_config");
+ enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig,NULL,(void *)rb_config,temp_buff,ASN_MAX_ENCODE_SIZE);
+ AssertFatal(enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ OCTET_STRING_fromBuf(cg_configinfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo->mcg_RB_Config,
+ (const char *)temp_buff, (enc_rval.encoded+7)>>3);
+ // this xer_fprint can be enabled for additional debugging messages
+ // xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo,(void *)cg_configinfo);
+ enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_ConfigInfo,NULL,(void *)cg_configinfo,
+ buffer,buffer_size);
+ AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ *enc_size = (enc_rval.encoded+7)/8;
+ ASN_STRUCT_FREE(asn_DEF_NR_RadioBearerConfig,rb_config);
+ ASN_STRUCT_FREE(asn_DEF_NR_CG_ConfigInfo,cg_configinfo);
+ ASN_STRUCT_FREE(asn_DEF_LTE_UE_CapabilityRAT_ContainerList,ue_cap_rat_container_list);
+ return RRC_OK;
+}
+//-----------------------------------------------------------------------------
+
+
+
+
+
+
//-----------------------------------------------------------------------------
void
rrc_eNB_process_MeasurementReport(
@@ -4334,6 +4583,8 @@ rrc_eNB_process_MeasurementReport(
long ncell_max = -150;
uint32_t earfcn_dl;
uint8_t KeNB_star[32] = { 0 };
+ char enc_buf[ASN_MAX_ENCODE_SIZE] = {0};
+ int enc_size = 0;
T(T_ENB_RRC_MEASUREMENT_REPORT, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame),
T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti));
@@ -4392,17 +4643,41 @@ rrc_eNB_process_MeasurementReport(
/* TODO: improve NR triggering */
if (measResults2->measId == 7) {
- if (ue_context_pP->ue_context.Status != RRC_NR_NSA) {
+ if ((ue_context_pP->ue_context.Status != RRC_NR_NSA) && (ue_context_pP->ue_context.Status != RRC_NR_NSA_RECONFIGURED)) {
MessageDef *msg;
ue_context_pP->ue_context.Status = RRC_NR_NSA;
- msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ);
- X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti;
- LOG_I(RRC,
- "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n",
- ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti);
- itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg);
- return;
+ if(is_en_dc_supported(ue_context_pP->ue_context.UE_Capability)) {
+ /** to add gNB as Secondary node CG-ConfigInfo to be added as per 36.423 r15 **/
+ if(encode_CG_ConfigInfo(enc_buf,sizeof(enc_buf),ue_context_pP,&enc_size) == RRC_OK)
+ LOG_I(RRC,"CG-ConfigInfo encoded successfully\n");
+
+ msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ);
+ memset(&(X2AP_ENDC_SGNB_ADDITION_REQ(msg)), 0, sizeof(x2ap_ENDC_sgnb_addition_req_t));
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).rnti = ctxt_pP->rnti;
+ memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer,enc_buf,enc_size);
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = enc_size;
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_physCellId
+ = measResults2->measResultNeighCells->choice.measResultListEUTRA.list.array[0]->physCellId;
+ //For the moment we have a single E-RAB which will be the one to be added to the gNB
+ //Not sure how to select bearers to be added if there are multiple.
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded = 1;
+
+ for (int e_rab=0; e_rab < X2AP_ENDC_SGNB_ADDITION_REQ(msg).nb_e_rabs_tobeadded; e_rab++) {
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id;
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].gtp_teid = ue_context_pP->ue_context.e_rab[e_rab].param.gtp_teid;
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].drb_ID = ue_context_pP->ue_context.DRB_configList->list.array[e_rab]->drb_Identity;
+ memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[e_rab].sgw_addr,
+ &ue_context_pP->ue_context.e_rab[e_rab].param.sgw_addr,
+ sizeof(transport_layer_addr_t));
+ }
+
+ LOG_I(RRC,
+ "[eNB %d] frame %d subframe %d: UE rnti %x switching to NSA mode\n",
+ ctxt_pP->module_id, ctxt_pP->frame, ctxt_pP->subframe, ctxt_pP->rnti);
+ itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(ctxt_pP->module_id), msg);
+ return;
+ }
}
}
@@ -4520,6 +4795,7 @@ rrc_eNB_process_MeasurementReport(
}
}
+
//-----------------------------------------------------------------------------
void
rrc_eNB_generate_HandoverPreparationInformation(
@@ -5512,7 +5788,8 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
// Configure target eNB SRB2
/// SRB2
@@ -6047,6 +6324,7 @@ rrc_eNB_generate_HO_RRCConnectionReconfiguration(const protocol_ctxt_t *const ct
ue_context_pP->ue_context.e_rab[i].param.nas_pdu.buffer = NULL;
}
}
+
LOG_I(RRC,
"[eNB %d] Frame %d, Logical Channel DL-DCCH, Generate RRCConnectionReconfiguration handover (bytes %d, UE id %x)\n",
ctxt_pP->module_id, ctxt_pP->frame, size, ue_context_pP->ue_context.rnti);
@@ -6191,7 +6469,8 @@ rrc_eNB_configure_rbs_handover(struct rrc_eNB_ue_context_s *ue_context_p, protoc
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
@@ -6217,10 +6496,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
LTE_SRB_ToAddModList_t *SRB_configList = ue_context_pP->ue_context.SRB_configList2[xid];
LTE_DRB_ToReleaseList_t *DRB_Release_configList2 = ue_context_pP->ue_context.DRB_Release_configList2[xid];
LTE_DRB_Identity_t *drb_id_p = NULL;
-
ue_context_pP->ue_context.ue_reestablishment_timer = 0;
ue_context_pP->ue_context.ue_rrc_inactivity_timer = 1; // reset rrc inactivity timer
-
/* CDRX: activated when RRC Connection Reconfiguration Complete is received */
rnti_t rnti = ue_context_pP->ue_id_rnti;
module_id_t module_id = ctxt_pP->module_id;
@@ -6241,8 +6518,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
LOG_I(RRC, "CDRX configuration activated after RRC Connection Reconfiguration Complete reception\n");
}
}
- /* End of CDRX processing */
+ /* End of CDRX processing */
T(T_ENB_RRC_CONNECTION_RECONFIGURATION_COMPLETE,
T_INT(ctxt_pP->module_id),
T_INT(ctxt_pP->frame),
@@ -6409,7 +6686,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
} else { // remove LCHAN from MAC/PHY
@@ -6468,7 +6746,8 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
} // end else of if (ue_context_pP->ue_context.DRB_active[drb_id] == 0)
@@ -6503,7 +6782,6 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
ue_context_pP->ue_context.nr_capabilities_requested = 1;
rrc_eNB_generate_NR_UECapabilityEnquiry(ctxt_pP, ue_context_pP);
}
-
}
//-----------------------------------------------------------------------------
@@ -6631,7 +6909,8 @@ rrc_eNB_generate_RRCConnectionSetup(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
break;
}
@@ -6682,14 +6961,6 @@ char openair_rrc_eNB_configuration(
LOG_I(RRC,
PROTOCOL_RRC_CTXT_FMT" Init...\n",
PROTOCOL_RRC_CTXT_ARGS(&ctxt));
-#if OCP_FRAMEWORK
-
- while ( RC.rrc[enb_mod_idP] == NULL ) {
- LOG_E(RRC, "RC.rrc not yet initialized, waiting 1 second\n");
- sleep(1);
- }
-
-#endif
AssertFatal(RC.rrc[enb_mod_idP] != NULL, "RC.rrc not initialized!");
AssertFatal(MAX_MOBILES_PER_ENB < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow");
AssertFatal(configuration!=NULL,"configuration input is null\n");
@@ -7334,33 +7605,34 @@ is_en_dc_supported(
*/
#define NCE nonCriticalExtension
return c != NULL
- && c->NCE != NULL
- && c->NCE->NCE != NULL
- && c->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL
- && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL
- && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 == LTE_IRAT_ParametersNR_r15__en_DC_r15_supported;
+ && c->NCE != NULL
+ && c->NCE->NCE != NULL
+ && c->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15 != NULL
+ && c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 != NULL
+ && *c->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->NCE->irat_ParametersNR_r15->en_DC_r15 ==
+ LTE_IRAT_ParametersNR_r15__en_DC_r15_supported;
#undef NCE
}
@@ -7536,7 +7808,37 @@ rrc_eNB_decode_dcch(
LOG_I(RRC,
PROTOCOL_RRC_CTXT_UE_FMT" UE State = RRC_HO_EXECUTION (xid %ld)\n",
PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.rrc_TransactionIdentifier);
- } else {
+ }
+ else if(ue_context_p->ue_context.Status == RRC_NR_NSA){
+ //Looking for a condition to trigger S1AP E-RAB-Modification-indication, based on the reception of RRCConnectionReconfigurationComplete
+ //including NR specific elements.
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension!=NULL) {
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension!=NULL) {
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
+ if (ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension!=NULL) {
+ if(ul_dcch_msg->message.choice.c1.choice.rrcConnectionReconfigurationComplete.criticalExtensions.choice.rrcConnectionReconfigurationComplete_r8.
+ nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension->nonCriticalExtension
+ ->scg_ConfigResponseNR_r15!=NULL) {
+ ue_context_p->ue_context.Status = RRC_NR_NSA_RECONFIGURED;
+ /*Trigger E-RAB Modification Indication */
+ rrc_eNB_send_E_RAB_Modification_Indication(ctxt_pP, ue_context_p);
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ else {
dedicated_DRB = 0;
ue_context_p->ue_context.Status = RRC_RECONFIGURED;
LOG_I(RRC,
@@ -7545,6 +7847,7 @@ rrc_eNB_decode_dcch(
}
ue_context_p->ue_context.reestablishment_xid = -1;
+
} else {
dedicated_DRB = 1;
ue_context_p->ue_context.Status = RRC_RECONFIGURED;
@@ -7892,15 +8195,74 @@ rrc_eNB_decode_dcch(
}
LOG_I(RRC, "got UE capabilities for UE %x\n", ctxt_pP->rnti);
-
int eutra_index = -1;
for (i = 0; i < ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.count; i++) {
- if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type == LTE_RAT_Type_eutra) {
+ if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type ==
+ LTE_RAT_Type_nr) {
+ if(ue_context_p->ue_context.UE_Capability_nr) {
+ ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr);
+ ue_context_p->ue_context.UE_Capability_nr = 0;
+ }
+
+ dec_rval = uper_decode(NULL,
+ &asn_DEF_NR_UE_NR_Capability,
+ (void **)&ue_context_p->ue_context.UE_Capability_nr,
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf,
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size,
+ 0, 0);
+
+ if (LOG_DEBUGFLAG(DEBUG_ASN1)) {
+ xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr);
+ }
+
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode nr UE capabilities (%zu bytes)\n",
+ PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed);
+ ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,ue_context_p->ue_context.UE_Capability_nr);
+ ue_context_p->ue_context.UE_Capability_nr = 0;
+ }
+
+ ue_context_p->ue_context.UE_NR_Capability_size =
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size;
+ }
+
+ if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type ==
+ LTE_RAT_Type_eutra_nr) {
+ if(ue_context_p->ue_context.UE_Capability_MRDC) {
+ ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC);
+ ue_context_p->ue_context.UE_Capability_MRDC = 0;
+ }
+
+ dec_rval = uper_decode(NULL,
+ &asn_DEF_NR_UE_MRDC_Capability,
+ (void **)&ue_context_p->ue_context.UE_Capability_MRDC,
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.buf,
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size,
+ 0, 0);
+
+ if (LOG_DEBUGFLAG(DEBUG_ASN1)) {
+ xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC);
+ }
+
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ LOG_E(RRC, PROTOCOL_RRC_CTXT_UE_FMT" Failed to decode MRDC UE capabilities (%zu bytes)\n",
+ PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),dec_rval.consumed);
+ ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,ue_context_p->ue_context.UE_Capability_MRDC);
+ ue_context_p->ue_context.UE_Capability_MRDC = 0;
+ }
+
+ ue_context_p->ue_context.UE_MRDC_Capability_size =
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->ueCapabilityRAT_Container.size;
+ }
+
+ if (ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[i]->rat_Type ==
+ LTE_RAT_Type_eutra) {
if (eutra_index != -1) {
LOG_E(RRC, "fatal: more than 1 eutra capability\n");
exit(1);
}
+
eutra_index = i;
}
}
@@ -7922,7 +8284,8 @@ rrc_eNB_decode_dcch(
ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.buf,
ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size,
0, 0);
- ue_context_p->ue_context.UE_Capability_size = ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size;
+ ue_context_p->ue_context.UE_Capability_size =
+ ul_dcch_msg->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList.list.array[eutra_index]->ueCapabilityRAT_Container.size;
if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
xer_fprint(stdout, &asn_DEF_LTE_UE_EUTRA_Capability, ue_context_p->ue_context.UE_Capability);
@@ -8020,6 +8383,8 @@ rrc_eNB_decode_dcch(
case LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10:
T(T_ENB_RRC_MBMS_COUNTING_RESPONSE_R10, T_INT(ctxt_pP->module_id), T_INT(ctxt_pP->frame),
T_INT(ctxt_pP->subframe), T_INT(ctxt_pP->rnti));
+ LOG_E(RRC, "THINH [LTE_UL_DCCH_MessageType__c1_PR_mbmsCountingResponse_r10]\n");
+
break;
case LTE_UL_DCCH_MessageType__c1_PR_interFreqRSTDMeasurementIndication_r10:
@@ -8039,36 +8404,54 @@ rrc_eNB_decode_dcch(
return 0;
//TTN for D2D
} else if (ul_dcch_msg->message.present == LTE_UL_DCCH_MessageType_PR_messageClassExtension) {
- LOG_I(RRC, "THINH [LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n");
+ LOG_I(RRC, "[LTE_UL_DCCH_MessageType_PR_messageClassExtension]\n");
switch (ul_dcch_msg->message.choice.messageClassExtension.present) {
case LTE_UL_DCCH_MessageType__messageClassExtension_PR_NOTHING: /* No components present */
break;
case LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2: //SidelinkUEInformation
- //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation
- LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n");
- LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP,
+ if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present ==
+ LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_scgFailureInformationNR_r15){
+ if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.
+ criticalExtensions.present == LTE_SCGFailureInformationNR_r15__criticalExtensions_PR_c1){
+ if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
+ choice.c1.present == LTE_SCGFailureInformationNR_r15__criticalExtensions__c1_PR_scgFailureInformationNR_r15){
+ if (ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
+ choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15!=NULL) {
+ LOG_E(RRC, "Received NR scgFailureInformation from UE, failure type: %ld \n",
+ ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.scgFailureInformationNR_r15.criticalExtensions.
+ choice.c1.choice.scgFailureInformationNR_r15.failureReportSCG_NR_r15->failureType_r15);
+ xer_fprint(stdout, &asn_DEF_LTE_UL_DCCH_Message, (void *)ul_dcch_msg);
+ }
+ }
+ }
+ }
+ else if(ul_dcch_msg->message.choice.messageClassExtension.choice.c2.present == LTE_UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12){
+ //case UL_DCCH_MessageType__messageClassExtension__c2_PR_sidelinkUEInformation_r12: //SidelinkUEInformation
+ LOG_I(RRC,"THINH [LTE_UL_DCCH_MessageType__messageClassExtension_PR_c2]\n");
+ LOG_DUMPMSG(RRC,DEBUG_RRC,(char *)Rx_sdu,sdu_sizeP,
"[MSG] RRC SidelinkUEInformation \n");
- MSC_LOG_RX_MESSAGE(
- MSC_RRC_ENB,
- MSC_RRC_UE,
- Rx_sdu,
- sdu_sizeP,
- MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u",
- MSC_AS_TIME_ARGS(ctxt_pP),
- ue_context_p->ue_context.rnti,
- sdu_sizeP);
- LOG_I(RRC,
- PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes "
- "(SidelinkUEInformation) ---> RRC_eNB\n",
- PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
- DCCH,
+ MSC_LOG_RX_MESSAGE(
+ MSC_RRC_ENB,
+ MSC_RRC_UE,
+ Rx_sdu,
+ sdu_sizeP,
+ MSC_AS_TIME_FMT" SidelinkUEInformation UE %x size %u",
+ MSC_AS_TIME_ARGS(ctxt_pP),
+ ue_context_p->ue_context.rnti,
sdu_sizeP);
- rrc_eNB_process_SidelinkUEInformation(
- ctxt_pP,
- ue_context_p,
- &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12);
+ LOG_I(RRC,
+ PROTOCOL_RRC_CTXT_UE_FMT" RLC RB %02d --- RLC_DATA_IND %d bytes "
+ "(SidelinkUEInformation) ---> RRC_eNB\n",
+ PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
+ DCCH,
+ sdu_sizeP);
+ rrc_eNB_process_SidelinkUEInformation(
+ ctxt_pP,
+ ue_context_p,
+ &ul_dcch_msg->message.choice.messageClassExtension.choice.c2.choice.sidelinkUEInformation_r12);
+ }
break;
default:
@@ -8641,96 +9024,109 @@ void rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) {
}
void rrc_eNB_process_AdditionResponseInformation(const module_id_t enb_mod_idP, x2ap_ENDC_sgnb_addition_req_ACK_t *m) {
+ NR_CG_Config_t *CG_Config = NULL;
+ {
+ int i;
+ printf("%d: ", m->rrc_buffer_size);
+ for (i=0; i<m->rrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]);
- NR_CG_Config_t *CG_Config = NULL;
+ printf("\n");
+ }
+ asn_dec_rval_t dec_rval = uper_decode_complete( NULL,
+ &asn_DEF_NR_CG_Config,
+ (void **)&CG_Config,
+ (uint8_t *)m->rrc_buffer,
+ (int) m->rrc_buffer_size);//m->rrc_buffer_size);
- {
- int i;
- printf("%d: ", m->rrc_buffer_size);
- for (i=0; i<m->rrc_buffer_size; i++) printf("%2.2x", (unsigned char)m->rrc_buffer[i]);
- printf("\n");
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n");
+ // free the memory
+ SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 );
+ return;
+ }
- }
- asn_dec_rval_t dec_rval = uper_decode_complete( NULL,
- &asn_DEF_NR_CG_Config,
- (void **)&CG_Config,
- (uint8_t *)m->rrc_buffer,
- (int) m->rrc_buffer_size);//m->rrc_buffer_size);
+ xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config);
+ // recreate enough of X2 EN-DC Container
+ AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config,
+ "CG_Config not present\n");
+ OCTET_STRING_t *scg_CellGroupConfig = NULL;
+ OCTET_STRING_t *nr1_conf = NULL;
- if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
- AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n");
- // free the memory
- SEQUENCE_free( &asn_DEF_NR_CG_Config, CG_Config, 1 );
- return;
- }
- xer_fprint(stdout,&asn_DEF_NR_CG_Config, CG_Config);
- // recreate enough of X2 EN-DC Container
+ if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig) {
+ scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig;
+#ifdef DEBUG_SCG_CONFIG
+ {
+ int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size;
+ int i;
+ LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s);
- AssertFatal(CG_Config->criticalExtensions.choice.c1->present == NR_CG_Config__criticalExtensions__c1_PR_cg_Config,
- "CG_Config not present\n");
+ for (i=0; i<size_s; i++) printf("%2.2x", (unsigned char)CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]);
- OCTET_STRING_t *scg_CellGroupConfig = NULL;
- OCTET_STRING_t *nr1_conf = NULL;
+ printf("\n");
+ }
+#endif
+ } else {
+ LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n");
+ return;
+ }
- if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig){
- scg_CellGroupConfig = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig;
+ if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config) {
+ nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config;
#ifdef DEBUG_SCG_CONFIG
- {
- int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->size;
- int i;
- LOG_I(RRC, "Dumping scg_CellGroupConfig: %d", size_s);
- for (i=0; i<size_s; i++) printf("%2.2x", (unsigned char)CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig->buf[i]);
- printf("\n");
-
- }
-#endif
+ {
+ int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size;
+ int i;
+ LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s);
+ for (i=0; i<size_s; i++) printf("%2.2x", (unsigned char)CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]);
+
+ printf("\n");
}
- else{
- LOG_W(RRC, "SCG Cell group configuration is not present in the Addition Response message \n");
- return;
- }
- if(CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config){
- nr1_conf = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config;
-#ifdef DEBUG_SCG_CONFIG
- {
- int size_s = CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->size;
- int i;
- LOG_I(RRC, "Dumping scg_RB_Config: %d", size_s);
- for (i=0; i<size_s; i++) printf("%2.2x", (unsigned char)CG_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config->buf[i]);
- printf("\n");
-
- }
#endif
- }
- else{
- LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n");
- return;
- }
+ } else {
+ LOG_W(RRC, "SCG RB configuration is not present in the Addition Response message \n");
+ return;
+ }
- protocol_ctxt_t ctxt;
- rrc_eNB_ue_context_t *ue_context;
- unsigned char buffer[8192];
- int size;
+ protocol_ctxt_t ctxt;
+ rrc_eNB_ue_context_t *ue_context;
+ unsigned char buffer[8192];
+ int size;
+ ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti);
+ ue_context->ue_context.nb_of_modify_endc_e_rabs = m->nb_e_rabs_admitted_tobeadded;
+ int j=0;
+
+ while(j < m->nb_e_rabs_admitted_tobeadded) {
+ for (int e_rab_idx=0; e_rab_idx<ue_context->ue_context.setup_e_rabs; e_rab_idx++) {
+ //Update ue_context information with gNB's address and new GTP tunnel ID
+ if( ue_context->ue_context.e_rab[e_rab_idx].param.e_rab_id == m->e_rabs_admitted_tobeadded[j].e_rab_id) {
+ memcpy(ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].buffer,
+ m->e_rabs_admitted_tobeadded[j].gnb_addr.buffer,
+ m->e_rabs_admitted_tobeadded[j].gnb_addr.length);
+ ue_context->ue_context.gnb_gtp_endc_addrs[e_rab_idx].length = m->e_rabs_admitted_tobeadded[j].gnb_addr.length;
+ ue_context->ue_context.gnb_gtp_endc_teid[e_rab_idx] = m->e_rabs_admitted_tobeadded[j].gtp_teid;
+ ue_context->ue_context.e_rab[e_rab_idx].status = E_RAB_STATUS_TOMODIFY;
+ break;
+ }
+ }
- ue_context = rrc_eNB_get_ue_context(RC.rrc[enb_mod_idP], m->rnti);
+ j++;
+ }
- PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt,
- 0,
- ENB_FLAG_YES,
- m->rnti,
- 0, 0);
-
- size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf);
-
- rrc_data_req(&ctxt,
- DCCH,
- rrc_eNB_mui++,
- SDU_CONFIRM_NO,
- size,
- buffer,
- PDCP_TRANSMISSION_MODE_CONTROL);
+ PROTOCOL_CTXT_SET_BY_INSTANCE(&ctxt,
+ 0,
+ ENB_FLAG_YES,
+ m->rnti,
+ 0, 0);
+ size = rrc_eNB_generate_RRCConnectionReconfiguration_endc(&ctxt, ue_context, buffer, 8192, scg_CellGroupConfig, nr1_conf);
+ rrc_data_req(&ctxt,
+ DCCH,
+ rrc_eNB_mui++,
+ SDU_CONFIRM_NO,
+ size,
+ buffer,
+ PDCP_TRANSMISSION_MODE_CONTROL);
}
@@ -9013,11 +9409,10 @@ void *rrc_enb_process_itti_msg(void *notUsed) {
}
case X2AP_ENDC_SGNB_ADDITION_REQ_ACK: {
- rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p));
- break;
+ rrc_eNB_process_AdditionResponseInformation(ENB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg_p));
+ break;
}
-
/* Messages from eNB app */
case RRC_CONFIGURATION_REQ:
LOG_I(RRC, "[eNB %d] Received %s : %p\n", instance, msg_name_p, &RRC_CONFIGURATION_REQ(msg_p));
@@ -9037,36 +9432,36 @@ void *rrc_enb_process_itti_msg(void *notUsed) {
break;
case M2AP_SETUP_RESP:
- rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p));
+ rrc_eNB_process_M2AP_SETUP_RESP(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_SETUP_RESP(msg_p));
break;
case M2AP_MBMS_SCHEDULING_INFORMATION:
- rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p));
- break;
+ rrc_eNB_process_M2AP_MBMS_SCHEDULING_INFORMATION(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SCHEDULING_INFORMATION(msg_p));
+ break;
case M2AP_MBMS_SESSION_START_REQ:
- rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p));
- break;
+ rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(&ctxt,0/*CC_id*/,ENB_INSTANCE_TO_MODULE_ID(instance),&M2AP_MBMS_SESSION_START_REQ(msg_p));
+ break;
case M2AP_MBMS_SESSION_STOP_REQ:
- rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p));
- break;
+ rrc_eNB_process_M2AP_MBMS_SESSION_STOP_REQ(&ctxt,&M2AP_MBMS_SESSION_STOP_REQ(msg_p));
+ break;
case M2AP_RESET:
- rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p));
- break;
+ rrc_eNB_process_M2AP_RESET(&ctxt,&M2AP_RESET(msg_p));
+ break;
case M2AP_ENB_CONFIGURATION_UPDATE_ACK:
- rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p));
- break;
+ rrc_eNB_process_M2AP_ENB_CONFIGURATION_UPDATE_ACK(&ctxt,&M2AP_ENB_CONFIGURATION_UPDATE_ACK(msg_p));
+ break;
case M2AP_ERROR_INDICATION:
- rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p));
- break;
+ rrc_eNB_process_M2AP_ERROR_INDICATION(&ctxt,&M2AP_ERROR_INDICATION(msg_p));
+ break;
case M2AP_MBMS_SERVICE_COUNTING_REQ:
- rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p));
- break;
+ rrc_eNB_process_M2AP_MBMS_SERVICE_COUNTING_REQ(&ctxt,&M2AP_MBMS_SERVICE_COUNTING_REQ(msg_p));
+ break;
case M2AP_MCE_CONFIGURATION_UPDATE:
rrc_eNB_process_M2AP_MCE_CONFIGURATION_UPDATE(&ctxt,&M2AP_MCE_CONFIGURATION_UPDATE(msg_p));
@@ -9103,17 +9498,16 @@ rrc_enb_task(
//-----------------------------------------------------------------------------
{
rrc_enb_init();
-
itti_mark_task_ready(TASK_RRC_ENB);
LOG_I(RRC,"Entering main loop of RRC message task\n");
while (1) {
(void) rrc_enb_process_itti_msg(NULL);
-{
- //extern volatile int go_nr;
- void rrc_go_nr(void);
- //if (go_nr) rrc_go_nr();
-}
+ {
+ //extern volatile int go_nr;
+ void rrc_go_nr(void);
+ //if (go_nr) rrc_go_nr();
+ }
}
}
diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c
index 6bbdef181b4e2793e3c3898e6fc5ee4b5a9dbc8c..1025d46f62621f91ce6235702b068dddcc481754 100644
--- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.c
+++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.c
@@ -92,6 +92,7 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP(
}
}
+
//------------------------------------------------------------------------------
boolean_t
gtpv_data_req(
diff --git a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h
index 00c7490359031a138200ee8c59db35023dcd4957..6318ed4927cc051a1a3b3c2c70956fc22e85eeae 100644
--- a/openair2/RRC/LTE/rrc_eNB_GTPV1U.h
+++ b/openair2/RRC/LTE/rrc_eNB_GTPV1U.h
@@ -43,6 +43,13 @@ rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP(
uint8_t *inde_list
);
+int
+rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP(
+ const protocol_ctxt_t *const ctxt_pP,
+ const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP,
+ uint8_t *inde_list
+);
+
/*! \fn rrc_eNB_send_GTPV1U_ENB_DELETE_TUNNEL_REQ(module_id_t enb_mod_idP, const rrc_eNB_ue_context_t* const ue_context_pP)
*\brief Send GTPV1U_ENB_DELETE_TUNNEL_REQ message to GTPV1U to destroy all UE-related tunnels.
*\param module_id Instance ID of eNB.
diff --git a/openair2/RRC/LTE/rrc_eNB_M2AP.c b/openair2/RRC/LTE/rrc_eNB_M2AP.c
index bd586dfc71cf7f855f5fa6e1c30ee32def55e02c..98a72895a073a60f18424ccf29efb4b7454be57e 100644
--- a/openair2/RRC/LTE/rrc_eNB_M2AP.c
+++ b/openair2/RRC/LTE/rrc_eNB_M2AP.c
@@ -63,6 +63,71 @@ rrc_M2AP_openair_rrc_top_init_MBMS(int eMBMS_active){
}
+static uint8_t rrc_M2AP_do_MBSFNCountingRequest(
+ uint8_t Mod_id,
+ uint8_t sync_area,
+ uint8_t *buffer,
+ LTE_MCCH_Message_t *mcch_message,
+ LTE_MBMSCountingRequest_r10_t **mbsfnCoutingRequest,
+ const m2ap_mbms_service_counting_req_t *const m2ap_mbms_service_counting_req
+) {
+ //int i,j,k;
+
+ asn_enc_rval_t enc_rval;
+ //LTE_MBSFN_SubframeConfig_t *mbsfn_SubframeConfig1;
+ //LTE_PMCH_Info_r9_t *pmch_Info_1;
+ //LTE_MBMS_SessionInfo_r9_t *mbms_Session_1;
+ // MBMS_SessionInfo_r9_t *mbms_Session_2;
+ //eNB_RRC_INST *rrc = RC.rrc[Mod_id];
+ //rrc_eNB_carrier_data_t *carrier = &rrc->carrier[0];
+ memset(mcch_message,0,sizeof(LTE_MCCH_Message_t));
+ //mcch_message->message.present = LTE_MCCH_MessageType_PR_c1;
+ mcch_message->message.present = LTE_MCCH_MessageType_PR_later;
+ //mcch_message->message.choice.c1.present = LTE_MCCH_MessageType__c1_PR_mbsfnAreaConfiguration_r9;
+ mcch_message->message.choice.later.present = LTE_MCCH_MessageType__later_PR_c2;
+ mcch_message->message.choice.later.choice.c2.present = LTE_MCCH_MessageType__later__c2_PR_mbmsCountingRequest_r10;
+ *mbsfnCoutingRequest = &mcch_message->message.choice.later.choice.c2.choice.mbmsCountingRequest_r10;
+
+
+ //LTE_CountingRequestList_r10_t countingRequestList_r10; // A_SEQUENCE_OF(struct LTE_CountingRequestInfo_r10) list;
+ struct LTE_CountingRequestInfo_r10 *lte_counting_request_info; //LTE_TMGI_r9_t tmgi_r10;
+ lte_counting_request_info = CALLOC(1,sizeof(struct LTE_CountingRequestInfo_r10));
+ uint8_t TMGI[5] = {4,3,2,1,0};
+ lte_counting_request_info->tmgi_r10.plmn_Id_r9.present = LTE_TMGI_r9__plmn_Id_r9_PR_plmn_Index_r9;
+ lte_counting_request_info->tmgi_r10.plmn_Id_r9.choice.plmn_Index_r9= 1;
+ memset(<e_counting_request_info->tmgi_r10.serviceId_r9,0,sizeof(OCTET_STRING_t));
+ OCTET_STRING_fromBuf(<e_counting_request_info->tmgi_r10.serviceId_r9,(const char*)&TMGI[2],3);
+ ASN_SEQUENCE_ADD(&(*mbsfnCoutingRequest)->countingRequestList_r10.list,lte_counting_request_info);
+
+ if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
+ xer_fprint(stdout,&asn_DEF_LTE_MCCH_Message,(void *)mcch_message);
+ }
+
+ xer_fprint(stdout,&asn_DEF_LTE_MCCH_Message,(void *)mcch_message);
+
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_MCCH_Message,
+ NULL,
+ (void *)mcch_message,
+ buffer,
+ 100);
+
+ if(enc_rval.encoded == -1) {
+ LOG_I(RRC, "[eNB AssertFatal]ASN1 message encoding failed (%s, %lu)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+ return -1;
+ }
+
+ LOG_I(RRC,"[eNB] MCCH Message Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8);
+
+ if (enc_rval.encoded==-1) {
+ msg("[RRC] ASN1 : MCCH encoding failed for MBSFNAreaConfiguration\n");
+ return(-1);
+ }
+
+ return((enc_rval.encoded+7)/8);
+
+}
+
static uint8_t rrc_M2AP_do_MBSFNAreaConfig(
uint8_t Mod_id,
@@ -96,6 +161,7 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig(
mbsfn_SubframeConfig1->radioframeAllocationPeriod= m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_period;//LTE_MBSFN_SubframeConfig__radioframeAllocationPeriod_n4;
mbsfn_SubframeConfig1->radioframeAllocationOffset= m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].radioframe_allocation_offset;
if(m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].is_four_sf){
+ LOG_I(RRC,"is_four_sf\n");
mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames;
mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3);
mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[i].mbms_sf_config_list[j].subframe_allocation) & 0xFF);
@@ -106,6 +172,7 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig(
}else {
+ LOG_I(RRC,"is_one_sf\n");
mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame;
mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1);
mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1;
@@ -128,7 +195,8 @@ static uint8_t rrc_M2AP_do_MBSFNAreaConfig(
*/
pmch_Info_1->pmch_Config_r9.sf_AllocEnd_r9= m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].allocated_sf_end;
pmch_Info_1->pmch_Config_r9.dataMCS_r9= m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].data_mcs;
- pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9= LTE_PMCH_Config_r9__mch_SchedulingPeriod_r9_rf16;
+ //pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9= LTE_PMCH_Config_r9__mch_SchedulingPeriod_r9_rf16;
+ pmch_Info_1->pmch_Config_r9.mch_SchedulingPeriod_r9 = m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].mch_scheduling_period;
// MBMSs-SessionInfoList-r9
for(k=0; k < m2ap_mbms_scheduling_information->mbms_area_config_list[i].pmch_config_list[j].num_mbms_session_list; k++){
// pmch_Info_1->mbms_SessionInfoList_r9 = CALLOC(1,sizeof(struct MBMS_SessionInfoList_r9));
@@ -240,6 +308,9 @@ static void rrc_M2AP_init_MCCH(
RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE =
malloc(RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area * sizeof(uint8_t *));
+
+ RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING =
+ malloc(RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area * sizeof(uint8_t *));
for (sync_area = 0; sync_area < RC.rrc[enb_mod_idP]->carrier[CC_id].num_mbsfn_sync_area; sync_area++) {
RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] = 0;
@@ -253,6 +324,20 @@ static void rrc_M2AP_init_MCCH(
&RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message,
m2ap_mbms_scheduling_information
);
+
+ RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[sync_area] = 0;
+ RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area] = (uint8_t *) malloc16(32);
+ AssertFatal(RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area] != NULL,
+ "[eNB %d]init_MCCH: FATAL, no memory for MCCH MESSAGE allocated \n", enb_mod_idP);
+
+ RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE_COUNTING[sync_area] = rrc_M2AP_do_MBSFNCountingRequest(enb_mod_idP,
+ sync_area,
+ (uint8_t *)RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE_COUNTING[sync_area],
+ &RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_counting,
+ &RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message_counting,
+ NULL//m2ap_mbms_scheduling_information
+ );
+
LOG_I(RRC, "mcch message pointer %p for sync area %d \n",
RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESSAGE[sync_area],
sync_area);
@@ -269,6 +354,8 @@ static void rrc_M2AP_init_MCCH(
AssertFatal(RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] != 255,
"RC.rrc[enb_mod_idP]->carrier[CC_id].sizeof_MCCH_MESSAGE[sync_area] == 255");
RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESS[sync_area].Active = 1;
+
+ RC.rrc[enb_mod_idP]->carrier[CC_id].MCCH_MESS_COUNTING[sync_area].Active = 1;
}
@@ -297,16 +384,347 @@ static void rrc_M2AP_init_MCCH(
(LTE_MBSFN_AreaInfoList_r9_t *) NULL,
(LTE_PMCH_InfoList_r9_t *) & (RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message->pmch_InfoList_r9),
(LTE_SystemInformationBlockType1_v1310_IEs_t *)NULL,
- 0,
+ 0,
+ (LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL,
+ (LTE_SchedulingInfo_MBMS_r14_t *) NULL,
+ (struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
+ (LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*)(RC.rrc[enb_mod_idP]->carrier[CC_id].mcch_message)
+ );
+ }
+
+ return;
+}
+
+
+static uint8_t rrc_M2AP_do_SIB1_MBMS_SIB13(
+ const protocol_ctxt_t *const ctxt_pP,
+ uint8_t Mod_id,
+ int CC_id,
+ const m2ap_setup_resp_t *const m2ap_setup_resp,
+ const m2ap_mbms_scheduling_information_t *const m2ap_mbms_scheduling_information
+){
+
+ int i,j,l;
+
+ eNB_RRC_INST *rrc = RC.rrc[ctxt_pP->module_id];
+ rrc_eNB_carrier_data_t *carrier=&rrc->carrier[CC_id];
+
+
+ struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member *sib13_part=NULL;
+ LTE_MBSFN_SubframeConfigList_t *MBSFNSubframeConfigList/*,*MBSFNSubframeConfigList_copy*/;
+
+ asn_enc_rval_t enc_rval;
+
+ LTE_BCCH_DL_SCH_Message_t *bcch_message = &RC.rrc[Mod_id]->carrier[CC_id].systemInformation;
+ LTE_BCCH_DL_SCH_Message_MBMS_t *bcch_message_fembms = &RC.rrc[Mod_id]->carrier[CC_id].siblock1_MBMS;
+ uint8_t *buffer;
+ uint8_t *buffer_fembms;
+ LTE_SystemInformationBlockType2_t **sib2;
+
+
+ LTE_MBSFN_AreaInfoList_r9_t *MBSFNArea_list/*,*MBSFNArea_list_copy*/;
+ LTE_SystemInformationBlockType13_r9_t **sib13 = &RC.rrc[Mod_id]->carrier[CC_id].sib13;
+ struct LTE_MBSFN_AreaInfo_r9 *MBSFN_Area1;
+
+ LTE_SystemInformationBlockType1_MBMS_r14_t **sib1_MBMS = &RC.rrc[Mod_id]->carrier[CC_id].sib1_MBMS;
+
+
+
+ if(ctxt_pP->brOption){
+ buffer = RC.rrc[Mod_id]->carrier[CC_id].SIB23_BR;
+ sib2 = &RC.rrc[Mod_id]->carrier[CC_id].sib2_BR;
+ LOG_I(RRC,"Running SIB2/3 Encoding for eMTC\n");
+
+
+ }else
+ {
+ buffer = RC.rrc[Mod_id]->carrier[CC_id].SIB23;
+ sib2 = &RC.rrc[Mod_id]->carrier[CC_id].sib2;
+ }
+
+ buffer_fembms = RC.rrc[Mod_id]->carrier[CC_id].SIB1_MBMS;
+
+
+ if (bcch_message) {
+ //memset(bcch_message,0,sizeof(LTE_BCCH_DL_SCH_Message_t));
+ } else {
+ LOG_E(RRC,"[eNB %d] BCCH_MESSAGE is null, exiting\n", Mod_id);
+ exit(-1);
+ }
+
+ if (!sib2) {
+ LOG_E(RRC,"[eNB %d] sib2 is null, exiting\n", Mod_id);
+ exit(-1);
+ }
+
+ if(!sib13){
+ LOG_I(RRC,"[eNB %d] sib13 is null, it should get created\n",Mod_id);
+ }
+
+
+ if(!sib1_MBMS){
+ LOG_I(RRC,"[eNB %d] sib1_MBMS is null, it should get created\n",Mod_id);
+ }
+
+ //if (!sib3) {
+ // LOG_E(RRC,"[eNB %d] sib3 is null, exiting\n", Mod_id);
+ // exit(-1);
+ //}
+
+ for (i=0; i < bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list.count; i++) {
+ struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member *typeandinfo;
+ typeandinfo = bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list.array[i];
+ switch(typeandinfo->present) {
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_NOTHING:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib3:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib4:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib5:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib6:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib7:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib8:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib9:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib10:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib11:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib12_v920:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib13_v920:
+ *sib13=&typeandinfo->choice.sib13_v920;
+ (*sib13)->notificationConfig_r9.notificationRepetitionCoeff_r9=LTE_MBMS_NotificationConfig_r9__notificationRepetitionCoeff_r9_n2;
+ (*sib13)->notificationConfig_r9.notificationOffset_r9=0;
+ (*sib13)->notificationConfig_r9.notificationSF_Index_r9=1;
+ // MBSFN-AreaInfoList
+ MBSFNArea_list= &(*sib13)->mbsfn_AreaInfoList_r9;//CALLOC(1,sizeof(*MBSFNArea_list));
+ memset(MBSFNArea_list,0,sizeof(*MBSFNArea_list));
+
+ for( j=0; j < m2ap_setup_resp->num_mcch_config_per_mbsfn; j++){
+ // MBSFN Area 1
+ MBSFN_Area1= CALLOC(1, sizeof(*MBSFN_Area1));
+ MBSFN_Area1->mbsfn_AreaId_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].mbsfn_area;
+ MBSFN_Area1->non_MBSFNregionLength= m2ap_setup_resp->mcch_config_per_mbsfn[j].pdcch_length;
+ MBSFN_Area1->notificationIndicator_r9= 0;
+ MBSFN_Area1->mcch_Config_r9.mcch_RepetitionPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].repetition_period;//LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__mcch_RepetitionPeriod_r9_rf32;
+ MBSFN_Area1->mcch_Config_r9.mcch_Offset_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].offset; // in accordance with mbsfn subframe configuration in sib2
+ MBSFN_Area1->mcch_Config_r9.mcch_ModificationPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].modification_period;
+
+ // Subframe Allocation Info
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf= MALLOC(1);
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1;
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=m2ap_setup_resp->mcch_config_per_mbsfn[j].subframe_allocation_info<<2; // FDD: SF1
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2;
+ MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= m2ap_setup_resp->mcch_config_per_mbsfn[j].mcs;
+ ASN_SEQUENCE_ADD(&MBSFNArea_list->list,MBSFN_Area1);
+ }
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib14_v1130:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib15_v1130:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib16_v1130:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib17_v1250:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib18_v1250:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib19_v1250:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib20_v1310:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib21_v1430:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib24_v1530:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib25_v1530:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib26_v1530:
+ break;
+ case LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib2:
+
+ LOG_I(RRC,"Adding MBSFN subframe Configuration 1 to SIB2, %p %p\n",&typeandinfo->choice.sib2,*sib2);
+
+ for(j=0; j < m2ap_mbms_scheduling_information->num_mbms_area_config_list ; j++) {
+
+ (&typeandinfo->choice.sib2)->mbsfn_SubframeConfigList = CALLOC(1,sizeof(struct LTE_MBSFN_SubframeConfigList));
+ MBSFNSubframeConfigList = (&typeandinfo->choice.sib2)->mbsfn_SubframeConfigList;
+
+ for(l=0; l < m2ap_mbms_scheduling_information->mbms_area_config_list[j].num_mbms_sf_config_list; l++){
+ LTE_MBSFN_SubframeConfig_t *sib2_mbsfn_SubframeConfig1;
+ sib2_mbsfn_SubframeConfig1= CALLOC(1,sizeof(*sib2_mbsfn_SubframeConfig1));
+ memset((void *)sib2_mbsfn_SubframeConfig1,0,sizeof(*sib2_mbsfn_SubframeConfig1));
+
+ sib2_mbsfn_SubframeConfig1->radioframeAllocationPeriod = m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].radioframe_allocation_period;
+ sib2_mbsfn_SubframeConfig1->radioframeAllocationOffset = m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].radioframe_allocation_offset;
+
+
+ if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){
+ LOG_I(RRC,"is_four_sf\n");
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames;
+
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3;
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0;
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF);
+
+ }else{
+ LOG_I(RRC,"is_one_sf\n");
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame;
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1;
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2;
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2);
+
+
+ }
+
+ ASN_SEQUENCE_ADD(&MBSFNSubframeConfigList->list,sib2_mbsfn_SubframeConfig1);
+ }
+ }
+
+ break;
+
+ }
+ }
+
+
+ if(*sib13==NULL){
+ sib13_part = CALLOC(1,sizeof(struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member));
+ memset(sib13_part,0,sizeof(struct LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member));
+ sib13_part->present = LTE_SystemInformation_r8_IEs__sib_TypeAndInfo__Member_PR_sib13_v920;
+
+ *sib13 = &sib13_part->choice.sib13_v920;
+
+ (*sib13)->notificationConfig_r9.notificationRepetitionCoeff_r9=LTE_MBMS_NotificationConfig_r9__notificationRepetitionCoeff_r9_n2;
+ (*sib13)->notificationConfig_r9.notificationOffset_r9=0;
+ (*sib13)->notificationConfig_r9.notificationSF_Index_r9=1;
+
+ // MBSFN-AreaInfoList
+ MBSFNArea_list= &(*sib13)->mbsfn_AreaInfoList_r9;//CALLOC(1,sizeof(*MBSFNArea_list));
+ memset(MBSFNArea_list,0,sizeof(*MBSFNArea_list));
+
+ for( i=0; i < m2ap_setup_resp->num_mcch_config_per_mbsfn; i++){
+ // MBSFN Area 1
+ MBSFN_Area1= CALLOC(1, sizeof(*MBSFN_Area1));
+ MBSFN_Area1->mbsfn_AreaId_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].mbsfn_area;
+ MBSFN_Area1->non_MBSFNregionLength= m2ap_setup_resp->mcch_config_per_mbsfn[i].pdcch_length;
+ MBSFN_Area1->notificationIndicator_r9= 0;
+ MBSFN_Area1->mcch_Config_r9.mcch_RepetitionPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].repetition_period;//LTE_MBSFN_AreaInfo_r9__mcch_Config_r9__mcch_RepetitionPeriod_r9_rf32;
+ MBSFN_Area1->mcch_Config_r9.mcch_Offset_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].offset; // in accordance with mbsfn subframe configuration in sib2
+ MBSFN_Area1->mcch_Config_r9.mcch_ModificationPeriod_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].modification_period;
+
+ // Subframe Allocation Info
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf= MALLOC(1);
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.size= 1;
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.buf[0]=m2ap_setup_resp->mcch_config_per_mbsfn[i].subframe_allocation_info<<2; // FDD: SF1
+ MBSFN_Area1->mcch_Config_r9.sf_AllocInfo_r9.bits_unused= 2;
+ MBSFN_Area1->mcch_Config_r9.signallingMCS_r9= m2ap_setup_resp->mcch_config_per_mbsfn[i].mcs;
+ ASN_SEQUENCE_ADD(&MBSFNArea_list->list,MBSFN_Area1);
+ }
+
+ ASN_SEQUENCE_ADD(&bcch_message->message.choice.c1.choice.systemInformation.criticalExtensions.choice.systemInformation_r8.sib_TypeAndInfo.list, sib13_part);
+
+ }
+
+ *sib1_MBMS = &bcch_message_fembms->message.choice.c1.choice.systemInformationBlockType1_MBMS_r14;
+
+
+ if((*sib1_MBMS)->systemInformationBlockType13_r14==NULL){
+ (*sib1_MBMS)->systemInformationBlockType13_r14 = CALLOC(1,sizeof(struct LTE_SystemInformationBlockType13_r9));
+ memset((*sib1_MBMS)->systemInformationBlockType13_r14,0,sizeof(struct LTE_SystemInformationBlockType13_r9));
+ }
+
+
+ memcpy((*sib1_MBMS)->systemInformationBlockType13_r14,*sib13,sizeof(struct LTE_SystemInformationBlockType13_r9));
+
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message_MBMS,
+ NULL,
+ (void *)bcch_message_fembms,
+ buffer_fembms,
+ 100);
+ AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+
+ LOG_I(RRC,"[eNB] MBMS SIB1_MBMS SystemInformation Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8);
+
+ if (enc_rval.encoded==-1) {
+ msg("[RRC] ASN1 : SI encoding failed for SIB23\n");
+ return(-1);
+ }
+
+
+
+ //xer_fprint(stdout, &asn_DEF_LTE_BCCH_DL_SCH_Message, (void *)bcch_message);
+
+ enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_BCCH_DL_SCH_Message,
+ NULL,
+ (void *)bcch_message,
+ buffer,
+ 900);
+ AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %lu)!\n",
+ enc_rval.failed_type->name, enc_rval.encoded);
+
+ LOG_I(RRC,"[eNB] MBMS SIB2 SystemInformation Encoded %zd bits (%zd bytes)\n",enc_rval.encoded,(enc_rval.encoded+7)/8);
+
+ if (enc_rval.encoded==-1) {
+ msg("[RRC] ASN1 : SI encoding failed for SIB23\n");
+ return(-1);
+ }
+
+ carrier->MBMS_flag =1;
+
+ if (NODE_IS_MONOLITHIC(rrc->node_type)) {
+ rrc_mac_config_req_eNB(ctxt_pP->module_id, CC_id,
+ 0,0,0,0,0,
+ 0,
+ 0xfffd,//rnti
+ (LTE_BCCH_BCH_Message_t *)NULL,
+ (LTE_RadioResourceConfigCommonSIB_t *) NULL,
+ (LTE_RadioResourceConfigCommonSIB_t *) NULL,
+ (struct LTE_PhysicalConfigDedicated *)NULL,
+ (LTE_SCellToAddMod_r10_t *)NULL,
+ //(struct LTE_PhysicalConfigDedicatedSCell_r10 *)NULL,
+ (LTE_MeasObjectToAddMod_t **) NULL,
+ (LTE_MAC_MainConfig_t *) NULL,
+ 0,
+ (struct LTE_LogicalChannelConfig *)NULL,
+ (LTE_MeasGapConfig_t *) NULL,
+ (LTE_TDD_Config_t *) NULL,
+ (LTE_MobilityControlInfo_t *)NULL,
+ (LTE_SchedulingInfoList_t *) NULL,
+ 0, NULL,
+ (LTE_AdditionalSpectrumEmission_t *)NULL,
+ (LTE_MBSFN_SubframeConfigList_t *) carrier->sib2->mbsfn_SubframeConfigList,
+ carrier->MBMS_flag,
+ (LTE_MBSFN_AreaInfoList_r9_t *) & carrier->sib13->mbsfn_AreaInfoList_r9,
+ (LTE_PMCH_InfoList_r9_t *) NULL
+ ,
+ (LTE_SystemInformationBlockType1_v1310_IEs_t *)NULL
+ ,
+ carrier->FeMBMS_flag,
(LTE_BCCH_DL_SCH_Message_MBMS_t *) NULL,
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
-
- return;
+
+ RC.rrc[ctxt_pP->module_id]->carrier[CC_id].sizeof_SIB23 = ((enc_rval.encoded+7)/8);
+
+ return 0;
}
//static uint8_t rrc_M2AP_do_SIB1(
// const protocol_ctxt_t *const ctxt_pP,
@@ -501,21 +919,23 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2(
if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){
+ LOG_I(RRC,"is_four_sf\n");
sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0;
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation) & 0xFF);
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation>>8) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF);
}else{
+ LOG_I(RRC,"is_one_sf\n");
sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2;
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation<<2);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2);
}
@@ -580,7 +1000,8 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
@@ -752,7 +1173,8 @@ for( i=0; i < m2ap_setup_resp->num_mcch_config_per_mbsfn; i++){
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
@@ -917,20 +1339,22 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2_SIB13(
if(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].is_four_sf){
sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_fourFrames;
+ LOG_I(RRC,"rrc_M2AP_do_SIB23_SIB2_SIB13 is_four_sf\n");
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(3);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 3;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 0;
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation) & 0xFF);
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation>>8) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[2] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation) & 0xFF);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[1] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>8) & 0xFF);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0] = ((m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation>>16) & 0xFF);
}else{
+ LOG_I(RRC,"rrc_M2AP_do_SIB23_SIB2_SIB13 rs_one_sf\n");
sib2_mbsfn_SubframeConfig1->subframeAllocation.present= LTE_MBSFN_SubframeConfig__subframeAllocation_PR_oneFrame;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf= MALLOC(1);
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.size= 1;
sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.bits_unused= 2;
- sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[j].subframe_allocation<<2);
+ sib2_mbsfn_SubframeConfig1->subframeAllocation.choice.oneFrame.buf[0]=(m2ap_mbms_scheduling_information->mbms_area_config_list[j].mbms_sf_config_list[l].subframe_allocation<<2);
}
@@ -1030,7 +1454,8 @@ static uint8_t rrc_M2AP_do_SIB23_SIB2_SIB13(
(LTE_SchedulingInfo_MBMS_r14_t *) NULL,
(struct LTE_NonMBSFN_SubframeConfig_r14 *) NULL,
(LTE_SystemInformationBlockType1_MBMS_r14_t *) NULL,
- (LTE_MBSFN_AreaInfoList_r9_t *) NULL
+ (LTE_MBSFN_AreaInfoList_r9_t *) NULL,
+ (LTE_MBSFNAreaConfiguration_r9_t*) NULL
);
}
@@ -1122,7 +1547,11 @@ rrc_eNB_process_M2AP_MBMS_SESSION_START_REQ(
rrc_M2AP_do_SIB23_SIB2(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_mbms_scheduling_information_g);
rrc_M2AP_do_SIB23_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g);
}else{
- rrc_M2AP_do_SIB23_SIB2_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g);
+ if(RC.rrc[ctxt_pP->module_id]->carrier[CC_id].FeMBMS_flag){
+ rrc_M2AP_do_SIB1_MBMS_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g);
+ }else{
+ rrc_M2AP_do_SIB23_SIB2_SIB13(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_setup_resp_g,m2ap_mbms_scheduling_information_g);
+ }
}
rrc_M2AP_init_MCCH(ctxt_pP,ctxt_pP->module_id,CC_id,m2ap_mbms_scheduling_information_g);
rrc_M2AP_init_MBMS(ctxt_pP->module_id, CC_id, 0);
diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.c b/openair2/RRC/LTE/rrc_eNB_S1AP.c
index 59998cebcce88304bc42e664abdd5c90dea0295e..9f92be366bdb4c82279364755a96c709ac81bfcf 100644
--- a/openair2/RRC/LTE/rrc_eNB_S1AP.c
+++ b/openair2/RRC/LTE/rrc_eNB_S1AP.c
@@ -96,36 +96,34 @@ void extract_imsi(uint8_t *pdu_buf, uint32_t pdu_len, rrc_eNB_ue_context_t *ue_c
&& pdu_len > NAS_MESSAGE_SECURITY_HEADER_SIZE))
return;
+ /* Decode plain NAS message */
+ EMM_msg *e_msg = &nas_msg.plain.emm;
+ emm_msg_header_t *emm_header = &e_msg->header;
+
if (header->security_header_type != SECURITY_HEADER_TYPE_NOT_PROTECTED) {
/* Decode the message authentication code */
DECODE_U32((char *) pdu_buf+size, header->message_authentication_code, size);
/* Decode the sequence number */
DECODE_U8((char *) pdu_buf+size, header->sequence_number, size);
- }
+ /* Decode the security header type and the protocol discriminator */
+ DECODE_U8(pdu_buf + size, *(uint8_t *)(emm_header), size);
- /* Note: the value of the pointer (i.e. the address) is given by value, so we
- * can modify it as we want. The callee retains the original address! */
+ /* Check that this is the right message */
+ if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE)
+ return;
+ }
pdu_buf += size;
pdu_len -= size;
- /* Decode plain NAS message */
- EMM_msg *e_msg = &nas_msg.plain.emm;
- emm_msg_header_t *emm_header = &e_msg->header;
- /* First decode the EMM message header */
- int e_head_size = 0;
/* Check that buffer contains more than only the header */
if (pdu_len <= sizeof(emm_msg_header_t))
return;
- /* Decode the security header type and the protocol discriminator */
- DECODE_U8(pdu_buf + e_head_size, *(uint8_t *)(emm_header), e_head_size);
+ /* First decode the EMM message header */
+ int e_head_size = 0;
/* Decode the message type */
DECODE_U8(pdu_buf + e_head_size, emm_header->message_type, e_head_size);
- /* Check that this is the right message */
- if (emm_header->protocol_discriminator != EPS_MOBILITY_MANAGEMENT_MESSAGE)
- return;
-
pdu_buf += e_head_size;
pdu_len -= e_head_size;
@@ -2284,3 +2282,75 @@ int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id)
}*/
return 0;
}
+
+
+int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP,
+ rrc_eNB_ue_context_t *const ue_context_pP) {
+ MessageDef *msg_p = NULL;
+ int e_rab = 0;
+ int e_rab_modify_index = 0;
+ int e_rab_notmodify_index = 0;
+
+ uint8_t inde_list[ue_context_pP->ue_context.nb_of_e_rabs];
+ memset(inde_list, 0, ue_context_pP->ue_context.nb_of_e_rabs*sizeof(uint8_t));
+
+ msg_p = itti_alloc_new_message (TASK_RRC_ENB, S1AP_E_RAB_MODIFICATION_IND);
+
+
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id = ue_context_pP->ue_context.eNB_ue_s1ap_id;
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).mme_ue_s1ap_id = ue_context_pP->ue_context.mme_ue_s1ap_id;
+
+ LOG_I (RRC,"E-RAB modification indication: nb nb_of_e_rabs %u status %u\n",
+ ue_context_pP->ue_context.nb_of_e_rabs,
+ ue_context_pP->ue_context.e_rab[e_rab].status);
+
+ if (ue_context_pP->ue_context.nb_of_modify_endc_e_rabs > 0){
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified = ue_context_pP->ue_context.nb_of_modify_endc_e_rabs;
+ for (e_rab = 0; e_rab < ue_context_pP->ue_context.setup_e_rabs ; e_rab++) {
+ //Add E-RAB in the list of E-RABs to be modified
+ if (ue_context_pP->ue_context.e_rab[e_rab].status == E_RAB_STATUS_TOMODIFY) {
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id;
+ memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.buffer,
+ ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer,
+ ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length);
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length;
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_tobemodified[e_rab_modify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab];
+ e_rab_modify_index++;
+ }
+ //Add E-RAB in the list of E-RABs NOT to be modified
+ else{
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].e_rab_id = ue_context_pP->ue_context.e_rab[e_rab].param.e_rab_id;
+ memcpy(S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.buffer,
+ ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].buffer,
+ ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length);
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].eNB_addr.length = ue_context_pP->ue_context.gnb_gtp_endc_addrs[e_rab].length;
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).e_rabs_nottobemodified[e_rab_notmodify_index].gtp_teid = ue_context_pP->ue_context.gnb_gtp_endc_teid[e_rab];
+ e_rab_notmodify_index++;
+ }
+ }
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_nottobemodified = e_rab_notmodify_index;
+ }
+
+ if (e_rab_modify_index > 0) {
+ LOG_I(RRC,"S1AP_E_RAB_MODIFICATION_IND: sending the message: nb_of_erabstobemodified %d, total e_rabs %d, index %d\n",
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).nb_of_e_rabs_tobemodified, ue_context_pP->ue_context.setup_e_rabs, e_rab);
+ MSC_LOG_TX_MESSAGE(
+ MSC_RRC_ENB,
+ MSC_S1AP_ENB,
+ (const char *)&S1AP_E_RAB_MODIFICATION_IND (msg_p),
+ sizeof(s1ap_e_rab_modification_ind_t),
+ MSC_AS_TIME_FMT" E RAB MODIFICATION IND UE %X eNB_ue_s1ap_id %u e_rabs:%u succ",
+ MSC_AS_TIME_ARGS(ctxt_pP),
+ ue_context_pP->ue_id_rnti,
+ S1AP_E_RAB_MODIFICATION_IND (msg_p).eNB_ue_s1ap_id,
+ e_rab_modify_index);
+ itti_send_msg_to_task (TASK_S1AP, ctxt_pP->instance, msg_p);
+ } else {
+ itti_free(ITTI_MSG_ORIGIN_ID(msg_p), msg_p);
+ }
+
+ return 0;
+}
+
+
+
diff --git a/openair2/RRC/LTE/rrc_eNB_S1AP.h b/openair2/RRC/LTE/rrc_eNB_S1AP.h
index e5ff9c27d600d6371132e3f33782caeb4a3a96eb..a55d17bfd1ce0cfa13f5a88dbed182aff98d3426 100644
--- a/openair2/RRC/LTE/rrc_eNB_S1AP.h
+++ b/openair2/RRC/LTE/rrc_eNB_S1AP.h
@@ -285,4 +285,6 @@ int rrc_eNB_send_X2AP_UE_CONTEXT_RELEASE(const protocol_ctxt_t* const ctxt_pP, r
int s1ap_ue_context_release(instance_t instance, const uint32_t eNB_ue_s1ap_id);
+int rrc_eNB_send_E_RAB_Modification_Indication(const protocol_ctxt_t *const ctxt_pP, rrc_eNB_ue_context_t *const ue_context_pP);
+
#endif /* RRC_ENB_S1AP_H_ */
diff --git a/openair2/RRC/LTE/rrc_eNB_UE_context.h b/openair2/RRC/LTE/rrc_eNB_UE_context.h
index 289b4d69d69275e75659a819a17b57d85fb2861c..e22f517d50193fff9f6ed55c9c8cb063578de222 100644
--- a/openair2/RRC/LTE/rrc_eNB_UE_context.h
+++ b/openair2/RRC/LTE/rrc_eNB_UE_context.h
@@ -28,6 +28,8 @@
* \email: lionel.gauthier@eurecom.fr
*/
#ifndef __RRC_ENB_UE_CONTEXT_H__
+#define __RRC_ENB_UE_CONTEXT_H__
+
#include "collection/tree.h"
#include "COMMON/platform_types.h"
#include "rrc_defs.h"
diff --git a/openair2/RRC/NR/L2_nr_interface.c b/openair2/RRC/NR/L2_nr_interface.c
index 1e8e45ef4d535bbd3a6b50c30f075454b7e80b67..0905f6d7de2ee3d71f271d5c3f081707d9dbb48d 100644
--- a/openair2/RRC/NR/L2_nr_interface.c
+++ b/openair2/RRC/NR/L2_nr_interface.c
@@ -51,9 +51,8 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP,
uint8_t *const buffer_pP ){
asn_enc_rval_t enc_rval;
- //SRB_INFO *Srb_info;
- //uint8_t Sdu_size = 0;
- uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f);
+ uint8_t Sdu_size = 0;
+ uint8_t sfn_msb = (uint8_t)((frameP>>4)&0x3f);
#ifdef DEBUG_RRC
LOG_D(RRC,"[eNB %d] mac_rrc_data_req to SRB ID=%ld\n",Mod_idP,Srb_id);
@@ -62,11 +61,15 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP,
gNB_RRC_INST *rrc;
rrc_gNB_carrier_data_t *carrier;
NR_BCCH_BCH_Message_t *mib;
+ NR_SRB_INFO * srb_info;
+ char payload_size, *payload_pP;
rrc = RC.nrrrc[Mod_idP];
carrier = &rrc->carrier;
mib = &carrier->mib;
+ srb_info = &carrier->Srb0;
+ /* MIBCH */
if( (Srb_id & RAB_OFFSET ) == MIBCH) {
mib->message.choice.mib->systemFrameNumber.buf[0] = sfn_msb << 2;
enc_rval = uper_encode_to_buffer(&asn_DEF_NR_BCCH_BCH_Message,
@@ -84,10 +87,31 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP,
return(3);
}
-//BCCH SIB1 SIBs
+ /* TODO BCCH SIB1 SIBs */
-//CCCH
+ /* CCCH */
+ if( (Srb_id & RAB_OFFSET ) == CCCH) {
+ //struct rrc_eNB_ue_context_s *ue_context_p = rrc_eNB_get_ue_context(RC.rrc[Mod_idP],rnti);
+ //if (ue_context_p == NULL) return(0);
+ //eNB_RRC_UE_t *ue_p = &ue_context_p->ue_context;
+ LOG_D(RRC,"[gNB %d] Frame %d CCCH request (Srb_id %ld)\n", Mod_idP, frameP, Srb_id);
+
+ // srb_info=&ue_p->Srb0;
+
+ payload_size = srb_info->Tx_buffer.payload_size;
+
+ // check if data is there for MAC
+ if (payload_size > 0) {
+ payload_pP = srb_info->Tx_buffer.Payload;
+ LOG_D(RRC,"[gNB %d] CCCH (%p) has %d bytes (dest: %p, src %p)\n", Mod_idP, srb_info, payload_size, buffer_pP, payload_pP);
+ // Fill buffer
+ memcpy((void *)buffer_pP, (void*)payload_pP, payload_size);
+ Sdu_size = payload_size;
+ srb_info->Tx_buffer.payload_size = 0;
+ }
+ return Sdu_size;
+ }
return(0);
-}
+}
\ No newline at end of file
diff --git a/openair2/RRC/NR/nr_rrc_defs.h b/openair2/RRC/NR/nr_rrc_defs.h
index 02b4154c41afe4ec2ee6143a055e3da638a0c440..eeb16c308742cea66728b32bfad2bf30ad4ae3d6 100644
--- a/openair2/RRC/NR/nr_rrc_defs.h
+++ b/openair2/RRC/NR/nr_rrc_defs.h
@@ -319,9 +319,10 @@ typedef struct gNB_RRC_UE_s {
uint8_t nb_release_of_e_rabs;
e_rab_failed_t e_rabs_release_failed[S1AP_MAX_E_RAB];
// LG: For GTPV1 TUNNELS
- uint32_t enb_gtp_teid[S1AP_MAX_E_RAB];
- transport_layer_addr_t enb_gtp_addrs[S1AP_MAX_E_RAB];
- rb_id_t enb_gtp_ebi[S1AP_MAX_E_RAB];
+ uint32_t gnb_gtp_teid[S1AP_MAX_E_RAB];
+ transport_layer_addr_t gnb_gtp_addrs[S1AP_MAX_E_RAB];
+ rb_id_t gnb_gtp_ebi[S1AP_MAX_E_RAB];
+
uint32_t ul_failure_timer;
uint32_t ue_release_timer;
uint32_t ue_release_timer_thres;
diff --git a/openair2/RRC/NR/nr_rrc_proto.h b/openair2/RRC/NR/nr_rrc_proto.h
index 5770b80595efd95d2098d5ca10cf9ad2bbc501fc..317282c81484c6133621660de4f8a2b2d6d7b98d 100644
--- a/openair2/RRC/NR/nr_rrc_proto.h
+++ b/openair2/RRC/NR/nr_rrc_proto.h
@@ -65,9 +65,9 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge(
struct rrc_gNB_ue_context_s *rrc_gNB_allocate_new_UE_context(gNB_RRC_INST *rrc_instance_pP);
-void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList);
+void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t * cg_config_info);
-void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p);
+void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m);
void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon,
NR_CellGroupConfig_t *secondaryCellGroup,
@@ -89,7 +89,7 @@ int generate_CG_Config(gNB_RRC_INST *rrc,
NR_RRCReconfiguration_t *reconfig,
NR_RadioBearerConfig_t *rbconfig);
-int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo);
+int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m);
diff --git a/openair2/RRC/NR/rrc_gNB.c b/openair2/RRC/NR/rrc_gNB.c
index fba661055419503d999df33ab65ebc6fddd9d19f..1f341cfdf9c76c118d92c7594aa99f9e64bebb60 100644
--- a/openair2/RRC/NR/rrc_gNB.c
+++ b/openair2/RRC/NR/rrc_gNB.c
@@ -81,6 +81,7 @@
#include "SIMULATION/TOOLS/sim.h" // for taus
#include "executables/softmodem-common.h"
+#include <openair2/RRC/NR/rrc_gNB_UE_context.h>
//#define XER_PRINT
@@ -94,12 +95,10 @@ mui_t rrc_gNB_mui = 0;
void openair_nr_rrc_on(const protocol_ctxt_t *const ctxt_pP) {
LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" gNB:OPENAIR NR RRC IN....\n",PROTOCOL_NR_RRC_CTXT_ARGS(ctxt_pP));
-
rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.SI, BCCH, 1);
RC.nrrrc[ctxt_pP->module_id]->carrier.SI.Active = 1;
rrc_config_nr_buffer (&RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0, CCCH, 1);
RC.nrrrc[ctxt_pP->module_id]->carrier.Srb0.Active = 1;
-
}
///---------------------------------------------------------------------------------------------------------------///
@@ -172,7 +171,6 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge(
ue_context_pP->ue_context.primaryCC_id,
physicalCellGroupConfig,
physicalcellgroup_config);
-
do_SpCellConfig(RC.nrrrc[ctxt_pP->module_id],
spCellConfig);
}
@@ -181,57 +179,47 @@ void rrc_gNB_generate_SgNBAdditionRequestAcknowledge(
///---------------------------------------------------------------------------------------------------------------///
static void init_NR_SI(gNB_RRC_INST *rrc) {
-
-
LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__);
-
-
-
- rrc->carrier.MIB = (uint8_t*) malloc16(4);
+ rrc->carrier.MIB = (uint8_t *) malloc16(4);
rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0);
-
-
LOG_I(NR_RRC,"Done init_NR_SI\n");
-
-
rrc_mac_config_req_gNB(rrc->module_id,
- rrc->carrier.ssb_SubcarrierOffset,
+ rrc->carrier.ssb_SubcarrierOffset,
rrc->carrier.pdsch_AntennaPorts,
(NR_ServingCellConfigCommon_t *)rrc->carrier.servingcellconfigcommon,
- 0,
- 0,
- (NR_CellGroupConfig_t *)NULL
- );
+ 0,
+ 0, // WIP hardcoded rnti
+ (NR_CellGroupConfig_t *)NULL
+ );
-
- if (get_softmodem_params()->phy_test > 0) {
+ if (get_softmodem_params()->phy_test > 0 || get_softmodem_params()->do_ra > 0) {
// This is for phytest only, emulate first X2 message if uecap.raw file is present
FILE *fd;
-
fd = fopen("uecap.raw","r");
+
if (fd != NULL) {
char buffer[4096];
int msg_len=fread(buffer,1,4096,fd);
LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len);
LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message;
-
asn_dec_rval_t dec_rval = uper_decode_complete( NULL,
- &asn_DEF_LTE_UL_DCCH_Message,
- (void **)<E_UL_DCCH_Message,
- (uint8_t *)buffer,
- msg_len);
-
+ &asn_DEF_LTE_UL_DCCH_Message,
+ (void **)<E_UL_DCCH_Message,
+ (uint8_t *)buffer,
+ msg_len);
+
if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n");
- // free the memory
- SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 );
- return;
- }
+ // free the memory
+ SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 );
+ return;
+ }
+
fclose(fd);
xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message);
// recreate enough of X2 EN-DC Container
AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation,
- "ueCapabilityInformation not present\n");
+ "ueCapabilityInformation not present\n");
NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo));
CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1;
CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1));
@@ -239,49 +227,37 @@ static void init_NR_SI(gNB_RRC_INST *rrc) {
CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo));
NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo;
cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo));
- asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096);
+ asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,
+ (void *)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,buffer,4096);
AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
- enc_rval.failed_type->name, enc_rval.encoded);
+ enc_rval.failed_type->name, enc_rval.encoded);
OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo,
- (const char *)buffer,
- (enc_rval.encoded+7)>>3);
- parse_CG_ConfigInfo(rrc,CG_ConfigInfo);
- }
- else {
+ (const char *)buffer,
+ (enc_rval.encoded+7)>>3);
+ parse_CG_ConfigInfo(rrc,CG_ConfigInfo,NULL);
+ } else {
struct rrc_gNB_ue_context_s *ue_context_p = rrc_gNB_allocate_new_UE_context(rrc);
-
- LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p);
- rrc_add_nsa_user(rrc,ue_context_p);
- }
+ LOG_I(NR_RRC,"Adding new user (%p)\n",ue_context_p);
+ rrc_add_nsa_user(rrc,ue_context_p,NULL);
+ }
}
}
char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigurationReq *configuration) {
protocol_ctxt_t ctxt;
-
gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP];
-
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gnb_mod_idP, GNB_FLAG_YES, NOT_A_RNTI, 0, 0,gnb_mod_idP);
-
LOG_I(NR_RRC,
PROTOCOL_NR_RRC_CTXT_FMT" Init...\n",
PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt));
-#if OCP_FRAMEWORK
- while (rrc == NULL ) {
- LOG_E(NR_RRC, "RC.nrrrc not yet initialized, waiting 1 second\n");
- sleep(1);
- }
-#endif
AssertFatal(rrc != NULL, "RC.nrrrc not initialized!");
AssertFatal(NUMBER_OF_UE_MAX < (module_id_t)0xFFFFFFFFFFFFFFFF, " variable overflow");
AssertFatal(configuration!=NULL,"configuration input is null\n");
rrc->module_id = gnb_mod_idP;
rrc->Nb_ue = 0;
-
rrc->carrier.Srb0.Active = 0;
-
nr_uid_linear_allocator_init(&rrc->uid_allocator);
RB_INIT(&rrc->rrc_ue_head);
rrc->initial_id2_s1ap_ids = hashtable_create (NUMBER_OF_UE_MAX * 2, NULL, NULL);
@@ -291,7 +267,6 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu
rrc->carrier.pdsch_AntennaPorts = configuration->pdsch_AntennaPorts;
/// System Information INIT
LOG_I(NR_RRC, PROTOCOL_NR_RRC_CTXT_FMT" Checking release \n",PROTOCOL_NR_RRC_CTXT_ARGS(&ctxt));
-
init_NR_SI(rrc);
rrc_init_nr_global_param();
openair_nr_rrc_on(&ctxt);
@@ -300,49 +275,26 @@ char openair_rrc_gNB_configuration(const module_id_t gnb_mod_idP, gNB_RrcConfigu
void rrc_gNB_process_AdditionRequestInformation(const module_id_t gnb_mod_idP, x2ap_ENDC_sgnb_addition_req_t *m) {
+ struct NR_CG_ConfigInfo *cg_configinfo = NULL;
+ asn_dec_rval_t dec_rval = uper_decode_complete(NULL,
+ &asn_DEF_NR_CG_ConfigInfo,
+ (void **)&cg_configinfo,
+ (uint8_t *)m->rrc_buffer,
+ (int) m->rrc_buffer_size);//m->rrc_buffer_size);
+ gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP];
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n");
+ // free the memory
+ SEQUENCE_free(&asn_DEF_NR_CG_ConfigInfo, cg_configinfo, 1);
+ return;
+ }
- LTE_UL_DCCH_Message_t *LTE_UL_DCCH_Message = NULL;
-
- asn_dec_rval_t dec_rval = uper_decode_complete( NULL,
- &asn_DEF_LTE_UL_DCCH_Message,
- (void **)<E_UL_DCCH_Message,
- (uint8_t *)m->rrc_buffer,
- (int) m->rrc_buffer_size);//m->rrc_buffer_size);
-
-/* asn_dec_rval_t dec_rval = uper_decode( NULL,
- &asn_DEF_LTE_UL_DCCH_Message,
- (void **)<E_UL_DCCH_Message,
- (uint8_t *)m->rrc_buffer,
- (int) m->rrc_buffer_size, 0, 0);//m->rrc_buffer_size);
-*/
- gNB_RRC_INST *rrc=RC.nrrrc[gnb_mod_idP];
-
- if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
- AssertFatal(1==0,"NR_UL_DCCH_MESSAGE decode error\n");
- // free the memory
- SEQUENCE_free( &asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message, 1 );
- return;
- }
- xer_fprint(stdout,&asn_DEF_LTE_UL_DCCH_Message, LTE_UL_DCCH_Message);
- // recreate enough of X2 EN-DC Container
- AssertFatal(LTE_UL_DCCH_Message->message.choice.c1.present == LTE_UL_DCCH_MessageType__c1_PR_ueCapabilityInformation,
- "ueCapabilityInformation not present\n");
- NR_CG_ConfigInfo_t *CG_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo));
- CG_ConfigInfo->criticalExtensions.present = NR_CG_ConfigInfo__criticalExtensions_PR_c1;
- CG_ConfigInfo->criticalExtensions.choice.c1 = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1));
- CG_ConfigInfo->criticalExtensions.choice.c1->present = NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo;
- CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo = calloc(1,sizeof(*CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo));
- NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo;
- cg_ConfigInfo->ue_CapabilityInfo = calloc(1,sizeof(*cg_ConfigInfo->ue_CapabilityInfo));
- asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_LTE_UE_CapabilityRAT_ContainerList,NULL,(void*)<E_UL_DCCH_Message->message.choice.c1.choice.ueCapabilityInformation.criticalExtensions.choice.c1.choice.ueCapabilityInformation_r8.ue_CapabilityRAT_ContainerList,m->rrc_buffer,m->rrc_buffer_size);
- AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
- enc_rval.failed_type->name, enc_rval.encoded);
- OCTET_STRING_fromBuf(cg_ConfigInfo->ue_CapabilityInfo,
- (const char *)m->rrc_buffer,
- (enc_rval.encoded+7)>>3);
- parse_CG_ConfigInfo(rrc,CG_ConfigInfo);
-
+ xer_fprint(stdout,&asn_DEF_NR_CG_ConfigInfo, cg_configinfo);
+ // recreate enough of X2 EN-DC Container
+ AssertFatal(cg_configinfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo,
+ "ueCapabilityInformation not present\n");
+ parse_CG_ConfigInfo(rrc,cg_configinfo,m);
}
///---------------------------------------------------------------------------------------------------------------///
@@ -440,16 +392,15 @@ void *rrc_gnb_task(void *args_p) {
openair_rrc_gNB_configuration(GNB_INSTANCE_TO_MODULE_ID(instance), &NRRRC_CONFIGURATION_REQ(msg_p));
break;
- /* Messages from X2AP */
+ /* Messages from X2AP */
case X2AP_ENDC_SGNB_ADDITION_REQ:
- LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n");
- rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p));
- break;
+ LOG_I(NR_RRC, "Received ENDC sgNB addition request from X2AP \n");
+ rrc_gNB_process_AdditionRequestInformation(GNB_INSTANCE_TO_MODULE_ID(instance), &X2AP_ENDC_SGNB_ADDITION_REQ(msg_p));
+ break;
case X2AP_ENDC_SGNB_RECONF_COMPLETE:
- LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n");
- break;
-
+ LOG_I(NR_RRC, "Handling of reconfiguration complete message at RRC gNB is pending \n");
+ break;
default:
LOG_E(NR_RRC, "[gNB %d] Received unexpected message %s\n", instance, msg_name_p);
diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.c b/openair2/RRC/NR/rrc_gNB_GTPV1U.c
new file mode 100644
index 0000000000000000000000000000000000000000..9ab1bbf43a0512d5351075bacc7ecc6b62f0ac63
--- /dev/null
+++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.c
@@ -0,0 +1,94 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file rrc_gNB_GTPV1U.c
+ * \brief rrc GTPV1U procedures for gNB
+ * \author Lionel GAUTHIER, Panos MATZAKOS
+ * \version 1.0
+ * \company Eurecom
+ * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr
+ */
+
+# include "rrc_defs.h"
+# include "rrc_extern.h"
+# include "RRC/LTE/MESSAGES/asn1_msg.h"
+# include "rrc_eNB_GTPV1U.h"
+# include "rrc_eNB_UE_context.h"
+# include "msc.h"
+# include "openair2/RRC/NR/rrc_gNB_UE_context.h"
+
+//# if defined(ENABLE_ITTI)
+# include "asn1_conversions.h"
+# include "intertask_interface.h"
+//#endif
+
+# include "common/ran_context.h"
+
+extern RAN_CONTEXT_t RC;
+
+int
+rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP(
+ const protocol_ctxt_t *const ctxt_pP,
+ const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP,
+ uint8_t *inde_list
+) {
+ rnti_t rnti;
+ int i;
+ struct rrc_gNB_ue_context_s *ue_context_p = NULL;
+
+ if (create_tunnel_resp_pP) {
+ LOG_D(RRC, PROTOCOL_RRC_CTXT_UE_FMT" RX CREATE_TUNNEL_RESP num tunnels %u \n",
+ PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
+ create_tunnel_resp_pP->num_tunnels);
+ rnti = create_tunnel_resp_pP->rnti;
+ ue_context_p = rrc_gNB_get_ue_context(
+ RC.nrrrc[ctxt_pP->module_id],
+ ctxt_pP->rnti);
+
+ for (i = 0; i < create_tunnel_resp_pP->num_tunnels; i++) {
+ ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]] = create_tunnel_resp_pP->enb_S1u_teid[i];
+ ue_context_p->ue_context.gnb_gtp_addrs[inde_list[i]] = create_tunnel_resp_pP->enb_addr;
+ ue_context_p->ue_context.gnb_gtp_ebi[inde_list[i]] = create_tunnel_resp_pP->eps_bearer_id[i];
+ LOG_I(RRC, PROTOCOL_RRC_CTXT_UE_FMT" rrc_eNB_process_GTPV1U_CREATE_TUNNEL_RESP tunnel (%u, %u) bearer UE context index %u, msg index %u, id %u, gtp addr len %d \n",
+ PROTOCOL_RRC_CTXT_UE_ARGS(ctxt_pP),
+ create_tunnel_resp_pP->enb_S1u_teid[i],
+ ue_context_p->ue_context.gnb_gtp_teid[inde_list[i]],
+ inde_list[i],
+ i,
+ create_tunnel_resp_pP->eps_bearer_id[i],
+ create_tunnel_resp_pP->enb_addr.length);
+ }
+
+ MSC_LOG_RX_MESSAGE(
+ MSC_RRC_ENB,
+ MSC_GTPU_ENB,
+ NULL,0,
+ MSC_AS_TIME_FMT" CREATE_TUNNEL_RESP RNTI %"PRIx16" ntuns %u ebid %u enb-s1u teid %u",
+ 0,0,rnti,
+ create_tunnel_resp_pP->num_tunnels,
+ ue_context_p->ue_context.gnb_gtp_ebi[0],
+ ue_context_p->ue_context.gnb_gtp_teid[0]);
+ (void)rnti; /* avoid gcc warning "set but not used" */
+ return 0;
+ } else {
+ return -1;
+ }
+}
diff --git a/openair2/RRC/NR/rrc_gNB_GTPV1U.h b/openair2/RRC/NR/rrc_gNB_GTPV1U.h
new file mode 100644
index 0000000000000000000000000000000000000000..caff825a7a6283b0b5d8f2670909a24f05b804d6
--- /dev/null
+++ b/openair2/RRC/NR/rrc_gNB_GTPV1U.h
@@ -0,0 +1,39 @@
+/*
+ * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file rrc_gNB_GTPV1U.h
+ * \brief rrc GTPV1U procedures for gNB
+ * \author Lionel GAUTHIER, Panos MATZAKOS
+ * \version 1.0
+ * \company Eurecom
+ * \email: lionel.gauthier@eurecom.fr, panagiotis.matzakos@eurecom.fr
+ */
+
+#ifndef RRC_GNB_GTPV1U_H_
+#define RRC_GNB_GTPV1U_H_
+
+
+int
+rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP(
+ const protocol_ctxt_t *const ctxt_pP,
+ const gtpv1u_enb_create_tunnel_resp_t *const create_tunnel_resp_pP,
+ uint8_t *inde_list
+);
diff --git a/openair2/RRC/NR/rrc_gNB_UE_context.h b/openair2/RRC/NR/rrc_gNB_UE_context.h
index 762d9642897c8ceb3bd28ad25f436e2c7ae50edb..d703c4c34caa9e72e79b9e8500e42f0f2457bb09 100644
--- a/openair2/RRC/NR/rrc_gNB_UE_context.h
+++ b/openair2/RRC/NR/rrc_gNB_UE_context.h
@@ -27,8 +27,9 @@
* \company Eurecom
* \email: lionel.gauthier@eurecom.fr
*/
-#ifndef __RRC_ENB_UE_CONTEXT_H__
-#define __RRC_ENB_UE_CONTEXT_H__
+#ifndef __RRC_GNB_UE_CONTEXT_H__
+#define __RRC_GNB_UE_CONTEXT_H__
+
#include "collection/tree.h"
#include "COMMON/platform_types.h"
#include "nr_rrc_defs.h"
diff --git a/openair2/RRC/NR/rrc_gNB_internode.c b/openair2/RRC/NR/rrc_gNB_internode.c
index 581015db56df98e5e2f1ddc7490164d806ca3a8b..cacff5cf5c179fd9bf27db57973a2ef338df36a3 100644
--- a/openair2/RRC/NR/rrc_gNB_internode.c
+++ b/openair2/RRC/NR/rrc_gNB_internode.c
@@ -38,48 +38,49 @@
#include "LTE_UE-CapabilityRAT-ContainerList.h"
#include "NR_CG-Config.h"
-int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo) {
-
+int parse_CG_ConfigInfo(gNB_RRC_INST *rrc, NR_CG_ConfigInfo_t *CG_ConfigInfo, x2ap_ENDC_sgnb_addition_req_t *m) {
if (CG_ConfigInfo->criticalExtensions.present == NR_CG_ConfigInfo__criticalExtensions_PR_c1) {
if (CG_ConfigInfo->criticalExtensions.choice.c1) {
if (CG_ConfigInfo->criticalExtensions.choice.c1->present == NR_CG_ConfigInfo__criticalExtensions__c1_PR_cg_ConfigInfo) {
- NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo;
- if (cg_ConfigInfo->ue_CapabilityInfo) {
- // Decode UE-CapabilityRAT-ContainerList
+ NR_CG_ConfigInfo_IEs_t *cg_ConfigInfo = CG_ConfigInfo->criticalExtensions.choice.c1->choice.cg_ConfigInfo;
+
+ if (cg_ConfigInfo->ue_CapabilityInfo) {
+ // Decode UE-CapabilityRAT-ContainerList
LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList=NULL;
- asn_dec_rval_t dec_rval = uper_decode(NULL,
- &asn_DEF_LTE_UE_CapabilityRAT_ContainerList,
- (void**)&UE_CapabilityRAT_ContainerList,
- cg_ConfigInfo->ue_CapabilityInfo->buf,
- cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0);
+ UE_CapabilityRAT_ContainerList = calloc(1,sizeof(LTE_UE_CapabilityRAT_ContainerList_t));
+ asn_dec_rval_t dec_rval = uper_decode(NULL,
+ &asn_DEF_LTE_UE_CapabilityRAT_ContainerList,
+ (void **)&UE_CapabilityRAT_ContainerList,
+ cg_ConfigInfo->ue_CapabilityInfo->buf,
+ cg_ConfigInfo->ue_CapabilityInfo->size, 0, 0);
+
if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
- AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n",
- dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size);
- }
- rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList);
- }
- if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n");
- }
- else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n");
- }
- else {
+ AssertFatal(1==0,"[InterNode] Failed to decode NR_UE_CapabilityRAT_ContainerList (%zu bits), size of OCTET_STRING %lu\n",
+ dec_rval.consumed, cg_ConfigInfo->ue_CapabilityInfo->size);
+ }
+
+ rrc_parse_ue_capabilities(rrc,UE_CapabilityRAT_ContainerList, m,cg_ConfigInfo);
+ }
+
+ if (cg_ConfigInfo->candidateCellInfoListMN) AssertFatal(1==0,"Can't handle candidateCellInfoListMN yet\n");
+ } else AssertFatal(1==0,"c1 extension is not cg_ConfigInfo, returning\n");
+ } else {
LOG_E(RRC,"c1 extension not found, returning\n");
- return(-1);
+ return(-1);
}
} else {
LOG_E(RRC,"Ignoring unknown CG_ConfigInfo extensions\n");
return(-1);
}
- return(0);
-}
-
-int generate_CG_Config(gNB_RRC_INST *rrc,
- NR_CG_Config_t *cg_Config,
- NR_RRCReconfiguration_t *reconfig,
- NR_RadioBearerConfig_t *rbconfig) {
+ return(0);
+}
+int generate_CG_Config(gNB_RRC_INST *rrc,
+ NR_CG_Config_t *cg_Config,
+ NR_RRCReconfiguration_t *reconfig,
+ NR_RadioBearerConfig_t *rbconfig) {
cg_Config->criticalExtensions.present = NR_CG_Config__criticalExtensions_PR_c1;
cg_Config->criticalExtensions.choice.c1 = calloc(1,sizeof(*cg_Config->criticalExtensions.choice.c1));
cg_Config->criticalExtensions.choice.c1->present = NR_CG_Config__criticalExtensions__c1_PR_cg_Config;
@@ -91,36 +92,37 @@ int generate_CG_Config(gNB_RRC_INST *rrc,
enc_rval.failed_type->name, enc_rval.encoded);
cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig = calloc(1,sizeof(OCTET_STRING_t));
OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_CellGroupConfig,
- (const char *)buffer,
- (enc_rval.encoded+7)>>3);
+ (const char *)buffer,
+ (enc_rval.encoded+7)>>3);
total_size = (enc_rval.encoded+7)>>3;
-
LOG_I(RRC,"Dumping NR_RRCReconfiguration message (%jd bytes)\n",(enc_rval.encoded+7)>>3);
- for (int i=0;i<(enc_rval.encoded+7)>>3;i++) {
+
+ for (int i=0; i<(enc_rval.encoded+7)>>3; i++) {
printf("%02x",((uint8_t *)buffer)[i]);
}
+
printf("\n");
FILE *fd = fopen("reconfig.raw","w");
- fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd);
+ fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd);
fclose(fd);
-
enc_rval = uper_encode_to_buffer(&asn_DEF_NR_RadioBearerConfig, NULL, (void *)rbconfig, buffer, 1024);
AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n",
enc_rval.failed_type->name, enc_rval.encoded);
cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config = calloc(1,sizeof(OCTET_STRING_t));
OCTET_STRING_fromBuf(cg_Config->criticalExtensions.choice.c1->choice.cg_Config->scg_RB_Config,
- (const char *)buffer,
- (enc_rval.encoded+7)>>3);
+ (const char *)buffer,
+ (enc_rval.encoded+7)>>3);
LOG_I(RRC,"Dumping scg_RB_Config message (%jd bytes)\n",(enc_rval.encoded+7)>>3);
- for (int i=0;i<(enc_rval.encoded+7)>>3;i++) {
- printf("%02x",((uint8_t*)buffer)[i]);
+
+ for (int i=0; i<(enc_rval.encoded+7)>>3; i++) {
+ printf("%02x",((uint8_t *)buffer)[i]);
}
+
printf("\n");
fd = fopen("rbconfig.raw","w");
- fwrite((void*)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd);
+ fwrite((void *)buffer,1,(size_t)((enc_rval.encoded+7)>>3),fd);
fclose(fd);
total_size = total_size + ((enc_rval.encoded+7)>>3);
-
return(total_size);
}
diff --git a/openair2/RRC/NR/rrc_gNB_nsa.c b/openair2/RRC/NR/rrc_gNB_nsa.c
index 763c208dfe64b72d31e684e8b14b9e9d1bab96e5..22e31aa48abf5f6e66a8919165ec6390f63e8be9 100644
--- a/openair2/RRC/NR/rrc_gNB_nsa.c
+++ b/openair2/RRC/NR/rrc_gNB_nsa.c
@@ -37,122 +37,211 @@
#include "LTE_UE-CapabilityRAT-ContainerList.h"
#include "NR_CG-Config.h"
#include "openair2/LAYER2/NR_MAC_gNB/mac_proto.h"
+#include "openair2/RRC/LTE/rrc_eNB_GTPV1U.h"
+#include "executables/softmodem-common.h"
+#include <openair2/RRC/NR/rrc_gNB_UE_context.h>
-void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) {
-
+void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc, LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList, x2ap_ENDC_sgnb_addition_req_t *m, NR_CG_ConfigInfo_IEs_t *cg_config_info) {
struct rrc_gNB_ue_context_s *ue_context_p = NULL;
+
OCTET_STRING_t *ueCapabilityRAT_Container_nr=NULL;
OCTET_STRING_t *ueCapabilityRAT_Container_MRDC=NULL;
+ asn_dec_rval_t dec_rval;
int list_size=0;
+
AssertFatal(UE_CapabilityRAT_ContainerList!=NULL,"UE_CapabilityRAT_ContainerList is null\n");
AssertFatal((list_size=UE_CapabilityRAT_ContainerList->list.count) >= 2, "UE_CapabilityRAT_ContainerList->list.size %d < 2\n",UE_CapabilityRAT_ContainerList->list.count);
- for (int i=0;i<list_size;i++) {
+
+ for (int i=0; i<list_size; i++) {
if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_nr) ueCapabilityRAT_Container_nr = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container;
else if (UE_CapabilityRAT_ContainerList->list.array[i]->rat_Type == LTE_RAT_Type_eutra_nr) ueCapabilityRAT_Container_MRDC = &UE_CapabilityRAT_ContainerList->list.array[i]->ueCapabilityRAT_Container;
- }
+ }
- AssertFatal(ueCapabilityRAT_Container_nr!=NULL,"ueCapabilityRAT_Container_nr is NULL\n");
- AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n");
// decode and store capabilities
ue_context_p = rrc_gNB_allocate_new_UE_context(rrc);
-
- asn_dec_rval_t dec_rval = uper_decode(NULL,
- &asn_DEF_NR_UE_NR_Capability,
- (void **)&ue_context_p->ue_context.UE_Capability_nr,
- ueCapabilityRAT_Container_nr->buf,
- ueCapabilityRAT_Container_nr->size, 0, 0);
-
- if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
- LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size);
+
+ if (ueCapabilityRAT_Container_nr != NULL) {
+ dec_rval = uper_decode(NULL,
+ &asn_DEF_NR_UE_NR_Capability,
+ (void **)&ue_context_p->ue_context.UE_Capability_nr,
+ ueCapabilityRAT_Container_nr->buf,
+ ueCapabilityRAT_Container_nr->size, 0, 0);
+
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ LOG_E(RRC, "Failed to decode UE NR capabilities (%zu bytes) container size %lu\n", dec_rval.consumed,ueCapabilityRAT_Container_nr->size);
ASN_STRUCT_FREE(asn_DEF_NR_UE_NR_Capability,
ue_context_p->ue_context.UE_Capability_nr);
ue_context_p->ue_context.UE_Capability_nr = 0;
AssertFatal(1==0,"exiting\n");
+ }
}
- dec_rval = uper_decode(NULL,
- &asn_DEF_NR_UE_MRDC_Capability,
- (void **)&ue_context_p->ue_context.UE_Capability_MRDC,
- ueCapabilityRAT_Container_MRDC->buf,
- ueCapabilityRAT_Container_MRDC->size, 0, 0);
+ if (ueCapabilityRAT_Container_MRDC != NULL) {
+ dec_rval = uper_decode(NULL,
+ &asn_DEF_NR_UE_MRDC_Capability,
+ (void **)&ue_context_p->ue_context.UE_Capability_MRDC,
+ ueCapabilityRAT_Container_MRDC->buf,
+ ueCapabilityRAT_Container_MRDC->size, 0, 0);
- if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ if ((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
LOG_E(RRC, "Failed to decode UE MRDC capabilities (%zu bytes)\n", dec_rval.consumed);
ASN_STRUCT_FREE(asn_DEF_NR_UE_MRDC_Capability,
ue_context_p->ue_context.UE_Capability_MRDC);
ue_context_p->ue_context.UE_Capability_MRDC = 0;
AssertFatal(1==0,"exiting\n");
+ }
}
// dump ue_capabilities
- if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
- xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr);
- }
+ if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_nr != NULL) ) {
+ xer_fprint(stdout, &asn_DEF_NR_UE_NR_Capability, ue_context_p->ue_context.UE_Capability_nr);
+ }
+
+ if ( LOG_DEBUGFLAG(DEBUG_ASN1 && ueCapabilityRAT_Container_MRDC != NULL) ) {
+ xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC);
+ }
- if ( LOG_DEBUGFLAG(DEBUG_ASN1) ) {
- xer_fprint(stdout, &asn_DEF_NR_UE_MRDC_Capability, ue_context_p->ue_context.UE_Capability_MRDC);
- }
+ if(cg_config_info && cg_config_info->mcg_RB_Config) {
+ asn_dec_rval_t dec_rval = uper_decode(NULL,
+ &asn_DEF_NR_RadioBearerConfig,
+ (void **)&ue_context_p->ue_context.rb_config,
+ cg_config_info->mcg_RB_Config->buf,
+ cg_config_info->mcg_RB_Config->size, 0, 0);
+
+ if((dec_rval.code != RC_OK) && (dec_rval.consumed == 0)) {
+ AssertFatal(1==0,"[InterNode] Failed to decode mcg_rb_config (%zu bits), size of OCTET_STRING %lu\n",
+ dec_rval.consumed, cg_config_info->mcg_RB_Config->size);
+ }
+ }
- rrc_add_nsa_user(rrc,ue_context_p);
+ xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void *)ue_context_p->ue_context.rb_config);
+ rrc_add_nsa_user(rrc,ue_context_p, m);
}
-void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p) {
-
-// generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331)
+/* generate prototypes for the tree management functions (RB_INSERT used in rrc_add_nsa_user) */
+RB_PROTOTYPE(rrc_nr_ue_tree_s, rrc_gNB_ue_context_s, entries,
+ rrc_gNB_compare_ue_rnti_id);
+void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_p, x2ap_ENDC_sgnb_addition_req_t *m) {
+ // generate nr-Config-r15 containers for LTE RRC : inside message for X2 EN-DC (CG-Config Message from 38.331)
rrc_gNB_carrier_data_t *carrier=&rrc->carrier;
-
MessageDef *msg;
msg = itti_alloc_new_message(TASK_RRC_ENB, X2AP_ENDC_SGNB_ADDITION_REQ_ACK);
-
-// NR RRCReconfiguration
-
+ gtpv1u_enb_create_tunnel_req_t create_tunnel_req;
+ gtpv1u_enb_create_tunnel_resp_t create_tunnel_resp;
+ protocol_ctxt_t ctxt;
+ // NR RRCReconfiguration
AssertFatal(rrc->Nb_ue < MAX_NR_RRC_UE_CONTEXTS,"cannot add another UE\n");
-
ue_context_p->ue_context.reconfig = calloc(1,sizeof(NR_RRCReconfiguration_t));
ue_context_p->ue_context.secondaryCellGroup = calloc(1,sizeof(NR_CellGroupConfig_t));
- memset((void*)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t));
+ memset((void *)ue_context_p->ue_context.reconfig,0,sizeof(NR_RRCReconfiguration_t));
ue_context_p->ue_context.reconfig->rrc_TransactionIdentifier=0;
ue_context_p->ue_context.reconfig->criticalExtensions.present = NR_RRCReconfiguration__criticalExtensions_PR_rrcReconfiguration;
NR_RRCReconfiguration_IEs_t *reconfig_ies=calloc(1,sizeof(NR_RRCReconfiguration_IEs_t));
ue_context_p->ue_context.reconfig->criticalExtensions.choice.rrcReconfiguration = reconfig_ies;
carrier->initial_csi_index[rrc->Nb_ue] = 0;
+ if (get_softmodem_params()->phy_test == 1 || get_softmodem_params()->do_ra == 1){
+ ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t));
+ fill_default_rbconfig(ue_context_p->ue_context.rb_config);
+ }
fill_default_reconfig(carrier->servingcellconfigcommon,
- reconfig_ies,
- ue_context_p->ue_context.secondaryCellGroup,
- carrier->pdsch_AntennaPorts,
- carrier->initial_csi_index[rrc->Nb_ue]);
-
- ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t));
-
- fill_default_rbconfig(ue_context_p->ue_context.rb_config);
+ reconfig_ies,
+ ue_context_p->ue_context.secondaryCellGroup,
+ carrier->pdsch_AntennaPorts,
+ carrier->initial_csi_index[rrc->Nb_ue]);
ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity;
NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config));
- memset((void*)CG_Config,0,sizeof(*CG_Config));
- int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config);
+ memset((void *)CG_Config,0,sizeof(*CG_Config));
+ //int CG_Config_size = generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config);
+ generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config);
+
+ if(m!=NULL) {
+ uint8_t inde_list[m->nb_e_rabs_tobeadded];
+ memset(inde_list, 0, m->nb_e_rabs_tobeadded*sizeof(uint8_t));
+
+ if (m->nb_e_rabs_tobeadded>0) {
+ for (int i=0; i<m->nb_e_rabs_tobeadded; i++) {
+ // Add the new E-RABs at the corresponding rrc ue context of the gNB
+ ue_context_p->ue_context.e_rab[i].param.e_rab_id = m->e_rabs_tobeadded[i].e_rab_id;
+ ue_context_p->ue_context.e_rab[i].param.gtp_teid = m->e_rabs_tobeadded[i].gtp_teid;
+ memcpy(&ue_context_p->ue_context.e_rab[i].param.sgw_addr, &m->e_rabs_tobeadded[i].sgw_addr, sizeof(transport_layer_addr_t));
+ ue_context_p->ue_context.nb_of_e_rabs++;
+ //Fill the required E-RAB specific information for the creation of the S1-U tunnel between the gNB and the SGW
+ create_tunnel_req.eps_bearer_id[i] = ue_context_p->ue_context.e_rab[i].param.e_rab_id;
+ create_tunnel_req.sgw_S1u_teid[i] = ue_context_p->ue_context.e_rab[i].param.gtp_teid;
+ memcpy(&create_tunnel_req.sgw_addr[i], &ue_context_p->ue_context.e_rab[i].param.sgw_addr, sizeof(transport_layer_addr_t));
+ inde_list[i] = i;
+ LOG_I(RRC,"S1-U tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n",
+ i,
+ create_tunnel_req.sgw_addr[i].buffer[0],
+ create_tunnel_req.sgw_addr[i].buffer[1],
+ create_tunnel_req.sgw_addr[i].buffer[2],
+ create_tunnel_req.sgw_addr[i].buffer[3],
+ create_tunnel_req.sgw_addr[i].length,
+ create_tunnel_req.sgw_S1u_teid[i]);
+ }
+
+ create_tunnel_req.rnti = ue_context_p->ue_id_rnti;
+ create_tunnel_req.num_tunnels = m->nb_e_rabs_tobeadded;
+ RB_INSERT(rrc_nr_ue_tree_s, &RC.nrrrc[rrc->module_id]->rrc_ue_head, ue_context_p);
+ PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, rrc->module_id, GNB_FLAG_YES, ue_context_p->ue_id_rnti, 0, 0,rrc->module_id);
+ gtpv1u_create_s1u_tunnel(
+ ctxt.instance,
+ &create_tunnel_req,
+ &create_tunnel_resp);
+ rrc_gNB_process_GTPV1U_CREATE_TUNNEL_RESP(
+ &ctxt,
+ &create_tunnel_resp,
+ &inde_list[0]);
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).nb_e_rabs_admitted_tobeadded = m->nb_e_rabs_tobeadded;
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).target_assoc_id = m->target_assoc_id;
+
+ for(int i=0; i<ue_context_p->ue_context.nb_of_e_rabs; i++) {
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = ue_context_p->ue_context.e_rab[i].param.e_rab_id;
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid = create_tunnel_resp.enb_S1u_teid[i];
+ memcpy(&X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr, &create_tunnel_resp.enb_addr, sizeof(transport_layer_addr_t));
+ //The length field in the X2AP targetting structure is expected in bits but the create_tunnel_resp returns the address length in bytes
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length = create_tunnel_resp.enb_addr.length*8;
+ LOG_I(RRC,"S1-U create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n",
+ i,
+ create_tunnel_resp.enb_addr.buffer[0],
+ create_tunnel_resp.enb_addr.buffer[1],
+ create_tunnel_resp.enb_addr.buffer[2],
+ create_tunnel_resp.enb_addr.buffer[3],
+ create_tunnel_resp.enb_addr.length,
+ create_tunnel_resp.enb_S1u_teid[i]);
+ LOG_I(RRC,"X2AP sGNB Addition Request: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n",
+ i,
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[0],
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[1],
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[2],
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer[3],
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length,
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gtp_teid);
+ }
+ } else
+ LOG_W(RRC, "No E-RAB to be added received from SgNB Addition Request message \n");
+ }
//X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = CG_Config_size; //Need to verify correct value for the buffer_size
// Send to X2 entity to transport to MeNB
asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CG_Config,
- NULL,
- (void *)CG_Config,
- X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer,
- 1024);
-
+ NULL,
+ (void *)CG_Config,
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer,
+ 1024);
X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).rrc_buffer_size = (enc_rval.encoded+7)>>3;
-
itti_send_msg_to_task(TASK_X2AP, ENB_MODULE_ID_TO_INSTANCE(0), msg); //Check right id instead of hardcoding
-
rrc->Nb_ue++;
// configure MAC and RLC
rrc_mac_config_req_gNB(rrc->module_id,
- rrc->carrier.ssb_SubcarrierOffset,
+ rrc->carrier.ssb_SubcarrierOffset,
rrc->carrier.pdsch_AntennaPorts,
- NULL,
- 1, // add_ue flag
- ue_context_p->ue_id_rnti,
- ue_context_p->ue_context.secondaryCellGroup);
+ NULL,
+ 1, // add_ue flag
+ ue_context_p->ue_id_rnti,
+ ue_context_p->ue_context.secondaryCellGroup);
}
diff --git a/openair2/RRC/NR/rrc_gNB_reconfig.c b/openair2/RRC/NR/rrc_gNB_reconfig.c
index 1df17a19aa0087757d84ec47c7158a410f4a2819..6ea6f3b3b33181ba9944a27df61963b92797f22c 100644
--- a/openair2/RRC/NR/rrc_gNB_reconfig.c
+++ b/openair2/RRC/NR/rrc_gNB_reconfig.c
@@ -49,23 +49,19 @@
void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon,
- NR_CellGroupConfig_t *secondaryCellGroup,
- int scg_id,
- int servCellIndex,
- int n_physical_antenna_ports,
- int initial_csi_index) {
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ int scg_id,
+ int servCellIndex,
+ int n_physical_antenna_ports,
+ int initial_csi_index) {
AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n");
AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n");
-
memset(secondaryCellGroup,0,sizeof(NR_CellGroupConfig_t));
secondaryCellGroup->cellGroupId = scg_id;
-
NR_RLC_BearerConfig_t *RLC_BearerConfig = calloc(1,sizeof(*RLC_BearerConfig));
-
RLC_BearerConfig->logicalChannelIdentity = 4;
RLC_BearerConfig->servedRadioBearer = calloc(1,sizeof(*RLC_BearerConfig->servedRadioBearer));
- RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity;
-
+ RLC_BearerConfig->servedRadioBearer->present = NR_RLC_BearerConfig__servedRadioBearer_PR_drb_Identity;
RLC_BearerConfig->servedRadioBearer->choice.drb_Identity=1;
RLC_BearerConfig->reestablishRLC=calloc(1,sizeof(*RLC_BearerConfig->reestablishRLC));
*RLC_BearerConfig->reestablishRLC=NR_RLC_BearerConfig__reestablishRLC_true;
@@ -73,17 +69,15 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
RLC_BearerConfig->rlc_Config->present = NR_RLC_Config_PR_am;
RLC_BearerConfig->rlc_Config->choice.am = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am));
RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength));
- *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18;
+ *RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18;
RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.t_PollRetransmit = NR_T_PollRetransmit_ms45;
RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollPDU = NR_PollPDU_p64;
RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.pollByte = NR_PollByte_kB500;
RLC_BearerConfig->rlc_Config->choice.am->ul_AM_RLC.maxRetxThreshold = NR_UL_AM_RLC__maxRetxThreshold_t32;
-
RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = calloc(1,sizeof(*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength));
*RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.sn_FieldLength = NR_SN_FieldLengthAM_size18;
RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_Reassembly = NR_T_Reassembly_ms15;
RLC_BearerConfig->rlc_Config->choice.am->dl_AM_RLC.t_StatusProhibit = NR_T_StatusProhibit_ms15;
-
RLC_BearerConfig->mac_LogicalChannelConfig = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig));
RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters = calloc(1,sizeof(*RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters));
RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->priority = 1;
@@ -99,10 +93,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_Mask = false;
RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->logicalChannelSR_DelayTimerApplied = false;
RLC_BearerConfig->mac_LogicalChannelConfig->ul_SpecificParameters->bitRateQueryProhibitTimer = NULL;
-
secondaryCellGroup->rlc_BearerToAddModList = calloc(1,sizeof(*secondaryCellGroup->rlc_BearerToAddModList));
ASN_SEQUENCE_ADD(&secondaryCellGroup->rlc_BearerToAddModList->list, RLC_BearerConfig);
-
secondaryCellGroup->mac_CellGroupConfig=calloc(1,sizeof(*secondaryCellGroup->mac_CellGroupConfig));
secondaryCellGroup->mac_CellGroupConfig->drx_Config = NULL;
secondaryCellGroup->mac_CellGroupConfig->schedulingRequestConfig = NULL;
@@ -126,25 +118,20 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->dummy=false;
secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_Type2OtherCell = false;
secondaryCellGroup->mac_CellGroupConfig->phr_Config->choice.setup->phr_ModeOtherCG = NR_PHR_Config__phr_ModeOtherCG_real;
-
secondaryCellGroup->mac_CellGroupConfig->skipUplinkTxDynamic=false;
secondaryCellGroup->mac_CellGroupConfig->ext1 = NULL;
-
-
secondaryCellGroup->physicalCellGroupConfig = calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig));
-
secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUCCH=NULL;
secondaryCellGroup->physicalCellGroupConfig->harq_ACK_SpatialBundlingPUSCH=NULL;
secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=calloc(1,sizeof(*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1));
*secondaryCellGroup->physicalCellGroupConfig->p_NR_FR1=20;
- secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic;
+ secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook=NR_PhysicalCellGroupConfig__pdsch_HARQ_ACK_Codebook_dynamic;
secondaryCellGroup->physicalCellGroupConfig->tpc_SRS_RNTI=NULL;
secondaryCellGroup->physicalCellGroupConfig->tpc_PUCCH_RNTI=NULL;
secondaryCellGroup->physicalCellGroupConfig->tpc_PUSCH_RNTI=NULL;
secondaryCellGroup->physicalCellGroupConfig->sp_CSI_RNTI=NULL;
secondaryCellGroup->physicalCellGroupConfig->cs_RNTI=NULL;
secondaryCellGroup->physicalCellGroupConfig->ext1=NULL;
-
secondaryCellGroup->spCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig));
secondaryCellGroup->spCellConfig->servCellIndex = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->servCellIndex));
*secondaryCellGroup->spCellConfig->servCellIndex = servCellIndex;
@@ -154,7 +141,26 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->spCellConfig->reconfigurationWithSync->t304=NR_ReconfigurationWithSync__t304_ms2000;
secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = NULL;
secondaryCellGroup->spCellConfig->reconfigurationWithSync->ext1 = NULL;
-
+ /* contention free ra */
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated = calloc(1,sizeof(struct NR_ReconfigurationWithSync__rach_ConfigDedicated));
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->present= NR_ReconfigurationWithSync__rach_ConfigDedicated_PR_uplink;
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink= calloc(1,sizeof(struct NR_RACH_ConfigDedicated));
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra= calloc(1,sizeof(struct NR_CFRA));
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->ra_Prioritization= NULL;
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions= calloc(1,sizeof(struct NR_CFRA__occasions));
+ memcpy(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->rach_ConfigGeneric,
+ &servingcellconfigcommon->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric, sizeof(NR_RACH_ConfigGeneric_t));
+ //secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= calloc(1,sizeof(long));
+ //*secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion = NR_CFRA__occasions__ssb_perRACH_Occasion_one;
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->occasions->ssb_perRACH_Occasion= NULL;
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.present = NR_CFRA__resources_PR_ssb;
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb = calloc(1,sizeof(struct NR_CFRA__resources__ssb));
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ra_ssb_OccasionMaskIndex = 0;
+ struct NR_CFRA_SSB_Resource *ssbElem = calloc(1,sizeof(struct NR_CFRA_SSB_Resource));
+ ssbElem->ssb = 0;
+ ssbElem->ra_PreambleIndex= 63;
+ ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->resources.choice.ssb->ssb_ResourceList.list,ssbElem);
+ secondaryCellGroup->spCellConfig->reconfigurationWithSync->rach_ConfigDedicated->choice.uplink->cfra->ext1 = NULL;
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants));
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->present = NR_SetupRelease_RLF_TimersAndConstants_PR_setup;
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup));
@@ -163,21 +169,18 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->n311 = NR_RLF_TimersAndConstants__n311_n1;
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1 = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1));
secondaryCellGroup->spCellConfig->rlf_TimersAndConstants->choice.setup->ext1->t311_v1530 = NR_RLF_TimersAndConstants__ext1__t311_v1530_ms30000;
-
secondaryCellGroup->spCellConfig->rlmInSyncOutOfSyncThreshold = NULL;
-
-
-
secondaryCellGroup->spCellConfig->spCellConfigDedicated = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated));
secondaryCellGroup->spCellConfig->spCellConfigDedicated->tdd_UL_DL_ConfigurationDedicated = NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP));
-
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdcch_Config=NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config));
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup;
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup));
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup = calloc(1,
+ sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup));
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL;
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA));
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,
+ sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA));
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup));
@@ -190,6 +193,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition));
*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0;
+#if 0
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList));
NR_TCI_State_t*tci0=calloc(1,sizeof(*tci0));
@@ -351,10 +355,11 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
tci15->qcl_Type1.referenceSignal.choice.ssb = 7;
tci15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC;
ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tci15);
+#endif
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL;
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0;
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL;
@@ -379,6 +384,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config));
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = NULL;
+#if 0
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig));
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup;
@@ -389,6 +396,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer));
*secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2;
+#endif
secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToReleaseList= NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList));
@@ -407,17 +415,45 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Common->pdcch_ConfigCommon->present = NR_SetupRelease_PDCCH_ConfigCommon_PR_setup;
bwp->bwp_Common->pdcch_ConfigCommon->choice.setup = calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup));
bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=NULL;
- bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=NULL;
- bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL;
+ bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet));
+ NR_ControlResourceSet_t *coreset = calloc(1,sizeof(*coreset));
+ coreset->controlResourceSetId=1;
+ // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B,
+ coreset->frequencyDomainResources.buf = calloc(1,6);
+ coreset->frequencyDomainResources.buf[0] = 0xff;
+ coreset->frequencyDomainResources.buf[1] = 0xff;
+ coreset->frequencyDomainResources.buf[2] = 0;
+ coreset->frequencyDomainResources.buf[3] = 0;
+ coreset->frequencyDomainResources.buf[4] = 0;
+ coreset->frequencyDomainResources.buf[5] = 0;
+ coreset->frequencyDomainResources.size = 6;
+ coreset->frequencyDomainResources.bits_unused = 3;
+ coreset->duration=1;
+ coreset->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved;
+ coreset->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle;
+
+ coreset->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset->tci_StatesPDCCH_ToAddList));
+ NR_TCI_StateId_t *tci[8];
+ for (int i=0;i<8;i++) {
+ tci[i]=calloc(1,sizeof(*tci[i]));
+ *tci[i] = i;
+ ASN_SEQUENCE_ADD(&coreset->tci_StatesPDCCH_ToAddList->list,tci[i]);
+ }
+ coreset->tci_StatesPDCCH_ToReleaseList = NULL;
+ coreset->tci_PresentInDCI = NULL;
+ coreset->pdcch_DMRS_ScramblingID = NULL;
+
+ bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonControlResourceSet = coreset;
+
+ bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->searchSpaceZero=NULL;
bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=NULL;
-
bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList=calloc(1,sizeof(*bwp->bwp_Common->pdcch_ConfigCommon->choice.setup->commonSearchSpaceList));
NR_SearchSpace_t *ss=calloc(1,sizeof(*ss));
ss->searchSpaceId = 1;
ss->controlResourceSetId=calloc(1,sizeof(*ss->controlResourceSetId));
- *ss->controlResourceSetId=0;
+ *ss->controlResourceSetId=1;
ss->monitoringSlotPeriodicityAndOffset = calloc(1,sizeof(*ss->monitoringSlotPeriodicityAndOffset));
ss->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1;
ss->duration=NULL;
@@ -474,64 +510,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Dedicated->pdcch_Config->present = NR_SetupRelease_PDCCH_Config_PR_setup;
bwp->bwp_Dedicated->pdcch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup));
bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList));
- NR_ControlResourceSet_t *coreset0 = calloc(1,sizeof(*coreset0));
- coreset0->controlResourceSetId=1;
- // frequencyDomainResources '11111111 11111111 00000000 00000000 00000000 00000'B,
- coreset0->frequencyDomainResources.buf = calloc(1,6);
- coreset0->frequencyDomainResources.buf[0] = 0xff;
- coreset0->frequencyDomainResources.buf[1] = 0xff;
- coreset0->frequencyDomainResources.buf[2] = 0;
- coreset0->frequencyDomainResources.buf[3] = 0;
- coreset0->frequencyDomainResources.buf[4] = 0;
- coreset0->frequencyDomainResources.buf[5] = 0;
- coreset0->frequencyDomainResources.size = 6;
- coreset0->frequencyDomainResources.bits_unused = 3;
- coreset0->duration=1;
- coreset0->cce_REG_MappingType.present = NR_ControlResourceSet__cce_REG_MappingType_PR_nonInterleaved;
- coreset0->precoderGranularity = NR_ControlResourceSet__precoderGranularity_sameAsREG_bundle;
-
- coreset0->tci_StatesPDCCH_ToAddList=calloc(1,sizeof(*coreset0->tci_StatesPDCCH_ToAddList));
- NR_TCI_StateId_t *tci[8];
- for (int i=0;i<8;i++) {
- tci[i]=calloc(1,sizeof(*tci[i]));
- *tci[i] = i;
- ASN_SEQUENCE_ADD(&coreset0->tci_StatesPDCCH_ToAddList->list,tci[i]);
- }
- coreset0->tci_StatesPDCCH_ToReleaseList = NULL;
- coreset0->tci_PresentInDCI = NULL;
- coreset0->pdcch_DMRS_ScramblingID = NULL;
+
ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list,
- coreset0);
+ coreset);
bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList = calloc(1,sizeof(*bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList));
- NR_SearchSpace_t *ss3 = calloc(1,sizeof(*ss3));
+
NR_SearchSpace_t *ss2 = calloc(1,sizeof(*ss2));
- ss3->searchSpaceId=3;
- ss3->controlResourceSetId=calloc(1,sizeof(*ss3->controlResourceSetId));
- *ss3->controlResourceSetId=1;
- ss3->monitoringSlotPeriodicityAndOffset=calloc(1,sizeof(*ss3->monitoringSlotPeriodicityAndOffset));
- ss3->monitoringSlotPeriodicityAndOffset->present = NR_SearchSpace__monitoringSlotPeriodicityAndOffset_PR_sl1;
- ss3->monitoringSlotPeriodicityAndOffset->choice.sl1=(NULL_t)0;
- ss3->duration=NULL;
- ss3->monitoringSymbolsWithinSlot = calloc(1,sizeof(*ss3->monitoringSymbolsWithinSlot));
- ss3->monitoringSymbolsWithinSlot->buf = calloc(1,2);
- ss3->monitoringSymbolsWithinSlot->size = 2;
- ss3->monitoringSymbolsWithinSlot->bits_unused = 2;
- ss3->monitoringSymbolsWithinSlot->buf[0]=0xc0;
- ss3->monitoringSymbolsWithinSlot->buf[1]=0x0;
- ss3->nrofCandidates=calloc(1,sizeof(*ss3->nrofCandidates));
- ss3->nrofCandidates->aggregationLevel1 = NR_SearchSpace__nrofCandidates__aggregationLevel1_n0;
- ss3->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0;
- ss3->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1;
- ss3->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n0;
- ss3->nrofCandidates->aggregationLevel16 = NR_SearchSpace__nrofCandidates__aggregationLevel16_n0;
- ss3->searchSpaceType=calloc(1,sizeof(*ss3->searchSpaceType));
- ss3->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_common;
- ss3->searchSpaceType->choice.common = calloc(1,sizeof(*ss3->searchSpaceType->choice.common));
- ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0=calloc(1,sizeof(*ss3->searchSpaceType->choice.common->dci_Format0_0_AndFormat1_0));
- ss3->searchSpaceType->choice.common->dci_Format2_0=NULL;
- ss3->searchSpaceType->choice.common->dci_Format2_2=NULL;
- ss3->searchSpaceType->choice.common->dci_Format2_3=NULL;
ss2->searchSpaceId=2;
ss2->controlResourceSetId=calloc(1,sizeof(*ss2->controlResourceSetId));
@@ -555,10 +540,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ss2->searchSpaceType=calloc(1,sizeof(*ss2->searchSpaceType));
ss2->searchSpaceType->present = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
ss2->searchSpaceType->choice.ue_Specific = calloc(1,sizeof(*ss2->searchSpaceType->choice.ue_Specific));
- ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_0_And_1_0;
+ ss2->searchSpaceType->choice.ue_Specific->dci_Formats=NR_SearchSpace__searchSpaceType__ue_Specific__dci_Formats_formats0_1_And_1_1;
- ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list,
- ss3);
ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdcch_Config->choice.setup->searchSpacesToAddModList->list,
ss2);
@@ -572,6 +555,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA));
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup;
+
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup));
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL;
@@ -583,6 +567,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition));
*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0;
+ bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=NULL;
+#if 0
bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList=calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList));
NR_TCI_State_t*tcid0=calloc(1,sizeof(*tcid0));
@@ -744,10 +730,11 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
tcid15->qcl_Type1.referenceSignal.choice.ssb = 7;
tcid15->qcl_Type1.qcl_Type=NR_QCL_Info__qcl_Type_typeC;
ASN_SEQUENCE_ADD(&bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToAddModList->list,tcid15);
+#endif
bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL;
- bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0;
+ bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL;
@@ -773,7 +760,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Dedicated->pdsch_Config->choice.setup->tci_StatesToReleaseList=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->vrb_ToPRB_Interleaver=NULL;
- bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType0;
+ bwp->bwp_Dedicated->pdsch_Config->choice.setup->resourceAllocation=NR_PDSCH_Config__resourceAllocation_resourceAllocationType1;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_TimeDomainAllocationList=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->pdsch_AggregationFactor=NULL;
bwp->bwp_Dedicated->pdsch_Config->choice.setup->rateMatchPatternToAddModList=NULL;
@@ -798,6 +785,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
bwp->bwp_Dedicated->pdsch_Config->choice.setup->p_ZP_CSI_RS_ResourceSet=NULL;
bwp->bwp_Dedicated->sps_Config = NULL; //calloc(1,sizeof(struct NR_SetupRelease_SPS_Config));
+ bwp->bwp_Dedicated->radioLinkMonitoringConfig = NULL;
+#if 0
bwp->bwp_Dedicated->radioLinkMonitoringConfig = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig));
bwp->bwp_Dedicated->radioLinkMonitoringConfig->present = NR_SetupRelease_RadioLinkMonitoringConfig_PR_setup;
@@ -808,6 +797,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureInstanceMaxCount = NR_RadioLinkMonitoringConfig__beamFailureInstanceMaxCount_n3;
bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = calloc(1,sizeof(*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer));
*bwp->bwp_Dedicated->radioLinkMonitoringConfig->choice.setup->beamFailureDetectionTimer = NR_RadioLinkMonitoringConfig__beamFailureDetectionTimer_pbfd2;
+#endif
ASN_SEQUENCE_ADD(&secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list,bwp);
@@ -816,6 +806,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
*secondaryCellGroup->spCellConfig->spCellConfigDedicated->firstActiveDownlinkBWP_Id=1;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->bwp_InactivityTimer = NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = NULL;
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = calloc(1, sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id));
+ *secondaryCellGroup->spCellConfig->spCellConfigDedicated->defaultDownlinkBWP_Id = 1;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig));
NR_BWP_UplinkDedicated_t *initialUplinkBWP = calloc(1,sizeof(*initialUplinkBWP));
@@ -833,7 +825,8 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup = calloc(1,sizeof(*pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup));
NR_DMRS_UplinkConfig_t *NR_DMRS_UplinkConfig = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup;
NR_DMRS_UplinkConfig->dmrs_Type = NULL;
- NR_DMRS_UplinkConfig->dmrs_AdditionalPosition =NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0;
+ NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = calloc(1,sizeof(*NR_DMRS_UplinkConfig->dmrs_AdditionalPosition));
+ *NR_DMRS_UplinkConfig->dmrs_AdditionalPosition = NR_DMRS_UplinkConfig__dmrs_AdditionalPosition_pos0;
NR_DMRS_UplinkConfig->phaseTrackingRS=NULL;
NR_DMRS_UplinkConfig->maxLength=NULL;
NR_DMRS_UplinkConfig->transformPrecodingDisabled = calloc(1,sizeof(*NR_DMRS_UplinkConfig->transformPrecodingDisabled));
@@ -924,7 +917,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
srs_res0->resourceMapping.repetitionFactor=NR_SRS_Resource__resourceMapping__repetitionFactor_n1;
srs_res0->freqDomainPosition=0;
srs_res0->freqDomainShift=0;
- srs_res0->freqHopping.c_SRS = 61;
+ srs_res0->freqHopping.c_SRS = 0;
srs_res0->freqHopping.b_SRS=0;
srs_res0->freqHopping.b_hop=0;
srs_res0->groupOrSequenceHopping=NR_SRS_Resource__groupOrSequenceHopping_neither;
@@ -1103,7 +1096,19 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id));
*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id = 1;
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = NULL;
+
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig = calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig));
+ NR_PUSCH_ServingCellConfig_t *pusch_scc = calloc(1,sizeof(*pusch_scc));
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->present = NR_SetupRelease_PUSCH_ServingCellConfig_PR_setup;
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->pusch_ServingCellConfig->choice.setup = pusch_scc;
+ pusch_scc->codeBlockGroupTransmission = NULL;
+ pusch_scc->rateMatching = NULL;
+ pusch_scc->xOverhead = NULL;
+ pusch_scc->ext1=calloc(1,sizeof(*pusch_scc->ext1));
+ pusch_scc->ext1->maxMIMO_Layers = calloc(1,sizeof(*pusch_scc->ext1->maxMIMO_Layers));
+ *pusch_scc->ext1->maxMIMO_Layers = 1;
+ pusch_scc->ext1->processingType2Enabled = NULL;
+
secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching = NULL;
secondaryCellGroup->spCellConfig->spCellConfigDedicated->supplementaryUplink=NULL;
@@ -1123,12 +1128,13 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
*pdsch_servingcellconfig->ext1->maxMIMO_Layers = 2;
pdsch_servingcellconfig->ext1->processingType2Enabled = NULL;
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig));
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup;
+ secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=NULL;
+ //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig=calloc(1,sizeof(*secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig));
+ //secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->present = NR_SetupRelease_CSI_MeasConfig_PR_setup;
NR_CSI_MeasConfig_t *csi_MeasConfig = calloc(1,sizeof(*csi_MeasConfig));
- secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig;
+// secondaryCellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup = csi_MeasConfig;
csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList = calloc(1,sizeof(*csi_MeasConfig->nzp_CSI_RS_ResourceToAddModList));
NR_NZP_CSI_RS_Resource_t *nzpres0 = calloc(1,sizeof(*nzpres0));
@@ -1668,7 +1674,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
imres0->csi_IM_ResourceElementPattern->choice.pattern1->symbolLocation_p1=7;
imres0->freqBand=calloc(1,sizeof(*imres0->freqBand));
imres0->freqBand->startingRB=0;
- imres0->freqBand->nrofRBs=276;
+ imres0->freqBand->nrofRBs=106;
imres0->periodicityAndOffset=calloc(1,sizeof(*imres0->periodicityAndOffset));
imres0->periodicityAndOffset->present = NR_CSI_ResourcePeriodicityAndOffset_PR_slots320;
imres0->periodicityAndOffset->choice.slots320 = 2;
@@ -1742,7 +1748,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires11->csi_RS_ResourceSetList.choice.csi_IM_ResourceSetList->list,csires110);
csires11->bwp_Id = 1;
csires11->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires11);
NR_CSI_ResourceConfig_t *csires10 = calloc(1,sizeof(*csires10));
csires10->csi_ResourceConfigId=10;
@@ -1755,7 +1761,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires10->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires100);
csires10->bwp_Id = 1;
csires10->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires10);
NR_CSI_ResourceConfig_t *csires2 = calloc(1,sizeof(*csires2));
csires2->csi_ResourceConfigId=2;
@@ -1768,7 +1774,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires2->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires20);
csires2->bwp_Id = 1;
csires2->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires2);
NR_CSI_ResourceConfig_t *csires3 = calloc(1,sizeof(*csires3));
csires3->csi_ResourceConfigId=3;
@@ -1781,7 +1787,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires3->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires30);
csires3->bwp_Id = 1;
csires3->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires3);
NR_CSI_ResourceConfig_t *csires4 = calloc(1,sizeof(*csires4));
csires4->csi_ResourceConfigId=4;
@@ -1794,7 +1800,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires4->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires40);
csires4->bwp_Id = 1;
csires4->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires4);
NR_CSI_ResourceConfig_t *csires5 = calloc(1,sizeof(*csires5));
csires5->csi_ResourceConfigId=5;
@@ -1807,7 +1813,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires5->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires50);
csires5->bwp_Id = 1;
csires5->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires5);
NR_CSI_ResourceConfig_t *csires6 = calloc(1,sizeof(*csires6));
csires6->csi_ResourceConfigId=6;
@@ -1820,7 +1826,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires6->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires60);
csires6->bwp_Id = 1;
csires6->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires6);
NR_CSI_ResourceConfig_t *csires7 = calloc(1,sizeof(*csires7));
csires7->csi_ResourceConfigId=7;
@@ -1833,7 +1839,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires7->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires70);
csires7->bwp_Id = 1;
csires7->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires7);
NR_CSI_ResourceConfig_t *csires8 = calloc(1,sizeof(*csires8));
csires8->csi_ResourceConfigId=8;
@@ -1846,7 +1852,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires8->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires80);
csires8->bwp_Id = 1;
csires8->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires8);
NR_CSI_ResourceConfig_t *csires9 = calloc(1,sizeof(*csires9));
csires9->csi_ResourceConfigId=9;
@@ -1859,7 +1865,7 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
ASN_SEQUENCE_ADD(&csires9->csi_RS_ResourceSetList.choice.nzp_CSI_RS_SSB->nzp_CSI_RS_ResourceSetList->list,csires90);
csires9->bwp_Id = 1;
csires9->resourceType = NR_CSI_ResourceConfig__resourceType_periodic;
- ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9);
+ //ASN_SEQUENCE_ADD(&csi_MeasConfig->csi_ResourceConfigToAddModList->list,csires9);
csi_MeasConfig->csi_ReportConfigToAddModList = calloc(1,sizeof(*csi_MeasConfig->csi_ReportConfigToAddModList));
csi_MeasConfig->csi_ReportConfigToReleaseList = NULL;
@@ -2005,30 +2011,26 @@ void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellco
}
void fill_default_reconfig(NR_ServingCellConfigCommon_t *servingcellconfigcommon,
- NR_RRCReconfiguration_IEs_t *reconfig,
- NR_CellGroupConfig_t *secondaryCellGroup,
- int n_physical_antenna_ports,
- int initial_csi_index) {
-
+ NR_RRCReconfiguration_IEs_t *reconfig,
+ NR_CellGroupConfig_t *secondaryCellGroup,
+ int n_physical_antenna_ports,
+ int initial_csi_index) {
AssertFatal(servingcellconfigcommon!=NULL,"servingcellconfigcommon is null\n");
AssertFatal(reconfig!=NULL,"reconfig is null\n");
AssertFatal(secondaryCellGroup!=NULL,"secondaryCellGroup is null\n");
-
// radioBearerConfig
reconfig->radioBearerConfig=NULL;
// secondaryCellGroup
- fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,0,0,n_physical_antenna_ports,initial_csi_index);
+ fill_default_secondaryCellGroup(servingcellconfigcommon,secondaryCellGroup,1,1,n_physical_antenna_ports,initial_csi_index);
xer_fprint(stdout, &asn_DEF_NR_CellGroupConfig, (const void*)secondaryCellGroup);
char scg_buffer[1024];
asn_enc_rval_t enc_rval = uper_encode_to_buffer(&asn_DEF_NR_CellGroupConfig, NULL, (void *)secondaryCellGroup, scg_buffer, 1024);
AssertFatal (enc_rval.encoded > 0, "ASN1 message encoding failed (%s, %jd)!\n", enc_rval.failed_type->name, enc_rval.encoded);
-
-
reconfig->secondaryCellGroup = calloc(1,sizeof(*reconfig->secondaryCellGroup));
OCTET_STRING_fromBuf(reconfig->secondaryCellGroup,
- (const char*)scg_buffer,
- (enc_rval.encoded+7)>>3);
+ (const char *)scg_buffer,
+ (enc_rval.encoded+7)>>3);
// measConfig
reconfig->measConfig=NULL;
// lateNonCriticalExtension
@@ -2060,15 +2062,15 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) {
drb_ToAddMod->pdcp_Config->drb->headerCompression.present = NR_PDCP_Config__drb__headerCompression_PR_notUsed;
drb_ToAddMod->pdcp_Config->drb->headerCompression.choice.notUsed = 0;
- drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL;
- drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL;
+ drb_ToAddMod->pdcp_Config->drb->integrityProtection=NULL;
+ drb_ToAddMod->pdcp_Config->drb->statusReportRequired=NULL;
drb_ToAddMod->pdcp_Config->drb->outOfOrderDelivery=NULL;
drb_ToAddMod->pdcp_Config->moreThanOneRLC = NULL;
drb_ToAddMod->pdcp_Config->t_Reordering = calloc(1,sizeof(*drb_ToAddMod->pdcp_Config->t_Reordering));
*drb_ToAddMod->pdcp_Config->t_Reordering = NR_PDCP_Config__t_Reordering_ms0;
drb_ToAddMod->pdcp_Config->ext1 = NULL;
-
+
ASN_SEQUENCE_ADD(&rbconfig->drb_ToAddModList->list,drb_ToAddMod);
rbconfig->drb_ToReleaseList = NULL;
@@ -2082,4 +2084,5 @@ void fill_default_rbconfig(NR_RadioBearerConfig_t *rbconfig) {
xer_fprint(stdout, &asn_DEF_NR_RadioBearerConfig, (const void*)rbconfig);
}
+
#endif
diff --git a/openair2/RRC/NR_UE/L2_interface_ue.c b/openair2/RRC/NR_UE/L2_interface_ue.c
index cb8ded1971d5952216582e277aaf6a0cc993a047..08976522b06217cd470fcc8139119558213e39d7 100644
--- a/openair2/RRC/NR_UE/L2_interface_ue.c
+++ b/openair2/RRC/NR_UE/L2_interface_ue.c
@@ -56,4 +56,15 @@ nr_mac_rrc_data_ind_ue(
return(0);
+}
+
+int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP,
+ const int CC_id,
+ const frame_t frameP,
+ const rb_id_t Srb_id,
+ uint8_t *const buffer_pP ){
+
+ // todo
+
+ return 0;
}
\ No newline at end of file
diff --git a/openair2/RRC/NR_UE/rrc_UE.c b/openair2/RRC/NR_UE/rrc_UE.c
index 87e899845e064cae155c0680de9c71e115ef3057..44215df2185ea3e42dcc62d030d434fc3257a043 100755
--- a/openair2/RRC/NR_UE/rrc_UE.c
+++ b/openair2/RRC/NR_UE/rrc_UE.c
@@ -42,7 +42,7 @@
#include "rrc_defs.h"
#include "rrc_proto.h"
#include "rrc_vars.h"
-#include "mac_proto.h"
+#include "LAYER2/NR_MAC_UE/mac_proto.h"
#include "executables/softmodem-common.h"
@@ -319,7 +319,7 @@ NR_UE_RRC_INST_t* openair_rrc_top_init_ue_nr(char* rrc_config_path){
RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ResourceConfig_list, NR_maxNrofCSI_ResourceConfigurations);
RRC_LIST_INIT(NR_UE_rrc_inst->CSI_ReportConfig_list, NR_maxNrofCSI_ReportConfigurations);
- if (get_softmodem_params()->phy_test==1) {
+ if (get_softmodem_params()->phy_test==1 || get_softmodem_params()->do_ra==1) {
// read in files for RRCReconfiguration and RBconfig
FILE *fd;
char filename[1024];
diff --git a/openair2/RRC/NR_UE/rrc_defs.h b/openair2/RRC/NR_UE/rrc_defs.h
index cb1207757dc5618ebc14779a8d6bfd62c18bd026..6481fb0cea266492f0d35ef86f40f0e7769feb05 100644
--- a/openair2/RRC/NR_UE/rrc_defs.h
+++ b/openair2/RRC/NR_UE/rrc_defs.h
@@ -39,8 +39,8 @@
#include "platform_types.h"
-#include "LAYER2/NR_MAC_UE/mac.h"
-#include "LAYER2/NR_MAC_COMMON/nr_mac.h"
+#include "NR_MAC_UE/mac.h"
+#include "NR_MAC_COMMON/nr_mac.h"
#include "rrc_list.h"
#include "NR_asn_constant.h"
#include "NR_MeasConfig.h"
diff --git a/openair2/RRC/NR_UE/rrc_proto.h b/openair2/RRC/NR_UE/rrc_proto.h
index 6e0d0a10deaef8c35afb09cd3fec8182ed9929b1..7bc7e4b90ceade782d5e58ef672f37bd374865d8 100644
--- a/openair2/RRC/NR_UE/rrc_proto.h
+++ b/openair2/RRC/NR_UE/rrc_proto.h
@@ -102,6 +102,18 @@ int8_t nr_rrc_ue_decode_NR_DL_DCCH_Message(const module_id_t module_id, const ui
\param pdu_len data length of pdu*/
int8_t nr_mac_rrc_data_ind_ue(const module_id_t module_id, const int CC_id, const uint8_t gNB_index, const channel_t channel, const uint8_t* pduP, const sdu_size_t pdu_len);
+/**\brief
+ \param module_id module id
+ \param CC_id component carrier id
+ \param frame_t frameP
+ \param rb_id_t SRB id
+ \param buffer_pP pointer to buffer*/
+int8_t mac_rrc_nr_data_req_ue(const module_id_t Mod_idP,
+ const int CC_id,
+ const frame_t frameP,
+ const rb_id_t Srb_id,
+ uint8_t *const buffer_pP);
+
/** @}*/
#endif
diff --git a/openair2/UTIL/OCG/OCG_if.h b/openair2/UTIL/OCG/OCG_if.h
index c515d9746dfbbf11d0769a597869f0d07dc091e1..cc55b56f36cd59618c17bb7cb1db1f5053fe660e 100644
--- a/openair2/UTIL/OCG/OCG_if.h
+++ b/openair2/UTIL/OCG/OCG_if.h
@@ -30,8 +30,8 @@
* \warning
*/
-#ifndef __CONFIGEN_IF_H__
-#define __CONFIG_IF_H__
+#ifndef __UTIL_OCG_OCG_IF__H__
+#define __UTIL_OCG_OCG_IF__H__
#ifdef __cplusplus
extern "C" {
diff --git a/openair2/UTIL/OPT/mac_pcap.h b/openair2/UTIL/OPT/mac_pcap.h
index 48b31bb3c07395b2b0d6382166356f717706d9d0..3141d17d5923a69f8a4735ce380cf55bbb985168 100644
--- a/openair2/UTIL/OPT/mac_pcap.h
+++ b/openair2/UTIL/OPT/mac_pcap.h
@@ -1,3 +1,6 @@
+#ifndef __UTIL_OPT_MAC_PCAP__H__
+#define __UTIL_OPT_MAC_PCAP__H__
+
#include <stdio.h>
#include <string.h>
#include <arpa/inet.h>
@@ -42,4 +45,4 @@ typedef struct MAC_Context_Info_t {
unsigned int subframesSinceCaptureStart;
} MAC_Context_Info_t;
-
+#endif
diff --git a/openair2/UTIL/OPT/opt.h b/openair2/UTIL/OPT/opt.h
index 86f1a045d853f107afbc9bba6237f5596c3bf424..6861e09cb17259d217c5fc08744b847130d317ec 100644
--- a/openair2/UTIL/OPT/opt.h
+++ b/openair2/UTIL/OPT/opt.h
@@ -88,16 +88,12 @@ typedef guint8 gboolean;
{ .s5= {NULL }} , \
}
-#ifdef OCP_FRAMEWORK
-#include <enums.h>
-#else
typedef enum trace_mode_e {
OPT_WIRESHARK,
OPT_PCAP,
OPT_TSHARK,
OPT_NONE
} trace_mode_t;
-#endif
typedef enum radio_type_e {
RADIO_TYPE_FDD = 1,
diff --git a/openair2/UTIL/OPT/packet-mac-lte.h b/openair2/UTIL/OPT/packet-mac-lte.h
index 4dfbe7912ec484a174567cac076d70627550ebe4..2d36e02df4d580af33f9fa5423dc984480f2d47f 100644
--- a/openair2/UTIL/OPT/packet-mac-lte.h
+++ b/openair2/UTIL/OPT/packet-mac-lte.h
@@ -22,6 +22,8 @@
modified to be used in OpenAir to create the LTE MAC/RLC encapsulated in UDP as per Wireshark feature
*/
+#ifndef __UTIL_OPT_PACKET_MAC_LTE__H__
+#define __UTIL_OPT_PACKET_MAC_LTE__H__
#include "ws_symbol_export.h"
@@ -376,3 +378,5 @@ typedef enum {
* vi: set shiftwidth=4 tabstop=8 expandtab:
* :indentSize=4:tabSize=8:noTabs=true:
*/
+
+#endif
diff --git a/openair2/UTIL/OSA/osa_defs.h b/openair2/UTIL/OSA/osa_defs.h
index 4812d82d9166a12b2bc14e242b05071e7e910754..3df350541f0e7d38e4cd81fb4ad08b39ae6558ef 100644
--- a/openair2/UTIL/OSA/osa_defs.h
+++ b/openair2/UTIL/OSA/osa_defs.h
@@ -29,8 +29,8 @@
* @ingroup security
*/
-#ifndef SECU_DEFS_H_
-#define SECU_DEFS_H_
+#ifndef __UTIL_OSA_OSA_DEFS__H__
+#define __UTIL_OSA_OSA_DEFS__H__
#define EIA0_ALG_ID 0x00
#define EIA1_128_ALG_ID 0x01
@@ -115,4 +115,4 @@ int stream_decrypt(uint8_t algorithm, stream_cipher_t *stream_cipher, uint8_t **
int stream_check_integrity(uint8_t algorithm, stream_cipher_t *stream_cipher, uint8_t *expected);
#undef SECU_DEBUG
-#endif /* SECU_DEFS_H_ */
+#endif /* __UTIL_OSA_OSA_DEFS__H__ */
diff --git a/openair2/UTIL/OTG/traffic_config.h b/openair2/UTIL/OTG/traffic_config.h
index 2f47682706bed8aa258e1c637dcbb12e03218d1b..c0a64a34650bfc3dd309a309200d5f7f08689eff 100644
--- a/openair2/UTIL/OTG/traffic_config.h
+++ b/openair2/UTIL/OTG/traffic_config.h
@@ -19,6 +19,9 @@
* contact@openairinterface.org
*/
+#ifndef __UTIL_OTG_TRAFFIC_CONFIG__H__
+#define __UTIL_OTG_TRAFFIC_CONFIG__H__
+
//IDT DISTRIBUTION PARAMETERS
#define IDT_DIST GAUSSIAN
#define IDT_MIN 2
@@ -40,3 +43,5 @@
//SOCKET MODE
#define DST_PORT 1234;
#define DST_IP "127.0.0.1"
+
+#endif
diff --git a/openair2/X2AP/x2ap_eNB.c b/openair2/X2AP/x2ap_eNB.c
index b297c96e569935e0404d44f74fe98de63e4022f2..bd7727274705b92da83d6c99a00953eaddd4a011 100644
--- a/openair2/X2AP/x2ap_eNB.c
+++ b/openair2/X2AP/x2ap_eNB.c
@@ -116,7 +116,9 @@ void x2ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_associa
/* some sanity check - to be refined at some point */
if (sctp_new_association_resp->sctp_state != SCTP_STATE_ESTABLISHED) {
X2AP_ERROR("x2ap_enb_data_p not NULL and sctp state not SCTP_STATE_ESTABLISHED, what to do?\n");
- abort();
+ // Allow for a gracious exit when we kill first the gNB, then the eNB
+ //abort();
+ return;
}
x2ap_enb_data_p->in_streams = sctp_new_association_resp->in_streams;
@@ -454,10 +456,12 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance,
x2ap_eNB_instance_t *instance_p;
x2ap_eNB_data_t *x2ap_eNB_data;
int ue_id;
-
- /* TODO: remove hardcoded value */
- x2ap_eNB_data = x2ap_is_eNB_id_in_list(3584);
+ LTE_PhysCellId_t target_pci;
+ target_pci = x2ap_ENDC_sgnb_addition_req->target_physCellId;
+ x2ap_eNB_data = x2ap_is_eNB_pci_in_list(target_pci);
DevAssert(x2ap_eNB_data != NULL);
+ DevAssert(x2ap_ENDC_sgnb_addition_req != NULL);
+
instance_p = x2ap_eNB_get_instance(instance);
DevAssert(instance_p != NULL);
@@ -474,7 +478,8 @@ void x2ap_eNB_handle_sgNB_add_req(instance_t instance,
x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req->rnti, ue_id, -1);
x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_NSA_PREPARE);
- x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_eNB_data, ue_id);
+ x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(instance_p, x2ap_ENDC_sgnb_addition_req,
+ x2ap_eNB_data, ue_id);
}
static
@@ -489,16 +494,31 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance,
* as far as I understand.. CROUX
*/
-
+ x2ap_id_manager *id_manager;
x2ap_eNB_instance_t *instance_p;
x2ap_eNB_data_t *target;
- /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id;
int ue_id;
+ /*int source_assoc_id = x2ap_ENDC_sgnb_addition_req_ACK->source_assoc_id;
int id_source;
int id_target;*/
instance_p = x2ap_eNB_get_instance(instance);
DevAssert(instance_p != NULL);
+ target = x2ap_get_eNB(NULL,x2ap_ENDC_sgnb_addition_req_ACK->target_assoc_id, 0);
+ DevAssert(target != NULL);
+
+ /* allocate x2ap ID */
+ id_manager = &instance_p->id_manager;
+ ue_id = x2ap_allocate_new_id(id_manager);
+ if (ue_id == -1) {
+ X2AP_ERROR("could not allocate a new X2AP UE ID\n");
+ exit(1);
+ }
+ /* id_source is ue_id, id_target is unknown yet */
+ x2ap_set_ids(id_manager, ue_id, x2ap_ENDC_sgnb_addition_req_ACK->rnti, ue_id,
+ x2ap_ENDC_sgnb_addition_req_ACK->MeNB_ue_x2_id);
+ x2ap_id_set_state(id_manager, ue_id, X2ID_STATE_SOURCE_OVERALL);
+
/*target = x2ap_get_eNB(NULL, source_assoc_id, 0);
DevAssert(target != NULL);*/
@@ -511,10 +531,36 @@ void x2ap_gNB_trigger_sgNB_add_req_ack(instance_t instance,
x2ap_set_ids(&instance_p->id_manager, ue_id, x2ap_handover_req_ack->rnti, id_source, id_target);*/
- //target = x2ap_get_eNB(NULL, 17, 0);
- target = x2ap_is_eNB_id_in_list (3585); //Currently hardcoded. Need to extract it differently
+ x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target,
+ x2ap_ENDC_sgnb_addition_req_ACK, ue_id);
+}
+
+/**
+ * @fn : Function triggers sgnb reconfiguration complete
+ * @param : IN instance, IN x2ap_reconf_complete
+**/
+static
+void x2ap_eNB_trigger_sgnb_reconfiguration_complete(instance_t instance,
+ x2ap_ENDC_reconf_complete_t *x2ap_reconf_complete)
+{
+ x2ap_eNB_instance_t *instance_p = NULL;
+ x2ap_eNB_data_t *target = NULL;
+ int id_source = -1;
+ int id_target = -1;
+ LTE_PhysCellId_t target_pci;
+
+ instance_p = x2ap_eNB_get_instance(instance);
+ DevAssert(instance_p != NULL);
+ DevAssert(x2ap_reconf_complete != NULL);
+
+ target_pci = x2ap_reconf_complete->target_physCellId;
+ target = x2ap_is_eNB_pci_in_list(target_pci);
DevAssert(target != NULL);
- x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK(instance_p, target, x2ap_ENDC_sgnb_addition_req_ACK, 0);
+
+ id_source = x2ap_reconf_complete->MeNB_ue_x2_id;
+ id_target = x2ap_reconf_complete->SgNB_ue_x2_id;
+ x2ap_eNB_generate_ENDC_x2_SgNB_reconfiguration_complete(instance_p, target, id_source, id_target);
+
}
@@ -594,6 +640,10 @@ void *x2ap_task(void *arg) {
LOG_I(X2AP, "Received elements for X2AP_ENDC_SGNB_ADDITION_REQ_ACK \n");
break;
+ case X2AP_ENDC_SGNB_RECONF_COMPLETE:
+ x2ap_eNB_trigger_sgnb_reconfiguration_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg),
+ &X2AP_ENDC_SGNB_RECONF_COMPLETE(received_msg));
+ break;
case SCTP_INIT_MSG_MULTI_CNF:
x2ap_eNB_handle_sctp_init_msg_multi_cnf(ITTI_MESSAGE_GET_INSTANCE(received_msg),
&received_msg->ittiMsg.sctp_init_msg_multi_cnf);
diff --git a/openair2/X2AP/x2ap_eNB_decoder.c b/openair2/X2AP/x2ap_eNB_decoder.c
index 93b82c2765fb985c414557f11cdd0f3edec76034..3762bc06dcc6bcdddcd1247d197ae57f753e2317 100644
--- a/openair2/X2AP/x2ap_eNB_decoder.c
+++ b/openair2/X2AP/x2ap_eNB_decoder.c
@@ -144,9 +144,9 @@ int x2ap_eNB_decode_pdu(X2AP_X2AP_PDU_t *pdu, const uint8_t *const buffer, uint3
length,
0,
0);
- //if (asn1_xer_print) {
+ if (asn1_xer_print) {
xer_fprint(stdout, &asn_DEF_X2AP_X2AP_PDU, pdu);
- //}
+ }
if (dec_ret.code != RC_OK) {
X2AP_ERROR("Failed to decode pdu\n");
diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.c b/openair2/X2AP/x2ap_eNB_generate_messages.c
index 0aeabce0d2cfcaa3bc545fc2ef2321cf46632b22..a96fa14f48e037f46ff460e2c3f67581dfcc2a80 100644
--- a/openair2/X2AP/x2ap_eNB_generate_messages.c
+++ b/openair2/X2AP/x2ap_eNB_generate_messages.c
@@ -1496,7 +1496,8 @@ int x2ap_eNB_generate_ENDC_x2_setup_response(
}
int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(
- x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id)
+ x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req,
+ x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id)
{
X2AP_X2AP_PDU_t pdu;
X2AP_SgNBAdditionRequest_t *out;
@@ -1507,44 +1508,21 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(
uint8_t *buffer;
uint32_t len;
int ret = 0;
-
- // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted
- // with values coming from RRC.
- uint16_t nRencryptionAlgorithms = 0;
- uint16_t nRintegrityProtectionAlgorithms = 0;
+ uint16_t nRencryptionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities.encryption_algorithms;
+ uint16_t nRintegrityProtectionAlgorithms = x2ap_ENDC_sgnb_addition_req->security_capabilities
+ .integrity_algorithms;
uint8_t SgNBSecurityKey[32] = { 0 };
- int uEaggregateMaximumBitRateDownlink = 100000000;
- int uEaggregateMaximumBitRateUplink = 100000000;
- int e_rabs_tobeadded = 1;
- int e_RAB_ID = 1;
- int drb_ID = 2;
+ int uEaggregateMaximumBitRateDownlink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_dl;
+ int uEaggregateMaximumBitRateUplink = x2ap_ENDC_sgnb_addition_req->ue_ambr.br_ul;
+ int e_rabs_tobeadded = x2ap_ENDC_sgnb_addition_req->nb_e_rabs_tobeadded;
long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present;
long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present;
long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present;
- long qCI = 1;
- X2AP_Pre_emptionCapability_t pre_emptionCapability = X2AP_Pre_emptionCapability_shall_not_trigger_pre_emption;
- X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability = X2AP_Pre_emptionVulnerability_not_pre_emptable;
- priority_level_t priority_level = PRIORITY_LEVEL_NO_PRIORITY;
- e_rab_tobe_added_t e_MCG_rabs_tobeadded;
- e_MCG_rabs_tobeadded.gtp_teid = 0;
- e_MCG_rabs_tobeadded.eNB_addr.length = 24;
- uint8_t buf[20] = { 0 };
- memcpy(e_MCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t));
-
- FILE *fd;
- fd = fopen("../../../executables/uecap.raw","r");
- if (fd != NULL) {
- OCTET_STRING_t CG_Config_Info;
- CG_Config_Info.size = 4096;
- CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));
- int msg_len=fread(CG_Config_Info.buf,1,CG_Config_Info.size,fd);
- CG_Config_Info.size = msg_len;
-
- /*char buffer[4096];
- int msg_len=fread(buffer,1,4096,fd);*/
- LOG_I(RRC,"Read in %d bytes for uecap\n",msg_len);
-
-
+ long qCI = 0;
+ X2AP_Pre_emptionCapability_t pre_emptionCapability;
+ X2AP_Pre_emptionVulnerability_t pre_emptionVulnerability;
+ priority_level_t priority_level;
+ memcpy(SgNBSecurityKey, x2ap_ENDC_sgnb_addition_req->kgnb, sizeof(x2ap_ENDC_sgnb_addition_req->kgnb));
/*OCTET_STRING_t CG_Config_Info;
CG_Config_Info.size = 4096;
CG_Config_Info.buf = (uint8_t *)calloc(4096, sizeof(uint8_t));*/
@@ -1614,13 +1592,17 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(
e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_ItemIEs__value_PR_E_RABs_ToBeAdded_SgNBAddReq_Item;
e_RABS_ToBeAdded_SgNBAddReq_Item = &e_RABS_ToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_ToBeAdded_SgNBAddReq_Item;
{
- e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = drb_ID;
- e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID;
+ e_RABS_ToBeAdded_SgNBAddReq_Item->drb_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].drb_ID;
+ e_RABS_ToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].e_rab_id;
e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB;
e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources;
e_RABS_ToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources;
if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){
- e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent;
+ e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_ToBeAdded_SgNBAddReq_Item__resource_configuration_PR_sgNBPDCPpresent;
+ qCI = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.qci;
+ priority_level = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.priority_level;
+ pre_emptionCapability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability;
+ pre_emptionVulnerability = x2ap_ENDC_sgnb_addition_req->e_rab_param[i].qos.allocation_retention_priority.pre_emp_vulnerability;
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.qCI = qCI;
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability = pre_emptionCapability;
@@ -1628,14 +1610,14 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel = priority_level;
//Continue from filling the UL_GTPtunnelEndpointInformation inspired from how it is done for the HO case
- INT32_TO_OCTET_STRING(e_MCG_rabs_tobeadded.gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID);
- e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = e_MCG_rabs_tobeadded.eNB_addr.length/8;
- e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_MCG_rabs_tobeadded.eNB_addr.length%8;
+ INT32_TO_OCTET_STRING(x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].gtp_teid, &e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID);
+ e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length/8;
+ e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.length%8;
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf =
calloc(1, e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size);
memcpy (e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf,
- e_MCG_rabs_tobeadded.eNB_addr.buffer,
+ x2ap_ENDC_sgnb_addition_req->e_rabs_tobeadded[i].sgw_addr.buffer,
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size);
}
@@ -1648,25 +1630,24 @@ int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request(
ie->id = X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer;
ie->criticality = X2AP_Criticality_reject;
ie->value.present = X2AP_SgNBAdditionRequest_IEs__value_PR_MeNBtoSgNBContainer;
- ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)calloc(CG_Config_Info.size, sizeof(uint8_t));
- memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, CG_Config_Info.buf, CG_Config_Info.size);
- ie->value.choice.MeNBtoSgNBContainer.size = CG_Config_Info.size; //4096;
+ if(NULL == (ie->value.choice.MeNBtoSgNBContainer.buf = (uint8_t *)
+ calloc(x2ap_ENDC_sgnb_addition_req->rrc_buffer_size, sizeof(uint8_t)))) {
+ X2AP_ERROR("Memory ALLocation failed\n");
+ exit(1);
+ }
+ memcpy(ie->value.choice.MeNBtoSgNBContainer.buf, x2ap_ENDC_sgnb_addition_req->rrc_buffer,
+ x2ap_ENDC_sgnb_addition_req->rrc_buffer_size);
+ ie->value.choice.MeNBtoSgNBContainer.size = x2ap_ENDC_sgnb_addition_req->rrc_buffer_size;
ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
if (x2ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) {
X2AP_ERROR("Failed to encode ENDC X2 SgNB_addition request message\n");
return -1;
}
-
+ free(ie->value.choice.MeNBtoSgNBContainer.buf);
MSC_LOG_TX_MESSAGE (MSC_X2AP_SRC_ENB, MSC_X2AP_TARGET_ENB, NULL, 0, "0 X2Setup/initiatingMessage assoc_id %u", x2ap_eNB_data_p->assoc_id);
x2ap_eNB_itti_send_sctp_data_req(instance_p->instance, x2ap_eNB_data_p->assoc_id, buffer, len, 0);
- fclose(fd);
- }
- else {
- LOG_I(RRC, "uecap.raw file could not be opened... \n");
- return -1;
- }
return ret;
@@ -1686,26 +1667,14 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in
uint8_t *buffer;
uint32_t len;
int ret = 0;
- int MeNB_UE_X2AP_id = ue_id;
- int SgNB_UE_X2AP_id = 0;
-
- // Currently hardcoded (dummy) values filling the fields of SgNB_addition_request message. To be substituted
- // with values coming from RRC.
- //uint16_t nRencryptionAlgorithms = 0;
- //uint16_t nRintegrityProtectionAlgorithms = 0;
- //uint8_t SgNBSecurityKey[32] = { 0 };
- //int uEaggregateMaximumBitRateDownlink = 100000000;
- //int uEaggregateMaximumBitRateUplink = 100000000;
- int e_rabs_admitted_tobeadded = 1;
- int e_RAB_ID = 1;
+
+ int MeNB_UE_X2AP_id = x2ap_sgnb_addition_req_ACK->MeNB_ue_x2_id;
+ int SgNB_UE_X2AP_id = ue_id;
+ int e_rabs_admitted_tobeadded = x2ap_sgnb_addition_req_ACK->nb_e_rabs_admitted_tobeadded;
long int pDCPatSgNB = X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present;
long int mCGresources = X2AP_EN_DC_ResourceConfiguration__mCGresources_not_present;
long int sCGresources = X2AP_EN_DC_ResourceConfiguration__sCGresources_not_present;
- e_rab_setup_t e_SCG_rabs_tobeadded;
- e_SCG_rabs_tobeadded.gtp_teid = 0;
- e_SCG_rabs_tobeadded.eNB_addr.length = 24;
- uint8_t buf[20] = { 0 };
- memcpy(e_SCG_rabs_tobeadded.eNB_addr.buffer, buf, 20*sizeof(uint8_t));
+
DevAssert(instance_p != NULL);
DevAssert(x2ap_eNB_data_p != NULL);
@@ -1748,21 +1717,21 @@ int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *in
e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_ItemIEs__value_PR_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item;
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item = &e_RABS_AdmittedToBeAdded_SgNBAddReq_ItemIEs->value.choice.E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item;
{
- e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = e_RAB_ID;
+ e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->e_RAB_ID = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].e_rab_id;
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.pDCPatSgNB = pDCPatSgNB;
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.mCGresources = mCGresources;
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->en_DC_ResourceConfiguration.sCGresources = sCGresources;
if (pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.present = X2AP_E_RABs_Admitted_ToBeAdded_SgNBAddReqAck_Item__resource_configuration_PR_sgNBPDCPpresent;
- INT32_TO_OCTET_STRING(e_SCG_rabs_tobeadded.gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID);
- e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = e_SCG_rabs_tobeadded.eNB_addr.length/8;
- e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = e_SCG_rabs_tobeadded.eNB_addr.length%8;
+ INT32_TO_OCTET_STRING(x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gtp_teid, &e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID);
+ e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length/8;
+ e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused = x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.length%8;
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf =
calloc(1, e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size);
memcpy (e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf,
- e_SCG_rabs_tobeadded.eNB_addr.buffer,
+ x2ap_sgnb_addition_req_ACK->e_rabs_admitted_tobeadded[i].gnb_addr.buffer,
e_RABS_AdmittedToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size);
}
diff --git a/openair2/X2AP/x2ap_eNB_generate_messages.h b/openair2/X2AP/x2ap_eNB_generate_messages.h
index 114ed84a686b87712f2317bd39144ff79fa2579a..3dfccc0e5201490a922d13bdc726fc3c8eee13f5 100644
--- a/openair2/X2AP/x2ap_eNB_generate_messages.h
+++ b/openair2/X2AP/x2ap_eNB_generate_messages.h
@@ -70,7 +70,7 @@ int x2ap_gNB_generate_ENDC_x2_setup_request(x2ap_eNB_instance_t *instance_p, x2a
int x2ap_eNB_generate_ENDC_x2_setup_response( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p);
-int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id);
+int x2ap_eNB_generate_ENDC_x2_SgNB_addition_request( x2ap_eNB_instance_t *instance_p, x2ap_ENDC_sgnb_addition_req_t *x2ap_ENDC_sgnb_addition_req, x2ap_eNB_data_t *x2ap_eNB_data_p, int ue_id);
int x2ap_gNB_generate_ENDC_x2_SgNB_addition_request_ACK( x2ap_eNB_instance_t *instance_p, x2ap_eNB_data_t *x2ap_eNB_data_p, x2ap_ENDC_sgnb_addition_req_ACK_t *x2ap_sgnb_addition_req_ACK, int ue_id);
diff --git a/openair2/X2AP/x2ap_eNB_handler.c b/openair2/X2AP/x2ap_eNB_handler.c
index afaae1756d49b443733bdb02d95f0f1b9ee85d0f..1c6c98cd81ec27dd43321de86f6058d7bd88fe3f 100644
--- a/openair2/X2AP/x2ap_eNB_handler.c
+++ b/openair2/X2AP/x2ap_eNB_handler.c
@@ -1652,7 +1652,6 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance,
x2ap_eNB_instance_t *instance_p;
x2ap_eNB_data_t *x2ap_eNB_data;
MessageDef *msg;
- int ue_id;
DevAssert (pdu != NULL);
x2SgNBAdditionRequest = &pdu->choice.initiatingMessage.value.choice.SgNBAdditionRequest;
@@ -1683,20 +1682,9 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance,
X2AP_ERROR("%s %d: ie is a NULL pointer \n",__FILE__,__LINE__);
return -1;
}
-
-
- // allocate a new X2AP UE ID
- ue_id = x2ap_allocate_new_id(&instance_p->id_manager);
- if (ue_id == -1) {
- X2AP_ERROR("could not allocate a new X2AP UE ID\n");
- // TODO: cancel handover: send HO preparation failure to source eNB
- exit(1);
- }
- // rnti is unknown yet, must not be set to -1, 0 is fine
- x2ap_set_ids(&instance_p->id_manager, ue_id, 0, ie->value.choice.UE_X2AP_ID, ue_id);
- x2ap_id_set_state(&instance_p->id_manager, ue_id, X2ID_STATE_TARGET);
-
- X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ue_id;
+ /* ue_x2_id = MeNB X2AP Id */
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).ue_x2_id = ie->value.choice.UE_X2AP_ID;
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).target_assoc_id = assoc_id;
/* X2AP_ProtocolIE_ID_id_NRUESecurityCapabilities */
@@ -1749,13 +1737,22 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance,
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.pre_emp_capability = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.pre_emptionCapability;
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rab_param[i].qos.allocation_retention_priority.priority_level = e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.full_E_RAB_Level_QoS_Parameters.allocationAndRetentionPriority.priorityLevel;
- memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.buffer,
+ memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer,
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.buf,
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size);
- X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].eNB_addr.length =
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length =
e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.transportLayerAddress.bits_unused;
+LOG_I(RRC,"x2u tunnel: index %d target sgw ip %d.%d.%d.%d length %d gtp teid %u\n",
+ i,
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[0],
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[1],
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[2],
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.buffer[3],
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].sgw_addr.length,
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid);
+
OCTET_STRING_TO_INT32(&e_RABS_ToBeAdded_SgNBAddReq_Item->resource_configuration.choice.sgNBPDCPpresent.s1_UL_GTPtunnelEndpoint.gTP_TEID,
X2AP_ENDC_SGNB_ADDITION_REQ(msg).e_rabs_tobeadded[i].gtp_teid);
}
@@ -1771,13 +1768,11 @@ int x2ap_gNB_handle_ENDC_sGNB_addition_request (instance_t instance,
X2AP_FIND_PROTOCOLIE_BY_ID(X2AP_SgNBAdditionRequest_IEs_t, ie, x2SgNBAdditionRequest,
X2AP_ProtocolIE_ID_id_MeNBtoSgNBContainer, true);
- X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer;
- //X2AP_MeNBtoSgNBContainer_t *container = &ie->value.choice.MeNBtoSgNBContainer;
- if (container->size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s
- { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); }
+ if (ie->value.choice.MeNBtoSgNBContainer.size > 8192 ) // TODO: this is the size of rrc_buffer in struct x2ap_handover_req_s
+ { printf("%s:%d: fatal: buffer too big\n", __FILE__, __LINE__); abort(); }
- memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size);
- X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size;
+ memcpy(X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer, ie->value.choice.MeNBtoSgNBContainer.buf, ie->value.choice.MeNBtoSgNBContainer.size);
+ X2AP_ENDC_SGNB_ADDITION_REQ(msg).rrc_buffer_size = ie->value.choice.MeNBtoSgNBContainer.size;
itti_send_msg_to_task(TASK_RRC_GNB, instance_p->instance, msg);
@@ -1891,10 +1886,10 @@ int x2ap_eNB_handle_ENDC_sGNB_addition_response (instance_t instance,
X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].e_rab_id = e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->e_RAB_ID ;
if(e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->en_DC_ResourceConfiguration.pDCPatSgNB == X2AP_EN_DC_ResourceConfiguration__pDCPatSgNB_present){
- memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.buffer,
+ memcpy(X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.buffer,
e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.buf,
e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size);
- X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].eNB_addr.length =
+ X2AP_ENDC_SGNB_ADDITION_REQ_ACK(msg).e_rabs_admitted_tobeadded[i].gnb_addr.length =
e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.size * 8 - e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.transportLayerAddress.bits_unused;
OCTET_STRING_TO_INT32(&e_RABS_Admitted_ToBeAdded_SgNBAddReqAck_Item->resource_configuration.choice.sgNBPDCPpresent.s1_DL_GTPtunnelEndpoint.gTP_TEID,
@@ -1963,7 +1958,7 @@ int x2ap_gNB_handle_ENDC_sGNB_reconfiguration_complete (instance_t instance,
instance_p = x2ap_eNB_get_instance(instance);
DevAssert(instance_p != NULL);
- //Allocate an ITTI X2AP_SGNB_ADDITION_REQ message instead
+ //Allocate an ITTI X2AP_sGNB_reconfiguration_complete message
msg = itti_alloc_new_message(TASK_X2AP, X2AP_ENDC_SGNB_RECONF_COMPLETE);
/* X2AP_ProtocolIE_ID_id_MeNB_UE_X2AP_ID */
diff --git a/openair2/X2AP/x2ap_eNB_management_procedures.h b/openair2/X2AP/x2ap_eNB_management_procedures.h
index c5217341c514818f8abe81231cfd9b9600e03821..7082f5ac95bc4cbdb37522d3f898fee29c7189b5 100644
--- a/openair2/X2AP/x2ap_eNB_management_procedures.h
+++ b/openair2/X2AP/x2ap_eNB_management_procedures.h
@@ -26,8 +26,8 @@
* \version 1.0
*/
-#ifndef X2AP_ENB_MANAGEMENT_PROCEDURES_H_
-#define X2AP_ENB_MANAGEMENT_PROCEDURES_H
+#ifndef __X2AP_ENB_MANAGEMENT_PROCEDURES__H__
+#define __X2AP_ENB_MANAGEMENT_PROCEDURES__H__
void x2ap_eNB_prepare_internal_data(void);
@@ -51,4 +51,4 @@ struct x2ap_eNB_data_s *x2ap_get_eNB(x2ap_eNB_instance_t *instance_p,
int32_t assoc_id,
uint16_t cnx_id);
-#endif /* X2AP_ENB_MANAGEMENT_PROCEDURES_H_ */
+#endif /* __X2AP_ENB_MANAGEMENT_PROCEDURES__H__ */
diff --git a/openair3/GTPV1-U/gtpv1u_eNB.c b/openair3/GTPV1-U/gtpv1u_eNB.c
index f15f295548e9e4a474479f12501df1a99ad3ef75..f095cce67de0b4be01ef56a211e6da46f649ad4a 100644
--- a/openair3/GTPV1-U/gtpv1u_eNB.c
+++ b/openair3/GTPV1-U/gtpv1u_eNB.c
@@ -943,6 +943,8 @@ gtpv1u_create_s1u_tunnel(
memcpy(&create_tunnel_resp_pP->enb_addr.buffer,
&RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up,
sizeof (in_addr_t));
+
+ LOG_I(GTPU,"Configured GTPu address : %x\n",RC.gtpv1u_data_g->enb_ip_address_for_S1u_S12_S4_up);
create_tunnel_resp_pP->enb_addr.length = sizeof (in_addr_t);
addrs_length_in_bytes = create_tunnel_req_pP->sgw_addr[i].length / 8;
AssertFatal((addrs_length_in_bytes == 4) ||
@@ -971,6 +973,15 @@ gtpv1u_create_s1u_tunnel(
gtpv1u_ue_data_p->bearers[eps_bearer_id - GTPV1U_BEARER_OFFSET].teid_sgw = create_tunnel_req_pP->sgw_S1u_teid[i];
gtpv1u_ue_data_p->num_bearers++;
create_tunnel_resp_pP->enb_S1u_teid[i] = s1u_teid;
+
+ LOG_I(GTPU,"Copied to create_tunnel_resp tunnel: index %d target gNB ip %d.%d.%d.%d length %d gtp teid %u\n",
+ i,
+ create_tunnel_resp_pP->enb_addr.buffer[0],
+ create_tunnel_resp_pP->enb_addr.buffer[1],
+ create_tunnel_resp_pP->enb_addr.buffer[2],
+ create_tunnel_resp_pP->enb_addr.buffer[3],
+ create_tunnel_resp_pP->enb_addr.length,
+ create_tunnel_resp_pP->enb_S1u_teid[i]);
} else {
create_tunnel_resp_pP->enb_S1u_teid[i] = 0;
create_tunnel_resp_pP->status = 0xFF;
diff --git a/openair3/GTPV1-U/gtpv1u_gNB.c b/openair3/GTPV1-U/gtpv1u_gNB.c
new file mode 100644
index 0000000000000000000000000000000000000000..f13bf13794771324bf32123f84c25c06f5cf370d
--- /dev/null
+++ b/openair3/GTPV1-U/gtpv1u_gNB.c
@@ -0,0 +1,311 @@
+/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.
+ * The OpenAirInterface Software Alliance licenses this file to You under
+ * the OAI Public License, Version 1.1 (the "License"); you may not use this file
+ * except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.openairinterface.org/?page_id=698
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *-------------------------------------------------------------------------------
+ * For more information about the OpenAirInterface (OAI) Software Alliance:
+ * contact@openairinterface.org
+ */
+
+/*! \file gtpv1u_gNB.c
+ * \brief
+ * \author Sebastien ROUX, Lionel GAUTHIER, Navid Nikaein, Panos MATZAKOS
+ * \version 1.0
+ * \company Eurecom
+ * \email: lionel.gauthier@eurecom.fr
+ */
+#include <stdio.h>
+#include <errno.h>
+
+#include "mme_config.h"
+#include "intertask_interface.h"
+#include "msc.h"
+
+#include "gtpv1u.h"
+#include "NwGtpv1u.h"
+#include "NwGtpv1uMsg.h"
+#include "NwGtpv1uPrivate.h"
+#include "NwLog.h"
+#include "gtpv1u_eNB_defs.h"
+#include "gtpv1_u_messages_types.h"
+#include "udp_eNB_task.h"
+#include "common/utils/LOG/log.h"
+#include "COMMON/platform_types.h"
+#include "COMMON/platform_constants.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
+#include "common/ran_context.h"
+#include "gtpv1u_eNB_defs.h"
+#include "gtpv1u_eNB_task.h"
+#include "gtpv1u_gNB_task.h"
+#include "rrc_eNB_GTPV1U.h"
+
+#undef GTP_DUMP_SOCKET
+
+extern unsigned char NB_eNB_INST;
+
+extern RAN_CONTEXT_t RC;
+
+extern NwGtpv1uRcT gtpv1u_eNB_send_udp_msg(
+ NwGtpv1uUdpHandleT udpHandle,
+ uint8_t *buffer,
+ uint32_t buffer_len,
+ uint32_t buffer_offset,
+ uint32_t peerIpAddr,
+ uint16_t peerPort);
+
+extern NwGtpv1uRcT gtpv1u_eNB_log_request(NwGtpv1uLogMgrHandleT hLogMgr,
+ uint32_t logLevel,
+ NwCharT *file,
+ uint32_t line,
+ NwCharT *logStr);
+
+static NwGtpv1uRcT gtpv1u_start_timer_wrapper(
+ NwGtpv1uTimerMgrHandleT tmrMgrHandle,
+ uint32_t timeoutSec,
+ uint32_t timeoutUsec,
+ uint32_t tmrType,
+ void *timeoutArg,
+ NwGtpv1uTimerHandleT *hTmr) {
+ NwGtpv1uRcT rc = NW_GTPV1U_OK;
+ long timer_id;
+
+ if (tmrType == NW_GTPV1U_TMR_TYPE_ONE_SHOT) {
+ timer_setup(timeoutSec,
+ timeoutUsec,
+ TASK_GTPV1_U,
+ INSTANCE_DEFAULT,
+ TIMER_ONE_SHOT,
+ timeoutArg,
+ &timer_id);
+ } else {
+ timer_setup(timeoutSec,
+ timeoutUsec,
+ TASK_GTPV1_U,
+ INSTANCE_DEFAULT,
+ TIMER_PERIODIC,
+ timeoutArg,
+ &timer_id);
+ }
+
+ return rc;
+}
+
+
+static NwGtpv1uRcT
+gtpv1u_stop_timer_wrapper(
+ NwGtpv1uTimerMgrHandleT tmrMgrHandle,
+ NwGtpv1uTimerHandleT hTmr) {
+ NwGtpv1uRcT rc = NW_GTPV1U_OK;
+ return rc;
+}
+
+/* Callback called when a gtpv1u message arrived on UDP interface */
+NwGtpv1uRcT gtpv1u_gNB_process_stack_req(
+ NwGtpv1uUlpHandleT hUlp,
+ NwGtpv1uUlpApiT *pUlpApi) {
+ boolean_t result = FALSE;
+ teid_t teid = 0;
+ hashtable_rc_t hash_rc = HASH_TABLE_KEY_NOT_EXISTS;
+ gtpv1u_teid_data_t *gtpv1u_teid_data_p = NULL;
+ protocol_ctxt_t ctxt;
+ NwGtpv1uRcT rc;
+
+ switch(pUlpApi->apiType) {
+ /* Here there are two type of messages handled:
+ * - T-PDU
+ * - END-MARKER
+ */
+ case NW_GTPV1U_ULP_API_RECV_TPDU: {
+ uint8_t buffer[4096];
+ uint32_t buffer_len;
+ //uint16_t msgType = NW_GTP_GPDU;
+ //NwGtpv1uMsgT *pMsg = NULL;
+ /* Nw-gptv1u stack has processed a PDU. we can schedule it to PDCP
+ * for transmission.
+ */
+ teid = pUlpApi->apiInfo.recvMsgInfo.teid;
+ //pMsg = (NwGtpv1uMsgT *) pUlpApi->apiInfo.recvMsgInfo.hMsg;
+ //msgType = pMsg->msgType;
+
+ if (NW_GTPV1U_OK != nwGtpv1uMsgGetTpdu(pUlpApi->apiInfo.recvMsgInfo.hMsg,
+ buffer, &buffer_len)) {
+ LOG_E(GTPU, "Error while retrieving T-PDU");
+ }
+
+ itti_free(TASK_UDP, ((NwGtpv1uMsgT *)pUlpApi->apiInfo.recvMsgInfo.hMsg)->msgBuf);
+#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0
+ gtpv1u_eNB_write_dump_socket(buffer,buffer_len);
+#endif
+ rc = nwGtpv1uMsgDelete(RC.gtpv1u_data_g->gtpv1u_stack,
+ pUlpApi->apiInfo.recvMsgInfo.hMsg);
+
+ if (rc != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "nwGtpv1uMsgDelete failed: 0x%x\n", rc);
+ }
+
+ hash_rc = hashtable_get(RC.gtpv1u_data_g->teid_mapping, teid, (void **)>pv1u_teid_data_p);
+
+ if (hash_rc == HASH_TABLE_OK) {
+#if defined(LOG_GTPU) && LOG_GTPU > 0
+ LOG_D(GTPU, "Received T-PDU from gtpv1u stack teid %u size %d -> enb module id %u ue module id %u rab id %u\n",
+ teid,
+ buffer_len,
+ gtpv1u_teid_data_p->enb_id,
+ gtpv1u_teid_data_p->ue_id,
+ gtpv1u_teid_data_p->eps_bearer_id);
+#endif
+ //warning "LG eps bearer mapping to DRB id to do (offset -4)"
+ PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, gtpv1u_teid_data_p->enb_id, ENB_FLAG_YES, gtpv1u_teid_data_p->ue_id, 0, 0,gtpv1u_teid_data_p->enb_id);
+ MSC_LOG_TX_MESSAGE(
+ MSC_GTPU_ENB,
+ MSC_PDCP_ENB,
+ NULL,0,
+ MSC_AS_TIME_FMT" DATA-REQ rb %u size %u",
+ 0,0,
+ (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4,
+ buffer_len);
+
+ result = pdcp_data_req(
+ &ctxt,
+ SRB_FLAG_NO,
+ (gtpv1u_teid_data_p->eps_bearer_id) ? gtpv1u_teid_data_p->eps_bearer_id - 4: 5-4,
+ 0, // mui
+ SDU_CONFIRM_NO, // confirm
+ buffer_len,
+ buffer,
+ PDCP_TRANSMISSION_MODE_DATA,NULL, NULL
+ );
+
+ if ( result == FALSE ) {
+ if (ctxt.configured == FALSE )
+ LOG_W(GTPU, "gNB node PDCP data request failed, cause: [UE:%x]RB is not configured!\n", ctxt.rnti) ;
+ else
+ LOG_W(GTPU, "PDCP data request failed\n");
+
+ return NW_GTPV1U_FAILURE;
+ }
+ } else {
+ LOG_W(GTPU, "Received T-PDU from gtpv1u stack teid %u unknown size %u", teid, buffer_len);
+ }
+ }
+ break;
+
+ default: {
+ LOG_E(GTPU, "Received undefined UlpApi (%02x) from gtpv1u stack!\n",
+ pUlpApi->apiType);
+ }
+ } // end of switch
+
+ return NW_GTPV1U_OK;
+}
+
+int gtpv1u_gNB_init(void) {
+ NwGtpv1uRcT rc = NW_GTPV1U_FAILURE;
+ NwGtpv1uUlpEntityT ulp;
+ NwGtpv1uUdpEntityT udp;
+ NwGtpv1uLogMgrEntityT log;
+ NwGtpv1uTimerMgrEntityT tmr;
+ // enb_properties_p = enb_config_get()->properties[0];
+ RC.gtpv1u_data_g = (gtpv1u_data_t *)calloc(sizeof(gtpv1u_data_t),1);
+ LOG_I(GTPU, "Initializing GTPU stack %p\n",&RC.gtpv1u_data_g);
+ //gtpv1u_data_g.gtpv1u_stack;
+ /* Initialize UE hashtable */
+ RC.gtpv1u_data_g->ue_mapping = hashtable_create (32, NULL, NULL);
+ AssertFatal(RC.gtpv1u_data_g->ue_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create returned %p\n", RC.gtpv1u_data_g->ue_mapping);
+ RC.gtpv1u_data_g->teid_mapping = hashtable_create (256, NULL, NULL);
+ AssertFatal(RC.gtpv1u_data_g->teid_mapping != NULL, " ERROR Initializing TASK_GTPV1_U task interface: in hashtable_create\n");
+ // RC.gtpv1u_data_g.enb_ip_address_for_S1u_S12_S4_up = enb_properties_p->enb_ipv4_address_for_S1U;
+ //gtpv1u_data_g.udp_data;
+ RC.gtpv1u_data_g->seq_num = 0;
+ RC.gtpv1u_data_g->restart_counter = 0;
+
+ /* Initializing GTPv1-U stack */
+ if ((rc = nwGtpv1uInitialize(&RC.gtpv1u_data_g->gtpv1u_stack, GTPU_STACK_ENB)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "Failed to setup nwGtpv1u stack %x\n", rc);
+ return -1;
+ }
+
+ if ((rc = nwGtpv1uSetLogLevel(RC.gtpv1u_data_g->gtpv1u_stack,
+ NW_LOG_LEVEL_DEBG)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "Failed to setup loglevel for stack %x\n", rc);
+ return -1;
+ }
+
+ /* Set the ULP API callback. Called once message have been processed by the
+ * nw-gtpv1u stack.
+ */
+ ulp.ulpReqCallback = gtpv1u_gNB_process_stack_req;
+ memset((void *)&(ulp.hUlp), 0, sizeof(NwGtpv1uUlpHandleT));
+
+ if ((rc = nwGtpv1uSetUlpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &ulp)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "nwGtpv1uSetUlpEntity: %x", rc);
+ return -1;
+ }
+
+ /* nw-gtpv1u stack requires an udp callback to send data over UDP.
+ * We provide a wrapper to UDP task.
+ */
+ udp.udpDataReqCallback = gtpv1u_eNB_send_udp_msg;
+ memset((void *)&(udp.hUdp), 0, sizeof(NwGtpv1uUdpHandleT));
+
+ if ((rc = nwGtpv1uSetUdpEntity(RC.gtpv1u_data_g->gtpv1u_stack, &udp)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "nwGtpv1uSetUdpEntity: %x", rc);
+ return -1;
+ }
+
+ log.logReqCallback = gtpv1u_eNB_log_request;
+ memset((void *)&(log.logMgrHandle), 0, sizeof(NwGtpv1uLogMgrHandleT));
+
+ if ((rc = nwGtpv1uSetLogMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &log)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "nwGtpv1uSetLogMgrEntity: %x", rc);
+ return -1;
+ }
+
+ /* Timer interface is more complicated as both wrappers doesn't send a message
+ * to the timer task but call the timer API functions start/stop timer.
+ */
+ tmr.tmrMgrHandle = 0;
+ tmr.tmrStartCallback = gtpv1u_start_timer_wrapper;
+ tmr.tmrStopCallback = gtpv1u_stop_timer_wrapper;
+
+ if ((rc = nwGtpv1uSetTimerMgrEntity(RC.gtpv1u_data_g->gtpv1u_stack, &tmr)) != NW_GTPV1U_OK) {
+ LOG_E(GTPU, "nwGtpv1uSetTimerMgrEntity: %x", rc);
+ return -1;
+ }
+
+#if defined(GTP_DUMP_SOCKET) && GTP_DUMP_SOCKET > 0
+
+ if ((ret = gtpv1u_eNB_create_dump_socket()) < 0) {
+ return -1;
+ }
+
+#endif
+ LOG_D(GTPU, "Initializing GTPV1U interface for eNB: DONE\n");
+ return 0;
+}
+
+void *gtpv1u_gNB_task(void *args) {
+ int rc = 0;
+ rc = gtpv1u_gNB_init();
+ AssertFatal(rc == 0, "gtpv1u_eNB_init Failed");
+ itti_mark_task_ready(TASK_GTPV1_U);
+ MSC_START_USE();
+
+ while(1) {
+ (void) gtpv1u_eNB_process_itti_msg (NULL);
+ }
+
+ return NULL;
+}
+
diff --git a/targets/COMMON/create_tasks_mbms.h b/openair3/GTPV1-U/gtpv1u_gNB_task.h
similarity index 73%
rename from targets/COMMON/create_tasks_mbms.h
rename to openair3/GTPV1-U/gtpv1u_gNB_task.h
index 843897cefb4a73b0f52fc74e7b2fc80ddeb0790d..42fae7a7149d53107d9a7662e1a698ff64664785 100644
--- a/targets/COMMON/create_tasks_mbms.h
+++ b/openair3/GTPV1-U/gtpv1u_gNB_task.h
@@ -1,5 +1,4 @@
-/*
- * Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+/* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
@@ -19,14 +18,20 @@
* contact@openairinterface.org
*/
-#ifndef CREATE_TASKS_H_
-#define CREATE_TASKS_H_
+/*! \file gtpv1u_gNB_task.h
+* \brief
+* \author Lionel Gauthier Panos Matzakos
+* \company Eurecom
+* \email: lionel.gauthier@eurecom.fr
+*/
-/* External declaration of L2L1 task that depend on the target */
-extern void *l2l1_task(void *arg);
+#ifndef GTPV1U_GNB_TASK_H_
+#define GTPV1U_GNB_TASK_H_
-int create_tasks(uint32_t enb_nb);
-int create_tasks_ue(uint32_t ue_nb);
-int create_tasks_mbms(uint32_t enb_nb);
+int gtpv1u_gNB_init(void);
+
+void *gtpv1u_gNB_task(void *args);
+
+
+#endif /* GTPV1U_GNB_TASK_H_ */
-#endif /* CREATE_TASKS_H_ */
diff --git a/openair3/M3AP/m3ap_MCE.c b/openair3/M3AP/m3ap_MCE.c
index 232b0c0ecec5842d85398dadabb7bf9a978d7aec..dec9b9689791bf5334082266bdefae0dddb4d079 100644
--- a/openair3/M3AP/m3ap_MCE.c
+++ b/openair3/M3AP/m3ap_MCE.c
@@ -142,6 +142,20 @@ void m3ap_MCE_handle_sctp_association_resp(instance_t instance, sctp_new_associa
sctp_new_association_resp->ulp_cnx_id);
//m3ap_handle_m3_setup_message(instance_p, m3ap_enb_data_p,
//sctp_new_association_resp->sctp_state == SCTP_STATE_SHUTDOWN);
+ sleep(4);
+ int index;
+ /* Trying to connect to the provided list of eNB ip address */
+ for (index = 0; index < instance_p->nb_m3; index++) {
+ //M2AP_INFO("eNB[%d] eNB id %u acting as an initiator (client)\n",
+ // instance_id, instance->eNB_id);
+ m3ap_MCE_register_MCE(instance_p,
+ &instance_p->target_mme_m3_ip_address[index],
+ &instance_p->mme_m3_ip_address,
+ instance_p->sctp_in_streams,
+ instance_p->sctp_out_streams,
+ instance_p->mce_port_for_M3C,
+ instance_p->multi_sd);
+ }
return;
}
diff --git a/openair3/M3AP/m3ap_MCE_generate_messages.h b/openair3/M3AP/m3ap_MCE_generate_messages.h
index 0884e8216e0c2d1df0126674080321a19005ff98..1a5733acc31bc049563c9f73584c9ccf8e0c6a81 100644
--- a/openair3/M3AP/m3ap_MCE_generate_messages.h
+++ b/openair3/M3AP/m3ap_MCE_generate_messages.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M2AP_ENB_GENERATE_MESSAGES_H_
-#define M2AP_ENB_GENERATE_MESSAGES_H_
+#ifndef __M3AP_MCE_GENERATE_MESSAGES__H__
+#define __M3AP_MCE_GENERATE_MESSAGES__H__
#include "m2ap_eNB_defs.h"
#include "m2ap_common.h"
@@ -37,27 +37,8 @@ int m2ap_eNB_generate_m2_setup_request(m2ap_eNB_instance_t *instance_p,
int m2ap_MCE_generate_m2_setup_response(m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p);
-/*int m2ap_MCE_generate_m2_setup_failure(instance_t instance,
- uint32_t assoc_id,
- M2AP_Cause_PR cause_type,
- long cause_value,
- long time_to_wait);*/
-
int m2ap_eNB_set_cause (M2AP_Cause_t * cause_p,
M2AP_Cause_PR cause_type,
long cause_value);
-//int m2ap_eNB_generate_m2_handover_request (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p,
-// m2ap_handover_req_t *m2ap_handover_req, int ue_id);
-//
-//int m2ap_eNB_generate_m2_handover_request_ack (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p,
-// m2ap_handover_req_ack_t *m2ap_handover_req_ack);
-//
-//int m2ap_eNB_generate_m2_ue_context_release (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p,
-// m2ap_ue_context_release_t *m2ap_ue_context_release);
-//
-//int m2ap_eNB_generate_m2_handover_cancel (m2ap_eNB_instance_t *instance_p, m2ap_eNB_data_t *m2ap_eNB_data_p,
-// int m2_ue_id,
-// m2ap_handover_cancel_cause_t cause);
-
-#endif /* M2AP_ENB_GENERATE_MESSAGES_H_ */
+#endif /* __M3AP_MCE_GENERATE_MESSAGES__H__ */
diff --git a/openair3/M3AP/m3ap_MCE_handler.h b/openair3/M3AP/m3ap_MCE_handler.h
index ce4997e80d7d95b1acf08ad8c64a149aa3405f65..09eca351b68477a0f5055c785d502403d2a1bf36 100644
--- a/openair3/M3AP/m3ap_MCE_handler.h
+++ b/openair3/M3AP/m3ap_MCE_handler.h
@@ -19,15 +19,15 @@
* contact@openairinterface.org
*/
-/*! \file m2ap_handler.h
- * \brief m2ap handler procedures for eNB
+/*! \file m3ap_handler.h
+ * \brief m3ap handler procedures for eNB
* \author Javier Morgade <javier.morgade@ieee.org>
* \date 2019
* \version 0.1
*/
-#ifndef M2AP_MCE_HANDLERS_H_
-#define M2AP_MCE_HANDLERS_H_
+#ifndef __M3AP_MCE_HANDLER__H__
+#define __M3AP_MCE_HANDLER__H__
#include "m2ap_MCE_defs.h"
@@ -40,4 +40,4 @@ int m3ap_MCE_handle_message(instance_t instance, uint32_t assoc_id, int32_t stre
const uint8_t * const data, const uint32_t data_length);
-#endif /* M2AP_MCE_HANDLERS_H_ */
+#endif /* __M3AP_MCE_HANDLER__H__ */
diff --git a/openair3/M3AP/m3ap_MCE_management_procedures.h b/openair3/M3AP/m3ap_MCE_management_procedures.h
index 2d18df8c26d23877bd9fd1b9d2e3312fbff64d3c..27e8c928a0f01af144dada89e8246c823575a6b1 100644
--- a/openair3/M3AP/m3ap_MCE_management_procedures.h
+++ b/openair3/M3AP/m3ap_MCE_management_procedures.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M3AP_MCE_MANAGEMENT_PROCEDURES_H_
-#define M3AP_MCE_MANAGEMENT_PROCEDURES_H
+#ifndef __M3AP_MCE_MANAGEMENT_PROCEDURES__H__
+#define __M3AP_MCE_MANAGEMENT_PROCEDURES__H__
void m3ap_MCE_prepare_internal_data(void);
@@ -50,4 +50,4 @@ struct m3ap_MCE_data_s *m3ap_get_MCE(m3ap_MCE_instance_t *instance_p,
int32_t assoc_id,
uint16_t cnx_id);
-#endif /* M3AP_MCE_MANAGEMENT_PROCEDURES_H_ */
+#endif /* __M3AP_MCE_MANAGEMENT_PROCEDURES__H__ */
diff --git a/openair3/M3AP/m3ap_MME_generate_messages.h b/openair3/M3AP/m3ap_MME_generate_messages.h
index 1632dc807acc307de1af06650f2f824272239c7a..146f58825a8d9bb18f7b0ed26c57dcea66e23209 100644
--- a/openair3/M3AP/m3ap_MME_generate_messages.h
+++ b/openair3/M3AP/m3ap_MME_generate_messages.h
@@ -19,15 +19,15 @@
* contact@openairinterface.org
*/
-/*! \file m2ap_MCE_generate_messages.h
- * \brief m2ap procedures for MCE
+/*! \file m3ap_MCE_generate_messages.h
+ * \brief m3ap procedures for MCE
* \author Javier Morgade <javier.morgade@ieee.org>
* \date 2019
* \version 0.1
*/
-#ifndef M2AP_MCE_GENERATE_MESSAGES_H_
-#define M2AP_MCE_GENERATE_MESSAGES_H_
+#ifndef M3AP_MCE_GENERATE_MESSAGES_H_
+#define M3AP_MCE_GENERATE_MESSAGES_H_
#include "m2ap_MCE_defs.h"
#include "m2ap_common.h"
diff --git a/openair3/M3AP/m3ap_MME_management_procedures.h b/openair3/M3AP/m3ap_MME_management_procedures.h
index e966ee1f17eb3ed982ee6e556b149b9607dc4339..b21189b9157013862894b267833aa95d35d8adfe 100644
--- a/openair3/M3AP/m3ap_MME_management_procedures.h
+++ b/openair3/M3AP/m3ap_MME_management_procedures.h
@@ -26,8 +26,8 @@
* \version 0.1
*/
-#ifndef M3AP_MME_MANAGEMENT_PROCEDURES_H_
-#define M3AP_MME_MANAGEMENT_PROCEDURES_H
+#ifndef __M3AP_MME_MANAGEMENT_PROCEDURES__H__
+#define __M3AP_MME_MANAGEMENT_PROCEDURES__H__
void m3ap_MME_prepare_internal_data(void);
@@ -51,4 +51,4 @@ struct m3ap_MME_data_s *m3ap_get_MME(m3ap_MME_instance_t *instance_p,
int32_t assoc_id,
uint16_t cnx_id);
-#endif /* M3AP_MME_MANAGEMENT_PROCEDURES_H_ */
+#endif /* __M3AP_MME_MANAGEMENT_PROCEDURES__H__ */
diff --git a/openair3/MME_APP/enb_paramdef_mme.h b/openair3/MME_APP/enb_paramdef_mme.h
index 3d65036553bc6579b96ac2fdb512441fc6b70daa..127c1855e779d34735c332b79095410d26c70197 100644
--- a/openair3/MME_APP/enb_paramdef_mme.h
+++ b/openair3/MME_APP/enb_paramdef_mme.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __MME_APP_ENB_PARAMDEF_MME__H__
+#define __MME_APP_ENB_PARAMDEF_MME__H__
+
#include "common/config/config_paramdesc.h"
#include "RRC_paramsvalues.h"
@@ -172,3 +175,4 @@ typedef struct ccparams_MME_s {
{ .s5= {NULL }} \
}
+#endif
diff --git a/openair3/MME_APP/mme_config.h b/openair3/MME_APP/mme_config.h
index 4371ad55f6f2ecf1a9865654060ebd267a6bb775..2eb0a66e85c07bc2ab4461750bb26b223dfcf2e1 100644
--- a/openair3/MME_APP/mme_config.h
+++ b/openair3/MME_APP/mme_config.h
@@ -26,8 +26,9 @@
EMAIL : javier.morgade@ieee.org
*/
-#ifndef MME_CONFIG_H_
-#define MME_CONFIG_H_
+#ifndef __MME_APP_MME_CONFIG__H__
+#define __MME_APP_MME_CONFIG__H__
+
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
@@ -48,5 +49,5 @@
int RCconfig_MME(void);
-#endif /* MME_CONFIG_H_ */
+#endif /* __MME_APP_MME_CONFIG__H__ */
/** @} */
diff --git a/openair3/NAS/COMMON/API/NETWORK/as_message.h b/openair3/NAS/COMMON/API/NETWORK/as_message.h
deleted file mode 100644
index 30810a325eace63c944b947bfb8c0a6487094e80..0000000000000000000000000000000000000000
--- a/openair3/NAS/COMMON/API/NETWORK/as_message.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * Copyright (c) 2015, EURECOM (www.eurecom.fr)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * The views and conclusions contained in the software and documentation are those
- * of the authors and should not be interpreted as representing official policies,
- * either expressed or implied, of the FreeBSD Project.
- */
-
-
-/*****************************************************************************
-
-Source as_message.h
-
-Version 0.1
-
-Date 2012/10/18
-
-Product NAS stack
-
-Subsystem Application Programming Interface
-
-Author Frederic Maurel
-
-Description Defines the messages supported by the Access Stratum sublayer
- protocol (usually RRC and S1AP for E-UTRAN) and functions used
- to encode and decode
-
-*****************************************************************************/
-#ifndef __AS_MESSAGE_H__
-#define __AS_MESSAGE_H__
-
-#include "commonDef.h"
-#include "networkDef.h"
-
-/****************************************************************************/
-/********************* G L O B A L C O N S T A N T S *******************/
-/****************************************************************************/
-
-/*
- * --------------------------------------------------------------------------
- * Access Stratum message types
- * --------------------------------------------------------------------------
- */
-#define AS_REQUEST 0x0100
-#define AS_RESPONSE 0x0200
-#define AS_INDICATION 0x0400
-#define AS_CONFIRM 0x0800
-
-/*
- * --------------------------------------------------------------------------
- * Access Stratum message identifiers
- * --------------------------------------------------------------------------
- */
-
-/* Broadcast information */
-#define AS_BROADCAST_INFO 0x01
-#define AS_BROADCAST_INFO_IND (AS_BROADCAST_INFO | AS_INDICATION)
-
-/* Cell information relevant for cell selection processing */
-#define AS_CELL_INFO 0x02
-#define AS_CELL_INFO_REQ (AS_CELL_INFO | AS_REQUEST)
-#define AS_CELL_INFO_CNF (AS_CELL_INFO | AS_CONFIRM)
-#define AS_CELL_INFO_IND (AS_CELL_INFO | AS_INDICATION)
-
-/* Paging information */
-#define AS_PAGING 0x03
-#define AS_PAGING_REQ (AS_PAGING | AS_REQUEST)
-#define AS_PAGING_IND (AS_PAGING | AS_INDICATION)
-
-/* NAS signalling connection establishment */
-#define AS_NAS_ESTABLISH 0x04
-#define AS_NAS_ESTABLISH_REQ (AS_NAS_ESTABLISH | AS_REQUEST)
-#define AS_NAS_ESTABLISH_IND (AS_NAS_ESTABLISH | AS_INDICATION)
-#define AS_NAS_ESTABLISH_RSP (AS_NAS_ESTABLISH | AS_RESPONSE)
-#define AS_NAS_ESTABLISH_CNF (AS_NAS_ESTABLISH | AS_CONFIRM)
-
-/* NAS signalling connection release */
-#define AS_NAS_RELEASE 0x05
-#define AS_NAS_RELEASE_REQ (AS_NAS_RELEASE | AS_REQUEST)
-#define AS_NAS_RELEASE_IND (AS_NAS_RELEASE | AS_INDICATION)
-
-/* Uplink information transfer */
-#define AS_UL_INFO_TRANSFER 0x06
-#define AS_UL_INFO_TRANSFER_REQ (AS_UL_INFO_TRANSFER | AS_REQUEST)
-#define AS_UL_INFO_TRANSFER_CNF (AS_UL_INFO_TRANSFER | AS_CONFIRM)
-#define AS_UL_INFO_TRANSFER_IND (AS_UL_INFO_TRANSFER | AS_INDICATION)
-
-/* Downlink information transfer */
-#define AS_DL_INFO_TRANSFER 0x07
-#define AS_DL_INFO_TRANSFER_REQ (AS_DL_INFO_TRANSFER | AS_REQUEST)
-#define AS_DL_INFO_TRANSFER_CNF (AS_DL_INFO_TRANSFER | AS_CONFIRM)
-#define AS_DL_INFO_TRANSFER_IND (AS_DL_INFO_TRANSFER | AS_INDICATION)
-
-/* Radio Access Bearer establishment */
-#define AS_RAB_ESTABLISH 0x08
-#define AS_RAB_ESTABLISH_REQ (AS_RAB_ESTABLISH | AS_REQUEST)
-#define AS_RAB_ESTABLISH_IND (AS_RAB_ESTABLISH | AS_INDICATION)
-#define AS_RAB_ESTABLISH_RSP (AS_RAB_ESTABLISH | AS_RESPONSE)
-#define AS_RAB_ESTABLISH_CNF (AS_RAB_ESTABLISH | AS_CONFIRM)
-
-/* Radio Access Bearer release */
-#define AS_RAB_RELEASE 0x09
-#define AS_RAB_RELEASE_REQ (AS_RAB_RELEASE | AS_REQUEST)
-#define AS_RAB_RELEASE_IND (AS_RAB_RELEASE | AS_INDICATION)
-
-/* NAS Cause */
-#define EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED (8)
-#define EPS_SERVICES_NOT_ALLOWED (7)
-#define PLMN_NOT_ALLOWED (11)
-#define TRACKING_AREA_NOT_ALLOWED (12)
-#define ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA (13)
-#define EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN (14)
-#define NO_SUITABLE_CELLS_IN_TRACKING_AREA (15)
-#define NETWORK_FAILURE (17)
-#define ESM_FAILURE (19)
-
-typedef enum nas_cause_s {
- NAS_CAUSE_EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED = EPS_SERVICES_AND_NON_EPS_SERVICES_NOT_ALLOWED,
- NAS_CAUSE_EPS_SERVICES_NOT_ALLOWED = EPS_SERVICES_NOT_ALLOWED,
- NAS_CAUSE_PLMN_NOT_ALLOWED = PLMN_NOT_ALLOWED,
- NAS_CAUSE_TRACKING_AREA_NOT_ALLOWED = TRACKING_AREA_NOT_ALLOWED,
- NAS_CAUSE_ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA = ROAMING_NOT_ALLOWED_IN_THIS_TRACKING_AREA,
- NAS_CAUSE_EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN = EPS_SERVICES_NOT_ALLOWED_IN_THIS_PLMN,
- NAS_CAUSE_NO_SUITABLE_CELLS_IN_TRACKING_AREA = NO_SUITABLE_CELLS_IN_TRACKING_AREA,
- NAS_CAUSE_NETWORK_FAILURE = NETWORK_FAILURE,
- NAS_CAUSE_ESM_FAILURE = ESM_FAILURE
-} nas_cause_t;
-
-/*
- * --------------------------------------------------------------------------
- * Access Stratum message global parameters
- * --------------------------------------------------------------------------
- */
-
-/* Error code */
-typedef enum nas_error_code_s {
- AS_SUCCESS = 1, /* Success code, transaction is going on */
- AS_TERMINATED_NAS, /* Transaction terminated by NAS */
- AS_TERMINATED_AS, /* Transaction terminated by AS */
- AS_FAILURE /* Failure code */
-} nas_error_code_t;
-
-/* Core network domain */
-typedef enum core_network_s {
- AS_PS = 1, /* Packet-Switched */
- AS_CS /* Circuit-Switched */
-} core_network_t;
-
-/* SAE Temporary Mobile Subscriber Identity */
-typedef struct as_stmsi_s {
- uint8_t MMEcode; /* MME code that allocated the GUTI */
- uint32_t m_tmsi; /* M-Temporary Mobile Subscriber Identity */
-} as_stmsi_t;
-
-/* Dedicated NAS information */
-typedef struct as_nas_info_s {
- uint32_t length; /* Length of the NAS information data */
- Byte_t* data; /* Dedicated NAS information data container */
-} as_nas_info_t;
-
-/* Radio Access Bearer identity */
-typedef uint8_t as_rab_id_t;
-
-/****************************************************************************/
-/************************ G L O B A L T Y P E S ************************/
-/****************************************************************************/
-
-/*
- * --------------------------------------------------------------------------
- * Broadcast information
- * --------------------------------------------------------------------------
- */
-
-/*
- * AS->NAS - Broadcast information indication
- * AS may asynchronously report to NAS available PLMNs within specific
- * location area
- */
-typedef struct broadcast_info_ind_s {
-#define PLMN_LIST_MAX_SIZE 6
- PLMN_LIST_T(PLMN_LIST_MAX_SIZE) plmnIDs; /* List of PLMN identifiers */
- ci_t cellID; /* Identity of the cell serving the listed PLMNs */
- tac_t tac; /* Code of the tracking area the cell belongs to */
-} broadcast_info_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * Cell information relevant for cell selection processing
- * --------------------------------------------------------------------------
- */
-
-/* Radio access technologies supported by the network */
-#define AS_GSM (1 << NET_ACCESS_GSM)
-#define AS_COMPACT (1 << NET_ACCESS_COMPACT)
-#define AS_UTRAN (1 << NET_ACCESS_UTRAN)
-#define AS_EGPRS (1 << NET_ACCESS_EGPRS)
-#define AS_HSDPA (1 << NET_ACCESS_HSDPA)
-#define AS_HSUPA (1 << NET_ACCESS_HSUPA)
-#define AS_HSDUPA (1 << NET_ACCESS_HSDUPA)
-#define AS_EUTRAN (1 << NET_ACCESS_EUTRAN)
-
-/*
- * NAS->AS - Cell Information request
- * NAS request AS to search for a suitable cell belonging to the selected
- * PLMN to camp on.
- */
-typedef struct cell_info_req_s {
- plmn_t plmnID; /* Selected PLMN identity */
- Byte_t rat; /* Bitmap - set of radio access technologies */
-} cell_info_req_t;
-
-/*
- * AS->NAS - Cell Information confirm
- * AS search for a suitable cell and respond to NAS. If found, the cell
- * is selected to camp on.
- */
-typedef struct cell_info_cnf_s {
- uint8_t errCode; /* Error code */
- ci_t cellID; /* Identity of the cell serving the selected PLMN */
- tac_t tac; /* Code of the tracking area the cell belongs to */
- AcT_t rat; /* Radio access technology supported by the cell */
- uint8_t rsrq; /* Reference signal received quality */
- uint8_t rsrp; /* Reference signal received power */
-} cell_info_cnf_t;
-
-/*
- * AS->NAS - Cell Information indication
- * AS may change cell selection if a more suitable cell is found.
- */
-typedef struct cell_info_ind_s {
- ci_t cellID; /* Identity of the new serving cell */
- tac_t tac; /* Code of the tracking area the cell belongs to */
-} cell_info_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * Paging information
- * --------------------------------------------------------------------------
- */
-
-/* Paging cause */
-typedef enum paging_cause_s {
- AS_CONNECTION_ESTABLISH, /* Establish NAS signalling connection */
- AS_EPS_ATTACH, /* Perform local detach and initiate EPS
- * attach procedure */
- AS_CS_FALLBACK /* Inititate CS fallback procedure */
-} paging_cause_t;
-
-/*
- * NAS->AS - Paging Information request
- * NAS requests the AS that NAS signalling messages or user data is pending
- * to be sent.
- */
-typedef struct paging_req_s {
- as_stmsi_t s_tmsi; /* UE identity */
- uint8_t CN_domain; /* Core network domain */
-} paging_req_t;
-
-/*
- * AS->NAS - Paging Information indication
- * AS reports to the NAS that appropriate procedure has to be initiated.
- */
-typedef struct paging_ind_s {
- paging_cause_t cause; /* Paging cause */
-} paging_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * NAS signalling connection establishment
- * --------------------------------------------------------------------------
- */
-
-/* Cause of RRC connection establishment */
-typedef enum as_cause_s {
- AS_CAUSE_UNKNOWN = 0,
- AS_CAUSE_EMERGENCY = NET_ESTABLISH_CAUSE_EMERGENCY,
- AS_CAUSE_HIGH_PRIO = NET_ESTABLISH_CAUSE_HIGH_PRIO,
- AS_CAUSE_MT_ACCESS = NET_ESTABLISH_CAUSE_MT_ACCESS,
- AS_CAUSE_MO_SIGNAL = NET_ESTABLISH_CAUSE_MO_SIGNAL,
- AS_CAUSE_MO_DATA = NET_ESTABLISH_CAUSE_MO_DATA,
- AS_CAUSE_V1020 = NET_ESTABLISH_CAUSE_V1020
-} as_cause_t;
-
-/* Type of the call associated to the RRC connection establishment */
-typedef enum as_call_type_s {
- AS_TYPE_ORIGINATING_SIGNAL = NET_ESTABLISH_TYPE_ORIGINATING_SIGNAL,
- AS_TYPE_EMERGENCY_CALLS = NET_ESTABLISH_TYPE_EMERGENCY_CALLS,
- AS_TYPE_ORIGINATING_CALLS = NET_ESTABLISH_TYPE_ORIGINATING_CALLS,
- AS_TYPE_TERMINATING_CALLS = NET_ESTABLISH_TYPE_TERMINATING_CALLS,
- AS_TYPE_MO_CS_FALLBACK = NET_ESTABLISH_TYPE_MO_CS_FALLBACK
-} as_call_type_t;
-
-/*
- * NAS->AS - NAS signalling connection establishment request
- * NAS requests the AS to perform the RRC connection establishment procedure
- * to transfer initial NAS message to the network while UE is in IDLE mode.
- */
-typedef struct nas_establish_req_s {
- as_cause_t cause; /* RRC connection establishment cause */
- as_call_type_t type; /* RRC associated call type */
- as_stmsi_t s_tmsi; /* UE identity */
- plmn_t plmnID; /* Selected PLMN identity */
- as_nas_info_t initialNasMsg; /* Initial NAS message to transfer */
-} nas_establish_req_t;
-
-/*
- * AS->NAS - NAS signalling connection establishment indication
- * AS transfers the initial NAS message to the NAS.
- */
-typedef struct nas_establish_ind_s {
- uint32_t UEid; /* UE lower layer identifier */
- tac_t tac; /* Code of the tracking area the initiating
- * UE belongs to */
- as_cause_t asCause; /* Establishment cause */
- as_nas_info_t initialNasMsg; /* Initial NAS message to transfer */
-} nas_establish_ind_t;
-
-/*
- * NAS->AS - NAS signalling connection establishment response
- * NAS responds to the AS that initial answer message has to be provided to
- * the UE.
- */
-typedef struct nas_establish_rsp_s {
- uint32_t UEid; /* UE lower layer identifier */
- as_stmsi_t s_tmsi; /* UE identity */
- nas_error_code_t errCode; /* Transaction status */
- as_nas_info_t nasMsg; /* NAS message to transfer */
- uint32_t nas_ul_count; /* UL NAS COUNT */
- uint16_t selected_encryption_algorithm;
- uint16_t selected_integrity_algorithm;
-} nas_establish_rsp_t;
-
-/*
- * AS->NAS - NAS signalling connection establishment confirm
- * AS transfers the initial answer message to the NAS.
- */
-typedef struct nas_establish_cnf_s {
- uint32_t UEid; /* UE lower layer identifier */
- nas_error_code_t errCode; /* Transaction status */
- as_nas_info_t nasMsg; /* NAS message to transfer */
- uint32_t ul_nas_count;
- uint16_t selected_encryption_algorithm;
- uint16_t selected_integrity_algorithm;
-} nas_establish_cnf_t;
-
-/*
- * --------------------------------------------------------------------------
- * NAS signalling connection release
- * --------------------------------------------------------------------------
- */
-
-/* Release cause */
-typedef enum release_cause_s {
- AS_AUTHENTICATION_FAILURE = 1, /* Authentication procedure failed */
- AS_DETACH /* Detach requested */
-} release_cause_t;
-
-/*
- * NAS->AS - NAS signalling connection release request
- * NAS requests the termination of the connection with the UE.
- */
-typedef struct nas_release_req_s {
- uint32_t UEid; /* UE lower layer identifier */
- as_stmsi_t s_tmsi; /* UE identity */
- release_cause_t cause; /* Release cause */
-} nas_release_req_t;
-
-/*
- * AS->NAS - NAS signalling connection release indication
- * AS reports that connection has been terminated by the network.
- */
-typedef struct nas_release_ind_s {
- release_cause_t cause; /* Release cause */
-} nas_release_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * NAS information transfer
- * --------------------------------------------------------------------------
- */
-
-/*
- * NAS->AS - Uplink data transfer request
- * NAS requests the AS to transfer uplink information to the NAS that
- * operates at the network side.
- */
-typedef struct ul_info_transfer_req_s {
- uint32_t UEid; /* UE lower layer identifier */
- as_stmsi_t s_tmsi; /* UE identity */
- as_nas_info_t nasMsg; /* Uplink NAS message */
-} ul_info_transfer_req_t;
-
-/*
- * AS->NAS - Uplink data transfer confirm
- * AS immediately notifies the NAS whether uplink information has been
- * successfully sent to the network or not.
- */
-typedef struct ul_info_transfer_cnf_s {
- uint32_t UEid; /* UE lower layer identifier */
- nas_error_code_t errCode; /* Transaction status */
-} ul_info_transfer_cnf_t;
-
-/*
- * AS->NAS - Uplink data transfer indication
- * AS delivers the uplink information message to the NAS that operates
- * at the network side.
- */
-typedef struct ul_info_transfer_ind_s {
- uint32_t UEid; /* UE lower layer identifier */
- as_nas_info_t nasMsg; /* Uplink NAS message */
-} ul_info_transfer_ind_t;
-
-/*
- * NAS->AS - Downlink data transfer request
- * NAS requests the AS to transfer downlink information to the NAS that
- * operates at the UE side.
- */
-typedef ul_info_transfer_req_t dl_info_transfer_req_t;
-
-/*
- * AS->NAS - Downlink data transfer confirm
- * AS immediately notifies the NAS whether downlink information has been
- * successfully sent to the network or not.
- */
-typedef ul_info_transfer_cnf_t dl_info_transfer_cnf_t;
-
-/*
- * AS->NAS - Downlink data transfer indication
- * AS delivers the downlink information message to the NAS that operates
- * at the UE side.
- */
-typedef ul_info_transfer_ind_t dl_info_transfer_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * Radio Access Bearer establishment
- * --------------------------------------------------------------------------
- */
-
-/* TODO: Quality of Service parameters */
-typedef struct {} as_qos_t;
-
-/*
- * NAS->AS - Radio access bearer establishment request
- * NAS requests the AS to allocate transmission resources to radio access
- * bearer initialized at the network side.
- */
-typedef struct rab_establish_req_s {
- as_stmsi_t s_tmsi; /* UE identity */
- as_rab_id_t rabID; /* Radio access bearer identity */
- as_qos_t QoS; /* Requested Quality of Service */
-} rab_establish_req_t;
-
-/*
- * AS->NAS - Radio access bearer establishment indication
- * AS notifies the NAS that specific radio access bearer has to be setup.
- */
-typedef struct rab_establish_ind_s {
- as_rab_id_t rabID; /* Radio access bearer identity */
-} rab_establish_ind_t;
-
-/*
- * NAS->AS - Radio access bearer establishment response
- * NAS responds to AS whether the specified radio access bearer has been
- * successfully setup or not.
- */
-typedef struct rab_establish_rsp_s {
- as_stmsi_t s_tmsi; /* UE identity */
- as_rab_id_t rabID; /* Radio access bearer identity */
- nas_error_code_t errCode; /* Transaction status */
-} rab_establish_rsp_t;
-
-/*
- * AS->NAS - Radio access bearer establishment confirm
- * AS notifies NAS whether the specified radio access bearer has been
- * successfully setup at the UE side or not.
- */
-typedef struct rab_establish_cnf_s {
- as_rab_id_t rabID; /* Radio access bearer identity */
- nas_error_code_t errCode; /* Transaction status */
-} rab_establish_cnf_t;
-
-/*
- * --------------------------------------------------------------------------
- * Radio Access Bearer release
- * --------------------------------------------------------------------------
- */
-
-/*
- * NAS->AS - Radio access bearer release request
- * NAS requests the AS to release transmission resources previously allocated
- * to specific radio access bearer at the network side.
- */
-typedef struct rab_release_req_s {
- as_stmsi_t s_tmsi; /* UE identity */
- as_rab_id_t rabID; /* Radio access bearer identity */
-} rab_release_req_t;
-
-/*
- * AS->NAS - Radio access bearer release indication
- * AS notifies NAS that specific radio access bearer has been released.
- */
-typedef struct rab_release_ind_s {
- as_rab_id_t rabID; /* Radio access bearer identity */
-} rab_release_ind_t;
-
-/*
- * --------------------------------------------------------------------------
- * Structure of the AS messages handled by the network sublayer
- * --------------------------------------------------------------------------
- */
-typedef struct as_message_s {
- uint16_t msgID;
- union {
- broadcast_info_ind_t broadcast_info_ind;
- cell_info_req_t cell_info_req;
- cell_info_cnf_t cell_info_cnf;
- cell_info_ind_t cell_info_ind;
- paging_req_t paging_req;
- paging_ind_t paging_ind;
- nas_establish_req_t nas_establish_req;
- nas_establish_ind_t nas_establish_ind;
- nas_establish_rsp_t nas_establish_rsp;
- nas_establish_cnf_t nas_establish_cnf;
- nas_release_req_t nas_release_req;
- nas_release_ind_t nas_release_ind;
- ul_info_transfer_req_t ul_info_transfer_req;
- ul_info_transfer_cnf_t ul_info_transfer_cnf;
- ul_info_transfer_ind_t ul_info_transfer_ind;
- dl_info_transfer_req_t dl_info_transfer_req;
- dl_info_transfer_cnf_t dl_info_transfer_cnf;
- dl_info_transfer_ind_t dl_info_transfer_ind;
- rab_establish_req_t rab_establish_req;
- rab_establish_ind_t rab_establish_ind;
- rab_establish_rsp_t rab_establish_rsp;
- rab_establish_cnf_t rab_establish_cnf;
- rab_release_req_t rab_release_req;
- rab_release_ind_t rab_release_ind;
- } __attribute__((__packed__)) msg;
-} as_message_t;
-
-/****************************************************************************/
-/******************** G L O B A L V A R I A B L E S ********************/
-/****************************************************************************/
-
-/****************************************************************************/
-/****************** E X P O R T E D F U N C T I O N S ******************/
-/****************************************************************************/
-
-int as_message_decode(const char* buffer, as_message_t* msg, int length);
-
-int as_message_encode(char* buffer, as_message_t* msg, int length);
-
-/* Implemented in the network_api.c body file */
-int as_message_send(as_message_t* as_msg);
-
-#endif /* __AS_MESSAGE_H__*/
diff --git a/openair3/NAS/COMMON/UTIL/socket.h b/openair3/NAS/COMMON/UTIL/socket.h
index 033046d98c08d04e39607740794f4b8cd2446737..58bc6b8527614361f36245e2b91cfbbd482bfa21 100644
--- a/openair3/NAS/COMMON/UTIL/socket.h
+++ b/openair3/NAS/COMMON/UTIL/socket.h
@@ -35,8 +35,8 @@ Author Frederic Maurel
Description Implements TCP socket handlers
*****************************************************************************/
-#ifndef __SOCKET_H__
-#define __SOCKET_H__
+#ifndef __NAS_COMMON_UTIL_SOCKET__H__
+#define __NAS_COMMON_UTIL_SOCKET__H__
#include <sys/types.h>
@@ -71,4 +71,4 @@ ssize_t socket_send(const void* id, const char* buffer, size_t length);
void socket_close(void* id);
-#endif /* __SOCKET_H__*/
+#endif /* __NAS_COMMON_UTIL_SOCKET__H__ */
diff --git a/openair3/NAS/COMMON/commonDef.h b/openair3/NAS/COMMON/commonDef.h
deleted file mode 100644
index e9f769db5555246ecf24aa1ffa6c2ded2e8e799c..0000000000000000000000000000000000000000
--- a/openair3/NAS/COMMON/commonDef.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright (c) 2015, EURECOM (www.eurecom.fr)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * The views and conclusions contained in the software and documentation are those
- * of the authors and should not be interpreted as representing official policies,
- * either expressed or implied, of the FreeBSD Project.
- */
-/*
-
-Source commonDef.h
-
-Version 0.1
-
-Date 2012/02/27
-
-Product NAS stack
-
-Subsystem include
-
-Author Frederic Maurel
-
-Description Contains global common definitions
-
-*****************************************************************************/
-#ifndef __COMMONDEF_H__
-#define __COMMONDEF_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <stdbool.h>
-
-typedef signed char boolean_t;
-
-#if !defined(TRUE)
-#define TRUE (boolean_t)0x01
-#endif
-
-#if !defined(FALSE)
-#define FALSE (boolean_t)0x00
-#endif
-
-#define BOOL_NOT(b) (b^TRUE)
-
-#define NAS_UE_ID_FMT "0x%06x"
-
-/****************************************************************************/
-/********************* G L O B A L C O N S T A N T S *******************/
-/****************************************************************************/
-
-#define RETURNok (0)
-#define RETURNerror (-1)
-
-/*
- * Name of the environment variable which defines the default directory
- * where the NAS application is executed and where are located files
- * where non-volatile data are stored
- */
-#define DEFAULT_NAS_PATH "PWD"
-
-/****************************************************************************/
-/************************ G L O B A L T Y P E S ************************/
-/****************************************************************************/
-
-/*
------------------------------------------------------------------------------
- Standard data type definitions
------------------------------------------------------------------------------
-*/
-typedef int8_t SByte_t; /* 8 bit signed integer */
-typedef uint8_t Byte_t; /* 8 bit unsigned integer */
-
-
-/*
------------------------------------------------------------------------------
- Common NAS data type definitions
------------------------------------------------------------------------------
-*/
-
-typedef uint8_t Stat_t; /* Registration status */
-typedef uint16_t lac_t; /* Location Area Code */
-typedef uint8_t rac_t; /* Routing Area Code */
-typedef uint16_t tac_t; /* Tracking Area Code */
-typedef uint32_t ci_t; /* Cell Identifier */
-typedef uint8_t AcT_t; /* Access Technology */
-
-/*
- * International Mobile Subscriber Identity
- */
-typedef struct {
- Byte_t length;
- union {
- struct {
- Byte_t digit2:4;
- Byte_t digit1:4;
- Byte_t digit4:4;
- Byte_t digit3:4;
- Byte_t digit6:4;
- Byte_t digit5:4;
- Byte_t digit8:4;
- Byte_t digit7:4;
- Byte_t digit10:4;
- Byte_t digit9:4;
- Byte_t digit12:4;
- Byte_t digit11:4;
- Byte_t digit14:4;
- Byte_t digit13:4;
-#define EVEN_PARITY 0
-#define ODD_PARITY 1
- Byte_t parity:4;
- Byte_t digit15:4;
- } num;
-#define IMSI_SIZE 8
- Byte_t value[IMSI_SIZE];
- } u;
-} imsi_t;
-
-#define NAS_IMSI2STR(iMsI_t_PtR,iMsI_sTr, MaXlEn) \
- {\
- int l_offset = 0;\
- int l_ret = 0;\
- l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u%u%u%u%u",\
- iMsI_t_PtR->u.num.digit1, iMsI_t_PtR->u.num.digit2,\
- iMsI_t_PtR->u.num.digit3, iMsI_t_PtR->u.num.digit4,\
- iMsI_t_PtR->u.num.digit5);\
- if ((iMsI_t_PtR->u.num.digit6 != 0xf) && (l_ret > 0)) {\
- l_offset += l_ret;\
- l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u", iMsI_t_PtR->u.num.digit6);\
- }\
- if (l_ret > 0) {\
- l_offset += l_ret;\
- l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u%u%u%u%u%u%u%u",\
- iMsI_t_PtR->u.num.digit7, iMsI_t_PtR->u.num.digit8,\
- iMsI_t_PtR->u.num.digit9, iMsI_t_PtR->u.num.digit10,\
- iMsI_t_PtR->u.num.digit11, iMsI_t_PtR->u.num.digit12,\
- iMsI_t_PtR->u.num.digit13, iMsI_t_PtR->u.num.digit14);\
- }\
- if ((iMsI_t_PtR->u.num.digit15 != 0xf) && (l_ret > 0)) {\
- l_offset += l_ret;\
- l_ret = snprintf(iMsI_sTr + l_offset, MaXlEn - l_offset, "%u", iMsI_t_PtR->u.num.digit15);\
- }\
- }
-
-/*
- * Mobile subscriber dialing number
- */
-typedef struct {
- Byte_t ext:1;
- /* Type Of Number */
-#define MSISDN_TON_UNKNOWKN 0b000
-#define MSISDN_TON_INTERNATIONAL 0b001
-#define MSISDN_TON_NATIONAL 0b010
-#define MSISDN_TON_NETWORK 0b011
-#define MSISDN_TON_SUBCRIBER 0b100
-#define MSISDN_TON_ABBREVIATED 0b110
-#define MSISDN_TON_RESERVED 0b111
- Byte_t ton:3;
- /* Numbering Plan Identification */
-#define MSISDN_NPI_UNKNOWN 0b0000
-#define MSISDN_NPI_ISDN_TELEPHONY 0b0001
-#define MSISDN_NPI_GENERIC 0b0010
-#define MSISDN_NPI_DATA 0b0011
-#define MSISDN_NPI_TELEX 0b0100
-#define MSISDN_NPI_MARITIME_MOBILE 0b0101
-#define MSISDN_NPI_LAND_MOBILE 0b0110
-#define MSISDN_NPI_ISDN_MOBILE 0b0111
-#define MSISDN_NPI_PRIVATE 0b1110
-#define MSISDN_NPI_RESERVED 0b1111
- Byte_t npi:4;
- /* Dialing Number */
- struct {
- Byte_t lsb:4;
- Byte_t msb:4;
-#define MSISDN_DIGIT_SIZE 10
- } digit[MSISDN_DIGIT_SIZE];
-} msisdn_t;
-
-/*
- * International Mobile Equipment Identity
- */
-typedef imsi_t imei_t;
-
-/*
- * Public Land Mobile Network identifier
- * PLMN = BCD encoding (Mobile Country Code + Mobile Network Code)
- */
-typedef struct {
- Byte_t MCCdigit2:4;
- Byte_t MCCdigit1:4;
- Byte_t MNCdigit3:4;
- Byte_t MCCdigit3:4;
- Byte_t MNCdigit2:4;
- Byte_t MNCdigit1:4;
-} plmn_t;
-
-/*
- * Location Area Identification
- */
-typedef struct {
- plmn_t plmn; /* <MCC> + <MNC> */
- lac_t lac; /* Location Area Code */
-} lai_t;
-
-/*
- * GPRS Routing Area Identification
- */
-typedef struct {
- plmn_t plmn; /* <MCC> + <MNC> */
- lac_t lac; /* Location Area Code */
- rac_t rac; /* Routing Area Code */
-} RAI_t;
-
-/*
- * EPS Tracking Area Identification
- */
-typedef struct {
- plmn_t plmn; /* <MCC> + <MNC> */
- tac_t tac; /* Tracking Area Code */
-} tai_t;
-
-/*
- * EPS Globally Unique MME Identity
- */
-typedef struct {
- plmn_t plmn; /* <MCC> + <MNC> */
- uint16_t MMEgid; /* MME group identifier */
- uint8_t MMEcode; /* MME code */
-} gummei_t;
-
-/*
- * EPS Globally Unique Temporary UE Identity
- */
-typedef struct {
- gummei_t gummei; /* Globally Unique MME Identity */
- uint32_t m_tmsi; /* M-Temporary Mobile Subscriber Identity */
-} GUTI_t;
-#define GUTI2STR(GuTi_PtR, GuTi_StR, MaXlEn) \
- {\
- int l_offset = 0;\
- int l_ret = 0;\
- l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%03u.",\
- GuTi_PtR->gummei.plmn.MCCdigit3 * 100 +\
- GuTi_PtR->gummei.plmn.MCCdigit2 * 10 +\
- GuTi_PtR->gummei.plmn.MCCdigit1);\
- if (l_ret > 0) {\
- l_offset += l_ret;\
- } else {\
- l_offset = MaXlEn;\
- }\
- if (GuTi_PtR->gummei.plmn.MNCdigit1 != 0xf) {\
- l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%03u|%04x|%02x|%08x",\
- GuTi_PtR->gummei.plmn.MNCdigit3 * 100 +\
- GuTi_PtR->gummei.plmn.MNCdigit2 * 10 +\
- GuTi_PtR->gummei.plmn.MNCdigit1,\
- GuTi_PtR->gummei.MMEgid,\
- GuTi_PtR->gummei.MMEcode,\
- GuTi_PtR->m_tmsi);\
- } else {\
- l_ret += snprintf(GuTi_StR + l_offset,MaXlEn-l_offset, "%02u|%04x|%02x|%08x",\
- GuTi_PtR->gummei.plmn.MNCdigit2 * 10 +\
- GuTi_PtR->gummei.plmn.MNCdigit1,\
- GuTi_PtR->gummei.MMEgid,\
- GuTi_PtR->gummei.MMEcode,\
- GuTi_PtR->m_tmsi);\
- }\
- }
-
-
-
-
-/* Checks PLMN validity */
-#define PLMN_IS_VALID(plmn) (((plmn).MCCdigit1 & \
- (plmn).MCCdigit2 & \
- (plmn).MCCdigit3) != 0x0F)
-
-/* Checks TAC validity */
-#define TAC_IS_VALID(tac) (((tac) != 0x0000) && ((tac) != 0xFFF0))
-
-/* Checks TAI validity */
-#define TAI_IS_VALID(tai) (PLMN_IS_VALID((tai).plmn) && \
- TAC_IS_VALID((tai).tac))
-/*
- * A list of PLMNs
- */
-#define PLMN_LIST_T(SIZE) struct {Byte_t n_plmns; plmn_t plmn[SIZE];}
-
-/*
- * A list of TACs
- */
-#define TAC_LIST_T(SIZE) struct {Byte_t n_tacs; TAC_t tac[SIZE];}
-
-/*
- * A list of TAIs
- */
-#define TAI_LIST_T(SIZE) struct {Byte_t n_tais; tai_t tai[SIZE];}
-
-typedef enum eps_protocol_discriminator_e {
- /* Protocol discriminator identifier for EPS Mobility Management */
- EPS_MOBILITY_MANAGEMENT_MESSAGE = 0x7,
-
- /* Protocol discriminator identifier for EPS Session Management */
- EPS_SESSION_MANAGEMENT_MESSAGE = 0x2,
-} eps_protocol_discriminator_t;
-
-/****************************************************************************/
-/******************** G L O B A L V A R I A B L E S ********************/
-/****************************************************************************/
-
-/****************************************************************************/
-/****************** E X P O R T E D F U N C T I O N S ******************/
-/****************************************************************************/
-
-#endif /* __COMMONDEF_H__*/
diff --git a/openair3/NAS/COMMON/networkDef.h b/openair3/NAS/COMMON/networkDef.h
deleted file mode 100644
index 5390eac2f0ba1d7be6cd59d311d4ab2358967a4b..0000000000000000000000000000000000000000
--- a/openair3/NAS/COMMON/networkDef.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2015, EURECOM (www.eurecom.fr)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * The views and conclusions contained in the software and documentation are those
- * of the authors and should not be interpreted as representing official policies,
- * either expressed or implied, of the FreeBSD Project.
- */
-
-/*****************************************************************************
-
-Source networkDef.h
-
-Version 0.1
-
-Date 2012/09/21
-
-Product NAS stack
-
-Subsystem include
-
-Author Frederic Maurel
-
-Description Contains network's global definitions
-
-*****************************************************************************/
-#ifndef __NETWORKDEF_H__
-#define __NETWORKDEF_H__
-
-/****************************************************************************/
-/********************* G L O B A L C O N S T A N T S *******************/
-/****************************************************************************/
-
-/*
- * ----------------------
- * Network selection mode
- * ----------------------
- */
-#define NET_PLMN_AUTO 0
-#define NET_PLMN_MANUAL 1
-
-/*
- * ---------------------------
- * Network registration status
- * ---------------------------
- */
-/* not registered, not currently searching an operator to register to */
-#define NET_REG_STATE_OFF 0
-/* registered, home network */
-#define NET_REG_STATE_HN 1
-/* not registered, currently trying to attach or searching an operator
- * to register to */
-#define NET_REG_STATE_ON 2
-/* registration denied */
-#define NET_REG_STATE_DENIED 3
-/* unknown (e.g. out of GERAN/UTRAN/E-UTRAN coverage) */
-#define NET_REG_STATE_UNKNOWN 4
-/* registered, roaming */
-#define NET_REG_STATE_ROAMING 5
-/* registered for "SMS only", home network */
-#define NET_REG_STATE_SMS_HN 6
-/* registered, for "SMS only", roaming */
-#define NET_REG_STATE_SMS_ROAMING 7
-/* attached for emergency bearer services only (applicable to UTRAN) */
-#define NET_REG_STATE_EMERGENCY 8
-
-/*
- * ------------------------------------
- * Network access technology indicators
- * ------------------------------------
- */
-#define NET_ACCESS_UNAVAILABLE (-1) /* Not available */
-#define NET_ACCESS_GSM 0 /* GSM */
-#define NET_ACCESS_COMPACT 1 /* GSM Compact */
-#define NET_ACCESS_UTRAN 2 /* UTRAN */
-#define NET_ACCESS_EGPRS 3 /* GSM w/EGPRS */
-#define NET_ACCESS_HSDPA 4 /* UTRAN w/HSDPA */
-#define NET_ACCESS_HSUPA 5 /* UTRAN w/HSUPA */
-#define NET_ACCESS_HSDUPA 6 /* UTRAN w/HSDPA and HSUPA */
-#define NET_ACCESS_EUTRAN 7 /* E-UTRAN */
-
-/*
- * ---------------------------------------
- * Network operator representation formats
- * ---------------------------------------
- */
-#define NET_FORMAT_LONG 0 /* long format alphanumeric */
-#define NET_FORMAT_SHORT 1 /* short format alphanumeric */
-#define NET_FORMAT_NUM 2 /* numeric format */
-
-#define NET_FORMAT_MAX_SIZE NET_FORMAT_LONG_SIZE
-
-/*
- * -----------------------------
- * Network operator availability
- * -----------------------------
- */
-#define NET_OPER_UNKNOWN 0 /* unknown operator */
-#define NET_OPER_AVAILABLE 1 /* available operator */
-#define NET_OPER_CURRENT 2 /* currently selected operator */
-#define NET_OPER_FORBIDDEN 3 /* forbidden operator */
-
-/*
- * --------------------------------------
- * Network connection establishment cause
- * --------------------------------------
- */
-#define NET_ESTABLISH_CAUSE_EMERGENCY 0x01
-#define NET_ESTABLISH_CAUSE_HIGH_PRIO 0x02
-#define NET_ESTABLISH_CAUSE_MT_ACCESS 0x03
-#define NET_ESTABLISH_CAUSE_MO_SIGNAL 0x04
-#define NET_ESTABLISH_CAUSE_MO_DATA 0x05
-#define NET_ESTABLISH_CAUSE_V1020 0x06
-
-/*
- * --------------------------------------
- * Network connection establishment type
- * --------------------------------------
- */
-#define NET_ESTABLISH_TYPE_ORIGINATING_SIGNAL 0x10
-#define NET_ESTABLISH_TYPE_EMERGENCY_CALLS 0x20
-#define NET_ESTABLISH_TYPE_ORIGINATING_CALLS 0x30
-#define NET_ESTABLISH_TYPE_TERMINATING_CALLS 0x40
-#define NET_ESTABLISH_TYPE_MO_CS_FALLBACK 0x50
-
-/*
- * -------------------
- * PDN connection type
- * -------------------
- */
-#define NET_PDN_TYPE_IPV4 (0 + 1)
-#define NET_PDN_TYPE_IPV6 (1 + 1)
-#define NET_PDN_TYPE_IPV4V6 (2 + 1)
-
-/****************************************************************************/
-/************************ G L O B A L T Y P E S ************************/
-/****************************************************************************/
-
-/*
- * ---------------------
- * PDN connection status
- * ---------------------
- */
-typedef enum {
- /* MT = The Mobile Terminal, NW = The Network */
- NET_PDN_MT_DEFAULT_ACT = 1, /* MT has activated a PDN connection */
- NET_PDN_NW_DEFAULT_DEACT, /* NW has deactivated a PDN connection */
- NET_PDN_MT_DEFAULT_DEACT, /* MT has deactivated a PDN connection */
- NET_PDN_NW_DEDICATED_ACT, /* NW has activated an EPS bearer context */
- NET_PDN_MT_DEDICATED_ACT, /* MT has activated an EPS bearer context */
- NET_PDN_NW_DEDICATED_DEACT, /* NW has deactivated an EPS bearer context */
- NET_PDN_MT_DEDICATED_DEACT, /* MT has deactivated an EPS bearer context */
-} network_pdn_state_t;
-
-/*
- * ---------------------------
- * Network operator identifier
- * ---------------------------
- */
-typedef struct {
-#define NET_FORMAT_LONG_SIZE 16 /* Long alphanumeric format */
-#define NET_FORMAT_SHORT_SIZE 8 /* Short alphanumeric format */
-#define NET_FORMAT_NUM_SIZE 6 /* Numeric format (PLMN identifier */
- union {
- unsigned char alpha_long[NET_FORMAT_LONG_SIZE+1];
- unsigned char alpha_short[NET_FORMAT_SHORT_SIZE+1];
- unsigned char num[NET_FORMAT_NUM_SIZE+1];
- } id;
-} network_plmn_t;
-
-/*
- * -------------------------------
- * EPS bearer level QoS parameters
- * -------------------------------
- */
-typedef struct {
- int gbrUL; /* Guaranteed Bit Rate for uplink */
- int gbrDL; /* Guaranteed Bit Rate for downlink */
- int mbrUL; /* Maximum Bit Rate for uplink */
- int mbrDL; /* Maximum Bit Rate for downlink */
- int qci; /* QoS Class Identifier */
-} network_qos_t;
-
-/*
- * -----------------------------
- * IPv4 packet filter parameters
- * -----------------------------
- */
-typedef struct {
- unsigned char protocol; /* Protocol identifier */
- unsigned char tos; /* Type of service */
-#define NET_PACKET_FILTER_IPV4_ADDR_SIZE 4
- unsigned char addr[NET_PACKET_FILTER_IPV4_ADDR_SIZE];
- unsigned char mask[NET_PACKET_FILTER_IPV4_ADDR_SIZE];
-} network_ipv4_data_t;
-
-/*
- * -----------------------------
- * IPv6 packet filter parameters
- * -----------------------------
- */
-typedef struct {
- unsigned char nh; /* Next header type */
- unsigned char tf; /* Traffic class */
-#define NET_PACKET_FILTER_IPV6_ADDR_SIZE 16
- unsigned char addr[NET_PACKET_FILTER_IPV6_ADDR_SIZE];
- unsigned char mask[NET_PACKET_FILTER_IPV6_ADDR_SIZE];
- unsigned int ipsec; /* IPSec security parameter index */
- unsigned int fl; /* Flow label */
-} network_ipv6_data_t;
-
-/*
- * -------------
- * Packet Filter
- * -------------
- */
-typedef struct {
- unsigned char id; /* Packet filter identifier */
-#define NET_PACKET_FILTER_DOWNLINK 0x01
-#define NET_PACKET_FILTER_UPLINK 0x02
-#define NET_PACKET_FILTER_BIDIR 0x03
- unsigned char dir; /* Packet filter direction */
- unsigned char precedence; /* Evaluation precedence */
- union {
- network_ipv4_data_t ipv4;
- network_ipv6_data_t ipv6;
- } data;
- unsigned short lport; /* Local (UE) port number */
- unsigned short rport; /* Remote (network) port number */
-} network_pkf_t;
-
-/*
- * ---------------------
- * Traffic Flow Template
- * ---------------------
- */
-typedef struct {
- int n_pkfs;
-#define NET_PACKET_FILTER_MAX 16
- network_pkf_t* pkf[NET_PACKET_FILTER_MAX];
-} network_tft_t;
-
-/****************************************************************************/
-/******************** G L O B A L V A R I A B L E S ********************/
-/****************************************************************************/
-
-/****************************************************************************/
-/****************** E X P O R T E D F U N C T I O N S ******************/
-/****************************************************************************/
-
-#endif /* __NETWORKDEF_H__*/
diff --git a/openair3/NAS/TEST/USER/user_parser.h b/openair3/NAS/TEST/USER/user_parser.h
index d1972de02894dbf80ec04f9c5d5d60d80501ca5c..e7fc07ee329a6e61fcdeda20e74fdc334a1c9975 100644
--- a/openair3/NAS/TEST/USER/user_parser.h
+++ b/openair3/NAS/TEST/USER/user_parser.h
@@ -39,8 +39,8 @@ Description Command line parser of the user simulator process
*****************************************************************************/
-#ifndef __USER_PARSER_H__
-#define __USER_PARSER__H__
+#ifndef __NAS_TEST_USER_USER_PARSER__H__
+#define __NAS_TEST_USER_USER_PARSER__H__
/****************************************************************************/
/********************* G L O B A L C O N S T A N T S *******************/
@@ -74,4 +74,4 @@ const char* user_parser_get_port(void);
const char* user_parser_get_devpath(void);
const char* user_parser_get_devattr(void);
-#endif /* __USER_PARSER_H__*/
+#endif /* __NAS_TEST_USER_USER_PARSER__H__ */
diff --git a/openair3/NAS/TOOLS/conf_network.c b/openair3/NAS/TOOLS/conf_network.c
index 7e71c9b4ee79cafbd68404350195e3c4dec18975..054189a130c949e4d132c04e9c72bf0b7cf22d49 100644
--- a/openair3/NAS/TOOLS/conf_network.c
+++ b/openair3/NAS/TOOLS/conf_network.c
@@ -43,7 +43,7 @@ void gen_network_record_from_conf(const plmn_conf_param_t *conf, network_record_
strcpy(record->fullname, conf->fullname);
strcpy(record->shortname, conf->shortname);
- char num[6];
+ char num[60];
sprintf(num, "%s%s", conf->mcc, conf->mnc);
record->num = atoi(num);
diff --git a/openair3/S1AP/s1ap_eNB.c b/openair3/S1AP/s1ap_eNB.c
index 3592cf80a14ef7d2e52f87b3b3112cf4558b38a2..c70350184706913a3baeb092ae9e8ab698f01cf2 100644
--- a/openair3/S1AP/s1ap_eNB.c
+++ b/openair3/S1AP/s1ap_eNB.c
@@ -69,7 +69,6 @@ s1ap_eNB_config_t s1ap_config;
static int s1ap_eNB_generate_s1_setup_request(
s1ap_eNB_instance_t *instance_p, s1ap_eNB_mme_data_t *s1ap_mme_data_p);
-
void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *s1ap_register_eNB);
void s1ap_eNB_handle_sctp_association_resp(instance_t instance, sctp_new_association_resp_t *sctp_new_association_resp);
@@ -221,8 +220,21 @@ void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *
/* Trying to connect to provided list of MME ip address */
for (index = 0; index < s1ap_register_eNB->nb_mme; index++) {
+ net_ip_address_t *mme_ip = &s1ap_register_eNB->mme_ip_address[index];
+ struct s1ap_eNB_mme_data_s *mme = NULL;
+ RB_FOREACH(mme, s1ap_mme_map, &new_instance->s1ap_mme_head) {
+ /* Compare whether IPv4 and IPv6 information is already present, in which
+ * wase we do not register again */
+ if (mme->mme_s1_ip.ipv4 == mme_ip->ipv4 && (!mme_ip->ipv4
+ || strncmp(mme->mme_s1_ip.ipv4_address, mme_ip->ipv4_address, 16) == 0)
+ && mme->mme_s1_ip.ipv6 == mme_ip->ipv6 && (!mme_ip->ipv6
+ || strncmp(mme->mme_s1_ip.ipv6_address, mme_ip->ipv6_address, 46) == 0))
+ break;
+ }
+ if (mme)
+ continue;
s1ap_eNB_register_mme(new_instance,
- &s1ap_register_eNB->mme_ip_address[index],
+ mme_ip,
&s1ap_register_eNB->enb_ip_address,
s1ap_register_eNB->sctp_in_streams,
s1ap_register_eNB->sctp_out_streams,
@@ -361,6 +373,12 @@ void *s1ap_eNB_process_itti_msg(void *notUsed) {
}
break;
+ case S1AP_E_RAB_MODIFICATION_IND: {
+ s1ap_eNB_generate_E_RAB_Modification_Indication(ITTI_MESSAGE_GET_INSTANCE(received_msg),
+ &S1AP_E_RAB_MODIFICATION_IND(received_msg));
+ }
+ break;
+
case S1AP_UE_CONTEXT_RELEASE_COMPLETE: {
s1ap_ue_context_release_complete(ITTI_MESSAGE_GET_INSTANCE(received_msg),
&S1AP_UE_CONTEXT_RELEASE_COMPLETE(received_msg));
@@ -508,3 +526,7 @@ static int s1ap_eNB_generate_s1_setup_request(
s1ap_eNB_itti_send_sctp_data_req(instance_p->instance, s1ap_mme_data_p->assoc_id, buffer, len, 0);
return ret;
}
+
+
+
+
diff --git a/openair3/S1AP/s1ap_eNB_decoder.c b/openair3/S1AP/s1ap_eNB_decoder.c
index 3eb182b159db73c3d981cd9078deebdf528f92e0..4635946a059446a3a9af91bab78e00e07de32773 100644
--- a/openair3/S1AP/s1ap_eNB_decoder.c
+++ b/openair3/S1AP/s1ap_eNB_decoder.c
@@ -112,6 +112,12 @@ static int s1ap_eNB_decode_successful_outcome(S1AP_S1AP_PDU_t *pdu) {
free(res.buffer);
break;
+ case S1AP_ProcedureCode_id_E_RABModificationIndication:
+ res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu);
+ free(res.buffer);
+ break;
+
+
default:
S1AP_ERROR("Unknown procedure ID (%d) for successfull outcome message\n",
(int)pdu->choice.successfulOutcome.procedureCode);
diff --git a/openair3/S1AP/s1ap_eNB_encoder.c b/openair3/S1AP/s1ap_eNB_encoder.c
index 0cd46214fc050997b06144af12deb77e4a2d3c39..227a3cb6a991d9ecc3f3211818f189b50a955ecb 100644
--- a/openair3/S1AP/s1ap_eNB_encoder.c
+++ b/openair3/S1AP/s1ap_eNB_encoder.c
@@ -118,6 +118,11 @@ int s1ap_eNB_encode_initiating(S1AP_S1AP_PDU_t *pdu,
free(res.buffer);
break;
+ case S1AP_ProcedureCode_id_E_RABModificationIndication:
+ res = asn_encode_to_new_buffer(NULL, ATS_CANONICAL_XER, &asn_DEF_S1AP_S1AP_PDU, pdu);
+ free(res.buffer);
+ break;
+
default:
S1AP_DEBUG("Unknown procedure ID (%d) for initiating message\n",
(int)pdu->choice.initiatingMessage.procedureCode);
diff --git a/openair3/S1AP/s1ap_eNB_handlers.c b/openair3/S1AP/s1ap_eNB_handlers.c
index 87abc1ede974206d84044a919937febd1e43d4e1..28ee11187ee6f0cbe588ffd555a290c6cfd09e9d 100644
--- a/openair3/S1AP/s1ap_eNB_handlers.c
+++ b/openair3/S1AP/s1ap_eNB_handlers.c
@@ -104,6 +104,11 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_
uint32_t stream,
S1AP_S1AP_PDU_t *pdu);
+static
+int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id,
+ uint32_t stream,
+ S1AP_S1AP_PDU_t *pdu);
+
/* Handlers matrix. Only eNB related procedure present here */
s1ap_message_decoded_callback messages_callback[][3] = {
{ 0, 0, 0 }, /* HandoverPreparation */
@@ -154,6 +159,9 @@ s1ap_message_decoded_callback messages_callback[][3] = {
{ 0, 0, 0 }, /* UplinkUEAssociatedLPPaTransport */
{ 0, 0, 0 }, /* DownlinkNonUEAssociatedLPPaTransport */
{ 0, 0, 0 }, /* UplinkNonUEAssociatedLPPaTransport */
+ { 0, 0, 0 }, /* UERadioCapabilityMatch */
+ { 0, 0, 0 }, /* PWSRestartIndication */
+ { 0, s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm, 0 }, /* E_RABModificationIndication */
};
char *s1ap_direction2String(int s1ap_dir) {
static char *s1ap_direction_String[] = {
@@ -1722,3 +1730,13 @@ int s1ap_eNB_handle_s1_path_switch_request_failure(uint32_t assoc_
// TODO continue
return 0;
}
+
+static
+int s1ap_eNB_handle_s1_ENDC_e_rab_modification_confirm(uint32_t assoc_id,
+ uint32_t stream,
+ S1AP_S1AP_PDU_t *pdu){
+
+ LOG_W(S1AP, "Implementation of S1AP E-RAB Modification confirm handler is pending...\n");
+ return 0;
+}
+
diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.c b/openair3/S1AP/s1ap_eNB_nas_procedures.c
index d271ddf6bad6c884daacc3874f30bf9e03b02229..c668e32d1ba912c770bae4b431fd7dfcd163b573 100644
--- a/openair3/S1AP/s1ap_eNB_nas_procedures.c
+++ b/openair3/S1AP/s1ap_eNB_nas_procedures.c
@@ -1620,3 +1620,319 @@ int s1ap_eNB_path_switch_req(instance_t instance,
return ret;
}
+
+
+//-----------------------------------------------------------------------------
+/*
+* eNB generate a S1 E_RAB Modification Indication towards MME
+*/
+/*int s1ap_eNB_generate_E_RAB_Modification_Indication(
+ instance_t instance,
+ s1ap_e_rab_modification_ind_t *e_rab_modification_ind)
+//-----------------------------------------------------------------------------
+{
+ struct s1ap_eNB_ue_context_s *ue_context_p = NULL;
+ S1AP_S1AP_PDU_t pdu;
+ S1AP_E_RABModificationIndication_t *out = NULL;
+ S1AP_E_RABModificationIndicationIEs_t *ie = NULL;
+ S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL;
+ S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL;
+
+ S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL;
+ S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL;
+
+
+ s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL;
+ s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance);
+ uint8_t *buffer = NULL;
+ uint32_t len = 0;
+ int ret = 0;
+ DevAssert(s1ap_eNB_instance_p != NULL);
+ DevAssert(e_rab_modification_ind != NULL);
+
+ int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified;
+ int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified;
+
+ uint32_t CSG_id = 0;
+
+ if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p,
+ e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) {
+ // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs
+ S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n",
+ e_rab_modification_ind->eNB_ue_s1ap_id);
+ return -1;
+ }
+
+ // Prepare the S1AP message to encode
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage;
+ pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication;
+ pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject;
+ pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication;
+ out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication;
+ // mandatory
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID;
+ ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID;
+ ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ //E-RABs to be modified list
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd;
+
+ //The following two for-loops here will probably need to change. We should do a different type of search
+ for(int i=0; i<num_e_rabs_tobemodified; i++){
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs = (S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *)calloc(1,sizeof(S1AP_E_RABToBeModifiedItemBearerModIndIEs_t));
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd;
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject;
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd;
+ E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd;
+
+ {
+ E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id;
+
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8;
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8;
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+ memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer,
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+
+ INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID);
+
+ }
+ ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs);
+ }
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ //E-RABs NOT to be modified list
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd;
+ ie->criticality = S1AP_Criticality_reject;
+ if(num_e_rabs_nottobemodified > 0) {
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd;
+
+ for(int i=0; i<num_e_rabs_nottobemodified; i++){
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs = (S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *)calloc(1,sizeof(S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t));
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd;
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject;
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd;
+ E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd;
+
+ {
+ E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_nottobemodified[i].e_rab_id;
+
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length/8;
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.length%8;
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf =
+ calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+ memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_nottobemodified[i].eNB_addr.buffer,
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+
+ INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_nottobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID);
+
+ }
+ ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs);
+ }
+ }
+ else{
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd;
+ ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0;
+ }
+
+
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo;
+ ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member;
+ INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id);
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+
+ if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) {
+ S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n");
+ return -1;
+ }
+
+ // Non UE-Associated signalling -> stream = 0
+ S1AP_INFO("Size of encoded message: %d \n", len);
+ s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance,
+ ue_context_p->mme_ref->assoc_id, buffer,
+ len, ue_context_p->tx_stream);
+
+//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0);
+ return ret;
+}*/
+
+int s1ap_eNB_generate_E_RAB_Modification_Indication(
+ instance_t instance,
+ s1ap_e_rab_modification_ind_t *e_rab_modification_ind)
+//-----------------------------------------------------------------------------
+{
+ struct s1ap_eNB_ue_context_s *ue_context_p = NULL;
+ S1AP_S1AP_PDU_t pdu;
+ S1AP_E_RABModificationIndication_t *out = NULL;
+ S1AP_E_RABModificationIndicationIEs_t *ie = NULL;
+ S1AP_E_RABToBeModifiedItemBearerModInd_t *E_RAB_ToBeModifiedItem_BearerModInd = NULL;
+ S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *E_RAB_ToBeModifiedItem_BearerModInd_IEs = NULL;
+
+ //S1AP_E_RABNotToBeModifiedItemBearerModInd_t *E_RAB_NotToBeModifiedItem_BearerModInd = NULL;
+ //S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *E_RAB_NotToBeModifiedItem_BearerModInd_IEs = NULL;
+
+
+ s1ap_eNB_instance_t *s1ap_eNB_instance_p = NULL;
+ s1ap_eNB_instance_p = s1ap_eNB_get_instance(instance);
+ uint8_t *buffer = NULL;
+ uint32_t len = 0;
+ int ret = 0;
+ DevAssert(s1ap_eNB_instance_p != NULL);
+ DevAssert(e_rab_modification_ind != NULL);
+
+ int num_e_rabs_tobemodified = e_rab_modification_ind->nb_of_e_rabs_tobemodified;
+ //int num_e_rabs_nottobemodified = e_rab_modification_ind->nb_of_e_rabs_nottobemodified;
+
+ //uint32_t CSG_id = 0;
+ //uint32_t pseudo_gtp_teid = 10;
+
+ if ((ue_context_p = s1ap_eNB_get_ue_context(s1ap_eNB_instance_p,
+ e_rab_modification_ind->eNB_ue_s1ap_id)) == NULL) {
+ // The context for this eNB ue s1ap id doesn't exist in the map of eNB UEs
+ S1AP_WARN("Failed to find ue context associated with eNB ue s1ap id: 0x%06x\n",
+ e_rab_modification_ind->eNB_ue_s1ap_id);
+ return -1;
+ }
+
+ // Prepare the S1AP message to encode
+ memset(&pdu, 0, sizeof(pdu));
+ pdu.present = S1AP_S1AP_PDU_PR_initiatingMessage;
+ pdu.choice.initiatingMessage.procedureCode = S1AP_ProcedureCode_id_E_RABModificationIndication;
+ pdu.choice.initiatingMessage.criticality = S1AP_Criticality_reject;
+ pdu.choice.initiatingMessage.value.present = S1AP_InitiatingMessage__value_PR_E_RABModificationIndication;
+ out = &pdu.choice.initiatingMessage.value.choice.E_RABModificationIndication;
+ /* mandatory */
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_MME_UE_S1AP_ID;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_MME_UE_S1AP_ID;
+ ie->value.choice.MME_UE_S1AP_ID = e_rab_modification_ind->mme_ue_s1ap_id;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_eNB_UE_S1AP_ID;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_ENB_UE_S1AP_ID;
+ ie->value.choice.ENB_UE_S1AP_ID = e_rab_modification_ind->eNB_ue_s1ap_id;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ //E-RABs to be modified list
+ ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedListBearerModInd;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABToBeModifiedListBearerModInd;
+
+ //The following two for-loops here will probably need to change. We should do a different type of search
+ for(int i=0; i<num_e_rabs_tobemodified; i++){
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs = (S1AP_E_RABToBeModifiedItemBearerModIndIEs_t *)calloc(1,sizeof(S1AP_E_RABToBeModifiedItemBearerModIndIEs_t));
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->id = S1AP_ProtocolIE_ID_id_E_RABToBeModifiedItemBearerModInd;
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject;
+ E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABToBeModifiedItemBearerModIndIEs__value_PR_E_RABToBeModifiedItemBearerModInd;
+ E_RAB_ToBeModifiedItem_BearerModInd = &E_RAB_ToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABToBeModifiedItemBearerModInd;
+
+ {
+ E_RAB_ToBeModifiedItem_BearerModInd->e_RAB_ID = e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id;
+
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8;
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8;
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf = calloc(1, E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+ memcpy (E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer,
+ E_RAB_ToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+
+ INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_ToBeModifiedItem_BearerModInd->dL_GTP_TEID);
+
+ }
+ ASN_SEQUENCE_ADD(&ie->value.choice.E_RABToBeModifiedListBearerModInd.list, E_RAB_ToBeModifiedItem_BearerModInd_IEs);
+ }
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);
+
+ //E-RABs NOT to be modified list
+ /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedListBearerModInd;
+ ie->criticality = S1AP_Criticality_reject;
+ //if(num_e_rabs_nottobemodified > 0) {
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd;
+
+ for(int i=0; i<num_e_rabs_tobemodified; i++){
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs = (S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t *)calloc(1,sizeof(S1AP_E_RABNotToBeModifiedItemBearerModIndIEs_t));
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->id = S1AP_ProtocolIE_ID_id_E_RABNotToBeModifiedItemBearerModInd;
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->criticality = S1AP_Criticality_reject;
+ E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.present = S1AP_E_RABNotToBeModifiedItemBearerModIndIEs__value_PR_E_RABNotToBeModifiedItemBearerModInd;
+ E_RAB_NotToBeModifiedItem_BearerModInd = &E_RAB_NotToBeModifiedItem_BearerModInd_IEs->value.choice.E_RABNotToBeModifiedItemBearerModInd;
+
+ {
+ E_RAB_NotToBeModifiedItem_BearerModInd->e_RAB_ID = 10; //e_rab_modification_ind->e_rabs_tobemodified[i].e_rab_id;
+
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length/8;
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.bits_unused = e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.length%8;
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf =
+ calloc(1, E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+ memcpy (E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.buf, e_rab_modification_ind->e_rabs_tobemodified[i].eNB_addr.buffer,
+ E_RAB_NotToBeModifiedItem_BearerModInd->transportLayerAddress.size);
+
+ //INT32_TO_OCTET_STRING(e_rab_modification_ind->e_rabs_tobemodified[i].gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID);
+ INT32_TO_OCTET_STRING(pseudo_gtp_teid, &E_RAB_NotToBeModifiedItem_BearerModInd->dL_GTP_TEID);
+
+ }
+ ASN_SEQUENCE_ADD(&ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list, E_RAB_NotToBeModifiedItem_BearerModInd_IEs);
+ }
+ // }
+ //else{
+// ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_E_RABNotToBeModifiedListBearerModInd;
+// ie->value.choice.E_RABNotToBeModifiedListBearerModInd.list.size = 0;
+// } /
+
+
+
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/
+
+ /*ie = (S1AP_E_RABModificationIndicationIEs_t *)calloc(1, sizeof(S1AP_E_RABModificationIndicationIEs_t));
+ ie->id = S1AP_ProtocolIE_ID_id_CSGMembershipInfo;
+ ie->criticality = S1AP_Criticality_reject;
+ ie->value.present = S1AP_E_RABModificationIndicationIEs__value_PR_CSGMembershipInfo;
+ ie->value.choice.CSGMembershipInfo.cSGMembershipStatus = S1AP_CSGMembershipStatus_member;
+ INT32_TO_BIT_STRING(CSG_id, &ie->value.choice.CSGMembershipInfo.cSG_Id);
+ ie->value.choice.CSGMembershipInfo.cSG_Id.bits_unused=5;
+ ie->value.choice.CSGMembershipInfo.cellAccessMode = S1AP_CellAccessMode_hybrid;
+ ASN_SEQUENCE_ADD(&out->protocolIEs.list, ie);*/
+
+ if (s1ap_eNB_encode_pdu(&pdu, &buffer, &len) < 0) {
+ S1AP_ERROR("Failed to encode S1 E-RAB modification indication \n");
+ return -1;
+ }
+
+ // Non UE-Associated signalling -> stream = 0
+ S1AP_INFO("Size of encoded message: %d \n", len);
+ s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance,
+ ue_context_p->mme_ref->assoc_id, buffer,
+ len, ue_context_p->tx_stream);
+
+//s1ap_eNB_itti_send_sctp_data_req(s1ap_eNB_instance_p->instance, ue_context_p->mme_ref->assoc_id, buffer, len, 0);
+ return ret;
+}
+
+
diff --git a/openair3/S1AP/s1ap_eNB_nas_procedures.h b/openair3/S1AP/s1ap_eNB_nas_procedures.h
index c4257198727a042cfacd7eeafac65e1dfc36a232..47f71cc795b1230d40990db9f11adfa10709e7e4 100644
--- a/openair3/S1AP/s1ap_eNB_nas_procedures.h
+++ b/openair3/S1AP/s1ap_eNB_nas_procedures.h
@@ -52,4 +52,8 @@ int s1ap_eNB_e_rab_release_resp(instance_t instance,
int s1ap_eNB_path_switch_req(instance_t instance,
s1ap_path_switch_req_t *path_switch_req_p);
+
+int s1ap_eNB_generate_E_RAB_Modification_Indication(
+ instance_t instance, s1ap_e_rab_modification_ind_t *e_rab_modification_ind);
+
#endif /* S1AP_ENB_NAS_PROCEDURES_H_ */
diff --git a/openair3/TEST/oaisim_mme_test_s1c_s1ap.h b/openair3/TEST/oaisim_mme_test_s1c_s1ap.h
index 3633f11e867424c2d4dc904076f99d43aff9f10e..4faec0e66e53085a80175a4383b233c29fec3694 100644
--- a/openair3/TEST/oaisim_mme_test_s1c_s1ap.h
+++ b/openair3/TEST/oaisim_mme_test_s1c_s1ap.h
@@ -19,6 +19,9 @@
* contact@openairinterface.org
*/
+#ifndef __TEST_OAISIM_MME_TEST_S1C_S1AP__H__
+#define __TEST_OAISIM_MME_TEST_S1C_S1AP__H__
+
#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
@@ -53,3 +56,5 @@ void s1ap_eNB_register_mme(s1ap_eNB_instance_t *instance_p,
uint16_t out_streams);
void s1ap_eNB_handle_register_eNB(instance_t instance, s1ap_register_enb_req_t *s1ap_register_eNB);
void *s1ap_eNB_task(void *arg);
+
+#endif
diff --git a/openair3/TEST/oaisim_mme_test_s1c_scenario.h b/openair3/TEST/oaisim_mme_test_s1c_scenario.h
index 8c33f457418e8fa67ba0a84cc940a66634206d7d..8b9a8dd54a14fc74b81f4fa8ba8aecbbaba51ac2 100644
--- a/openair3/TEST/oaisim_mme_test_s1c_scenario.h
+++ b/openair3/TEST/oaisim_mme_test_s1c_scenario.h
@@ -19,6 +19,9 @@
* contact@openairinterface.org
*/
+#ifndef __TEST_OAISIM_MME_TEST_S1C_SCENARIO__H__
+#define __TEST_OAISIM_MME_TEST_S1C_SCENARIO__H__
+
#include <stdlib.h>
#include <stdint.h>
@@ -49,3 +52,5 @@ int compare_buffer(const uint8_t *buffer, const uint32_t length_buffer, con
unsigned decode_hex_length(const char *h);
int decode_hex(uint8_t *dst, const char *h);
uint8_t *decode_hex_dup(const char *hex);
+
+#endif
diff --git a/openair3/UTILS/mme_config.h b/openair3/UTILS/mme_config.h
index 37b7dff8651359e6415351f3deee6bf30f1c70ab..417c8bbd5f44606a3599018ca7700779025c2ce0 100644
--- a/openair3/UTILS/mme_config.h
+++ b/openair3/UTILS/mme_config.h
@@ -19,14 +19,14 @@
* contact@openairinterface.org
*/
+#ifndef __UTILS_MME_CONFIG__H__
+#define __UTILS_MME_CONFIG__H__
+
#include <pthread.h>
#include <stdint.h>
#include "mme_default_values.h"
-#ifndef MME_CONFIG_H_
-#define MME_CONFIG_H_
-
#define MME_CONFIG_STRING_MME_CONFIG "MME"
#define MME_CONFIG_STRING_REALM "REALM"
#define MME_CONFIG_STRING_MAXENB "MAXENB"
@@ -183,4 +183,4 @@ int config_parse_opt_line(int argc, char *argv[], mme_config_t *mme_config);
//int yyparse(struct mme_config_s *mme_config_p);
-#endif /* MME_CONFIG_H_ */
+#endif /* __UTILS_MME_CONFIG__H__ */
diff --git a/openair3/UTILS/queue.h b/openair3/UTILS/queue.h
deleted file mode 100644
index f8665c0f1a37b15fbe2b0c7be54354455b644314..0000000000000000000000000000000000000000
--- a/openair3/UTILS/queue.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Copyright (c) 1991, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)queue.h 8.5 (Berkeley) 8/20/94
- */
-
-#ifndef _SYS_QUEUE_H_
-#define _SYS_QUEUE_H_
-
-/*
- * This file defines five types of data structures: singly-linked lists,
- * lists, simple queues, tail queues, and circular queues.
- *
- * A singly-linked list is headed by a single forward pointer. The
- * elements are singly linked for minimum space and pointer manipulation
- * overhead at the expense of O(n) removal for arbitrary elements. New
- * elements can be added to the list after an existing element or at the
- * head of the list. Elements being removed from the head of the list
- * should use the explicit macro for this purpose for optimum
- * efficiency. A singly-linked list may only be traversed in the forward
- * direction. Singly-linked lists are ideal for applications with large
- * datasets and few or no removals or for implementing a LIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may only be traversed in the forward direction.
- *
- * A simple queue is headed by a pair of pointers, one the head of the
- * list and the other to the tail of the list. The elements are singly
- * linked to save space, so elements can only be removed from the
- * head of the list. New elements can be added to the list after
- * an existing element, at the head of the list, or at the end of the
- * list. A simple queue may only be traversed in the forward direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * A circle queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or after
- * an existing element, at the head of the list, or at the end of the list.
- * A circle queue may be traversed in either direction, but has a more
- * complex end of list detection.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- * SLIST LIST STAILQ TAILQ CIRCLEQ
- * _HEAD + + + + +
- * _HEAD_INITIALIZER + + + + +
- * _ENTRY + + + + +
- * _INIT + + + + +
- * _EMPTY + + + + +
- * _FIRST + + + + +
- * _NEXT + + + + +
- * _PREV - - - + +
- * _LAST - - + + +
- * _FOREACH + + + + +
- * _FOREACH_REVERSE - - - + +
- * _INSERT_HEAD + + + + +
- * _INSERT_BEFORE - + - + +
- * _INSERT_AFTER + + + + +
- * _INSERT_TAIL - - + + +
- * _REMOVE_HEAD + - + - -
- * _REMOVE + + + + +
- */
-
-/*
- * List definitions.
- */
-#define LIST_HEAD(name, type) \
-struct name { \
- struct type *lh_first; /* first element */ \
-}
-
-#define LIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define LIST_ENTRY(type) \
-struct { \
- struct type *le_next; /* next element */ \
- struct type **le_prev; /* address of previous next element */ \
-}
-
-/*
- * List functions.
- */
-#define LIST_INIT(head) do { \
- (head)->lh_first = NULL; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_AFTER(listelm, elm, field) do { \
- if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \
- (listelm)->field.le_next->field.le_prev = \
- &(elm)->field.le_next; \
- (listelm)->field.le_next = (elm); \
- (elm)->field.le_prev = &(listelm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.le_prev = (listelm)->field.le_prev; \
- (elm)->field.le_next = (listelm); \
- *(listelm)->field.le_prev = (elm); \
- (listelm)->field.le_prev = &(elm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.le_next = (head)->lh_first) != NULL) \
- (head)->lh_first->field.le_prev = &(elm)->field.le_next;\
- (head)->lh_first = (elm); \
- (elm)->field.le_prev = &(head)->lh_first; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_REMOVE(elm, field) do { \
- if ((elm)->field.le_next != NULL) \
- (elm)->field.le_next->field.le_prev = \
- (elm)->field.le_prev; \
- *(elm)->field.le_prev = (elm)->field.le_next; \
-} while (/*CONSTCOND*/0)
-
-#define LIST_FOREACH(var, head, field) \
- for ((var) = ((head)->lh_first); \
- (var); \
- (var) = ((var)->field.le_next))
-
-/*
- * List access methods.
- */
-#define LIST_EMPTY(head) ((head)->lh_first == NULL)
-#define LIST_FIRST(head) ((head)->lh_first)
-#define LIST_NEXT(elm, field) ((elm)->field.le_next)
-
-
-/*
- * Singly-linked List definitions.
- */
-#define SLIST_HEAD(name, type) \
-struct name { \
- struct type *slh_first; /* first element */ \
-}
-
-#define SLIST_HEAD_INITIALIZER(head) \
- { NULL }
-
-#define SLIST_ENTRY(type) \
-struct { \
- struct type *sle_next; /* next element */ \
-}
-
-/*
- * Singly-linked List functions.
- */
-#define SLIST_INIT(head) do { \
- (head)->slh_first = NULL; \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \
- (elm)->field.sle_next = (slistelm)->field.sle_next; \
- (slistelm)->field.sle_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_INSERT_HEAD(head, elm, field) do { \
- (elm)->field.sle_next = (head)->slh_first; \
- (head)->slh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_REMOVE_HEAD(head, field) do { \
- (head)->slh_first = (head)->slh_first->field.sle_next; \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_REMOVE(head, elm, type, field) do { \
- if ((head)->slh_first == (elm)) { \
- SLIST_REMOVE_HEAD((head), field); \
- } \
- else { \
- struct type *curelm = (head)->slh_first; \
- while(curelm->field.sle_next != (elm)) \
- curelm = curelm->field.sle_next; \
- curelm->field.sle_next = \
- curelm->field.sle_next->field.sle_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define SLIST_FOREACH(var, head, field) \
- for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next)
-
-/*
- * Singly-linked List access methods.
- */
-#define SLIST_EMPTY(head) ((head)->slh_first == NULL)
-#define SLIST_FIRST(head) ((head)->slh_first)
-#define SLIST_NEXT(elm, field) ((elm)->field.sle_next)
-
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define STAILQ_HEAD(name, type) \
-struct name { \
- struct type *stqh_first; /* first element */ \
- struct type **stqh_last; /* addr of last next element */ \
-}
-
-#define STAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).stqh_first }
-
-#define STAILQ_ENTRY(type) \
-struct { \
- struct type *stqe_next; /* next element */ \
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define STAILQ_INIT(head) do { \
- (head)->stqh_first = NULL; \
- (head)->stqh_last = &(head)->stqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) \
- (head)->stqh_last = &(elm)->field.stqe_next; \
- (head)->stqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.stqe_next = NULL; \
- *(head)->stqh_last = (elm); \
- (head)->stqh_last = &(elm)->field.stqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\
- (head)->stqh_last = &(elm)->field.stqe_next; \
- (listelm)->field.stqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_REMOVE_HEAD(head, field) do { \
- if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \
- (head)->stqh_last = &(head)->stqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_REMOVE(head, elm, type, field) do { \
- if ((head)->stqh_first == (elm)) { \
- STAILQ_REMOVE_HEAD((head), field); \
- } else { \
- struct type *curelm = (head)->stqh_first; \
- while (curelm->field.stqe_next != (elm)) \
- curelm = curelm->field.stqe_next; \
- if ((curelm->field.stqe_next = \
- curelm->field.stqe_next->field.stqe_next) == NULL) \
- (head)->stqh_last = &(curelm)->field.stqe_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define STAILQ_FOREACH(var, head, field) \
- for ((var) = ((head)->stqh_first); \
- (var); \
- (var) = ((var)->field.stqe_next))
-
-#define STAILQ_CONCAT(head1, head2) do { \
- if (!STAILQ_EMPTY((head2))) { \
- *(head1)->stqh_last = (head2)->stqh_first; \
- (head1)->stqh_last = (head2)->stqh_last; \
- STAILQ_INIT((head2)); \
- } \
-} while (/*CONSTCOND*/0)
-
-/*
- * Singly-linked Tail queue access methods.
- */
-#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL)
-#define STAILQ_FIRST(head) ((head)->stqh_first)
-#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
-
-
-/*
- * Simple queue definitions.
- */
-#define SIMPLEQ_HEAD(name, type) \
-struct name { \
- struct type *sqh_first; /* first element */ \
- struct type **sqh_last; /* addr of last next element */ \
-}
-
-#define SIMPLEQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).sqh_first }
-
-#define SIMPLEQ_ENTRY(type) \
-struct { \
- struct type *sqe_next; /* next element */ \
-}
-
-/*
- * Simple queue functions.
- */
-#define SIMPLEQ_INIT(head) do { \
- (head)->sqh_first = NULL; \
- (head)->sqh_last = &(head)->sqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
- (head)->sqh_last = &(elm)->field.sqe_next; \
- (head)->sqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.sqe_next = NULL; \
- *(head)->sqh_last = (elm); \
- (head)->sqh_last = &(elm)->field.sqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
- (head)->sqh_last = &(elm)->field.sqe_next; \
- (listelm)->field.sqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_REMOVE_HEAD(head, field) do { \
- if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
- (head)->sqh_last = &(head)->sqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_REMOVE(head, elm, type, field) do { \
- if ((head)->sqh_first == (elm)) { \
- SIMPLEQ_REMOVE_HEAD((head), field); \
- } else { \
- struct type *curelm = (head)->sqh_first; \
- while (curelm->field.sqe_next != (elm)) \
- curelm = curelm->field.sqe_next; \
- if ((curelm->field.sqe_next = \
- curelm->field.sqe_next->field.sqe_next) == NULL) \
- (head)->sqh_last = &(curelm)->field.sqe_next; \
- } \
-} while (/*CONSTCOND*/0)
-
-#define SIMPLEQ_FOREACH(var, head, field) \
- for ((var) = ((head)->sqh_first); \
- (var); \
- (var) = ((var)->field.sqe_next))
-
-/*
- * Simple queue access methods.
- */
-#define SIMPLEQ_EMPTY(head) ((head)->sqh_first == NULL)
-#define SIMPLEQ_FIRST(head) ((head)->sqh_first)
-#define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
-
-
-/*
- * Tail queue definitions.
- */
-#define _TAILQ_HEAD(name, type, qual) \
-struct name { \
- qual type *tqh_first; /* first element */ \
- qual type *qual *tqh_last; /* addr of last next element */ \
-}
-#define TAILQ_HEAD(name, type) _TAILQ_HEAD(name, struct type,)
-
-#define TAILQ_HEAD_INITIALIZER(head) \
- { NULL, &(head).tqh_first }
-
-#define _TAILQ_ENTRY(type, qual) \
-struct { \
- qual type *tqe_next; /* next element */ \
- qual type *qual *tqe_prev; /* address of previous next element */\
-}
-#define TAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,)
-
-/*
- * Tail queue functions.
- */
-#define TAILQ_INIT(head) do { \
- (head)->tqh_first = NULL; \
- (head)->tqh_last = &(head)->tqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_HEAD(head, elm, field) do { \
- if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
- (head)->tqh_first->field.tqe_prev = \
- &(elm)->field.tqe_next; \
- else \
- (head)->tqh_last = &(elm)->field.tqe_next; \
- (head)->tqh_first = (elm); \
- (elm)->field.tqe_prev = &(head)->tqh_first; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.tqe_next = NULL; \
- (elm)->field.tqe_prev = (head)->tqh_last; \
- *(head)->tqh_last = (elm); \
- (head)->tqh_last = &(elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
- if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
- (elm)->field.tqe_next->field.tqe_prev = \
- &(elm)->field.tqe_next; \
- else \
- (head)->tqh_last = &(elm)->field.tqe_next; \
- (listelm)->field.tqe_next = (elm); \
- (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
- (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
- (elm)->field.tqe_next = (listelm); \
- *(listelm)->field.tqe_prev = (elm); \
- (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_REMOVE(head, elm, field) do { \
- if (((elm)->field.tqe_next) != NULL) \
- (elm)->field.tqe_next->field.tqe_prev = \
- (elm)->field.tqe_prev; \
- else \
- (head)->tqh_last = (elm)->field.tqe_prev; \
- *(elm)->field.tqe_prev = (elm)->field.tqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define TAILQ_FOREACH(var, head, field) \
- for ((var) = ((head)->tqh_first); \
- (var); \
- (var) = ((var)->field.tqe_next))
-
-#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
- for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \
- (var); \
- (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)))
-
-#define TAILQ_CONCAT(head1, head2, field) do { \
- if (!TAILQ_EMPTY(head2)) { \
- *(head1)->tqh_last = (head2)->tqh_first; \
- (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \
- (head1)->tqh_last = (head2)->tqh_last; \
- TAILQ_INIT((head2)); \
- } \
-} while (/*CONSTCOND*/0)
-
-/*
- * Tail queue access methods.
- */
-#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
-#define TAILQ_FIRST(head) ((head)->tqh_first)
-#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define TAILQ_LAST(head, headname) \
- (*(((struct headname *)((head)->tqh_last))->tqh_last))
-#define TAILQ_PREV(elm, headname, field) \
- (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-
-/*
- * Circular queue definitions.
- */
-#define CIRCLEQ_HEAD(name, type) \
-struct name { \
- struct type *cqh_first; /* first element */ \
- struct type *cqh_last; /* last element */ \
-}
-
-#define CIRCLEQ_HEAD_INITIALIZER(head) \
- { (void *)&head, (void *)&head }
-
-#define CIRCLEQ_ENTRY(type) \
-struct { \
- struct type *cqe_next; /* next element */ \
- struct type *cqe_prev; /* previous element */ \
-}
-
-/*
- * Circular queue functions.
- */
-#define CIRCLEQ_INIT(head) do { \
- (head)->cqh_first = (void *)(head); \
- (head)->cqh_last = (void *)(head); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
- (elm)->field.cqe_next = (listelm)->field.cqe_next; \
- (elm)->field.cqe_prev = (listelm); \
- if ((listelm)->field.cqe_next == (void *)(head)) \
- (head)->cqh_last = (elm); \
- else \
- (listelm)->field.cqe_next->field.cqe_prev = (elm); \
- (listelm)->field.cqe_next = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
- (elm)->field.cqe_next = (listelm); \
- (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
- if ((listelm)->field.cqe_prev == (void *)(head)) \
- (head)->cqh_first = (elm); \
- else \
- (listelm)->field.cqe_prev->field.cqe_next = (elm); \
- (listelm)->field.cqe_prev = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
- (elm)->field.cqe_next = (head)->cqh_first; \
- (elm)->field.cqe_prev = (void *)(head); \
- if ((head)->cqh_last == (void *)(head)) \
- (head)->cqh_last = (elm); \
- else \
- (head)->cqh_first->field.cqe_prev = (elm); \
- (head)->cqh_first = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
- (elm)->field.cqe_next = (void *)(head); \
- (elm)->field.cqe_prev = (head)->cqh_last; \
- if ((head)->cqh_first == (void *)(head)) \
- (head)->cqh_first = (elm); \
- else \
- (head)->cqh_last->field.cqe_next = (elm); \
- (head)->cqh_last = (elm); \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_REMOVE(head, elm, field) do { \
- if ((elm)->field.cqe_next == (void *)(head)) \
- (head)->cqh_last = (elm)->field.cqe_prev; \
- else \
- (elm)->field.cqe_next->field.cqe_prev = \
- (elm)->field.cqe_prev; \
- if ((elm)->field.cqe_prev == (void *)(head)) \
- (head)->cqh_first = (elm)->field.cqe_next; \
- else \
- (elm)->field.cqe_prev->field.cqe_next = \
- (elm)->field.cqe_next; \
-} while (/*CONSTCOND*/0)
-
-#define CIRCLEQ_FOREACH(var, head, field) \
- for ((var) = ((head)->cqh_first); \
- (var) != (const void *)(head); \
- (var) = ((var)->field.cqe_next))
-
-#define CIRCLEQ_FOREACH_REVERSE(var, head, field) \
- for ((var) = ((head)->cqh_last); \
- (var) != (const void *)(head); \
- (var) = ((var)->field.cqe_prev))
-
-/*
- * Circular queue access methods.
- */
-#define CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))
-#define CIRCLEQ_FIRST(head) ((head)->cqh_first)
-#define CIRCLEQ_LAST(head) ((head)->cqh_last)
-#define CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
-#define CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
-
-#define CIRCLEQ_LOOP_NEXT(head, elm, field) \
- (((elm)->field.cqe_next == (void *)(head)) \
- ? ((head)->cqh_first) \
- : (elm->field.cqe_next))
-#define CIRCLEQ_LOOP_PREV(head, elm, field) \
- (((elm)->field.cqe_prev == (void *)(head)) \
- ? ((head)->cqh_last) \
- : (elm->field.cqe_prev))
-
-#endif /* sys/queue.h */
diff --git a/openair3/UTILS/tree.h b/openair3/UTILS/tree.h
deleted file mode 100644
index 351df9dfc5a0bd7f480b1ffd907eac9890f0a62c..0000000000000000000000000000000000000000
--- a/openair3/UTILS/tree.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * Copyright 2002 Niels Provos <provos@citi.umich.edu>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _SYS_TREE_H_
-#define _SYS_TREE_H_
-
-/*
- * This file defines data structures for different types of trees:
- * splay trees and red-black trees.
- *
- * A splay tree is a self-organizing data structure. Every operation
- * on the tree causes a splay to happen. The splay moves the requested
- * node to the root of the tree and partly rebalances it.
- *
- * This has the benefit that request locality causes faster lookups as
- * the requested nodes move to the top of the tree. On the other hand,
- * every lookup causes memory writes.
- *
- * The Balance Theorem bounds the total access time for m operations
- * and n inserts on an initially empty tree as O((m + n)lg n). The
- * amortized cost for a sequence of m accesses to a splay tree is O(lg n);
- *
- * A red-black tree is a binary search tree with the node color as an
- * extra attribute. It fulfills a set of conditions:
- * - every search path from the root to a leaf consists of the
- * same number of black nodes,
- * - each red node (except for the root) has a black parent,
- * - each leaf node is black.
- *
- * Every operation on a red-black tree is bounded as O(lg n).
- * The maximum height of a red-black tree is 2lg (n+1).
- */
-
-#define SPLAY_HEAD(name, type) \
-struct name { \
- struct type *sph_root; /* root of the tree */ \
-}
-
-#define SPLAY_INITIALIZER(root) \
- { NULL }
-
-#define SPLAY_INIT(root) do { \
- (root)->sph_root = NULL; \
-} while (0)
-
-#define SPLAY_ENTRY(type) \
-struct { \
- struct type *spe_left; /* left element */ \
- struct type *spe_right; /* right element */ \
-}
-
-#define SPLAY_LEFT(elm, field) (elm)->field.spe_left
-#define SPLAY_RIGHT(elm, field) (elm)->field.spe_right
-#define SPLAY_ROOT(head) (head)->sph_root
-#define SPLAY_EMPTY(head) (SPLAY_ROOT(head) == NULL)
-
-/* SPLAY_ROTATE_{LEFT,RIGHT} expect that tmp hold SPLAY_{RIGHT,LEFT} */
-#define SPLAY_ROTATE_RIGHT(head, tmp, field) do { \
- SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(tmp, field); \
- SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
- (head)->sph_root = tmp; \
-} while (0)
-
-#define SPLAY_ROTATE_LEFT(head, tmp, field) do { \
- SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(tmp, field); \
- SPLAY_LEFT(tmp, field) = (head)->sph_root; \
- (head)->sph_root = tmp; \
-} while (0)
-
-#define SPLAY_LINKLEFT(head, tmp, field) do { \
- SPLAY_LEFT(tmp, field) = (head)->sph_root; \
- tmp = (head)->sph_root; \
- (head)->sph_root = SPLAY_LEFT((head)->sph_root, field); \
-} while (0)
-
-#define SPLAY_LINKRIGHT(head, tmp, field) do { \
- SPLAY_RIGHT(tmp, field) = (head)->sph_root; \
- tmp = (head)->sph_root; \
- (head)->sph_root = SPLAY_RIGHT((head)->sph_root, field); \
-} while (0)
-
-#define SPLAY_ASSEMBLE(head, node, left, right, field) do { \
- SPLAY_RIGHT(left, field) = SPLAY_LEFT((head)->sph_root, field); \
- SPLAY_LEFT(right, field) = SPLAY_RIGHT((head)->sph_root, field);\
- SPLAY_LEFT((head)->sph_root, field) = SPLAY_RIGHT(node, field); \
- SPLAY_RIGHT((head)->sph_root, field) = SPLAY_LEFT(node, field); \
-} while (0)
-
-/* Generates prototypes and inline functions */
-
-#define SPLAY_PROTOTYPE(name, type, field, cmp) \
-void name##_SPLAY(struct name *, struct type *); \
-void name##_SPLAY_MINMAX(struct name *, int); \
-struct type *name##_SPLAY_INSERT(struct name *, struct type *); \
-struct type *name##_SPLAY_REMOVE(struct name *, struct type *); \
- \
-/* Finds the node with the same key as elm */ \
-static __inline struct type * \
-name##_SPLAY_FIND(struct name *head, struct type *elm) \
-{ \
- if (SPLAY_EMPTY(head)) \
- return(NULL); \
- name##_SPLAY(head, elm); \
- if ((cmp)(elm, (head)->sph_root) == 0) \
- return (head->sph_root); \
- return (NULL); \
-} \
- \
-static __inline struct type * \
-name##_SPLAY_NEXT(struct name *head, struct type *elm) \
-{ \
- name##_SPLAY(head, elm); \
- if (SPLAY_RIGHT(elm, field) != NULL) { \
- elm = SPLAY_RIGHT(elm, field); \
- while (SPLAY_LEFT(elm, field) != NULL) { \
- elm = SPLAY_LEFT(elm, field); \
- } \
- } else \
- elm = NULL; \
- return (elm); \
-} \
- \
-static __inline struct type * \
-name##_SPLAY_MIN_MAX(struct name *head, int val) \
-{ \
- name##_SPLAY_MINMAX(head, val); \
- return (SPLAY_ROOT(head)); \
-}
-
-/* Main splay operation.
- * Moves node close to the key of elm to top
- */
-#define SPLAY_GENERATE(name, type, field, cmp) \
-struct type * \
-name##_SPLAY_INSERT(struct name *head, struct type *elm) \
-{ \
- if (SPLAY_EMPTY(head)) { \
- SPLAY_LEFT(elm, field) = SPLAY_RIGHT(elm, field) = NULL; \
- } else { \
- int __comp; \
- name##_SPLAY(head, elm); \
- __comp = (cmp)(elm, (head)->sph_root); \
- if(__comp < 0) { \
- SPLAY_LEFT(elm, field) = SPLAY_LEFT((head)->sph_root, field);\
- SPLAY_RIGHT(elm, field) = (head)->sph_root; \
- SPLAY_LEFT((head)->sph_root, field) = NULL; \
- } else if (__comp > 0) { \
- SPLAY_RIGHT(elm, field) = SPLAY_RIGHT((head)->sph_root, field);\
- SPLAY_LEFT(elm, field) = (head)->sph_root; \
- SPLAY_RIGHT((head)->sph_root, field) = NULL; \
- } else \
- return ((head)->sph_root); \
- } \
- (head)->sph_root = (elm); \
- return (NULL); \
-} \
- \
-struct type * \
-name##_SPLAY_REMOVE(struct name *head, struct type *elm) \
-{ \
- struct type *__tmp; \
- if (SPLAY_EMPTY(head)) \
- return (NULL); \
- name##_SPLAY(head, elm); \
- if ((cmp)(elm, (head)->sph_root) == 0) { \
- if (SPLAY_LEFT((head)->sph_root, field) == NULL) { \
- (head)->sph_root = SPLAY_RIGHT((head)->sph_root, field);\
- } else { \
- __tmp = SPLAY_RIGHT((head)->sph_root, field); \
- (head)->sph_root = SPLAY_LEFT((head)->sph_root, field);\
- name##_SPLAY(head, elm); \
- SPLAY_RIGHT((head)->sph_root, field) = __tmp; \
- } \
- return (elm); \
- } \
- return (NULL); \
-} \
- \
-void \
-name##_SPLAY(struct name *head, struct type *elm) \
-{ \
- struct type __node, *__left, *__right, *__tmp; \
- int __comp; \
-\
- SPLAY_LEFT(&__node, field) = SPLAY_RIGHT(&__node, field) = NULL;\
- __left = __right = &__node; \
-\
- while ((__comp = (cmp)(elm, (head)->sph_root))) { \
- if (__comp < 0) { \
- __tmp = SPLAY_LEFT((head)->sph_root, field); \
- if (__tmp == NULL) \
- break; \
- if ((cmp)(elm, __tmp) < 0){ \
- SPLAY_ROTATE_RIGHT(head, __tmp, field); \
- if (SPLAY_LEFT((head)->sph_root, field) == NULL)\
- break; \
- } \
- SPLAY_LINKLEFT(head, __right, field); \
- } else if (__comp > 0) { \
- __tmp = SPLAY_RIGHT((head)->sph_root, field); \
- if (__tmp == NULL) \
- break; \
- if ((cmp)(elm, __tmp) > 0){ \
- SPLAY_ROTATE_LEFT(head, __tmp, field); \
- if (SPLAY_RIGHT((head)->sph_root, field) == NULL)\
- break; \
- } \
- SPLAY_LINKRIGHT(head, __left, field); \
- } \
- } \
- SPLAY_ASSEMBLE(head, &__node, __left, __right, field); \
-} \
- \
-/* Splay with either the minimum or the maximum element \
- * Used to find minimum or maximum element in tree. \
- */ \
-void name##_SPLAY_MINMAX(struct name *head, int __comp) \
-{ \
- struct type __node, *__left, *__right, *__tmp; \
-\
- SPLAY_LEFT(&__node, field) = SPLAY_RIGHT(&__node, field) = NULL;\
- __left = __right = &__node; \
-\
- while (1) { \
- if (__comp < 0) { \
- __tmp = SPLAY_LEFT((head)->sph_root, field); \
- if (__tmp == NULL) \
- break; \
- if (__comp < 0){ \
- SPLAY_ROTATE_RIGHT(head, __tmp, field); \
- if (SPLAY_LEFT((head)->sph_root, field) == NULL)\
- break; \
- } \
- SPLAY_LINKLEFT(head, __right, field); \
- } else if (__comp > 0) { \
- __tmp = SPLAY_RIGHT((head)->sph_root, field); \
- if (__tmp == NULL) \
- break; \
- if (__comp > 0) { \
- SPLAY_ROTATE_LEFT(head, __tmp, field); \
- if (SPLAY_RIGHT((head)->sph_root, field) == NULL)\
- break; \
- } \
- SPLAY_LINKRIGHT(head, __left, field); \
- } \
- } \
- SPLAY_ASSEMBLE(head, &__node, __left, __right, field); \
-}
-
-#define SPLAY_NEGINF -1
-#define SPLAY_INF 1
-
-#define SPLAY_INSERT(name, x, y) name##_SPLAY_INSERT(x, y)
-#define SPLAY_REMOVE(name, x, y) name##_SPLAY_REMOVE(x, y)
-#define SPLAY_FIND(name, x, y) name##_SPLAY_FIND(x, y)
-#define SPLAY_NEXT(name, x, y) name##_SPLAY_NEXT(x, y)
-#define SPLAY_MIN(name, x) (SPLAY_EMPTY(x) ? NULL \
- : name##_SPLAY_MIN_MAX(x, SPLAY_NEGINF))
-#define SPLAY_MAX(name, x) (SPLAY_EMPTY(x) ? NULL \
- : name##_SPLAY_MIN_MAX(x, SPLAY_INF))
-
-#define SPLAY_FOREACH(x, name, head) \
- for ((x) = SPLAY_MIN(name, head); \
- (x) != NULL; \
- (x) = SPLAY_NEXT(name, head, x))
-
-/* Macros that define a red-back tree */
-#define RB_HEAD(name, type) \
-struct name { \
- struct type *rbh_root; /* root of the tree */ \
-}
-
-#define RB_INITIALIZER(root) \
- { NULL }
-
-#define RB_INIT(root) do { \
- (root)->rbh_root = NULL; \
-} while (0)
-
-#define RB_BLACK 0
-#define RB_RED 1
-#define RB_ENTRY(type) \
-struct { \
- struct type *rbe_left; /* left element */ \
- struct type *rbe_right; /* right element */ \
- struct type *rbe_parent; /* parent element */ \
- int rbe_color; /* node color */ \
-}
-
-#define RB_LEFT(elm, field) (elm)->field.rbe_left
-#define RB_RIGHT(elm, field) (elm)->field.rbe_right
-#define RB_PARENT(elm, field) (elm)->field.rbe_parent
-#define RB_COLOR(elm, field) (elm)->field.rbe_color
-#define RB_ROOT(head) (head)->rbh_root
-#define RB_EMPTY(head) (RB_ROOT(head) == NULL)
-
-#define RB_SET(elm, parent, field) do { \
- RB_PARENT(elm, field) = parent; \
- RB_LEFT(elm, field) = RB_RIGHT(elm, field) = NULL; \
- RB_COLOR(elm, field) = RB_RED; \
-} while (0)
-
-#define RB_SET_BLACKRED(black, red, field) do { \
- RB_COLOR(black, field) = RB_BLACK; \
- RB_COLOR(red, field) = RB_RED; \
-} while (0)
-
-#ifndef RB_AUGMENT
-#define RB_AUGMENT(x)
-#endif
-
-#define RB_ROTATE_LEFT(head, elm, tmp, field) do { \
- (tmp) = RB_RIGHT(elm, field); \
- if ((RB_RIGHT(elm, field) = RB_LEFT(tmp, field))) { \
- RB_PARENT(RB_LEFT(tmp, field), field) = (elm); \
- } \
- RB_AUGMENT(elm); \
- if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
- if ((elm) == RB_LEFT(RB_PARENT(elm, field), field)) \
- RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
- else \
- RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
- } else \
- (head)->rbh_root = (tmp); \
- RB_LEFT(tmp, field) = (elm); \
- RB_PARENT(elm, field) = (tmp); \
- RB_AUGMENT(tmp); \
- if ((RB_PARENT(tmp, field))) \
- RB_AUGMENT(RB_PARENT(tmp, field)); \
-} while (0)
-
-#define RB_ROTATE_RIGHT(head, elm, tmp, field) do { \
- (tmp) = RB_LEFT(elm, field); \
- if ((RB_LEFT(elm, field) = RB_RIGHT(tmp, field))) { \
- RB_PARENT(RB_RIGHT(tmp, field), field) = (elm); \
- } \
- RB_AUGMENT(elm); \
- if ((RB_PARENT(tmp, field) = RB_PARENT(elm, field))) { \
- if ((elm) == RB_LEFT(RB_PARENT(elm, field), field)) \
- RB_LEFT(RB_PARENT(elm, field), field) = (tmp); \
- else \
- RB_RIGHT(RB_PARENT(elm, field), field) = (tmp); \
- } else \
- (head)->rbh_root = (tmp); \
- RB_RIGHT(tmp, field) = (elm); \
- RB_PARENT(elm, field) = (tmp); \
- RB_AUGMENT(tmp); \
- if ((RB_PARENT(tmp, field))) \
- RB_AUGMENT(RB_PARENT(tmp, field)); \
-} while (0)
-
-/* Generates prototypes and inline functions */
-#define RB_PROTOTYPE(name, type, field, cmp) \
-void name##_RB_INSERT_COLOR(struct name *, struct type *); \
-void name##_RB_REMOVE_COLOR(struct name *, struct type *, struct type *);\
-struct type *name##_RB_REMOVE(struct name *, struct type *); \
-struct type *name##_RB_INSERT(struct name *, struct type *); \
-struct type *name##_RB_FIND(struct name *, struct type *); \
-struct type *name##_RB_NEXT(struct type *); \
-struct type *name##_RB_MINMAX(struct name *, int); \
- \
-
-/* Main rb operation.
- * Moves node close to the key of elm to top
- */
-#define RB_GENERATE(name, type, field, cmp) \
-void \
-name##_RB_INSERT_COLOR(struct name *head, struct type *elm) \
-{ \
- struct type *parent, *gparent, *tmp; \
- while ((parent = RB_PARENT(elm, field)) && \
- RB_COLOR(parent, field) == RB_RED) { \
- gparent = RB_PARENT(parent, field); \
- if (parent == RB_LEFT(gparent, field)) { \
- tmp = RB_RIGHT(gparent, field); \
- if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
- RB_COLOR(tmp, field) = RB_BLACK; \
- RB_SET_BLACKRED(parent, gparent, field);\
- elm = gparent; \
- continue; \
- } \
- if (RB_RIGHT(parent, field) == elm) { \
- RB_ROTATE_LEFT(head, parent, tmp, field);\
- tmp = parent; \
- parent = elm; \
- elm = tmp; \
- } \
- RB_SET_BLACKRED(parent, gparent, field); \
- RB_ROTATE_RIGHT(head, gparent, tmp, field); \
- } else { \
- tmp = RB_LEFT(gparent, field); \
- if (tmp && RB_COLOR(tmp, field) == RB_RED) { \
- RB_COLOR(tmp, field) = RB_BLACK; \
- RB_SET_BLACKRED(parent, gparent, field);\
- elm = gparent; \
- continue; \
- } \
- if (RB_LEFT(parent, field) == elm) { \
- RB_ROTATE_RIGHT(head, parent, tmp, field);\
- tmp = parent; \
- parent = elm; \
- elm = tmp; \
- } \
- RB_SET_BLACKRED(parent, gparent, field); \
- RB_ROTATE_LEFT(head, gparent, tmp, field); \
- } \
- } \
- RB_COLOR(head->rbh_root, field) = RB_BLACK; \
-} \
- \
-void \
-name##_RB_REMOVE_COLOR(struct name *head, struct type *parent, struct type *elm) \
-{ \
- struct type *tmp; \
- while ((elm == NULL || RB_COLOR(elm, field) == RB_BLACK) && \
- elm != RB_ROOT(head)) { \
- if (RB_LEFT(parent, field) == elm) { \
- tmp = RB_RIGHT(parent, field); \
- if (RB_COLOR(tmp, field) == RB_RED) { \
- RB_SET_BLACKRED(tmp, parent, field); \
- RB_ROTATE_LEFT(head, parent, tmp, field);\
- tmp = RB_RIGHT(parent, field); \
- } \
- if ((RB_LEFT(tmp, field) == NULL || \
- RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
- (RB_RIGHT(tmp, field) == NULL || \
- RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
- RB_COLOR(tmp, field) = RB_RED; \
- elm = parent; \
- parent = RB_PARENT(elm, field); \
- } else { \
- if (RB_RIGHT(tmp, field) == NULL || \
- RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK) {\
- struct type *oleft; \
- if ((oleft = RB_LEFT(tmp, field)))\
- RB_COLOR(oleft, field) = RB_BLACK;\
- RB_COLOR(tmp, field) = RB_RED; \
- RB_ROTATE_RIGHT(head, tmp, oleft, field);\
- tmp = RB_RIGHT(parent, field); \
- } \
- RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
- RB_COLOR(parent, field) = RB_BLACK; \
- if (RB_RIGHT(tmp, field)) \
- RB_COLOR(RB_RIGHT(tmp, field), field) = RB_BLACK;\
- RB_ROTATE_LEFT(head, parent, tmp, field);\
- elm = RB_ROOT(head); \
- break; \
- } \
- } else { \
- tmp = RB_LEFT(parent, field); \
- if (RB_COLOR(tmp, field) == RB_RED) { \
- RB_SET_BLACKRED(tmp, parent, field); \
- RB_ROTATE_RIGHT(head, parent, tmp, field);\
- tmp = RB_LEFT(parent, field); \
- } \
- if ((RB_LEFT(tmp, field) == NULL || \
- RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) &&\
- (RB_RIGHT(tmp, field) == NULL || \
- RB_COLOR(RB_RIGHT(tmp, field), field) == RB_BLACK)) {\
- RB_COLOR(tmp, field) = RB_RED; \
- elm = parent; \
- parent = RB_PARENT(elm, field); \
- } else { \
- if (RB_LEFT(tmp, field) == NULL || \
- RB_COLOR(RB_LEFT(tmp, field), field) == RB_BLACK) {\
- struct type *oright; \
- if ((oright = RB_RIGHT(tmp, field)))\
- RB_COLOR(oright, field) = RB_BLACK;\
- RB_COLOR(tmp, field) = RB_RED; \
- RB_ROTATE_LEFT(head, tmp, oright, field);\
- tmp = RB_LEFT(parent, field); \
- } \
- RB_COLOR(tmp, field) = RB_COLOR(parent, field);\
- RB_COLOR(parent, field) = RB_BLACK; \
- if (RB_LEFT(tmp, field)) \
- RB_COLOR(RB_LEFT(tmp, field), field) = RB_BLACK;\
- RB_ROTATE_RIGHT(head, parent, tmp, field);\
- elm = RB_ROOT(head); \
- break; \
- } \
- } \
- } \
- if (elm) \
- RB_COLOR(elm, field) = RB_BLACK; \
-} \
- \
-struct type * \
-name##_RB_REMOVE(struct name *head, struct type *elm) \
-{ \
- struct type *child, *parent, *old = elm; \
- int color; \
- if (RB_LEFT(elm, field) == NULL) \
- child = RB_RIGHT(elm, field); \
- else if (RB_RIGHT(elm, field) == NULL) \
- child = RB_LEFT(elm, field); \
- else { \
- struct type *left; \
- elm = RB_RIGHT(elm, field); \
- while ((left = RB_LEFT(elm, field))) \
- elm = left; \
- child = RB_RIGHT(elm, field); \
- parent = RB_PARENT(elm, field); \
- color = RB_COLOR(elm, field); \
- if (child) \
- RB_PARENT(child, field) = parent; \
- if (parent) { \
- if (RB_LEFT(parent, field) == elm) \
- RB_LEFT(parent, field) = child; \
- else \
- RB_RIGHT(parent, field) = child; \
- RB_AUGMENT(parent); \
- } else \
- RB_ROOT(head) = child; \
- if (RB_PARENT(elm, field) == old) \
- parent = elm; \
- (elm)->field = (old)->field; \
- if (RB_PARENT(old, field)) { \
- if (RB_LEFT(RB_PARENT(old, field), field) == old)\
- RB_LEFT(RB_PARENT(old, field), field) = elm;\
- else \
- RB_RIGHT(RB_PARENT(old, field), field) = elm;\
- RB_AUGMENT(RB_PARENT(old, field)); \
- } else \
- RB_ROOT(head) = elm; \
- RB_PARENT(RB_LEFT(old, field), field) = elm; \
- if (RB_RIGHT(old, field)) \
- RB_PARENT(RB_RIGHT(old, field), field) = elm; \
- if (parent) { \
- left = parent; \
- do { \
- RB_AUGMENT(left); \
- } while ((left = RB_PARENT(left, field))); \
- } \
- goto color; \
- } \
- parent = RB_PARENT(elm, field); \
- color = RB_COLOR(elm, field); \
- if (child) \
- RB_PARENT(child, field) = parent; \
- if (parent) { \
- if (RB_LEFT(parent, field) == elm) \
- RB_LEFT(parent, field) = child; \
- else \
- RB_RIGHT(parent, field) = child; \
- RB_AUGMENT(parent); \
- } else \
- RB_ROOT(head) = child; \
-color: \
- if (color == RB_BLACK) \
- name##_RB_REMOVE_COLOR(head, parent, child); \
- return (old); \
-} \
- \
-/* Inserts a node into the RB tree */ \
-struct type * \
-name##_RB_INSERT(struct name *head, struct type *elm) \
-{ \
- struct type *tmp; \
- struct type *parent = NULL; \
- int comp = 0; \
- tmp = RB_ROOT(head); \
- while (tmp) { \
- parent = tmp; \
- comp = (cmp)(elm, parent); \
- if (comp < 0) \
- tmp = RB_LEFT(tmp, field); \
- else if (comp > 0) \
- tmp = RB_RIGHT(tmp, field); \
- else \
- return (tmp); \
- } \
- RB_SET(elm, parent, field); \
- if (parent != NULL) { \
- if (comp < 0) \
- RB_LEFT(parent, field) = elm; \
- else \
- RB_RIGHT(parent, field) = elm; \
- RB_AUGMENT(parent); \
- } else \
- { \
- RB_ROOT(head) = elm; \
- } \
- name##_RB_INSERT_COLOR(head, elm); \
- return (NULL); \
-} \
- \
-/* Finds the node with the same key as elm */ \
-struct type * \
-name##_RB_FIND(struct name *head, struct type *elm) \
-{ \
- struct type *tmp = RB_ROOT(head); \
- int comp; \
- while (tmp) { \
- comp = cmp(elm, tmp); \
- if (comp < 0) \
- tmp = RB_LEFT(tmp, field); \
- else if (comp > 0) \
- tmp = RB_RIGHT(tmp, field); \
- else \
- return (tmp); \
- } \
- return (NULL); \
-} \
- \
-struct type * \
-name##_RB_NEXT(struct type *elm) \
-{ \
- if (RB_RIGHT(elm, field)) { \
- elm = RB_RIGHT(elm, field); \
- while (RB_LEFT(elm, field)) \
- elm = RB_LEFT(elm, field); \
- } else { \
- if (RB_PARENT(elm, field) && \
- (elm == RB_LEFT(RB_PARENT(elm, field), field))) \
- elm = RB_PARENT(elm, field); \
- else { \
- while (RB_PARENT(elm, field) && \
- (elm == RB_RIGHT(RB_PARENT(elm, field), field)))\
- elm = RB_PARENT(elm, field); \
- elm = RB_PARENT(elm, field); \
- } \
- } \
- return (elm); \
-} \
- \
-struct type * \
-name##_RB_MINMAX(struct name *head, int val) \
-{ \
- struct type *tmp = RB_ROOT(head); \
- struct type *parent = NULL; \
- while (tmp) { \
- parent = tmp; \
- if (val < 0) \
- tmp = RB_LEFT(tmp, field); \
- else \
- tmp = RB_RIGHT(tmp, field); \
- } \
- return (parent); \
-}
-
-#define RB_NEGINF -1
-#define RB_INF 1
-
-#define RB_INSERT(name, x, y) name##_RB_INSERT(x, y)
-#define RB_REMOVE(name, x, y) name##_RB_REMOVE(x, y)
-#define RB_FIND(name, x, y) name##_RB_FIND(x, y)
-#define RB_NEXT(name, x, y) name##_RB_NEXT(y)
-#define RB_MIN(name, x) name##_RB_MINMAX(x, RB_NEGINF)
-#define RB_MAX(name, x) name##_RB_MINMAX(x, RB_INF)
-
-#define RB_FOREACH(x, name, head) \
- for ((x) = RB_MIN(name, head); \
- (x) != NULL; \
- (x) = name##_RB_NEXT(x))
-
-#endif /* _SYS_TREE_H_ */
diff --git a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c
index c4e593ca922a766e8ba4f2c141d6c20a40433c52..af5ab5ad6d169a0bd574ff7b8de8ad3bd1b5b179 100644
--- a/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c
+++ b/targets/ARCH/BLADERF/USERSPACE/LIB/bladerf_lib.c
@@ -330,7 +330,10 @@ int trx_brf_set_gains(openair0_device* device,
{
return(0);
}
-
+int trx_brf_write_init(openair0_device *device)
+{
+ return 0;
+}
#define RXDCLENGTH 16384
int16_t cos_fsover8[8] = {2047, 1447, 0, -1448, -2047, -1448, 0, 1447};
@@ -1145,6 +1148,7 @@ int device_init(openair0_device *device,
device->trx_stop_func = trx_brf_stop;
device->trx_set_freq_func = trx_brf_set_freq;
device->trx_set_gains_func = trx_brf_set_gains;
+ device->trx_write_init = trx_brf_write_init;
device->openair0_cfg = openair0_cfg;
device->priv = (void *)brf;
diff --git a/targets/ARCH/COMMON/common_lib.h b/targets/ARCH/COMMON/common_lib.h
index ecadb68c0ca7917fc870faf63d6cd88d5835993d..d086c0e13a08b95955da404c840b6729b59f4141 100644
--- a/targets/ARCH/COMMON/common_lib.h
+++ b/targets/ARCH/COMMON/common_lib.h
@@ -52,6 +52,9 @@
#define RAU_LOCAL_RADIO_HEAD 0
#define RAU_REMOTE_RADIO_HEAD 1
+#define MAX_WRITE_THREAD_PACKAGE 10
+#define MAX_WRITE_THREAD_BUFFER_SIZE 8
+
#ifndef MAX_CARDS
#define MAX_CARDS 8
#endif
@@ -69,13 +72,9 @@ typedef enum {
max_gain=0,med_gain,byp_gain
} rx_gain_t;
-#if OCP_FRAMEWORK
-#include <enums.h>
-#else
typedef enum {
duplex_mode_TDD=1,duplex_mode_FDD=0
} duplex_mode_t;
-#endif
/** @addtogroup _GENERIC_PHY_RF_INTERFACE_
@@ -275,8 +274,37 @@ typedef struct {
void *rx;
} if_buffer_t;
+typedef struct {
+ openair0_timestamp timestamp;
+ void *buff[MAX_WRITE_THREAD_BUFFER_SIZE];// buffer to be write;
+ int nsamps;
+ int cc;
+ signed char first_packet;
+ signed char last_packet;
+ int flags_msb;
+} openair0_write_package_t;
+
+typedef struct {
+ openair0_write_package_t write_package[MAX_WRITE_THREAD_PACKAGE];
+ int start;
+ int end;
+ /// \internal This variable is protected by \ref mutex_write
+ int count_write;
+ /// pthread struct for trx write thread
+ pthread_t pthread_write;
+ /// pthread attributes for trx write thread
+ pthread_attr_t attr_write;
+ /// condition varible for trx write thread
+ pthread_cond_t cond_write;
+ /// mutex for trx write thread
+ pthread_mutex_t mutex_write;
+} openair0_thread_t;
+
/*!\brief structure holds the parameters to configure USRP devices */
struct openair0_device_t {
+ /*!tx write thread*/
+ openair0_thread_t write_thread;
+
/*!brief Module ID of this device */
int Mod_id;
@@ -400,6 +428,12 @@ struct openair0_device_t {
* \param arg pointer to capabilities or configuration
*/
void (*configure_rru)(int idx, void *arg);
+
+ /*! \brief RRU Configuration callback
+ * \param idx RU index
+ * \param arg pointer to capabilities or configuration
+ */
+ int (*trx_write_init)(openair0_device *device);
};
/* type of device init function, implemented in shared lib */
diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c
index c5822a3650f11950e287e2cddc2c79975b79e359..1d3c280f0e5d18a6485e5bd9f45cb9f3e0bae916 100644
--- a/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c
+++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c
@@ -197,6 +197,10 @@ int trx_eth_reset_stats(openair0_device* device)
return(0);
}
+int trx_eth_write_init(openair0_device *device)
+{
+ return 0;
+}
int ethernet_tune(openair0_device *device,
unsigned int option,
@@ -284,7 +288,7 @@ int ethernet_tune(openair0_device *device,
/******************* interface level options *************************/
case MTU_SIZE: /* change MTU of the eth interface */
ifr.ifr_addr.sa_family = AF_INET;
- strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name));
+ strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)-1);
ifr.ifr_mtu =value;
if (ioctl(eth->sockfdd,SIOCSIFMTU,(caddr_t)&ifr) < 0 )
perror ("[ETHERNET] Can't set the MTU");
@@ -294,7 +298,7 @@ int ethernet_tune(openair0_device *device,
case TX_Q_LEN: /* change TX queue length of eth interface */
ifr.ifr_addr.sa_family = AF_INET;
- strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name));
+ strncpy(ifr.ifr_name,eth->if_name, sizeof(ifr.ifr_name)-1);
ifr.ifr_qlen =value;
if (ioctl(eth->sockfdd,SIOCSIFTXQLEN,(caddr_t)&ifr) < 0 )
perror ("[ETHERNET] Can't set the txqueuelen");
@@ -415,8 +419,9 @@ int transport_init(openair0_device *device,
device->trx_reset_stats_func = trx_eth_reset_stats;
device->trx_end_func = trx_eth_end;
device->trx_stop_func = trx_eth_stop;
- device->trx_set_freq_func = trx_eth_set_freq;
- device->trx_set_gains_func = trx_eth_set_gains;
+ device->trx_set_freq_func = trx_eth_set_freq;
+ device->trx_set_gains_func = trx_eth_set_gains;
+ device->trx_write_init = trx_eth_write_init;
if (eth->flags == ETH_RAW_MODE) {
device->trx_write_func = trx_eth_write_raw;
diff --git a/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h b/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h
index 95d00290271218aa2ed72d41f03baedcd1e1b679..0f2147847a6145230078b8e4f30f16d9c23eef12 100644
--- a/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h
+++ b/targets/ARCH/ETHERNET/USERSPACE/LIB/if_defs.h
@@ -30,6 +30,9 @@
* \warning
*/
+#ifndef __ETHERNET_USERSPACE_LIB_IF_DEFS__H__
+#define __ETHERNET_USERSPACE_LIB_IF_DEFS__H__
+
#include <netinet/ether.h>
#include <stdint.h>
@@ -37,15 +40,11 @@
#include "PHY/LTE_TRANSPORT/if5_tools.h"
// ETH transport preference modes
-#ifdef OCP_FRAMEWORK
-#include "enums.h"
-#else
#define ETH_UDP_MODE 0
#define ETH_RAW_MODE 1
#define ETH_UDP_IF4p5_MODE 2
#define ETH_RAW_IF4p5_MODE 3
#define ETH_RAW_IF5_MOBIPASS 4
-#endif
// COMMOM HEADER LENGTHS
@@ -84,3 +83,5 @@
#define RAW_IF5_MOBIPASS_BLOCK_SIZE_BYTES 1280
#define RAW_IF5_MOBIPASS_SIZE_BYTES (MAC_HEADER_SIZE_BYTES + sizeof_IF5_mobipass_header_t + RAW_IF5_MOBIPASS_BLOCK_SIZE_BYTES)
#define PAYLOAD_MOBIPASS_NUM_SAMPLES 640
+
+#endif
diff --git a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp
index 5b20d8a8c71be4ba9ea850ff25474e1d8798abd8..1273097f3b901468f6ffd56ff2737fcbf22114c0 100644
--- a/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp
+++ b/targets/ARCH/IRIS/USERSPACE/LIB/iris_lib.cpp
@@ -510,6 +510,11 @@ int trx_iris_reset_stats(openair0_device *device) {
}
+int trx_iris_write_init(openair0_device *device)
+{
+ return 0;
+}
+
extern "C" {
/*! \brief Initialize Openair Iris target. It returns 0 if OK
@@ -831,6 +836,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) {
device->trx_set_freq_func = trx_iris_set_freq;
device->trx_set_gains_func = trx_iris_set_gains;
device->openair0_cfg = openair0_cfg;
+ device->trx_write_init = trx_iris_write_init;
s->sample_rate = openair0_cfg[0].sample_rate;
// TODO:
diff --git a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp
index 9fcfbdf5712a2da59f123b471e49b0ef12ee3c09..79a389bfeb46a7e02bf3f3ac397e6dbb55b97d76 100644
--- a/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp
+++ b/targets/ARCH/LMSSDR/USERSPACE/LIB/lms_lib.cpp
@@ -350,6 +350,10 @@ void trx_lms_end(openair0_device *device) {
}
+int trx_lms_write_init(openair0_device *device)
+{
+ return 0;
+}
extern "C" {
/*! \brief Initialize Openair LMSSDR target. It returns 0 if OK
* \param device the hardware to use
@@ -406,6 +410,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg){
device->trx_stop_func = trx_lms_stop;
device->trx_set_freq_func = trx_lms_set_freq;
device->trx_set_gains_func = trx_lms_set_gains;
+ device->trx_write_init = trx_lms_write_init;
device->openair0_cfg = openair0_cfg;
diff --git a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
index 90b0a2e554d9c9199f04f5556b8e9d901867d464..6e94717a6fbcf02525782f11eebf58e31a01cf44 100644
--- a/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+++ b/targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
@@ -50,6 +50,8 @@
#include "common_lib.h"
#include "assertions.h"
+#include "common/utils/LOG/vcd_signal_dumper.h"
+
#include <sys/resource.h>
#ifdef __SSE4_1__
@@ -68,6 +70,8 @@
* @{
*/
+extern int usrp_tx_thread;
+
typedef struct {
@@ -341,37 +345,12 @@ static int trx_usrp_write(openair0_device *device,
int flags_lsb = flags&0xff;
int flags_msb = (flags>>8)&0xff;
-
-#if defined(__x86_64) || defined(__i386__)
- #ifdef __AVX2__
- nsamps2 = (nsamps+7)>>3;
- __m256i buff_tx[8][nsamps2];
- #else
- nsamps2 = (nsamps+3)>>2;
- __m128i buff_tx[8][nsamps2];
- #endif
-#elif defined(__arm__)
- nsamps2 = (nsamps+3)>>2;
- int16x8_t buff_tx[8][nsamps2];
-#else
-#error Unsupported CPU architecture, USRP device cannot be built
-#endif
- // bring RX data into 12 LSBs for softmodem RX
- for (int i=0; i<cc; i++) {
- for (int j=0; j<nsamps2; j++) {
-#if defined(__x86_64__) || defined(__i386__)
-#ifdef __AVX2__
- buff_tx[i][j] = _mm256_slli_epi16(((__m256i *)buff[i])[j],4);
-#else
- buff_tx[i][j] = _mm_slli_epi16(((__m128i *)buff[i])[j],4);
-#endif
-#elif defined(__arm__)
- buff_tx[i][j] = vshlq_n_s16(((int16x8_t *)buff[i])[j],4);
-#endif
- }
- }
+ int end;
+ openair0_thread_t *write_thread = &device->write_thread;
+ openair0_write_package_t *write_package = write_thread->write_package;
+ AssertFatal( MAX_WRITE_THREAD_BUFFER_SIZE >= cc,"Do not support more than %d cc number\n", MAX_WRITE_THREAD_BUFFER_SIZE);
boolean_t first_packet_state=false,last_packet_state=false;
@@ -404,13 +383,181 @@ static int trx_usrp_write(openair0_device *device,
last_packet_state = true;
}
-
+ if(usrp_tx_thread == 0){
+#if defined(__x86_64) || defined(__i386__)
+ #ifdef __AVX2__
+ nsamps2 = (nsamps+7)>>3;
+ __m256i buff_tx[8][nsamps2];
+ #else
+ nsamps2 = (nsamps+3)>>2;
+ __m128i buff_tx[8][nsamps2];
+ #endif
+#elif defined(__arm__)
+ nsamps2 = (nsamps+3)>>2;
+ int16x8_t buff_tx[8][nsamps2];
+#else
+#error Unsupported CPU architecture, USRP device cannot be built
+#endif
+
+ // bring RX data into 12 LSBs for softmodem RX
+ for (int i=0; i<cc; i++) {
+ for (int j=0; j<nsamps2; j++) {
+#if defined(__x86_64__) || defined(__i386__)
+#ifdef __AVX2__
+ buff_tx[i][j] = _mm256_slli_epi16(((__m256i *)buff[i])[j],4);
+#else
+ buff_tx[i][j] = _mm_slli_epi16(((__m128i *)buff[i])[j],4);
+#endif
+#elif defined(__arm__)
+ buff_tx[i][j] = vshlq_n_s16(((int16x8_t *)buff[i])[j],4);
+#endif
+ }
+ }
+
s->tx_md.has_time_spec = true;
s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet_state;
s->tx_md.end_of_burst = last_packet_state;
s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate);
s->tx_count++;
+VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,1);
+ // bit 3 enables gpio (for backward compatibility)
+ if (flags_msb&8) {
+ // push GPIO bits 7-9 from flags_msb
+ int gpio789=(flags_msb&7)<<7;
+ s->usrp->set_command_time(s->tx_md.time_spec);
+ s->usrp->set_gpio_attr("FP0", "OUT", gpio789, 0x380);
+ s->usrp->clear_command_time();
+ }
+VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_BEAM_SWITCHING_GPIO,0);
+
+ if (cc>1) {
+ std::vector<void *> buff_ptrs;
+
+ for (int i=0; i<cc; i++)
+ buff_ptrs.push_back(&(((int16_t *)buff_tx[i])[0]));
+
+ ret = (int)s->tx_stream->send(buff_ptrs, nsamps, s->tx_md);
+ }
+ else {
+ ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md);
+ }
+
+ if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
+ return ret;
+ }
+ else{
+ pthread_mutex_lock(&write_thread->mutex_write);
+
+ if(write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE){
+ LOG_W(HW,"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n", write_thread->count_write, write_thread->start, write_thread->end);
+ write_thread->end = write_thread->start;
+ write_thread->count_write = 0;
+ }
+
+ end = write_thread->end;
+ write_package[end].timestamp = timestamp;
+ write_package[end].nsamps = nsamps;
+ write_package[end].cc = cc;
+ write_package[end].first_packet = first_packet_state;
+ write_package[end].last_packet = last_packet_state;
+ write_package[end].flags_msb = flags_msb;
+ for (int i = 0; i < cc; i++)
+ write_package[end].buff[i] = buff[i];
+ write_thread->count_write++;
+ write_thread->end = (write_thread->end + 1)% MAX_WRITE_THREAD_PACKAGE;
+ pthread_cond_signal(&write_thread->cond_write);
+ pthread_mutex_unlock(&write_thread->mutex_write);
+ return 0;
+ }
+
+}
+
+//-----------------------start--------------------------
+/*! \brief Called to send samples to the USRP RF target
+ @param device pointer to the device structure specific to the RF hardware target
+ @param timestamp The timestamp at which the first sample MUST be sent
+ @param buff Buffer which holds the samples
+ @param nsamps number of samples to be sent
+ @param antenna_id index of the antenna if the device has multiple antennas
+ @param flags flags must be set to TRUE if timestamp parameter needs to be applied
+*/
+void *trx_usrp_write_thread(void * arg){
+ int ret=0;
+ openair0_device *device=(openair0_device *)arg;
+ openair0_thread_t *write_thread = &device->write_thread;
+ openair0_write_package_t *write_package = write_thread->write_package;
+
+ usrp_state_t *s;
+ int nsamps2; // aligned to upper 32 or 16 byte boundary
+ int start;
+ openair0_timestamp timestamp;
+ void **buff;
+ int nsamps;
+ int cc;
+ signed char first_packet;
+ signed char last_packet;
+ int flags_msb;
+
+ while(1){
+ pthread_mutex_lock(&write_thread->mutex_write);
+ while (write_thread->count_write == 0) {
+ pthread_cond_wait(&write_thread->cond_write,&write_thread->mutex_write); // this unlocks mutex_rxtx while waiting and then locks it again
+ }
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, 1 );
+ s = (usrp_state_t *)device->priv;
+ start = write_thread->start;
+ timestamp = write_package[start].timestamp;
+ buff = write_package[start].buff;
+ nsamps = write_package[start].nsamps;
+ cc = write_package[start].cc;
+ first_packet = write_package[start].first_packet;
+ last_packet = write_package[start].last_packet;
+ flags_msb = write_package[start].flags_msb;
+ write_thread->start = (write_thread->start + 1)% MAX_WRITE_THREAD_PACKAGE;
+ write_thread->count_write--;
+ pthread_mutex_unlock(&write_thread->mutex_write);
+ /*if(write_thread->count_write != 0){
+ LOG_W(HW,"count write = %d, start = %d, end = %d\n", write_thread->count_write, write_thread->start, write_thread->end);
+ }*/
+
+ #if defined(__x86_64) || defined(__i386__)
+ #ifdef __AVX2__
+ nsamps2 = (nsamps+7)>>3;
+ __m256i buff_tx[8][nsamps2];
+ #else
+ nsamps2 = (nsamps+3)>>2;
+ __m128i buff_tx[8][nsamps2];
+ #endif
+ #elif defined(__arm__)
+ nsamps2 = (nsamps+3)>>2;
+ int16x8_t buff_tx[8][nsamps2];
+ #else
+ #error Unsupported CPU architecture, USRP device cannot be built
+ #endif
+
+ // bring RX data into 12 LSBs for softmodem RX
+ for (int i=0; i<cc; i++) {
+ for (int j=0; j<nsamps2; j++) {
+ #if defined(__x86_64__) || defined(__i386__)
+ #ifdef __AVX2__
+ buff_tx[i][j] = _mm256_slli_epi16(((__m256i *)buff[i])[j],4);
+ #else
+ buff_tx[i][j] = _mm_slli_epi16(((__m128i *)buff[i])[j],4);
+ #endif
+ #elif defined(__arm__)
+ buff_tx[i][j] = vshlq_n_s16(((int16x8_t *)buff[i])[j],4);
+ #endif
+ }
+ }
+
+
+ s->tx_md.has_time_spec = true;
+ s->tx_md.start_of_burst = (s->tx_count==0) ? true : first_packet;
+ s->tx_md.end_of_burst = last_packet;
+ s->tx_md.time_spec = uhd::time_spec_t::from_ticks(timestamp, s->sample_rate);
+ s->tx_count++;
+
// bit 3 enables gpio (for backward compatibility)
if (flags_msb&8) {
// push GPIO bits 7-9 from flags_msb
@@ -432,11 +579,34 @@ static int trx_usrp_write(openair0_device *device,
ret = (int)s->tx_stream->send(&(((int16_t *)buff_tx[0])[0]), nsamps, s->tx_md);
}
- if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
+ if (ret != nsamps) LOG_E(HW,"[xmit] tx samples %d != %d\n",ret,nsamps);
+ VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_USRP_SEND_RETURN, ret );
+ VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_THREAD, 0 );
+
+ if(0) break;
+ }
+
+ return NULL;
+}
+
+int trx_usrp_write_init(openair0_device *device){
+
+ uhd::set_thread_priority_safe(1.0);
+ openair0_thread_t *write_thread = &device->write_thread;
+ printf("initializing tx write thread\n");
+
+ write_thread->start = 0;
+ write_thread->end = 0;
+ write_thread->count_write = 0;
+ printf("end of tx write thread\n");
- return ret;
+ pthread_create(&write_thread->pthread_write,NULL,trx_usrp_write_thread,(void *)device);
+
+ return(0);
}
+//---------------------end-------------------------
+
/*! \brief Receive samples from hardware.
* Read \ref nsamps samples from each channel to buffers. buff[0] is the array for
* the first channel. *ptimestamp is the time at which the first sample
@@ -765,6 +935,7 @@ extern "C" {
device->trx_stop_func = trx_usrp_stop;
device->trx_set_freq_func = trx_usrp_set_freq;
device->trx_set_gains_func = trx_usrp_set_gains;
+ device->trx_write_init = trx_usrp_write_init;
// hotfix! to be checked later
@@ -805,7 +976,6 @@ extern "C" {
double usrp_master_clock;
if (device_adds[0].get("type") == "b200") {
- printf("Found USRP b200\n");
device->type = USRP_B200_DEV;
usrp_master_clock = 30.72e6;
args += boost::str(boost::format(",master_clock_rate=%f") % usrp_master_clock);
diff --git a/targets/ARCH/rfsimulator/README.md b/targets/ARCH/rfsimulator/README.md
index 421cc662bb2a6fe1a462317f578bd15a82dbc430..9ec0ae50659ecf34f7d30a6ddccd1ab0397efa45 100644
--- a/targets/ARCH/rfsimulator/README.md
+++ b/targets/ARCH/rfsimulator/README.md
@@ -96,11 +96,19 @@ sudo RFSIMULATOR=server ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-LTE-
### Launch UE in another window
```bash
-sudo RFSIMULATOR=<TARGET_GNB_INTERFACE_ADDRESS> ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path ../../../ci-scripts/rrc-files
+sudo RFSIMULATOR=<TARGET_GNB_INTERFACE_ADDRESS> ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path .
```
-Note:
+
+Notes:
+
1. <TARGET_GNB_INTERFACE_ADDRESS> can be 127.0.0.1 if both gNB and nrUE executables run on the same host, OR the IP interface address of the remote host running the gNB executable, if the gNB and nrUE run on separate hosts
-2. the --rrc_config_path parameter can be omitted (but not necessarily) if the gNB and nrUE run on the same host, in which case the gNB provides the nrUE with the necessary rrc configuration
+2. the --rrc_config_path parameter SHALL specify where the 2 RAW files are located (`rbconfig.raw` and `reconfig.raw`).
+ - If you are running on the same machine and launched the 2 executables (`nr-softmodem` and `nr-uesoftmodem`) from the same directory, nothing has to be done.
+ - If you launched the 2 executables from 2 different folders, just point to the location where you launched the `nr-softmodem`:
+ * `sudo RFSIMULATOR=<TARGET_GNB_INTERFACE_ADDRESS> ./nr-uesoftmodem --rfsim --phy-test --rrc_config_path /the/path/where/you/launched/nr-softmodem`
+ - If you are not running on the same machine or launched the 2 executables from 2 different folders, you need to **COPY** the 2 raw files
+ * `scp usera@machineA:/the/path/where/you/launched/nr-softmodem/r*config.raw userb@machineB:/the/path/where/you/will/launch/nr-uesoftmodem/`
+ * Obviously this operation SHALL be done before launching the `nr-uesoftmodem` executable.
3. to enable the noS1 mode --noS1 and --nokrnmod 1 options should be added to the command line
diff --git a/targets/ARCH/rfsimulator/apply_channelmod.c b/targets/ARCH/rfsimulator/apply_channelmod.c
index faf84bb0aaa47dba7d287a5af4195155451eb33b..7aa5d78bf85657b07c661d8b539cee6a42b7bb7a 100644
--- a/targets/ARCH/rfsimulator/apply_channelmod.c
+++ b/targets/ARCH/rfsimulator/apply_channelmod.c
@@ -34,6 +34,9 @@
#include <common/utils/LOG/log.h>
#include <common/config/config_userapi.h>
#include <openair1/SIMULATION/TOOLS/sim.h>
+#include <common/utils/telnetsrv/telnetsrv.h>
+#include <common/utils/load_module_shlib.h>
+#include <targets/ARCH/rfsimulator/rfsimulator.h>
/*
Legacy study:
@@ -99,8 +102,8 @@ void rxAddInput( struct complex16 *input_sig, struct complex16 *after_channel_si
} //l
}
- out_ptr->r += round(rx_tmp.x*pathLossLinear + noise_per_sample*gaussdouble(0.0,1.0));
- out_ptr->i += round(rx_tmp.y*pathLossLinear + noise_per_sample*gaussdouble(0.0,1.0));
+ out_ptr->r += round(rx_tmp.x*pathLossLinear + noise_per_sample*gaussZiggurat(0.0,1.0));
+ out_ptr->i += round(rx_tmp.y*pathLossLinear + noise_per_sample*gaussZiggurat(0.0,1.0));
out_ptr++;
}
@@ -112,3 +115,4 @@ void rxAddInput( struct complex16 *input_sig, struct complex16 *after_channel_si
channelDesc->path_loss_dB,
10*log10(noise_per_sample));
}
+
diff --git a/targets/ARCH/rfsimulator/new_channel_sim.c b/targets/ARCH/rfsimulator/new_channel_sim.c
new file mode 100644
index 0000000000000000000000000000000000000000..0501babd2004df7b92b13b7c1e0adb919b57ec4f
--- /dev/null
+++ b/targets/ARCH/rfsimulator/new_channel_sim.c
@@ -0,0 +1,108 @@
+/*
+* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+* contributor license agreements. See the NOTICE file distributed with
+* this work for additional information regarding copyright ownership.
+* The OpenAirInterface Software Alliance licenses this file to You under
+* the OAI Public License, Version 1.1 (the "License"); you may not use this file
+* except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.openairinterface.org/?page_id=698
+*
+* Author and copyright: Laurent Thomas, open-cells.com
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*-------------------------------------------------------------------------------
+* For more information about the OpenAirInterface (OAI) Software Alliance:
+* contact@openairinterface.org
+*/
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdbool.h>
+#include <errno.h>
+
+
+#include <common/utils/assertions.h>
+#include <common/utils/LOG/log.h>
+#include <common/config/config_userapi.h>
+#include <openair1/SIMULATION/TOOLS/sim.h>
+#include <targets/ARCH/rfsimulator/rfsimulator.h>
+
+// Ziggurat
+static double wn[128],fn[128];
+static uint32_t iz,jz,jsr=123456789,kn[128];
+static int32_t hz;
+#define SHR3 (jz=jsr, jsr^=(jsr<<13),jsr^=(jsr>>17),jsr^=(jsr<<5),jz+jsr)
+#define UNI (0.5+(signed) SHR3 * 0.2328306e-9)
+
+double nfix(void) {
+ const double r = 3.442620;
+ static double x, y;
+
+ for (;;) {
+ x=hz * wn[iz];
+
+ if (iz==0) {
+ do {
+ x = - 0.2904764 * log (UNI);
+ y = - log (UNI);
+ } while (y+y < x*x);
+
+ return (hz>0)? r+x : -r-x;
+ }
+
+ if (fn[iz]+UNI*(fn[iz-1]-fn[iz])<exp(-0.5*x*x)) {
+ return x;
+ }
+
+ hz = SHR3;
+ iz = hz&127;
+
+ if (abs(hz) < kn[iz]) {
+ return ((hz)*wn[iz]);
+ }
+ }
+}
+
+/*!\Procedure to create tables for normal distribution kn,wn and fn. */
+
+void tableNor(unsigned long seed) {
+ jsr=seed;
+ double dn = 3.442619855899;
+ int i;
+ const double m1 = 2147483648.0;
+ double q;
+ double tn = 3.442619855899;
+ const double vn = 9.91256303526217E-03;
+ q = vn/exp(-0.5*dn*dn);
+ kn[0] = ((dn/q)*m1);
+ kn[1] = 0;
+ wn[0] = ( q / m1 );
+ wn[127] = ( dn / m1 );
+ fn[0] = 1.0;
+ fn[127] = ( exp ( - 0.5 * dn * dn ) );
+
+ for ( i = 126; 1 <= i; i-- ) {
+ dn = sqrt (-2.0 * log ( vn/dn + exp(-0.5*dn*dn)));
+ kn[i+1] = ((dn / tn)*m1);
+ tn = dn;
+ fn[i] = (exp (-0.5*dn*dn));
+ wn[i] = (dn / m1);
+ }
+
+ return;
+}
+
+double gaussZiggurat(double mean, double variance) {
+ hz=SHR3;
+ iz=hz&127;
+ return abs(hz)<kn[iz]? hz*wn[iz] : nfix();
+}
diff --git a/targets/ARCH/rfsimulator/rfsimulator.h b/targets/ARCH/rfsimulator/rfsimulator.h
new file mode 100644
index 0000000000000000000000000000000000000000..292873032e010d7d1443f5e5424fe4c087962f39
--- /dev/null
+++ b/targets/ARCH/rfsimulator/rfsimulator.h
@@ -0,0 +1,37 @@
+/*
+* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
+* contributor license agreements. See the NOTICE file distributed with
+* this work for additional information regarding copyright ownership.
+* The OpenAirInterface Software Alliance licenses this file to You under
+* the OAI Public License, Version 1.1 (the "License"); you may not use this file
+* except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.openairinterface.org/?page_id=698
+*
+* Author and copyright: Laurent Thomas, open-cells.com
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*-------------------------------------------------------------------------------
+* For more information about the OpenAirInterface (OAI) Software Alliance:
+* contact@openairinterface.org
+*/
+
+#ifndef __RFSIMULATOR_H
+#define __RFSIMULATOR_H
+double gaussZiggurat(double mean, double variance);
+void tableNor(unsigned long seed);
+void rxAddInput( struct complex16 *input_sig,
+ struct complex16 *after_channel_sig,
+ int rxAnt,
+ channel_desc_t *channelDesc,
+ int nbSamples,
+ uint64_t TS,
+ uint32_t CirSize
+ );
+
+#endif
diff --git a/targets/ARCH/rfsimulator/simulator.c b/targets/ARCH/rfsimulator/simulator.c
index dc448b33e91a20e77d0723b983ea7d03b46cd353..81ea1cf8ba147a2f4828eab677a1a259a3c991ea 100644
--- a/targets/ARCH/rfsimulator/simulator.c
+++ b/targets/ARCH/rfsimulator/simulator.c
@@ -44,12 +44,14 @@
#include <common/utils/assertions.h>
#include <common/utils/LOG/log.h>
#include <common/utils/load_module_shlib.h>
+#include <common/utils/telnetsrv/telnetsrv.h>
#include <common/config/config_userapi.h>
#include "common_lib.h"
#include <openair1/PHY/defs_eNB.h>
#include "openair1/PHY/defs_UE.h"
#define CHANNELMOD_DYNAMICLOAD
#include <openair1/SIMULATION/TOOLS/sim.h>
+#include <targets/ARCH/rfsimulator/rfsimulator.h>
#define PORT 4043 //default TCP port for this simulator
#define CirSize 307200 // 100ms is enough
@@ -77,11 +79,25 @@ extern RAN_CONTEXT_t RC;
#define RFSIMULATOR_PARAMS_DESC {\
{"serveraddr", "<ip address to connect to>\n", 0, strptr:&(rfsimulator->ip), defstrval:"127.0.0.1", TYPE_STRING, 0 },\
{"serverport", "<port to connect to>\n", 0, u16ptr:&(rfsimulator->port), defuintval:PORT, TYPE_UINT16, 0 },\
- {RFSIMU_OPTIONS_PARAMNAME, RFSIM_CONFIG_HELP_OPTIONS, 0, strlistptr:NULL, defstrlistval:NULL, TYPE_STRINGLIST,0},\
+ {RFSIMU_OPTIONS_PARAMNAME, RFSIM_CONFIG_HELP_OPTIONS, 0, strlistptr:NULL, defstrlistval:NULL, TYPE_STRINGLIST,0 },\
{"IQfile", "<file path to use when saving IQs>\n", 0, strptr:&(saveF), defstrval:"/tmp/rfsimulator.iqs",TYPE_STRING, 0 },\
- {"modelname", "<channel model name>\n", 0, strptr:&(modelname), defstrval:"AWGN", TYPE_STRING, 0 }\
+ {"modelname", "<channel model name>\n", 0, strptr:&(modelname), defstrval:"AWGN", TYPE_STRING, 0 },\
+ {"ploss", "<channel path loss in dB>\n", 0, dblptr:&(rfsimulator->chan_pathloss), defdblval:0, TYPE_DOUBLE, 0 },\
+ {"forgetfact", "<channel forget factor ((0 to 1)>\n", 0, dblptr:&(rfsimulator->chan_forgetfact), defdblval:0, TYPE_DOUBLE, 0 },\
+ {"offset", "<channel offset in samps>\n", 0, iptr:&(rfsimulator->chan_offset), defintval:0, TYPE_INT, 0 }\
};
+
+
+static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt, void *arg);
+static telnetshell_cmddef_t rfsimu_cmdarray[] = {
+ {"setmodel","<model name>",(cmdfunc_t)rfsimu_setchanmod_cmd,TELNETSRV_CMDFLAG_PUSHINTPOOLQ},
+ {"","",NULL},
+};
+
+static telnetshell_vardef_t rfsimu_vardef[] = {
+ {"",0,NULL}
+};
pthread_mutex_t Sockmutex;
typedef struct complex16 sample_t; // 2*16 bits complex number
@@ -113,6 +129,11 @@ typedef struct {
double sample_rate;
double tx_bw;
int channelmod;
+ double chan_pathloss;
+ double chan_forgetfact;
+ int chan_offset;
+ void *telnetcmd_qid;
+ poll_telnetcmdq_func_t poll_telnetcmdq;
} rfsimulator_state_t;
@@ -146,13 +167,27 @@ void allocCirBuf(rfsimulator_state_t *bridge, int sock) {
// the value channel_model->path_loss_dB seems only a storage place (new_channel_desc_scm() only copy the passed value)
// Legacy changes directlty the variable channel_model->path_loss_dB place to place
// while calling new_channel_desc_scm() with path losses = 0
+ static bool init_done=false;
+
+ if (!init_done) {
+ uint64_t rand;
+ FILE *h=fopen("/dev/random","r");
+ if ( 1 != fread(&rand,sizeof(rand),1,h) )
+ LOG_W(HW, "Simulator can't read /dev/random\n");
+ fclose(h);
+ randominit(rand);
+ tableNor(rand);
+ init_done=true;
+ }
+
ptr->channel_model=new_channel_desc_scm(bridge->tx_num_channels,bridge->rx_num_channels,
bridge->channelmod,
bridge->sample_rate,
bridge->tx_bw,
- 0.0, // forgetting_factor
- 0, // maybe used for TA
- 0); // path_loss in dB
+ bridge->chan_forgetfact, // forgetting_factor
+ bridge->chan_offset, // maybe used for TA
+ bridge->chan_pathloss); // path_loss in dB
+ set_channeldesc_owner(ptr->channel_model, RFSIMU_MODULEID);
random_channel(ptr->channel_model,false);
}
}
@@ -279,6 +314,41 @@ void rfsimulator_readconfig(rfsimulator_state_t *rfsimulator) {
rfsimulator->typeStamp = UE_MAGICDL_FDD;
}
+static int rfsimu_setchanmod_cmd(char *buff, int debug, telnet_printfunc_t prnt, void *arg) {
+ char *modelname=NULL;
+ int s = sscanf(buff,"%ms\n",&modelname);
+ if (s == 1) {
+ int channelmod=modelid_fromname(modelname);
+ if (channelmod<0)
+ prnt("ERROR: model %s unknown\n",modelname);
+ else {
+ rfsimulator_state_t *t = (rfsimulator_state_t *)arg;
+ for (int i=0; i<FD_SETSIZE; i++) {
+ buffer_t *b=&t->buf[i];
+ if (b->conn_sock >= 0 ) {
+ channel_desc_t *newmodel=new_channel_desc_scm(t->tx_num_channels,t->rx_num_channels,
+ channelmod,
+ t->sample_rate,
+ t->tx_bw,
+ t->chan_forgetfact, // forgetting_factor
+ t->chan_offset, // maybe used for TA
+ t->chan_pathloss); // path_loss in dB
+ set_channeldesc_owner(newmodel, RFSIMU_MODULEID);
+ random_channel(newmodel,false);
+ channel_desc_t *oldmodel=b->channel_model;
+ b->channel_model=newmodel;
+ free_channel_desc_scm(oldmodel);
+ prnt("New model %s applied to channel connected to sock %d\n",modelname,i);
+ }
+ }
+ }
+ } else {
+ prnt("ERROR: no model specified\n");
+ }
+ free(modelname);
+ return CMDSTATUS_FOUND;
+}
+
int server_start(openair0_device *device) {
rfsimulator_state_t *t = (rfsimulator_state_t *) device->priv;
t->typeStamp=ENB_MAGICDL_FDD;
@@ -368,6 +438,7 @@ static int rfsimulator_write_internal(rfsimulator_state_t *t, openair0_timestamp
if (t->lastWroteTS > timestamp+nsamps)
LOG_E(HW,"Not supported to send Tx out of order (same in USRP) %lu, %lu\n",
t->lastWroteTS, timestamp);
+
t->lastWroteTS=timestamp+nsamps;
if (!alreadyLocked)
@@ -469,16 +540,21 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi
b->trashingPacket=true;
} else if ( b->lastReceivedTS < b->th.timestamp) {
int nbAnt= b->th.nbAnt;
-
+
+ if ( b->th.timestamp-b->lastReceivedTS < CirSize ) {
for (uint64_t index=b->lastReceivedTS; index < b->th.timestamp; index++ ) {
for (int a=0; a < nbAnt; a++) {
b->circularBuf[(index*nbAnt+a)%CirSize].r = 0;
b->circularBuf[(index*nbAnt+a)%CirSize].i = 0;
}
}
+ } else {
+ memset(b->circularBuf, 0, sampleToByte(CirSize,1));
+ }
if (b->lastReceivedTS != 0 && b->th.timestamp-b->lastReceivedTS > 50 )
LOG_W(HW,"UEsock: %d gap of: %ld in reception\n", fd, b->th.timestamp-b->lastReceivedTS );
+
b->lastReceivedTS=b->th.timestamp;
} else if ( b->lastReceivedTS > b->th.timestamp && b->th.size == 1 ) {
@@ -497,7 +573,7 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi
LOG_E(HW,"UEsock: %d Tx/Rx shift too large Tx:%lu, Rx:%lu\n", fd, t->lastWroteTS, b->lastReceivedTS);
pthread_mutex_unlock(&Sockmutex);
- b->transferPtr=(char *)&b->circularBuf[b->lastReceivedTS%CirSize];
+ b->transferPtr=(char *)&b->circularBuf[(b->lastReceivedTS*b->th.nbAnt)%CirSize];
b->remainToTransfer=sampleToByte(b->th.size, b->th.nbAnt);
}
@@ -561,6 +637,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo
pthread_mutex_unlock(&Sockmutex);
usleep(10000);
pthread_mutex_lock(&Sockmutex);
+
if ( t->lastWroteTS < t->nextTimestamp ) {
// Assuming Tx is not done fully in another thread
// We can never write is the past from the received time
@@ -574,6 +651,7 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo
for ( int i=0; i < t->tx_num_channels; i++)
samplesVoid[i]=(void *)&v;
+
LOG_I(HW, "No samples Tx occured, so we send 1 sample to notify it: Tx:%lu, Rx:%lu\n",
t->lastWroteTS, t->nextTimestamp);
rfsimulator_write_internal(t, t->nextTimestamp,
@@ -625,8 +703,10 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo
// it seems legacy behavior is: never in UL, each frame in DL
if (reGenerateChannel)
random_channel(ptr->channel_model,0);
+ if (t->poll_telnetcmdq)
+ t->poll_telnetcmdq(t->telnetcmd_qid,t);
- for (int a=0; a<nbAnt; a++) {
+ for (int a=0; a<nbAnt; a++) {//loop over number of Rx antennas
if ( ptr->channel_model != NULL ) // apply a channel model
rxAddInput( ptr->circularBuf, (struct complex16 *) samplesVoid[a],
a,
@@ -637,13 +717,16 @@ int rfsimulator_read(openair0_device *device, openair0_timestamp *ptimestamp, vo
);
else { // no channel modeling
sample_t *out=(sample_t *)samplesVoid[a];
-
- for ( int i=0; i < nsamps; i++ ) {
- out[i].r+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].r;
- out[i].i+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt+a)%CirSize].i;
- }
+ int nbAnt_tx = ptr->th.nbAnt;//number of Tx antennas
+ //LOG_I(HW, "nbAnt_tx %d\n",nbAnt_tx);
+ for (int i=0; i < nsamps; i++) {//loop over nsamps
+ for (int a_tx=0; a_tx<nbAnt_tx; a_tx++){//sum up signals from nbAnt_tx antennas
+ out[i].r+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt_tx+a_tx)%CirSize].r;
+ out[i].i+=ptr->circularBuf[((t->nextTimestamp+i)*nbAnt_tx+a_tx)%CirSize].i;
+ } // end for a_tx
+ } // end for i (number of samps)
} // end of no channel modeling
- } // end for a...
+ } // end for a (number of rx antennas)
}
}
@@ -679,6 +762,9 @@ int rfsimulator_set_freq(openair0_device *device, openair0_config_t *openair0_cf
int rfsimulator_set_gains(openair0_device *device, openair0_config_t *openair0_cfg) {
return 0;
}
+int rfsimulator_write_init(openair0_device *device){
+ return 0;
+}
__attribute__((__visibility__("default")))
int device_init(openair0_device *device, openair0_config_t *openair0_cfg) {
// to change the log level, use this on command line
@@ -702,6 +788,7 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) {
device->type = USRP_B200_DEV;
device->openair0_cfg=&openair0_cfg[0];
device->priv = rfsimulator;
+ device->trx_write_init = rfsimulator_write_init;
for (int i=0; i<FD_SETSIZE; i++)
rfsimulator->buf[i].conn_sock=-1;
@@ -712,7 +799,20 @@ int device_init(openair0_device *device, openair0_config_t *openair0_cfg) {
rfsimulator->rx_num_channels=openair0_cfg->rx_num_channels;
rfsimulator->sample_rate=openair0_cfg->sample_rate;
rfsimulator->tx_bw=openair0_cfg->tx_bw;
- randominit(0);
+ //randominit(0);
set_taus_seed(0);
+ /* look for telnet server, if it is loaded, add the channel modeling commands to it */
+ add_telnetcmd_func_t addcmd = (add_telnetcmd_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_ADDCMD_FNAME);
+
+ if (addcmd != NULL) {
+ rfsimulator->poll_telnetcmdq = (poll_telnetcmdq_func_t)get_shlibmodule_fptr("telnetsrv", TELNET_POLLCMDQ_FNAME);
+ addcmd("rfsimu",rfsimu_vardef,rfsimu_cmdarray);
+ for(int i=0; rfsimu_cmdarray[i].cmdfunc != NULL; i++) {
+ if ( rfsimu_cmdarray[i].qptr != NULL) {
+ rfsimulator->telnetcmd_qid = rfsimu_cmdarray[i].qptr;
+ break;
+ }
+ }
+ }
return 0;
}
diff --git a/targets/ARCH/tcp_bridge/tcp_bridge.c b/targets/ARCH/tcp_bridge/tcp_bridge.c
index 8b287acfa14b24f009e5b30a653504e57c832269..f8c12dcb7acb0e89140f106b6b43eb246dd87c1b 100644
--- a/targets/ARCH/tcp_bridge/tcp_bridge.c
+++ b/targets/ARCH/tcp_bridge/tcp_bridge.c
@@ -243,6 +243,11 @@ ts += nsamps;
return nsamps;
}
+int tcp_bridge_write_init(openair0_device *device)
+{
+ return 0;
+}
+
__attribute__((__visibility__("default")))
int device_init(openair0_device* device, openair0_config_t *openair0_cfg)
{
@@ -267,6 +272,7 @@ int device_init(openair0_device* device, openair0_config_t *openair0_cfg)
device->trx_set_gains_func = tcp_bridge_set_gains;
device->trx_write_func = tcp_bridge_write;
device->trx_read_func = tcp_bridge_read;
+ device->trx_write_init = tcp_bridge_write_init;
device->priv = tcp_bridge;
diff --git a/targets/COMMON/create_nr_tasks.c b/targets/COMMON/create_nr_tasks.c
index 24c4115980b795055657de60673fa388f25d982b..13f72b387665f5fda364660301a7b96d13946459 100644
--- a/targets/COMMON/create_nr_tasks.c
+++ b/targets/COMMON/create_nr_tasks.c
@@ -51,17 +51,17 @@ int create_gNB_tasks(uint32_t gnb_nb)
}
if (gnb_nb > 0) {
- /* Last task to create, others task must be ready before its start */
+ // Last task to create, others task must be ready before its start
if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) {
LOG_E(GNB_APP, "Create task for gNB APP failed\n");
return -1;
}
}
-/*
+
if (EPC_MODE_ENABLED) {
if (gnb_nb > 0) {
- if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) {
+ /*if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) {
LOG_E(SCTP, "Create task for SCTP failed\n");
return -1;
}
@@ -69,7 +69,7 @@ int create_gNB_tasks(uint32_t gnb_nb)
if (itti_create_task (TASK_S1AP, s1ap_eNB_task, NULL) < 0) {
LOG_E(S1AP, "Create task for S1AP failed\n");
return -1;
- }
+ }*/
if(!emulate_rf){
if (itti_create_task (TASK_UDP, udp_eNB_task, NULL) < 0) {
LOG_E(UDP_, "Create task for UDP failed\n");
@@ -84,7 +84,15 @@ int create_gNB_tasks(uint32_t gnb_nb)
}
}
-*/
+
+ /*if (gnb_nb > 0) {
+ // Last task to create, others task must be ready before its start
+ if (itti_create_task (TASK_GNB_APP, gNB_app_task, NULL) < 0) {
+ LOG_E(GNB_APP, "Create task for gNB APP failed\n");
+ return -1;
+ }
+ }*/
+
if (gnb_nb > 0) {
LOG_I(NR_RRC,"Creating NR RRC gNB Task\n");
@@ -100,4 +108,4 @@ int create_gNB_tasks(uint32_t gnb_nb)
return 0;
}
-#endif
+//#endif
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf
index 1363be3bce6962951e61ac96f7adf74c97e24466..d5bc492644ce6466e5f8a5f25aab4c9f52842b91 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.32PRB.usrpx300.conf
@@ -105,8 +105,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +114,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf
index 1fbc8e30ef27fd9db09c4ee06057670e6d03308a..93a6c7fbc92ee18b71e592a0a0dd31e0ddaba260 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band257.tm1.66PRB.usrpn300.conf
@@ -105,8 +105,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +114,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf
new file mode 100644
index 0000000000000000000000000000000000000000..81796ada2c8407ae1274b389194002cb4c05e564
--- /dev/null
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.106PRB.slave.conf
@@ -0,0 +1,295 @@
+Active_gNBs = ( "gNB-Eurecom-5GNRBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+gNBs =
+(
+ {
+ ////////// Identification parameters:
+ gNB_ID = 0xe00;
+
+ cell_type = "CELL_MACRO_GNB";
+
+ gNB_name = "gNB-Eurecom-5GNRBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+
+ plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;});
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ ssb_SubcarrierOffset = 0;
+ pdsch_AntennaPorts = 1;
+
+ servingCellConfigCommon = (
+ {
+ #spCellConfigCommon
+
+ physCellId = 0;
+
+# downlinkConfigCommon
+ #frequencyInfoDL
+ # this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
+ absoluteFrequencySSB = 641032;
+ dl_frequencyBand = 78;
+ # this is 3600 MHz
+ dl_absoluteFrequencyPointA = 640000;
+ #scs-SpecificCarrierList
+ dl_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ dl_subcarrierSpacing = 1;
+ dl_carrierBandwidth = 106;
+ #initialDownlinkBWP
+ #genericParameters
+ # this is RBstart=0,L=50 (275*(L-1))+RBstart
+ initialDLBWPlocationAndBandwidth = 6366;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialDLBWPsubcarrierSpacing = 1;
+ #pdcch-ConfigCommon
+ initialDLBWPcontrolResourceSetZero = 12;
+ initialDLBWPsearchSpaceZero = 0;
+ #pdsch-ConfigCommon
+ #pdschTimeDomainAllocationList (up to 16 entries)
+ initialDLBWPk0_0 = 0;
+ #initialULBWPmappingType
+ #0=typeA,1=typeB
+ initialDLBWPmappingType_0 = 0;
+ #this is SS=1,L=13
+ initialDLBWPstartSymbolAndLength_0 = 40;
+
+ initialDLBWPk0_1 = 0;
+ initialDLBWPmappingType_1 = 0;
+ #this is SS=2,L=12
+ initialDLBWPstartSymbolAndLength_1 = 53;
+
+ initialDLBWPk0_2 = 0;
+ initialDLBWPmappingType_2 = 0;
+ #this is SS=1,L=12
+ initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=4
+ initialDLBWPstartSymbolAndLength_3 = 57;
+
+ #uplinkConfigCommon
+ #frequencyInfoUL
+ ul_frequencyBand = 78;
+ #scs-SpecificCarrierList
+ ul_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ ul_subcarrierSpacing = 1;
+ ul_carrierBandwidth = 106;
+ pMax = 20;
+ #initialUplinkBWP
+ #genericParameters
+ initialULBWPlocationAndBandwidth = 6366;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialULBWPsubcarrierSpacing = 1;
+ #rach-ConfigCommon
+ #rach-ConfigGeneric
+ prach_ConfigurationIndex = 98;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+ prach_msg1_FDM = 0;
+ prach_msg1_FrequencyStart = 0;
+ zeroCorrelationZoneConfig = 13;
+ preambleReceivedTargetPower = -118;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+ preambleTransMax = 6;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+ powerRampingStep = 1;
+#ra_ReponseWindow
+#1,2,4,8,10,20,40,80
+ ra_ResponseWindow = 4;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
+#oneHalf (0..15) 4,8,12,16,...60,64
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+ ra_ContentionResolutionTimer = 7;
+ rsrp_ThresholdSSB = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
+ prach_RootSequenceIndex = 1;
+ # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+ #
+ msg1_SubcarrierSpacing = 1,
+
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+ restrictedSetConfig = 0,
+ # pusch-ConfigCommon (up to 16 elements)
+ initialULBWPk2_0 = 2;
+ initialULBWPmappingType_0 = 1
+ # this is SS=0 L=11
+ initialULBWPstartSymbolAndLength_0 = 55;
+
+ initialULBWPk2_1 = 2;
+ initialULBWPmappingType_1 = 1;
+ # this is SS=0 L=12
+ initialULBWPstartSymbolAndLength_1 = 69;
+
+ initialULBWPk2_2 = 7;
+ initialULBWPmappingType_2 = 1;
+ # this is SS=10 L=4
+ initialULBWPstartSymbolAndLength_2 = 52;
+
+
+ msg3_DeltaPreamble = 1;
+ p0_NominalWithGrant =-90;
+
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+ pucchGroupHopping = 0;
+ hoppingId = 40;
+ p0_nominal = -90;
+# ssb_PositionsInBurs_BitmapPR
+# 1=short, 2=medium, 3=long
+ ssb_PositionsInBurst_PR = 2;
+ ssb_PositionsInBurst_Bitmap = 1;
+
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+ ssb_periodicityServingCell = 2;
+
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+ dmrs_TypeA_Position = 0;
+
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ subcarrierSpacing = 1;
+
+
+ #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ referenceSubcarrierSpacing = 1;
+ # pattern1
+ # dl_UL_TransmissionPeriodicity
+ # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+ dl_UL_TransmissionPeriodicity = 6;
+ nrofDownlinkSlots = 7;
+ nrofDownlinkSymbols = 6;
+ nrofUplinkSlots = 2;
+ nrofUplinkSymbols = 4;
+
+ ssPBCH_BlockPower = 10;
+ }
+
+ );
+
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "192.168.12.26";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+ target_enb_x2_ip_address = (
+ { ipv4 = "192.168.12.188";
+ ipv6 = "192:168:30::17";
+ preference = "ipv4";
+ }
+ );
+
+ NETWORK_INTERFACES :
+ {
+
+ GNB_INTERFACE_NAME_FOR_S1_MME = "enp0s31f6";
+ GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.75/24";
+ GNB_INTERFACE_NAME_FOR_S1U = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.75/24";
+ GNB_PORT_FOR_S1U = 2152; # Spec 2152
+
+ GNB_IPV4_ADDRESS_FOR_X2C = "192.168.12.75/23";
+ GNB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 114;
+ eNB_instances = [0];
+ sdr_addrs = "addr=192.168.20.2,mgmt_addr=192.168.20.2";
+ clock_src = "internal";
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
+ parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
+ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
+ worker_config = "WORKER_ENABLE";
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="medium";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="medium";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="medium";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf
index 904a4556007e3b20f2a7ae18282fc31c4c8a439b..dbcbb2ed4f5456add888adeb842345d3e94fc5f2 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpn300.conf
@@ -46,7 +46,7 @@ gNBs =
#initialDownlinkBWP
#genericParameters
# this is RBstart=0,L=50 (275*(L-1))+RBstart
- initialDLBWPlocationAndBandwidth = 13475;
+ initialDLBWPlocationAndBandwidth = 6366;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
@@ -59,7 +59,7 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
- #this is SS=2,L=3
+ #this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
@@ -71,6 +71,12 @@ gNBs =
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=4
+ initialDLBWPstartSymbolAndLength_3 = 57;
+
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
@@ -83,7 +89,7 @@ gNBs =
pMax = 20;
#initialUplinkBWP
#genericParameters
- initialULBWPlocationAndBandwidth = 13475;
+ initialULBWPlocationAndBandwidth = 6366;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
@@ -105,8 +111,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,16 +120,16 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
-
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
+
# pusch-ConfigCommon (up to 16 elements)
initialULBWPk2_0 = 2;
initialULBWPmappingType_0 = 1
@@ -135,6 +141,11 @@ gNBs =
# this is SS=0 L=12
initialULBWPstartSymbolAndLength_1 = 69;
+ initialULBWPk2_2 = 7;
+ initialULBWPmappingType_2 = 1;
+ # this is SS=10 L=4
+ initialULBWPstartSymbolAndLength_2 = 52;
+
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
@@ -237,8 +248,10 @@ RUs = (
max_pdschReferenceSignalPower = -27;
max_rxgain = 114;
eNB_instances = [0];
- sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2";
- #clock_src = "external";
+ #beamforming 1x4 matrix:
+ bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000];
+ sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2";
+ clock_src = "external";
}
);
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf
index 06aa4f6f9f69eb3fc6cebcfca30391e1c6b91340..0b04dc82d1741148aa38a192c5397682e3b073d3 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.usrpx300.conf
@@ -33,10 +33,10 @@ gNBs =
# downlinkConfigCommon
#frequencyInfoDL
# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
- absoluteFrequencySSB = 633032;
+ absoluteFrequencySSB = 641032;
dl_frequencyBand = 78;
- # this is 3480 MHz
- dl_absoluteFrequencyPointA = 632000;
+ # this is 3600 MHz
+ dl_absoluteFrequencyPointA = 640000;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
@@ -59,7 +59,7 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
- #this is SS=2,L=3
+ #this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
@@ -71,6 +71,11 @@ gNBs =
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=5
+ initialDLBWPstartSymbolAndLength_3 = 57;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
@@ -105,8 +110,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +119,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
@@ -148,7 +153,7 @@ gNBs =
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
- ssb_PositionsInBurst_Bitmap = 255;
+ ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
@@ -237,7 +242,8 @@ RUs = (
max_pdschReferenceSignalPower = -27;
max_rxgain = 114;
eNB_instances = [0];
- sdr_addrs = "type=x300";
+ sdr_addrs = "type=x300";
+ clock_src = "external";
}
);
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf
index b82c455ef4359f04720dd853de6c0ff87fee5283..ae17efc9bd0c674df1a29f2e59b4b3efea138b03 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpn300.conf
@@ -59,7 +59,7 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
- #this is SS=2,L=3
+ #this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
@@ -71,6 +71,11 @@ gNBs =
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=5
+ initialDLBWPstartSymbolAndLength_3 = 57;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
@@ -105,8 +110,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +119,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf
index 4cbec5b86e7ecbb25b9c36abdd1d6aab20b716d9..c907dcfe8d84c38ea5f7ae353408d45de201cb09 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.217PRB.usrpx300.conf
@@ -59,7 +59,7 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
- #this is SS=2,L=3
+ #this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
@@ -71,6 +71,11 @@ gNBs =
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=5
+ initialDLBWPstartSymbolAndLength_3 = 57;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
@@ -105,8 +110,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +119,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf
index f5e2298a9971243481be25ea9a7260d419ac1172..464ce6b9aae149f2278f001b7430d832371a9b61 100644
--- a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.273PRB.usrpn300.conf
@@ -59,7 +59,7 @@ gNBs =
#initialULBWPmappingType
#0=typeA,1=typeB
initialDLBWPmappingType_0 = 0;
- #this is SS=2,L=3
+ #this is SS=1,L=13
initialDLBWPstartSymbolAndLength_0 = 40;
initialDLBWPk0_1 = 0;
@@ -71,6 +71,11 @@ gNBs =
initialDLBWPmappingType_2 = 0;
#this is SS=1,L=12
initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=5
+ initialDLBWPstartSymbolAndLength_3 = 57;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
@@ -105,8 +110,8 @@ gNBs =
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
-#0=oneeighth,1=onefourth,2=half,3=one,4=two,5=four,6=eight,7=sixteen
- ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 3;
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
@@ -114,8 +119,8 @@ gNBs =
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
-#0 = 839, 1 = 139
- prach_RootSequenceIndex_PR = 1;
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
@@ -237,7 +242,7 @@ RUs = (
max_pdschReferenceSignalPower = -27;
max_rxgain = 114;
eNB_instances = [0];
- sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2";
+ sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2";
clock_src = "external";
}
);
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf
new file mode 100644
index 0000000000000000000000000000000000000000..ea105d86b62abdd255804e375323f0eda99d1a14
--- /dev/null
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_enb.conf
@@ -0,0 +1,281 @@
+Active_eNBs = ( "eNB-Eurecom-LTEBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+eNBs =
+(
+ {
+ # real_time choice in {hard, rt-preempt, no}
+ real_time = "no";
+ ////////// Identification parameters:
+ eNB_ID = 0xe01;
+
+ cell_type = "CELL_MACRO_ENB";
+
+ eNB_name = "eNB-Eurecom-LTEBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+ plmn_list = (
+ { mcc = 222; mnc = 01; mnc_length = 2; }
+ );
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ component_carriers = (
+ {
+ node_function = "eNodeB_3GPP";
+ node_timing = "synch_to_ext_device";
+ node_synch_ref = 0;
+ nb_antenna_ports = 1;
+ ue_TransmissionMode = 1;
+ frame_type = "FDD";
+ tdd_config = 3;
+ tdd_config_s = 0;
+ prefix_type = "NORMAL";
+ eutra_band = 7;
+ downlink_frequency = 2680000000L; //2655000000L;
+ uplink_frequency_offset = -120000000;
+
+ Nid_cell = 0;
+ N_RB_DL = 25; //100;
+ Nid_cell_mbsfn = 0;
+ nb_antennas_tx = 1;
+ nb_antennas_rx = 1;
+ prach_root = 0;
+ tx_gain = 90;
+ rx_gain = 115;
+ pbch_repetition = "FALSE";
+ prach_config_index = 0;
+ prach_high_speed = "DISABLE";
+ prach_zero_correlation = 1;
+ prach_freq_offset = 2;
+ pucch_delta_shift = 1;
+ pucch_nRB_CQI = 0;
+ pucch_nCS_AN = 0;
+ pucch_n1_AN = 0;
+ pdsch_referenceSignalPower = -29;
+ pdsch_p_b = 0;
+ pusch_n_SB = 1;
+ pusch_enable64QAM = "DISABLE";
+ pusch_hoppingMode = "interSubFrame";
+ pusch_hoppingOffset = 0;
+ pusch_groupHoppingEnabled = "ENABLE";
+ pusch_groupAssignment = 0;
+ pusch_sequenceHoppingEnabled = "DISABLE";
+ pusch_nDMRS1 = 1;
+ phich_duration = "NORMAL";
+ phich_resource = "ONESIXTH";
+ srs_enable = "DISABLE";
+ /* srs_BandwidthConfig =;
+ srs_SubframeConfig =;
+ srs_ackNackST =;
+ srs_MaxUpPts =;*/
+
+ pusch_p0_Nominal = -96;
+ pusch_alpha = "AL1";
+ pucch_p0_Nominal = -96;
+ msg3_delta_Preamble = 6;
+ pucch_deltaF_Format1 = "deltaF2";
+ pucch_deltaF_Format1b = "deltaF3";
+ pucch_deltaF_Format2 = "deltaF0";
+ pucch_deltaF_Format2a = "deltaF0";
+ pucch_deltaF_Format2b = "deltaF0";
+
+ rach_numberOfRA_Preambles = 64;
+ rach_preamblesGroupAConfig = "DISABLE";
+/*
+ rach_sizeOfRA_PreamblesGroupA = ;
+ rach_messageSizeGroupA = ;
+ rach_messagePowerOffsetGroupB = ;
+*/
+ rach_powerRampingStep = 4;
+ rach_preambleInitialReceivedTargetPower = -108;
+ rach_preambleTransMax = 10;
+ rach_raResponseWindowSize = 10;
+ rach_macContentionResolutionTimer = 48;
+ rach_maxHARQ_Msg3Tx = 4;
+
+ pcch_default_PagingCycle = 128;
+ pcch_nB = "oneT";
+ bcch_modificationPeriodCoeff = 2;
+ ue_TimersAndConstants_t300 = 1000;
+ ue_TimersAndConstants_t301 = 1000;
+ ue_TimersAndConstants_t310 = 1000;
+ ue_TimersAndConstants_t311 = 10000;
+ ue_TimersAndConstants_n310 = 20;
+ ue_TimersAndConstants_n311 = 1;
+
+ //Parameters for SIB18
+ rxPool_sc_CP_Len = "normal";
+ rxPool_sc_Period = "sf40";
+ rxPool_data_CP_Len = "normal";
+ rxPool_ResourceConfig_prb_Num = 20;
+ rxPool_ResourceConfig_prb_Start = 5;
+ rxPool_ResourceConfig_prb_End = 44;
+ rxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ rxPool_ResourceConfig_offsetIndicator_choice = 0;
+ rxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000";
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+/* rxPool_dataHoppingConfig_hoppingParameter = 0;
+ rxPool_dataHoppingConfig_numSubbands = "ns1";
+ rxPool_dataHoppingConfig_rbOffset = 0;
+ rxPool_commTxResourceUC-ReqAllowed = "TRUE";
+*/
+ // Parameters for SIB19
+ discRxPool_cp_Len = "normal"
+ discRxPool_discPeriod = "rf32"
+ discRxPool_numRetx = 1;
+ discRxPool_numRepetition = 2;
+ discRxPool_ResourceConfig_prb_Num = 5;
+ discRxPool_ResourceConfig_prb_Start = 3;
+ discRxPool_ResourceConfig_prb_End = 21;
+ discRxPool_ResourceConfig_offsetIndicator_present = "prSmall";
+ discRxPool_ResourceConfig_offsetIndicator_choice = 0;
+ discRxPool_ResourceConfig_subframeBitmap_present = "prBs40";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff";
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
+ discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
+
+ }
+ );
+
+ srb1_parameters :
+ {
+ # timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
+ timer_poll_retransmit = 80;
+
+ # timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
+ timer_reordering = 35;
+
+ # timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
+ timer_status_prohibit = 0;
+
+ # poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
+ poll_pdu = 4;
+
+ # poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
+ poll_byte = 99999;
+
+ # max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
+ max_retx_threshold = 4;
+ }
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+ enable_measurement_reports = "yes";
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "192.168.18.99";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+
+ NETWORK_INTERFACES :
+ {
+ ENB_INTERFACE_NAME_FOR_S1_MME = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.199/24";
+
+ ENB_INTERFACE_NAME_FOR_S1U = "eth1";
+ ENB_IPV4_ADDRESS_FOR_S1U = "192.168.18.199/24";
+ ENB_PORT_FOR_S1U = 2152; # Spec 2152
+
+ ENB_IPV4_ADDRESS_FOR_X2C = "192.168.18.199/24";
+ ENB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="debug";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ phy_test_mode = 0;
+ puSch10xSnr = 160;
+ puCch10xSnr = 160;
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ parallel_config = "PARALLEL_RU_L1_TRX_SPLITaaaaaa";
+ worker_config = "ENABLE";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 118;
+ eNB_instances = [0];
+ clock_src = "external";
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="high";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="high";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="high";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
diff --git a/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf
new file mode 100644
index 0000000000000000000000000000000000000000..b63939add2be238eeee83d1d0f710a793e30ba2b
--- /dev/null
+++ b/targets/PROJECTS/GENERIC-LTE-EPC/CONF/testing_gnb.conf
@@ -0,0 +1,293 @@
+Active_gNBs = ( "gNB-Eurecom-5GNRBox");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+gNBs =
+(
+ {
+ ////////// Identification parameters:
+ gNB_ID = 0xe00;
+
+ cell_type = "CELL_MACRO_GNB";
+
+ gNB_name = "gNB-Eurecom-5GNRBox";
+
+ // Tracking area code, 0x0000 and 0xfffe are reserved values
+ tracking_area_code = 1;
+
+ plmn_list = ({mcc = 222; mnc = 01; mnc_length = 2;});
+
+ tr_s_preference = "local_mac"
+
+ ////////// Physical parameters:
+
+ ssb_SubcarrierOffset = 31; //0;
+ pdsch_AntennaPorts = 1;
+
+ servingCellConfigCommon = (
+ {
+ #spCellConfigCommon
+
+ physCellId = 0;
+
+# downlinkConfigCommon
+ #frequencyInfoDL
+ # this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP)
+ absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell
+ dl_frequencyBand = 78;
+ # this is 3600 MHz
+ dl_absoluteFrequencyPointA = 640000;
+ #scs-SpecificCarrierList
+ dl_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ dl_subcarrierSpacing = 1;
+ dl_carrierBandwidth = 106;
+ #initialDownlinkBWP
+ #genericParameters
+ # this is RBstart=84,L=13 (275*(L-1))+RBstart
+ initialDLBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialDLBWPsubcarrierSpacing = 1;
+ #pdcch-ConfigCommon
+ initialDLBWPcontrolResourceSetZero = 0;
+ initialDLBWPsearchSpaceZero = 0;
+ #pdsch-ConfigCommon
+ #pdschTimeDomainAllocationList (up to 16 entries)
+ initialDLBWPk0_0 = 0;
+ #initialULBWPmappingType
+ #0=typeA,1=typeB
+ initialDLBWPmappingType_0 = 0;
+ #this is SS=1,L=13
+ initialDLBWPstartSymbolAndLength_0 = 40;
+
+ initialDLBWPk0_1 = 0;
+ initialDLBWPmappingType_1 = 0;
+ #this is SS=2,L=12
+ initialDLBWPstartSymbolAndLength_1 = 53;
+
+ initialDLBWPk0_2 = 0;
+ initialDLBWPmappingType_2 = 0;
+ #this is SS=1,L=12
+ initialDLBWPstartSymbolAndLength_2 = 54;
+
+ initialDLBWPk0_3 = 0;
+ initialDLBWPmappingType_3 = 0;
+ #this is SS=1,L=4 //5 (4 is for 43, 5 is for 57)
+ initialDLBWPstartSymbolAndLength_3 = 57; //43; //57;
+ #uplinkConfigCommon
+ #frequencyInfoUL
+ ul_frequencyBand = 78;
+ #scs-SpecificCarrierList
+ ul_offstToCarrier = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ ul_subcarrierSpacing = 1;
+ ul_carrierBandwidth = 106;
+ pMax = 20;
+ #initialUplinkBWP
+ #genericParameters
+ initialULBWPlocationAndBandwidth = 6366; //28875; //6366; #6407; #3384;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ initialULBWPsubcarrierSpacing = 1;
+ #rach-ConfigCommon
+ #rach-ConfigGeneric
+ prach_ConfigurationIndex = 98;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+ prach_msg1_FDM = 0;
+ prach_msg1_FrequencyStart = 0;
+ zeroCorrelationZoneConfig = 13;
+ preambleReceivedTargetPower = -100;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+ preambleTransMax = 6;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+ powerRampingStep = 1;
+#ra_ReponseWindow
+#1,2,4,8,10,20,40,80
+ ra_ResponseWindow = 5;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
+#oneHalf (0..15) 4,8,12,16,...60,64
+ ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14; //15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+ ra_ContentionResolutionTimer = 7;
+ rsrp_ThresholdSSB = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+ prach_RootSequenceIndex_PR = 2;
+ prach_RootSequenceIndex = 1;
+ # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+ #
+ msg1_SubcarrierSpacing = 1,
+
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+ restrictedSetConfig = 0,
+ # pusch-ConfigCommon (up to 16 elements)
+ initialULBWPk2_0 = 2;
+ initialULBWPmappingType_0 = 1
+ # this is SS=0 L=11
+ initialULBWPstartSymbolAndLength_0 = 55;
+
+ initialULBWPk2_1 = 2;
+ initialULBWPmappingType_1 = 1;
+ # this is SS=0 L=12
+ initialULBWPstartSymbolAndLength_1 = 69;
+
+ initialULBWPk2_2 = 7;
+ initialULBWPmappingType_2 = 1;
+ # this is SS=10 L=4
+ initialULBWPstartSymbolAndLength_2 = 52;
+
+ msg3_DeltaPreamble = 1;
+ p0_NominalWithGrant =-90;
+
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+ pucchGroupHopping = 0;
+ hoppingId = 40;
+ p0_nominal = -90;
+# ssb_PositionsInBurs_BitmapPR
+# 1=short, 2=medium, 3=long
+ ssb_PositionsInBurst_PR = 2;
+ ssb_PositionsInBurst_Bitmap = 1; #0x80;
+
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+ ssb_periodicityServingCell = 2;
+
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+ dmrs_TypeA_Position = 0;
+
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ subcarrierSpacing = 1;
+
+
+ #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+ referenceSubcarrierSpacing = 1;
+ # pattern1
+ # dl_UL_TransmissionPeriodicity
+ # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+ dl_UL_TransmissionPeriodicity = 6;
+ nrofDownlinkSlots = 7; //8; //7;
+ nrofDownlinkSymbols = 6; //0; //6;
+ nrofUplinkSlots = 2;
+ nrofUplinkSymbols = 4; //0; //4;
+
+ ssPBCH_BlockPower = -25;
+ }
+
+ );
+
+
+ # ------- SCTP definitions
+ SCTP :
+ {
+ # Number of streams to use in input/output
+ SCTP_INSTREAMS = 2;
+ SCTP_OUTSTREAMS = 2;
+ };
+
+
+ ////////// MME parameters:
+ mme_ip_address = ( { ipv4 = "192.168.18.99";
+ ipv6 = "192:168:30::17";
+ active = "yes";
+ preference = "ipv4";
+ }
+ );
+
+ ///X2
+ enable_x2 = "yes";
+ t_reloc_prep = 1000; /* unit: millisecond */
+ tx2_reloc_overall = 2000; /* unit: millisecond */
+ target_enb_x2_ip_address = (
+ { ipv4 = "192.168.18.199";
+ ipv6 = "192:168:30::17";
+ preference = "ipv4";
+ }
+ );
+
+ NETWORK_INTERFACES :
+ {
+
+ GNB_INTERFACE_NAME_FOR_S1_MME = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.18.198/24";
+ GNB_INTERFACE_NAME_FOR_S1U = "eth0";
+ GNB_IPV4_ADDRESS_FOR_S1U = "192.168.18.198/24";
+ GNB_PORT_FOR_S1U = 2152; # Spec 2152
+ GNB_IPV4_ADDRESS_FOR_X2C = "192.168.18.198/24";
+ GNB_PORT_FOR_X2C = 36422; # Spec 36422
+ };
+ }
+);
+
+MACRLCs = (
+ {
+ num_cc = 1;
+ tr_s_preference = "local_L1";
+ tr_n_preference = "local_RRC";
+ }
+);
+
+L1s = (
+ {
+ num_cc = 1;
+ tr_n_preference = "local_mac";
+ }
+);
+
+RUs = (
+ {
+ local_rf = "yes"
+ nb_tx = 1
+ nb_rx = 1
+ att_tx = 0
+ att_rx = 0;
+ bands = [7];
+ max_pdschReferenceSignalPower = -27;
+ max_rxgain = 114;
+ eNB_instances = [0];
+ clock_src = "external";
+ }
+);
+
+THREAD_STRUCT = (
+ {
+ #three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
+ //parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
+ parallel_config = "PARALLEL_SINGLE_THREAD";
+ #two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
+ worker_config = "WORKER_ENABLE";
+ }
+);
+
+ log_config :
+ {
+ global_log_level ="info";
+ global_log_verbosity ="medium";
+ hw_log_level ="info";
+ hw_log_verbosity ="medium";
+ phy_log_level ="info";
+ phy_log_verbosity ="medium";
+ mac_log_level ="info";
+ mac_log_verbosity ="high";
+ rlc_log_level ="info";
+ rlc_log_verbosity ="medium";
+ pdcp_log_level ="info";
+ pdcp_log_verbosity ="medium";
+ rrc_log_level ="info";
+ rrc_log_verbosity ="medium";
+ };
+
diff --git a/targets/RT/USER/gNB_usrp.gtkw b/targets/RT/USER/gNB_usrp.gtkw
index e6726e7d9feb67e3c2f57a5b9cf38f202d8b112f..ebf3a576659c7e6b86683fda50716c40e81f0f96 100644
--- a/targets/RT/USER/gNB_usrp.gtkw
+++ b/targets/RT/USER/gNB_usrp.gtkw
@@ -1,21 +1,25 @@
[*]
[*] GTKWave Analyzer v3.3.61 (w)1999-2014 BSI
-[*] Tue Dec 17 15:31:51 2019
+[*] Wed Mar 4 14:05:43 2020
[*]
-[dumpfile] "/tmp/gNB.vcd"
-[dumpfile_mtime] "Tue Dec 17 15:25:49 2019"
-[dumpfile_size] 6343431
+[dumpfile] "/tmp/gNB_trx_thread.vcd"
+[dumpfile_mtime] "Wed Mar 4 14:05:10 2020"
+[dumpfile_size] 10750468
[savefile] "/home/wangts/openairinterface5g/targets/RT/USER/gNB_usrp.gtkw"
-[timestart] 1517712000
-[size] 1920 1018
-[pos] -9 -33
-*-19.276148 1518358451 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 31148700000
+[size] 1916 1002
+[pos] -1 -25
+*-23.852516 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 386
[signals_width] 344
[sst_expanded] 1
-[sst_vpaned_height] 267
+[sst_vpaned_height] 262
@28
functions.trx_read
+functions.trx_write_thread
+@25
+variables.trx_write_flags[63:0]
+@28
functions.trx_write
@420
variables.frame_number_TX0_UE[63:0]
@@ -28,43 +32,50 @@ variables.frame_number_RX1_UE[63:0]
variables.trx_ts_ue[63:0]
variables.trx_ts[63:0]
variables.trx_tst[63:0]
+@22
+variables.frame_number_RX0_UE[63:0]
+@420
+variables.frame_number_RX0_UE[63:0]
+@24
variables.frame_number_RX0_RU[63:0]
variables.tti_number_RX0_RU[63:0]
-variables.frame_number_TX0_RU[63:0]
-variables.tti_number_TX0_RU[63:0]
-@28
-functions.mac_schedule_dlsch
-functions.macxface_eNB_dlsch_ulsch_scheduler
-@24
variables.frame_number_RX0_gNB[63:0]
variables.slot_number_RX0_gNB[63:0]
-variables.frame_number_TX0_gNB[63:0]
-variables.slot_number_TX0_gNB[63:0]
+variables.slot_number_RX1_gNB[63:0]
+variables.frame_number_RX1_gNB[63:0]
@28
-functions.gNB_thread_rxtx0
+functions.phy_procedures_ru_feprx0
+functions.phy_procedures_ru_feprx1
+functions.phy_procedures_gNB_uespec_rx
+functions.nr_rx_pusch
+functions.nr_ulsch_procedures_rx
+functions.gNB_ulsch_decoding
@24
-variables.frame_number_RX1_gNB[63:0]
-variables.slot_number_RX1_gNB[63:0]
+variables.frame_number_TX0_RU[63:0]
+variables.frame_number_TX0_gNB[63:0]
variables.frame_number_TX1_gNB[63:0]
+variables.tti_number_TX0_RU[63:0]
+variables.slot_number_TX0_gNB[63:0]
variables.slot_number_TX1_gNB[63:0]
+@29
+functions.mac_schedule_dlsch
@28
+functions.macxface_gNB_dlsch_ulsch_scheduler
+functions.gNB_thread_rxtx0
functions.gNB_thread_rxtx1
-functions.phy_enb_pdcch_tx
-functions.phy_eNB_dlsch_encoding
-functions.phy_eNB_dlsch_encoding_w
functions.generate_dlsch
-@420
-variables.frame_number_RX0_UE[63:0]
-@28
-functions.phy_procedures_ru_feprx0
-functions.phy_procedures_ru_feprx1
+functions.phy_procedures_gNB_common_tx
+functions.phy_procedures_gNB_tx
+functions.gNB_pdcch_tx
+functions.gNB_dlsch_encoding
+functions.gNB_pdsch_codeword_scrambling
+functions.gNB_pdsch_modulation
functions.phy_procedures_ru_feptx_ofdm0
functions.phy_procedures_ru_feptx_ofdm1
functions.phy_procedures_ru_feptx_ofdm2
functions.phy_procedures_ru_feptx_prec0
functions.phy_procedures_ru_feptx_prec1
functions.phy_procedures_ru_feptx_prec2
-@22
variables.ru_tx_ofdm_mask[63:0]
[pattern_trace] 1
[pattern_trace] 0
diff --git a/targets/RT/USER/lte-enb.c b/targets/RT/USER/lte-enb.c
index cb04480d3321c1080299ecd7aaaaa4069ced9151..147bc955aeb2d0c80f5f30fe23e2fb1a701d9512 100644
--- a/targets/RT/USER/lte-enb.c
+++ b/targets/RT/USER/lte-enb.c
@@ -851,9 +851,7 @@ void init_eNB_proc(int inst) {
for (CC_id=0; CC_id<RC.nb_CC[inst]; CC_id++) {
eNB = RC.eNB[inst][CC_id];
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing eNB processes instance:%d CC_id %d \n",inst,CC_id);
-#endif
proc = &eNB->proc;
L1_proc = &proc->L1_proc;
L1_proc_tx = &proc->L1_proc_tx;
@@ -1247,9 +1245,7 @@ void init_eNB(int single_thread_flag,
eNB->abstraction_flag = 0;
eNB->single_thread_flag = single_thread_flag;
LOG_I(PHY,"Initializing eNB %d CC_id %d single_thread_flag:%d\n",inst,CC_id,single_thread_flag);
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing eNB %d CC_id %d\n",inst,CC_id);
-#endif
LOG_I(PHY,"Registering with MAC interface module\n");
AssertFatal((eNB->if_inst = IF_Module_init(inst))!=NULL,"Cannot register interface");
eNB->if_inst->schedule_response = schedule_response;
diff --git a/targets/RT/USER/lte-ru.c b/targets/RT/USER/lte-ru.c
index 8c9b143100ef19c0e9a58c9104659a2ff9ca5d43..4d890200770a33f8f7bb88d59cd1be1d7ded2a90 100644
--- a/targets/RT/USER/lte-ru.c
+++ b/targets/RT/USER/lte-ru.c
@@ -679,7 +679,11 @@ void rx_rf(RU_t *ru,
resynch=1;
}
- proc->timestamp_rx = ts-ru->ts_offset;
+ if(get_softmodem_params()->emulate_rf) {
+ proc->timestamp_rx = old_ts + fp->samples_per_tti;
+ } else {
+ proc->timestamp_rx = ts-ru->ts_offset;
+ }
// AssertFatal(rxs == fp->samples_per_tti,
// "rx_rf: Asked for %d samples, got %d from SDR\n",fp->samples_per_tti,rxs);
@@ -2233,9 +2237,7 @@ void init_RU_proc(RU_t *ru) {
RU_proc_t *proc;
pthread_attr_t *attr_FH=NULL, *attr_FH1=NULL, *attr_prach=NULL, *attr_asynch=NULL, *attr_synch=NULL, *attr_emulateRF=NULL, *attr_ctrl=NULL, *attr_prach_br=NULL;
//pthread_attr_t *attr_fep=NULL;
-#ifndef OCP_FRAMEWORK
LOG_I(PHY,"Initializing RU proc %d (%s,%s),\n",ru->idx,NB_functions[ru->function],NB_timing[ru->if_timing]);
-#endif
proc = &ru->proc;
memset((void *)proc,0,sizeof(RU_proc_t));
proc->ru = ru;
@@ -2339,19 +2341,22 @@ void init_RU_proc(RU_t *ru) {
LOG_I(PHY,"%s() DJP - added creation of pthread_prach\n", __FUNCTION__);
pthread_create( &proc->pthread_prach, attr_prach, ru_thread_prach, (void *)ru );
ru->state=RU_RUN;
- fill_rf_config(ru,ru->rf_config_file);
- init_frame_parms(ru->frame_parms,1);
- ru->frame_parms->nb_antennas_rx = ru->nb_rx;
- phy_init_RU(ru);
- ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg);
- if (ret < 0) {
- LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n");
- exit(1);
- }
+ if(!get_softmodem_params()->emulate_rf)
+ {
+ fill_rf_config(ru,ru->rf_config_file);
+ init_frame_parms(ru->frame_parms,1);
+ ru->frame_parms->nb_antennas_rx = ru->nb_rx;
+ phy_init_RU(ru);
+ ret = openair0_device_load(&ru->rfdevice,&ru->openair0_cfg);
+ if (ret < 0) {
+ LOG_I(PHY,"Exiting, cannot load device. Make sure that your SDR board is connected!\n");
+ exit(1);
+ }
- if (setup_RU_buffers(ru)!=0) {
- LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n");
- exit(1);
+ if (setup_RU_buffers(ru)!=0) {
+ LOG_I(PHY,"Exiting, cannot initialize RU Buffers\n");
+ exit(1);
+ }
}
}
diff --git a/targets/RT/USER/lte-softmodem.c b/targets/RT/USER/lte-softmodem.c
index d8c5e25593915c3a328384fc8a1734cd659b20c3..0d0dde4ac47a322cb436485326f5c911fa32bc90 100644
--- a/targets/RT/USER/lte-softmodem.c
+++ b/targets/RT/USER/lte-softmodem.c
@@ -170,6 +170,7 @@ extern void init_eNB_afterRU(void);
int transmission_mode=1;
int emulate_rf = 0;
int numerology = 0;
+int usrp_tx_thread = 0;
THREAD_STRUCT thread_struct;
/* struct for ethernet specific parameters given in eNB conf file */
@@ -437,9 +438,6 @@ int restart_L1L2(module_id_t enb_id) {
}
RC.ru_mask |= (1 << ru->idx);
- /* copy the changed frame parameters to the RU */
- /* TODO this should be done for all RUs associated to this eNB */
- memcpy(&ru->frame_parms, &RC.eNB[enb_id][0]->frame_parms, sizeof(LTE_DL_FRAME_PARMS));
set_function_spec_param(RC.ru[enb_id]);
/* reset the list of connected UEs in the MAC, since in this process with
* loose all UEs (have to reconnect) */
@@ -555,6 +553,8 @@ int main ( int argc, char **argv )
MSC_INIT(MSC_E_UTRAN, THREAD_MAX+TASK_MAX);
init_opt();
+ // to make a graceful exit when ctrl-c is pressed
+ set_softmodem_sighandler();
check_clock();
#ifndef PACKAGE_VERSION
# define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL"
@@ -659,6 +659,7 @@ int main ( int argc, char **argv )
initTpool("n", L1proc->threadPool, true);
initNotifiedFIFO(L1proc->respEncode);
initNotifiedFIFO(L1proc->respDecode);
+ RC.eNB[x][CC_id]->proc.L1_proc_tx.threadPool = L1proc->threadPool;
}
@@ -711,9 +712,12 @@ int main ( int argc, char **argv )
sync_var=0;
pthread_cond_broadcast(&sync_cond);
pthread_mutex_unlock(&sync_mutex);
+ create_tasks_mbms(1);
config_check_unknown_cmdlineopt(CONFIG_CHECKALLSECTIONS);
}
- create_tasks_mbms(1);
+ else
+ create_tasks_mbms(1);
+ //create_tasks_mbms(1);
// wait for end of program
LOG_UI(ENB_APP,"TYPE <CTRL-C> TO TERMINATE\n");
@@ -723,7 +727,7 @@ int main ( int argc, char **argv )
// end of CI modifications
//getchar();
if(IS_SOFTMODEM_DOFORMS)
- load_softscope("enb");
+ load_softscope("enb",NULL);
itti_wait_tasks_end();
oai_exit=1;
LOG_I(ENB_APP,"oai_exit=%d\n",oai_exit);
diff --git a/targets/RT/USER/lte-softmodem.h b/targets/RT/USER/lte-softmodem.h
index c5fdb5f5468cbebb2d8474f9dcbaf4d41047abb5..1c537dabe39d5cdb4f79f5469f2bd550321563f3 100644
--- a/targets/RT/USER/lte-softmodem.h
+++ b/targets/RT/USER/lte-softmodem.h
@@ -155,6 +155,10 @@ extern int sync_var;
extern int transmission_mode;
extern double cpuf;
+extern int emulate_rf;
+extern int numerology;
+extern int usrp_tx_thread;
+
// In lte-enb.c
extern void stop_eNB(int);
extern void kill_eNB_proc(int inst);
diff --git a/targets/RT/USER/lte-uesoftmodem.c b/targets/RT/USER/lte-uesoftmodem.c
index 2c9271888bd9fd11d6a64b269709e1effd89519e..54a9f4a669e7fb8087d1acca604348d46442aa82 100644
--- a/targets/RT/USER/lte-uesoftmodem.c
+++ b/targets/RT/USER/lte-uesoftmodem.c
@@ -171,6 +171,8 @@ extern void get_uethreads_params(void);
int transmission_mode=1;
+int usrp_tx_thread = 0;
+
char *usrp_args=NULL;
char *usrp_clksrc=NULL;
@@ -757,7 +759,7 @@ int main( int argc, char **argv ) {
}
if(IS_SOFTMODEM_DOFORMS)
- load_softscope("ue");
+ load_softscope("ue",NULL);
config_check_unknown_cmdlineopt(CONFIG_CHECKALLSECTIONS);
printf("Sending sync to all threads (%p,%p,%p)\n",&sync_var,&sync_cond,&sync_mutex);