Commit c8fbd905 authored by Calvin HSU's avatar Calvin HSU
Browse files

UE: Add frequency domain resource in type0-pdcch and new field rb_offset

parent 31caae03
...@@ -115,8 +115,10 @@ typedef struct { ...@@ -115,8 +115,10 @@ typedef struct {
typedef struct { typedef struct {
/// frequency_domain_resource; /// frequency_domain_resource;
uint32_t rb_start; //uint32_t rb_start;
uint32_t rb_end; //uint32_t rb_end;
uint64_t frequency_domain_resource;
uint16_t rb_offset;
uint8_t duration; uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
......
...@@ -774,7 +774,7 @@ typedef struct { ...@@ -774,7 +774,7 @@ typedef struct {
int tciStatesPDCCH; int tciStatesPDCCH;
int tciPresentInDCI; int tciPresentInDCI;
uint16_t pdcchDMRSScramblingID; uint16_t pdcchDMRSScramblingID;
uint16_t rb_offset;
} NR_UE_PDCCH_CORESET; } NR_UE_PDCCH_CORESET;
// Slots for PDCCH Monitoring configured as periodicity and offset // Slots for PDCCH Monitoring configured as periodicity and offset
......
...@@ -68,16 +68,18 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ...@@ -68,16 +68,18 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config->number_of_candidates[4]; pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config->number_of_candidates[4];
pdcch_vars2->coreset[i].duration = dci_config->coreset.duration; pdcch_vars2->coreset[i].duration = dci_config->coreset.duration;
//pdcch_vars2->coreset[i].frequencyDomainResources;
//dci_config.coreset.rb_start; pdcch_vars2->coreset[i].frequencyDomainResources = dci_config.coreset.frequency_domain_resource;
//dci_config.coreset.rb_end; pdcch_vars2->coreset[i].rb_offset = dci_config.coreset.rb_offset;
if(dci_config->coreset.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){ if(dci_config->coreset.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){
pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = dci_config->coreset.cce_reg_interleaved_shift_index; pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = dci_config->coreset.cce_reg_interleaved_shift_index;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = dci_config->coreset.cce_reg_interleaved_reg_bundle_size; pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = dci_config->coreset.cce_reg_interleaved_reg_bundle_size;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size; pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size;
}else{ }else{ //CCE_REG_MAPPING_TYPE_NON_INTERLEAVED
; pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 0;
} }
pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity; pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity;
......
...@@ -236,8 +236,17 @@ int8_t nr_ue_decode_mib( ...@@ -236,8 +236,17 @@ int8_t nr_ue_decode_mib(
//uint32_t cell_id = 0; // obtain from L1 later //uint32_t cell_id = 0; // obtain from L1 later
mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset; //mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset;
mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1; //mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1;
uint64_t mask = 0x0;
uint8_t i;
for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
mask = mask >> 1;
mask = mask | 0x100000000000;
}
mac->type0_pdcch_dci_config.coreset.frequency_domain_resource = mask;
mac->type0_pdcch_dci_config.coreset.rb_offset = rb_offset; // additional parameter other than coreset
//mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols; //mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols;
mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED; mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED;
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2 mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2
......
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