Merge branch 'ocp_nrsimulator' into 'develop-nr'

Critical bugs from compilation, Ocp nrsimulator

See merge request !512

cmake_targets/build_oai

@@ -43,10 +43,10 @@ conf_nvram_path=$OPENAIR_DIR/openair3/NAS/TOOLS/ue_eurecom_test_sfr.conf
 MSC_GEN=0
 XFORMS="True"
 UE_EXPANSION="False"
+UESIM_EXPANSION="False"
 PRINT_STATS="False"
 VCD_TIMING="False"
-DEADLINE_SCHEDULER_FLAG_USER="False"
-FORCE_DEADLINE_SCHEDULER_FLAG_USER=""
+DEADLINE_SCHEDULER_FLAG_USER=""
 CPU_AFFINITY_FLAG_USER="False" #Only valid when lowlatecy flag is set to False
 REL="Rel15"
 NR_REL="NR_Rel15"
@@ -78,7 +78,7 @@ trap handle_ctrl_c INT
 function print_help() {
   echo_info "
 This program installs OpenAirInterface Software
-You should have ubuntu 14.xx, updated, and the Linux kernel >= 3.14
+You should have ubuntu 16.xx or 18.04 updated
 Options
 -h
    This help
@@ -116,7 +116,7 @@ Options
    Rel8 limits the implementation to 3GPP Release 8 version
    Rel10 limits the implementation to 3GPP Release 10 version
 -w | --hardware
-   EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, ADRV9371_ZC706, None (Default)
+   EXMIMO, USRP, BLADERF, ETHERNET, LMSSDR, ADRV9371_ZC706, SIMU, None (Default)
    Adds this RF board support (in external packages installation and in compilation)
 -t | --transport protocol
    ETHERNET , None
@@ -175,6 +175,9 @@ Options
 --basic-simulator
    Generates a basic [1 UE + 1 eNB + no channel] simulator.
    See targets/ARCH/tcp_bridge/README.tcp_bridge_oai for documentation.
+--rfsimulator
+   Generate virtual RF driver
+   to use it, set the environement variable RFSIMULATOR to \"enb\" in the eNB and to the eNB IP address in the UEs
 Usage (first build):
  NI/ETTUS B201  + COTS UE : ./build_oai -I  --eNB -x --install-system-files -w USRP
 Usage (Regular):
@@ -250,7 +253,7 @@ function main() {
        -w | --hardware)
             HW="$2" #"${i#*=}"
             # Use OAI_USRP  as the key word USRP is used inside UHD driver
-	    if [ "$HW" != "BLADERF" -a  "$HW" != "USRP" -a "$HW" != "LMSSDR" -a  "$HW" != "None" -a  "$HW" != "EXMIMO" -a  "$HW" != "ADRV9371_ZC706"  ] ; then 
+	    if [ "$HW" != "BLADERF" -a  "$HW" != "USRP" -a "$HW" != "LMSSDR" -a  "$HW" != "None" -a  "$HW" != "EXMIMO" -a  "$HW" != "ADRV9371_ZC706"  -a  "$HW" != "SIMU" ] ; then 
 		echo_fatal "Unknown HW type $HW will exit..."		
 	    else
 		if [ "$HW" == "USRP" ] ; then 
@@ -265,6 +268,9 @@ function main() {
 		if [ "$HW" == "LMSSDR" ] ; then 
 		    HW="OAI_LMSSDR"
 		fi 
+		if [ "$HW" == "SIMU" ] ; then
+                    HW="OAI_SIMU"
+                fi
 		echo_info "Setting hardware to: $HW"
 	    fi
             shift 2;;
@@ -331,13 +337,13 @@ function main() {
 	    BUILD_DOXYGEN=1
             echo_info "Will build doxygen support"
             shift;;     
-       --disable-deadline)
-            FORCE_DEADLINE_SCHEDULER_FLAG_USER="False"
-            echo_info "Disabling the usage of deadline scheduler"
-            shift 1;;
-       --enable-deadline)
-            FORCE_DEADLINE_SCHEDULER_FLAG_USER="True"
-            echo_info "Enabling the usage of deadline scheduler"
+            --disable-deadline)
+                DEADLINE_SCHEDULER_FLAG_USER="False"
+                echo_info "Disabling the usage of deadline scheduler"
+                shift 1;;
+            --enable-deadline)
+                DEADLINE_SCHEDULER_FLAG_USER="True"
+                echo_info "Enabling the usage of deadline scheduler"
             shift 1;;
        --enable-cpu-affinity)
             CPU_AFFINITY_FLAG_USER="True"
@@ -400,7 +406,11 @@ function main() {
             BASIC_SIMULATOR=1
             echo_info "Compiling the basic simulator"
             shift 1;;
-        -h | --help)
+            --rfsimulator)
+                RFSIMULATOR=true
+                echo_info "Compiling the RF simulator"
+                shift 1;;
+            -h | --help)
             print_help
             exit 1;;
 	*)
@@ -441,33 +451,18 @@ function main() {
       fi
   fi
 
-  echo_info "RF HW set to $HW" 
-  #Now we set flags to enable deadline scheduler settings
-  #By default: USRP: disable, 
-  #By default: BLADERF: enable,
-  #By default: EXMIMO: enable
-  if [ "$FORCE_DEADLINE_SCHEDULER_FLAG_USER" = "" ]; then
-     if [ "$HW" = "EXMIMO" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="True"
-     elif [ "$HW" = "ETHERNET" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     elif [ "$HW" = "OAI_USRP" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     elif [ "$HW" = "OAI_ADRV9371_ZC706" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     elif [ "$HW" = "OAI_BLADERF" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     elif [ "$HW" = "OAI_LMSSDR" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     elif [ "$HW" = "None" ] ; then 
-        DEADLINE_SCHEDULER_FLAG_USER="False"
-     else 
-        echo_error "Unknown HW type $HW. Exiting now..."
-        exit 
-     fi
-  else
-     DEADLINE_SCHEDULER_FLAG_USER=$FORCE_DEADLINE_SCHEDULER_FLAG_USER
-  fi
+    echo_info "RF HW set to $HW" 
+    # If the user doesn't specify the Linux scheduler to use, we set a value
+    if [ "$DEADLINE_SCHEDULER_FLAG_USER" = "" ]; then
+	case "$HW" in
+            "EXMIMO")
+		DEADLINE_SCHEDULER_FLAG_USER="True"
+		;;
+            *)
+		DEADLINE_SCHEDULER_FLAG_USER="False"
+		;;
+	esac
+    fi
 
   #Disable CPU Affinity for deadline scheduler
   if [ "$DEADLINE_SCHEDULER_FLAG_USER" = "True" ] ; then 

cmake_targets/tools/make_asn1c_includes.sh

+#!/bin/bash
+GENERATED_FULL_DIR=$1
+shift
+ASN1_SOURCE_DIR=$1
+shift
+export ASN1C_PREFIX=$1 
+shift
+options=$*
+done_flag="$GENERATED_FULL_DIR"/done
+if [ "$done_flag" -ot $ASN1_SOURCE_DIR ] ; then 
+   rm -f "$GENERATED_FULL_DIR"/${ASN1C_PREFIX}*.c "$GENERATED_FULL_DIR"/${ASN1C_PREFIX}*.h
+   mkdir -p "$GENERATED_FULL_DIR"
+   asn1c -pdu=all -fcompound-names -gen-PER -no-gen-OER -no-gen-example $options -D $GENERATED_FULL_DIR $ASN1_SOURCE_DIR |& egrep -v "^Copied|^Compiled" | sort -u
+fi
+touch $done_flag

common/utils/backtrace.h

@@ -23,9 +23,16 @@
 
 #ifndef BACKTRACE_H_
 #define BACKTRACE_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 void display_backtrace(void);
 
 void backtrace_handle_signal(siginfo_t *info);
+#ifdef __cplusplus
+}
+#endif
+
 
 #endif /* BACKTRACE_H_ */

openair1/PHY/INIT/nr_init_ue.c

@@ -919,7 +919,7 @@ void init_nr_ue_transport(PHY_VARS_NR_UE *ue,int abstraction_flag) {
 
   for (i=0; i<NUMBER_OF_CONNECTED_eNB_MAX; i++) {
     for (j=0; j<2; j++) {
-      for (k=0; k<2; k++) {
+      for (k=0; k<RX_NB_TH_MAX; k++) {
 	AssertFatal((ue->dlsch[k][i][j]  = new_nr_ue_dlsch(1,NUMBER_OF_HARQ_PID_MAX,NSOFT,MAX_LDPC_ITERATIONS,ue->frame_parms.N_RB_DL, abstraction_flag))!=NULL,"Can't get ue dlsch structures\n");
 
 	LOG_D(PHY,"dlsch[%d][%d][%d] => %p\n",k,i,j,ue->dlsch[i][j]);

openair1/PHY/NR_UE_TRANSPORT/dci_nr.c

@@ -421,6 +421,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
 #ifdef NR_PDCCH_DCI_DEBUG
       printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_extract_rbs_single)-> c_rb=%d\n",c_rb);
 #endif
+      rxF=NULL;
       // first we set initial conditions for pointer to rxdataF depending on the situation of the first RB within the CORESET (c_rb = n_BWP_start)
       if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) {
         //if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): even case

openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c

@@ -516,7 +516,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
                            p_nrLDPC_procBuf[r],
                            p_procTime);
 
-		if (check_crc(llrProcBuf,harq_process->B,harq_process->F,crc_type)) {
+		// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
+		if (check_crc((uint8_t*)llrProcBuf,harq_process->B,harq_process->F,crc_type)) {
 		  printf("CRC OK\n");
 		  ret = 2;
 		}

openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c

@@ -1350,7 +1350,7 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext,
   unsigned char aatx,aarx,pilots=0;
   __m128i *dl_ch128,*dl_ch128_2,*dl_ch_mag128,*dl_ch_mag128b,*rxdataF128,*rxdataF_comp128,*rho128;
   __m128i mmtmpD0,mmtmpD1,mmtmpD2,mmtmpD3,QAM_amp128,QAM_amp128b;
-
+  QAM_amp128b = _mm_setzero_si128();
 
   if (symbol == 2){
       pilots=1;

openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c

@@ -266,123 +266,33 @@ void nr_pbch_channel_compensation(int **rxdataF_ext,
 				  int **rxdataF_comp,
 				  NR_DL_FRAME_PARMS *frame_parms,
 				  uint32_t symbol,
-				  uint8_t output_shift)
-{
-
-  short conjugate[8]__attribute__((aligned(16))) = {-1,1,-1,1,-1,1,-1,1};
-  //short conjugate2[8]__attribute__((aligned(16))) = {1,-1,1,-1,1,-1,1,-1};
-#if defined(__x86_64__) || defined(__i386__)
-  __m128i mmtmpP0,mmtmpP1,mmtmpP2,mmtmpP3;
-#elif defined(__arm__)
-  int16x8_t mmtmpP0,mmtmpP1,mmtmpP2,mmtmpP3;
-#endif
-
-  uint16_t nb_re=180;
-  uint8_t aarx;
-
-#if defined(__x86_64__) || defined(__i386__)
-  __m128i *dl_ch128,*rxdataF128,*rxdataF_comp128;
-#elif defined(__arm__)
-
-#endif
+				  uint8_t output_shift) {
 
+  const uint16_t nb_re=symbol == 2 ? 72 : 180;
+    
   AssertFatal((symbol > 0 && symbol < 4),
 	      "symbol %d is illegal for PBCH DM-RS\n",
 	      symbol);
-
-  if (symbol == 2) nb_re = 72;
-
+  
   //  printf("comp: symbol %d : nb_re %d\n",symbol,nb_re);
 
-  for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
+  for (int aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
     
-#if defined(__x86_64__) || defined(__i386__)
-    dl_ch128          = (__m128i *)&dl_ch_estimates_ext[aarx][symbol*20*12];
-    rxdataF128        = (__m128i *)&rxdataF_ext[aarx][symbol*20*12];
-    rxdataF_comp128   = (__m128i *)&rxdataF_comp[aarx][symbol*20*12];
+    vect128 *dl_ch128          = (vect128 *)&dl_ch_estimates_ext[aarx][symbol*20*12];
+    vect128 *rxdataF128        = (vect128 *)&rxdataF_ext[aarx][symbol*20*12];
+    vect128 *rxdataF_comp128   = (vect128 *)&rxdataF_comp[aarx][symbol*20*12];
     /*
     printf("ch compensation dl_ch ext addr %p \n", &dl_ch_estimates_ext[aarx][symbol*20*12]);
     printf("rxdataf ext addr %p symbol %d\n", &rxdataF_ext[aarx][symbol*20*12], symbol);
     printf("rxdataf_comp addr %p\n",&rxdataF_comp[aarx][symbol*20*12]); 
     */
-#elif defined(__arm__)
-// to be filled in
-#endif
 
     for (int re=0; re<nb_re; re+=12) {
-      //            printf("******re %d\n",re);
-#if defined(__x86_64__) || defined(__i386__)
-      // multiply by conjugated channel
-      mmtmpP0 = _mm_madd_epi16(dl_ch128[0],rxdataF128[0]);
-      //  print_ints("re",&mmtmpP0);
-      // mmtmpP0 contains real part of 4 consecutive outputs (32-bit)
-      mmtmpP1 = _mm_shufflelo_epi16(dl_ch128[0],_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_shufflehi_epi16(mmtmpP1,_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_sign_epi16(mmtmpP1,*(__m128i*)&conjugate[0]);
-      //  print_ints("im",&mmtmpP1);
-      mmtmpP1 = _mm_madd_epi16(mmtmpP1,rxdataF128[0]);
-      // mmtmpP1 contains imag part of 4 consecutive outputs (32-bit)
-      mmtmpP0 = _mm_srai_epi32(mmtmpP0,output_shift);
-      //  print_ints("re(shift)",&mmtmpP0);
-      mmtmpP1 = _mm_srai_epi32(mmtmpP1,output_shift);
-      //  print_ints("im(shift)",&mmtmpP1);
-      mmtmpP2 = _mm_unpacklo_epi32(mmtmpP0,mmtmpP1);
-      mmtmpP3 = _mm_unpackhi_epi32(mmtmpP0,mmtmpP1);
-      //      print_ints("c0",&mmtmpP2);
-      //  print_ints("c1",&mmtmpP3);
-      rxdataF_comp128[0] = _mm_packs_epi32(mmtmpP2,mmtmpP3);
-      /*
-        print_shorts("rx:",rxdataF128);
-        print_shorts("ch:",dl_ch128);
-        print_shorts("pack:",rxdataF_comp128);
-      */
-      // multiply by conjugated channel
-      mmtmpP0 = _mm_madd_epi16(dl_ch128[1],rxdataF128[1]);
-      // mmtmpP0 contains real part of 4 consecutive outputs (32-bit)
-      mmtmpP1 = _mm_shufflelo_epi16(dl_ch128[1],_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_shufflehi_epi16(mmtmpP1,_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_sign_epi16(mmtmpP1,*(__m128i*)&conjugate[0]);
-      mmtmpP1 = _mm_madd_epi16(mmtmpP1,rxdataF128[1]);
-      // mmtmpP1 contains imag part of 4 consecutive outputs (32-bit)
-      mmtmpP0 = _mm_srai_epi32(mmtmpP0,output_shift);
-      mmtmpP1 = _mm_srai_epi32(mmtmpP1,output_shift);
-      mmtmpP2 = _mm_unpacklo_epi32(mmtmpP0,mmtmpP1);
-      mmtmpP3 = _mm_unpackhi_epi32(mmtmpP0,mmtmpP1);
-      rxdataF_comp128[1] = _mm_packs_epi32(mmtmpP2,mmtmpP3);
-      //  print_shorts("rx:",rxdataF128+1);
-      //  print_shorts("ch:",dl_ch128+1);
-      //  print_shorts("pack:",rxdataF_comp128+1);
-      
-      // multiply by conjugated channel
-      mmtmpP0 = _mm_madd_epi16(dl_ch128[2],rxdataF128[2]);
-      // mmtmpP0 contains real part of 4 consecutive outputs (32-bit)
-      mmtmpP1 = _mm_shufflelo_epi16(dl_ch128[2],_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_shufflehi_epi16(mmtmpP1,_MM_SHUFFLE(2,3,0,1));
-      mmtmpP1 = _mm_sign_epi16(mmtmpP1,*(__m128i*)&conjugate[0]);
-      mmtmpP1 = _mm_madd_epi16(mmtmpP1,rxdataF128[2]);
-      // mmtmpP1 contains imag part of 4 consecutive outputs (32-bit)
-      mmtmpP0 = _mm_srai_epi32(mmtmpP0,output_shift);
-      mmtmpP1 = _mm_srai_epi32(mmtmpP1,output_shift);
-      mmtmpP2 = _mm_unpacklo_epi32(mmtmpP0,mmtmpP1);
-      mmtmpP3 = _mm_unpackhi_epi32(mmtmpP0,mmtmpP1);
-      rxdataF_comp128[2] = _mm_packs_epi32(mmtmpP2,mmtmpP3);
-      //  print_shorts("rx:",rxdataF128+2);
-      //  print_shorts("ch:",dl_ch128+2);
-      //      print_shorts("pack:",rxdataF_comp128+2);
-      
-      dl_ch128+=3;
-      rxdataF128+=3;
-      rxdataF_comp128+=3;
-      
-#elif defined(__arm__)
-      // to be filled in
-#endif
+      *rxdataF_comp128++ = mulByConjugate128(rxdataF128++, dl_ch128++, output_shift);
+      *rxdataF_comp128++ = mulByConjugate128(rxdataF128++, dl_ch128++, output_shift);
+      *rxdataF_comp128++ = mulByConjugate128(rxdataF128++, dl_ch128++, output_shift);
     }
   }
-#if defined(__x86_64__) || defined(__i386__)
-  _mm_empty();
-  _m_empty();
-#endif
 }
 
 void nr_pbch_detection_mrc(NR_DL_FRAME_PARMS *frame_parms,

openair1/PHY/NR_UE_TRANSPORT/nr_prach.c

@@ -577,7 +577,7 @@ int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe,
   uint8_t preamble_index     = ue->prach_resources[eNB_id]->ra_PreambleIndex;
   //uint8_t tdd_mapindex       = ue->prach_resources[eNB_id]->ra_TDD_map_index;
   int16_t *prachF           = ue->prach_vars[eNB_id]->prachF;
-  static int16_t prach_tmp[45600*2] __attribute__((aligned(32)));
+  static int16_t prach_tmp[45600*4] __attribute__((aligned(32)));
   int16_t *prach            = prach_tmp;
   int16_t *prach2;
   int16_t amp               = ue->prach_vars[eNB_id]->amp;

openair1/PHY/NR_UE_TRANSPORT/pucch_nr.h

@@ -116,7 +116,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
    * Where base sequence r_u_v(n)=exp[j*phi(n)*pi/4] 0<=n<=M_ZC-1 and M_ZC={6,12,18,24}
    * For M_ZC=30, base sequence r_u_v(n)=exp[-j((pi*[u+1]*[n+1]*[n+2])/31)]
    */
-  int16_t table_5_2_2_2_1_Re[30][6]={ // Table 5.2.2.2-1 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=6)
+  static const int16_t table_5_2_2_2_1_Re[30][6]={ // Table 5.2.2.2-1 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=6)
   {-23170, 23170,-23170,-23170, 23170,-23170},
   {-23170,-23170, 23170, 23170,-23170,-23170},
   {-23170,-23170,-23170,-23170, 23170,-23170},
@@ -148,7 +148,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   { 23170, 23170, 23170,-23170,-23170, 23170},
   { 23170, 23170,-23170, 23170, 23170, 23170}
   };
-  int16_t table_5_2_2_2_1_Im[30][6]={ // Table 5.2.2.2-1 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=6)
+  static const int16_t table_5_2_2_2_1_Im[30][6]={ // Table 5.2.2.2-1 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=6)
   {-23170,-23170, 23170, 23170,-23170,-23170},
   {-23170, 23170,-23170,-23170, 23170,-23170},
   {-23170,-23170,-23170, 23170, 23170,-23170},
@@ -180,7 +180,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   { 23170, 23170,-23170, 23170,-23170,-23170},
   { 23170, 23170,-23170, 23170,-23170,-23170}
   };
-  int16_t table_5_2_2_2_2_Re[30][12]={ // Table 5.2.2.2-2 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=12)
+  static const int16_t table_5_2_2_2_2_Re[30][12]={ // Table 5.2.2.2-2 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=12)
   {-23170, 23170,-23170,-23170,-23170,-23170,-23170, 23170, 23170, 23170, 23170,-23170},
   {-23170,-23170, 23170,-23170, 23170,-23170, 23170, 23170, 23170,-23170,-23170,-23170},
   {-23170,-23170,-23170, 23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170},
@@ -212,7 +212,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   { 23170, 23170,-23170, 23170, 23170, 23170, 23170, 23170, 23170,-23170,-23170, 23170},
   {-23170,-23170,-23170,-23170,-23170,-23170,-23170, 23170, 23170, 23170,-23170,-23170}
   };
-  int16_t table_5_2_2_2_2_Im[30][12]={  // Table 5.2.2.2-2 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=12)
+  static const int16_t table_5_2_2_2_2_Im[30][12]={  // Table 5.2.2.2-2 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=12)
   {-23170, 23170,-23170,-23170,-23170, 23170,-23170,-23170, 23170, 23170, 23170,-23170},
   {-23170, 23170, 23170,-23170, 23170, 23170,-23170,-23170, 23170, 23170, 23170, 23170},
   {-23170, 23170, 23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170, 23170,-23170},
@@ -244,7 +244,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   { 23170,-23170, 23170, 23170, 23170,-23170,-23170,-23170, 23170, 23170,-23170, 23170},
   {-23170, 23170,-23170, 23170,-23170,-23170, 23170,-23170,-23170, 23170, 23170,-23170}
   };
-  int16_t table_5_2_2_2_3_Re[30][18]={ // Table 5.2.2.2-3 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=18)
+  static const int16_t table_5_2_2_2_3_Re[30][18]={ // Table 5.2.2.2-3 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=18)
   { 23170,-23170, 23170,-23170,-23170, 23170,-23170, 23170,-23170,-23170, 23170, 23170, 23170, 23170, 23170, 23170, 23170, 23170},
   {-23170,-23170,-23170, 23170, 23170,-23170,-23170, 23170,-23170,-23170, 23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170},
   {-23170,-23170, 23170, 23170, 23170,-23170,-23170, 23170, 23170, 23170, 23170, 23170, 23170, 23170,-23170, 23170,-23170, 23170},
@@ -276,7 +276,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   { 23170,-23170, 23170,-23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170,-23170, 23170,-23170,-23170, 23170},
   {-23170,-23170, 23170, 23170, 23170, 23170, 23170, 23170, 23170,-23170,-23170,-23170, 23170, 23170,-23170, 23170,-23170, 23170}
   };
-  int16_t table_5_2_2_2_3_Im[30][18]={ // Table 5.2.2.2-3 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=18)
+  static const int16_t table_5_2_2_2_3_Im[30][18]={ // Table 5.2.2.2-3 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=18)
   {-23170, 23170,-23170,-23170, 23170, 23170,-23170,-23170, 23170,-23170,-23170,-23170, 23170, 23170, 23170,-23170,-23170,-23170},
   { 23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170,-23170, 23170, 23170,-23170, 23170,-23170, 23170},
   {-23170, 23170, 23170,-23170,-23170, 23170,-23170,-23170, 23170, 23170, 23170, 23170, 23170,-23170, 23170,-23170,-23170,-23170},
@@ -308,7 +308,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   {-23170,-23170, 23170,-23170,-23170,-23170, 23170, 23170, 23170, 23170,-23170, 23170, 23170,-23170,-23170, 23170,-23170, 23170},
   {-23170, 23170, 23170,-23170,-23170,-23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170, 23170, 23170,-23170, 23170,-23170}
   };
-  int16_t table_5_2_2_2_4_Re[30][24]={ // Table 5.2.2.2-4 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=24)
+  static const int16_t table_5_2_2_2_4_Re[30][24]={ // Table 5.2.2.2-4 (Re part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=24)
   { 23170,-23170,-23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170, 23170,-23170,-23170,-23170,-23170,-23170,-23170,-23170},
   { 23170,-23170,-23170, 23170, 23170,-23170, 23170,-23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170,-23170, 23170,-23170,-23170,-23170,-23170},
   { 23170,-23170,-23170, 23170, 23170, 23170,-23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170, 23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170,-23170},
@@ -340,7 +340,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
   {-23170, 23170,-23170, 23170,-23170, 23170, 23170,-23170, 23170,-23170,-23170, 23170, 23170,-23170, 23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170},
   {-23170,-23170, 23170, 23170,-23170, 23170, 23170,-23170, 23170,-23170, 23170,-23170, 23170,-23170,-23170, 23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170}
   };
-  int16_t table_5_2_2_2_4_Im[30][24]={ // Table 5.2.2.2-4 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=24)
+  static const int16_t table_5_2_2_2_4_Im[30][24]={ // Table 5.2.2.2-4 (Im part) TS 38.211 Subclause 5.2.2.2 Base sequences of length less than 36 (M_ZC=24)
   {-23170,-23170, 23170,-23170, 23170, 23170, 23170,-23170, 23170,-23170,-23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170, 23170, 23170, 23170,-23170,-23170,-23170},
   {-23170,-23170, 23170, 23170, 23170,-23170, 23170,-23170,-23170, 23170,-23170,-23170,-23170, 23170,-23170, 23170, 23170, 23170,-23170, 23170, 23170, 23170,-23170,-23170},
   {-23170,-23170,-23170, 23170,-23170,-23170,-23170, 23170, 23170,-23170,-23170,-23170,-23170,-23170, 23170, 23170, 23170, 23170,-23170,-23170,-23170, 23170,-23170,-23170},
@@ -378,17 +378,17 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
    * One table for no intra-slot hopping
    * Two tables for intra-slot hopping (mprime=0 and mprime=1)
    */
-    uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_noHop[14] = {0,0,0,2,2,3,3,4,4,5,5,6,6,7}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when no intra-slot hopping
-    uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m0Hop[14] = {0,0,0,1,1,1,1,2,2,2,2,3,3,3}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=0
-    uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m1Hop[14] = {0,0,0,1,1,2,2,2,2,3,3,3,3,4}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=1
+    static const uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_noHop[14] = {0,0,0,2,2,3,3,4,4,5,5,6,6,7}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when no intra-slot hopping
+    static const uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m0Hop[14] = {0,0,0,1,1,1,1,2,2,2,2,3,3,3}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=0
+    static const uint8_t table_6_3_2_4_1_1_N_SF_mprime_PUCCH_1_m1Hop[14] = {0,0,0,1,1,2,2,2,2,3,3,3,3,4}; // for index PUCCH-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=1
   /*
    * The following tables implement TS 38.211 table 6.4.1.3.1.1-1: Number of DM-RS symbols and the corresponding N_SF_mprime_PUCCH_1
    * One table for no intra-slot hopping
    * Two tables for intra-slot hopping (mprime=0 and mprime=1)
    */
-    uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_noHop[14] = {0,0,0,2,3,3,4,4,5,5,6,6,7,7}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when no intra-slot hopping
-    uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m0Hop[14] = {0,0,0,1,1,2,2,2,2,3,3,3,3,4}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=0
-    uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m1Hop[14] = {0,0,0,1,2,1,2,2,3,2,3,3,4,3}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=1
+    static const uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_noHop[14] = {0,0,0,2,3,3,4,4,5,5,6,6,7,7}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when no intra-slot hopping
+    static const uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m0Hop[14] = {0,0,0,1,1,2,2,2,2,3,3,3,3,4}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=0
+    static const uint8_t table_6_4_1_3_1_1_1_N_SF_mprime_PUCCH_1_m1Hop[14] = {0,0,0,1,2,1,2,2,3,2,3,3,4,3}; // for index PUCCH-DM-RS-length, we obtain N_SF_mprime_PUCCH_1 when intra-slot hopping and mprime=1
   /* The following tables implement TS 38.211 table 6.3.2.4.1-2: Orthogonal sequences wi(m)=exp(j*2*pi*phi(m)/N_SF) for PUCCH format 1
     uint16_t table_6_3_2_4_1_2_W2[2][2] = {{0,0},          {0,1}};
     uint16_t table_6_3_2_4_1_2_W3[3][3] = {{0,0,0},        {0,1,2},        {0,2,1}};
@@ -397,7 +397,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
     uint16_t table_6_3_2_4_1_2_W6[2][2] = {{0,0,0,0,0,0},  {0,1,2,3,4,5},  {0,2,4,0,2,4},  {0,3,0,3,0,3},  {0,4,2,0,4,2},  {0,5,4,3,2,1}};
     uint16_t table_6_3_2_4_1_2_W7[2][2] = {{0,0,0,0,0,0,0},{0,1,2,3,4,5,6},{0,2,4,6,1,3,5},{0,3,6,2,5,1,4},{0,4,1,5,2,6,3},{0,5,3,1,6,4,2},{0,6,5,4,3,2,1}};
    */
-    int16_t table_6_3_2_4_1_2_Wi_Re[8][7][7] = {
+    static const int16_t table_6_3_2_4_1_2_Wi_Re[8][7][7] = {
     {{0,0,0,0,0,0,0},                            {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0}},
     {{32767,0,0,0,0,0,0},                        {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0}},
     {{32767,32767,0,0,0,0,0},                    {32767,-32767,0,0,0,0,0},                     {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0},                              {0,0,0,0,0,0,0}},
@@ -407,7 +407,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
     {{32767,32767,32767,32767,32767,32767,0},    {32767,16384,-16384,-32767,-16384,16384,0},   {32767,-16384,-16384,32767,-16384,-16384,0},  {32767,-32767,32767,-32767,32767,-32767,0},   {32767,-16384,-16384,32767,-16384,-16384,0},  {32767,16384,-16384,-32767,-16384,16384,0},   {0,0,0,0,0,0,0}},
     {{32767,32767,32767,32767,32767,32767,32767},{32767,20430,-7291,-29522,-29522,-7291,20430},{32767,-7291,-29522,20430,20430,-29522,-7291},{32767,-29522,20430,-7291,-7291,20430,-29522},{32767,-29522,20430,-7291,-7291,20430,-29522},{32767,-7291,-29522,20430,20430,-29522,-7291},{32767,20430,-7291,-29522,-29522,-7291,20430}}
     };
-    int16_t table_6_3_2_4_1_2_Wi_Im[8][7][7] = {
+    static const int16_t table_6_3_2_4_1_2_Wi_Im[8][7][7] = {
     {{0,0,0,0,0,0,0},{0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0}},
     {{0,0,0,0,0,0,0},{0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0}},
     {{0,0,0,0,0,0,0},{0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0},                           {0,0,0,0,0,0,0}},
@@ -418,7 +418,7 @@ void nr_generate_pucch3_4(PHY_VARS_NR_UE *ue,
     {{0,0,0,0,0,0,0},{0,25618,31945,14217,-14217,-31945,-25618},{0,31945,-14217,-25618,25618,14217,-31945},{0,14217,-25618,31945,-31945,25618,-14217},{0,-14217,25618,-31945,31945,-25618,14217},{0,-31945,14217,25618,-25618,-14217,31945},{0,-25618,-31945,-14217,14217,31945,25618}}
     };
 
-    uint8_t list_of_prime_numbers[46] = {2,  3,  5,  7,  11, 13, 17, 19, 23, 29,
+    static const uint8_t list_of_prime_numbers[46] = {2,  3,  5,  7,  11, 13, 17, 19, 23, 29,
                                          31, 37, 41, 43, 47, 53, 59, 61, 67, 71,
                                          73, 79, 83, 89, 97, 101,103,107,109,113,
                                          127,131,137,139,149,151,157,163,167,173,

openair1/PHY/defs_RU.h

@@ -399,7 +399,7 @@ typedef struct RU_t_s{
   /// function pointer to release function for radio interface
   int                  (*stop_rf)(struct RU_t_s *ru);
   /// function pointer to initialization function for radio interface
-  int                  (*start_if)(struct RU_t_s *ru,struct PHY_VARS_eNB_s *eNB);
+  int                  (*start_if)(struct RU_t_s *ru,struct PHY_VARS_gNB_s *gNB);
   /// function pointer to RX front-end processing routine (DFTs/prefix removal or NULL)
   void                 (*feprx)(struct RU_t_s *ru);
   /// function pointer to TX front-end processing routine (IDFTs and prefix removal or NULL)

openair1/PHY/defs_nr_UE.h

@@ -1021,11 +1021,13 @@ typedef struct {
   NR_UE_COMMON    common_vars;
 
   nr_ue_if_module_t *if_inst;
+
   nr_downlink_indication_t dl_indication;
   nr_uplink_indication_t ul_indication;
   /// UE FAPI DCI request
   nr_dcireq_t dcireq;
 
+  // CHECK if we need those as they are also included in dl_indictation
   /// UE FAPI indication for DLSCH reception
   fapi_nr_rx_indication_t rx_ind;
   /// UE FAPI indication for DCI reception

openair1/PHY/sse_intrin.h

@@ -26,11 +26,11 @@
  * The host CPU needs to have support for SSE2 at least. SSE3 and SSE4.1 functions are emulated if the CPU lacks support for them.
  * This will slow down the softmodem, but may be valuable if only offline signal processing is required.
  *
- * \author S. Held
- * \email sebastian.held@imst.de
- * \company IMST GmbH
- * \date 2015
- * \version 0.1
+ * \author S. Held, Laurent THOMAS
+ * \email sebastian.held@imst.de, laurent.thomas@open-cells.com	
+ * \company IMST GmbH, Open Cells Project
+ * \date 2019
+ * \version 0.2
 */
 
 #ifndef SSE_INTRIN_H
@@ -40,23 +40,23 @@
 #if defined(__x86_64) || defined(__i386__)
 
 #ifndef __SSE2__
-#  error SSE2 processor intrinsics disabled
+  #  error SSE2 processor intrinsics disabled
 #endif
 
 #include <emmintrin.h>
 #include <xmmintrin.h>
 
 #ifdef __SSE3__
-#  include <pmmintrin.h>
-#  include <tmmintrin.h>
+  #include <pmmintrin.h>
+  #include <tmmintrin.h>
 #endif
 
 #ifdef __SSE4_1__
-#  include <smmintrin.h>
+  #include <smmintrin.h>
 #endif
 
 #ifdef __AVX2__
-#  include <immintrin.h>
+  #include <immintrin.h>
 #endif
 
 // ------------------------------------------------
@@ -108,8 +108,7 @@ typedef union {
  * \date 2006-2008
  * \copyright Apache License 2.0
  */
-static inline __m128i ssp_comge_epi8_SSE2(__m128i a, __m128i b)
-{
+static inline __m128i ssp_comge_epi8_SSE2(__m128i a, __m128i b) {
   __m128i c;
   c = _mm_cmpgt_epi8( a, b );
   a = _mm_cmpeq_epi8( a, b );
@@ -126,13 +125,11 @@ static inline __m128i ssp_comge_epi8_SSE2(__m128i a, __m128i b)
  * \date 2006-2008
  * \copyright Apache License 2.0
  */
-static inline __m128i ssp_shuffle_epi8_SSE2 (__m128i a, __m128i mask)
-{
+static inline __m128i ssp_shuffle_epi8_SSE2 (__m128i a, __m128i mask) {
   ssp_m128 A,B, MASK, maskZero;
   A.i        = a;
   maskZero.i = ssp_comge_epi8_SSE2( mask, _mm_setzero_si128()        );