Changes

Page history
AMD EPYC Processors Added authored by Manish's avatar Manish
Show whitespace changes
Inline Side-by-side
5g-nr-development-and-setup.md
View page @ ebf19798
...@@ -36,6 +36,10 @@ LDPC on FPGA (same as above) ...@@ -36,6 +36,10 @@ LDPC on FPGA (same as above)
3. Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz with 18 cores and 2x10Gbit Ethernet 3. Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz with 18 cores and 2x10Gbit Ethernet
4. AMD EPYC™ 3rd Gen 7513 32-Core Processor and 2x10Gbit Ethernet
5. AMD EPYC™ 3rd Gen 7713 64 Cores Processor and 2x10Gbit Ethernet
## SDR (Software Defined Radio) / USRP (Universal Software Radio Peripheral) ## SDR (Software Defined Radio) / USRP (Universal Software Radio Peripheral)
Please also see the following presentation for more details on hardware: Please also see the following presentation for more details on hardware:
...@@ -80,4 +84,4 @@ please see [gNB vs COTS UE Testing](https://gitlab.eurecom.fr/oai/openairinterfa ...@@ -80,4 +84,4 @@ please see [gNB vs COTS UE Testing](https://gitlab.eurecom.fr/oai/openairinterfa
# Further documents # Further documents
- [UE_FAPI-like_interface.docx](/uploads/f7386f3a64806fd6b2ac1fc3d0252fff/UE_FAPI-like_interface.docx) - [UE_FAPI-like_interface.docx](/uploads/f7386f3a64806fd6b2ac1fc3d0252fff/UE_FAPI-like_interface.docx)
-- Florian Kaltenberger 17.7.2020 -- Manish 25.3.2022
\ No newline at end of file \ No newline at end of file