linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.009.git-186-g4082c748 # /dev/cpu_dma_latency set to 0us log init done Downlink for CC_id 0 frequency set to 875000000 configuring for UE CPU Freq is 3.591969 [NETLINK]Opened socket with fd 35 reported resolution = 1 ns [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 RBstart 0, len 1 --> alloc 0 1, allocdist0_even 1, allocdist0_odd 1000 RBstart 0, len 2 --> alloc 0 3, allocdist0_even 41, allocdist0_odd 41000 RBstart 0, len 3 --> alloc 0 7, allocdist0_even 1041, allocdist0_odd 41001 RBstart 0, len 4 --> alloc 0 f, allocdist0_even 41041, allocdist0_odd 41041 RBstart 0, len 5 --> alloc 0 1f, allocdist0_even 41043, allocdist0_odd 43041 RBstart 0, len 6 --> alloc 0 3f, allocdist0_even 410c3, allocdist0_odd c3041 RBstart 0, len 7 --> alloc 0 7f, allocdist0_even 430c3, allocdist0_odd c3043 RBstart 0, len 8 --> alloc 0 ff, allocdist0_even c30c3, allocdist0_odd c30c3 RBstart 0, len 9 --> alloc 0 1ff, allocdist0_even c30c7, allocdist0_odd c70c3 RBstart 0, len 10 --> alloc 0 3ff, allocdist0_even c31c7, allocdist0_odd 1c70c3 RBstart 0, len 11 --> alloc 0 7ff, allocdist0_even c71c7, allocdist0_odd 1c70c7 RBstart 0, len 12 --> alloc 0 fff, allocdist0_even 1c71c7, allocdist0_odd 1c71c7 RBstart 0, len 13 --> alloc 0 1fff, allocdist0_even 1c71cf, allocdist0_odd 1cf1c7 RBstart 0, len 14 --> alloc 0 3fff, allocdist0_even 1c73cf, allocdist0_odd 3cf1c7 RBstart 0, len 15 --> alloc 0 7fff, allocdist0_even 1cf3cf, allocdist0_odd 3cf1cf RBstart 0, len 16 --> alloc 0 ffff, allocdist0_even 3cf3cf, allocdist0_odd 3cf3cf RBstart 0, len 17 --> alloc 0 1ffff, allocdist0_even 3cf3df, allocdist0_odd 3df3cf RBstart 0, len 18 --> alloc 0 3ffff, allocdist0_even 3cf7df, allocdist0_odd 7df3cf RBstart 0, len 19 --> alloc 0 7ffff, allocdist0_even 3df7df, allocdist0_odd 7df3df RBstart 0, len 20 --> alloc 0 fffff, allocdist0_even 7df7df, allocdist0_odd 7df7df RBstart 0, len 21 --> alloc 0 1fffff, allocdist0_even 7df7ff, allocdist0_odd 7ff7df RBstart 0, len 22 --> alloc 0 3fffff, allocdist0_even 7dffff, allocdist0_odd fff7df RBstart 0, len 23 --> alloc 0 7fffff, allocdist0_even 7fffff, allocdist0_odd fff7ff RBstart 0, len 24 --> alloc 0 ffffff, allocdist0_even ffffff, allocdist0_odd ffffff RBstart 0, len 25 --> alloc 0 1ffffff, allocdist0_even 40ffffff, allocdist0_odd ffffff RBstart 1, len 1 --> alloc 0 2, allocdist0_even 40, allocdist0_odd 40000 RBstart 1, len 2 --> alloc 0 6, allocdist0_even 1040, allocdist0_odd 40001 RBstart 1, len 3 --> alloc 0 e, allocdist0_even 41040, allocdist0_odd 40041 RBstart 1, len 4 --> alloc 0 1e, allocdist0_even 41042, allocdist0_odd 42041 RBstart 1, len 5 --> alloc 0 3e, allocdist0_even 410c2, allocdist0_odd c2041 RBstart 1, len 6 --> alloc 0 7e, allocdist0_even 430c2, allocdist0_odd c2043 RBstart 1, len 7 --> alloc 0 fe, allocdist0_even c30c2, allocdist0_odd c20c3 RBstart 1, len 8 --> alloc 0 1fe, allocdist0_even c30c6, allocdist0_odd c60c3 RBstart 1, len 9 --> alloc 0 3fe, allocdist0_even c31c6, allocdist0_odd 1c60c3 RBstart 1, len 10 --> alloc 0 7fe, allocdist0_even c71c6, allocdist0_odd 1c60c7 RBstart 1, len 11 --> alloc 0 ffe, allocdist0_even 1c71c6, allocdist0_odd 1c61c7 RBstart 1, len 12 --> alloc 0 1ffe, allocdist0_even 1c71ce, allocdist0_odd 1ce1c7 RBstart 1, len 13 --> alloc 0 3ffe, allocdist0_even 1c73ce, allocdist0_odd 3ce1c7 RBstart 1, len 14 --> alloc 0 7ffe, allocdist0_even 1cf3ce, allocdist0_odd 3ce1cf RBstart 1, len 15 --> alloc 0 fffe, allocdist0_even 3cf3ce, allocdist0_odd 3ce3cf RBstart 1, len 16 --> alloc 0 1fffe, allocdist0_even 3cf3de, allocdist0_odd 3de3cf RBstart 1, len 17 --> alloc 0 3fffe, allocdist0_even 3cf7de, allocdist0_odd 7de3cf RBstart 1, len 18 --> alloc 0 7fffe, allocdist0_even 3df7de, allocdist0_odd 7de3df RBstart 1, len 19 --> alloc 0 ffffe, allocdist0_even 7df7de, allocdist0_odd 7de7df RBstart 1, len 20 --> alloc 0 1ffffe, allocdist0_even 7df7fe, allocdist0_odd 7fe7df RBstart 1, len 21 --> alloc 0 3ffffe, allocdist0_even 7dfffe, allocdist0_odd ffe7df RBstart 1, len 22 --> alloc 0 7ffffe, allocdist0_even 7ffffe, allocdist0_odd ffe7ff RBstart 1, len 23 --> alloc 0 fffffe, allocdist0_even fffffe, allocdist0_odd ffefff RBstart 1, len 24 --> alloc 0 1fffffe, allocdist0_even 40fffffe, allocdist0_odd ffefff RBstart 2, len 1 --> alloc 0 4, allocdist0_even 1000, allocdist0_odd 1 RBstart 2, len 2 --> alloc 0 c, allocdist0_even 41000, allocdist0_odd 41 RBstart 2, len 3 --> alloc 0 1c, allocdist0_even 41002, allocdist0_odd 2041 RBstart 2, len 4 --> alloc 0 3c, allocdist0_even 41082, allocdist0_odd 82041 RBstart 2, len 5 --> alloc 0 7c, allocdist0_even 43082, allocdist0_odd 82043 RBstart 2, len 6 --> alloc 0 fc, allocdist0_even c3082, allocdist0_odd 820c3 RBstart 2, len 7 --> alloc 0 1fc, allocdist0_even c3086, allocdist0_odd 860c3 RBstart 2, len 8 --> alloc 0 3fc, allocdist0_even c3186, allocdist0_odd 1860c3 RBstart 2, len 9 --> alloc 0 7fc, allocdist0_even c7186, allocdist0_odd 1860c7 RBstart 2, len 10 --> alloc 0 ffc, allocdist0_even 1c7186, allocdist0_odd 1861c7 RBstart 2, len 11 --> alloc 0 1ffc, allocdist0_even 1c718e, allocdist0_odd 18e1c7 RBstart 2, len 12 --> alloc 0 3ffc, allocdist0_even 1c738e, allocdist0_odd 38e1c7 RBstart 2, len 13 --> alloc 0 7ffc, allocdist0_even 1cf38e, allocdist0_odd 38e1cf RBstart 2, len 14 --> alloc 0 fffc, allocdist0_even 3cf38e, allocdist0_odd 38e3cf RBstart 2, len 15 --> alloc 0 1fffc, allocdist0_even 3cf39e, allocdist0_odd 39e3cf RBstart 2, len 16 --> alloc 0 3fffc, allocdist0_even 3cf79e, allocdist0_odd 79e3cf RBstart 2, len 17 --> alloc 0 7fffc, allocdist0_even 3df79e, allocdist0_odd 79e3df RBstart 2, len 18 --> alloc 0 ffffc, allocdist0_even 7df79e, allocdist0_odd 79e7df RBstart 2, len 19 --> alloc 0 1ffffc, allocdist0_even 7df7be, allocdist0_odd 7be7df RBstart 2, len 20 --> alloc 0 3ffffc, allocdist0_even 7dffbe, allocdist0_odd fbe7df RBstart 2, len 21 --> alloc 0 7ffffc, allocdist0_even 7fffbe, allocdist0_odd fbe7ff RBstart 2, len 22 --> alloc 0 fffffc, allocdist0_even ffffbe, allocdist0_odd fbefff RBstart 2, len 23 --> alloc 0 1fffffc, allocdist0_even 40ffffbe, allocdist0_odd fbefff RBstart 3, len 1 --> alloc 0 8, allocdist0_even 40000, allocdist0_odd 40 RBstart 3, len 2 --> alloc 0 18, allocdist0_even 40002, allocdist0_odd 2040 RBstart 3, len 3 --> alloc 0 38, allocdist0_even 40082, allocdist0_odd 82040 RBstart 3, len 4 --> alloc 0 78, allocdist0_even 42082, allocdist0_odd 82042 RBstart 3, len 5 --> alloc 0 f8, allocdist0_even c2082, allocdist0_odd 820c2 RBstart 3, len 6 --> alloc 0 1f8, allocdist0_even c2086, allocdist0_odd 860c2 RBstart 3, len 7 --> alloc 0 3f8, allocdist0_even c2186, allocdist0_odd 1860c2 RBstart 3, len 8 --> alloc 0 7f8, allocdist0_even c6186, allocdist0_odd 1860c6 RBstart 3, len 9 --> alloc 0 ff8, allocdist0_even 1c6186, allocdist0_odd 1861c6 RBstart 3, len 10 --> alloc 0 1ff8, allocdist0_even 1c618e, allocdist0_odd 18e1c6 RBstart 3, len 11 --> alloc 0 3ff8, allocdist0_even 1c638e, allocdist0_odd 38e1c6 RBstart 3, len 12 --> alloc 0 7ff8, allocdist0_even 1ce38e, allocdist0_odd 38e1ce RBstart 3, len 13 --> alloc 0 fff8, allocdist0_even 3ce38e, allocdist0_odd 38e3ce RBstart 3, len 14 --> alloc 0 1fff8, allocdist0_even 3ce39e, allocdist0_odd 39e3ce RBstart 3, len 15 --> alloc 0 3fff8, allocdist0_even 3ce79e, allocdist0_odd 79e3ce RBstart 3, len 16 --> alloc 0 7fff8, allocdist0_even 3de79e, allocdist0_odd 79e3de RBstart 3, len 17 --> alloc 0 ffff8, allocdist0_even 7de79e, allocdist0_odd 79e7de RBstart 3, len 18 --> alloc 0 1ffff8, allocdist0_even 7de7be, allocdist0_odd 7be7de RBstart 3, len 19 --> alloc 0 3ffff8, allocdist0_even 7defbe, allocdist0_odd fbe7de RBstart 3, len 20 --> alloc 0 7ffff8, allocdist0_even 7fefbe, allocdist0_odd fbe7fe RBstart 3, len 21 --> alloc 0 fffff8, allocdist0_even ffefbe, allocdist0_odd fbeffe RBstart 3, len 22 --> alloc 0 1fffff8, allocdist0_even 40ffefbe, allocdist0_odd fbeffe RBstart 4, len 1 --> alloc 0 10, allocdist0_even 2, allocdist0_odd 2000 RBstart 4, len 2 --> alloc 0 30, allocdist0_even 82, allocdist0_odd 82000 RBstart 4, len 3 --> alloc 0 70, allocdist0_even 2082, allocdist0_odd 82002 RBstart 4, len 4 --> alloc 0 f0, allocdist0_even 82082, allocdist0_odd 82082 RBstart 4, len 5 --> alloc 0 1f0, allocdist0_even 82086, allocdist0_odd 86082 RBstart 4, len 6 --> alloc 0 3f0, allocdist0_even 82186, allocdist0_odd 186082 RBstart 4, len 7 --> alloc 0 7f0, allocdist0_even 86186, allocdist0_odd 186086 RBstart 4, len 8 --> alloc 0 ff0, allocdist0_even 186186, allocdist0_odd 186186 RBstart 4, len 9 --> alloc 0 1ff0, allocdist0_even 18618e, allocdist0_odd 18e186 RBstart 4, len 10 --> alloc 0 3ff0, allocdist0_even 18638e, allocdist0_odd 38e186 RBstart 4, len 11 --> alloc 0 7ff0, allocdist0_even 18e38e, allocdist0_odd 38e18e RBstart 4, len 12 --> alloc 0 fff0, allocdist0_even 38e38e, allocdist0_odd 38e38e RBstart 4, len 13 --> alloc 0 1fff0, allocdist0_even 38e39e, allocdist0_odd 39e38e RBstart 4, len 14 --> alloc 0 3fff0, allocdist0_even 38e79e, allocdist0_odd 79e38e RBstart 4, len 15 --> alloc 0 7fff0, allocdist0_even 39e79e, allocdist0_odd 79e39e RBstart 4, len 16 --> alloc 0 ffff0, allocdist0_even 79e79e, allocdist0_odd 79e79e RBstart 4, len 17 --> alloc 0 1ffff0, allocdist0_even 79e7be, allocdist0_odd 7be79e RBstart 4, len 18 --> alloc 0 3ffff0, allocdist0_even 79efbe, allocdist0_odd fbe79e RBstart 4, len 19 --> alloc 0 7ffff0, allocdist0_even 7befbe, allocdist0_odd fbe7be RBstart 4, len 20 --> alloc 0 fffff0, allocdist0_even fbefbe, allocdist0_odd fbefbe RBstart 4, len 21 --> alloc 0 1fffff0, allocdist0_even 40fbefbe, allocdist0_odd fbefbe RBstart 5, len 1 --> alloc 0 20, allocdist0_even 80, allocdist0_odd 80000 RBstart 5, len 2 --> alloc 0 60, allocdist0_even 2080, allocdist0_odd 80002 RBstart 5, len 3 --> alloc 0 e0, allocdist0_even 82080, allocdist0_odd 80082 RBstart 5, len 4 --> alloc 0 1e0, allocdist0_even 82084, allocdist0_odd 84082 RBstart 5, len 5 --> alloc 0 3e0, allocdist0_even 82184, allocdist0_odd 184082 RBstart 5, len 6 --> alloc 0 7e0, allocdist0_even 86184, allocdist0_odd 184086 RBstart 5, len 7 --> alloc 0 fe0, allocdist0_even 186184, allocdist0_odd 184186 RBstart 5, len 8 --> alloc 0 1fe0, allocdist0_even 18618c, allocdist0_odd 18c186 RBstart 5, len 9 --> alloc 0 3fe0, allocdist0_even 18638c, allocdist0_odd 38c186 RBstart 5, len 10 --> alloc 0 7fe0, allocdist0_even 18e38c, allocdist0_odd 38c18e RBstart 5, len 11 --> alloc 0 ffe0, allocdist0_even 38e38c, allocdist0_odd 38c38e RBstart 5, len 12 --> alloc 0 1ffe0, allocdist0_even 38e39c, allocdist0_odd 39c38e RBstart 5, len 13 --> alloc 0 3ffe0, allocdist0_even 38e79c, allocdist0_odd 79c38e RBstart 5, len 14 --> alloc 0 7ffe0, allocdist0_even 39e79c, allocdist0_odd 79c39e RBstart 5, len 15 --> alloc 0 fffe0, allocdist0_even 79e79c, allocdist0_odd 79c79e RBstart 5, len 16 --> alloc 0 1fffe0, allocdist0_even 79e7bc, allocdist0_odd 7bc79e RBstart 5, len 17 --> alloc 0 3fffe0, allocdist0_even 79efbc, allocdist0_odd fbc79e RBstart 5, len 18 --> alloc 0 7fffe0, allocdist0_even 7befbc, allocdist0_odd fbc7be RBstart 5, len 19 --> alloc 0 ffffe0, allocdist0_even fbefbc, allocdist0_odd fbcfbe RBstart 5, len 20 --> alloc 0 1ffffe0, allocdist0_even 40fbefbc, allocdist0_odd fbcfbe RBstart 6, len 1 --> alloc 0 40, allocdist0_even 2000, allocdist0_odd 2 RBstart 6, len 2 --> alloc 0 c0, allocdist0_even 82000, allocdist0_odd 82 RBstart 6, len 3 --> alloc 0 1c0, allocdist0_even 82004, allocdist0_odd 4082 RBstart 6, len 4 --> alloc 0 3c0, allocdist0_even 82104, allocdist0_odd 104082 RBstart 6, len 5 --> alloc 0 7c0, allocdist0_even 86104, allocdist0_odd 104086 RBstart 6, len 6 --> alloc 0 fc0, allocdist0_even 186104, allocdist0_odd 104186 RBstart 6, len 7 --> alloc 0 1fc0, allocdist0_even 18610c, allocdist0_odd 10c186 RBstart 6, len 8 --> alloc 0 3fc0, allocdist0_even 18630c, allocdist0_odd 30c186 RBstart 6, len 9 --> alloc 0 7fc0, allocdist0_even 18e30c, allocdist0_odd 30c18e RBstart 6, len 10 --> alloc 0 ffc0, allocdist0_even 38e30c, allocdist0_odd 30c38e RBstart 6, len 11 --> alloc 0 1ffc0, allocdist0_even 38e31c, allocdist0_odd 31c38e RBstart 6, len 12 --> alloc 0 3ffc0, allocdist0_even 38e71c, allocdist0_odd 71c38e RBstart 6, len 13 --> alloc 0 7ffc0, allocdist0_even 39e71c, allocdist0_odd 71c39e RBstart 6, len 14 --> alloc 0 fffc0, allocdist0_even 79e71c, allocdist0_odd 71c79e RBstart 6, len 15 --> alloc 0 1fffc0, allocdist0_even 79e73c, allocdist0_odd 73c79e RBstart 6, len 16 --> alloc 0 3fffc0, allocdist0_even 79ef3c, allocdist0_odd f3c79e RBstart 6, len 17 --> alloc 0 7fffc0, allocdist0_even 7bef3c, allocdist0_odd f3c7be RBstart 6, len 18 --> alloc 0 ffffc0, allocdist0_even fbef3c, allocdist0_odd f3cfbe RBstart 6, len 19 --> alloc 0 1ffffc0, allocdist0_even 40fbef3c, allocdist0_odd f3cfbe RBstart 7, len 1 --> alloc 0 80, allocdist0_even 80000, allocdist0_odd 80 RBstart 7, len 2 --> alloc 0 180, allocdist0_even 80004, allocdist0_odd 4080 RBstart 7, len 3 --> alloc 0 380, allocdist0_even 80104, allocdist0_odd 104080 RBstart 7, len 4 --> alloc 0 780, allocdist0_even 84104, allocdist0_odd 104084 RBstart 7, len 5 --> alloc 0 f80, allocdist0_even 184104, allocdist0_odd 104184 RBstart 7, len 6 --> alloc 0 1f80, allocdist0_even 18410c, allocdist0_odd 10c184 RBstart 7, len 7 --> alloc 0 3f80, allocdist0_even 18430c, allocdist0_odd 30c184 RBstart 7, len 8 --> alloc 0 7f80, allocdist0_even 18c30c, allocdist0_odd 30c18c RBstart 7, len 9 --> alloc 0 ff80, allocdist0_even 38c30c, allocdist0_odd 30c38c RBstart 7, len 10 --> alloc 0 1ff80, allocdist0_even 38c31c, allocdist0_odd 31c38c RBstart 7, len 11 --> alloc 0 3ff80, allocdist0_even 38c71c, allocdist0_odd 71c38c RBstart 7, len 12 --> alloc 0 7ff80, allocdist0_even 39c71c, allocdist0_odd 71c39c RBstart 7, len 13 --> alloc 0 fff80, allocdist0_even 79c71c, allocdist0_odd 71c79c RBstart 7, len 14 --> alloc 0 1fff80, allocdist0_even 79c73c, allocdist0_odd 73c79c RBstart 7, len 15 --> alloc 0 3fff80, allocdist0_even 79cf3c, allocdist0_odd f3c79c RBstart 7, len 16 --> alloc 0 7fff80, allocdist0_even 7bcf3c, allocdist0_odd f3c7bc RBstart 7, len 17 --> alloc 0 ffff80, allocdist0_even fbcf3c, allocdist0_odd f3cfbc RBstart 7, len 18 --> alloc 0 1ffff80, allocdist0_even 40fbcf3c, allocdist0_odd f3cfbc RBstart 8, len 1 --> alloc 0 100, allocdist0_even 4, allocdist0_odd 4000 RBstart 8, len 2 --> alloc 0 300, allocdist0_even 104, allocdist0_odd 104000 RBstart 8, len 3 --> alloc 0 700, allocdist0_even 4104, allocdist0_odd 104004 RBstart 8, len 4 --> alloc 0 f00, allocdist0_even 104104, allocdist0_odd 104104 RBstart 8, len 5 --> alloc 0 1f00, allocdist0_even 10410c, allocdist0_odd 10c104 RBstart 8, len 6 --> alloc 0 3f00, allocdist0_even 10430c, allocdist0_odd 30c104 RBstart 8, len 7 --> alloc 0 7f00, allocdist0_even 10c30c, allocdist0_odd 30c10c RBstart 8, len 8 --> alloc 0 ff00, allocdist0_even 30c30c, allocdist0_odd 30c30c RBstart 8, len 9 --> alloc 0 1ff00, allocdist0_even 30c31c, allocdist0_odd 31c30c RBstart 8, len 10 --> alloc 0 3ff00, allocdist0_even 30c71c, allocdist0_odd 71c30c RBstart 8, len 11 --> alloc 0 7ff00, allocdist0_even 31c71c, allocdist0_odd 71c31c RBstart 8, len 12 --> alloc 0 fff00, allocdist0_even 71c71c, allocdist0_odd 71c71c RBstart 8, len 13 --> alloc 0 1fff00, allocdist0_even 71c73c, allocdist0_odd 73c71c RBstart 8, len 14 --> alloc 0 3fff00, allocdist0_even 71cf3c, allocdist0_odd f3c71c RBstart 8, len 15 --> alloc 0 7fff00, allocdist0_even 73cf3c, allocdist0_odd f3c73c RBstart 8, len 16 --> alloc 0 ffff00, allocdist0_even f3cf3c, allocdist0_odd f3cf3c RBstart 8, len 17 --> alloc 0 1ffff00, allocdist0_even 40f3cf3c, allocdist0_odd f3cf3c RBstart 9, len 1 --> alloc 0 200, allocdist0_even 100, allocdist0_odd 100000 RBstart 9, len 2 --> alloc 0 600, allocdist0_even 4100, allocdist0_odd 100004 RBstart 9, len 3 --> alloc 0 e00, allocdist0_even 104100, allocdist0_odd 100104 RBstart 9, len 4 --> alloc 0 1e00, allocdist0_even 104108, allocdist0_odd 108104 RBstart 9, len 5 --> alloc 0 3e00, allocdist0_even 104308, allocdist0_odd 308104 RBstart 9, len 6 --> alloc 0 7e00, allocdist0_even 10c308, allocdist0_odd 30810c RBstart 9, len 7 --> alloc 0 fe00, allocdist0_even 30c308, allocdist0_odd 30830c RBstart 9, len 8 --> alloc 0 1fe00, allocdist0_even 30c318, allocdist0_odd 31830c RBstart 9, len 9 --> alloc 0 3fe00, allocdist0_even 30c718, allocdist0_odd 71830c RBstart 9, len 10 --> alloc 0 7fe00, allocdist0_even 31c718, allocdist0_odd 71831c RBstart 9, len 11 --> alloc 0 ffe00, allocdist0_even 71c718, allocdist0_odd 71871c RBstart 9, len 12 --> alloc 0 1ffe00, allocdist0_even 71c738, allocdist0_odd 73871c RBstart 9, len 13 --> alloc 0 3ffe00, allocdist0_even 71cf38, allocdist0_odd f3871c RBstart 9, len 14 --> alloc 0 7ffe00, allocdist0_even 73cf38, allocdist0_odd f3873c RBstart 9, len 15 --> alloc 0 fffe00, allocdist0_even f3cf38, allocdist0_odd f38f3c RBstart 9, len 16 --> alloc 0 1fffe00, allocdist0_even 40f3cf38, allocdist0_odd f38f3c RBstart 10, len 1 --> alloc 0 400, allocdist0_even 4000, allocdist0_odd 4 RBstart 10, len 2 --> alloc 0 c00, allocdist0_even 104000, allocdist0_odd 104 RBstart 10, len 3 --> alloc 0 1c00, allocdist0_even 104008, allocdist0_odd 8104 RBstart 10, len 4 --> alloc 0 3c00, allocdist0_even 104208, allocdist0_odd 208104 RBstart 10, len 5 --> alloc 0 7c00, allocdist0_even 10c208, allocdist0_odd 20810c RBstart 10, len 6 --> alloc 0 fc00, allocdist0_even 30c208, allocdist0_odd 20830c RBstart 10, len 7 --> alloc 0 1fc00, allocdist0_even 30c218, allocdist0_odd 21830c RBstart 10, len 8 --> alloc 0 3fc00, allocdist0_even 30c618, allocdist0_odd 61830c RBstart 10, len 9 --> alloc 0 7fc00, allocdist0_even 31c618, allocdist0_odd 61831c RBstart 10, len 10 --> alloc 0 ffc00, allocdist0_even 71c618, allocdist0_odd 61871c RBstart 10, len 11 --> alloc 0 1ffc00, allocdist0_even 71c638, allocdist0_odd 63871c RBstart 10, len 12 --> alloc 0 3ffc00, allocdist0_even 71ce38, allocdist0_odd e3871c RBstart 10, len 13 --> alloc 0 7ffc00, allocdist0_even 73ce38, allocdist0_odd e3873c RBstart 10, len 14 --> alloc 0 fffc00, allocdist0_even f3ce38, allocdist0_odd e38f3c RBstart 10, len 15 --> alloc 0 1fffc00, allocdist0_even 40f3ce38, allocdist0_odd e38f3c RBstart 11, len 1 --> alloc 0 800, allocdist0_even 100000, allocdist0_odd 100 RBstart 11, len 2 --> alloc 0 1800, allocdist0_even 100008, allocdist0_odd 8100 RBstart 11, len 3 --> alloc 0 3800, allocdist0_even 100208, allocdist0_odd 208100 RBstart 11, len 4 --> alloc 0 7800, allocdist0_even 108208, allocdist0_odd 208108 RBstart 11, len 5 --> alloc 0 f800, allocdist0_even 308208, allocdist0_odd 208308 RBstart 11, len 6 --> alloc 0 1f800, allocdist0_even 308218, allocdist0_odd 218308 RBstart 11, len 7 --> alloc 0 3f800, allocdist0_even 308618, allocdist0_odd 618308 RBstart 11, len 8 --> alloc 0 7f800, allocdist0_even 318618, allocdist0_odd 618318 RBstart 11, len 9 --> alloc 0 ff800, allocdist0_even 718618, allocdist0_odd 618718 RBstart 11, len 10 --> alloc 0 1ff800, allocdist0_even 718638, allocdist0_odd 638718 RBstart 11, len 11 --> alloc 0 3ff800, allocdist0_even 718e38, allocdist0_odd e38718 RBstart 11, len 12 --> alloc 0 7ff800, allocdist0_even 738e38, allocdist0_odd e38738 RBstart 11, len 13 --> alloc 0 fff800, allocdist0_even f38e38, allocdist0_odd e38f38 RBstart 11, len 14 --> alloc 0 1fff800, allocdist0_even 40f38e38, allocdist0_odd e38f38 RBstart 12, len 1 --> alloc 0 1000, allocdist0_even 8, allocdist0_odd 8000 RBstart 12, len 2 --> alloc 0 3000, allocdist0_even 208, allocdist0_odd 208000 RBstart 12, len 3 --> alloc 0 7000, allocdist0_even 8208, allocdist0_odd 208008 RBstart 12, len 4 --> alloc 0 f000, allocdist0_even 208208, allocdist0_odd 208208 RBstart 12, len 5 --> alloc 0 1f000, allocdist0_even 208218, allocdist0_odd 218208 RBstart 12, len 6 --> alloc 0 3f000, allocdist0_even 208618, allocdist0_odd 618208 RBstart 12, len 7 --> alloc 0 7f000, allocdist0_even 218618, allocdist0_odd 618218 RBstart 12, len 8 --> alloc 0 ff000, allocdist0_even 618618, allocdist0_odd 618618 RBstart 12, len 9 --> alloc 0 1ff000, allocdist0_even 618638, allocdist0_odd 638618 RBstart 12, len 10 --> alloc 0 3ff000, allocdist0_even 618e38, allocdist0_odd e38618 RBstart 12, len 11 --> alloc 0 7ff000, allocdist0_even 638e38, allocdist0_odd e38638 RBstart 12, len 12 --> alloc 0 fff000, allocdist0_even e38e38, allocdist0_odd e38e38 RBstart 12, len 13 --> alloc 0 1fff000, allocdist0_even 40e38e38, allocdist0_odd e38e38 RBstart 13, len 1 --> alloc 0 2000, allocdist0_even 200, allocdist0_odd 200000 RBstart 13, len 2 --> alloc 0 6000, allocdist0_even 8200, allocdist0_odd 200008 RBstart 13, len 3 --> alloc 0 e000, allocdist0_even 208200, allocdist0_odd 200208 RBstart 13, len 4 --> alloc 0 1e000, allocdist0_even 208210, allocdist0_odd 210208 RBstart 13, len 5 --> alloc 0 3e000, allocdist0_even 208610, allocdist0_odd 610208 RBstart 13, len 6 --> alloc 0 7e000, allocdist0_even 218610, allocdist0_odd 610218 RBstart 13, len 7 --> alloc 0 fe000, allocdist0_even 618610, allocdist0_odd 610618 RBstart 13, len 8 --> alloc 0 1fe000, allocdist0_even 618630, allocdist0_odd 630618 RBstart 13, len 9 --> alloc 0 3fe000, allocdist0_even 618e30, allocdist0_odd e30618 RBstart 13, len 10 --> alloc 0 7fe000, allocdist0_even 638e30, allocdist0_odd e30638 RBstart 13, len 11 --> alloc 0 ffe000, allocdist0_even e38e30, allocdist0_odd e30e38 RBstart 13, len 12 --> alloc 0 1ffe000, allocdist0_even 40e38e30, allocdist0_odd e30e38 RBstart 14, len 1 --> alloc 0 4000, allocdist0_even 8000, allocdist0_odd 8 RBstart 14, len 2 --> alloc 0 c000, allocdist0_even 208000, allocdist0_odd 208 RBstart 14, len 3 --> alloc 0 1c000, allocdist0_even 208010, allocdist0_odd 10208 RBstart 14, len 4 --> alloc 0 3c000, allocdist0_even 208410, allocdist0_odd 410208 RBstart 14, len 5 --> alloc 0 7c000, allocdist0_even 218410, allocdist0_odd 410218 RBstart 14, len 6 --> alloc 0 fc000, allocdist0_even 618410, allocdist0_odd 410618 RBstart 14, len 7 --> alloc 0 1fc000, allocdist0_even 618430, allocdist0_odd 430618 RBstart 14, len 8 --> alloc 0 3fc000, allocdist0_even 618c30, allocdist0_odd c30618 RBstart 14, len 9 --> alloc 0 7fc000, allocdist0_even 638c30, allocdist0_odd c30638 RBstart 14, len 10 --> alloc 0 ffc000, allocdist0_even e38c30, allocdist0_odd c30e38 RBstart 14, len 11 --> alloc 0 1ffc000, allocdist0_even 40e38c30, allocdist0_odd c30e38 RBstart 15, len 1 --> alloc 0 8000, allocdist0_even 200000, allocdist0_odd 200 RBstart 15, len 2 --> alloc 0 18000, allocdist0_even 200010, allocdist0_odd 10200 RBstart 15, len 3 --> alloc 0 38000, allocdist0_even 200410, allocdist0_odd 410200 RBstart 15, len 4 --> alloc 0 78000, allocdist0_even 210410, allocdist0_odd 410210 RBstart 15, len 5 --> alloc 0 f8000, allocdist0_even 610410, allocdist0_odd 410610 RBstart 15, len 6 --> alloc 0 1f8000, allocdist0_even 610430, allocdist0_odd 430610 RBstart 15, len 7 --> alloc 0 3f8000, allocdist0_even 610c30, allocdist0_odd c30610 RBstart 15, len 8 --> alloc 0 7f8000, allocdist0_even 630c30, allocdist0_odd c30630 RBstart 15, len 9 --> alloc 0 ff8000, allocdist0_even e30c30, allocdist0_odd c30e30 RBstart 15, len 10 --> alloc 0 1ff8000, allocdist0_even 40e30c30, allocdist0_odd c30e30 RBstart 16, len 1 --> alloc 0 10000, allocdist0_even 10, allocdist0_odd 10000 RBstart 16, len 2 --> alloc 0 30000, allocdist0_even 410, allocdist0_odd 410000 RBstart 16, len 3 --> alloc 0 70000, allocdist0_even 10410, allocdist0_odd 410010 RBstart 16, len 4 --> alloc 0 f0000, allocdist0_even 410410, allocdist0_odd 410410 RBstart 16, len 5 --> alloc 0 1f0000, allocdist0_even 410430, allocdist0_odd 430410 RBstart 16, len 6 --> alloc 0 3f0000, allocdist0_even 410c30, allocdist0_odd c30410 RBstart 16, len 7 --> alloc 0 7f0000, allocdist0_even 430c30, allocdist0_odd c30430 RBstart 16, len 8 --> alloc 0 ff0000, allocdist0_even c30c30, allocdist0_odd c30c30 RBstart 16, len 9 --> alloc 0 1ff0000, allocdist0_even 40c30c30, allocdist0_odd c30c30 RBstart 17, len 1 --> alloc 0 20000, allocdist0_even 400, allocdist0_odd 400000 RBstart 17, len 2 --> alloc 0 60000, allocdist0_even 10400, allocdist0_odd 400010 RBstart 17, len 3 --> alloc 0 e0000, allocdist0_even 410400, allocdist0_odd 400410 RBstart 17, len 4 --> alloc 0 1e0000, allocdist0_even 410420, allocdist0_odd 420410 RBstart 17, len 5 --> alloc 0 3e0000, allocdist0_even 410c20, allocdist0_odd c20410 RBstart 17, len 6 --> alloc 0 7e0000, allocdist0_even 430c20, allocdist0_odd c20430 RBstart 17, len 7 --> alloc 0 fe0000, allocdist0_even c30c20, allocdist0_odd c20c30 RBstart 17, len 8 --> alloc 0 1fe0000, allocdist0_even 40c30c20, allocdist0_odd c20c30 RBstart 18, len 1 --> alloc 0 40000, allocdist0_even 10000, allocdist0_odd 10 RBstart 18, len 2 --> alloc 0 c0000, allocdist0_even 410000, allocdist0_odd 410 RBstart 18, len 3 --> alloc 0 1c0000, allocdist0_even 410020, allocdist0_odd 20410 RBstart 18, len 4 --> alloc 0 3c0000, allocdist0_even 410820, allocdist0_odd 820410 RBstart 18, len 5 --> alloc 0 7c0000, allocdist0_even 430820, allocdist0_odd 820430 RBstart 18, len 6 --> alloc 0 fc0000, allocdist0_even c30820, allocdist0_odd 820c30 RBstart 18, len 7 --> alloc 0 1fc0000, allocdist0_even 40c30820, allocdist0_odd 820c30 RBstart 19, len 1 --> alloc 0 80000, allocdist0_even 400000, allocdist0_odd 400 RBstart 19, len 2 --> alloc 0 180000, allocdist0_even 400020, allocdist0_odd 20400 RBstart 19, len 3 --> alloc 0 380000, allocdist0_even 400820, allocdist0_odd 820400 RBstart 19, len 4 --> alloc 0 780000, allocdist0_even 420820, allocdist0_odd 820420 RBstart 19, len 5 --> alloc 0 f80000, allocdist0_even c20820, allocdist0_odd 820c20 RBstart 19, len 6 --> alloc 0 1f80000, allocdist0_even 40c20820, allocdist0_odd 820c20 RBstart 20, len 1 --> alloc 0 100000, allocdist0_even 20, allocdist0_odd 20000 RBstart 20, len 2 --> alloc 0 300000, allocdist0_even 820, allocdist0_odd 820000 RBstart 20, len 3 --> alloc 0 700000, allocdist0_even 20820, allocdist0_odd 820020 RBstart 20, len 4 --> alloc 0 f00000, allocdist0_even 820820, allocdist0_odd 820820 RBstart 20, len 5 --> alloc 0 1f00000, allocdist0_even 40820820, allocdist0_odd 820c20 RBstart 21, len 1 --> alloc 0 200000, allocdist0_even 800, allocdist0_odd 800000 RBstart 21, len 2 --> alloc 0 600000, allocdist0_even 20800, allocdist0_odd 800020 RBstart 21, len 3 --> alloc 0 e00000, allocdist0_even 820800, allocdist0_odd 800820 RBstart 21, len 4 --> alloc 0 1e00000, allocdist0_even 40820800, allocdist0_odd 800c20 RBstart 22, len 1 --> alloc 0 400000, allocdist0_even 20000, allocdist0_odd 20 RBstart 22, len 2 --> alloc 0 c00000, allocdist0_even 820000, allocdist0_odd 820 RBstart 22, len 3 --> alloc 0 1c00000, allocdist0_even 40820000, allocdist0_odd c20 RBstart 23, len 1 --> alloc 0 800000, allocdist0_even 800000, allocdist0_odd 800 RBstart 23, len 2 --> alloc 0 1800000, allocdist0_even 40800000, allocdist0_odd c00 RBstart 24, len 1 --> alloc 0 1000000, allocdist0_even 40000000, allocdist0_odd 400 nVRB 0 => nVRB_even_dist 0 rballoc =>(00000001.00000000.00000000.00000000) nVRB 1 => nVRB_even_dist 24 rballoc =>(01000001.00000000.00000000.00000000) nVRB 2 => nVRB_even_dist 48 rballoc =>(01000001.00010000.00000000.00000000) nVRB 3 => nVRB_even_dist 72 rballoc =>(01000001.00010000.00000100.00000000) nVRB 4 => nVRB_even_dist 1 rballoc =>(01000003.00010000.00000100.00000000) nVRB 5 => nVRB_even_dist 25 rballoc =>(03000003.00010000.00000100.00000000) nVRB 6 => nVRB_even_dist 49 rballoc =>(03000003.00030000.00000100.00000000) nVRB 7 => nVRB_even_dist 73 rballoc =>(03000003.00030000.00000300.00000000) PHY_vars_UE_g[0][0] = 0x7f50f287d010 CPU Freq is 3.592086 HW: Configuring card 0, nb_antennas_tx/rx 1/1 Card 0, channel 0, Setting tx_gain 0.000000, rx_gain 0.000000, tx_freq 875000000.000000, rx_freq 875000000.000000 Card 0, channel 1, Setting tx_gain 0.000000, rx_gain 0.000000, tx_freq 875000000.000000, rx_freq 875000000.000000 Card 0, channel 2, Setting tx_gain 0.000000, rx_gain 0.000000, tx_freq 875000000.000000, rx_freq 875000000.000000 Card 0, channel 3, Setting tx_gain 0.000000, rx_gain 0.000000, tx_freq 875000000.000000, rx_freq 875000000.000000 Setting the HW to USRP and initializing openair0 ... Checking for USRPs Found USRP B200-- Operating over USB 3. -- Detecting internal GPSDO.... Found an internal GPSDO -- Initialize CODEC control... -- Initialize Radio control... -- Performing register loopback test... pass -- Performing register loopback test... pass -- Performing CODEC loopback test... pass -- Performing CODEC loopback test... pass -- Asking for clock rate 32.000000 MHz... -- Actually got clock rate 32.000000 MHz. -- Performing timer loopback test... pass -- Performing timer loopback test... pass -- Setting master clock rate selection to 'automatic'. -- Setting references to the internal GPSDO -- Initializing time to the internal GPSDO -- Asking for clock rate 30.720000 MHz... -- Actually got clock rate 30.720000 MHz. -- Performing timer loopback test... pass -- Performing timer loopback test... pass Setting rx freq/gain on channel 0/2 -- Tune Request: 875.000000 MHz -- The RF LO does not support the requested frequency: -- Requested LO Frequency: 875.000000 MHz -- RF LO Result: 874.999999 MHz -- Attempted to use the DSP to reach the requested frequency: -- Desired DSP Frequency: -0.000001 MHz -- DSP Result: -0.000001 MHz -- Successfully tuned to 875.000000 MHz -- cal 0: freq 3500000000.000000, offset 46.000000, diff 2625000000.000000 cal 1: freq 2660000000.000000, offset 53.000000, diff 1785000000.000000 cal 2: freq 2300000000.000000, offset 54.000000, diff 1425000000.000000 cal 3: freq 1880000000.000000, offset 55.000000, diff 1005000000.000000 cal 4: freq 816000000.000000, offset 62.000000, diff 59000000.000000 RX Gain 0 86.000000 (62.000000) => 24.000000 (max 76.000000) Setting tx freq/gain on channel 0/2 -- Tune Request: 875.000000 MHz -- The RF LO does not support the requested frequency: -- Requested LO Frequency: 875.000000 MHz -- RF LO Result: 874.999999 MHz -- Attempted to use the DSP to reach the requested frequency: -- Desired DSP Frequency: 0.000001 MHz -- DSP Result: 0.000001 MHz -- Successfully tuned to 875.000000 MHz -- Actual master clock: 30.720000MHz... rx_max_num_samps 2044 tx_max_num_samps 2044 RX Channel 0 Actual RX sample rate: 7.680000MSps... Actual RX frequency: 0.875000GHz... Actual RX gain: 24.000000... Actual RX bandwidth: 2.500000M... Actual RX antenna: RX2... TX Channel 0 Actual TX sample rate: 7.680000MSps... Actual TX frequency: 0.875000GHz... Actual TX gain: 70.000000... Actual TX bandwidth: 2.500000M... Actual TX antenna: TX/RX... Device timestamp: 0.000442... Done [MAC][I][l2_init] [MAIN] MAC_INIT_GLOBAL_PARAM IN... [MAC][I][mac_init_global_param] [MAIN] CALLING RLC_MODULE_INIT... [MAC][I][mac_init_global_param] [MAIN] RLC_MODULE_INIT OK, malloc16 for mac_rlc_xface... [MAC][I][mac_init_global_param] [MAIN] malloc16 OK, mac_rlc_xface @ 0x17376730 [MAC][I][mac_init_global_param] [MAIN] RLC interface setup and init [PDCP][I][pdcp_layer_init] PDCP layer has been initialized [MAC][I][mac_init_global_param] [MAIN] Init Global Param Done [MAC][I][l2_init] [MAIN] init eNB MAC functions [MAC][I][l2_init] [MAIN] init UE MAC functions [MAC][I][l2_init] [MAIN] PHY Frame configuration [MAC][I][mac_top_init] [MAIN] Init function start:Nb_UE_INST=1 [MAC][I][ue_init_mac] [UE0] Applying default macMainConfig [MAC][I][mac_top_init] [MAIN] Init function start:Nb_eNB_INST=0 [MAC][I][mac_top_init] [MAIN] calling RRC [RRC][I][fill_ue_capability] Allocating 408 bytes for UE_EUTRA_Capability [PHY][I][fill_ue_capability] [RRC]UE Capability encoded, 15 bytes (120 bits) [RRC][I][openair_rrc_top_init] [UE] eMBMS active state is 0 [MAC][I][mac_top_init] [MAIN][INIT] Init function finished ITTI tasks created Filling UE band info Band 3 (3) : DL 1805000000..1880000000 Hz, UL 1710000000..1785000000 Hz, Duplex FDD Band 20 (20) : DL 791000000..821000000 Hz, UL 832000000..862000000 Hz, Duplex FDD Band 7 (7) : DL 2620000000..2690000000 Hz, UL 2500000000..2570000000 Hz, Duplex FDD Band 38 (38) : DL 2570000000..2630000000 Hz, UL 2570000000..2620000000 Hz, Duplex TDD [RRC][I][openair_rrc_lite_ue_init] [FRAME 00000][ UE][MOD 00][RNTI 0] Init... [RRC][I][openair_rrc_on] [FRAME 00000][ UE][MOD 00][RNTI 0] OPENAIR RRC IN.... Mapping UE CC_id 0, rx_ant 0, freq 875000000 on card 0, chain 0 Mapping UE CC_id 0, tx_ant 0, freq 875000000 on card 0, chain 0 Setting UE buffer to all-RX Intializing UE Threads ... waiting for sync (UE_thread_tx) Locked sync_mutex, waiting (UE_thread_tx) waiting for sync (UE_thread_rx) Locked sync_mutex, waiting (UE_thread_rx) UE_thread_sync in with PHY_vars_UE 0x7f50f287d010 waiting for sync (UE_thread_synch) Locked sync_mutex, waiting (UE_sync_thread) [HW][I][UE_thread] [SCHED][eNB] eNB main deadline thread 14436 started on CPU 4 UE threads created waiting for sync (UE_thread) Locked sync_mutex, waiting (UE_thread) TYPE TO TERMINATE Entering ITTI signals handler unlocked sync_mutex, waiting (UE_thread_tx) Starting UE TX thread unlocked sync_mutex, waiting (UE_thread_rx) Starting UE RX thread unlocked sync_mutex, waiting (UE_thread) starting UE thread unlocked sync_mutex (UE_sync_thread) starting UE synch thread (IC -1) Scanning band 1, dl_min 2110000000, ul_min 1920000000 Scanning band 2, dl_min 1930000000, ul_min 1850000000 Scanning band 3, dl_min 1805000000, ul_min 1710000000 Scanning band 4, dl_min 2110000000, ul_min 1710000000 Scanning band 5, dl_min 869000000, ul_min 824000000 [PHY][I][UE_thread_synch] [SCHED][UE] Check absolute frequency DL 875000000, UL 830000000 (oai_exit 0) [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 [PHY][I][initial_sync] [UE0] Initial sync : Estimated PSS position 11252, Nid2 1 [PHY][I][initial_sync] [UE0] Initial sync : Estimated power: 40 dB [PHY][I][initial_sync] Calling sss detection (FDD normal CP) [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 [PHY][I][pbch_detection] [UE0] Initial sync: starting PBCH detection (rx_offset 7924) [PHY][I][pbch_detection] [UE 0] RX RSSI -33 dBm, digital (47, 0) dB, linear (55232, 0), avg rx power 47 dB (55232 lin), RX gain 80 dB [PHY][I][pbch_detection] [UE 0] N0 -91 dBm digital (16, 0) dB, linear (476, 0), avg noise power 0 dB (0 lin) [PHY][I][pbch_detection] [UE0] Initial sync: pbch decoded sucessfully mode1_flag 1, tx_ant 1, frame 786, N_RB_DL 25, phich_duration 0, phich_resource 1/6! [PHY][I][initial_sync] FDD Normal prefix: CellId 10 metric 63, phase 4, flip 0, pbch 0 [PHY][I][initial_sync] [UE0] In synch, rx_offset 7924 samples [PHY][I][initial_sync] [UE 0] Frame 786 RRC Measurements => rssi -35.0 dBm (dig 45.0 dB, gain 80), N0 -91 dBm, rsrp -59.7 dBm/RE, rsrq 9.0 dB [PHY][I][initial_sync] [UE 0] Frame 786 MIB Information => FDD, NORMAL, NidCell 10, N_RB_DL 25, PHICH DURATION 0, PHICH RESOURCE 1/6, TX_ANT 1 [PHY][I][initial_sync] [UE 0] Frame 786 Measured Carrier Frequency 875000125 Hz (offset -125 Hz) [HW][I][UE_thread_synch] Got synch: hw_slot_offset 2 -- Tune Request: 830.000125 MHz -- The RF LO does not support the requested frequency: -- Requested LO Frequency: 830.000125 MHz -- RF LO Result: 830.000124 MHz -- Attempted to use the DSP to reach the requested frequency: -- Desired DSP Frequency: 0.000001 MHz -- DSP Result: 0.000001 MHz -- Successfully tuned to 830.000125 MHz -- -- Tune Request: 875.000125 MHz -- The RF LO does not support the requested frequency: -- Requested LO Frequency: 875.000125 MHz -- RF LO Result: 875.000125 MHz -- Attempted to use the DSP to reach the requested frequency: -- Desired DSP Frequency: -0.000000 MHz -- DSP Result: -0.000000 MHz -- Successfully tuned to 875.000125 MHz -- Setting USRP RX gain to 18.000000 [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 [PHY][I][initial_sync] [UE0] Initial sync : Estimated PSS position 11252, Nid2 1 [PHY][I][initial_sync] [UE0] Initial sync : Estimated power: 35 dB [PHY][I][initial_sync] Calling sss detection (FDD normal CP) [PHY][I][init_frame_parms] Initializing frame parms for N_RB_DL 25, Ncp 0, osf 1 lte_parms.c: Setting N_RB_DL to 25, ofdm_symbol_size 512 [PHY][I][pbch_detection] [UE0] Initial sync: starting PBCH detection (rx_offset 7924) [PHY][I][pbch_detection] [UE 0] RX RSSI -33 dBm, digital (42, 0) dB, linear (16576, 0), avg rx power 47 dB (54326 lin), RX gain 80 dB [PHY][I][pbch_detection] [UE 0] N0 -96 dBm digital (11, 0) dB, linear (160, 0), avg noise power 10 dB (11 lin) [PHY][I][pbch_detection] [UE0] Initial sync: pbch decoded sucessfully mode1_flag 1, tx_ant 1, frame 890, N_RB_DL 25, phich_duration 0, phich_resource 1/6! [PHY][I][initial_sync] FDD Normal prefix: CellId 10 metric 55, phase 4, flip 0, pbch 0 [PHY][I][initial_sync] [UE0] In synch, rx_offset 7924 samples [PHY][I][initial_sync] [UE0] Sending synch status to higher layers [RRC][I][openair_rrc_lite_ue_init] [FRAME 00000][ UE][MOD 00][RNTI 0] Init... [RRC][I][openair_rrc_on] [FRAME 00000][ UE][MOD 00][RNTI 0] OPENAIR RRC IN.... pcfich_reg : 10,22,35,47 Ngroup_PHICH 1 (phich_config_common.phich_resource 1,phich_config_common.phich_duration normal, NidCell 10,Ncp 0, frame_type 0), smallest pcfich REG 10, n0 46, n1 75 (first PHICH REG 10) phich_reg :0 => 11,27,43 [PHY][I][initial_sync] [UE 0] Frame 890 RRC Measurements => rssi -40.5 dBm (dig 39.5 dB, gain 80), N0 -96 dBm, rsrp -65.2 dBm/RE, rsrq 9.0 dB [PHY][I][initial_sync] [UE 0] Frame 890 MIB Information => FDD, NORMAL, NidCell 10, N_RB_DL 25, PHICH DURATION 0, PHICH RESOURCE 1/6, TX_ANT 1 [PHY][I][initial_sync] [UE 0] Frame 890 Measured Carrier Frequency 875000125 Hz (offset 0 Hz) [HW][I][UE_thread_synch] Got synch: hw_slot_offset 2 [PHY][I][lte_ue_pbch_procedures] [UE 0] frame 890, slot 1: Adjusting frame counter (PBCH ant_tx=1, frame_tx=893, phase 1). [RRC][I][decode_SIB1] [UE 0] : Dumping SIB 1 [RRC][I][decode_SIB1] PLMN MCC 502, MNC 11, TAC 0x2711 [RRC][I][decode_SIB1] cellReservedForOperatorUse : raw:1 decoded:notReserved [RRC][I][decode_SIB1] Found Unknown operator (no entry in internal table) [RRC][I][decode_SIB1] cellAccessRelatedInfo.cellIdentity : raw:3584 decoded:00.00.e0.00 [RRC][I][decode_SIB1] cellAccessRelatedInfo.cellBarred : raw:1 decoded:notBarred [RRC][I][decode_SIB1] cellAccessRelatedInfo.intraFreqReselection : raw:1 decoded:notAllowed [RRC][I][decode_SIB1] cellAccessRelatedInfo.csg_Indication : 0 [RRC][I][decode_SIB1] cellAccessRelatedInfo.csg_Identity : not defined [RRC][I][decode_SIB1] cellSelectionInfo.q_RxLevMin : -65 [RRC][I][decode_SIB1] cellSelectionInfo.q_RxLevMinOffset : not defined [RRC][I][decode_SIB1] p_Max : not defined [RRC][I][decode_SIB1] freqBandIndicator : 5 [RRC][I][decode_SIB1] si_Periodicity[0] : rf8 [RRC][I][decode_SIB1] siSchedulingInfoSIBType[0] : SIB3 [RRC][I][decode_SIB1] siWindowLength : 20ms [RRC][I][decode_SIB1] systemInfoValueTag : 0 [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Configuring MAC/PHY from eNB 0 [RRC][I][decode_SI] [UE 0] Frame 897 Found SIB2 from eNB 0 [RRC][I][dump_sib2] ac_BarringInfo : not defined [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.preambleInfo.numberOfRA_Preambles : raw:15 decoded:n64 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.preambleInfo.preamblesGroupAConfig : not defined [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.powerRampingParameters.powerRampingStep : raw:2 decoded:dB4 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.powerRampingParameters.preambleInitialReceivedTargetPower : raw:6 decoded:dBm-108 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.preambleTransMax : raw:6 decoded:n10 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.ra_ResponseWindowSize : raw:7 decoded:sf10 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.ra_SupervisionInfo.mac_ContentionResolutionTimer : raw:5 decoded:sf48 [RRC][I][dump_sib2] radioResourceConfigCommon.rach_ConfigCommon.maxHARQ_Msg3Tx : 4 [RRC][I][dump_sib2] radioResourceConfigCommon.bcch_Config.modificationPeriodCoeff : raw:0 decoded:n2 [RRC][I][dump_sib2] radioResourceConfigCommon.pcch_Config.defaultPagingCycle : raw:2 decoded:rf64 [RRC][I][dump_sib2] radioResourceConfigCommon.pcch_Config.nB : raw:2 decoded:oneT [RRC][I][dump_sib2] radioResourceConfigCommon.prach_Config.rootSequenceIndex : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.prach_Config.prach_ConfigInfo.prach_ConfigIndex : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.prach_Config.prach_ConfigInfo.highSpeedFlag : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.prach_Config.prach_ConfigInfo.zeroCorrelationZoneConfig : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.prach_Config.prach_ConfigInfo.prach_FreqOffset : 2 [RRC][I][dump_sib2] radioResourceConfigCommon.pdsch_ConfigCommon.referenceSignalPower : -26 [RRC][I][dump_sib2] radioResourceConfigCommon.pdsch_ConfigCommon.p_b : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.pusch_ConfigBasic.n_SB : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.pusch_ConfigBasic.hoppingMode : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.pusch_ConfigBasic.pusch_HoppingOffset : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.pusch_ConfigBasic.enable64QAM : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.ul_ReferenceSignalsPUSCH.groupHoppingEnabled : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.ul_ReferenceSignalsPUSCH.groupAssignmentPUSCH : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.ul_ReferenceSignalsPUSCH.sequenceHoppingEnabled : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pusch_ConfigCommon.ul_ReferenceSignalsPUSCH.cyclicShift : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.pucch_ConfigCommon.deltaPUCCH_Shift : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pucch_ConfigCommon.nRB_CQI : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.pucch_ConfigCommon.nCS_AN : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.pucch_ConfigCommon.n1PUCCH_AN : 0 [RRC][I][dump_sib2] radioResourceConfigCommon.soundingRS_UL_ConfigCommon.present : raw:1 decoded:release [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.p0_NominalPUSCH : -80 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.alpha : 7 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.p0_NominalPUCCH : -108 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaFList_PUCCH.deltaF_PUCCH_Format1 : 2 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaFList_PUCCH.deltaF_PUCCH_Format1b : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaFList_PUCCH.deltaF_PUCCH_Format2 : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaFList_PUCCH.deltaF_PUCCH_Format2a : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaFList_PUCCH.deltaF_PUCCH_Format2b : 1 [RRC][I][dump_sib2] radioResourceConfigCommon.uplinkPowerControlCommon.deltaPreambleMsg3 : 6 [RRC][I][dump_sib2] radioResourceConfigCommon.ul_CyclicPrefixLength : 0 [RRC][I][dump_sib2] ue_TimersAndConstants.t300 : 5 [RRC][I][dump_sib2] ue_TimersAndConstants.t301 : 5 [RRC][I][dump_sib2] ue_TimersAndConstants.t310 : 5 [RRC][I][dump_sib2] ue_TimersAndConstants.n310 : 7 [RRC][I][dump_sib2] ue_TimersAndConstants.t311 : 3 [RRC][I][dump_sib2] ue_TimersAndConstants.n311 : 0 [RRC][I][dump_sib2] freqInfo.ul_CarrierFreq : not defined [RRC][I][dump_sib2] freqInfo.ul_Bandwidth : not defined [RRC][I][dump_sib2] freqInfo.additionalSpectrumEmission : 1 [RRC][I][dump_sib2] mbsfn_SubframeConfigList : not defined [RRC][I][dump_sib2] timeAlignmentTimerCommon : 7 [RRC][I][dump_sib2] lateNonCriticalExtension : not defined [RRC][I][dump_sib2] ssac_BarringForMMTEL_Voice_r9 : not defined [RRC][I][dump_sib2] ssac_BarringForMMTEL_Video_r9 : not defined [RRC][I][dump_sib2] ac_BarringForCSFB_r10 : not defined [RRC][I][decode_SI] [FRAME 00897][RRC_UE][MOD 00][][--- MAC_CONFIG_REQ (SIB2 params eNB 0) --->][MAC_UE][MOD 00][] [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Configuring MAC/PHY from eNB 0 [PHY][I][phy_config_sib2_ue] [UE0] Frame 897: Applying radioResourceConfigCommon from eNB0 [RRC][I][rrc_ue_generate_RRCConnectionRequest] [UE 0] : Frame 897, Logical Channel UL-CCCH (SRB0), Generating RRCConnectionRequest (bytes 6, eNB 0) [RRC][I][decode_SI] [UE 0] Received SIB1/SIB2/SIB3 Switching to RRC_SI_RECEIVED [RRC][I][decode_SI] [UE 0] Frame 897 Found SIB3 from eNB 0 [RRC][I][dump_sib3] Dumping SIB3 (see TS36.331 V8.21.0) [RRC][I][dump_sib3] cellReselectionInfoCommon.q_Hyst : raw:4 decoded:4 dB [RRC][I][dump_sib3] cellReselectionInfoCommon.speedStateReselectionPars : not defined [RRC][I][dump_sib3] cellReselectionServingFreqInfo.s_NonIntraSearch : not defined [RRC][I][dump_sib3] cellReselectionServingFreqInfo.threshServingLow : 31 [RRC][I][dump_sib3] cellReselectionServingFreqInfo.cellReselectionPriority : 7 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.q_RxLevMin : -70 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.p_Max : not defined [RRC][I][dump_sib3] intraFreqCellReselectionInfo.s_IntraSearch : 31 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.allowedMeasBandwidth : 0 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.presenceAntennaPort1 : 0 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.neighCellConfig : 0 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.t_ReselectionEUTRA : 1 [RRC][I][dump_sib3] intraFreqCellReselectionInfo.t_ReselectionEUTRA_SF : not defined [RRC][I][decode_SI] SIStatus 7, SIcnt 1/1 [MAC][I][ue_scheduler] Received RRC_MAC_CCCH_DATA_REQ from TASK_RRC_UE: instance 0, frameP 898, eNB_index 0 [MAC][I][ue_process_rar] [eNB 0][RAPROC] Frame 898 Received RAR (66|00.30.03.4c.fd.ab) for preamble 38/38 [MAC][I][ue_process_rar] [UE 0][RAPROC] rar->Timing_Advance_Command 3 [MAC][I][ue_process_rar] [UE 0][RAPROC] rar->t_crnti fdab [PHY][I][phy_procedures_UE_TX] [UE 0][RAPROC] Frame 899, Subframe 0 next slot 0 Generating (RRCConnectionRequest) Msg3 (nb_rb 1, first_rb 1, round 0, rvidx 0) Msg3: 20.6.1f|52.bd.12.ed.4d.56 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 0/48 [PHY][I][pusch_power_cntl] [UE 0][RAPROC] frame 899, subframe 0: Msg3 Po_PUSCH -63 dBm (-10800,0,100*PL=4300,0,200) [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 1/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 2/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 3/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 4/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 5/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 6/48 [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 7/48 [PHY][I][pusch_power_cntl] [UE 0][RAPROC] frame 899, subframe 8: Msg3 Po_PUSCH -64 dBm (-10800,0,100*PL=4200,0,200) [MAC][I][ue_scheduler] Frame 899: Contention resolution timer 8/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 9/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 10/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 11/48 [PHY][I][phy_procedures_UE_TX] [UE 0][RAPROC] Frame 900, Subframe 2 next slot 4 Generating (RRCConnectionRequest) Msg3 (nb_rb 1, first_rb 1, round 0, rvidx 0) Msg3: 20.6.1f|52.bd.12.ed.4d.56 [PHY][I][pusch_power_cntl] [UE 0][RAPROC] frame 900, subframe 2: Msg3 Po_PUSCH -63 dBm (-10800,0,100*PL=4300,0,200) [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 0/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 1/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 2/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 3/48 [PHY][I][pusch_power_cntl] [UE 0][RAPROC] frame 900, subframe 6: Msg3 Po_PUSCH -63 dBm (-10800,0,100*PL=4300,0,200) [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 4/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 5/48 [MAC][I][ue_scheduler] Frame 900: Contention resolution timer 6/48 [MAC][I][ue_scheduler] Frame 901: Contention resolution timer 7/48 [PHY][I][pusch_power_cntl] [UE 0][RAPROC] frame 901, subframe 0: Msg3 Po_PUSCH -63 dBm (-10800,0,100*PL=4300,0,200) [MAC][I][ue_scheduler] Frame 901: Contention resolution timer 8/48 [MAC][I][ue_scheduler] Frame 901: Contention resolution timer 9/48 [MAC][I][ue_scheduler] Frame 901: Contention resolution timer 10/48 [MAC][I][ue_send_sdu] [UE 0][RAPROC] Frame 901 : received contention resolution msg: 52.bd.12.ed.4d.56, Terminating RA procedure [MAC][I][ue_send_sdu] [UE 0][RAPROC] Frame 901 : Clearing RA_active flag [MAC][I][ue_send_sdu] [UE 0][RAPROC] Frame 901 : Clearing contention resolution timer [PHY][I][ra_succeeded] [UE 0][RAPROC] Frame 901 Random-access procedure succeeded [RRC][I][rrc_ue_decode_ccch] [UE0][RAPROC] Frame 901 : Logical Channel DL-CCCH (SRB0), Received RRCConnectionSetup RNTI fdab [RLC][I][rrc_rlc_add_rlc] [FRAME 00901][ UE][MOD 00][RNTI fdab] [SRB 1] rrc_rlc_add_rlc SRB [RLC][I][rlc_am_configure] [FRAME 00901][ UE][MOD 00][RNTI fdab][SRB AM 01][CONFIGURE] max_retx_threshold 8 poll_pdu 4 poll_byte 10000 t_poll_retransmit 80 t_reordering 35 t_status_prohibit 0 [RRC][I][rrc_ue_establish_srb1] [UE 0], CONFIG_SRB1 1 corresponding to eNB_index 0 [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Configuring MAC/PHY from eNB 0 [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Applying RRC logicalChannelConfig from eNB0 [RRC][I][rrc_ue_process_radioResourceConfigDedicated] [UE 0] State = RRC_CONNECTED (eNB 0) [RRC][I][rrc_ue_generate_RRCConnectionSetupComplete] [UE 0][RAPROC] Frame 901 : Logical Channel UL-DCCH (SRB1), Generating RRCConnectionSetupComplete (bytes59, eNB 0) [RLC][I][rlc_am_data_req] [FRAME 00901][ UE][MOD 00][RNTI fdab][SRB AM 01] RLC_AM_DATA_REQ size 64 Bytes, NB SDU 1 current_sdu_index=0 next_sdu_index=1 conf 0 mui 0 [PHY][I][pucch_power_cntl] [UE 0][SR fdab] frame 902, subframe 0: Po_PUCCH -63 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB g_pucch 0 dB [PHY][I][pucch_power_cntl] [UE 0][SR fdab] frame 910, subframe 0: Po_PUCCH -63 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB g_pucch 0 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][process_timing_advance] [UE 0] Got timing advance 7 from MAC, new value 40 [PHY][I][process_timing_advance] [UE 0] Got timing advance 7 from MAC, new value 68 n1_pucch_UE: subframe 8, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 911, subframe 2: Po_PUCCH -64 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -2 dB [PHY][I][process_timing_advance] [UE 0] Got timing advance 7 from MAC, new value 96 [RRC][N][rrc_lite_data_ind] [UE 0] Frame 911: received a DCCH 1 message on SRB 0 with Size 5 from eNB ??? [RRC][I][rrc_ue_decode_dcch] [UE 0] Received securityModeCommand (eNB 0) [RRC][I][rrc_ue_process_securityModeCommand] [UE 0] Frame 911: Receiving from SRB1 (DL-DCCH), Processing securityModeCommand (eNB 0) [RRC][I][rrc_ue_process_securityModeCommand] [UE 0] Security algorithm is set to eea0 [RRC][I][rrc_ue_process_securityModeCommand] [UE 0] Integrity protection algorithm is set to none [RRC][I][rrc_ue_process_securityModeCommand] [UE 0] Frame 911: Receiving from SRB1 (DL-DCCH), encoding securityModeComplete (eNB 0) [RLC][I][rlc_am_data_req] [FRAME 00911][ UE][MOD 00][RNTI fdab][SRB AM 01] RLC_AM_DATA_REQ size 7 Bytes, NB SDU 1 current_sdu_index=1 next_sdu_index=2 conf 0 mui 1 [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][process_timing_advance] [UE 0] Got timing advance 2 from MAC, new value 104 n1_pucch_UE: subframe 6, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 913, subframe 0: Po_PUCCH -66 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -4 dB [PHY][I][process_timing_advance] [UE 0] Got timing advance -1 from MAC, new value 100 [PHY][I][process_timing_advance] [UE 0] Got timing advance -1 from MAC, new value 96 [RRC][N][rrc_lite_data_ind] [UE 0] Frame 912: received a DCCH 1 message on SRB 0 with Size 5 from eNB ??? [RRC][I][rrc_ue_decode_dcch] [UE 0] Received Capability Enquiry (eNB 0) [RRC][I][rrc_ue_process_ueCapabilityEnquiry] [UE 0] Frame 912: Receiving from SRB1 (DL-DCCH), Processing UECapabilityEnquiry (eNB 0) [RLC][I][rlc_am_data_req] [FRAME 00912][ UE][MOD 00][RNTI fdab][SRB AM 01] RLC_AM_DATA_REQ size 24 Bytes, NB SDU 1 current_sdu_index=2 next_sdu_index=3 conf 0 mui 2 n1_pucch_UE: subframe 8, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 913, subframe 2: Po_PUCCH -66 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -4 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][pucch_power_cntl] [UE 0][SR fdab] frame 914, subframe 0: Po_PUCCH -69 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB g_pucch -6 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][pucch_power_cntl] [UE 0][SR fdab] frame 922, subframe 0: Po_PUCCH -71 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB g_pucch -8 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][process_timing_advance] [UE 0] Got timing advance -12 from MAC, new value 48 n1_pucch_UE: subframe 7, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 924, subframe 1: Po_PUCCH -72 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -10 dB [PHY][I][process_timing_advance] [UE 0] Got timing advance -12 from MAC, new value 0 n1_pucch_UE: subframe 8, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 924, subframe 2: Po_PUCCH -72 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -10 dB [PHY][I][process_timing_advance] [UE 0] Got timing advance -12 from MAC, new value -48 [RRC][N][rrc_lite_data_ind] [UE 0] Frame 924: received a DCCH 1 message on SRB 0 with Size 20 from eNB ??? [RRC][I][rrc_ue_process_rrcConnectionReconfiguration] [UE 0] Frame 924: Receiving from SRB1 (DL-DCCH), Processing RRCConnectionReconfiguration (eNB 0) [RRC][I][rrc_ue_process_rrcConnectionReconfiguration] Radio Resource Configuration is present [RLC][I][rrc_rlc_add_rlc] [FRAME 00924][ UE][MOD 00][RNTI fdab] [DRB 1] rrc_rlc_add_rlc DRB [RRC][I][rrc_ue_establish_drb] [UE 0] Frame 924: processing RRCConnectionReconfiguration: reconfiguring DRB 1/LCID 3 [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Configuring MAC/PHY from eNB 0 [MAC][I][rrc_mac_config_req] [CONFIG][UE 0] Applying RRC logicalChannelConfig from eNB0 [MAC][I][rrc_mac_config_req] [CONFIG][UE0] Applying RRC macMainConfig from eNB0 [RRC][I][rrc_ue_process_radioResourceConfigDedicated] [UE 0] State = RRC_CONNECTED (eNB 0) [RRC][I][rrc_ue_generate_RRCConnectionReconfigurationComplete] [FRAME 00924][ UE][MOD 00][RNTI fdab] Logical Channel UL-DCCH (SRB1), Generating RRCConnectionReconfigurationComplete (bytes 2, eNB_index 0) [RRC][I][rrc_ue_decode_dcch] [UE 0] State = RRC_RECONFIGURED (eNB 0) [RLC][I][rlc_am_data_req] [FRAME 00924][ UE][MOD 00][RNTI fdab][SRB AM 01] RLC_AM_DATA_REQ size 7 Bytes, NB SDU 1 current_sdu_index=3 next_sdu_index=4 conf 0 mui 3 [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][process_timing_advance] [UE 0] Got timing advance 20 from MAC, new value 32 n1_pucch_UE: subframe 7, nCCE 0 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 935, subframe 1: Po_PUCCH -74 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -12 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 3, dlsch0_harq->delta_PUCCH 3 n1_pucch_UE: subframe 6, nCCE 1 [PHY][I][pucch_power_cntl] [UE 0][PDSCH fdab] frame 1310, subframe 0: Po_PUCCH -68 dBm : Po_NOMINAL_PUCCH -108 dBm, PL 43 dB, g_pucch -6 dB [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][generate_ue_dlsch_params_from_dci] format1 TPC 0, dlsch0_harq->delta_PUCCH -1 [PHY][I][process_timing_advance] [UE 0] Got timing advance 3 from MAC, new value 44 [PHY][E][generate_ue_dlsch_params_from_dci] Format 1A: harq_pid > 1 [PHY][E][lte_ue_pdcch_procedures] [UE 0] Frame 2779, subframe 7: Problem in DCI!