defs.h 34 KB
Newer Older
1
/*******************************************************************************
2 3
    OpenAirInterface
    Copyright(c) 1999 - 2014 Eurecom
4

5 6 7 8
    OpenAirInterface is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
9 10


11 12 13 14
    OpenAirInterface is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
15

16 17 18 19
    You should have received a copy of the GNU General Public License
    along with OpenAirInterface.The full GNU General Public License is
    included in this distribution in the file called "COPYING". If not,
    see <http://www.gnu.org/licenses/>.
20 21

  Contact Information
22 23
  OpenAirInterface Admin: openair_admin@eurecom.fr
  OpenAirInterface Tech : openair_tech@eurecom.fr
24
  OpenAirInterface Dev  : openair4g-devel@lists.eurecom.fr
25

ghaddab's avatar
ghaddab committed
26
  Address      : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE
27 28

*******************************************************************************/
29
/*! \file LAYER2/MAC/defs.h
30
* \brief MAC data structures, constant, and function prototype
31
* \author Navid Nikaein and Raymond Knopp
32 33
* \date 2011
* \version 0.5
34
* \email navid.nikaein@eurecom.fr
35 36

*/
37 38 39 40
/** @defgroup _oai2  openair2 Reference Implementation
 * @ingroup _ref_implementation_
 * @{
 */
41

42
/*@}*/
43

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
#ifndef __LAYER2_MAC_DEFS_H__
#define __LAYER2_MAC_DEFS_H__



#ifdef USER_MODE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif

//#include "COMMON/openair_defs.h"

#include "COMMON/platform_constants.h"
#include "COMMON/mac_rrc_primitives.h"
#include "PHY/defs.h"
#include "RadioResourceConfigCommon.h"
#include "RadioResourceConfigDedicated.h"
#include "MeasGapConfig.h"
#include "TDD-Config.h"
#include "RACH-ConfigCommon.h"
#include "MeasObjectToAddModList.h"
66
#include "MobilityControlInfo.h"
67 68 69 70
#ifdef Rel10
#include "MBSFN-AreaInfoList-r9.h"
#include "MBSFN-SubframeConfigList.h"
#include "PMCH-InfoList-r9.h"
knopp's avatar
knopp committed
71
#include "SCellToAddMod-r10.h"
72 73 74 75 76 77
#endif

//#ifdef PHY_EMUL
//#include "SIMULATION/PHY_EMULATION/impl_defs.h"
//#endif

78 79
/** @defgroup _mac  MAC
 * @ingroup _oai2
80 81 82
 * @{
 */

83
#define BCCH_PAYLOAD_SIZE_MAX 128
84
#define CCCH_PAYLOAD_SIZE_MAX 128
85
#define PCCH_PAYLOAD_SIZE_MAX 128
86

87 88 89 90 91
#define SCH_PAYLOAD_SIZE_MAX 4096
/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB)

#ifdef Rel10

92
// Mask for identifying subframe for MBMS
93 94 95 96 97 98 99 100 101 102 103 104 105 106
#define MBSFN_TDD_SF3 0x80// for TDD
#define MBSFN_TDD_SF4 0x40
#define MBSFN_TDD_SF7 0x20
#define MBSFN_TDD_SF8 0x10
#define MBSFN_TDD_SF9 0x08
#define MBSFN_FDD_SF1 0x80// for FDD
#define MBSFN_FDD_SF2 0x40
#define MBSFN_FDD_SF3 0x20
#define MBSFN_FDD_SF6 0x10
#define MBSFN_FDD_SF7 0x08
#define MBSFN_FDD_SF8 0x04

#define MAX_MBSFN_AREA 8
#define MAX_PMCH_perMBSFN 15
107
/*!\brief MAX MCCH payload size  */
108
#define MCCH_PAYLOAD_SIZE_MAX 128
109
//#define MCH_PAYLOAD_SIZE_MAX 16384// this value is using in case mcs and TBS index are high
110 111 112 113 114 115
#endif

#ifdef USER_MODE
#define printk printf
#endif //USER_MODE

116
/*!\brief Maximum number of logical channl group IDs */
117
#define MAX_NUM_LCGID 4
118 119 120 121 122 123 124 125 126
/*!\brief logical channl group ID 0 */
#define LCGID0 0
/*!\brief logical channl group ID 1 */
#define LCGID1 1
/*!\brief logical channl group ID 2 */
#define LCGID2 2
/*!\brief logical channl group ID 3 */
#define LCGID3 3
/*!\brief Maximum number of logical chanels */
127
#define MAX_NUM_LCID 11
128
/*!\brief Maximum number od control elemenets */
129
#define MAX_NUM_CE 5
130
/*!\brief Maximum number of random access process */
131
#define NB_RA_PROC_MAX 4
132
/*!\brief size of buffer status report table */
133
#define BSR_TABLE_SIZE 64
134
/*!\brief The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1 */
135
#define PHR_MAPPING_OFFSET 23  // if ( x>= -23 ) val = floor (x + 23) 
136
/*!\brief maximum number of resource block groups */
137
#define N_RBG_MAX 25 // for 20MHz channel BW
138
/*!\brief minimum value for channel quality indicator */
139
#define MIN_CQI_VALUE  0
140
/*!\brief maximum value for channel quality indicator */
141 142
#define MAX_CQI_VALUE  15

143

144 145 146
#define LCID_EMPTY 0
#define LCID_NOT_EMPTY 1

147 148 149
/* 
 * eNB part 
 */ 
150

151 152 153 154 155

/* 
 * UE/ENB common part 
 */ 
/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */
156
typedef struct {
157 158 159
  uint8_t RAPID:6;
  uint8_t T:1;
  uint8_t E:1;
160 161
} __attribute__((__packed__))RA_HEADER_RAPID;

162
/*!\brief  MAC header of Random Access Response for backoff indicator (BI)*/
163
typedef struct {
164 165 166 167
  uint8_t BI:4;
  uint8_t R:2;
  uint8_t T:1;
  uint8_t E:1;
168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197
} __attribute__((__packed__))RA_HEADER_BI;
/*
typedef struct {
  uint64_t padding:16;
  uint64_t t_crnti:16;
  uint64_t hopping_flag:1;
  uint64_t rb_alloc:10;
  uint64_t mcs:4;
  uint64_t TPC:3;
  uint64_t UL_delay:1;
  uint64_t cqi_req:1;
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t R:1;                        // octet MSB
  } __attribute__((__packed__))RAR_PDU;

typedef struct {
  uint64_t padding:16;
  uint64_t R:1;                        // octet MSB
  uint64_t Timing_Advance_Command:11;  // first/2nd octet LSB
  uint64_t cqi_req:1;
  uint64_t UL_delay:1;
  uint64_t TPC:3;
  uint64_t mcs:4;
  uint64_t rb_alloc:10;
  uint64_t hopping_flag:1;
  uint64_t t_crnti:16;
  } __attribute__((__packed__))RAR_PDU;

#define sizeof_RAR_PDU 6
*/
198
/*!\brief  MAC subheader short with 7bit Length field */
199
typedef struct {
200 201 202 203 204
  uint8_t LCID:5;  // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;     // octet 1 MSB
  uint8_t L:7;     // octet 2 LSB
  uint8_t F:1;     // octet 2 MSB
205
} __attribute__((__packed__))SCH_SUBHEADER_SHORT;
206
/*!\brief  MAC subheader long  with 15bit Length field */
207
typedef struct {
208 209 210 211 212 213 214
  uint8_t LCID:5;   // octet 1 LSB
  uint8_t E:1;
  uint8_t R:2;      // octet 1 MSB
  uint8_t L_MSB:7;
  uint8_t F:1;      // octet 2 MSB
  uint8_t L_LSB:8;
  uint8_t padding;
215
} __attribute__((__packed__))SCH_SUBHEADER_LONG;
216
/*!\brief MAC subheader short without length field */
217
typedef struct {
218 219 220
  uint8_t LCID:5;
  uint8_t E:1;
  uint8_t R:2;
221 222
} __attribute__((__packed__))SCH_SUBHEADER_FIXED;

223
/*!\brief  mac control element: short buffer status report for a specific logical channel group ID*/
224
typedef struct {
225 226
  uint8_t Buffer_size:6;  // octet 1 LSB
  uint8_t LCGID:2;        // octet 1 MSB
227 228 229
} __attribute__((__packed__))BSR_SHORT;

typedef BSR_SHORT BSR_TRUNCATED;
230
/*!\brief  mac control element: long buffer status report for all logical channel group ID*/
231
typedef struct {
232 233 234 235 236
  uint32_t Buffer_size3:6;
  uint32_t Buffer_size2:6;
  uint32_t Buffer_size1:6;
  uint32_t Buffer_size0:6;
  uint32_t padding:8;
237 238 239
} __attribute__((__packed__))BSR_LONG;

#define BSR_LONG_SIZE  (sizeof(BSR_LONG))
240
/*!\brief  mac control element: timing advance  */
241
typedef struct {
242 243
  uint8_t TA:6;
  uint8_t R:2;
244
} __attribute__((__packed__))TIMING_ADVANCE_CMD;
245
/*!\brief  mac control element: power headroom report  */
246
typedef struct {
247 248
  uint8_t PH:6;
  uint8_t R:2;
249 250
} __attribute__((__packed__))POWER_HEADROOM_CMD;

251
/*!\brief  DCI PDU filled by MAC for the PHY  */
252
typedef struct {
253 254
  uint8_t Num_ue_spec_dci ;
  uint8_t Num_common_dci  ;
255
  //  uint32_t nCCE;
256
  uint32_t num_pdcch_symbols;
257 258
  DCI_ALLOC_t dci_alloc[NUM_DCI_MAX] ;
} DCI_PDU;
259
/*! \brief CCCH payload */
260
typedef struct {
261
  uint8_t payload[CCCH_PAYLOAD_SIZE_MAX] ;
262
} __attribute__((__packed__))CCCH_PDU;
263
/*! \brief BCCH payload */
264
typedef struct {
265
  uint8_t payload[BCCH_PAYLOAD_SIZE_MAX] ;
266
} __attribute__((__packed__))BCCH_PDU;
267 268 269 270
/*! \brief BCCH payload */
typedef struct {
  uint8_t payload[PCCH_PAYLOAD_SIZE_MAX] ;
} __attribute__((__packed__))PCCH_PDU;
271 272

#ifdef Rel10
273
/*! \brief MCCH payload */
274
typedef struct {
275
  uint8_t payload[MCCH_PAYLOAD_SIZE_MAX] ;
276
} __attribute__((__packed__))MCCH_PDU;
277
/*!< \brief MAC control element for activation and deactivation of component carriers */
278 279 280 281 282 283 284 285 286 287
typedef struct {
  uint8_t C7:1;/*!< \brief Component carrier 7 */
  uint8_t C6:1;/*!< \brief Component carrier 6 */
  uint8_t C5:1;/*!< \brief Component carrier 5 */
  uint8_t C4:1;/*!< \brief Component carrier 4 */
  uint8_t C3:1;/*!< \brief Component carrier 3 */
  uint8_t C2:1;/*!< \brief Component carrier 2 */
  uint8_t C1:1;/*!< \brief Component carrier 1 */
  uint8_t R:1;/*!< \brief Reserved  */
} __attribute__((__packed__))CC_ELEMENT;
288
/*! \brief MAC control element: MCH Scheduling Information */
289
typedef struct {
290 291 292
  uint8_t stop_sf_MSB:3; // octet 1 LSB
  uint8_t lcid:5;        // octet 2 MSB
  uint8_t stop_sf_LSB:8;
293
} __attribute__((__packed__))MSI_ELEMENT;
294 295
#endif
/*! \brief Values of CCCH LCID for DLSCH */ 
296
#define CCCH_LCHANID 0
297 298
/*!\brief Values of BCCH logical channel */
#define BCCH 3  // SI 
299 300
/*!\brief Values of PCCH logical channel */
#define PCCH 4  // Paging 
301 302 303 304 305 306 307 308 309 310 311 312 313 314
/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0  // srb0
/*!\brief DCCH / SRB1 logical channel */
#define DCCH 1  // srb1
/*!\brief DCCH1 / SRB2  logical channel */
#define DCCH1 2 // srb2
/*!\brief DTCH DRB1  logical channel */
#define DTCH 3 // LCID
/*!\brief MCCH logical channel */
#define MCCH 4 
/*!\brief MTCH logical channel */
#define MTCH 1 
// DLSCH LCHAN ID
/*!\brief LCID of UE contention resolution identity for DLSCH*/
315
#define UE_CONT_RES 28
316
/*!\brief LCID of timing advance for DLSCH */
317
#define TIMING_ADV_CMD 29
318
/*!\brief LCID of discontinous reception mode for DLSCH */
319
#define DRX_CMD 30
320
/*!\brief LCID of padding LCID for DLSCH */
321 322 323 324
#define SHORT_PADDING 31

#ifdef Rel10
// MCH LCHAN IDs (table6.2.1-4 TS36.321)
325
/*!\brief LCID of MCCH for DL */
326
#define MCCH_LCHANID 0
327 328 329
/*!\brief LCID of MCH scheduling info for DL */
#define MCH_SCHDL_INFO 3
/*!\brief LCID of Carrier component activation/deactivation */
330
#define CC_ACT_DEACT 27
331 332 333
#endif

// ULSCH LCHAN IDs
334
/*!\brief LCID of extended power headroom for ULSCH */
335
#define EXTENDED_POWER_HEADROOM 25
336
/*!\brief LCID of power headroom for ULSCH */
337
#define POWER_HEADROOM 26
338
/*!\brief LCID of CRNTI for ULSCH */
339
#define CRNTI 27
340
/*!\brief LCID of truncated BSR for ULSCH */
341
#define TRUNCATED_BSR 28
342
/*!\brief LCID of short BSR for ULSCH */
343
#define SHORT_BSR 29
344
/*!\brief LCID of long BSR for ULSCH */
345 346
#define LONG_BSR 30

347
/*! \brief Downlink SCH PDU Structure */
348
typedef struct {
349 350
  int8_t payload[8][SCH_PAYLOAD_SIZE_MAX];
  uint16_t Pdu_size[8];
351 352
} __attribute__ ((__packed__)) DLSCH_PDU;

353
/*! \brief MCH PDU Structure */
354
typedef struct {
355 356
  int8_t payload[SCH_PAYLOAD_SIZE_MAX];
  uint16_t Pdu_size;
357
  uint8_t mcs;
358 359 360
  uint8_t sync_area;
  uint8_t msi_active;
  uint8_t mcch_active;
361
  uint8_t mtch_active;
362 363
} __attribute__ ((__packed__)) MCH_PDU;

364
/*! \brief Uplink SCH PDU Structure */
365
typedef struct {
366 367
  int8_t payload[SCH_PAYLOAD_SIZE_MAX];         /*!< \brief SACH payload */
  uint16_t Pdu_size;
368 369 370 371
} __attribute__ ((__packed__)) ULSCH_PDU;

#include "PHY/impl_defs_top.h"

372
/*!\brief  UE ULSCH scheduling states*/
373 374 375
typedef enum {
  S_UL_NONE =0,
  S_UL_WAITING,
376 377
  S_UL_SCHEDULED,
  S_UL_BUFFERED,
378 379 380
  S_UL_NUM_STATUS
} UE_ULSCH_STATUS;

381
/*!\brief  UE DLSCH scheduling states*/
382 383 384
typedef enum {
  S_DL_NONE =0,
  S_DL_WAITING,
385 386
  S_DL_SCHEDULED,
  S_DL_BUFFERED,
387 388 389
  S_DL_NUM_STATUS
} UE_DLSCH_STATUS;

390
/*!\brief  scheduling policy for the contention-based access */
391
typedef enum {
392 393 394 395 396
  CBA_ES=0, /// equal share of RB among groups w
  CBA_ES_S,  /// equal share of RB among groups with small allocation
  CBA_PF, /// proportional fair (kind of)
  CBA_PF_S,  /// proportional fair (kind of) with small RB allocation
  CBA_RS /// random allocation
397 398 399
} CBA_POLICY;


400
/*! \brief temporary struct for ULSCH sched */
401
typedef struct {
402
  rnti_t rnti;
403 404
  uint16_t subframe;
  uint16_t serving_num;
405 406
  UE_ULSCH_STATUS status;
} eNB_ULSCH_INFO;
407
/*! \brief temp struct for DLSCH sched */
408
typedef struct {
409
  rnti_t rnti;
410 411 412
  uint16_t weight;
  uint16_t subframe;
  uint16_t serving_num;
413 414
  UE_DLSCH_STATUS status;
} eNB_DLSCH_INFO;
415
/*! \brief eNB overall statistics */
416
typedef struct {
417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435
  /// num BCCH PDU per CC 
  uint32_t total_num_bcch_pdu;
  /// BCCH buffer size  
  uint32_t bcch_buffer;
  /// total BCCH buffer size  
  uint32_t total_bcch_buffer;
  /// BCCH MCS
  uint32_t bcch_mcs;

  /// num CCCH PDU per CC 
  uint32_t total_num_ccch_pdu;
  /// BCCH buffer size  
  uint32_t ccch_buffer;
  /// total BCCH buffer size  
  uint32_t total_ccch_buffer;
  /// BCCH MCS
  uint32_t ccch_mcs;

/// num active users
436 437 438 439 440
  uint16_t num_dlactive_UEs;
  ///  available number of PRBs for a give SF
  uint16_t available_prbs;
  /// total number of PRB available for the user plane
  uint32_t total_available_prbs;
441 442
  /// aggregation
  /// total avilable nccc : num control channel element
443
  uint16_t available_ncces;
444 445
  // only for a new transmission, should be extended for retransmission
  // current dlsch  bit rate for all transport channels
446 447 448 449 450
  uint32_t dlsch_bitrate;
  //
  uint32_t dlsch_bytes_tx;
  //
  uint32_t dlsch_pdus_tx;
451
  //
452 453 454 455 456
  uint32_t total_dlsch_bitrate;
  //
  uint32_t total_dlsch_bytes_tx;
  //
  uint32_t total_dlsch_pdus_tx;
457 458
  
  // here for RX
459 460 461 462 463
  //
  uint32_t ulsch_bitrate;
  //
  uint32_t ulsch_bytes_rx;
  //
464 465 466 467 468 469 470 471
  uint64_t ulsch_pdus_rx; 

  uint32_t total_ulsch_bitrate;
  //
  uint32_t total_ulsch_bytes_rx;
  //
  uint32_t total_ulsch_pdus_rx;
  
472
} eNB_STATS;
473
/*! \brief eNB statistics for the connected UEs*/
474
typedef struct {
475 476

  /// CRNTI of UE
477
  rnti_t crnti; ///user id (rnti) of connected UEs
478
  // rrc status
479 480 481
  uint8_t rrc_status;
  /// harq pid
  uint8_t harq_pid;
482
  /// harq rounf
483
  uint8_t harq_round;
484
  /// DL Wideband CQI index (2 TBs)
485 486 487 488 489
  uint8_t dl_cqi;
  /// total available number of PRBs for a new transmission
  uint16_t rbs_used;
  /// total available number of PRBs for a retransmission
  uint16_t rbs_used_retx;
490
  /// total nccc used for a new transmission: num control channel element
491
  uint16_t ncce_used;
492
  /// total avilable nccc for a retransmission: num control channel element
493
  uint16_t ncce_used_retx;
494 495

  // mcs1 before the rate adaptaion
496
  uint8_t dlsch_mcs1;
497
  /// Target mcs2 after rate-adaptation
498
  uint8_t dlsch_mcs2;
499
  //  current TBS with mcs2
500
  uint32_t TBS;
501
  //  total TBS with mcs2
502
  //  uint32_t total_TBS;
503
  //  total rb used for a new transmission
504
  uint32_t total_rbs_used;
505
  //  total rb used for retransmission
506
  uint32_t total_rbs_used_retx;
507

508
   /// TX
509 510 511 512 513 514 515 516
  /// Num pkt
  uint32_t num_pdu_tx[NB_RB_MAX];
  /// num bytes
  uint32_t num_bytes_tx[NB_RB_MAX];
  /// num retransmission / harq
  uint32_t num_retransmission;
  /// instantaneous tx throughput for each TTI
  //  uint32_t tti_throughput[NB_RB_MAX];
517 518

  /// overall
519
  //
520 521 522 523
  uint32_t  dlsch_bitrate;
  //total
  uint32_t  total_dlsch_bitrate;
  /// headers+ CE +  padding bytes for a MAC PDU
524
  uint64_t overhead_bytes;
525
  /// headers+ CE +  padding bytes for a MAC PDU
526
  uint64_t total_overhead_bytes;
527
  /// headers+ CE +  padding bytes for a MAC PDU
528
  uint64_t avg_overhead_bytes;
529
  // MAC multiplexed payload
530 531 532
  uint64_t total_sdu_bytes;
  // total MAC pdu bytes
  uint64_t total_pdu_bytes;
533

534 535 536 537
  // total num pdu
  uint32_t total_num_pdus;
  //
  //  uint32_t avg_pdu_size;
538 539

  /// RX
540 541 542 543 544 545

  /// preassigned mcs after rate adaptation
  uint8_t ulsch_mcs1;
  /// adjusted mcs
  uint8_t ulsch_mcs2;

546 547 548 549
  /// estimated average pdu inter-departure time
  uint32_t avg_pdu_idt;
  /// estimated average pdu size
  uint32_t avg_pdu_ps;
550
  ///
551 552
  uint32_t aggregated_pdu_size;
  uint32_t aggregated_pdu_arrival;
553

554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569
  ///  uplink transport block size
  uint32_t ulsch_TBS;

  ///  total rb used for a new uplink transmission
  uint32_t num_retransmission_rx;
  ///  total rb used for a new uplink transmission
  uint32_t rbs_used_rx;
   ///  total rb used for a new uplink retransmission
  uint32_t rbs_used_retx_rx;
  ///  total rb used for a new uplink transmission
  uint32_t total_rbs_used_rx;
  /// normalized rx power 
  int32_t      normalized_rx_power;
   /// target rx power 
  int32_t    target_rx_power;

570
  /// num rx pdu
571
  uint32_t num_pdu_rx[NB_RB_MAX];
572
  /// num bytes rx
573
  uint32_t num_bytes_rx[NB_RB_MAX];
574
  /// instantaneous rx throughput for each TTI
575
  //  uint32_t tti_goodput[NB_RB_MAX];
576 577
  /// errors
  uint32_t num_errors_rx;
578 579 580 581 582 583 584 585 586 587
  
  uint64_t overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t total_overhead_bytes_rx;
  /// headers+ CE +  padding bytes for a MAC PDU
  uint64_t avg_overhead_bytes_rx;
 //
  uint32_t  ulsch_bitrate;
  //total
  uint32_t  total_ulsch_bitrate;
588
  /// overall
589 590
  ///  MAC pdu bytes
  uint64_t pdu_bytes_rx;
591
  /// total MAC pdu bytes
592
  uint64_t total_pdu_bytes_rx;
593
  /// total num pdu
594
  uint32_t total_num_pdus_rx;
595
  /// num of error pdus
596
  uint32_t total_num_errors_rx;
597

598
} eNB_UE_STATS;
599
/*! \brief eNB template for UE context information  */
600
typedef struct {
601
  /// C-RNTI of UE
602
  rnti_t rnti;
603 604 605 606
  /// NDI from last scheduling
  uint8_t oldNDI[8];
  /// NDI from last UL scheduling
  uint8_t oldNDI_UL[8];
607
  /// Flag to indicate UL has been scheduled at least once
gauthier's avatar
gauthier committed
608
  boolean_t ul_active;
knopp's avatar
knopp committed
609 610
  /// Flag to indicate UE has been configured (ACK from RRCConnectionSetup received)
  boolean_t configured;
611 612 613 614

  // PHY interface info

  /// DCI format for DLSCH
615
  uint16_t DLSCH_dci_fmt;
616

617
  /// Current Aggregation Level for DCI
618
  uint8_t DCI_aggregation_min;
619

620
  /// size of DLSCH size in bit 
621
  uint8_t DLSCH_dci_size_bits;
622 623

  /// DCI buffer for DLSCH
624 625 626
  /* rounded to 32 bits unit (actual value should be 8 due to the logic
   * of the function generate_dci0) */
  uint8_t DLSCH_DCI[8][(((MAX_DCI_SIZE_BITS)+31)>>5)*4];
627 628

  /// Number of Allocated RBs for DL after scheduling (prior to frequency allocation)
629
  uint16_t nb_rb[8]; // num_max_harq
630 631

  /// Number of Allocated RBs for UL after scheduling (prior to frequency allocation)
632
  uint16_t nb_rb_ul[8]; // num_max_harq
633

634 635
  /// Number of Allocated RBs by the ulsch preprocessor
  uint8_t pre_allocated_nb_rb_ul;
636

637 638
  /// index of Allocated RBs by the ulsch preprocessor
  int8_t pre_allocated_rb_table_index_ul;
639

640 641
  /// total allocated RBs
  int8_t total_allocated_rbs;
642

643
  /// pre-assigned MCS by the ulsch preprocessor
644
  uint8_t pre_assigned_mcs_ul;
645 646 647 648

  /// assigned MCS by the ulsch scheduler
  uint8_t assigned_mcs_ul;

649
  /// DCI buffer for ULSCH
650 651 652
  /* rounded to 32 bits unit (actual value should be 8 due to the logic
   * of the function generate_dci0) */
  uint8_t ULSCH_DCI[8][(((MAX_DCI_SIZE_BITS)+31)>>5)*4];
653 654

  /// DL DAI
655
  uint8_t DAI;
656 657

  /// UL DAI
658
  uint8_t DAI_ul[10];
659 660

  /// UL Scheduling Request Received
661
  uint8_t ul_SR;
662

663
  ///Resource Block indication for each sub-band in MU-MIMO
664
  uint8_t rballoc_subband[8][50];
665 666 667

  // Logical channel info for link with RLC

668
  /// Last received UE BSR info for each logical channel group id
669
  uint8_t bsr_info[MAX_NUM_LCGID];
670

671 672 673
  /// LCGID mapping
  long lcgidmap[11];

674
  /// phr information
675
  int8_t phr_info;
676

677 678 679
  /// phr information
  int8_t phr_info_configured;

680
  ///dl buffer info
681
  uint32_t dl_buffer_info[MAX_NUM_LCID];
682
  /// total downlink buffer info
683
  uint32_t dl_buffer_total;
684
  /// total downlink pdus
685
  uint32_t dl_pdus_total;
686
  /// downlink pdus for each LCID
687
  uint32_t dl_pdus_in_buffer[MAX_NUM_LCID];
688
  /// creation time of the downlink buffer head for each LCID
689
  uint32_t dl_buffer_head_sdu_creation_time[MAX_NUM_LCID];
690
  /// maximum creation time of the downlink buffer head across all LCID
691
  uint32_t  dl_buffer_head_sdu_creation_time_max;
692
  /// a flag indicating that the downlink head SDU is segmented  
693
  uint8_t    dl_buffer_head_sdu_is_segmented[MAX_NUM_LCID];
694
  /// size of remaining size to send for the downlink head SDU
695
  uint32_t dl_buffer_head_sdu_remaining_size_to_send[MAX_NUM_LCID];
696

697
  /// total uplink buffer size 
698
  uint32_t ul_total_buffer;
699
  /// uplink buffer creation time for each LCID
700
  uint32_t ul_buffer_creation_time[MAX_NUM_LCGID];
701
  /// maximum uplink buffer creation time across all the LCIDs
702
  uint32_t ul_buffer_creation_time_max;
703
  /// uplink buffer size per LCID
704 705
  uint32_t ul_buffer_info[MAX_NUM_LCGID];

706 707 708
  /// UE tx power
  int32_t ue_tx_power;

kaltenbe's avatar
kaltenbe committed
709
  /// stores the frame where the last TPC was transmitted
710 711 712 713
  uint32_t pusch_tpc_tx_frame;
  uint32_t pusch_tpc_tx_subframe;
  uint32_t pucch_tpc_tx_frame;
  uint32_t pucch_tpc_tx_subframe;
kaltenbe's avatar
kaltenbe committed
714

715 716 717
#ifdef LOCALIZATION
  eNB_UE_estimated_distances distance;
#endif
718 719
} UE_TEMPLATE;

720
/*! \brief scheduling control information set through an API (not used)*/
721
typedef struct {
722
  ///UL transmission bandwidth in RBs
723
  uint8_t ul_bandwidth[MAX_NUM_LCID];
724
  ///DL transmission bandwidth in RBs
725
  uint8_t dl_bandwidth[MAX_NUM_LCID];
726

727 728
  //To do GBR bearer
  uint8_t min_ul_bandwidth[MAX_NUM_LCID];
729

730
  uint8_t min_dl_bandwidth[MAX_NUM_LCID];
731

732
  ///aggregated bit rate of non-gbr bearer per UE
733
  uint64_t  ue_AggregatedMaximumBitrateDL;
734
  ///aggregated bit rate of non-gbr bearer per UE
735
  uint64_t  ue_AggregatedMaximumBitrateUL;
736
  ///CQI scheduling interval in subframes.
737
  uint16_t cqiSchedInterval;
738
  ///Contention resolution timer used during random access
739
  uint8_t mac_ContentionResolutionTimer;
740

741
  uint16_t max_allowed_rbs[MAX_NUM_LCID];
742

743
  uint8_t max_mcs[MAX_NUM_LCID];
744

745
  uint16_t priority[MAX_NUM_LCID];
746

747 748 749 750 751 752
  // resource scheduling information
  uint8_t       harq_pid[MAX_NUM_CCs];
  uint8_t       round[MAX_NUM_CCs];
  uint8_t       dl_pow_off[MAX_NUM_CCs];
  uint16_t      pre_nb_available_rbs[MAX_NUM_CCs];
  unsigned char rballoc_sub_UE[MAX_NUM_CCs][N_RBG_MAX];
753
  uint16_t      ta_timer;
754 755
  int16_t       ta_update;
  int32_t       context_active_timer;
756
  int32_t       cqi_req_timer;
757
  int32_t       ul_inactivity_timer;
758
  int32_t       ul_failure_timer;
759
  int32_t       ul_scheduled;
760
  int32_t       ra_pdcch_order_sent;
761
  int32_t       ul_out_of_sync;
762
  int32_t       phr_received;
763
} UE_sched_ctrl;
764
/*! \brief eNB template for the Random access information */
765 766
typedef struct {
  /// Flag to indicate this process is active
gauthier's avatar
gauthier committed
767
  boolean_t RA_active;
768
  /// Size of DCI for RA-Response (bytes)
769
  uint8_t RA_dci_size_bytes1;
770
  /// Size of DCI for RA-Response (bits)
771
  uint8_t RA_dci_size_bits1;
772
  /// Actual DCI to transmit for RA-Response
773
  uint8_t RA_alloc_pdu1[(MAX_DCI_SIZE_BITS>>3)+1];
774
  /// DCI format for RA-Response (should be 1A)
775
  uint8_t RA_dci_fmt1;
776
  /// Size of DCI for Msg4/ContRes (bytes)
777
  uint8_t RA_dci_size_bytes2;
778
  /// Size of DCI for Msg4/ContRes (bits)
779
  uint8_t RA_dci_size_bits2;
780
  /// Actual DCI to transmit for Msg4/ContRes
781
  uint8_t RA_alloc_pdu2[(MAX_DCI_SIZE_BITS>>3)+1];
782
  /// DCI format for Msg4/ContRes (should be 1A)
783
  uint8_t RA_dci_fmt2;
784
  /// Flag to indicate the eNB should generate RAR.  This is triggered by detection of PRACH
785
  uint8_t generate_rar;
786
  /// Subframe where preamble was received
787
  uint8_t preamble_subframe;
788
  /// Subframe where Msg3 is to be sent
789
  uint8_t Msg3_subframe;
790
  /// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC.  This is triggered by first ULSCH reception at eNB for new user.
791
  uint8_t generate_Msg4;
792
  /// Flag to indicate that eNB is waiting for ACK that UE has received Msg3.
793
  uint8_t wait_ack_Msg4;
794
  /// UE RNTI allocated during RAR
795
  rnti_t rnti;
796
  /// RA RNTI allocated from received PRACH
797
  uint16_t RA_rnti;
798
  /// Received preamble_index
799
  uint8_t preamble_index;
800
  /// Received UE Contention Resolution Identifier
801
  uint8_t cont_res_id[6];
802
  /// Timing offset indicated by PHY
803
  int16_t timing_offset;
804
  /// Timeout for RRC connection
805
  int16_t RRC_timer;
806 807 808
} RA_TEMPLATE;


809
/*! \brief subband bitmap confguration (for ALU icic algo purpose), in test phase */
810 811 812 813 814 815 816
typedef struct {
  uint8_t sbmap[NUMBER_OF_SUBBANDS_MAX]; //13 = number of SB MAX for 100 PRB
  uint8_t periodicity;
  uint8_t first_subframe;
  uint8_t sb_size;
  uint8_t nb_active_sb;
} SBMAP_CONF;
817
/*! \brief UE list used by eNB to order UEs/CC for scheduling*/ 
818
typedef struct {
819
  /// DLSCH pdu 
knopp's avatar
knopp committed
820 821 822 823 824
  DLSCH_PDU DLSCH_pdu[MAX_NUM_CCs][2][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection parameters for UEs
  UE_TEMPLATE UE_template[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
  /// DCI template and MAC connection for RA processes
  int pCC_id[NUMBER_OF_UE_MAX];
825
  /// sorted downlink component carrier for the scheduler 
knopp's avatar
knopp committed
826
  int ordered_CCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
827
  /// number of downlink active component carrier 
knopp's avatar
knopp committed
828
  int numactiveCCs[NUMBER_OF_UE_MAX];
829
  /// sorted uplink component carrier for the scheduler 
knopp's avatar
knopp committed
830
  int ordered_ULCCids[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
831
  /// number of uplink active component carrier 
knopp's avatar
knopp committed
832
  int numactiveULCCs[NUMBER_OF_UE_MAX];
833
  /// number of downlink active component carrier 
834
  uint8_t dl_CC_bitmap[NUMBER_OF_UE_MAX];
835
  /// eNB to UE statistics
knopp's avatar
knopp committed
836
  eNB_UE_STATS eNB_UE_stats[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
837
  /// scheduling control info
knopp's avatar
knopp committed
838 839 840
  UE_sched_ctrl UE_sched_ctrl[NUMBER_OF_UE_MAX];

  int next[NUMBER_OF_UE_MAX];
841
  int head;
842 843
  int next_ul[NUMBER_OF_UE_MAX];
  int head_ul;
knopp's avatar
knopp committed
844 845 846 847
  int avail;
  int num_UEs;
  boolean_t active[NUMBER_OF_UE_MAX];
} UE_list_t;
848

849
/*! \brief eNB common channels */ 
850
typedef struct {
851 852 853 854
  /// Outgoing DCI for PHY generated by eNB scheduler
  DCI_PDU DCI_pdu;
  /// Outgoing BCCH pdu for PHY
  BCCH_PDU BCCH_pdu;
855 856
  /// Outgoing BCCH DCI allocation
  uint32_t BCCH_alloc_pdu;
857 858 859
  /// Outgoing CCCH pdu for PHY
  CCCH_PDU CCCH_pdu;
  RA_TEMPLATE RA_template[NB_RA_PROC_MAX];
860 861
  /// VRB map for common channels
  uint8_t vrb_map[100];
862 863
  /// MBSFN SubframeConfig
  struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8];
864
  /// number of subframe allocation pattern available for MBSFN sync area
865
  uint8_t num_sf_allocation_pattern;
866
#ifdef Rel10
867
  /// MBMS Flag
868
  uint8_t MBMS_flag;
869 870 871
  /// Outgoing MCCH pdu for PHY
  MCCH_PDU MCCH_pdu;
  /// MCCH active flag
872
  uint8_t msi_active;
873
  /// MCCH active flag
874
  uint8_t mcch_active;
875
  /// MTCH active flag
876
  uint8_t mtch_active;
877
  /// number of active MBSFN area
878
  uint8_t num_active_mbsfn_area;
879 880 881 882 883 884 885 886 887 888
  /// MBSFN Area Info
  struct  MBSFN_AreaInfo_r9 *mbsfn_AreaInfo[MAX_MBSFN_AREA];
  /// PMCH Config
  struct PMCH_Config_r9 *pmch_Config[MAX_PMCH_perMBSFN];
  /// MBMS session info list
  struct MBMS_SessionInfoList_r9 *mbms_SessionList[MAX_PMCH_perMBSFN];
  /// Outgoing MCH pdu for PHY
  MCH_PDU MCH_pdu;
#endif
#ifdef CBA
889
  /// number of CBA groups 
890
  uint8_t num_active_cba_groups;
891
  /// RNTI for each CBA group 
892
  uint16_t cba_rnti[NUM_MAX_CBA_GROUP];
893
  /// MCS for each CBA group 
894
  uint8_t group_mcs[NUM_MAX_CBA_GROUP];
895 896
#endif
} COMMON_channels_t;
897
/*! \brief top level eNB MAC structure */ 
898 899
typedef struct {
  ///
knopp's avatar
knopp committed
900 901 902 903 904 905 906 907
  uint16_t Node_id;
  /// frame counter
  frame_t frame;
  /// subframe counter
  sub_frame_t subframe;
  /// Common cell resources
  COMMON_channels_t common_channels[MAX_NUM_CCs];
  UE_list_t UE_list;
908

909 910
  ///subband bitmap configuration
  SBMAP_CONF sbmap_conf;
911 912
  /// CCE table used to build DCI scheduling information
  int CCE_table[MAX_NUM_CCs][800];
913
  ///  active flag for Other lcid
914
  uint8_t lcid_active[NB_RB_MAX];
915
  /// eNB stats
916
  eNB_STATS eNB_stats[MAX_NUM_CCs];
917
  // MAC function execution peformance profiler
918
  /// processing time of eNB scheduler 
919
  time_stats_t eNB_scheduler;
920
  /// processing time of eNB scheduler for SI 
921
  time_stats_t schedule_si;
922
  /// processing time of eNB scheduler for Random access
923
  time_stats_t schedule_ra;
924
  /// processing time of eNB ULSCH scheduler 
925
  time_stats_t schedule_ulsch;
926
  /// processing time of eNB DCI generation
927
  time_stats_t fill_DLSCH_dci;
928
  /// processing time of eNB MAC preprocessor
929
  time_stats_t schedule_dlsch_preprocessor;
930
  /// processing time of eNB DLSCH scheduler 
931
  time_stats_t schedule_dlsch; // include rlc_data_req + MAC header + preprocessor
932
  /// processing time of eNB MCH scheduler 
933
  time_stats_t schedule_mch;
934
  /// processing time of eNB ULSCH reception
935
  time_stats_t rx_ulsch_sdu; // include rlc_data_ind
936 937

} eNB_MAC_INST;
938

939 940 941 942 943 944 945 946 947 948 949 950 951
/* 
 * UE part 
 */ 

/*!\brief UE layer 2 status */
typedef enum {
  CONNECTION_OK=0,
  CONNECTION_LOST,
  PHY_RESYNCH,
  PHY_HO_PRACH
} UE_L2_STATE_t;

/*!\brief UE scheduling info */
952 953
typedef struct {
  /// buffer status for each lcgid
954
  uint8_t  BSR[MAX_NUM_LCGID]; // should be more for mesh topology
955
  /// keep the number of bytes in rlc buffer for each lcid
956
  uint16_t  BSR_bytes[MAX_NUM_LCGID];
957
  /// buffer status for each lcid
958
  uint8_t  LCID_status[MAX_NUM_LCID];
959
  /// SR pending as defined in 36.321
960
  uint8_t  SR_pending;
961
  /// SR_COUNTER as defined in 36.321
962
  uint16_t SR_COUNTER;
963
  /// logical channel group ide for each LCID
964
  uint8_t  LCGID[MAX_NUM_LCID];
965
  /// retxBSR-Timer, default value is sf2560
966
  uint16_t retxBSR_Timer;
967
  /// retxBSR_SF, number of subframe before triggering a regular BSR
968
  int16_t retxBSR_SF;
969
  /// periodicBSR-Timer, default to infinity
970
  uint16_t periodicBSR_Timer;
971
  /// periodicBSR_SF, number of subframe before triggering a periodic BSR
972
  int16_t periodicBSR_SF;
973
  /// default value is 0: not configured
974
  uint16_t sr_ProhibitTimer;
975
  /// sr ProhibitTime running
976
  uint8_t sr_ProhibitTimer_Running;
977
  ///  default value to n5
978
  uint16_t maxHARQ_Tx;
979
  /// default value is false
980
  uint16_t ttiBundling;
981
  /// default value is release
982 983 984 985
  struct DRX_Config *drx_config;
  /// default value is release
  struct MAC_MainConfig__phr_Config *phr_config;
  ///timer before triggering a periodic PHR
986
  uint16_t periodicPHR_Timer;
987
  ///timer before triggering a prohibit PHR
988
  uint16_t prohibitPHR_Timer;
989
  ///DL Pathloss change value
990
  uint16_t PathlossChange;
991
  ///number of subframe before triggering a periodic PHR
992
  int16_t periodicPHR_SF;
993
  ///number of subframe before triggering a prohibit PHR
994
  int16_t prohibitPHR_SF;
995
  ///DL Pathloss Change in db
996
  uint16_t PathlossChange_db;
997
  //Bj bucket usage per  lcid
998
  int16_t Bj[MAX_NUM_LCID];
999
  // Bucket size per lcid
1000
  int16_t bucket_size[MAX_NUM_LCID];
1001
} UE_SCHEDULING_INFO;
1002
/*!\brief Top level UE MAC structure */
1003
typedef struct {
1004
  uint16_t Node_id;
1005
  /// frame counter
1006
  frame_t     frame;
1007
  /// subframe counter
1008
  sub_frame_t subframe;
1009
  /// C-RNTI of UE
1010
  uint16_t crnti;
1011
  /// C-RNTI of UE before HO
1012
  rnti_t crnti_before_ho; ///user id (rnti) of connected UEs
1013 1014
  /// uplink active flag
  uint8_t ul_active;
1015
  /// pointer to RRC PHY configuration
1016
  RadioResourceConfigCommonSIB_t *radioResourceConfigCommon;
1017
  /// pointer to RACH_ConfigDedicated (NULL when not active, i.e. upon HO completion or T304 expiry)
1018 1019
  struct RACH_ConfigDedicated *rach_ConfigDedicated;
  /// pointer to RRC PHY configuration
1020
  struct PhysicalConfigDedicated *physicalConfigDedicated;
1021 1022 1023 1024
#ifdef Rel10
  /// pointer to RRC PHY configuration SCEll
  struct PhysicalConfigDedicatedSCell_r10 *physicalConfigDedicatedSCell_r10;
#endif
1025 1026 1027
  /// pointer to TDD Configuration (NULL for FDD)
  TDD_Config_t *tdd_Config;
  /// Number of adjacent cells to measure
1028
  uint8_t  n_adj_cells;
1029
  /// Array of adjacent physical cell ids
1030
  uint32_t adj_cell_id[6];
1031 1032 1033 1034 1035 1036
  /// Pointer to RRC MAC configuration
  MAC_MainConfig_t *macConfig;
  /// Pointer to RRC Measurement gap configuration
  MeasGapConfig_t  *measGapConfig;
  /// Pointers to LogicalChannelConfig indexed by LogicalChannelIdentity. Note NULL means LCHAN is inactive.
  LogicalChannelConfig_t *logicalChannelConfig[MAX_NUM_LCID];
1037
  /// Scheduling Information
1038 1039 1040 1041 1042 1043
  UE_SCHEDULING_INFO scheduling_info;
  /// Outgoing CCCH pdu for PHY
  CCCH_PDU CCCH_pdu;
  /// Incoming DLSCH pdu for PHY
  //DLSCH_PDU DLSCH_pdu[NUMBER_OF_UE_MAX][2];
  /// number of attempt for rach
1044
  uint8_t RA_attempt_number;
1045
  /// Random-access procedure flag
1046
  uint8_t RA_active;
1047
  /// Random-access window counter
1048
  int8_t RA_window_cnt;
1049
  /// Random-access Msg3 size in bytes
1050
  uint8_t RA_Msg3_size;
1051
  /// Random-access prachMaskIndex
1052
  uint8_t RA_prachMaskIndex;
1053
  /// Flag indicating Preamble set (A,B) used for first Msg3 transmission
1054
  uint8_t RA_usedGroupA;
1055 1056 1057
  /// Random-access Resources
  PRACH_RESOURCES_t RA_prach_resources;
  /// Random-access PREAMBLE_TRANSMISSION_COUNTER
1058
  uint8_t RA_PREAMBLE_TRANSMISSION_COUNTER;
1059
  /// Random-access backoff counter
1060
  int16_t RA_backoff_cnt;
1061
  /// Random-access variable for window calculation (frame of last change in window counter)
1062
  uint32_t RA_tx_frame;
1063
  /// Random-access variable for window calculation (subframe of last change in window counter)
1064
  uint8_t RA_tx_subframe;
1065 1066
  /// Random-access Group B maximum path-loss
  /// Random-access variable for backoff (frame of last change in backoff counter)
1067
  uint32_t RA_backoff_frame;
1068
  /// Random-access variable for backoff (subframe of last change in backoff counter)
1069
  uint8_t RA_backoff_subframe;
1070
  /// Random-access Group B maximum path-loss
1071
  uint16_t RA_maxPL;
1072
  /// Random-access Contention Resolution Timer active flag
1073
  uint8_t RA_contention_resolution_timer_active;
1074
  /// Random-access Contention Resolution Timer count value
1075
  uint8_t RA_contention_resolution_cnt;
1076
  /// power headroom reporitng reconfigured
1077
  uint8_t PHR_reconfigured;
1078
  /// power headroom state as configured by the higher layers
1079
  uint8_t PHR_state;
1080
  /// power backoff due to power management (as allowed by P-MPRc) for this cell
1081
  uint8_t PHR_reporting_active;
1082
  /// power backoff due to power management (as allowed by P-MPRc) for this cell
1083
  uint8_t power_backoff_db[NUMBER_OF_eNB_MAX];