Commit 09f149d8 authored by calvin wang's avatar calvin wang

Stabilization UE BSR feature

parent 1568b5a1
......@@ -69,7 +69,10 @@ void ue_mac_reset(module_id_t module_idP,uint8_t eNB_index)
// cancel all pending SRs
UE_mac_inst[module_idP].scheduling_info.SR_pending=0;
UE_mac_inst[module_idP].scheduling_info.SR_COUNTER=0;
UE_mac_inst[module_idP].BSR_reporting_active[REGULAR_BSR]=0;
UE_mac_inst[module_idP].BSR_reporting_active[PADDING_BSR]=0;
UE_mac_inst[module_idP].BSR_reporting_active[PERIODIC_BSR]=0;
UE_mac_inst[module_idP].retxBSRTimer_expires_flag = 0;
// stop ongoing RACH procedure
// discard explicitly signaled ra_PreambleIndex and ra_RACH_MaskIndex, if any
......@@ -228,10 +231,34 @@ rrc_mac_config_req(
UE_mac_inst[Mod_idP].scheduling_info.sr_ProhibitTimer = (uint16_t) 0;
}
if (mac_MainConfig->ext2 && mac_MainConfig->ext2->mac_MainConfig_v1020) {
if (mac_MainConfig->ext2->mac_MainConfig_v1020->extendedBSR_Sizes_r10) {
UE_mac_inst[Mod_idP].scheduling_info.extendedBSR_Sizes_r10 = (uint16_t) *mac_MainConfig->ext2->mac_MainConfig_v1020->extendedBSR_Sizes_r10;
} else {
UE_mac_inst[Mod_idP].scheduling_info.extendedBSR_Sizes_r10 = (uint16_t)0;
}
if (mac_MainConfig->ext2->mac_MainConfig_v1020->extendedPHR_r10) {
UE_mac_inst[Mod_idP].scheduling_info.extendedPHR_r10 = (uint16_t) *mac_MainConfig->ext2->mac_MainConfig_v1020->extendedPHR_r10;
} else {
UE_mac_inst[Mod_idP].scheduling_info.extendedPHR_r10 = (uint16_t)0;
}
} else {
UE_mac_inst[Mod_idP].scheduling_info.extendedBSR_Sizes_r10 = (uint16_t)0;
UE_mac_inst[Mod_idP].scheduling_info.extendedPHR_r10 = (uint16_t)0;
}
#endif
UE_mac_inst[Mod_idP].scheduling_info.periodicBSR_SF = get_sf_periodicBSRTimer(UE_mac_inst[Mod_idP].scheduling_info.periodicBSR_Timer);
UE_mac_inst[Mod_idP].scheduling_info.retxBSR_SF = get_sf_retxBSRTimer(UE_mac_inst[Mod_idP].scheduling_info.retxBSR_Timer);
UE_mac_inst[Mod_idP].scheduling_info.periodicBSR_SF = 0xFFFF;
UE_mac_inst[Mod_idP].scheduling_info.retxBSR_SF = 0xFFFF;
UE_mac_inst[Mod_idP].BSR_reporting_active[REGULAR_BSR]=0;
UE_mac_inst[Mod_idP].BSR_reporting_active[PADDING_BSR]=0;
UE_mac_inst[Mod_idP].BSR_reporting_active[PERIODIC_BSR]=0;
UE_mac_inst[Mod_idP].retxBSRTimer_expires_flag = 0;
LOG_D(MAC,"[UE %d]: periodic BSR %d (SF), retx BSR %d (SF)\n",
Mod_idP,
UE_mac_inst[Mod_idP].scheduling_info.periodicBSR_SF,
UE_mac_inst[Mod_idP].scheduling_info.retxBSR_SF);
UE_mac_inst[Mod_idP].scheduling_info.drx_config = mac_MainConfig->drx_Config;
UE_mac_inst[Mod_idP].scheduling_info.phr_config = mac_MainConfig->phr_Config;
......@@ -252,6 +279,7 @@ rrc_mac_config_req(
UE_mac_inst[Mod_idP].scheduling_info.periodicPHR_SF = get_sf_perioidicPHR_Timer(UE_mac_inst[Mod_idP].scheduling_info.periodicPHR_Timer);
UE_mac_inst[Mod_idP].scheduling_info.prohibitPHR_SF = get_sf_prohibitPHR_Timer(UE_mac_inst[Mod_idP].scheduling_info.prohibitPHR_Timer);
UE_mac_inst[Mod_idP].scheduling_info.PathlossChange_db = get_db_dl_PathlossChange(UE_mac_inst[Mod_idP].scheduling_info.PathlossChange);
UE_mac_inst[Mod_idP].PHR_reporting_active = 0;
LOG_D(MAC,"[UE %d] config PHR (%d): periodic %d (SF) prohibit %d (SF) pathlosschange %d (db) \n",
Mod_idP,
(mac_MainConfig->phr_Config)?mac_MainConfig->phr_Config->present:-1,
......
......@@ -336,6 +336,14 @@ typedef struct {
#define SHORT_BSR 29
/*!\brief LCID of long BSR for ULSCH */
#define LONG_BSR 30
/*!\brief first level bsr type for ULSCH: Regular BSR,Padding BSR,Periodic BSR*/
#define BSR_TYPE_FIRST_LEVEL 3
/*!\brief first level bsr type states*/
typedef enum {
REGULAR_BSR =0,
PADDING_BSR,
PERIODIC_BSR
} UE_FIRST_LEVEL_BSR_TYPE;
/*! \brief Downlink SCH PDU Structure */
typedef struct {
......@@ -945,8 +953,10 @@ typedef enum {
typedef struct {
/// buffer status for each lcgid
uint8_t BSR[MAX_NUM_LCGID]; // should be more for mesh topology
/// keep the number of bytes in rlc buffer for each lcid
/// keep the number of bytes in rlc buffer for each lcgid
uint16_t BSR_bytes[MAX_NUM_LCGID];
/// after multiplexing buffer remain for each lcid
uint16_t LCID_buffer_remain[MAX_NUM_LCID];
/// buffer status for each lcid
uint8_t LCID_status[MAX_NUM_LCID];
/// SR pending as defined in 36.321
......@@ -958,11 +968,11 @@ typedef struct {
/// retxBSR-Timer, default value is sf2560
uint16_t retxBSR_Timer;
/// retxBSR_SF, number of subframe before triggering a regular BSR
int16_t retxBSR_SF;
int16_t retxBSR_SF; // if value equal oxFFFF means counters are NOT active
/// periodicBSR-Timer, default to infinity
uint16_t periodicBSR_Timer;
/// periodicBSR_SF, number of subframe before triggering a periodic BSR
int16_t periodicBSR_SF;
int16_t periodicBSR_SF; // if value equal oxFFFF means counters are NOT active
/// default value is 0: not configured
uint16_t sr_ProhibitTimer;
/// sr ProhibitTime running
......@@ -987,6 +997,12 @@ typedef struct {
int16_t prohibitPHR_SF;
///DL Pathloss Change in db
uint16_t PathlossChange_db;
/// default value is false
uint16_t extendedBSR_Sizes_r10;
/// default value is false
uint16_t extendedPHR_r10;
//Bj bucket usage per lcid
int16_t Bj[MAX_NUM_LCID];
// Bucket size per lcid
......@@ -1074,6 +1090,11 @@ typedef struct {
uint8_t PHR_reporting_active;
/// power backoff due to power management (as allowed by P-MPRc) for this cell
uint8_t power_backoff_db[NUMBER_OF_eNB_MAX];
/// BSR report falg management
uint8_t BSR_reporting_active[BSR_TYPE_FIRST_LEVEL];
/// retxBSR-Timer expires flag
uint8_t retxBSRTimer_expires_flag;
/// MBSFN_Subframe Configuration
struct MBSFN_SubframeConfig *mbsfn_SubframeConfig[8]; // FIXME replace 8 by MAX_MBSFN_AREA?
/// number of subframe allocation pattern available for MBSFN sync area
......
......@@ -46,6 +46,8 @@
extern const uint32_t BSR_TABLE[BSR_TABLE_SIZE];
//extern uint32_t EBSR_Level[63];
extern const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE];
//extern uint32_t Extended_BSR_TABLE[63]; ----currently not used
extern UE_MAC_INST *UE_mac_inst;
extern eNB_MAC_INST *eNB_mac_inst;
......
......@@ -545,13 +545,13 @@ int cba_access(module_id_t module_idP,frame_t frameP,sub_frame_t subframe, uint8
*/
int get_bsr_lcgid (module_id_t module_idP);
/*! \fn uint8_t get_bsr_len (module_id_t module_idP,uint16_t bufflen);
/*! \fn int get_bsr_type (module_id_t module_idP,uint16_t bufflen);
\brief determine whether the bsr is short or long assuming that the MAC pdu is built
\param[in] Mod_id instance of the UE
\param[in] bufflen size of phy transport block
\param[out] bsr_len size of bsr control element
*/
uint8_t get_bsr_len (module_id_t module_idP, uint16_t buflen);
int get_bsr_type (module_id_t module_idP, uint8_t eNB_index,frame_t frameP,uint16_t buflen);
/*! \fn BSR_SHORT * get_bsr_short(module_id_t module_idP, uint8_t bsr_len)
\brief get short bsr level
......
......@@ -391,7 +391,7 @@ PRACH_RESOURCES_t *ue_get_rach(module_id_t module_idP,int CC_id,frame_t frameP,
1); //post_padding
return(&UE_mac_inst[module_idP].RA_prach_resources);
} else if (UE_mac_inst[module_idP].scheduling_info.BSR_bytes[DCCH] > 0) {
} else if (UE_mac_inst[module_idP].scheduling_info.BSR_bytes[UE_mac_inst[module_idP].scheduling_info.LCGID[DCCH]] > 0) {
// This is for triggering a transmission on DCCH using PRACH (during handover, or sending SR for example)
dcch_header_len = 2 + 2; /// SHORT Subheader + C-RNTI control element
rlc_status = mac_rlc_status_ind(module_idP,UE_mac_inst[module_idP].crnti, eNB_indexP,frameP,ENB_FLAG_NO,MBMS_FLAG_NO,
......
This diff is collapsed.
......@@ -45,6 +45,15 @@ const uint32_t BSR_TABLE[BSR_TABLE_SIZE]= {0,10,12,14,17,19,22,26,31,36,42,49,57
1326,1552,1817,2127,2490,2915,3413,3995,4677,5467,6411,7505,8787,10287,12043,14099,
16507,19325,22624,26487,31009,36304,42502,49759,58255,68201,79846,93479,109439, 128125,150000, 300000
};
// extended bsr table--currently not used
const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE] = {0,10,13,16,19,23,29,35,43,53,65,80,98,120,147,
181,223,274,337,414,509,625,769,945,1162,1429,
1757,2161,2657,3267,4017,4940,6074,7469,9185,
11294,13888,17077,20999,25822,31752,39045,48012,
59039,72598,89272,109774,134986,165989,204111,
250990,308634,379519,466683,573866,705666,867737,
1067031,1312097,1613447,1984009,2439678,3000000,
6000000};
//uint32_t EBSR_Level[63]={0,10,13,16,19,23,29,35,43,53,65,80,98,120,147,181};
......
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