Commit 2a9dc8c2 authored by knopp's avatar knopp

added format 1C support for UE. Corrected compilation error for EXMIMO2 targets

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@7743 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 878eef41
......@@ -134,7 +134,7 @@ else (CMAKE_SYSTEM_PROCESSOR STREQUAL "armv7l")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -mavx2")
endif()
if (CPUINFO MATCHES "sse4_2")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -msse4.2")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -msse4.2 -mavx2")
endif()
if (CPUINFO MATCHES "sse4_1")
set(C_FLAGS_PROCESSOR "${C_FLAGS_PROCESSOR} -msse4.1")
......@@ -386,7 +386,7 @@ elseif (${RF_BOARD} STREQUAL "ETHERNET")
set(HW_SOURCE ${HW_SOURCE}
${OPENAIR_TARGETS}/ARCH/ETHERNET/USERSPACE/LIB/ethernet_lib.c
)
set(LOWLATENCY True)
set(LOWLATENCY False)
elseif (${RF_BOARD} STREQUAL "CPRIGW")
set(HW_SOURCE ${HW_SOURCE}
......
......@@ -42,7 +42,7 @@ set ( NAS_BUILT_IN_EPC False )
set ( NAS_BUILT_IN_UE False )
set ( NAS_MME False )
set ( NAS_NETLINK False )
set ( NAS_UE True )
set ( NAS_UE False )
set ( NB_ANTENNAS_RX 2 )
set ( NB_ANTENNAS_TX 2 )
set ( NB_ANTENNAS_TXRX 2 )
......
This diff is collapsed.
......@@ -829,14 +829,73 @@ struct DCI1B_5MHz_4A_TDD {
typedef struct DCI1B_5MHz_4A_TDD DCI1B_5MHz_4A_TDD_t;
#define sizeof_DCI1B_5MHz_4A_TDD_t 31
/// DCI Format Type 1C (1.4 MHz, 8 bits)
struct DCI1C_1_5MHz
{
/// padding to 32bits
uint32_t padding32:24;
uint32_t mcs:5;
uint32_t rballoc:3; // N_RB_step = 2, Ngap=Ngap1=3, NDLVRBGap = 6, ceil(log2((3*4)/2)) = 3
} __attribute__ ((__packed__));
typedef struct DCI1C_1_5MHz DCI1C_1_5MHz_t;
#define sizeof_DCI1C_1_5MHz_t 8
/*********************************************************
**********************************************************/
/// DCI Format Type 1C (5 MHz, 12 bits)
typedef struct __attribute__ ((__packed__))
struct DCI1C_5MHz
{
uint32_t rballoc:7;
uint32_t tbs_index:5;
}
DCI1C_5MHz_t;
#define sizeof_DCI1C_5MHz_t 12
/// padding to 32bits
uint32_t padding32:20;
uint32_t mcs:5;
uint32_t rballoc:7; // N_RB_step = 2, Ngap1=Ngap2=12, NDLVRBGap = 24, ceil(log2((12*13)/2)) = 7
} __attribute__ ((__packed__));
typedef struct DCI1C_5MHz DCI1C_5MHz_t;
#define sizeof_DCI1C_5MHz_t 12
/// DCI Format Type 1C (10 MHz, 13 bits)
struct DCI1C_10MHz
{
/// padding to 32bits
uint32_t padding32:19;
uint32_t mcs:5;
uint32_t rballoc:7; // N_RB_step = 4, Ngap1=27, NDLVRBGap = 46, ceil(log2(((11*12)/2)) = 7
uint32_t Ngap:1;
} __attribute__ ((__packed__));
typedef struct DCI1C_10MHz DCI1C_10MHz_t;
#define sizeof_DCI1C_10MHz_t 13
/// DCI Format Type 1C (15 MHz, 14 bits)
struct DCI1C_15MHz
{
/// padding to 32bits
uint32_t padding32:18;
uint32_t mcs:5;
uint32_t rballoc:8; // N_RB_step = 4, Ngap1=64, ceil(log2((16*17)/2)) = 8
uint32_t Ngap:1;
} __attribute__ ((__packed__));
typedef struct DCI1C_15MHz DCI1C_15MHz_t;
#define sizeof_DCI1C_15MHz_t X
/// DCI Format Type 1C (20 MHz, 15 bits)
struct DCI1C_20MHz
{
/// padding to 32bits
uint32_t padding32:17;
uint32_t mcs:5;
uint32_t rballoc:9; // N_RB_step = 4, Ngap1=48, ceil(log2((24*25)/2)) = 9
uint32_t Ngap:1;
} __attribute__ ((__packed__));
typedef struct DCI1C_20MHz DCI1C_20MHz_t;
#define sizeof_DCI1C_20MHz_t 15
/*********************************************************
**********************************************************/
/// DCI Format Type 1D (5 MHz, FDD, 2 Antenna Ports, 27 bits)
struct DCI1D_5MHz_2A_FDD {
......
This diff is collapsed.
......@@ -124,6 +124,8 @@ typedef struct {
MIMO_mode_t mimo_mode;
/// Current RB allocation
uint32_t rb_alloc[4];
/// distributed/localized flag
vrb_t vrb_type;
/// Current subband PMI allocation
uint16_t pmi_alloc;
/// Current subband RI allocation
......@@ -549,8 +551,12 @@ typedef struct {
uint16_t nb_rb;
/// Current subband PMI allocation
uint16_t pmi_alloc;
/// Current RB allocation
uint32_t rb_alloc[4];
/// Current RB allocation (even slots)
uint32_t rb_alloc_even[4];
/// Current RB allocation (odd slots)
uint32_t rb_alloc_odd[4];
/// distributed/localized flag
vrb_t vrb_type;
/// downlink power offset field
uint8_t dl_power_off;
} LTE_DL_UE_HARQ_t;
......
......@@ -59,3 +59,5 @@ unsigned int TBStable[TBStable_rowCnt][110] = {{16,32,56,88,120,152,176,208,224,
{616,1256,1864,2536,3112,3752,4392,5160,5736,6200,6968,7480,8248,8760,9528,10296,10680,11448,12216,12576,13536,14112,14688,15264,15840,16416,16992,17568,18336,19080,19848,20616,20616,21384,22152,22920,23688,24496,24496,25456,26416,26416,27376,28336,28336,29296,29296,30576,31704,31704,32856,32856,34008,34008,35160,35160,36696,36696,37888,37888,39232,39232,40576,40576,40576,42368,42368,43816,43816,43816,45352,45352,46888,46888,46888,48936,48936,48936,51024,51024,51024,52752,52752,52752,55056,55056,55056,55056,57336,57336,57336,59256,59256,59256,61664,61664,61664,61664,63776,63776,63776,63776,66592,66592,66592,66592,68808,68808,68808,71112},
{712,1480,2216,2984,3752,4392,5160,5992,6712,7480,8248,8760,9528,10296,11064,11832,12576,13536,14112,14688,15264,16416,16992,17568,18336,19080,19848,20616,21384,22152,22920,23688,24496,25456,25456,26416,27376,28336,29296,29296,30576,30576,31704,32856,32856,34008,35160,35160,36696,36696,37888,37888,39232,40576,40576,40576,42368,42368,43816,43816,45352,45352,46888,46888,48936,48936,48936,51024,51024,52752,52752,52752,55056,55056,55056,55056,57336,57336,57336,59256,59256,59256,61664,61664,61664,63776,63776,63776,66592,66592,66592,68808,68808,68808,71112,71112,71112,73712,73712,75376,75376,75376,75376,75376,75376,75376,75376,75376,75376,75376}
};
unsigned int TBStable1C[32] = {40, 56, 72, 120, 136, 144, 176, 208, 224, 256, 280, 296, 328, 336, 392, 488, 552, 600, 632, 696, 776, 840, 904, 1000, 1064, 1128, 1224, 1288, 1384, 1480, 1608, 1736};
......@@ -26,7 +26,7 @@
Address : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE
*******************************************************************************/
extern unsigned int dlsch_tbs25[27][25],TBStable[27][110];
extern unsigned int dlsch_tbs25[27][25],TBStable[27][110],TBStable1C[32];
extern unsigned short lte_cqi_eff1024[16];
extern char lte_cqi_snr_dB[15];
extern short conjugate[8],conjugate2[8];
......
......@@ -257,23 +257,31 @@ void fill_UE_dlsch_MCH(PHY_VARS_UE *phy_vars_ue,int mcs,int ndi,int rvidx,int eN
switch(frame_parms->N_RB_DL) {
case 6:
dlsch->harq_processes[0]->rb_alloc[0] = 0x3f;
dlsch->harq_processes[0]->rb_alloc_even[0] = 0x3f;
dlsch->harq_processes[0]->rb_alloc_odd[0] = 0x3f;
break;
case 25:
dlsch->harq_processes[0]->rb_alloc[0] = 0x1ffffff;
dlsch->harq_processes[0]->rb_alloc_even[0] = 0x1ffffff;
dlsch->harq_processes[0]->rb_alloc_odd[0] = 0x1ffffff;
break;
case 50:
dlsch->harq_processes[0]->rb_alloc[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc[1] = 0x3ffff;
dlsch->harq_processes[0]->rb_alloc_even[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_odd[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_even[1] = 0x3ffff;
dlsch->harq_processes[0]->rb_alloc_odd[1] = 0x3ffff;
break;
case 100:
dlsch->harq_processes[0]->rb_alloc[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc[1] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc[2] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc[3] = 0xf;
dlsch->harq_processes[0]->rb_alloc_even[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_odd[0] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_even[1] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_odd[1] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_even[2] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_odd[2] = 0xffffffff;
dlsch->harq_processes[0]->rb_alloc_even[3] = 0xf;
dlsch->harq_processes[0]->rb_alloc_odd[3] = 0xf;
break;
}
}
......
......@@ -852,6 +852,7 @@ void dlsch_detection_mrc(LTE_DL_FRAME_PARMS *frame_parms,
@param rb_alloc RB allocation vector
@param symbol Symbol to extract
@param subframe Subframe number
@param vrb_type Flag to indicate distributed VRB type
@param high_speed_flag
@param frame_parms Pointer to frame descriptor
*/
......@@ -1232,7 +1233,7 @@ uint32_t get_TBS_UL(uint8_t mcs, uint16_t nb_rb);
@param vrb_type VRB type (0=localized,1=distributed)
@param rb_alloc_dci rballoc field from DCI
*/
uint32_t get_rballoc(uint8_t vrb_type,uint16_t rb_alloc_dci);
uint32_t get_rballoc(vrb_t vrb_type,uint16_t rb_alloc_dci);
/* \brief Return bit-map of resource allocation for a given DCI rballoc (RIV format) and vrb type
@returns Transmission mode (1-7)
......@@ -1341,7 +1342,8 @@ void ulsch_extract_rbs_single(int32_t **rxdataF,
uint8_t subframe2harq_pid(LTE_DL_FRAME_PARMS *frame_parms,frame_t frame,uint8_t subframe);
uint8_t subframe2harq_pid_eNBrx(LTE_DL_FRAME_PARMS *frame_parms,uint8_t subframe);
int generate_ue_dlsch_params_from_dci(uint8_t subframe,
int generate_ue_dlsch_params_from_dci(int frame,
uint8_t subframe,
void *dci_pdu,
rnti_t rnti,
DCI_format_t dci_format,
......
lte_dfts: lte_dfts.c
gcc -O3 -mavx2 -o lte_dfts lte_dfts.c time_meas.c file_output.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR/COMMON -DUSER_MODE -DMR_MAIN -DNB_ANTENNAS_RX=1 # -DD256STATS #-DD64STATS
gcc -O2 -mavx2 -g -ggdb -o lte_dfts lte_dfts.c time_meas.c file_output.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR/COMMON -DUSER_MODE -DMR_MAIN -DNB_ANTENNAS_RX=1 # -DD256STATS #-DD64STATS
lte_dfts.s: lte_dfts.c
gcc -O2 -mavx2 -S lte_dfts.c time_meas.c file_output.c ../../SIMULATION/TOOLS/taus.c -I$$OPENAIR1_DIR -I$$OPENAIR_TARGETS -I$$OPENAIR2_DIR/COMMON -DUSER_MODE -DMR_MAIN -DNB_ANTENNAS_RX=1 # -DD256STATS #-DD64STATS
dft_cycles: lte_dfts
./lte_dfts | egrep cycles
......@@ -493,7 +493,7 @@ void phy_scope_UE(FD_lte_phy_scope_ue *form,
if (phy_vars_ue->dlsch_ue[eNB_id][0]!=NULL) {
coded_bits_per_codeword = get_G(frame_parms,
phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->nb_rb,
phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->rb_alloc,
phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->rb_alloc_even,
get_Qm(mcs),
phy_vars_ue->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->Nl,
num_pdcch_symbols,
......
......@@ -130,8 +130,6 @@ static inline void stop_meas(time_stats_t *ts)
static inline void reset_meas(time_stats_t *ts) {
static int cpu_freq_set=0;
ts->trials=0;
ts->diff=0;
ts->diff_now=0;
......
......@@ -68,6 +68,8 @@ typedef enum {TDD=1,FDD=0} lte_frame_type_t;
typedef enum {EXTENDED=1,NORMAL=0} lte_prefix_type_t;
typedef enum {LOCALIZED=0,DISTRIBUTED=1} vrb_t;
/// Enumeration for parameter PHICH-Duration \ref PHICH_CONFIG_COMMON::phich_duration.
typedef enum {
normal=0,
......
......@@ -63,6 +63,9 @@
# include <smmintrin.h>
#endif
#ifdef __AVX2__
# include <immintrin.h>
#endif
// ------------------------------------------------
// compatibility functions if SSE3 or SSE4 is not available
......
This diff is collapsed.
......@@ -3043,6 +3043,7 @@ PMI_FEEDBACK:
if ((dci_alloc_rx[i].rnti == n_rnti) &&
(generate_ue_dlsch_params_from_dci(0,
0,
dci_alloc_rx[i].dci_pdu,
dci_alloc_rx[i].rnti,
dci_alloc_rx[i].format,
......@@ -3055,7 +3056,7 @@ PMI_FEEDBACK:
//dump_dci(&PHY_vars_UE->lte_frame_parms,&dci_alloc_rx[i]);
coded_bits_per_codeword = get_G(&PHY_vars_eNB->lte_frame_parms,
PHY_vars_UE->dlsch_ue[0][0]->harq_processes[PHY_vars_UE->dlsch_ue[0][0]->current_harq_pid]->nb_rb,
PHY_vars_UE->dlsch_ue[0][0]->harq_processes[PHY_vars_UE->dlsch_ue[0][0]->current_harq_pid]->rb_alloc,
PHY_vars_UE->dlsch_ue[0][0]->harq_processes[PHY_vars_UE->dlsch_ue[0][0]->current_harq_pid]->rb_alloc_even,
get_Qm(PHY_vars_UE->dlsch_ue[0][0]->harq_processes[PHY_vars_UE->dlsch_ue[0][0]->current_harq_pid]->mcs),
PHY_vars_UE->dlsch_ue[0][0]->harq_processes[PHY_vars_UE->dlsch_ue[0][0]->current_harq_pid]->Nl,
PHY_vars_UE->lte_ue_pdcch_vars[0]->num_pdcch_symbols,
......@@ -3099,6 +3100,7 @@ PMI_FEEDBACK:
case 1:
case 2:
generate_ue_dlsch_params_from_dci(0,
0,
&DLSCH_alloc_pdu_1[0],
(common_flag==0)? C_RNTI : SI_RNTI,
(common_flag==0)? format1 : format1A,
......@@ -3113,6 +3115,7 @@ PMI_FEEDBACK:
case 3:
// printf("Rate: TM3 (before) round %d (%d) first_tx %d\n",round,PHY_vars_UE->dlsch_ue[0][0]->harq_processes[0]->round,PHY_vars_UE->dlsch_ue[0][0]->harq_processes[0]->first_tx);
generate_ue_dlsch_params_from_dci(0,
0,
&DLSCH_alloc_pdu_1[0],
(common_flag==0)? C_RNTI : SI_RNTI,
(common_flag==0)? format2A : format1A,
......@@ -3127,6 +3130,7 @@ PMI_FEEDBACK:
case 4:
generate_ue_dlsch_params_from_dci(0,
0,
&DLSCH_alloc_pdu_1[0],
(common_flag==0)? C_RNTI : SI_RNTI,
(common_flag==0)? format2 : format1A,
......@@ -3141,6 +3145,7 @@ PMI_FEEDBACK:
case 5:
case 6:
generate_ue_dlsch_params_from_dci(0,
0,
&DLSCH_alloc_pdu2_1E[0],
C_RNTI,
format1E_2A_M10PRB,
......@@ -3389,7 +3394,7 @@ PMI_FEEDBACK:
dlsch0_ue_harq = PHY_vars_UE->dlsch_ue[eNB_id][0]->harq_processes[PHY_vars_UE->dlsch_ue[eNB_id][0]->current_harq_pid];
dlsch0_eNB_harq = PHY_vars_UE->dlsch_eNB[eNB_id]->harq_processes[PHY_vars_UE->dlsch_ue[eNB_id][0]->current_harq_pid];
dlsch0_eNB_harq->mimo_mode = LARGE_CDD;
dlsch0_eNB_harq->rb_alloc[0] = dlsch0_ue_harq->rb_alloc[0];
dlsch0_eNB_harq->rb_alloc[0] = dlsch0_ue_harq->rb_alloc_even[0];
dlsch0_eNB_harq->nb_rb = dlsch0_ue_harq->nb_rb;
dlsch0_eNB_harq->mcs = dlsch0_ue_harq->mcs;
dlsch0_eNB_harq->rvidx = dlsch0_ue_harq->rvidx;
......
......@@ -554,7 +554,7 @@ int main(int argc, char **argv)
for (i=1; i<64; i++) {
if (preamble_energy_max < preamble_energy_list[i]) {
// printf("preamble %d => %d\n",i,preamble_energy_list[i]);
// printf("preamble %d => %d\n",i,preamble_energy_list[i]);
preamble_energy_max = preamble_energy_list[i];
preamble_max = i;
}
......
......@@ -422,6 +422,17 @@ int trx_eth_reset_stats(openair0_device* device) {
}
int openair0_set_gains(openair0_device* device,
openair0_config_t *openair0_cfg) {
return(0);
}
int openair0_set_frequencies(openair0_device* device, openair0_config_t *openair0_cfg, int dummy) {
return(0);
}
void trx_eth_end(openair0_device *device) {
......
......@@ -1631,8 +1631,10 @@ static void* eNB_thread( void* arg )
int frame = 0;
#ifndef EXMIMO
spp = openair0_cfg[0].samples_per_packet;
tx_pos=spp*openair0_cfg[0].tx_delay;
#endif
while (!oai_exit) {
start_meas( &softmodem_stats_mt );
......
......@@ -175,9 +175,9 @@ static const eutra_band_t eutra_bands[] = {
{12, 698 * MHz, 716 * MHz, 728 * MHz, 746 * MHz, FDD},
{13, 777 * MHz, 787 * MHz, 746 * MHz, 756 * MHz, FDD},
{14, 788 * MHz, 798 * MHz, 758 * MHz, 768 * MHz, FDD},
{17, 704 * MHz, 716 * MHz, 734 * MHz, 746 * MHz, FDD},
{20, 832 * MHz, 862 * MHz, 791 * MHz, 821 * MHz, FDD},
{22, 3510 * MHz, 3590 * MHz, 3410 * MHz, 3490 * MHz, FDD},
{33, 1900 * MHz, 1920 * MHz, 1900 * MHz, 1920 * MHz, TDD},
{34, 2010 * MHz, 2025 * MHz, 2010 * MHz, 2025 * MHz, TDD},
{35, 1850 * MHz, 1910 * MHz, 1850 * MHz, 1910 * MHz, TDD},
......
......@@ -152,7 +152,7 @@ static void * rx_pdsch_thread(void *param)
harq_pid = UE->dlsch_ue[eNB_id][0]->current_harq_pid;
UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->G = get_G(&UE->lte_frame_parms,
UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->nb_rb,
UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->rb_alloc,
UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->rb_alloc_even,
get_Qm(UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->mcs),
UE->dlsch_ue[eNB_id][0]->harq_processes[harq_pid]->Nl,
UE->lte_ue_pdcch_vars[eNB_id]->num_pdcch_symbols,
......
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