Commit 2dfe84a7 authored by Florian Kaltenberger's avatar Florian Kaltenberger

bugfixing for UL. Remaining problems: CCE allocations in subframe 5 lead to...

bugfixing for UL. Remaining problems: CCE allocations in subframe 5 lead to occasional illegal DCI allocations (affects UL DCI which is missed by UE). waveform compliance with CQI in ULSCH.
parent 15cd4ab0
...@@ -7598,9 +7598,9 @@ int generate_eNB_ulsch_params_from_dci(void *dci_pdu, ...@@ -7598,9 +7598,9 @@ int generate_eNB_ulsch_params_from_dci(void *dci_pdu,
break; break;
} }
} else { } else {
ulsch->harq_processes[harq_pid]->O_RI = 0;//1; ulsch->harq_processes[harq_pid]->O_RI = 0;
ulsch->harq_processes[harq_pid]->Or2 = 0; ulsch->harq_processes[harq_pid]->Or2 = 0;
ulsch->harq_processes[harq_pid]->Or1 = 0;//sizeof_HLC_subband_cqi_nopmi_5MHz; ulsch->harq_processes[harq_pid]->Or1 = 0;
ulsch->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi; ulsch->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi;
} }
......
...@@ -1466,7 +1466,6 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB, ...@@ -1466,7 +1466,6 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB,
nseq_PHICH = ((ulsch_eNB[UE_id]->harq_processes[harq_pid]->first_rb/Ngroup_PHICH) + nseq_PHICH = ((ulsch_eNB[UE_id]->harq_processes[harq_pid]->first_rb/Ngroup_PHICH) +
ulsch_eNB[UE_id]->harq_processes[harq_pid]->n_DMRS)%(2*NSF_PHICH); ulsch_eNB[UE_id]->harq_processes[harq_pid]->n_DMRS)%(2*NSF_PHICH);
//#ifdef DEBUG_PHICH
LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d subframe %d Generating PHICH, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d dci_alloc %d)\n", LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d subframe %d Generating PHICH, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d dci_alloc %d)\n",
phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx, phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,
subframe,ngroup_PHICH,Ngroup_PHICH,nseq_PHICH, subframe,ngroup_PHICH,Ngroup_PHICH,nseq_PHICH,
...@@ -1474,7 +1473,6 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB, ...@@ -1474,7 +1473,6 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB,
ulsch_eNB[UE_id]->harq_processes[harq_pid]->first_rb, ulsch_eNB[UE_id]->harq_processes[harq_pid]->first_rb,
ulsch_eNB[UE_id]->harq_processes[harq_pid]->dci_alloc); ulsch_eNB[UE_id]->harq_processes[harq_pid]->dci_alloc);
//#endif
if (ulsch_eNB[UE_id]->Msg3_active == 1) { if (ulsch_eNB[UE_id]->Msg3_active == 1) {
LOG_D(PHY,"[eNB %d][PUSCH %d][RAPROC] Frame %d, subframe %d: Generating Msg3 PHICH for UE %d, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d\n", LOG_D(PHY,"[eNB %d][PUSCH %d][RAPROC] Frame %d, subframe %d: Generating Msg3 PHICH for UE %d, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d\n",
phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe, phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe,
...@@ -1509,12 +1507,10 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB, ...@@ -1509,12 +1507,10 @@ void generate_phich_top(PHY_VARS_eNB *phy_vars_eNB,
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH NACK / (no format0 DCI) Setting subframe_scheduling_flag\n", LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH NACK / (no format0 DCI) Setting subframe_scheduling_flag\n",
phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe); phy_vars_eNB->Mod_id,harq_pid,phy_vars_eNB->proc[sched_subframe].frame_tx,subframe);
ulsch_eNB[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1; ulsch_eNB[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
// ulsch_eNB[UE_id]->harq_processes[harq_pid]->Ndi = 0;
// ulsch_eNB[UE_id]->harq_processes[harq_pid]->round++; //this is already done in phy_procedures
ulsch_eNB[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch_eNB[UE_id]->harq_processes[harq_pid]->round&3]; ulsch_eNB[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch_eNB[UE_id]->harq_processes[harq_pid]->round&3];
ulsch_eNB[UE_id]->harq_processes[harq_pid]->O_RI = 0; ulsch_eNB[UE_id]->harq_processes[harq_pid]->O_RI = 0;
ulsch_eNB[UE_id]->harq_processes[harq_pid]->Or2 = 0; ulsch_eNB[UE_id]->harq_processes[harq_pid]->Or2 = 0;
ulsch_eNB[UE_id]->harq_processes[harq_pid]->Or1 = 0;//sizeof_HLC_subband_cqi_nopmi_5MHz; ulsch_eNB[UE_id]->harq_processes[harq_pid]->Or1 = 0;
ulsch_eNB[UE_id]->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi; ulsch_eNB[UE_id]->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi;
} else { } else {
......
...@@ -1058,18 +1058,21 @@ int32_t generate_prach( PHY_VARS_UE *phy_vars_ue, uint8_t eNB_id, uint8_t subfra ...@@ -1058,18 +1058,21 @@ int32_t generate_prach( PHY_VARS_UE *phy_vars_ue, uint8_t eNB_id, uint8_t subfra
} }
//__m128i mmtmpX0,mmtmpX1,mmtmpX2,mmtmpX3; //__m128i mmtmpX0,mmtmpX1,mmtmpX2,mmtmpX3;
void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_energy_list, uint16_t *preamble_delay_list, uint16_t Nf, uint8_t tdd_mapindex) void rx_prach(PHY_VARS_eNB *phy_vars_eNB,
uint8_t subframe,
uint16_t *preamble_energy_list,
uint16_t *preamble_delay_list,
uint16_t Nf,
uint8_t tdd_mapindex)
{ {
int i; int i;
lte_frame_type_t frame_type = phy_vars_eNB->lte_frame_parms.frame_type; lte_frame_type_t frame_type = phy_vars_eNB->lte_frame_parms.frame_type;
//uint8_t tdd_config = phy_vars_eNB->lte_frame_parms.tdd_config;
uint16_t rootSequenceIndex = phy_vars_eNB->lte_frame_parms.prach_config_common.rootSequenceIndex; uint16_t rootSequenceIndex = phy_vars_eNB->lte_frame_parms.prach_config_common.rootSequenceIndex;
uint8_t prach_ConfigIndex = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex; uint8_t prach_ConfigIndex = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.prach_ConfigIndex;
uint8_t Ncs_config = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig; uint8_t Ncs_config = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.zeroCorrelationZoneConfig;
uint8_t restricted_set = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag; uint8_t restricted_set = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.highSpeedFlag;
//uint8_t n_ra_prboffset = phy_vars_eNB->lte_frame_parms.prach_config_common.prach_ConfigInfo.prach_FreqOffset;
int16_t *prachF = phy_vars_eNB->lte_eNB_prach_vars.prachF; int16_t *prachF = phy_vars_eNB->lte_eNB_prach_vars.prachF;
int16_t **rxsigF = phy_vars_eNB->lte_eNB_prach_vars.rxsigF; int16_t **rxsigF = phy_vars_eNB->lte_eNB_prach_vars.rxsigF;
int16_t **prach_ifft = phy_vars_eNB->lte_eNB_prach_vars.prach_ifft; int16_t **prach_ifft = phy_vars_eNB->lte_eNB_prach_vars.prach_ifft;
...@@ -1086,12 +1089,8 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene ...@@ -1086,12 +1089,8 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene
uint16_t numshift=0; uint16_t numshift=0;
uint16_t *prach_root_sequence_map; uint16_t *prach_root_sequence_map;
uint8_t prach_fmt = get_prach_fmt(prach_ConfigIndex,frame_type); uint8_t prach_fmt = get_prach_fmt(prach_ConfigIndex,frame_type);
//uint8_t Nsp=2;
//uint8_t f_ra,t1_ra;
uint16_t N_ZC = (prach_fmt <4)?839:139; uint16_t N_ZC = (prach_fmt <4)?839:139;
uint8_t not_found; uint8_t not_found;
// LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->lte_frame_parms;
// uint16_t subframe_offset;
int k; int k;
uint16_t u; uint16_t u;
int16_t *Xu; int16_t *Xu;
...@@ -1107,7 +1106,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene ...@@ -1107,7 +1106,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene
for (aa=0; aa<nb_ant_rx; aa++) { for (aa=0; aa<nb_ant_rx; aa++) {
prach[aa] = (int16_t*)&phy_vars_eNB->lte_eNB_common_vars.rxdata[0][aa][subframe*phy_vars_eNB->lte_frame_parms.samples_per_tti-phy_vars_eNB->N_TA_offset]; prach[aa] = (int16_t*)&phy_vars_eNB->lte_eNB_common_vars.rxdata[0][aa][subframe*phy_vars_eNB->lte_frame_parms.samples_per_tti-phy_vars_eNB->N_TA_offset];
// remove_625_Hz(phy_vars_eNB,prach[aa]);
} }
// First compute physical root sequence // First compute physical root sequence
...@@ -1134,37 +1132,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene ...@@ -1134,37 +1132,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene
n_ra_prb = get_prach_prb_offset(&(phy_vars_eNB->lte_frame_parms),tdd_mapindex,Nf); n_ra_prb = get_prach_prb_offset(&(phy_vars_eNB->lte_frame_parms),tdd_mapindex,Nf);
prach_root_sequence_map = (prach_fmt < 4) ? prach_root_sequence_map0_3 : prach_root_sequence_map4; prach_root_sequence_map = (prach_fmt < 4) ? prach_root_sequence_map0_3 : prach_root_sequence_map4;
/*
// this code is now part of get_prach_prb_offset
if (frame_type == TDD) { // TDD
// adjust n_ra_prboffset for frequency multiplexing (p.36 36.211)
f_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[tdd_mapindex].f_ra;
if (prach_fmt < 4) {
if ((f_ra&1) == 0) {
n_ra_prb = n_ra_prboffset + 6*(f_ra>>1);
} else {
n_ra_prb = phy_vars_eNB->lte_frame_parms.N_RB_UL - 6 - n_ra_prboffset + 6*(f_ra>>1);
}
} else {
if ((tdd_config >2) && (tdd_config<6))
Nsp = 2;
t1_ra = tdd_preamble_map[prach_ConfigIndex][tdd_config].map[0].t1_ra;
if ((((Nf&1)*(2-Nsp)+t1_ra)&1) == 0) {
n_ra_prb = 6*f_ra;
} else {
n_ra_prb = phy_vars_eNB->lte_frame_parms.N_RB_UL - 6*(f_ra+1);
}
}
}
*/
// printf("NCS %d\n",NCS);
// PDP is oversampled, e.g. 1024 sample instead of 839 // PDP is oversampled, e.g. 1024 sample instead of 839
// Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839 // Adapt the NCS (zero-correlation zones) with oversampling factor e.g. 1024/839
NCS2 = (N_ZC==839) ? ((NCS<<10)/839) : ((NCS<<8)/139); NCS2 = (N_ZC==839) ? ((NCS<<10)/839) : ((NCS<<8)/139);
...@@ -1217,9 +1184,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene ...@@ -1217,9 +1184,6 @@ void rx_prach(PHY_VARS_eNB *phy_vars_eNB,uint8_t subframe,uint16_t *preamble_ene
break; break;
} }
// nsymb = (frame_parms->Ncp==0) ? 14:12;
// subframe_offset = (unsigned int)frame_parms->ofdm_symbol_size*subframe*nsymb;
preamble_offset_old = 99; preamble_offset_old = 99;
for (preamble_index=0 ; preamble_index<64 ; preamble_index++) { for (preamble_index=0 ; preamble_index<64 ; preamble_index++) {
......
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...@@ -99,7 +99,7 @@ uint64_t DLSCH_alloc_pdu_1[2]; ...@@ -99,7 +99,7 @@ uint64_t DLSCH_alloc_pdu_1[2];
#define CCCH_RB_ALLOC computeRIV(PHY_vars_eNB->lte_frame_parms.N_RB_UL,0,2) #define CCCH_RB_ALLOC computeRIV(PHY_vars_eNB->lte_frame_parms.N_RB_UL,0,2)
//#define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13 //#define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13
//#define DLSCH_RB_ALLOC 0x0001 //#define DLSCH_RB_ALLOC 0x0001
void do_OFDM_mod_l(mod_sym_t **txdataF, int32_t **txdata, uint16_t next_slot, LTE_DL_FRAME_PARMS *frame_parms) void do_OFDM_mod_l(int32_t **txdataF, int32_t **txdata, uint16_t next_slot, LTE_DL_FRAME_PARMS *frame_parms)
{ {
int aa, slot_offset, slot_offset_F; int aa, slot_offset, slot_offset_F;
...@@ -2111,7 +2111,7 @@ PMI_FEEDBACK: ...@@ -2111,7 +2111,7 @@ PMI_FEEDBACK:
// printf("Trial %d : Round %d, pmi_feedback %d \n",trials,round,pmi_feedback); // printf("Trial %d : Round %d, pmi_feedback %d \n",trials,round,pmi_feedback);
for (aa=0; aa<PHY_vars_eNB->lte_frame_parms.nb_antennas_tx; aa++) { for (aa=0; aa<PHY_vars_eNB->lte_frame_parms.nb_antennas_tx; aa++) {
memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNB_id][aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(mod_sym_t)); memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNB_id][aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t));
} }
if (input_fd==NULL) { if (input_fd==NULL) {
......
...@@ -131,7 +131,6 @@ int main(int argc, char **argv) ...@@ -131,7 +131,6 @@ int main(int argc, char **argv)
double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0; double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1=0.0;
uint8_t snr1set=0; uint8_t snr1set=0;
double snr_step=1,input_snr_step=1; double snr_step=1,input_snr_step=1;
//mod_sym_t **txdataF;
int **txdata; int **txdata;
double **s_re,**s_im,**r_re,**r_im; double **s_re,**s_im,**r_re,**r_im;
double iqim = 0.0; double iqim = 0.0;
...@@ -451,7 +450,7 @@ int main(int argc, char **argv) ...@@ -451,7 +450,7 @@ int main(int argc, char **argv)
//if (trials%100==0) //if (trials%100==0)
//eNB2UE[0]->first_run = 1; //eNB2UE[0]->first_run = 1;
eNB2UE->first_run = 1; eNB2UE->first_run = 1;
memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[0][0][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(mod_sym_t)); memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[0][0][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t));
generate_mch(PHY_vars_eNB,sched_subframe,input_buffer,0); generate_mch(PHY_vars_eNB,sched_subframe,input_buffer,0);
......
...@@ -57,11 +57,11 @@ PHY_VARS_UE *PHY_vars_UE; ...@@ -57,11 +57,11 @@ PHY_VARS_UE *PHY_vars_UE;
#define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13 #define DLSCH_RB_ALLOC 0x1fbf // igore DC component,RB13
mod_sym_t *dummybuf[4]; int32_t *dummybuf[4];
mod_sym_t dummy0[2048*14]; int32_t dummy0[2048*14];
mod_sym_t dummy1[2048*14]; int32_t dummy1[2048*14];
mod_sym_t dummy2[2048*14]; int32_t dummy2[2048*14];
mod_sym_t dummy3[2048*14]; int32_t dummy3[2048*14];
int main(int argc, char **argv) int main(int argc, char **argv)
...@@ -72,7 +72,6 @@ int main(int argc, char **argv) ...@@ -72,7 +72,6 @@ int main(int argc, char **argv)
int i,l,aa; int i,l,aa;
double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1; double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1;
uint8_t snr1set=0; uint8_t snr1set=0;
//mod_sym_t **txdataF;
int **txdata,**txdata1,**txdata2; int **txdata,**txdata1,**txdata2;
double **s_re,**s_im,**s_re1,**s_im1,**s_re2,**s_im2,**r_re,**r_im,**r_re1,**r_im1,**r_re2,**r_im2; double **s_re,**s_im,**s_re1,**s_im1,**s_re2,**s_im2,**r_re,**r_im,**r_re1,**r_im1,**r_re2,**r_im2;
double iqim = 0.0; double iqim = 0.0;
...@@ -603,7 +602,7 @@ int main(int argc, char **argv) ...@@ -603,7 +602,7 @@ int main(int argc, char **argv)
dummybuf[2] = dummy2; dummybuf[2] = dummy2;
dummybuf[3] = dummy3; dummybuf[3] = dummy3;
generate_pbch(&PHY_vars_eNB->lte_eNB_pbch, generate_pbch(&PHY_vars_eNB->lte_eNB_pbch,
(mod_sym_t**)dummybuf, (int32_t**)dummybuf,
AMP, AMP,
&PHY_vars_eNB->lte_frame_parms, &PHY_vars_eNB->lte_frame_parms,
pbch_pdu, pbch_pdu,
......
...@@ -410,7 +410,6 @@ int main(int argc, char **argv) ...@@ -410,7 +410,6 @@ int main(int argc, char **argv)
int i,l,aa; int i,l,aa;
double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1; double sigma2, sigma2_dB=0,SNR,snr0=-2.0,snr1;
//mod_sym_t **txdataF;
int **txdata; int **txdata;
double **s_re,**s_im,**r_re,**r_im; double **s_re,**s_im,**r_re,**r_im;
...@@ -773,8 +772,8 @@ int main(int argc, char **argv) ...@@ -773,8 +772,8 @@ int main(int argc, char **argv)
PHY_vars_eNB->ulsch_eNB[0] = new_eNB_ulsch(8,MAX_TURBO_ITERATIONS,N_RB_DL,0); PHY_vars_eNB->ulsch_eNB[0] = new_eNB_ulsch(MAX_TURBO_ITERATIONS,N_RB_DL,0);
PHY_vars_UE->ulsch_ue[0] = new_ue_ulsch(8,N_RB_DL,0); PHY_vars_UE->ulsch_ue[0] = new_ue_ulsch(N_RB_DL,0);
PHY_vars_eNB->proc[subframe].frame_tx = 0; PHY_vars_eNB->proc[subframe].frame_tx = 0;
...@@ -838,7 +837,7 @@ int main(int argc, char **argv) ...@@ -838,7 +837,7 @@ int main(int argc, char **argv)
// printf("DCI (SF %d): txdataF %p (0 %p)\n",subframe,&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][512*14*subframe],&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][0]); // printf("DCI (SF %d): txdataF %p (0 %p)\n",subframe,&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][512*14*subframe],&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][0]);
for (aa=0; aa<PHY_vars_eNB->lte_frame_parms.nb_antennas_tx_eNB; aa++) { for (aa=0; aa<PHY_vars_eNB->lte_frame_parms.nb_antennas_tx_eNB; aa++) {
memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(mod_sym_t)); memset(&PHY_vars_eNB->lte_eNB_common_vars.txdataF[eNb_id][aa][0],0,FRAME_LENGTH_COMPLEX_SAMPLES_NO_PREFIX*sizeof(int32_t));
/* /*
re_offset = PHY_vars_eNB->lte_frame_parms.first_carrier_offset; re_offset = PHY_vars_eNB->lte_frame_parms.first_carrier_offset;
......
...@@ -635,8 +635,8 @@ int main(int argc, char **argv) ...@@ -635,8 +635,8 @@ int main(int argc, char **argv)
UE2eNB->max_Doppler = maxDoppler; UE2eNB->max_Doppler = maxDoppler;
// NN: N_RB_UL has to be defined in ulsim // NN: N_RB_UL has to be defined in ulsim
PHY_vars_eNB->ulsch_eNB[0] = new_eNB_ulsch(8,max_turbo_iterations,N_RB_DL,0); PHY_vars_eNB->ulsch_eNB[0] = new_eNB_ulsch(max_turbo_iterations,N_RB_DL,0);
PHY_vars_UE->ulsch_ue[0] = new_ue_ulsch(8,N_RB_DL,0); PHY_vars_UE->ulsch_ue[0] = new_ue_ulsch(N_RB_DL,0);
// Create transport channel structures for 2 transport blocks (MIMO) // Create transport channel structures for 2 transport blocks (MIMO)
for (i=0; i<2; i++) { for (i=0; i<2; i++) {
......
...@@ -184,6 +184,12 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, ...@@ -184,6 +184,12 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
size_bytes = sizeof(DCI1A_1_5MHz_FDD_t); size_bytes = sizeof(DCI1A_1_5MHz_FDD_t);
size_bits = sizeof_DCI1A_1_5MHz_FDD_t; size_bits = sizeof_DCI1A_1_5MHz_FDD_t;
break; break;
case 15:/*
((DCI1A_2_5MHz_FDD_t*)DLSCH_dci)->type = 1;
((DCI1A_2_5MHz_FDD_t*)DLSCH_dci)->rballoc = 31;
size_bytes = sizeof(DCI1A_1_5MHz_FDD_t);
size_bits = sizeof_DCI1A_1_5MHz_FDD_t;*/
break;
case 25: case 25:
((DCI1A_5MHz_FDD_t*)DLSCH_dci)->type = 1; ((DCI1A_5MHz_FDD_t*)DLSCH_dci)->type = 1;
((DCI1A_5MHz_FDD_t*)DLSCH_dci)->rballoc = 511; ((DCI1A_5MHz_FDD_t*)DLSCH_dci)->rballoc = 511;
...@@ -196,6 +202,12 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag, ...@@ -196,6 +202,12 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
size_bytes = sizeof(DCI1A_10MHz_FDD_t); size_bytes = sizeof(DCI1A_10MHz_FDD_t);
size_bits = sizeof_DCI1A_10MHz_FDD_t; size_bits = sizeof_DCI1A_10MHz_FDD_t;
break; break;
case 75:
/* ((DCI1A_15MHz_FDD_t*)DLSCH_dci)->type = 1;
((DCI1A_15MHz_FDD_t*)DLSCH_dci)->rballoc = 2047;
size_bytes = sizeof(DCI1A_10MHz_FDD_t);
size_bits = sizeof_DCI1A_10MHz_FDD_t;*/
break;
case 100: case 100:
((DCI1A_20MHz_FDD_t*)DLSCH_dci)->type = 1; ((DCI1A_20MHz_FDD_t*)DLSCH_dci)->type = 1;
((DCI1A_20MHz_FDD_t*)DLSCH_dci)->rballoc = 8191; ((DCI1A_20MHz_FDD_t*)DLSCH_dci)->rballoc = 8191;
......
...@@ -183,21 +183,10 @@ void rx_sdu( ...@@ -183,21 +183,10 @@ void rx_sdu(
UE_list->UE_template[CC_idP][UE_id].bsr_info[lcgid] = (payload_ptr[0] & 0x3f); UE_list->UE_template[CC_idP][UE_id].bsr_info[lcgid] = (payload_ptr[0] & 0x3f);
// update buffer info // update buffer info
// old_buffer_info = UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid];
UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid]=BSR_TABLE[UE_list->UE_template[CC_idP][UE_id].bsr_info[lcgid]]; UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid]=BSR_TABLE[UE_list->UE_template[CC_idP][UE_id].bsr_info[lcgid]];
UE_list->UE_template[CC_idP][UE_id].ul_total_buffer+= UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid]; UE_list->UE_template[CC_idP][UE_id].ul_total_buffer= UE_list->UE_template[CC_idP][UE_id].ul_buffer_info[lcgid];
/*
if (UE_list->UE_template[CC_idP][UE_id].ul_total_buffer >= old_buffer_info)
UE_list->UE_template[CC_idP][UE_id].ul_total_buffer -= old_buffer_info;
else
UE_list->UE_template[CC_idP][UE_id].ul_total_buffer = 0;
*/
if (UE_list->UE_template[CC_idP][UE_id].ul_total_buffer >= 300000)
UE_list->UE_template[CC_idP][UE_id].ul_total_buffer = 300000;
PHY_vars_eNB_g[enb_mod_idP][CC_idP]->pusch_stats_bsr[UE_id][(frameP*10)+subframeP] = (payload_ptr[0] & 0x3f); PHY_vars_eNB_g[enb_mod_idP][CC_idP]->pusch_stats_bsr[UE_id][(frameP*10)+subframeP] = (payload_ptr[0] & 0x3f);
if (UE_id == UE_list->head) if (UE_id == UE_list->head)
...@@ -784,7 +773,7 @@ void schedule_ulsch_rnti(module_id_t module_idP, ...@@ -784,7 +773,7 @@ void schedule_ulsch_rnti(module_id_t module_idP,
UE_sched_ctrl->ul_failure_timer); UE_sched_ctrl->ul_failure_timer);
// reset the scheduling request // reset the scheduling request
UE_template->ul_SR = 0; UE_template->ul_SR = 0;
aggregation = process_ue_cqi(module_idP,UE_id); // =2 by default!! aggregation = process_ue_cqi(module_idP,UE_id);
status = mac_eNB_get_rrc_status(module_idP,rnti); status = mac_eNB_get_rrc_status(module_idP,rnti);
if (status < RRC_CONNECTED) if (status < RRC_CONNECTED)
cqi_req = 0; cqi_req = 0;
...@@ -838,7 +827,7 @@ void schedule_ulsch_rnti(module_id_t module_idP, ...@@ -838,7 +827,7 @@ void schedule_ulsch_rnti(module_id_t module_idP,
UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power; UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul; UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1=UE_template->pre_assigned_mcs_ul;
mcs = cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS mcs = cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
if ((cqi_req==1) && (mcs==20)) { if ((cqi_req==1) && (mcs>19)) {
mcs=19; mcs=19;
} }
if (UE_template->pre_allocated_rb_table_index_ul >=0) { if (UE_template->pre_allocated_rb_table_index_ul >=0) {
......
...@@ -119,6 +119,7 @@ const char* eurecomVariablesNames[] = { ...@@ -119,6 +119,7 @@ const char* eurecomVariablesNames[] = {
"mp_free", "mp_free",
"ue_inst_cnt_rx", "ue_inst_cnt_rx",
"ue_inst_cnt_tx", "ue_inst_cnt_tx",
"dci_info",
"ue0_BSR", "ue0_BSR",
"ue0_BO", "ue0_BO",
"ue0_scheduled", "ue0_scheduled",
...@@ -133,6 +134,14 @@ const char* eurecomVariablesNames[] = { ...@@ -133,6 +134,14 @@ const char* eurecomVariablesNames[] = {
"ue0_rssi5", "ue0_rssi5",
"ue0_rssi6", "ue0_rssi6",
"ue0_rssi7", "ue0_rssi7",
"ue0_res0",
"ue0_res1",
"ue0_res2",
"ue0_res3",
"ue0_res4",
"ue0_res5",
"ue0_res6",
"ue0_res7",
"ue0_MCS0", "ue0_MCS0",
"ue0_MCS1", "ue0_MCS1",
"ue0_MCS2", "ue0_MCS2",
...@@ -157,6 +166,14 @@ const char* eurecomVariablesNames[] = { ...@@ -157,6 +166,14 @@ const char* eurecomVariablesNames[] = {
"ue0_ROUND5", "ue0_ROUND5",
"ue0_ROUND6", "ue0_ROUND6",
"ue0_ROUND7", "ue0_ROUND7",
"ue0_SFN0",
"ue0_SFN1",
"ue0_SFN2",
"ue0_SFN3",
"ue0_SFN4",
"ue0_SFN5",
"ue0_SFN6",
"ue0_SFN7",
}; };
const char* eurecomFunctionsNames[] = { const char* eurecomFunctionsNames[] = {
...@@ -238,6 +255,7 @@ const char* eurecomFunctionsNames[] = { ...@@ -238,6 +255,7 @@ const char* eurecomFunctionsNames[] = {
"macxface_phy_config_sib2_eNB", "macxface_phy_config_sib2_eNB",
"macxface_phy_config_dedicated_eNB", "macxface_phy_config_dedicated_eNB",
"phy_ue_compute_prach", "phy_ue_compute_prach",
"phy_enb_ulsch_msg3",
"phy_enb_ulsch_decoding0", "phy_enb_ulsch_decoding0",
"phy_enb_ulsch_decoding1", "phy_enb_ulsch_decoding1",
"phy_enb_ulsch_decoding2", "phy_enb_ulsch_decoding2",
......
...@@ -91,6 +91,7 @@ typedef enum { ...@@ -91,6 +91,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLE_MP_FREE, VCD_SIGNAL_DUMPER_VARIABLE_MP_FREE,
VCD_SIGNAL_DUMPER_VARIABLES_UE_INST_CNT_RX, VCD_SIGNAL_DUMPER_VARIABLES_UE_INST_CNT_RX,
VCD_SIGNAL_DUMPER_VARIABLES_UE_INST_CNT_TX, VCD_SIGNAL_DUMPER_VARIABLES_UE_INST_CNT_TX,
VCD_SIGNAL_DUMPER_VARIABLES_DCI_INFO,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR, VCD_SIGNAL_DUMPER_VARIABLES_UE0_BSR,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO, VCD_SIGNAL_DUMPER_VARIABLES_UE0_BO,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED, VCD_SIGNAL_DUMPER_VARIABLES_UE0_SCHEDULED,
...@@ -105,6 +106,14 @@ typedef enum { ...@@ -105,6 +106,14 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI5, VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI5,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI6, VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI6,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI7, VCD_SIGNAL_DUMPER_VARIABLES_UE0_RSSI7,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES0,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES1,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES2,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES3,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES4,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES5,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES6,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_RES7,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS0, VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS0,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS1, VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS1,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS2, VCD_SIGNAL_DUMPER_VARIABLES_UE0_MCS2,
...@@ -129,6 +138,14 @@ typedef enum { ...@@ -129,6 +138,14 @@ typedef enum {
VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND5, VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND5,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND6, VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND6,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND7, VCD_SIGNAL_DUMPER_VARIABLES_UE0_ROUND7,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN0,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN1,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN2,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN3,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN4,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN5,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN6,
VCD_SIGNAL_DUMPER_VARIABLES_UE0_SFN7,
VCD_SIGNAL_DUMPER_VARIABLES_LAST, VCD_SIGNAL_DUMPER_VARIABLES_LAST,
VCD_SIGNAL_DUMPER_VARIABLES_END = VCD_SIGNAL_DUMPER_VARIABLES_LAST, VCD_SIGNAL_DUMPER_VARIABLES_END = VCD_SIGNAL_DUMPER_VARIABLES_LAST,
} vcd_signal_dump_variables; } vcd_signal_dump_variables;
...@@ -212,6 +229,7 @@ typedef enum { ...@@ -212,6 +229,7 @@ typedef enum {
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_CONFIG_SIB2_ENB, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_CONFIG_SIB2_ENB,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_CONFIG_DEDICATED_ENB, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_CONFIG_DEDICATED_ENB,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_UE_COMPUTE_PRACH,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_MSG3,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING0, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING0,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING1, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING1,
VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING2, VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_ULSCH_DECODING2,
......
...@@ -36,7 +36,7 @@ eNBs = ...@@ -36,7 +36,7 @@ eNBs =
nb_antennas_tx = 1; nb_antennas_tx = 1;
nb_antennas_rx = 1; nb_antennas_rx = 1;
tx_gain = 90; tx_gain = 90;
rx_gain = 127; rx_gain = 125;
prach_root = 0; prach_root = 0;
prach_config_index = 0; prach_config_index = 0;
prach_high_speed = "DISABLE"; prach_high_speed = "DISABLE";
...@@ -66,7 +66,7 @@ eNBs = ...@@ -66,7 +66,7 @@ eNBs =
pusch_p0_Nominal = -90; pusch_p0_Nominal = -90;
pusch_alpha = "AL1"; pusch_alpha = "AL1";
pucch_p0_Nominal = -108; pucch_p0_Nominal = -100;
msg3_delta_Preamble = 6; msg3_delta_Preamble = 6;
pucch_deltaF_Format1 = "deltaF2"; pucch_deltaF_Format1 = "deltaF2";
pucch_deltaF_Format1b = "deltaF3"; pucch_deltaF_Format1b = "deltaF3";
...@@ -140,10 +140,10 @@ eNBs = ...@@ -140,10 +140,10 @@ eNBs =
NETWORK_INTERFACES : NETWORK_INTERFACES :
{ {
ENB_INTERFACE_NAME_FOR_S1_MME = "eth0"; ENB_INTERFACE_NAME_FOR_S1_MME = "eth0";
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.215/24";
ENB_INTERFACE_NAME_FOR_S1U = "eth0"; ENB_INTERFACE_NAME_FOR_S1U = "eth0";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.213/24"; ENB_IPV4_ADDRESS_FOR_S1U = "192.168.12.215/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152 ENB_PORT_FOR_S1U = 2152; # Spec 2152
}; };
......
[*] [*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Thu Mar 17 23:50:10 2016 [*] Sun Apr 10 20:34:38 2016
[*] [*]
[dumpfile] "/tmp/openair_dump_eNB.vcd" [dumpfile] "/tmp/openair_dump_eNB.vcd"
[dumpfile_mtime] "Thu Mar 17 23:49:36 2016" [dumpfile_mtime] "Sun Apr 10 20:26:57 2016"
[dumpfile_size] 236045612 [dumpfile_size] 181182776
[savefile] "/home/papillon/openairinterface5g/targets/RT/USER/eNB_usrp.gtkw" [savefile] "/home/papillon/openairinterface5g/targets/RT/USER/eNB_usrp.gtkw"
[timestart] 10372000000 [timestart] 19787100000
[size] 1535 876 [size] 1535 876
[pos] -1 -1 [pos] -1 -1
*-29.793451 12619679774 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.793451 19795882832 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 284 [sst_width] 284
[signals_width] 238 [signals_width] 238
[sst_expanded] 1 [sst_expanded] 1
...@@ -51,82 +51,110 @@ functions.eNB_thread_tx9 ...@@ -51,82 +51,110 @@ functions.eNB_thread_tx9
functions.phy_procedures_eNb_tx functions.phy_procedures_eNb_tx
functions.phy_procedures_eNb_rx functions.phy_procedures_eNb_rx
@24 @24
variables.dci_info[63:0]
variables.ue0_BO[63:0] variables.ue0_BO[63:0]
@420 @420
variables.ue0_BSR[63:0] variables.ue0_BSR[63:0]
@421
variables.ue0_timing_advance[63:0] variables.ue0_timing_advance[63:0]
@28 @28
functions.macxface_initiate_ra_proc functions.macxface_initiate_ra_proc
functions.macxface_terminate_ra_proc functions.macxface_terminate_ra_proc
functions.phy_enb_ulsch_msg3
functions.macxface_SR_indication functions.macxface_SR_indication
@420 @420
variables.ue0_SR_ENERGY[63:0] variables.ue0_SR_ENERGY[63:0]
variables.ue0_SR_THRES[63:0] variables.ue0_SR_THRES[63:0]
@25
variables.dci_info[63:0]
@28 @28
functions.phy_enb_ulsch_decoding0 functions.phy_enb_ulsch_decoding0
@24
variables.ue0_res0[63:0]
@420 @420
variables.ue0_rssi0[63:0] variables.ue0_rssi0[63:0]
variables.ue0_MCS0[63:0] variables.ue0_MCS0[63:0]
variables.ue0_RB0[63:0] variables.ue0_RB0[63:0]
@24 @24
variables.ue0_ROUND0[63:0] variables.ue0_ROUND0[63:0]
variables.ue0_SFN0[63:0]
@28 @28
functions.phy_enb_ulsch_decoding1 functions.phy_enb_ulsch_decoding1
@24
variables.ue0_res1[63:0]
@420 @420
variables.ue0_rssi1[63:0] variables.ue0_rssi1[63:0]
variables.ue0_MCS1[63:0] variables.ue0_MCS1[63:0]
variables.ue0_RB1[63:0] variables.ue0_RB1[63:0]
@24 @24
variables.ue0_ROUND1[63:0] variables.ue0_ROUND1[63:0]
variables.ue0_SFN1[63:0]