Commit 434c9b98 authored by Guy De Souza's avatar Guy De Souza

DLSCH support functions/ physical channel up to layer mapping

parent a5a5e85f
......@@ -1293,8 +1293,8 @@ set(PHY_SRC_UE
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dci.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dci_tools.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch_tools.c
${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c
#${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_dlsch_tools.c
#${OPENAIR1_DIR}/PHY/NR_TRANSPORT/nr_tbs_tools.c
${OPENAIR1_DIR}/PHY/NR_REFSIG/nr_gold.c
${OPENAIR1_DIR}/PHY/TOOLS/file_output.c
${OPENAIR1_DIR}/PHY/TOOLS/cadd_vv.c
......
......@@ -156,6 +156,21 @@ typedef struct {
#define NFAPI_NR_SCH_CONFIG_SS_PBCH_BLOCK_POWER 0x5023
#define NFAPI_NR_SCH_CONFIG_N_SSB_CRB 0x5024
typedef struct {
nfapi_uint16_tlv_t data_scrambling_id;
nfapi_uint16_tlv_t mcs_table;
nfapi_uint16_tlv_t aggregation_factor;
nfapi_uint16_tlv_t prb_bundling_type;
nfapi_uint16_tlv_t rbg_size;
nfapi_uint16_tlv_t resource_allocation_config;
nfapi_uint16_tlv_t vrb_to_prb_interleaver;
nfapi_uint16_tlv_t code_block_groug_transmission;
nfapi_uint16_tlv_t x_overhead;
nfapi_uint16_tlv_t max_dci_codewords;
} nfapi_nr_pdsch_config_t;
#define NFAPI_NR_PDSCH_CONFIG_TAG
typedef struct {
nfapi_uint16_tlv_t prach_RootSequenceIndex; ///// L1 parameter 'PRACHRootSequenceIndex'
......@@ -170,12 +185,6 @@ typedef struct {
nfapi_uint16_tlv_t preambleReceivedTargetPower;
} nfapi_nr_rach_config_t;
typedef struct {
nfapi_uint16_tlv_t dmrs_typeA_position; ///// Position of (first) DL DM-RS
nfapi_uint16_tlv_t time_domain_alloc_k0; ///// L1 parameter 'K0'
nfapi_uint16_tlv_t time_domain_alloc_mapping_type; ///// L1 parameter 'Mapping-type'
} nfapi_nr_pdsch_config_t;
typedef struct {
nfapi_uint16_tlv_t groupHoppingEnabledTransformPrecoding; ///// L1 parameter 'Group-hopping-enabled-Transform-precoding'
nfapi_uint16_tlv_t msg3_DeltaPreamble; ///// L1 parameter 'Delta-preamble-msg3'
......@@ -229,8 +238,8 @@ typedef struct {
nfapi_nr_subframe_config_t subframe_config;
nfapi_nr_rf_config_t rf_config;
nfapi_nr_sch_config_t sch_config;
nfapi_nr_pdsch_config_t dlsch_config;
nfapi_nr_rach_config_t rach_config;
nfapi_nr_pdsch_config_t pdsch_config;
nfapi_nr_pusch_config_t pusch_config;
nfapi_nr_pucch_config_t pucch_config;
nfapi_nr_tdd_ul_dl_config_t tdd_ul_dl_config;
......@@ -473,13 +482,35 @@ typedef struct {
typedef struct {
nfapi_tl_t tl;
nfapi_nr_search_space_t sib1searchSpace;
nfapi_nr_coreset_t sib1ControlResourceSets;
nfapi_nr_search_space_t sibssearchSpace;
nfapi_nr_coreset_t sibsControlResourceSets;
nfapi_nr_search_space_t ra_SearchSpace;
nfapi_nr_coreset_t ra_ControlResourceSets;
uint16_t length;
uint8_t pdu_index;
uint16_t rnti;
uint8_t resource_allocation_type;
uint8_t virtual_resource_block_assignment_flag;
uint32_t resource_block_coding;
uint8_t modulation;
uint8_t redundancy_version;
uint8_t transport_blocks;
uint8_t transport_block_to_codeword_swap_flag;
uint8_t transmission_scheme;
uint8_t number_of_layers;
uint8_t number_of_subbands;
uint8_t codebook_index[NFAPI_MAX_NUM_SUBBANDS];
uint8_t ue_category_capacity;
uint8_t pa;
uint8_t delta_power_offset_index;
uint8_t ngap;
uint8_t nprb;
uint8_t transmission_mode;
uint8_t num_bf_prb_per_subband;
uint8_t num_bf_vector;
nfapi_bf_vector_t bf_vector[NFAPI_MAX_BF_VECTORS];
}nfapi_nr_dl_config_dlsch_pdu_rel15_t;
#define NFAPI_NR_DL_CONFIG_REQUEST_DLSCH_PDU_REL15_TAG
typedef struct {
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
} nfapi_nr_dl_config_dlsch_pdu;
typedef struct {
nfapi_tl_t tl;
......@@ -512,7 +543,7 @@ typedef struct {
union {
nfapi_nr_dl_config_dci_dl_pdu dci_dl_pdu;
nfapi_nr_dl_config_bch_pdu_rel15_t bch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu_rel15_t dlsch_pdu_rel15;
nfapi_nr_dl_config_dlsch_pdu dlsch_pdu;
nfapi_nr_dl_config_pch_pdu_rel15_t pch_pdu_rel15;
nfapi_nr_dl_config_nbch_pdu_rel15_t nbch_pdu_rel15;
nfapi_nr_dl_config_npdcch_pdu_rel15_t npdcch_pdu_rel15;
......
......@@ -30,4 +30,134 @@
* \warning
*/
#include "nr_dlsch.h"
#include "nr_dci.h"
void nr_pdsch_codeword_scrambling(uint32_t *in,
uint8_t size,
uint8_t q,
uint32_t Nid,
uint32_t n_RNTI,
uint32_t* out) {
uint8_t reset;
uint32_t x1, x2, s=0;
reset = 1;
x2 = (n_RNTI<<15) + (q<<14) + Nid;
for (int i=0; i<size; i++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
reset = 0;
}
*out ^= (((*in)>>i)&1) ^ ((s>>i)&1);
}
}
void nr_pdsch_codeword_modulation(uint32_t *in,
uint8_t Qm,
uint32_t length,
uint16_t *out) {
uint16_t offset = (Qm==2)? NR_MOD_TABLE_QPSK_OFFSET : (Qm==4)? NR_MOD_TABLE_QAM16_OFFSET : \
(Qm==6)? NR_MOD_TABLE_QAM64_OFFSET: (Qm==8)? NR_MOD_TABLE_QAM256_OFFSET : 0;
AssertFatal(offset, "Invalid modulation order %d\n", Qm);
for (int i=0; i<length/Qm; i++) {
uint8_t idx = 0, b_idx;
for (int j=0; j<Qm; j++) {
b_idx = (i*Qm+j)&0x1f;
if (i && (!b_idx))
in++;
idx ^= (((*in)>>b_idx)&1)<<(Qm-j);
}
out[i<<1] = nr_mod_table[(offset+idx)<<1];
out[(i<<1)+1] = nr_mod_table[((offset+idx)<<1)+1];
}
}
void nr_pdsch_layer_mapping(uint16_t **mod_symbs,
uint8_t n_codewords,
uint8_t n_layers,
uint16_t *n_symbs,
uint16_t **tx_layers) {
switch (n_layers) {
case 1:
memcpy((void*)tx_layers[0], (void*)mod_symbs[0], (n_symbs[0]<<1)*sizeof(uint16_t));
break;
case 2:
case 3:
case 4:
for (int i=0; i<n_symbs[0]/n_layers; i++)
for (int l=0; l<n_layers; l++) {
tx_layers[l][i<<1] = mod_symbs[0][(n_layers*i+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[0][((n_layers*i+l)<<1)+1];
}
break;
case 5:
for (int i=0; i<n_symbs[0]>>1; i++)
for (int l=0; l<2; l++) {
tx_layers[l][i<<1] = mod_symbs[0][((i<<1)+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[0][(((i<<1)+l)<<1)+1];
}
for (int i=0; i<n_symbs[1]/3; i++)
for (int l=2; l<5; l++) {
tx_layers[l][i<<1] = mod_symbs[1][(3*i+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[1][((3*i+l)<<1)+1];
}
break;
case 6:
for (int q=0; q<2; q++)
for (int i=0; i<n_symbs[q]/3; i++)
for (int l=0; l<3; l++) {
tx_layers[l][i<<1] = mod_symbs[q][(3*i+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[q][((3*i+l)<<1)+1];
}
break;
case 7:
for (int i=0; i<n_symbs[0]/3; i++)
for (int l=0; l<3; l++) {
tx_layers[l][i<<1] = mod_symbs[1][(3*i+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[1][((3*i+l)<<1)+1];
}
for (int i=0; i<n_symbs[1]/4; i++)
for (int l=3; l<7; l++) {
tx_layers[l][i<<1] = mod_symbs[0][((i<<2)+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[0][(((i<<2)+l)<<1)+1];
}
break;
case 8:
for (int q=0; q<2; q++)
for (int i=0; i<n_symbs[q]>>2; i++)
for (int l=0; l<3; l++) {
tx_layers[l][i<<1] = mod_symbs[q][((i<<2)+l)<<1];
tx_layers[l][(i<<1)+1] = mod_symbs[q][(((i<<2)+l)<<1)+1];
}
break;
default:
AsserFatal(0, "Invalid number of layers %d\n", n_layers);
}
}
uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t dlsch,
NR_gNB_DCI_ALLOC_t dci_alloc,
int32_t** txdataF,
int16_t amp,
NR_DL_FRAME_PARMS frame_parms,
nfapi_nr_config_request_t config) {
return 0;
}
......@@ -32,6 +32,7 @@
#include "PHY/defs_gNB.h"
extern short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT];
void nr_get_time_domain_allocation_type(nfapi_nr_config_request_t config,
NR_gNB_DCI_ALLOC_t dci_alloc,
......@@ -50,3 +51,21 @@ void nr_get_PRG_parms(NR_BWP_PARMS* bwp, NR_gNB_DCI_ALLOC_t dci_alloc, uint8_t p
uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
void nr_pdsch_codeword_scrambling(uint32_t *in,
uint8_t size,
uint8_t q,
uint32_t Nid,
uint32_t n_RNTI,
uint32_t* out);
void nr_pdsch_codeword_modulation(uint32_t *in,
uint8_t Qm,
uint32_t length,
uint16_t *out);
void nr_pdsch_layer_mapping(uint16_t **mod_symbs,
uint8_t n_codewords,
uint8_t n_layers,
uint16_t *n_symbs,
uint16_t **tx_layers);
......@@ -40,7 +40,10 @@ uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 49
616, 666, 719, 772, 822, 873, -1, 711, 754, 797, 841, 885, -1, 948};
uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \
378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772};
uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \
336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \
1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \
3104, 3240, 3368, 3496, 3624, 3752, 3824};
uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx) {
switch(table_idx) {
......@@ -68,7 +71,7 @@ uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx) {
break;
case 2:
return ((Imcs==20)?0xaaa00 : (Imcs==26)?0xe5200 : nr_target_code_rate_table3[Imcs]<<10);
return ((Imcs==20)?0xaaa00 : (Imcs==26)?0xe5200 : nr_target_code_rate_table2[Imcs]<<10);
break;
case 3:
......@@ -79,3 +82,18 @@ uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx) {
AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx);
}
}
static inline uint8_t is_codeword_disabled(uint8_t format, uint8_t Imcs, uint8_t rv) {
return ((format==NFAPI_NR_DL_DCI_FORMAT_1_1)&&(Imcs==26)&&(rv==1));
}
/*uint16_t nr_get_tbs(NR_gNB_DCI_ALLOC_t dci_alloc, nfapi_nr_config_request_t config) {
uint8_t rnti_type = dci_alloc.pdcch_params.rnti_type;
uint8_t N_PRB_oh = ((rnti_type==NFAPI_NR_RNTI_SI)||(rnti_type==NFAPI_NR_RNTI_RA)||(rnti_type==NFAPI_NR_RNTI_P))? 0 : \
(config.pdsch_config.);
uint16_t N_prime_RE = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS - N_PRB_oh;
LOG_I(MAC, "N_prime_RE %d for %d symbols %d DMRS per PRB and %d overhead\n", N_prime_RE, N_sh_symb, N_PRB_DMRS, N_PRB_oh);
}*/
......@@ -52,9 +52,12 @@
#define ONE_OVER_SQRT2_Q15 23170
#define ONE_OVER_TWO_Q15 16384
#define NR_MOD_TABLE_SIZE_SHORT 14
#define NR_MOD_TABLE_SIZE_SHORT 686
#define NR_MOD_TABLE_BPSK_OFFSET 1
#define NR_MOD_TABLE_QPSK_OFFSET 3
#define NR_MOD_TABLE_QAM16_OFFSET 7
#define NR_MOD_TABLE_QAM64_OFFSET 23
#define NR_MOD_TABLE_QAM256_OFFSET 87
#define NR_PSS_LENGTH 127
#define NR_SSS_LENGTH 127
......
......@@ -94,7 +94,29 @@ unsigned short config_frames[4] = {2,9,11,13};
// current status is that every UE has a DL scope for a SINGLE eNB (gnb_id=0)
// at eNB 0, an UL scope for every UE
short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,23170,23170,-23170,-23170,23170,23170,23170,-23170,-23170,23170,-23170,-23170};
short nr_mod_table[NR_MOD_TABLE_SIZE_SHORT] = {0,0,23170,23170,-23170,-23170,23170,23170,23170,-23170,-23170,23170,-23170,-23170,10362,10362,10362,31086,31086,10362,31086,31086,10362,-10362\
,10362,-31086,31086,-10362,31086,-31086,-10362,10362,-10362,31086,-31086,10362,-31086,31086,-10362,-10362,-10362,-31086,-31086,-10362,-31086,-31086,15169,15169,15169,5057,5057,15169,5057\
,5057,15169,25281,15169,35393,5057,25281,5057,35393,25281,15169,25281,5057,35393,15169,35393,5057,25281,25281,25281,35393,35393,25281,35393,35393,15169,-15169,15169,-5057,5057,-15169,5057\
,-5057,15169,-25281,15169,-35393,5057,-25281,5057,-35393,25281,-15169,25281,-5057,35393,-15169,35393,-5057,25281,-25281,25281,-35393,35393,-25281,35393,-35393,-15169,15169,-15169,5057,-5057\
,15169,-5057,5057,-15169,25281,-15169,35393,-5057,25281,-5057,35393,-25281,15169,-25281,5057,-35393,15169,-35393,5057,-25281,25281,-25281,35393,-35393,25281,-35393,35393,-15169,-15169,-15169\
,-5057,-5057,-15169,-5057,-5057,-15169,-25281,-15169,-35393,-5057,-25281,-5057,-35393,-25281,-15169,-25281,-5057,-35393,-15169,-35393,-5057,-25281,-25281,-25281,-35393,-35393,-25281,-35393\
,-35393,12566,12566,12566,17592,17592,12566,17592,17592,12566,7540,12566,2514,17592,7540,17592,2514,7540,12566,7540,17592,2514,12566,2514,17592,7540,7540,7540,2514,2514,7540,2514,2514,12566\
,27644,12566,22618,17592,27644,17592,22618,12566,32670,12566,37696,17592,32670,17592,37696,7540,27644,7540,22618,2514,27644,2514,22618,7540,32670,7540,37696,2514,32670,2514,37696,27644,12566\
,27644,17592,22618,12566,22618,17592,27644,7540,27644,2514,22618,7540,22618,2514,32670,12566,32670,17592,37696,12566,37696,17592,32670,7540,32670,2514,37696,7540,37696,2514,27644,27644,27644\
,22618,22618,27644,22618,22618,27644,32670,27644,37696,22618,32670,22618,37696,32670,27644,32670,22618,37696,27644,37696,22618,32670,32670,32670,37696,37696,32670,37696,37696,12566,-12566\
,12566,-17592,17592,-12566,17592,-17592,12566,-7540,12566,-2514,17592,-7540,17592,-2514,7540,-12566,7540,-17592,2514,-12566,2514,-17592,7540,-7540,7540,-2514,2514,-7540,2514,-2514,12566,-27644\
,12566,-22618,17592,-27644,17592,-22618,12566,-32670,12566,-37696,17592,-32670,17592,-37696,7540,-27644,7540,-22618,2514,-27644,2514,-22618,7540,-32670,7540,-37696,2514,-32670,2514,-37696\
,27644,-12566,27644,-17592,22618,-12566,22618,-17592,27644,-7540,27644,-2514,22618,-7540,22618,-2514,32670,-12566,32670,-17592,37696,-12566,37696,-17592,32670,-7540,32670,-2514,37696,-7540\
,37696,-2514,27644,-27644,27644,-22618,22618,-27644,22618,-22618,27644,-32670,27644,-37696,22618,-32670,22618,-37696,32670,-27644,32670,-22618,37696,-27644,37696,-22618,32670,-32670,32670\
,-37696,37696,-32670,37696,-37696,-12566,12566,-12566,17592,-17592,12566,-17592,17592,-12566,7540,-12566,2514,-17592,7540,-17592,2514,-7540,12566,-7540,17592,-2514,12566,-2514,17592,-7540\
,7540,-7540,2514,-2514,7540,-2514,2514,-12566,27644,-12566,22618,-17592,27644,-17592,22618,-12566,32670,-12566,37696,-17592,32670,-17592,37696,-7540,27644,-7540,22618,-2514,27644,-2514,22618\
,-7540,32670,-7540,37696,-2514,32670,-2514,37696,-27644,12566,-27644,17592,-22618,12566,-22618,17592,-27644,7540,-27644,2514,-22618,7540,-22618,2514,-32670,12566,-32670,17592,-37696,12566\
,-37696,17592,-32670,7540,-32670,2514,-37696,7540,-37696,2514,-27644,27644,-27644,22618,-22618,27644,-22618,22618,-27644,32670,-27644,37696,-22618,32670,-22618,37696,-32670,27644,-32670,22618\
,-37696,27644,-37696,22618,-32670,32670,-32670,37696,-37696,32670,-37696,37696,-12566,-12566,-12566,-17592,-17592,-12566,-17592,-17592,-12566,-7540,-12566,-2514,-17592,-7540,-17592,-2514,-7540\
,-12566,-7540,-17592,-2514,-12566,-2514,-17592,-7540,-7540,-7540,-2514,-2514,-7540,-2514,-2514,-12566,-27644,-12566,-22618,-17592,-27644,-17592,-22618,-12566,-32670,-12566,-37696,-17592,-32670\
,-17592,-37696,-7540,-27644,-7540,-22618,-2514,-27644,-2514,-22618,-7540,-32670,-7540,-37696,-2514,-32670,-2514,-37696,-27644,-12566,-27644,-17592,-22618,-12566,-22618,-17592,-27644,-7540,-27644\
,-2514,-22618,-7540,-22618,-2514,-32670,-12566,-32670,-17592,-37696,-12566,-37696,-17592,-32670,-7540,-32670,-2514,-37696,-7540,-37696,-2514,-27644,-27644,-27644,-22618,-22618,-27644,-22618,-22618\
,-27644,-32670,-27644,-37696,-22618,-32670,-22618,-37696,-32670,-27644,-32670,-22618,-37696,-27644,-37696,-22618,-32670,-32670,-32670,-37696,-37696,-32670,-37696,-37696};
FD_lte_phy_scope_ue *form_ue[NUMBER_OF_UE_MAX];
FD_lte_phy_scope_enb *form_enb[MAX_NUM_CCs][NUMBER_OF_UE_MAX];
......
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