Commit 45db11de authored by Guy De Souza's avatar Guy De Souza

Interface adaptations/ gNB Tx procedure update

parent fa03cace
......@@ -17,6 +17,16 @@ typedef struct {
uint32_t value;
} nfapi_uint32_tlv_t;
typedef struct {
nfapi_tl_t tl;
int64_t value;
} nfapi_int64_tlv_t;
typedef struct {
nfapi_tl_t tl;
uint64_t value;
} nfapi_uint64_tlv_t;
// nFAPI enums
typedef enum {
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE = 0,
......@@ -366,16 +376,16 @@ uint8_t *block_numbers;
typedef struct{
nfapi_uint16_tlv_t coreset_id;
nfapi_uint16_tlv_t frequency_domain_resources;
nfapi_uint16_tlv_t duration;
nfapi_uint16_tlv_t cce_reg_mapping_type;
nfapi_uint16_tlv_t reg_bundle_size;
nfapi_uint16_tlv_t interleaver_size;
nfapi_uint16_tlv_t shift_index;
nfapi_uint16_tlv_t precoder_granularity;
nfapi_uint16_tlv_t tci_state_id;
nfapi_uint16_tlv_t tci_present_in_dci;
nfapi_uint8_tlv_t coreset_id;
nfapi_uint64_tlv_t frequency_domain_resources;
nfapi_uint8_tlv_t duration;
nfapi_uint8_tlv_t cce_reg_mapping_type;
nfapi_uint8_tlv_t reg_bundle_size;
nfapi_uint8_tlv_t interleaver_size;
nfapi_uint8_tlv_t shift_index;
nfapi_uint8_tlv_t precoder_granularity;
nfapi_uint8_tlv_t tci_state_id;
nfapi_uint8_tlv_t tci_present_in_dci;
nfapi_uint16_tlv_t pdcch_dmrs_scrambling_id;
} nfapi_nr_coreset_t;
......@@ -411,6 +421,7 @@ typedef struct {
uint8_t nb_ss_sets_per_slot;
uint8_t sfn_mod2;
uint8_t search_space_type;
uint16_t scrambling_id;
nfapi_bf_vector_t bf_vector;
} nfapi_nr_dl_config_pdcch_parameters_rel15_t;
......
......@@ -20,7 +20,7 @@
*/
/*! \file PHY/NR_TRANSPORT/nr_dci.c
* \brief Implements DCI encoding/decoding and PDCCH TX/RX procedures (38.212/38.213/38.214). V15.1 2018-06.
* \brief Implements DCI encoding/decoding and PDCCH TX/RX procedures (38.212/38.213/38.214). V15.2.0 2018-06.
* \author Guy De Souza
* \date 2018
* \version 0.1
......@@ -130,21 +130,19 @@ uint8_t nr_get_dci_size(nfapi_nr_dci_format_e format,
return size;
}
void nr_pdcch_scrambling(NR_gNB_DCI_ALLOC_t dci_alloc,
nr_pdcch_vars_t pdcch_vars,
nfapi_nr_config_request_t config,
void nr_pdcch_scrambling(uint32_t *in,
uint8_t size,
uint32_t Nid,
uint32_t n_RNTI,
uint32_t* out) {
uint8_t reset;
uint32_t x1, x2, s=0;
uint32_t Nid = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_vars.dmrs_scrambling_id : config.sch_config.physical_cell_id.value;
uint32_t n_RNTI = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? dci_alloc.rnti : 0;
uint32_t *in = dci_alloc.dci_pdu;
reset = 1;
x2 = (n_RNTI<<16) + Nid;
for (int i=0; i<dci_alloc.size; i++) {
for (int i=0; i<size; i++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
reset = 0;
......@@ -154,13 +152,12 @@ void nr_pdcch_scrambling(NR_gNB_DCI_ALLOC_t dci_alloc,
}
uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
uint32_t *gold_pdcch_dmrs,
int32_t** txdataF,
int16_t amp,
NR_DL_FRAME_PARMS frame_parms,
nfapi_nr_config_request_t config,
nr_pdcch_vars_t pdcch_vars)
nfapi_nr_config_request_t config)
{
uint16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH<<1];
......@@ -169,17 +166,15 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
int k,l,k_prime,dci_idx, dmrs_idx;
nr_cce_t cce;
uint8_t n_rb = pdcch_vars.coreset_params.n_rb;
uint8_t rb_offset = pdcch_vars.coreset_params.n_symb;
uint8_t n_symb = pdcch_vars.coreset_params.rb_offset;
uint8_t first_slot = pdcch_vars.first_slot;
uint8_t first_symb = pdcch_vars.ss_params.first_symbol_idx;
/*First iteration: single DCI*/
NR_gNB_DCI_ALLOC_t dci_alloc = pdcch_vars.dci_alloc[0];
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params = dci_alloc.pdcch_params;
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if (pdcch_vars.coreset_params.config_type == nr_cset_config_pdcch_config)
gold_pdcch_dmrs += ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+rb_offset)*3/32;
if (pdcch_params.config_type == nr_cset_config_pdcch_config)
gold_pdcch_dmrs += ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*3/32;
for (int i=0; i<NR_MAX_PDCCH_DMRS_LENGTH>>1; i++) {
idx = ((((gold_pdcch_dmrs[(i<<1)>>5])>>((i<<1)&0x1f))&1)<<1) ^ (((gold_pdcch_dmrs[((i<<1)+1)>>5])>>(((i<<1)+1)&0x1f))&1);
......@@ -195,8 +190,10 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
//channel coding
// scrambling
uint32_t scrambled_payload[4];
nr_pdcch_scrambling(dci_alloc, pdcch_vars, config, scrambled_payload);
uint32_t scrambled_payload[4];
uint32_t Nid = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? pdcch_params.scrambling_id : config.sch_config.physical_cell_id.value;
uint32_t n_RNTI = (dci_alloc.search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC)? dci_alloc.rnti : 0;
nr_pdcch_scrambling(dci_alloc.dci_pdu, dci_alloc.size, Nid, n_RNTI, scrambled_payload);
// QPSK modulation
uint32_t mod_dci[NR_MAX_DCI_SIZE>>1];
......@@ -212,8 +209,8 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
/*The coreset is initialised
* in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset
* in time: by its first slot and its first symbol*/
uint8_t cset_start_sc = frame_parms.first_carrier_offset + ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+rb_offset)*NR_NB_SC_PER_RB;
uint8_t cset_start_symb = first_slot*frame_parms.symbols_per_slot + first_symb;
uint8_t cset_start_sc = frame_parms.first_carrier_offset + ((int)floor(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_params.rb_offset)*NR_NB_SC_PER_RB;
uint8_t cset_start_symb = pdcch_params.first_slot*frame_parms.symbols_per_slot + pdcch_params.first_symbol;
dci_idx = 0;
dmrs_idx = 0;
......@@ -222,10 +219,10 @@ uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
if (cset_start_sc >= frame_parms.ofdm_symbol_size)
cset_start_sc -= frame_parms.ofdm_symbol_size;
if (pdcch_vars.coreset_params.precoder_granularity == nr_cset_same_as_reg_bundle) {
if (pdcch_params.precoder_granularity == nr_cset_same_as_reg_bundle) {
for (int cce_idx=0; cce_idx<dci_alloc.L; cce_idx++){
cce = pdcch_vars.cce_list[cce_idx];
cce = dci_alloc.cce_list[cce_idx];
for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
k = cset_start_sc + cce.reg_list[reg_idx].start_sc_idx;
l = cset_start_symb + cce.reg_list[reg_idx].symb_idx;
......
......@@ -62,17 +62,6 @@ typedef struct {
nr_coreset_config_type_e config_type;
} nr_pdcch_coreset_params_t;
typedef struct {
uint8_t reg_idx;
uint8_t start_sc_idx;
uint8_t symb_idx;
} nr_reg_t;
typedef struct {
uint8_t cce_idx;
nr_reg_t reg_list[NR_NB_REG_PER_CCE];
} nr_cce_t;
typedef struct {
uint8_t first_slot;
uint8_t nb_slots;
......@@ -90,17 +79,17 @@ uint8_t nr_get_dci_size(nfapi_nr_dci_format_e format,
NR_BWP_PARMS* bwp,
nfapi_nr_config_request_t* config);
uint8_t nr_generate_dci_top(NR_gNB_DCI_ALLOC_t dci_alloc,
uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
uint32_t *gold_pdcch_dmrs,
int32_t** txdataF,
int16_t amp,
NR_DL_FRAME_PARMS frame_parms,
nfapi_nr_config_request_t config,
nr_pdcch_vars_t pdcch_vars);
nfapi_nr_config_request_t config);
void nr_pdcch_scrambling(NR_gNB_DCI_ALLOC_t dci_alloc,
nr_pdcch_vars_t pdcch_vars,
nfapi_nr_config_request_t config,
void nr_pdcch_scrambling(uint32_t *in,
uint8_t size,
uint32_t Nid,
uint32_t n_RNTI,
uint32_t* out);
#endif //__PHY_NR_TRANSPORT_DCI__H
......@@ -58,6 +58,10 @@ typedef struct {
nfapi_nr_search_space_type_e search_space_type;
/// Format
nfapi_nr_dci_format_e format;
/// PDCCH parameters
nfapi_nr_dl_config_pdcch_parameters_rel15_t pdcch_params;
/// CCE list
nr_cce_t cce_list[NR_MAX_PDCCH_AGG_LEVEL];
/// DCI pdu
uint32_t dci_pdu[4];
} NR_gNB_DCI_ALLOC_t;
......@@ -287,7 +291,7 @@ typedef struct PHY_VARS_gNB_s {
nfapi_preamble_pdu_t preamble_list[MAX_NUM_RX_PRACH_PREAMBLES];
Sched_Rsp_t Sched_INFO;
NR_gNB_PDCCH pdcch_vars[2];
NR_gNB_PDCCH pdcch_vars;
LTE_eNB_PHICH phich_vars[2];
NR_gNB_COMMON common_vars;
......
......@@ -133,6 +133,17 @@ typedef enum {
nr_cset_all_contiguous_rbs
} nr_coreset_precoder_granularity_type_e;
typedef struct {
uint8_t reg_idx;
uint8_t start_sc_idx;
uint8_t symb_idx;
} nr_reg_t;
typedef struct {
uint8_t cce_idx;
nr_reg_t reg_list[NR_NB_REG_PER_CCE];
} nr_cce_t;
typedef struct NR_DL_FRAME_PARMS {
/// frequency range
nr_frequency_range_e freq_range;
......
......@@ -60,7 +60,7 @@ void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu)
{
int idx = subframe&1;
NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars[idx];
NR_gNB_PDCCH *pdcch_vars = &gNB->pdcch_vars;
nfapi_nr_dl_config_dci_pdu_rel15_t *pdu = &dl_config_pdu->dci_dl_pdu_rel15;
LOG_D(PHY,"Frame %d, Subframe %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:subframe_tx:%d idx:%d pdcch_vars->num_dci:%d\n",frame,subframe, pdcch_vars->num_dci, proc->subframe_tx, idx, pdcch_vars->num_dci);
......@@ -121,6 +121,15 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
dl_config_pdu,
TX_req->tx_request_body.tx_pdu_list[dl_config_pdu->bch_pdu_rel15.pdu_index].segments[0].segment_data);
break;
case NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE:
handle_nfapi_nr_dci_dl_pdu(gNB,
frame, subframe,
proc,
dl_config_pdu);
gNB->pdcch_vars.num_dci++;
do_oai=1;
break;
}
}
......
......@@ -38,4 +38,8 @@
#include "SCHED_NR/sched_nr.h"
#include "nfapi_nr_interface.h"
void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO);
\ No newline at end of file
void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO);
void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
int frame, int subframe,
gNB_rxtx_proc_t *proc,
nfapi_nr_dl_config_request_pdu_t *dl_config_pdu);
......@@ -157,6 +157,7 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
int aa;
int frame=proc->frame_tx;
int subframe=proc->subframe_tx;
uint8_t num_dci=0;
NR_DL_FRAME_PARMS *fp=&gNB->frame_parms;
nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
......@@ -178,10 +179,18 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
nr_common_signal_procedures(gNB,frame, subframe);
//if (frame == 9)
//write_output("txdataF.m","txdataF",gNB->common_vars.txdataF[aa],fp->samples_per_frame_wCP, 1, 1);
}
num_dci = gNB->pdcch_vars.num_dci;
if (num_dci) {
LOG_I(PHY, "[gNB %d] Frame %d subframe %d \
Calling nr_generate_dci_top (number of DCI %d)\n", gNB->Mod_id, frame, subframe, num_dci);
//temporary DCI generation test
NR_gNB_DCI_ALLOC_t dci_alloc;
nr_pdcch_vars_t pdcch_vars;
nr_generate_dci_top(dci_alloc, gNB->nr_gold_pdcch_dmrs[0][0],gNB->common_vars.txdataF, 512, *fp, *cfg, pdcch_vars);
if (nfapi_mode == 0 || nfapi_mode == 1)
nr_generate_dci_top(gNB->pdcch_vars,
gNB->nr_gold_pdcch_dmrs[0][0],
gNB->common_vars.txdataF,
AMP, *fp, *cfg);
}
}
......@@ -416,6 +416,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
if((subframeP == 0) && (frameP & 7) == 0){
schedule_nr_mib(module_idP, frameP, subframeP);
}
/*
* Temporary DCI scheduling for PDCCH testing in the absence of phy-test mode and pending proper scheduling
* currently schedules PDCCH type 1 for RA-RNTI*/
/*
if (phy_test == 0){
// This schedules SI for legacy LTE and eMTC starting in subframeP
......
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