Commit 4c9c6f68 authored by Florian Kaltenberger's avatar Florian Kaltenberger

Merge remote-tracking branch 'origin/develop-nr' into ocp_nrsimulator

parents 9021be8c 98541813
......@@ -94,14 +94,21 @@ function build_on_vm {
echo "############################################################"
echo "Creating VM ($VM_NAME) on Ubuntu Cloud Image base"
echo "############################################################"
acquire_vm_create_lock
uvt-kvm create $VM_NAME release=xenial --memory $VM_MEMORY --cpu $VM_CPU --unsafe-caching --template ci-scripts/template-host.xml
fi
echo "Waiting for VM to be started"
uvt-kvm wait $VM_NAME --insecure
echo "Waiting for VM to be started"
uvt-kvm wait $VM_NAME --insecure
VM_IP_ADDR=`uvt-kvm ip $VM_NAME`
echo "$VM_NAME has for IP addr = $VM_IP_ADDR"
release_vm_create_lock
else
echo "Waiting for VM to be started"
uvt-kvm wait $VM_NAME --insecure
VM_IP_ADDR=`uvt-kvm ip $VM_NAME`
echo "$VM_NAME has for IP addr = $VM_IP_ADDR"
VM_IP_ADDR=`uvt-kvm ip $VM_NAME`
echo "$VM_NAME has for IP addr = $VM_IP_ADDR"
fi
echo "############################################################"
echo "Copying GIT repo into VM ($VM_NAME)"
......
......@@ -49,6 +49,35 @@ function create_usage {
echo ""
}
function acquire_vm_create_lock {
local FlockFile="/tmp/vmclone.lck"
local unlocked="0"
touch ${FlockFile} 2>/dev/null
if [[ $? -ne 0 ]]
then
echo "Cannot access lock file ${FlockFile}"
exit 2
fi
while [ $unlocked -eq 0 ]
do
exec 5>${FlockFile}
flock -nx 5
if [[ $? -ne 0 ]]
then
echo "Another instance of VM creation is running"
sleep 10
else
unlocked="1"
fi
done
chmod 666 ${FlockFile} 2>/dev/null
}
function release_vm_create_lock {
local FlockFile="/tmp/vmclone.lck"
rm -Rf ${FlockFile}
}
function create_vm {
echo "############################################################"
echo "OAI CI VM script"
......@@ -60,10 +89,12 @@ function create_vm {
echo "############################################################"
echo "Creating VM ($VM_NAME) on Ubuntu Cloud Image base"
echo "############################################################"
acquire_vm_create_lock
uvt-kvm create $VM_NAME release=xenial --memory $VM_MEMORY --cpu $VM_CPU --unsafe-caching --template ci-scripts/template-host.xml
echo "Waiting for VM to be started"
uvt-kvm wait $VM_NAME --insecure
VM_IP_ADDR=`uvt-kvm ip $VM_NAME`
echo "$VM_NAME has for IP addr = $VM_IP_ADDR"
release_vm_create_lock
}
......@@ -441,10 +441,16 @@ function run_test_on_vm {
echo "############################################################"
echo "Creating test EPC VM ($EPC_VM_NAME) on Ubuntu Cloud Image base"
echo "############################################################"
acquire_vm_create_lock
uvt-kvm create $EPC_VM_NAME release=xenial --unsafe-caching
echo "Waiting for VM to be started"
uvt-kvm wait $EPC_VM_NAME --insecure
release_vm_create_lock
else
echo "Waiting for VM to be started"
uvt-kvm wait $EPC_VM_NAME --insecure
fi
uvt-kvm wait $EPC_VM_NAME --insecure
EPC_VM_IP_ADDR=`uvt-kvm ip $EPC_VM_NAME`
echo "$EPC_VM_NAME has for IP addr = $EPC_VM_IP_ADDR"
scp -o StrictHostKeyChecking=no /etc/apt/apt.conf.d/01proxy ubuntu@$EPC_VM_IP_ADDR:/home/ubuntu
......
......@@ -2638,7 +2638,7 @@ if (${T_TRACER})
#all "add_executable" definitions (except tests, rb_tool, updatefw)
lte-softmodem lte-softmodem-nos1 lte-uesoftmodem lte-uesoftmodem-nos1
nr-softmodem nr-softmodem-nos1 nr-uesoftmodem nr-uesoftmodem-nos1
dlsim_tm4 dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
dlsim_tm4 nr_dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim
pdcchsim pucchsim prachsim syncsim ulsim
ldpctest polartest
#all "add_library" definitions
......
......@@ -1057,8 +1057,8 @@
(Test2: PBCH and synchronization, 106PBR),
(Test3: PBCH-only, 217 PRB),
(Test4: PBCH and synchronization, 217 RPB),
(Test5: PBCH-only, 217 PRB),
(Test6: PBCH and synchronization, 217 PRB)</desc>
(Test5: PBCH-only, 273 PRB),
(Test6: PBCH and synchronization, 273 PRB)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
......@@ -1071,12 +1071,51 @@
-s0 -S1 -n10 -I -R217
-s0 -S1 -n1000 -R273
-s0 -S1 -n10 -I -R273</main_exec_args>
<tags>nr_pbchsim.test1 nr_pbchsim.test2</tags>
<tags>nr_pbchsim.test1 nr_pbchsim.test2 nr_pbchsim.test3 nr_pbchsim.test4 nr_pbchsim.test5 nr_pbchsim.test6</tags>
<search_expr_true>PBCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
</testCase>
<testCase id="015105">
<class>execution</class>
<desc>nr_dlsim Test cases. (Test1: 106 PRB),
(Test2: 217 PRB),
(Test3: 273 PRB)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_dlsim.Rel15</main_exec>
<main_exec_args>-n100 -R106
-n100 -R217
-n100 -R273</main_exec_args>
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3</tags>
<search_expr_true>PDCCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
</testCase>
<testCase id="015106">
<class>execution</class>
<desc>nr_dlschsim Test cases. (Test1: 106 PRB),
(Test2: 217 PRB),
(Test3: 273 PRB)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
<pre_exec>$OPENAIR_DIR/cmake_targets/autotests/tools/free_mem.bash</pre_exec>
<pre_exec_args></pre_exec_args>
<main_exec> $OPENAIR_DIR/targets/bin/nr_dlsim.Rel15</main_exec>
<main_exec_args>-R 106 -m9 -s13 -n100
-R 217 -m15 -s15 -n100
-R 273 -m19 -s20 -n100</main_exec_args>
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3</tags>
<search_expr_true>PDSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
</testCase>
<testCase id="015110">
<class>execution</class>
......
#!/bin/sh
echo "building ctags for openair1 and openair2 ..."
ctags -e -R --exclude=openair1/DOCS/ --exclude=openair2/DOCS/ --exclude=openair2/RRC/CELLULAR/ --exclude=openair2/NAS/DRIVER/CELLULAR/ --exclude=openair2/SIMULATION/ --exclude=targets/DOCS/ --exclude=targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi
ctags -e -R --exclude=openair1/DOCS/ --exclude=openair2/DOCS/ --exclude=openair1/SIMULATION/ --exclude=targets/DOCS/ --exclude=targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi
......@@ -13,6 +13,9 @@
#define NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS 5
#define NFAPI_NR_MAX_NB_TCI_STATES_PDCCH 64
#define NFAPI_NR_MAX_NB_CORESETS 12
#define NFAPI_NR_MAX_NB_SEARCH_SPACES 40
// Extension to the generic structures for single tlv values
typedef struct {
......@@ -356,7 +359,8 @@ typedef enum {
typedef enum {
NFAPI_NR_CSET_CONFIG_MIB_SIB1=0,
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG, // implicit assumption of coreset Id other than 0
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG_CSET_0
} nfapi_nr_coreset_config_type_e;
typedef enum {
......@@ -364,6 +368,31 @@ typedef enum {
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
} nfapi_nr_coreset_precoder_granularity_type_e;
typedef enum {
NFAPI_NR_QCL_TYPE_A=0,
NFAPI_NR_QCL_TYPE_B,
NFAPI_NR_QCL_TYPE_C,
NFAPI_NR_QCL_TYPE_D
} nfapi_nr_qcl_type_e;
typedef enum {
NFAPI_NR_SS_PERIODICITY_SL1=1,
NFAPI_NR_SS_PERIODICITY_SL2=2,
NFAPI_NR_SS_PERIODICITY_SL4=4,
NFAPI_NR_SS_PERIODICITY_SL5=5,
NFAPI_NR_SS_PERIODICITY_SL8=8,
NFAPI_NR_SS_PERIODICITY_SL10=10,
NFAPI_NR_SS_PERIODICITY_SL16=16,
NFAPI_NR_SS_PERIODICITY_SL20=20,
NFAPI_NR_SS_PERIODICITY_SL40=40,
NFAPI_NR_SS_PERIODICITY_SL80=80,
NFAPI_NR_SS_PERIODICITY_SL160=160,
NFAPI_NR_SS_PERIODICITY_SL320=320,
NFAPI_NR_SS_PERIODICITY_SL640=640,
NFAPI_NR_SS_PERIODICITY_SL1280=1280,
NFAPI_NR_SS_PERIODICITY_SL2560=2560
} nfapi_nr_search_space_monitoring_periodicity_e;
typedef enum {
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_A=0,
NFAPI_NR_PDSCH_TIME_DOMAIN_ALLOC_TYPE_DEFAULT_B,
......@@ -496,9 +525,9 @@ typedef struct{
uint8_t css_format_2_2;
uint8_t css_format_2_3;
uint8_t uss_dci_formats;
uint8_t srs_monitoring_periodicity;
uint8_t slot_monitoring_periodicity;
uint8_t slot_monitoring_offset;
uint16_t srs_monitoring_periodicity;
uint16_t slot_monitoring_periodicity;
uint16_t slot_monitoring_offset;
uint16_t monitoring_symbols_in_slot;
uint16_t number_of_candidates[NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS];
} nfapi_nr_search_space_t;
......@@ -516,7 +545,7 @@ typedef struct {
uint8_t aggregation_level;
uint8_t n_rb;
uint8_t n_symb;
uint8_t rb_offset;
int8_t rb_offset;
uint8_t cr_mapping_type;
uint8_t reg_bundle_size;
uint8_t interleaver_size;
......
......@@ -1160,7 +1160,6 @@ uint32_t polar_decoder_int16(int16_t *input,
out[0]=Ar;
return(crc^rxcrc);
......
......@@ -54,13 +54,19 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
//int i;
unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10;
unsigned int rx_offset;
NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0];
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
uint16_t nb_rb_coreset = 24;
uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset+516;
NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns]][0];
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
uint16_t nb_rb_coreset = 0;
uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516;
uint16_t nb_rb_pdsch = 50;
uint8_t p=0;
uint8_t l0 = 2;
uint8_t l0 = pdcch_vars->coreset[0].duration;
uint64_t coreset_freq_dom = pdcch_vars->coreset[0].frequencyDomainResources;
for (int i = 0; i < 45; i++) {
if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> i) & 0x1) nb_rb_coreset++;
}
nb_rb_coreset = 6 * nb_rb_coreset;
//printf("corset duration %d nb_rb_coreset %d\n", l0, nb_rb_coreset);
void (*dft)(int16_t *,int16_t *, int);
int tmp_dft_in[8192] __attribute__ ((aligned (32))); // This is for misalignment issues for 6 and 15 PRBs
......@@ -104,9 +110,9 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
}
if (no_prefix) {
slot_offset = frame_parms->ofdm_symbol_size * (frame_parms->symbols_per_slot*frame_parms->slots_per_subframe) * (Ns>>1);
slot_offset = frame_parms->ofdm_symbol_size * (frame_parms->symbols_per_slot) * (Ns);
} else {
slot_offset = (frame_parms->samples_per_subframe) * (Ns>>1);
slot_offset = (frame_parms->samples_per_slot) * (Ns);
}
/*if (l<0 || l>=7-frame_parms->Ncp) {
......@@ -122,7 +128,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
memset(&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],0,frame_parms->ofdm_symbol_size*sizeof(int));
memset(&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],0,frame_parms->ofdm_symbol_size*sizeof(int));
rx_offset = sample_offset + slot_offset + nb_prefix_samples0 - SOFFSET;
// Align with 256 bit
......@@ -130,7 +136,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
#ifdef DEBUG_FEP
// if (ue->frame <100)
/*LOG_I(PHY,*/printf("slot_fep: frame %d: slot %d, symbol %d, nb_prefix_samples %d, nb_prefix_samples0 %d, slot_offset %d, sample_offset %d,rx_offset %d, frame_length_samples %d\n", ue->proc.proc_rxtx[(Ns>>1)&1].frame_rx,Ns, symbol,
/*LOG_I(PHY,*/printf("slot_fep: frame %d: slot %d, symbol %d, nb_prefix_samples %d, nb_prefix_samples0 %d, slot_offset %d, sample_offset %d,rx_offset %d, frame_length_samples %d\n", ue->proc.proc_rxtx[(Ns)&1].frame_rx,Ns, symbol,
nb_prefix_samples,nb_prefix_samples0,slot_offset,sample_offset,rx_offset,frame_length_samples);
#endif
......@@ -146,14 +152,14 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
(void *)&common_vars->rxdata[aa][rx_offset % frame_length_samples],
frame_parms->ofdm_symbol_size*sizeof(int));
dft((int16_t *)tmp_dft_in,
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
} else { // use dft input from RX buffer directly
#if UE_TIMING_TRACE
start_meas(&ue->rx_dft_stats);
#endif
dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
#if UE_TIMING_TRACE
stop_meas(&ue->rx_dft_stats);
#endif
......@@ -175,11 +181,11 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
(void *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
frame_parms->ofdm_symbol_size*sizeof(int));
dft((int16_t *)tmp_dft_in,
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
} else { // use dft input from RX buffer directly
dft((int16_t *)&common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
(int16_t *)&common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
}
#if UE_TIMING_TRACE
stop_meas(&ue->rx_dft_stats);
......
......@@ -32,6 +32,7 @@
//#define NR_PBCH_DMRS_LENGTH_DWORD 5
//#define NR_PBCH_DMRS_LENGTH 144
//#define DEBUG_PDCCH
#include "refsig_defs_ue.h"
#include "PHY/defs_nr_UE.h"
......
This diff is collapsed.
......@@ -61,11 +61,13 @@ void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m
else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
}
uint8_t cond = N_reg%(bsize*R);
AssertFatal(cond==0, "CCE to REG interleaving: Invalid configuration leading to non integer C\n");
C = N_reg/(bsize*R);
if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
AssertFatal((N_reg%(bsize*R))==0, "CCE to REG interleaving: Invalid configuration leading to non integer C (N_reg %d, bsize %d R %d)\n",
N_reg, bsize, R);
C = N_reg/(bsize*R);
}
tmp = L * (( Y + (m*N_cce)/(L*M_s_max) + n_CI ) % (N_cce/L));
tmp = L * (( Y + (m*N_cce)/(L*M_s_max) + n_CI ) % CEILIDIV(N_cce,L));
LOG_I(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d tmp %d\n", m, bsize, R, tmp);
for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
......@@ -189,14 +191,16 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
#endif
break;
case NFAPI_NR_RNTI_C:
case NFAPI_NR_RNTI_C:
// indicating a DL DCI format 1bit
pos++;
*dci_pdu |= (pdu_rel15->format_indicator&1)<<(dci_alloc->size-pos);
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize;
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_alloc->size-pos));
if (((pdu_rel15->frequency_domain_assignment+1)&1) ==0) //fsize are all 1 38.212 p86
{
......@@ -223,8 +227,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// Time domain assignment 4bit
pos+=4;
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->time_domain_assignment&0xf) << (dci_alloc->size-pos));
// VRB to PRB mapping 1bit
pos++;
......@@ -244,7 +247,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// HARQ process number 4bit
pos+=4;
*dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->harq_pid&0xf)<<(dci_alloc->size-pos));
// Downlink assignment index 2bit
pos+=2;
......@@ -252,15 +255,15 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// TPC command for scheduled PUCCH 2bit
pos+=2;
*dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->tpc&3)<<(dci_alloc->size-pos));
// PUCCH resource indicator 3bit
pos+=3;
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator&0x7)<<(dci_alloc->size-pos));
// PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3;
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos));
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_alloc->size-pos));
} //end else
break;
......
......@@ -28,6 +28,7 @@
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
#include "filt16a_32.h"
#include "T.h"
//#define DEBUG_PDSCH
//#define DEBUG_PDCCH
......@@ -271,8 +272,8 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t nushift;
int **dl_ch_estimates =ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset];
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF;
int **dl_ch_estimates =ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].dl_ch_estimates[eNB_offset];
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF;
nushift = 1;
ue->frame_parms.nushift = nushift;
......@@ -287,7 +288,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
k = coreset_start_subcarrier;
#ifdef DEBUG_PDCCH
printf("PDCCH Channel Estimation : ThreadId %d, eNB_offset %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n",ue->current_thread_id[Ns>>1], eNB_offset,ch_offset,ue->frame_parms.ofdm_symbol_size,
printf("PDCCH Channel Estimation : ThreadId %d, eNB_offset %d ch_offset %d, OFDM size %d, Ncp=%d, l=%d, Ns=%d, k=%d symbol %d\n",ue->current_thread_id[Ns], eNB_offset,ch_offset,ue->frame_parms.ofdm_symbol_size,
ue->frame_parms.Ncp,l,Ns,k, symbol);
#endif
......@@ -297,7 +298,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
// generate pilot
nr_pdcch_dmrs_rx(ue,eNB_offset,Ns,ue->nr_gold_pdcch[eNB_offset][Ns>>1][symbol], &pilot[0],2000,nb_rb_coreset);
nr_pdcch_dmrs_rx(ue,eNB_offset,Ns,ue->nr_gold_pdcch[eNB_offset][Ns][symbol], &pilot[0],2000,nb_rb_coreset);
for (aarx=0; aarx<ue->frame_parms.nb_antennas_rx; aarx++) {
......@@ -459,16 +460,16 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
break;
}
//if( (Ns== 2) && (l == 0))
if( (Ns== 1) && (l == 0))
{
// do ifft of channel estimate
for (aarx=0; aarx<ue->frame_parms.nb_antennas_rx; aarx++)
for (p=0; p<ue->frame_parms.nb_antenna_ports_eNB; p++) {
if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx])
if (ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].dl_ch_estimates[eNB_offset][(p<<1)+aarx])
{
LOG_D(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d \n", Ns, ue->current_thread_id[Ns>>1], l);
idft((int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset][(p<<1)+aarx][0],
(int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates_time[eNB_offset][(p<<1)+aarx],1);
LOG_D(PHY,"Channel Impulse Computation Slot %d ThreadId %d Symbol %d \n", Ns, ue->current_thread_id[Ns], l);
idft((int16_t*) &ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].dl_ch_estimates[eNB_offset][(p<<1)+aarx][0],
(int16_t*) ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].dl_ch_estimates_time[eNB_offset][(p<<1)+aarx],1);
}
}
}
......@@ -496,8 +497,8 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t nushift;
int **dl_ch_estimates =ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].dl_ch_estimates[eNB_offset];
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns>>1]].rxdataF;
int **dl_ch_estimates =ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].dl_ch_estimates[eNB_offset];
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF;
nushift = (p>>1)&1;
ue->frame_parms.nushift = nushift;
......
......@@ -806,7 +806,7 @@ int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
// For each BWP the number of CORESETs is limited to 3 (including initial CORESET Id=0 -> ControlResourceSetId (0..maxNrofControlReourceSets-1) (0..12-1)
//uint32_t n_BWP_start = 0;
//uint32_t n_rb_offset = 0;
uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB);
uint32_t n_rb_offset = pdcch_vars2->coreset[nb_coreset_active].rb_offset/*+(int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)*/;
// start time position for CORESET
// parameter symbol_mon is a 14 bits bitmap indicating monitoring symbols within a slot
uint8_t start_symbol = 0;
......@@ -1049,7 +1049,7 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8
x2 = (((1<<16)*n_rnti)+n_id); //mod 2^31 is implicit //this is c_init in 38.211 v15.1.0 Section 7.3.2.3
// x2 = (nr_tti_rx << 9) + frame_parms->Nid_cell; //this is c_init in 36.211 Sec 6.8.2
#ifdef NR_PDCCH_DCI_DEBUG
printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_unscrambling)-> (c_init=%d, n_id=%d, n_rnti=%d, length=%d)\n",x2,n_id,n_rnti,length);
//printf("\t\t<-NR_PDCCH_DCI_DEBUG (nr_pdcch_unscrambling)-> (c_init=%d, n_id=%d, n_rnti=%d, length=%d)\n",x2,n_id,n_rnti,length);
#endif
for (i = 0; i < length; i++) {
if ((i & 0x1f) == 0) {
......@@ -1119,13 +1119,13 @@ void nr_dci_decoding_procedure0(int s,
uint32_t *CCEmap1,
uint32_t *CCEmap2) {
uint16_t crc, CCEind, nCCE[3];
uint32_t crc, CCEind, nCCE[3];
uint32_t *CCEmap = NULL, CCEmap_mask = 0;
uint8_t L2 = (1 << L);
unsigned int Yk, nb_candidates = 0, i, m;
unsigned int CCEmap_cand;
int8_t decoderState=0;
uint32_t decoderState=0;
// A[p], p is the current active CORESET
uint16_t A[3]={39827,39829,39839};
......@@ -1362,17 +1362,17 @@ void nr_dci_decoding_procedure0(int s,
#endif
*/
uint32_t dci_estimation[4]={0};
uint64_t dci_estimation[2]={0};
nr_polar_init(&nrPolar_params, 1, sizeof_bits, L2);
t_nrPolar_paramsPtr currentPtrDCI=nr_polar_params(nrPolar_params, 1, sizeof_bits, L2);
decoderState = polar_decoder_int16(&pdcch_vars[eNB_id]->e_rx[CCEind*9*6*2],
(uint64_t*)dci_estimation,
dci_estimation,
currentPtrDCI);
crc = decoderState;
crc = decoderState;
//crc = (crc16(&dci_decoded_output[current_thread_id][0], sizeof_bits) >> 16) ^ extract_crc(&dci_decoded_output[current_thread_id][0], sizeof_bits);
#ifdef NR_PDCCH_DCI_DEBUG
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> ... we end function dci_decoding() with crc=%x\n",crc);
......@@ -1452,12 +1452,12 @@ void nr_dci_decoding_procedure0(int s,
dci_alloc[*dci_cnt].dci_pdu[1] = dci_estimation[1];
dci_alloc[*dci_cnt].dci_pdu[2] = dci_estimation[2];
dci_alloc[*dci_cnt].dci_pdu[3] = dci_estimation[3];
#ifdef NR_PDCCH_DCI_DEBUG
//#ifdef NR_PDCCH_DCI_DEBUG
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> rnti matches -> DCI FOUND !!! crc =>%x, sizeof_bits %d, sizeof_bytes %d \n",
dci_alloc[*dci_cnt].rnti, dci_alloc[*dci_cnt].dci_length, sizeof_bytes);
printf ("\t\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure0)-> dci_cnt %d (format_css %d crc_scrambled %d) L %d, firstCCE %d pdu[0] %x pdu[1] %x pdu[2] %x pdu[3] %x \n",
*dci_cnt, format_css,*crc_scrambled,dci_alloc[*dci_cnt].L, dci_alloc[*dci_cnt].firstCCE,dci_alloc[*dci_cnt].dci_pdu[0],dci_alloc[*dci_cnt].dci_pdu[1],dci_alloc[*dci_cnt].dci_pdu[2],dci_alloc[*dci_cnt].dci_pdu[3]);
#endif
//#endif
if ((format_css == cformat0_0_and_1_0) || (format_uss == uformat0_0_and_1_0)){
if ((*crc_scrambled == _p_rnti) || (*crc_scrambled == _si_rnti) || (*crc_scrambled == _ra_rnti)){
dci_alloc[*dci_cnt].format = format1_0;
......@@ -2676,7 +2676,7 @@ uint8_t nr_dci_decoding_procedure(int s,
printf("\t<-NR_PDCCH_DCI_DEBUG (nr_dci_decoding_procedure)-> calculating dci format size for common searchSpaces with format css_dci_format=%d, format_0_0_1_0_size_bits=%d, format_0_0_1_0_size_bytes=%d\n",
css_dci_format,format_0_0_1_0_size_bits,format_0_0_1_0_size_bytes);
#endif
for (int aggregationLevel = 3; aggregationLevel<4 ; aggregationLevel++) { // We fix aggregationLevel to 3 for testing=> nbr of CCE=8
for (int aggregationLevel = 0; aggregationLevel<5 ; aggregationLevel++) { // We fix aggregationLevel to 3 for testing=> nbr of CCE=8
//for (int aggregationLevel = 2; aggregationLevel<5 ; aggregationLevel++) {
// for aggregation level aggregationLevel. The number of candidates (for L2= 2^aggregationLevel) will be calculated in function nr_dci_decoding_procedure0
#ifdef NR_PDCCH_DCI_DEBUG
......
......@@ -52,7 +52,7 @@
//#define DEBUG_DCI
#define NR_PDCCH_DCI_TOOLS
#define NR_PDCCH_DCI_TOOLS_DEBUG
//#define NR_PDCCH_DCI_TOOLS_DEBUG
typedef unsigned __int128 uint128_t;
......
......@@ -618,10 +618,10 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
#ifdef DEBUG_PBCH
printf("xtra_byte %x payload %x\n", xtra_byte, payload);
for (i=0; i<(NR_POLAR_PBCH_PAYLOAD_BITS>>3); i++){
// printf("unscrambling pbch_a[%d] = %x \n", i,pbch_a[i]);
printf("[PBCH] decoder payload[%d] = %x\n",i,decoded_output[i]);
}
for (int i=0; i<(NR_POLAR_PBCH_PAYLOAD_BITS>>3); i++){
// printf("unscrambling pbch_a[%d] = %x \n", i,pbch_a[i]);
printf("[PBCH] decoder payload[%d] = %x\n",i,decoded_output[i]);
}
#endif
ue->dl_indication.rx_ind = &ue->rx_ind; // hang on rx_ind instance
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -1032,7 +1032,7 @@ typedef struct {
fapi_nr_dci_indication_t dci_ind;
// point to the current rxTx thread index
uint8_t current_thread_id[10];
uint8_t current_thread_id[40];
NR_UE_PDSCH *pdsch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX+1]; // two RxTx Threads
NR_UE_PDSCH_FLP *pdsch_vars_flp[NUMBER_OF_CONNECTED_eNB_MAX+1];
......
......@@ -736,7 +736,7 @@ typedef struct {
-- Corresponds to L1 parameter 'HoppingID' (see 38.211, section 6.3.2.2)
hoppingId BIT STRING (SIZE (10)) OPTIONAL, -- Need R
*/
uint16_t hoppingId;
uint32_t hoppingId;
/*
-- Power control parameter P0 for PUCCH transmissions. Value in dBm. Only even values (step size 2) allowed.
-- Corresponds to L1 parameter 'p0-nominal-pucch' (see 38.213, section 7.2)
......
File mode changed from 100644 to 100755
......@@ -49,6 +49,9 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_config_pdcch_parameters_rel15_t* p
nr_frequency_range_e freq_range,
uint8_t rmsi_pdcch_config,
uint8_t ssb_idx,
uint8_t k_ssb,
uint16_t sfn_ssb,
uint8_t n_ssb,
uint16_t nb_slots_per_frame,
uint16_t N_RB);
......
......@@ -48,11 +48,13 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
/// component carrier id
uint8_t cc_id = scheduled_response->CC_id;
uint32_t i;
int slot = scheduled_response->slot;
uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
if(scheduled_response != NULL){
// Note: we have to handle the thread IDs for this. To be revisited completely.
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[0][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[0][0][0];
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[0];
NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms;
PRACH_RESOURCES_t *prach_resources = PHY_vars_UE_g[module_id][cc_id]->prach_resources[0];
......@@ -88,8 +90,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size;
}else{ //CCE_REG_MAPPING_TYPE_NON_INTERLEAVED
pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 6;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 1;
}
pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity;
......
This diff is collapsed.
......@@ -144,7 +144,7 @@ int main(int argc, char **argv) {
//char input_val_str[50],input_val_str2[50];
//uint16_t NB_RB=25;
SCM_t channel_model = AWGN; //Rayleigh1_anticorr;
uint8_t N_RB_DL = 106, mu = 1;
uint16_t N_RB_DL = 106, mu = 1;
unsigned char frame_type = 0;
unsigned char pbch_phase = 0;
int frame = 0, subframe = 0;
......@@ -362,9 +362,10 @@ int main(int argc, char **argv) {
if (snr1set == 0)
snr1 = snr0 + 10;
gNB2UE = new_channel_desc_scm(n_tx, n_rx, channel_model, 61.44e6, //N_RB2sampling_rate(N_RB_DL),
40e6, //N_RB2channel_bandwidth(N_RB_DL),
0, 0, 0);
gNB2UE = new_channel_desc_scm(n_tx, n_rx, channel_model,
61.44e6, //N_RB2sampling_rate(N_RB_DL),
40e6, //N_RB2channel_bandwidth(N_RB_DL),
0, 0, 0);
if (gNB2UE == NULL) {