Commit 511562bb authored by Calvin HSU's avatar Calvin HSU

UE: update L2 intra primitives, FAPI message

parent 248aa027
Pipeline #10255 failed with stage
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......@@ -191,20 +191,16 @@ typedef struct {
typedef struct {
uint16_t pdu_length;
uint16_t pdu_index;
uint16_t pdu_index;
uint8_t* pdu;
} fapi_nr_tx_request_pdu_t;
typedef struct {
fapi_nr_tx_config_t tx_config;
uint16_t number_of_pdus;
fapi_nr_tx_request_pdu_t* tx_pdu_list;
} fapi_nr_tx_request_body_t;
///
typedef struct {
uint32_t sfn_slot;
fapi_nr_tx_request_body_t tx_request_body;
fapi_nr_tx_config_t tx_config;
uint16_t number_of_pdus;
fapi_nr_tx_request_body_t *tx_request_body;
} fapi_nr_tx_request_t;
......@@ -244,8 +240,20 @@ typedef struct {
} fapi_nr_dl_config_dci_pdu;
typedef struct {
uint16_t rnti;
fapi_nr_dci_pdu_rel15_t dci_config;
uint8_t format_indicator; //1 bit
uint16_t frequency_domain_assignment; //up to 9 bits
uint8_t time_domain_assignment; // 4 bits
uint8_t vrb_to_prb_mapping; //0 or 1 bit
uint8_t mcs; //5 bits
uint8_t ndi; //1 bit
uint8_t rv; //2 bits
uint8_t harq_pid; //4 bits
uint8_t dai; //0, 2 or 4 bits
uint8_t tpc; //2 bits
uint8_t pucch_resource_indicator; //3 bits
uint8_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
} fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
......@@ -726,4 +734,4 @@ typedef struct {
} fapi_nr_config_request_t;
#endif /* _FAPI_INTERFACE_H_ */
#endif
......@@ -61,8 +61,7 @@
typedef enum {
SFN_C_MOD_2_EQ_0,
SFN_C_MOD_2_EQ_1,
SFN_C_EQ_SFN_SSB
SFN_C_MOD_2_EQ_1
} SFN_C_TYPE;
/*!\brief Top level UE MAC structure */
......
......@@ -43,7 +43,8 @@
\param extra_bits extra bits for frame calculation
\param l_ssb_equal_64 check if ssb number of candicate is equal 64, 1=equal; 0=non equal. Reference 38.212 7.1.1
\param pduP pointer to pdu
\param pdu_length length of pdu*/
\param pdu_length length of pdu
\param cell_id cell id */
int8_t nr_ue_decode_mib(
module_id_t module_id,
int cc_id,
......@@ -51,7 +52,8 @@ int8_t nr_ue_decode_mib(
uint8_t extra_bits,
uint32_t ssb_length,
uint32_t ssb_index,
void *pduP );
void *pduP,
uint16_t cell_id );
/**\brief primitive from RRC layer to MAC layer for configuration L1/L2, now supported 4 rrc messages: MIB, cell_group_config for MAC/PHY, spcell_config(serving cell config)
......
......@@ -52,17 +52,17 @@ int8_t nr_ue_decode_mib(
uint8_t extra_bits, // 8bits 38.212 c7.1.1
uint32_t ssb_length,
uint32_t ssb_index,
void *pduP ){
void *pduP,
uint16_t cell_id ){
printf("[L2][MAC] decode mib\n");
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index,
NR_BCCH_BCH, (uint8_t *) pduP, 3 );
nr_mac_rrc_data_ind_ue( module_id, cc_id, gNB_index, NR_BCCH_BCH, (uint8_t *) pduP, 3 ); // fixed 3 bytes MIB PDU
if(mac->mib != NULL){
AssertFatal(mac->mib != NULL, "nr_ue_decode_mib() mac->mib == NULL\n");
//if(mac->mib != NULL){
uint32_t frame = (mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused);
uint32_t frame_number_4lsb = (uint32_t)(extra_bits & 0xf); // extra bits[0:3]
uint32_t half_frame_bit = (uint32_t)(( extra_bits >> 4 ) & 0x1 ); // extra bits[4]
......@@ -96,11 +96,20 @@ int8_t nr_ue_decode_mib(
printf("ssb index(extra bits): %d\n", (int)ssb_index);
#endif
subcarrier_spacing_t scs_ssb = scs_15kHz; // default for testing
subcarrier_spacing_t scs_pdcch = scs_15kHz; // default for testing
channel_bandwidth_t min_channel_bw = bw_5MHz; // deafult for testing
subcarrier_spacing_t scs_ssb = scs_30kHz; // default for testing
subcarrier_spacing_t scs_pdcch;
// assume carrier frequency < 6GHz
if(mac->mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60){
scs_pdcch = scs_15kHz;
}else{ //NR_MIB__subCarrierSpacingCommon_scs30or120
scs_pdcch = scs_30kHz;
}
channel_bandwidth_t min_channel_bw = bw_40MHz; // deafult for testing
uint32_t is_condition_A = 1;
uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13
frequency_range_t frequency_range = FR1;
uint32_t index_4msb = (mac->mib->pdcch_ConfigSIB1 >> 4) & 0xf;
uint32_t index_4lsb = (mac->mib->pdcch_ConfigSIB1 & 0xf);
......@@ -225,14 +234,14 @@ int8_t nr_ue_decode_mib(
AssertFatal(num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
AssertFatal(rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
uint32_t cell_id = 0; // obtain from L1 later
//uint32_t cell_id = 0; // obtain from L1 later
mac->type0_pdcch_dci_config.coreset.rb_start = rb_offset;
mac->type0_pdcch_dci_config.coreset.rb_end = rb_offset + num_rbs - 1;
//mac->type0_pdcch_dci_config.type0_pdcch_coreset.duration = num_symbols;
mac->type0_pdcch_dci_config.coreset.cce_reg_mapping_type = CCE_REG_MAPPING_TYPE_INTERLEAVED;
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_reg_bundle_size = 6; // L 38.211 7.3.2.2
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_interleaver_size = 2; // R 38.211 7.3.2.2
mac->type0_pdcch_dci_config.coreset.cce_reg_interleaved_shift_index = cell_id;
mac->type0_pdcch_dci_config.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
mac->type0_pdcch_dci_config.coreset.pdcch_dmrs_scrambling_id = cell_id;
......@@ -243,14 +252,15 @@ int8_t nr_ue_decode_mib(
float big_o;
float big_m;
uint32_t temp;
SFN_C_TYPE sfn_c;
SFN_C_TYPE sfn_c; // only valid for mux=1
uint32_t n_c;
uint32_t number_of_search_space_per_slot;
uint32_t first_symbol_index;
uint32_t search_space_duration; // element of search space
uint32_t coreset_duration; // element of coreset
const uint32_t scs_index = 0;
const uint32_t num_slot_per_frame = 10;
const uint32_t num_slot_per_frame = 20;
// 38.213 table 10.1-1
......@@ -303,7 +313,7 @@ const uint32_t num_slot_per_frame = 10;
// 38.213 Table 13-13
AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n");
// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
sfn_c = SFN_C_EQ_SFN_SSB;
// sfn_c = SFN_C_EQ_SFN_SSB;
n_c = get_ssb_slot(ssb_index);
switch(ssb_index & 0x3){ // ssb_index(i) mod 4
case 0:
......@@ -325,7 +335,7 @@ const uint32_t num_slot_per_frame = 10;
// 38.213 Table 13-14
AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
sfn_c = SFN_C_EQ_SFN_SSB;
// sfn_c = SFN_C_EQ_SFN_SSB;
n_c = get_ssb_slot(ssb_index);
switch(ssb_index & 0x7){ // ssb_index(i) mod 8
case 0:
......@@ -367,7 +377,7 @@ const uint32_t num_slot_per_frame = 10;
// 38.213 Table 13-15
AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n");
// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
sfn_c = SFN_C_EQ_SFN_SSB;
// sfn_c = SFN_C_EQ_SFN_SSB;
n_c = get_ssb_slot(ssb_index);
switch(ssb_index & 0x3){ // ssb_index(i) mod 4
case 0:
......@@ -417,15 +427,13 @@ const uint32_t num_slot_per_frame = 10;
if(mac->if_module != NULL && mac->if_module->phy_config_request != NULL){
mac->if_module->phy_config_request(&mac->phy_config);
}
}
//}
return 0;
}
// TODO: change to UE parameter, scs: 15KHz, slot duration: 1ms
uint32_t get_ssb_frame(){
return 0;
}
......@@ -458,9 +466,9 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
if((mac->type0_pdcch_ss_sfn_c == SFN_C_MOD_2_EQ_1) && (rx_frame & 0x1) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch;
}
if((mac->type0_pdcch_ss_sfn_c == SFN_C_EQ_SFN_SSB) && ( get_ssb_frame() )){
search_space_mask = search_space_mask | type0_pdcch;
}
//if((mac->type0_pdcch_ss_sfn_c == SFN_C_EQ_SFN_SSB) && ( get_ssb_frame() )){
// search_space_mask = search_space_mask | type0_pdcch;
//}
}
if(mac->type0_pdcch_ss_mux_pattern == 2){
// 38.213 Table 13-13, 13-14
......@@ -526,11 +534,20 @@ int8_t nr_ue_decode_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fap
}else if(rnti == mac->ra_rnti){
}else if(rnti == P_RNTI){
}else{ // c-rnti
/// check if this is pdcch order
//dci->random_access_preamble_index;
//dci->ss_pbch_index;
//dci->prach_mask_index;
/// else normal DL-SCH grant
}
}
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe)
{
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe){
return 0;
}
\ No newline at end of file
......@@ -41,7 +41,7 @@
static nr_ue_if_module_t *nr_ue_if_module_inst[MAX_IF_MODULES];
// L2 Abstraction Layer
int8_t handle_bcch_bch(module_id_t module_id, int cc_id, uint8_t gNB_index, uint8_t *pduP, uint8_t additional_bits, uint32_t ssb_index, uint32_t ssb_length){
int8_t handle_bcch_bch(module_id_t module_id, int cc_id, uint8_t gNB_index, uint8_t *pduP, uint8_t additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id){
return nr_ue_decode_mib( module_id,
cc_id,
......@@ -49,7 +49,8 @@ int8_t handle_bcch_bch(module_id_t module_id, int cc_id, uint8_t gNB_index, uint
additional_bits,
ssb_length, // Lssb = 64 is not support
ssb_index,
pduP );
pduP,
cell_id);
}
......@@ -117,7 +118,8 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.pdu,
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.additional_bits,
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.ssb_index,
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.ssb_length )) << FAPI_NR_RX_PDU_TYPE_MIB;
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.ssb_length,
(dl_info->rx_ind->rx_request_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;
break;
case FAPI_NR_RX_PDU_TYPE_SIB:
ret_mask |= (handle_bcch_dlsch(dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
......@@ -156,8 +158,23 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
case FAPI_NR_DCI_TYPE_1_0:
dl_config->dl_config_request_body[dl_config->number_pdus].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DLSCH;
dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15.dci_config = *dci;
dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15.rnti = 0x0000; // UE-spec
// mapping into DL_CONFIG_REQ for DL-SCH
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15
dlsch_config_pdu->format_indicator = dci->dci_format;
dlsch_config_pdu->frequency_domain_assignment = dci->frequency_domain_resouce_assignment;
dlsch_config_pdu->time_domain_assignment = dci->time_domain_resource_assignment;
dlsch_config_pdu->vrb_to_prb_mapping = dci->vrb_to_prb_mapping;
dlsch_config_pdu->mcs = dci->mcs;
dlsch_config_pdu->ndi = dci->new_data_indication;
dlsch_config_pdu->rv = dci->redundancy_version;
dlsch_config_pdu->harq_pid = dci->harq_process;
dlsch_config_pdu->dai = dci->downlink_assignment_index;
dlsch_config_pdu->tpc = dci->tpc_command;
dlsch_config_pdu->pucch_resource_indicator = dci->pucch_resource_indicator;
dlsch_config_pdu->pdsch_to_harq_feedback_timing_indicator = dci->pdsch_to_harq_feedback_timing_indicator;
dl_config->dl_config_request_body[dl_config->number_pdus].dlsch_pdu.dlsch_config_rel15.rnti = 0x0000; // TX RNTI: UE-spec
dl_config->number_pdus = dl_config->number_pdus + 1;
ret_mask |= (handle_dci(
......
......@@ -186,8 +186,9 @@ int8_t nr_ue_dl_indication(nr_downlink_indication_t *dl_info);
\param pduP pointer to bch pdu
\param additional_bits corresponding to 38.212 ch.7
\param ssb_index SSB index within 0 - (L_ssb-1) corresponding to 38.331 ch.13 parameter i
\param ssb_length corresponding to L1 parameter L_ssb */
int8_t handle_bcch_bch(module_id_t module_id, int cc_id, uint8_t gNB_index, uint8_t *pduP, uint8_t additional_bits, uint32_t ssb_index, uint32_t ssb_length);
\param ssb_length corresponding to L1 parameter L_ssb
\param cell_id cell id */
int8_t handle_bcch_bch(module_id_t module_id, int cc_id, uint8_t gNB_index, uint8_t *pduP, uint8_t additional_bits, uint32_t ssb_index, uint32_t ssb_length, uint16_t cell_id);
// TODO check
/**\brief handle BCCH-DL-SCH message from dl_indication
......
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