Commit 61e36839 authored by Guy De Souza's avatar Guy De Souza

DMRS shift disabling on gNB

parent 550751fc
......@@ -55,8 +55,8 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10;
unsigned int rx_offset;
NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0];
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
uint16_t nb_rb_coreset = 24;
uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset + pdcch_vars->coreset[0].rb_offset*NR_NB_SC_PER_RB;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
uint16_t nb_rb_coreset = pdcch_vars->coreset[0].rb_offset;
uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516;
uint16_t nb_rb_pdsch = 50;
uint8_t p=0;
......
......@@ -32,7 +32,7 @@
#include "nr_dci.h"
//#define DEBUG_PDCCH_DMRS
#define DEBUG_PDCCH_DMRS
#define DEBUG_DCI
#define DEBUG_CHANNEL_CODING
......@@ -207,12 +207,12 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) {
/*if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) {
for (int symb=cset_start_symb; symb<cset_start_symb + pdcch_params.n_symb; symb++)
gold_pdcch_dmrs[symb] += (pdcch_params.rb_offset*3)>>5;
dmrs_offset = (pdcch_params.rb_offset*3)&0x1f;
LOG_I(PHY, "PDCCH DMRS offset %d\n", dmrs_offset);
}
}*/ // DMRS shift currently disable for compatibility with the OAI UE
for (int symb=cset_start_symb; symb<cset_start_symb + pdcch_params.n_symb; symb++) {
if (dmrs_offset) {
......
......@@ -21,7 +21,7 @@
/*! \file PHY/LTE_TRANSPORT/dlsch_coding.c
* \brief Top-level routines for implementing LDPC-coded (DLSCH) transport channels from 38-212, 15.2
* \author H.Wang
* \author H.Wang, Guy De Souza
* \date 2018
* \version 0.1
* \company Eurecom
......
......@@ -29,7 +29,7 @@
#include "filt16a_32.h"
#include "T.h"
//#define DEBUG_PDSCH
//#define DEBUG_PDCCH
#define DEBUG_PDCCH
int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue,
......@@ -262,7 +262,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
unsigned short coreset_start_subcarrier,
unsigned short nb_rb_coreset)
{
int pilot[200] __attribute__((aligned(16)));
int pilot[300] __attribute__((aligned(16)));
unsigned char aarx,p;
unsigned short k;
unsigned int pilot_cnt;
......
......@@ -604,7 +604,7 @@ int main(int argc, char **argv)
uint64_t mask = 0x0;
uint16_t num_rbs=24;
uint16_t rb_offset=0;
uint16_t rb_offset=24;
uint16_t cell_id=0;
uint16_t num_symbols=2;
for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
......
......@@ -47,7 +47,7 @@ extern RAN_CONTEXT_t RC;
void nr_init_coreset(nfapi_nr_coreset_t *coreset) {
coreset->coreset_id = 1;
coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
coreset->frequency_domain_resources = 0x1E000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
coreset->duration = 2;
coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
coreset->reg_bundle_size = 6;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment