Commit a964b894 authored by Calvin HSU's avatar Calvin HSU

UE: rx_frame, rx_slot in nr-ue.c to be fill.

parent 4a60d91a
Pipeline #10271 failed with stage
in 0 seconds
......@@ -115,7 +115,7 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type);
uint32_t get_ssb_frame(void);
uint32_t get_ssb_frame(uint32_t test);
uint32_t get_ssb_slot(uint32_t ssb_index);
......
......@@ -446,8 +446,8 @@ int8_t nr_ue_decode_mib(
// TODO: change to UE parameter, scs: 15KHz, slot duration: 1ms
uint32_t get_ssb_frame(){
return 0;
uint32_t get_ssb_frame(uint32_t test){
return test;
}
// Performs :
......@@ -486,14 +486,14 @@ NR_UE_L2_STATE_t nr_ue_scheduler(
}
if(mac->type0_pdcch_ss_mux_pattern == 2){
// 38.213 Table 13-13, 13-14
if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){
if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
}
}
if(mac->type0_pdcch_ss_mux_pattern == 3){
// 38.213 Table 13-15
if((rx_frame == get_ssb_frame()) && (rx_slot == mac->type0_pdcch_ss_n_c)){
if((rx_frame == get_ssb_frame(rx_frame)) && (rx_slot == mac->type0_pdcch_ss_n_c)){
search_space_mask = search_space_mask | type0_pdcch;
mac->type0_pdcch_consecutive_slots = mac->type0_pdcch_dci_config.duration;
}
......
......@@ -630,7 +630,8 @@ static void *UE_thread_rxn_txnp4(void *arg) {
UE->ul_indication.module_id = 0;
UE->ul_indication.gNB_index = 0;
UE->ul_indication.cc_id = 0;
UE->ul_indication.slot = 0; // to be fill
UE->ul_indication.frame = 0; // to be fill
// [TODO] mapping right after NR initial sync
//UE->ul_indication.frame = ;
//UE->ul_indication.slot = ;
......
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