Commit be8d32d5 authored by Cedric Roux's avatar Cedric Roux

Merge remote-tracking branch 'origin/develop_integration_2018_w05' into develop

Summary of changes:
- noS1 fixes
- various bugs fixed
parents cd8e8458 ea0d7781
This diff is collapsed.
......@@ -30,7 +30,7 @@ set ( MESSAGE_CHART_GENERATOR_RLC_MAC False )
set ( MESSAGE_CHART_GENERATOR_PHY False )
set ( MSG_PRINT False )
set ( MU_RECEIVER False )
set ( NAS_ADDRESS_FIX True )
set ( NAS_ADDRESS_FIX False )
set ( NAS_BUILT_IN_UE False)
set ( NAS_MME False )
set ( NAS_UE False )
......
......@@ -44,11 +44,11 @@ load_module $OPENAIR_DIR/targets/bin/nasmesh.ko
if [ "$1" = "eNB" ]; then
echo "bring up oai0 interface for enb"
sudo ifconfig oai0 10.0.1.1 netmask 255.255.255.0 broadcast 10.0.1.255
$OPENAIR_DIR/targets/bin/rb_tool -a -c0 -i0 -z0 -s 10.0.1.1 -t 10.0.1.9 -r 1
$OPENAIR_DIR/targets/bin/rb_tool -a -c0 -i0 -z0 -s 10.0.1.1 -t 10.0.1.2 -r 1
else
if [ "$1" = "UE" ]; then
echo "bring up oai0 interface for UE"
sudo ifconfig oai0 10.0.1.9 netmask 255.255.255.0 broadcast 10.0.1.255
$OPENAIR_DIR/targets/bin/rb_tool -a -c0 -i0 -z0 -s 10.0.1.9 -t 10.0.1.1 -r 1
$OPENAIR_DIR/targets/bin/rb_tool -a -c0 -i0 -z0 -s 10.0.1.2 -t 10.0.1.1 -r 1
fi
fi
......@@ -22,19 +22,42 @@
/*!\brief Initilization and reconfiguration routines for LTE PHY */
#include "defs.h"
#include "PHY/extern.h"
#include "MAC_INTERFACE/extern.h"
//#include "ARCH/CBMIMO1/DEVICE_DRIVER/extern.h"
/*!
* @addtogroup _PHY_STRUCTURES_
* Memory Initializaion and Cleanup for LTE MODEM.
* @{
\section _Memory_init_ Memory Initialization for LTE MODEM
void init_lte_top(LTE_DL_FRAME_PARMS *frame_parms)
{
*/
crcTableInit();
//#define DEBUG_PHY
t
ccodedot11_init();
ccodedot11_init_inv();
ccodelte_init();
ccodelte_init_inv();
treillis_table_init();
phy_generate_viterbi_tables();
phy_generate_viterbi_tables_lte();
init_td8();
init_td16();
#ifdef __AVX2__
init_td16avx2();
#endif
lte_sync_time_init(frame_parms);
generate_ul_ref_sigs();
generate_ul_ref_sigs_rx();
generate_64qam_table();
generate_16qam_table();
generate_RIV_tables();
init_unscrambling_lut();
init_scrambling_lut();
//set_taus_seed(1328);
}
/*
......
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/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
#include "defs.h"
#include "SCHED/defs.h"
#include "PHY/extern.h"
#include "SIMULATION/TOOLS/defs.h"
#include "RadioResourceConfigCommonSIB.h"
#include "RadioResourceConfigDedicated.h"
#include "TDD-Config.h"
#include "LAYER2/MAC/extern.h"
#include "MBSFN-SubframeConfigList.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
#include "assertions.h"
#include <math.h>
int phy_init_RU(RU_t *ru) {
LTE_DL_FRAME_PARMS *fp = &ru->frame_parms;
int i,j;
int p;
int re;
LOG_I(PHY,"Initializing RU signal buffers (if_south %s) nb_tx %d\n",ru_if_types[ru->if_south],ru->nb_tx);
if (ru->if_south <= REMOTE_IF5) { // this means REMOTE_IF5 or LOCAL_RF, so allocate memory for time-domain signals
// Time-domain signals
ru->common.txdata = (int32_t**)malloc16(ru->nb_tx*sizeof(int32_t*));
ru->common.rxdata = (int32_t**)malloc16(ru->nb_rx*sizeof(int32_t*) );
for (i=0; i<ru->nb_tx; i++) {
// Allocate 10 subframes of I/Q TX signal data (time) if not
ru->common.txdata[i] = (int32_t*)malloc16_clear( fp->samples_per_tti*10*sizeof(int32_t) );
LOG_I(PHY,"[INIT] common.txdata[%d] = %p (%lu bytes)\n",i,ru->common.txdata[i],
fp->samples_per_tti*10*sizeof(int32_t));
}
for (i=0;i<ru->nb_rx;i++) {
ru->common.rxdata[i] = (int32_t*)malloc16_clear( fp->samples_per_tti*10*sizeof(int32_t) );
}
} // IF5 or local RF
else {
LOG_I(PHY,"No rxdata/txdata for RU\n");
ru->common.txdata = (int32_t**)NULL;
ru->common.rxdata = (int32_t**)NULL;
}
if (ru->function != NGFI_RRU_IF5) { // we need to do RX/TX RU processing
LOG_I(PHY,"nb_tx %d\n",ru->nb_tx);
ru->common.rxdata_7_5kHz = (int32_t**)malloc16(ru->nb_rx*sizeof(int32_t*) );
for (i=0;i<ru->nb_rx;i++) {
ru->common.rxdata_7_5kHz[i] = (int32_t*)malloc16_clear( 2*fp->samples_per_tti*2*sizeof(int32_t) );
LOG_I(PHY,"rxdata_7_5kHz[%d] %p for RU %d\n",i,ru->common.rxdata_7_5kHz[i],ru->idx);
}
// allocate IFFT input buffers (TX)
ru->common.txdataF_BF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*));
LOG_I(PHY,"[INIT] common.txdata_BF= %p (%lu bytes)\n",ru->common.txdataF_BF,
ru->nb_tx*sizeof(int32_t*));
for (i=0; i<ru->nb_tx; i++) {
ru->common.txdataF_BF[i] = (int32_t*)malloc16_clear(fp->symbols_per_tti*fp->ofdm_symbol_size*sizeof(int32_t) );
LOG_I(PHY,"txdataF_BF[%d] %p for RU %d\n",i,ru->common.txdataF_BF[i],ru->idx);
}
// allocate FFT output buffers (RX)
ru->common.rxdataF = (int32_t**)malloc16(ru->nb_rx*sizeof(int32_t*) );
for (i=0; i<ru->nb_rx; i++) {
// allocate 2 subframes of I/Q signal data (frequency)
ru->common.rxdataF[i] = (int32_t*)malloc16_clear(sizeof(int32_t)*(2*fp->ofdm_symbol_size*fp->symbols_per_tti) );
LOG_I(PHY,"rxdataF[%d] %p for RU %d\n",i,ru->common.rxdataF[i],ru->idx);
}
/* number of elements of an array X is computed as sizeof(X) / sizeof(X[0]) */
AssertFatal(ru->nb_rx <= sizeof(ru->prach_rxsigF) / sizeof(ru->prach_rxsigF[0]),
"nb_antennas_rx too large");
ru->prach_rxsigF = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*));
for (j=0;j<4;j++) ru->prach_rxsigF_br[j] = (int16_t**)malloc(ru->nb_rx * sizeof(int16_t*));
for (i=0; i<ru->nb_rx; i++) {
ru->prach_rxsigF[i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) );
LOG_D(PHY,"[INIT] prach_vars->rxsigF[%d] = %p\n",i,ru->prach_rxsigF[i]);
#ifdef Rel14
for (j=0;j<4;j++) {
ru->prach_rxsigF_br[j][i] = (int16_t*)malloc16_clear( fp->ofdm_symbol_size*12*2*sizeof(int16_t) );
LOG_D(PHY,"[INIT] prach_vars_br->rxsigF[%d] = %p\n",i,ru->prach_rxsigF_br[j][i]);
}
#endif
}
AssertFatal(RC.nb_L1_inst <= NUMBER_OF_eNB_MAX,"eNB instances %d > %d\n",
RC.nb_L1_inst,NUMBER_OF_eNB_MAX);
LOG_E(PHY,"[INIT] %s() RC.nb_L1_inst:%d \n", __FUNCTION__, RC.nb_L1_inst);
for (i=0; i<RC.nb_L1_inst; i++) {
for (p=0;p<15;p++) {
LOG_D(PHY,"[INIT] %s() nb_antenna_ports_eNB:%d \n", __FUNCTION__, ru->eNB_list[i]->frame_parms.nb_antenna_ports_eNB);
if (p<ru->eNB_list[i]->frame_parms.nb_antenna_ports_eNB || p==5) {
LOG_D(PHY,"[INIT] %s() DO BEAM WEIGHTS nb_antenna_ports_eNB:%d nb_tx:%d\n", __FUNCTION__, ru->eNB_list[i]->frame_parms.nb_antenna_ports_eNB, ru->nb_tx);
ru->beam_weights[i][p] = (int32_t **)malloc16_clear(ru->nb_tx*sizeof(int32_t*));
for (j=0; j<ru->nb_tx; j++) {
ru->beam_weights[i][p][j] = (int32_t *)malloc16_clear(fp->ofdm_symbol_size*sizeof(int32_t));
// antenna ports 0-3 are mapped on antennas 0-3
// antenna port 4 is mapped on antenna 0
// antenna ports 5-14 are mapped on all antennas
if (((p<4) && (p==j)) || ((p==4) && (j==0))) {
for (re=0; re<fp->ofdm_symbol_size; re++)
{
ru->beam_weights[i][p][j][re] = 0x00007fff;
//LOG_D(PHY,"[INIT] lte_common_vars->beam_weights[%d][%d][%d][%d] = %d\n", i,p,j,re,ru->beam_weights[i][p][j][re]);
}
}
else if (p>4) {
for (re=0; re<fp->ofdm_symbol_size; re++)
{
ru->beam_weights[i][p][j][re] = 0x00007fff/ru->nb_tx;
//LOG_D(PHY,"[INIT] lte_common_vars->beam_weights[%d][%d][%d][%d] = %d\n", i,p,j,re,ru->beam_weights[i][p][j][re]);
}
}
//LOG_D(PHY,"[INIT] lte_common_vars->beam_weights[%d][%d] = %p (%lu bytes)\n", i,j,ru->beam_weights[i][p][j], fp->ofdm_symbol_size*sizeof(int32_t));
} // for (j=0
} // if (p<ru
} // for p
} //for i
} // !=IF5
ru->common.sync_corr = (uint32_t*)malloc16_clear( LTE_NUMBER_OF_SUBFRAMES_PER_FRAME*sizeof(uint32_t)*fp->samples_per_tti );
return(0);
}
This diff is collapsed.
......@@ -465,7 +465,7 @@ int lte_sync_time(int **rxdata, ///rx data in time domain
*eNB_id = sync_source;
LOG_D(PHY,"[UE] lte_sync_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n",sync_source,peak_pos,peak_val,dB_fixed(peak_val)/2);
LOG_I(PHY,"[UE] lte_sync_time: Sync source = %d, Peak found at pos %d, val = %d (%d dB)\n",sync_source,peak_pos,peak_val,dB_fixed(peak_val)/2);
#ifdef DEBUG_PHY
......
......@@ -2260,7 +2260,7 @@ uint8_t generate_dci_top(uint8_t num_pdcch_symbols,
y[0] = &yseq0[0];
y[1] = &yseq1[0];
#if 0
#if 1
// reset all bits to <NIL>, here we set <NIL> elements as 2
// memset(e, 2, DCI_BITS_MAX);
// here we interpret NIL as a random QPSK sequence. That makes power estimation easier.
......@@ -2271,7 +2271,7 @@ uint8_t generate_dci_top(uint8_t num_pdcch_symbols,
/* clear all bits, the above code may generate too much false detections
* (not sure about this, to be checked somehow)
*/
memset(e, 0, DCI_BITS_MAX);
// memset(e, 0, DCI_BITS_MAX);
e_ptr = e;
......@@ -3125,8 +3125,8 @@ uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_UE *ue,
mi,
((ue->decode_SIB == 1) ? SI_RNTI : 0),
ra_rnti,
P_RNTI,
agregationLevel,
P_RNTI,
agregationLevel,
format1A,
format1A,
format1A,
......@@ -3144,7 +3144,7 @@ uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_UE *ue,
((format0_found==1)&&(format_c_found==1)))
return(dci_cnt);
if (DCIFormat == 1)
if (DCIFormat == format1)
{
if ((tmode < 3) || (tmode == 7)) {
//printf("Crnti decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat);
......@@ -3187,14 +3187,14 @@ uint16_t dci_CRNTI_decoding_procedure(PHY_VARS_UE *ue,
//printf("Crnti 1 decoding frame param agregation %d DCI %d \n",agregationLevel,DCIFormat);
}
else
else if (DCIFormat == format1A)
{
AssertFatal(0,"Other Transmission mode not yet coded\n");
}
}
else
{
AssertFatal(0,"DCI format %d not yet implemented \n",DCIFormat);
LOG_W(PHY,"DCI format %d wrong or not yet implemented \n",DCIFormat);
}
return(dci_cnt);
......@@ -3418,7 +3418,7 @@ uint16_t dci_decoding_procedure(PHY_VARS_UE *ue,
if (do_common == 1) {
#ifdef DEBUG_DCI_DECODING
printf("[DCI search] doing common search/format0 aggregation 4\n");
printf("[DCI search] subframe %d: doing common search/format0 aggregation 4\n",subframe);
#endif
if (ue->prach_resources[eNB_id])
......
......@@ -5056,10 +5056,10 @@ void compute_llr_offset(LTE_DL_FRAME_PARMS *frame_parms,
if(symbol < (frame_parms->symbols_per_tti-1))
pdsch_vars->llr_offset[symbol+1] = pdsch_vars->llr_offset[symbol] + llr_offset;
//LOG_I(PHY,"Granted Re subframe %d / symbol %d => %d (%d RBs)\n", subframe, symbol_mod, granted_re,dlsch0_harq->nb_rb);
//LOG_I(PHY,"Pbch/PSS/SSS Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, pbch_pss_sss_re);
//LOG_I(PHY,"CRS Re Per PRB subframe %d / symbol %d => %d \n", subframe, symbol_mod, crs_re);
//LOG_I(PHY,"Data Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, data_re);
// LOG_I(PHY,"Granted Re subframe %d / symbol %d => %d (%d RBs)\n", subframe, symbol_mod, granted_re,dlsch0_harq->nb_rb);
// LOG_I(PHY,"Pbch/PSS/SSS Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, pbch_pss_sss_re);
// LOG_I(PHY,"CRS Re Per PRB subframe %d / symbol %d => %d \n", subframe, symbol_mod, crs_re);
// LOG_I(PHY,"Data Re subframe %d / symbol %d => %d \n", subframe, symbol_mod, data_re);
......@@ -5096,7 +5096,6 @@ void prepare_dl_decoding_format1_1A(DCI_format_t dci_format,
uint8_t NPRB = 0;
uint8_t NPRB4TBS = 0;
uint8_t nb_rb_alloc = 0;
if(dci_format == format1A)
{
......@@ -5138,14 +5137,12 @@ void prepare_dl_decoding_format1_1A(DCI_format_t dci_format,
}
*/
nb_rb_alloc = NPRB;
}
}
else // format1
{
NPRB = conv_nprb(rah, rballoc, N_RB_DL);
NPRB4TBS=NPRB;
nb_rb_alloc = NPRB;
}
pdlsch0->current_harq_pid = harq_pid;
......@@ -5246,7 +5243,6 @@ void prepare_dl_decoding_format1_1A(DCI_format_t dci_format,
pdlsch0_harq->rb_alloc_even[1] = localRIV2alloc_LUT50_1[rballoc];
pdlsch0_harq->rb_alloc_odd[0] = localRIV2alloc_LUT50_0[rballoc];
pdlsch0_harq->rb_alloc_odd[1] = localRIV2alloc_LUT50_1[rballoc];
printf("rballoc: %08x.%08x\n",pdlsch0_harq->rb_alloc_even[0],pdlsch0_harq->rb_alloc_even[1]);
} else { // DISTRIBUTED
if ((rballoc&(1<<10)) == 0) {
rballoc = rballoc&(~(1<<10));
......@@ -5328,7 +5324,7 @@ void prepare_dl_decoding_format1_1A(DCI_format_t dci_format,
pdcch_vars,
pdsch_vars,
pdlsch0_harq,
nb_rb_alloc,
NPRB,
subframe);
}
......@@ -6560,7 +6556,7 @@ uint8_t pdcch_alloc2ul_subframe(LTE_DL_FRAME_PARMS *frame_parms,uint8_t n)
else
ul_subframe = ((n+4)%10);
if ((subframe_select(frame_parms,ul_subframe) != SF_UL) && (frame_parms->frame_type == TDD)) return(255);
// AssertFatal(frame_parms->frame_type == FDD || subframe_select(frame_parms,ul_subframe) == SF_UL,"illegal ul_subframe %d (n %d)\n",ul_subframe,n);
LOG_D(PHY, "subframe %d: PUSCH subframe = %d\n", n, ul_subframe);
return ul_subframe;
......@@ -7261,6 +7257,10 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
harq_pid = subframe2harq_pid(frame_parms,
pdcch_alloc2ul_frame(frame_parms,proc->frame_rx,subframe),
pdcch_alloc2ul_subframe(frame_parms,subframe));
LOG_D(PHY,"Frame %d, Subframe %d: Programming ULSCH for (%d.%d) => harq_pid %d\n",
proc->frame_rx,subframe,
pdcch_alloc2ul_frame(frame_parms,proc->frame_rx,subframe),
pdcch_alloc2ul_subframe(frame_parms,subframe), harq_pid);
if (harq_pid == 255) {
LOG_E(PHY, "frame %d, subframe %d, rnti %x, format %d: illegal harq_pid!\n",
......@@ -8053,7 +8053,7 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
dlsch[0]->harq_ack[subframe].vDAI_UL = dai+1;
/*LOG_I(PHY, "[PUSCH %d] Format0 DCI %s, CQI_req=%d, cshift=%d, TPC=%d, DAI=%d, vDAI_UL[sf#%d]=%d, NDI=%d, MCS=%d, RBalloc=%d, first_rb=%d, harq_pid=%d, nb_rb=%d, subframe_scheduling_flag=%d"
LOG_D(PHY, "[PUSCH %d] Format0 DCI %s, CQI_req=%d, cshift=%d, TPC=%d, DAI=%d, vDAI_UL[sf#%d]=%d, NDI=%d, MCS=%d, RBalloc=%d, first_rb=%d, harq_pid=%d, nb_rb=%d, subframe_scheduling_flag=%d"
" ulsch->bundling %d, O_ACK %d \n",
harq_pid,
(frame_parms->frame_type == TDD? "TDD" : "FDD"),
......@@ -8061,7 +8061,8 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
ulsch->harq_processes[harq_pid]->first_rb, harq_pid, ulsch->harq_processes[harq_pid]->nb_rb,
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag,
ulsch->bundling,
ulsch->harq_processes[harq_pid]->O_ACK);*/
ulsch->harq_processes[harq_pid]->O_ACK);
LOG_D(PHY,"Setting beta_offset_cqi_times8 to %d, index %d\n",
beta_cqi[ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index],
ue->pusch_config_dedicated[eNB_id].betaOffset_CQI_Index);
......@@ -8118,7 +8119,7 @@ int generate_ue_ulsch_params_from_dci(void *dci_pdu,
#ifdef UE_DEBUG_TRACE
LOG_I(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe);
LOG_D(PHY,"Format 0 DCI : ulsch (ue): AbsSubframe %d.%d\n",proc->frame_rx%1024,subframe);
LOG_D(PHY,"Format 0 DCI : ulsch (ue): NBRB %d\n",ulsch->harq_processes[harq_pid]->nb_rb);
LOG_D(PHY,"Format 0 DCI :ulsch (ue): first_rb %d\n",ulsch->harq_processes[harq_pid]->first_rb);
LOG_D(PHY,"Format 0 DCI :ulsch (ue): rballoc %d\n",rballoc);
......
......@@ -845,18 +845,20 @@ int rx_pdsch(PHY_VARS_UE *ue,
pllr_symbol_cw1 = (int8_t*)pdsch_vars[eNB_id]->llr[1];
pllr_symbol_cw0 += llr_offset_symbol;
pllr_symbol_cw1 += llr_offset_symbol;
/*LOG_I(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %x @LLR Buff(symb) %x\n",
proc->frame_rx, proc->subframe_rx,symbol,
/*
LOG_I(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %x @LLR Buff(symb) %x\n",
frame, subframe,symbol,
nb_rb,dlsch0_harq->Qm,
pdsch_vars[eNB_id]->llr_length[symbol],
pdsch_vars[eNB_id]->llr_offset[symbol],
(int16_t*)pdsch_vars[eNB_id]->llr[0],
pllr_symbol);*/
pllr_symbol_cw0);
*/
switch (dlsch0_harq->Qm) {
case 2 :
if ((rx_type==rx_standard) || (codeword_TB1 == -1)) {
dlsch_qpsk_llr(frame_parms,
pdsch_vars[eNB_id]->rxdataF_comp0,
(int16_t*)pllr_symbol_cw0,
......
......@@ -672,14 +672,14 @@ int dlsch_qpsk_llr(LTE_DL_FRAME_PARMS *frame_parms,
}
//printf("dlsch_qpsk_llr: symbol %d,nb_rb %d, len %d,pbch_pss_sss_adjust %d\n",symbol,nb_rb,len,pbch_pss_sss_adjust);
/*LOG_I(PHY,"dlsch_qpsk_llr: [symb %d / FirstSym %d / Length %d]: @LLR Buff %x, @LLR Buff(symb) %x \n",
/*
LOG_I(PHY,"dlsch_qpsk_llr: [symb %d / FirstSym %d / Length %d]: @LLR Buff %x, @LLR Buff(symb) %x \n",
symbol,
first_symbol_flag,
len,
dlsch_llr,
llr32);*/
llr32);
*/
//printf("ll32p=%p , dlsch_llr=%p, symbol=%d, flag=%d \n", llr32, dlsch_llr, symbol, first_symbol_flag);
for (i=0; i<len; i++) {
*llr32 = *rxF;
......
......@@ -105,7 +105,7 @@ void send_IF4p5(RU_t *ru, int frame, int subframe, uint16_t packet_type) {
if ((ru->ifdevice.trx_write_func(&ru->ifdevice,
symbol_id,
&tx_buffer,
db_fulllength,
db_fulllength,
1,
IF4p5_PDLFFT)) < 0) {
perror("ETHERNET write for IF4p5_PDLFFT\n");
......@@ -138,19 +138,18 @@ void send_IF4p5(RU_t *ru, int frame, int subframe, uint16_t packet_type) {
if (packet_type == IF4p5_PULFFT) {
uint16_t *rx0 = (uint16_t*) &rxdataF[0][blockoffsetF];
uint16_t *rx1 = (uint16_t*) &rxdataF[0][slotoffsetF];
for (symbol_id=fp->symbols_per_tti-nsym; symbol_id<fp->symbols_per_tti; symbol_id++) {
uint32_t *rx0 = (uint32_t*) &rxdataF[0][blockoffsetF];
uint32_t *rx1 = (uint32_t*) &rxdataF[0][slotoffsetF];
for (symbol_id=fp->symbols_per_tti-nsym; symbol_id<fp->symbols_per_tti; symbol_id++) {
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_SEND_IF4_SYMBOL, symbol_id );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_SEND_IF4_SYMBOL, symbol_id );
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_COMPR_IF, 1 );
start_meas(&ru->compression);
for (element_id=0; element_id<db_halflength; element_id+=8) {
i = (uint16_t*) &rx0[element_id];
for (element_id=0; element_id<db_halflength; element_id+=8) {
i = (uint16_t*) &rx0[element_id];
d = (uint16_t*) &data_block[element_id];
d[0] = ((uint16_t) lin2alaw_if4p5[i[0]]) | ((uint16_t)(lin2alaw_if4p5[i[1]]<<8));
d[1] = ((uint16_t) lin2alaw_if4p5[i[2]]) | ((uint16_t)(lin2alaw_if4p5[i[3]]<<8));
......@@ -176,10 +175,10 @@ void send_IF4p5(RU_t *ru, int frame, int subframe, uint16_t packet_type) {
stop_meas(&ru->compression);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_COMPR_IF, 0 );
packet_header->frame_status &= ~(0x000f<<26);
packet_header->frame_status |= (symbol_id&0x000f)<<26;
packet_header->frame_status &= ~(0x000f<<26);
packet_header->frame_status |= (symbol_id&0x000f)<<26;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_IF, 1 );
start_meas(&ru->transport);
start_meas(&ru->transport);
if ((ru->ifdevice.trx_write_func(&ru->ifdevice,
symbol_id,
&tx_buffer,
......@@ -188,7 +187,7 @@ void send_IF4p5(RU_t *ru, int frame, int subframe, uint16_t packet_type) {
IF4p5_PULFFT)) < 0) {
perror("ETHERNET write for IF4p5_PULFFT\n");
}
stop_meas(&ru->transport);
stop_meas(&ru->transport);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE_IF, 0 );
slotoffsetF += fp->ofdm_symbol_size;
blockoffsetF += fp->ofdm_symbol_size;
......@@ -351,6 +350,9 @@ void recv_IF4p5(RU_t *ru, int *frame, int *subframe, uint16_t *packet_type, uint
//if (element_id==0) LOG_I(PHY,"recv_if4p5: symbol %d rxdata0 = (%u,%u)\n",*symbol_number,*i,*(i+1));
}
LOG_D(PHY,"PULFFT_IF4p5: CC_id %d : frame %d, subframe %d (symbol %d)=> %d dB\n",ru->idx,*frame,*subframe,*symbol_number,
dB_fixed(signal_energy((int*)&rxdataF[0][slotoffsetF],db_halflength)+
signal_energy((int*)&rxdataF[0][blockoffsetF],db_halflength)));
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_DECOMPR_IF, 0 );
} else if (*packet_type >= IF4p5_PRACH &&
*packet_type <= IF4p5_PRACH + 4) {
......
......@@ -614,9 +614,14 @@ void schedule_response(Sched_Rsp_t *Sched_INFO)
AssertFatal(RC.eNB[Mod_id]!=NULL,"RC.eNB[%d] is null\n",Mod_id);
AssertFatal(RC.eNB[Mod_id][CC_id]!=NULL,"RC.eNB[%d][%d] is null\n",Mod_id,CC_id);
eNB = RC.eNB[Mod_id][CC_id];
fp = &eNB->frame_parms;
proc = &eNB->proc.proc_rxtx[0];
if ((fp->frame_type == TDD) && (subframe_select(fp,subframe)==SF_UL)) return;
ul_subframe = pdcch_alloc2ul_subframe(fp,subframe);
ul_frame = pdcch_alloc2ul_frame(fp,frame,subframe);
......@@ -650,9 +655,10 @@ void schedule_response(Sched_Rsp_t *Sched_INFO)
int do_oai =0;
int dont_send =0;
if ((ul_subframe<10)&&
(subframe_select(fp,ul_subframe)==SF_UL)) { // This means that there is an ul_subframe that can be configured here
LOG_D(PHY,"NFAPI: Clearing dci allocations for potential UL subframe %d\n",ul_subframe);
if (ul_subframe<10) { // This means that there is an ul_subframe that can be configured here
LOG_D(PHY,"NFAPI: Clearing dci allocations for potential UL\n");
harq_pid = subframe2harq_pid(fp,ul_frame,ul_subframe);
// clear DCI allocation maps for new subframe
......
......@@ -416,6 +416,7 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
int offset = eNB->CC_id;//proc == &eNB->proc.proc_rxtx[0] ? 0 : 1;
if ((fp->frame_type == TDD) && (subframe_select(fp,subframe)==SF_UL)) return;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_ENB_TX+offset,1);
......@@ -451,7 +452,8 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
}
/* save old HARQ information needed for PHICH generation */
if (ul_subframe < 10) { // This means that there is a potential UL subframe that will be scheduled here
if ((ul_subframe < 10)&&
(subframe_select(fp,ul_subframe)==SF_UL)) { // This means that there is a potential UL subframe that will be scheduled here
for (i=0; i<NUMBER_OF_UE_MAX; i++) {
harq_pid = subframe2harq_pid(fp,ul_frame,ul_subframe);
if (eNB->ulsch[i]) {
......@@ -576,181 +578,6 @@ void phy_procedures_eNB_TX(PHY_VARS_eNB *eNB,
}
#ifdef Rel14
void prach_procedures(PHY_VARS_eNB *eNB,
int br_flag) {
#else
void prach_procedures(PHY_VARS_eNB *eNB) {
#endif
uint16_t max_preamble[4],max_preamble_energy[4],max_preamble_delay[4];
uint16_t i;
int frame,subframe;
#ifdef Rel14
if (br_flag==1) {
subframe = eNB->proc.subframe_prach_br;
frame = eNB->proc.frame_prach_br;
pthread_mutex_lock(&eNB->UL_INFO_mutex);
eNB->UL_INFO.rach_ind_br.rach_indication_body.number_of_preambles=0;
pthread_mutex_unlock(&eNB->UL_INFO_mutex);
}
else
#endif
{
pthread_mutex_lock(&eNB->UL_INFO_mutex);
eNB->UL_INFO.rach_ind.rach_indication_body.number_of_preambles=0;
pthread_mutex_unlock(&eNB->UL_INFO_mutex);
subframe = eNB->proc.subframe_prach;
frame = eNB->proc.frame_prach;
}
RU_t *ru;
int aa=0;
int ru_aa;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_ENB_PRACH_RX,1);
for (i=0;i<eNB->num_RU;i++) {
ru=eNB->RU_list[i];
for (ru_aa=0,aa=0;ru_aa<ru->nb_rx;ru_aa++,aa++) {
eNB->prach_vars.rxsigF[0][aa] = eNB->RU_list[i]->prach_rxsigF[ru_aa];
#ifdef Rel14
int ce_level;
if (br_flag==1)
for (ce_level=0;ce_level<4;ce_level++) eNB->prach_vars_br.rxsigF[ce_level][aa] = eNB->RU_list[i]->prach_rxsigF_br[ce_level][ru_aa];
#endif
}
}
rx_prach(eNB,
eNB->RU_list[0],
&max_preamble[0],
&max_preamble_energy[0],
&max_preamble_delay[0],
frame,
0
#ifdef Rel14
,br_flag
#endif
);
//#ifdef DEBUG_PHY_PROC
LOG_D(PHY,"[RAPROC] Frame %d, subframe %d : Most likely preamble %d, energy %d dB delay %d\n",
frame,subframe,
max_preamble[0],
max_preamble_energy[0]/10,
max_preamble_delay[0]);
//q#endif
#ifdef Rel14
if (br_flag==1) {
int prach_mask;
prach_mask = is_prach_subframe(&eNB->frame_parms,eNB->proc.frame_prach_br,eNB->proc.subframe_prach_br);
eNB->UL_INFO.rach_ind_br.rach_indication_body.preamble_list = eNB->preamble_list_br;
int ind=0;
int ce_level=0;
/* Save for later, it doesn't work
for (int ind=0,ce_level=0;ce_level<4;ce_level++) {
if ((eNB->frame_parms.prach_emtc_config_common.prach_ConfigInfo.prach_CElevel_enable[ce_level]==1)&&
(prach_mask&(1<<(1+ce_level)) > 0) && // prach is active and CE level has finished its repetitions
(eNB->prach_vars_br.repetition_number[ce_level]==
eNB->frame_parms.prach_emtc_config_common.prach_ConfigInfo.prach_numRepetitionPerPreambleAttempt[ce_level])) {
*/
if (eNB->frame_parms.prach_emtc_config_common.prach_ConfigInfo.prach_CElevel_enable[0]==1){
if ((eNB->prach_energy_counter == 100) &&
(max_preamble_energy[0] > eNB->measurements.prach_I0 + 100)) {
eNB->UL_INFO.rach_ind_br.rach_indication_body.number_of_preambles++;
eNB->preamble_list_br[ind].preamble_rel8.timing_advance = max_preamble_delay[ind];//
eNB->preamble_list_br[ind].preamble_rel8.preamble = max_preamble[ind];
// note: fid is implicitly 0 here, this is the rule for eMTC RA-RNTI from 36.321, Section 5.1.4
eNB->preamble_list_br[ind].preamble_rel8.rnti = 1+subframe+(eNB->prach_vars_br.first_frame[ce_level]%40);
eNB->preamble_list_br[ind].instance_length = 0; //don't know exactly what this is
eNB->preamble_list_br[ind].preamble_rel13.rach_resource_type = 1+ce_level; // CE Level
LOG_D(PHY,"Filling NFAPI indication for RACH %d CELevel %d (mask %x) : TA %d, Preamble %d, rnti %x, rach_resource_type %d\n",
ind,
ce_level,
prach_mask,
eNB->preamble_list_br[ind].preamble_rel8.timing_advance,
eNB->preamble_list_br[ind].preamble_rel8.preamble,
eNB->preamble_list_br[ind].preamble_rel8.rnti,
eNB->preamble_list_br[ind].preamble_rel13.rach_resource_type);
}
/*
ind++;
}
} */// ce_level
}
}