Commit cf8645d8 authored by gauthier's avatar gauthier

Limitation of non SI DLSCH allocations in subframe 0/5 to PRBS not around DC...

Limitation of non SI DLSCH allocations in subframe 0/5 to PRBS not around DC (avoid puncturing from PBCH). Placement of SI around DC instead of randomized allocations. Placement of RA allocations at PRB 0-3.  Tested DL throughput on 5 MHz to 16 Mbit/s in TM1.
parent a59cabd1
......@@ -257,7 +257,7 @@
#define AMP_OVER_2 (AMP>>1)
/// Threshold for PUCCH Format 1 detection
#define PUCCH1_THRES 4
#define PUCCH1_THRES 10
/// Threshold for PUCCH Format 1a/1b detection
#define PUCCH1a_THRES 4
......
......@@ -280,7 +280,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
} else { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,1,5);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -292,7 +292,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// FDD, normal UL/DLSCH
if (mac_xface->lte_frame_parms->frame_type == FDD) { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,2,6);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -320,7 +320,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
} else { //FDD
schedule_ulsch(module_idP,frameP,cooperation_flag,3,7);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -358,7 +358,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
// schedule_RA(module_idP,frameP, subframeP, 0);
schedule_ulsch(module_idP, frameP, cooperation_flag, 4, 8);
// schedule_ue_spec(module_idP, frameP, subframeP, mbsfn_status);
schedule_ue_spec(module_idP, frameP, subframeP, mbsfn_status);
fill_DLSCH_dci(module_idP, frameP, subframeP, mbsfn_status);
}
}
......@@ -428,7 +428,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
} else { //FDD
// schedule_ulsch(module_idP,frameP,cooperation_flag,6,0);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -457,7 +457,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
} else { //FDD
//schedule_ulsch(module_idP,frameP,cooperation_flag,7,1);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -486,7 +486,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
} else { //FDD
//schedule_ulsch(module_idP,frameP,cooperation_flag,8,2);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......@@ -530,7 +530,7 @@ void eNB_dlsch_ulsch_scheduler(module_id_t module_idP,uint8_t cooperation_flag,
}
} else { //FDD
// schedule_ulsch(module_idP,frameP,cooperation_flag,9,3);
// schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
schedule_ue_spec(module_idP,frameP,subframeP,mbsfn_status);
fill_DLSCH_dci(module_idP,frameP,subframeP,mbsfn_status);
}
......
......@@ -302,6 +302,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
// msg("[MAC][eNB] Frame %d, subframeP %d: Generated DLSCH (Msg4) DCI, format 1A, for UE %d\n",frameP, subframeP,UE_id);
// Schedule Reflection of Connection request
/*
// randomize frequency allocation for RA
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
......@@ -309,7 +310,9 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1))
break;
}
*/
first_rb=0;
vrb_map[first_rb] = 1;
vrb_map[first_rb+1] = 1;
vrb_map[first_rb+2] = 1;
......@@ -669,6 +672,7 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
((DCI1A_5MHz_FDD_t*)&RA_template->RA_alloc_pdu2[0])->ndi=1;
}
/*
// randomize frequency allocation for RA
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
......@@ -676,7 +680,8 @@ void schedule_RA(module_id_t module_idP,frame_t frameP, sub_frame_t subframeP,un
if ((vrb_map[first_rb] != 1) && (vrb_map[first_rb+3] != 1))
break;
}
*/
first_rb=0;
vrb_map[first_rb] = 1;
vrb_map[first_rb+1] = 1;
vrb_map[first_rb+2] = 1;
......
......@@ -111,6 +111,7 @@ schedule_SI(
LOG_D(MAC,"[eNB %d] Frame %d : BCCH->DLSCH CC_id %d, Received %d bytes \n",module_idP,frameP,CC_id,bcch_sdu_length);
// Allocate 4 PRBs in a random location
/*
while (1) {
first_rb = (unsigned char)(taus()%(PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL-4));
if ((vrb_map[first_rb] != 1) &&
......@@ -119,6 +120,25 @@ schedule_SI(
(vrb_map[first_rb+3] != 1))
break;
}
*/
switch (PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL) {
case 6:
first_rb = 0;
break;
case 15:
first_rb = 6;
break;
case 25:
first_rb = 11;
break;
case 50:
first_rb = 23;
break;
case 100:
first_rb = 48;
break;
}
vrb_map[first_rb] = 1;
vrb_map[first_rb+1] = 1;
vrb_map[first_rb+2] = 1;
......
......@@ -1041,8 +1041,12 @@ int allocate_CCEs(int module_idP,
}
} // fCCE>=0
else {
if (DCI_pdu->num_pdcch_symbols == 3)
if (DCI_pdu->num_pdcch_symbols == 3) {
allocation_is_feasible = 0;
LOG_I(MAC,"subframe %d: Dropping Allocation for RNTI %x\n",
subframeP,dci_alloc->rnti);
}
else {
DCI_pdu->num_pdcch_symbols++;
nCCE_max = mac_xface->get_nCCE_max(module_idP,CC_idP,DCI_pdu->num_pdcch_symbols,subframeP);
......
......@@ -176,6 +176,7 @@ void assign_rbs_required (module_id_t Mod_id,
eNB_UE_stats[CC_id]->DL_cqi[0], MIN_CQI_VALUE, MAX_CQI_VALUE);
*/
eNB_UE_stats[CC_id]->dlsch_mcs1=cqi_to_mcs[eNB_UE_stats[CC_id]->DL_cqi[0]];
eNB_UE_stats[CC_id]->dlsch_mcs1 = cmin(eNB_UE_stats[CC_id]->dlsch_mcs1,openair_daq_vars.target_ue_dl_mcs);
}
......@@ -729,6 +730,7 @@ void dlsch_scheduler_pre_processor (module_id_t Mod_id,
}
}
#define SF05_LIMIT 1
void dlsch_scheduler_pre_processor_reset (int module_idP,
int UE_id,
......@@ -748,8 +750,10 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
rnti_t rnti = UE_RNTI(module_idP,UE_id);
uint8_t *vrb_map = &eNB_mac_inst[module_idP].common_channels[CC_id].vrb_map;
int RBGsize = PHY_vars_eNB_g[module_idP][CC_id]->lte_frame_parms.N_RB_DL/N_RBG;
#ifdef SF05_LIMIT
int subframe05_limit=0;
int sf05_upper=-1,sf05_lower=-1;
#endif
// initialize harq_pid and round
mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,
frameP,subframeP,
......@@ -762,13 +766,46 @@ void dlsch_scheduler_pre_processor_reset (int module_idP,
ue_sched_ctl->dl_pow_off[CC_id] = 2;
nb_rbs_required_remaining[CC_id][UE_id] = 0;
#ifdef SF05_LIMIT
switch (N_RBG) {
case 6:
sf05_lower=0;
sf05_upper=5;
break;
case 8:
sf05_lower=2;
sf05_upper=5;
break;
case 13:
sf05_lower=4;
sf05_upper=7;
break;
case 17:
sf05_lower=7;
sf05_upper=9;
break;
case 25:
sf05_lower=11;
sf05_upper=13;
break;
}
#endif
// Initialize Subbands according to VRB map
for (i=0; i<N_RBG; i++) {
ue_sched_ctl->rballoc_sub_UE[CC_id][i] = 0;
rballoc_sub[CC_id][i] = 0;
#ifdef SF05_LIMIT
// for avoiding 6+ PRBs around DC in subframe 0-5 (avoid excessive errors)
if ((subframeP==0 || subframeP==5) &&
(i>=sf05_lower && i<=sf05_upper))
rballoc_sub[CC_id][i]=1;
#endif
// for SI-RNTI,RA-RNTI and P-RNTI allocations
for (j=0;j<RBGsize;j++) {
if (vrb_map[j+(i*RBGsize)]!=0) {
if (vrb_map[j+(i*RBGsize)]!=0) {
rballoc_sub[CC_id][i] = 1;
LOG_D(MAC,"Frame %d, subframe %d : vrb %d allocated\n",frameP,subframeP,j+(i*RBGsize));
break;
}
}
......
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