NR PDCCH: dci field interpreting in FAPI / Adding DCI format 0_1 and 1_1

parent 753d4b70
......@@ -37,8 +37,8 @@ typedef struct {
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t tpc_cmd_number ; // 5 TPC_CMD_NUMBER: The parameter xxx provided by higher layers determines the index to the TPC command number for an UL of a cell. Each TPC command number is 2 bits
uint8_t block_number ; // 6 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
......@@ -81,7 +81,7 @@ typedef struct {
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd_number_format2_3 ; // 41 TPC_CMD_NUMBER_FORMAT2_3:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
......@@ -225,13 +225,19 @@ typedef struct {
typedef struct {
} fapi_nr_ul_config_pucch_pdu;
typedef enum {pusch_freq_hopping_disabled = 0 , pusch_freq_hopping_enabled = 1}pusch_freq_hopping_t;
typedef struct {
uint16_t number_rbs;
uint16_t start_rb;
uint16_t number_symbols;
uint16_t start_symbol;
pusch_freq_hopping_t pusch_freq_hopping;
uint8_t mcs;
uint8_t ndi;
uint8_t rv;
uint8_t harq_process_nbr;
int8_t accumulated_delta_PUSCH;
int8_t absolute_delta_PUSCH;
} fapi_nr_ul_config_pusch_pdu_rel15_t;
typedef struct {
......@@ -273,6 +279,7 @@ typedef struct {
fapi_nr_dl_config_dci_dl_pdu_rel15_t dci_config_rel15;
} fapi_nr_dl_config_dci_pdu;
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint16_t number_rbs;
......@@ -280,7 +287,18 @@ typedef struct {
uint16_t number_symbols;
uint16_t start_symbol;
uint8_t mcs;
uint8_t ndi;
uint8_t rv;
uint8_t tb2_mcs;
uint8_t tb2_ndi;
uint8_t tb2_rv;
uint8_t harq_process_nbr;
vrb_to_prb_mapping_t vrb_to_prb_mapping;
uint8_t dai;
double scaling_factor_S;
int8_t accumulated_delta_PUCCH;
uint8_t pucch_resource_id;
uint8_t pdsch_to_harq_feedback_time_ind;
// to be check the fields needed to L1 with NR_DL_UE_HARQ_t and NR_UE_DLSCH_t
} fapi_nr_dl_config_dlsch_pdu_rel15_t;
......
This diff is collapsed.
......@@ -49,8 +49,8 @@ struct NR_DCI_INFO_EXTRACTED {
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t tpc_cmd_number ; // 5 TPC_CMD_NUMBER: The parameter xxx provided by higher layers determines the index to the TPC command number for an UL of a cell. Each TPC command number is 2 bits
uint8_t block_number ; // 6 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
......@@ -93,7 +93,7 @@ struct NR_DCI_INFO_EXTRACTED {
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd_number_format2_3 ; // 41 TPC_CMD_NUMBER_FORMAT2_3:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
......
This diff is collapsed.
......@@ -145,6 +145,10 @@ typedef struct {
// int calibration_flag;
/// Number of soft channel bits
uint32_t G;
// number of symbols
uint8_t nb_symbols;
// first symbol in the slot
uint8_t start_symbol;
// decode phich
uint8_t decode_phich;
......
......@@ -624,8 +624,8 @@ typedef struct {
#define SUL_IND_0_1 2
#define SLOT_FORMAT_IND 3
#define PRE_EMPTION_IND 4
#define TPC_CMD_NUMBER 5
#define BLOCK_NUMBER 6
#define BLOCK_NUMBER 5
#define CLOSE_LOOP_IND 6
#define BANDWIDTH_PART_IND 7
#define SHORT_MESSAGE_IND 8
#define SHORT_MESSAGES 9
......@@ -660,7 +660,7 @@ typedef struct {
#define ANTENNA_PORTS 38
#define TCI 39
#define SRS_REQUEST 40
#define TPC_CMD_NUMBER_FORMAT2_3 41
#define TPC_CMD 41
#define CSI_REQUEST 42
#define CBGTI 43
#define CBGFI 44
......@@ -732,7 +732,7 @@ typedef struct {
} NR_UE_CORESET_CCE_REG_MAPPING_t;
typedef enum {allContiguousRBs=0,sameAsREGbundle=1} NR_UE_CORESET_precoder_granularity_t;
typedef enum {tciPresentInDCI_enabled = 1} tciPresentInDCI_t;
typedef struct {
/*
* define CORESET structure according to 38.331
......@@ -771,7 +771,7 @@ typedef struct {
NR_UE_CORESET_CCE_REG_MAPPING_t cce_reg_mappingType;
NR_UE_CORESET_precoder_granularity_t precoderGranularity;
int tciStatesPDCCH;
int tciPresentInDCI;
tciPresentInDCI_t tciPresentInDCI;
uint16_t pdcchDMRSScramblingID;
uint16_t rb_offset;
} NR_UE_PDCCH_CORESET;
......@@ -1214,6 +1214,14 @@ typedef struct {
PUCCH_Config_t pucch_config_dedicated_nr[NUMBER_OF_CONNECTED_eNB_MAX];
PUSCH_Config_t pusch_config;
SRS_NR srs;
crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig;
supplementaryUplink_t supplementaryUplink;
dmrs_UplinkConfig_t dmrs_UplinkConfig;
dmrs_DownlinkConfig_t dmrs_DownlinkConfig;
csi_MeasConfig_t csi_MeasConfig;
PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig;
#endif
......
......@@ -372,12 +372,104 @@ typedef struct {
/* FFS TODO_NR partial structure that should be complete */
typedef enum {
semiStatic = 0,
dynamic = 1
} pdsch_HARQ_ACK_Codebook_t;
////////////////////////////////////////////////////////////////////////////////################################
#define MAX_NR_RATE_MATCH_PATTERNS 4
#define MAX_NR_ZP_CSI_RS_RESOURCES 32
typedef enum{
dl_resourceAllocationType0 = 1,
dl_resourceAllocationType1 = 2,
dl_dynamicSwitch = 3
} dl_resourceAllocation_t;
typedef enum{
dl_rgb_config1 = 1,
dl_rgb_config2 = 2
} dl_rgb_Size_t;
typedef enum {
st_n4 = 1,
st_wideband = 2
} static_bundleSize_t;
typedef enum {
dy_1_n4 = 1,
dy_1_wideband = 2,
dy_1_n2_wideband = 3,
dy_1_n4_wideband = 4
} bundleSizeSet1_t;
typedef enum {
dy_2_n4 = 1,
dy_2_wideband = 2,
} bundleSizeSet2_t;
typedef struct{
bundleSizeSet1_t bundleSizeSet1;
bundleSizeSet2_t bundleSizeSet2;
} dynamic_bundleSize_t;
typedef struct {
static_bundleSize_t staticBundling;
dynamic_bundleSize_t dynamicBundlig;
} prb_bundleType_t;
typedef enum {
nb_code_n1 = 1,
nb_code_n2 = 2
} maxNrofCodeWordsScheduledByDCI_t;
typedef struct{
// to be defined FIXME!!!
}rateMatchPattern_t;
typedef struct{
// to be defined FIXME!!!
}zp_CSI_RS_Resource_t;
typedef struct {
/*
* resourceAllocation
*/
dl_resourceAllocation_t dl_resourceAllocation;
/*
* corresponds to I, where I the number of entries in the higher layer parameter pdsch-AllocationList
*/
uint8_t n_pdsh_alloc_list;
/*
* rateMatchPatternToAddModList
*/
rateMatchPattern_t rateMatchPatternToAddModList[MAX_NR_RATE_MATCH_PATTERNS];
/*
* rateMatchPatternToReleaseList
*/
uint8_t rateMatchPatternToReleaseList[MAX_NR_RATE_MATCH_PATTERNS];
/*
* n_rateMatchPatterns indicates the number of rateMatchPatterns defined currently
*/
uint8_t n_rateMatchPatterns;
/*
* zp-CSI-RS-ResourceToAddModList
*/
zp_CSI_RS_Resource_t zp_CSI_RS_Resource[MAX_NR_ZP_CSI_RS_RESOURCES];
/*
* zp-CSI-RS-ResourceToReleaseList
*/
uint8_t zp_CSI_RS_ResourceId[MAX_NR_ZP_CSI_RS_RESOURCES];
/*
* n_zp-CSI-RS-Resource
*/
uint8_t n_zp_CSI_RS_ResourceId;
/*
* rgb_Size
*/
dl_rgb_Size_t dl_rgbSize;
/*
* prb-BundlingType
*/
prb_bundleType_t prbBundleType;
/*
* pdsch-HARQ-ACK-Codebook: this is part of the IE PhysicalCellGroupConfig which is used to configure cell-group specific L1 parameters (TS 38.331)
*/
pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook;
////////////////////////////////////////////////////////////////////////////////################################
/*
Maximum number of code words that a single DCI may schedule. This changes the number of MCS/RV/NDI bits in the DCI message from 1 to 2.
*/
......@@ -415,8 +507,168 @@ typedef struct {
mappingType_t mappingType;
uint8_t startSymbolAndLength;
} PUSCH_TimeDomainResourceAllocation_t;
////////////////////////////////////////////////////////////////////////////////################################
typedef struct { // The IE PTRS-UplinkConfig is used to configure uplink Phase-Tracking-Reference-Signals (PTRS)
} ptrs_UplinkConfig_t;
typedef enum{
maxCodeBlockGroupsPerTransportBlock_n2 = 2,
maxCodeBlockGroupsPerTransportBlock_n4 = 4,
maxCodeBlockGroupsPerTransportBlock_n6 = 6,
maxCodeBlockGroupsPerTransportBlock_n8 = 8
} maxCodeBlockGroupsPerTransportBlock_t;
typedef struct{ // The IE PUSCH-ServingCellConfig is used to configure UE specific PUSCH parameters that are common across the UE's BWPs of one serving cell
maxCodeBlockGroupsPerTransportBlock_t maxCodeBlockGroupsPerTransportBlock;
} PUSCH_ServingCellConfig_t;
typedef struct{ // CSI-MeasConfig IE is used to configure CSI-RS (reference signals)
uint8_t reportTriggerSize;
} csi_MeasConfig_t;
typedef enum {
pdsch_dmrs_type1 = 1,
pdsch_dmrs_type2 = 2
} pdsch_dmrs_type_t;
typedef enum {
pusch_dmrs_type1 = 1,
pusch_dmrs_type2 = 2
} pusch_dmrs_type_t;
typedef enum {
pdsch_dmrs_pos0 = 0,
pdsch_dmrs_pos1 = 1,
pdsch_dmrs_pos3 = 3,
} pdsch_dmrs_AdditionalPosition_t;
typedef enum {
pusch_dmrs_pos0 = 0,
pusch_dmrs_pos1 = 1,
pusch_dmrs_pos3 = 3,
} pusch_dmrs_AdditionalPosition_t;
typedef enum {
pdsch_len1 = 1,
pdsch_len2 = 2
} pdsch_maxLength_t;
typedef enum {
pusch_len1 = 1,
pusch_len2 = 2
} pusch_maxLength_t;
typedef struct { // The IE DMRS-DownlinkConfig is used to configure downlink demodulation reference signals for PDSCH
pdsch_dmrs_type_t pdsch_dmrs_type;
pdsch_dmrs_AdditionalPosition_t pdsch_dmrs_AdditionalPosition;
pdsch_maxLength_t pdsch_maxLength;
uint16_t scramblingID0;
uint16_t scramblingID1;
} dmrs_DownlinkConfig_t;
typedef struct { // The IE DMRS-UplinkConfig is used to configure uplink demodulation reference signals for PUSCH
pusch_dmrs_type_t pusch_dmrs_type;
pusch_dmrs_AdditionalPosition_t pusch_dmrs_AdditionalPosition;
pusch_maxLength_t pusch_maxLength;
uint16_t scramblingID0;
uint16_t scramblingID1;
} dmrs_UplinkConfig_t;
typedef struct {
/*
* Serving cell ID of a PSCell. The PCell of the Master Cell Group uses ID = 0
*/
uint8_t servCellIndex;
}servCellIndex_t;
typedef struct{
uint8_t cif_presence;
}own_t;
typedef struct{
servCellIndex_t scheduling_cell_id;
uint8_t cif_InSchedulingCell;
}other_t;
typedef struct{
own_t own;
other_t other;
}schedulingCellInfo_t;
typedef struct{
schedulingCellInfo_t schedulingCellInfo;
} crossCarrierSchedulingConfig_t;
typedef struct{
// this variable will be filled with '1' if SUL is supported and '0' if SUL is not supported
uint8_t supplementaryUplink;
}supplementaryUplink_t;
typedef enum {
txConfig_codebook = 1,
txConfig_nonCodebook = 2
} txConfig_t;
typedef enum {
f_hop_mode1 = 1,
f_hop_mode2 = 2
} frequencyHopping_t;
typedef enum{
ul_resourceAllocationType0 = 1,
ul_resourceAllocationType1 = 2,
ul_dynamicSwitch = 3
} ul_resourceAllocation_t;
typedef enum{
ul_rgb_config1 = 1,
ul_rgb_config2 = 2
} ul_rgb_Size_t;
typedef enum {
transformPrecoder_enabled = 1,
transformPrecoder_disabled = 2
} transformPrecoder_t;
typedef enum {
codebookSubset_fullyAndPartialAndNonCoherent = 1,
codebookSubset_partialAndNonCoherent = 2,
codebookSubset_nonCoherent = 3
} codebookSubset_t;
typedef enum{
betaOffset_dynamic = 1,
betaOffset_semiStatic = 2
}betaOffset_type_t;
typedef struct{
} betaOffset_t;
typedef struct {
betaOffset_type_t betaOffset_type;
betaOffset_t betaOffset;
} uci_onPusch_t;
typedef struct {
/*
* txConfig
*/
txConfig_t txConfig;
/*
* frequencyHopping
*/
frequencyHopping_t frequencyHopping;
/*
* frequencyHoppingOffsetLists
*/
uint16_t frequencyHoppingOffsetLists[4];
// n_frequencyHoppingOffsetLists contains the number of offsets listed. We can list up to 4 offsets
uint8_t n_frequencyHoppingOffsetLists;
/*
* resourceAllocation
*/
ul_resourceAllocation_t ul_resourceAllocation;
/*
* rgb_Size
*/
ul_rgb_Size_t ul_rgbSize;
/*
* corresponds to I, where I the number of entries in the higher layer parameter pusch-AllocationList
*/
uint8_t n_push_alloc_list;
/*
* transformPrecoder
*/
transformPrecoder_t transformPrecoder;
/*
* codebookSubset
*/
codebookSubset_t codebookSubset;
/*
* maxRank
*/
uint8_t maxRank;
/*
* uci_onPusch
*/
uci_onPusch_t uci_onPusch;
////////////////////////////////////////////////////////////////////////////////################################
PUSCH_PowerControl_t pusch_PowerControl;
PUSCH_TimeDomainResourceAllocation_t *pusch_TimeDomainResourceAllocation[MAX_NR_OF_UL_ALLOCATIONS];
} PUSCH_Config_t;
......@@ -649,11 +901,6 @@ typedef struct {
typedef uint16_t RNTI_value_t;
typedef enum {
semiStatic = 0,
dynamic = 1
} pdsch_HARQ_ACK_Codebook_t;
typedef struct {
/*
-- Enables spatial bundling of HARQ ACKs. It is configured per cell group (i.e. for all the cells within the cell group) for PUCCH
......@@ -750,6 +997,12 @@ typedef enum {
n12_dl_harq = 12,
n16_dl_harq = 16
} nrofHARQ_ProcessesForPDSCH_t;
typedef enum{
maxCodeBlockGroupsPerTransportBlock_dl_n2 = 2,
maxCodeBlockGroupsPerTransportBlock_dl_n4 = 4,
maxCodeBlockGroupsPerTransportBlock_dl_n6 = 6,
maxCodeBlockGroupsPerTransportBlock_dl_n8 = 8
} maxCodeBlockGroupsPerTransportBlock_dl_t;
typedef struct {
/*
......@@ -772,7 +1025,14 @@ typedef struct {
-- If the field is absent, the UE sends the HARQ feedback on the PUCCH of the SpCell of this cell group.
*/
uint8_t pucch_Cell;
/*
* maxCodeBlockGroupsPerTransportBlock_dl_t
*/
maxCodeBlockGroupsPerTransportBlock_dl_t maxCodeBlockGroupsPerTransportBlock_dl;
/*
* codeBlockGroupFlushIndicator (boolean)
*/
uint8_t codeBlockGroupFlushIndicator;
} PDSCH_ServingCellConfig_t;
/***********************************************************************
......
......@@ -49,6 +49,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
if(scheduled_response != NULL){
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[0][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[0];
if(scheduled_response->dl_config != NULL){
fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config;
......@@ -86,16 +88,47 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
//pdcch_vars2->coreset[i].tciStatesPDCCH;
//pdcch_vars2->coreset[i].tciPresentInDCI;
pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config->coreset.pdcch_dmrs_scrambling_id;
}else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
// dlsch config pdu
}
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15;
uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr;
dlsch0->current_harq_pid = current_harq_pid;
dlsch0->active = 1;
dlsch0->harq_processes[current_harq_pid]->nb_rb = dlsch_config_pdu->number_rbs;
dlsch0->harq_processes[current_harq_pid]->start_rb = dlsch_config_pdu->start_rb;
dlsch0->harq_processes[current_harq_pid]->nb_symbols = dlsch_config_pdu->number_symbols;
dlsch0->harq_processes[current_harq_pid]->start_symbol = dlsch_config_pdu->start_symbol;
dlsch0->harq_processes[current_harq_pid]->mcs = dlsch_config_pdu->mcs;
dlsch0->harq_processes[current_harq_pid]->DCINdi = dlsch_config_pdu->ndi;
dlsch0->harq_processes[current_harq_pid]->rvidx = dlsch_config_pdu->rv;
dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH;
dlsch0->harq_processes[current_harq_pid]->harq_ack.pucch_resource_indicator = dlsch_config_pdu->pucch_resource_id;
dlsch0->harq_processes[current_harq_pid]->harq_ack.slot_for_feedback_ack = dlsch_config_pdu->pdsch_to_harq_feedback_time_ind;
//pdlsch0->rnti = rnti;
}
}
}else{
pdcch_vars2->nb_search_space = 0;
}
if(scheduled_response->ul_config != NULL){
fapi_nr_ul_config_request_t *ul_config = scheduled_response->ul_config;
for(i=0; i<ul_config->number_pdus; ++i){
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_PUSCH){
// pusch config pdu
fapi_nr_ul_config_pusch_pdu_rel15_t *pusch_config_pdu = &ul_config->ul_config_list[i].ulsch_config_pdu.ulsch_pdu_rel15;
uint8_t current_harq_pid = pusch_config_pdu->harq_process_nbr;
ulsch0->harq_processes[current_harq_pid]->nb_rb = pusch_config_pdu->number_rbs;
ulsch0->harq_processes[current_harq_pid]->first_rb = pusch_config_pdu->start_rb;
ulsch0->harq_processes[current_harq_pid]->nb_symbols = pusch_config_pdu->number_symbols;
ulsch0->harq_processes[current_harq_pid]->start_symbol = pusch_config_pdu->start_symbol;
ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs;
ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi;
ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv;
ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
}
}
}else{
}
......
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