Commit d56525c8 authored by knopp's avatar knopp

NFAPI UL indications added and full UE connection tested.

parent 8da1c4b5
......@@ -1722,7 +1722,7 @@ add_executable(lte-softmodem
${T_SOURCE}
)
target_link_libraries (lte-softmodem -ldl
target_link_libraries (lte-softmodem -ldl
-Wl,--start-group
RRC_LIB S1AP_LIB S1AP_ENB GTPV1U SECU_CN SECU_OSA UTIL HASHTABLE SCTP_CLIENT UDP SCHED_LIB PHY LFDS L2 ${MSC_LIB} ${RAL_LIB} ${NAS_UE_LIB} ${ITTI_LIB} ${MIH_LIB} ${FLPT_MSG_LIB} ${ASYNC_IF_LIB} ${FLEXRAN_AGENT_LIB} LFDS7
-Wl,--end-group )
......
......@@ -97,14 +97,21 @@ void phy_config_request(PHY_Config_t *phy_config) {
fp->nushift = fp->Nid_cell%6;
fp->eutra_band = eutra_band;
fp->Ncp = Ncp;
fp->Ncp_UL = Ncp;
fp->nb_antenna_ports_eNB = p_eNB;
fp->threequarter_fs = 0;
AssertFatal(cfg->phich_config.phich_resource.value<4, "Illegal phich_Resource\n");
fp->phich_config_common.phich_resource = phich_resource_table[cfg->phich_config.phich_resource.value];
fp->phich_config_common.phich_duration = cfg->phich_config.phich_duration.value;
fp->dl_CarrierFreq = from_earfcn(eutra_band,dl_CarrierFreq);
fp->ul_CarrierFreq = fp->dl_CarrierFreq - get_uldl_offset(eutra_band);
fp->ul_CarrierFreq = fp->dl_CarrierFreq - (get_uldl_offset(eutra_band)*100000);
fp->tdd_config = 0;
fp->tdd_config_S = 0;
if (fp->dl_CarrierFreq==fp->ul_CarrierFreq)
fp->frame_type = TDD;
else
......@@ -177,16 +184,20 @@ void phy_config_request(PHY_Config_t *phy_config) {
init_ul_hopping(fp);
fp->soundingrs_ul_config_common.enabled_flag = 1;
fp->soundingrs_ul_config_common.enabled_flag = 0;// 1; Don't know how to turn this off in NFAPI
fp->soundingrs_ul_config_common.srs_BandwidthConfig = cfg->srs_config.bandwidth_configuration.value;
fp->soundingrs_ul_config_common.srs_SubframeConfig = cfg->srs_config.srs_subframe_configuration.value;
fp->soundingrs_ul_config_common.ackNackSRS_SimultaneousTransmission = cfg->srs_config.srs_acknack_srs_simultaneous_transmission.value;
fp->soundingrs_ul_config_common.srs_MaxUpPts = cfg->srs_config.max_up_pts.value;
fp->num_MBSFN_config = 0;
init_ncs_cell(fp,RC.eNB[Mod_id][CC_id]->ncs_cell);
init_ul_hopping(fp);
init_ul_hopping(fp);
RC.eNB[Mod_id][CC_id]->configured = 1;
LOG_I(PHY,"eNB %d/%d configured\n",Mod_id,CC_id);
}
void phy_config_sib1_ue(uint8_t Mod_id,int CC_id,
......@@ -1651,7 +1662,7 @@ int phy_init_lte_eNB(PHY_VARS_eNB *eNB,
lte_gold(fp,eNB->lte_gold_table,fp->Nid_cell);
generate_pcfich_reg_mapping(fp);
generate_phich_reg_mapping(fp);
for (UE_id=0; UE_id<NUMBER_OF_UE_MAX; UE_id++) {
eNB->first_run_timing_advance[UE_id] =
1; ///This flag used to be static. With multiple eNBs this does no longer work, hence we put it in the structure. However it has to be initialized with 1, which is performed here.
......@@ -1668,6 +1679,7 @@ int phy_init_lte_eNB(PHY_VARS_eNB *eNB,
if (abstraction_flag==0) {
common_vars->rxdata = (int32_t **)NULL;
common_vars->txdataF = (int32_t **)malloc16(NB_ANTENNA_PORTS_ENB*sizeof(int32_t*));
common_vars->rxdataF = (int32_t **)malloc16(64*sizeof(int32_t*));
......@@ -1683,17 +1695,17 @@ int phy_init_lte_eNB(PHY_VARS_eNB *eNB,
// Channel estimates for SRS
for (UE_id=0; UE_id<NUMBER_OF_UE_MAX; UE_id++) {
srs_vars[UE_id].srs_ch_estimates = (int32_t**)malloc16( fp->nb_antennas_rx*sizeof(int32_t*) );
srs_vars[UE_id].srs_ch_estimates_time = (int32_t**)malloc16( fp->nb_antennas_rx*sizeof(int32_t*) );
for (i=0; i<fp->nb_antennas_rx; i++) {
srs_vars[UE_id].srs_ch_estimates[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size );
srs_vars[UE_id].srs_ch_estimates_time[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2 );
}
} //UE_id
// Channel estimates for SRS
for (UE_id=0; UE_id<NUMBER_OF_UE_MAX; UE_id++) {
srs_vars[UE_id].srs_ch_estimates = (int32_t**)malloc16( 64*sizeof(int32_t*) );
srs_vars[UE_id].srs_ch_estimates_time = (int32_t**)malloc16( 64*sizeof(int32_t*) );
for (i=0; i<64; i++) {
srs_vars[UE_id].srs_ch_estimates[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size );
srs_vars[UE_id].srs_ch_estimates_time[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2 );
}
} //UE_id
} // abstraction_flag = 0
else { //UPLINK abstraction = 1
eNB->sinr_dB = (double*) malloc16_clear( fp->N_RB_DL*12*sizeof(double) );
......@@ -1732,28 +1744,28 @@ int phy_init_lte_eNB(PHY_VARS_eNB *eNB,
pusch_vars[UE_id] = (LTE_eNB_PUSCH*)malloc16_clear( NUMBER_OF_UE_MAX*sizeof(LTE_eNB_PUSCH) );
if (abstraction_flag==0) {
for (eNB_id=0; eNB_id<3; eNB_id++) {
pusch_vars[UE_id]->rxdataF_ext = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->rxdataF_ext2 = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->drs_ch_estimates = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->drs_ch_estimates_time = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->rxdataF_comp = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->ul_ch_mag = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->ul_ch_magb = (int32_t**)malloc16( 2*sizeof(int32_t*) );
for (i=0; i<2; i++) {
// RK 2 times because of output format of FFT!
// FIXME We should get rid of this
pusch_vars[UE_id]->rxdataF_ext[i] = (int32_t*)malloc16_clear( 2*sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->rxdataF_ext2[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->drs_ch_estimates[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->drs_ch_estimates_time[i] = (int32_t*)malloc16_clear( 2*2*sizeof(int32_t)*fp->ofdm_symbol_size );
pusch_vars[UE_id]->rxdataF_comp[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->ul_ch_mag[i] = (int32_t*)malloc16_clear( fp->symbols_per_tti*sizeof(int32_t)*fp->N_RB_UL*12 );
pusch_vars[UE_id]->ul_ch_magb[i] = (int32_t*)malloc16_clear( fp->symbols_per_tti*sizeof(int32_t)*fp->N_RB_UL*12 );
}
} //eNB_id
pusch_vars[UE_id]->rxdataF_ext = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->rxdataF_ext2 = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->drs_ch_estimates = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->drs_ch_estimates_time = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->rxdataF_comp = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->ul_ch_mag = (int32_t**)malloc16( 2*sizeof(int32_t*) );
pusch_vars[UE_id]->ul_ch_magb = (int32_t**)malloc16( 2*sizeof(int32_t*) );
AssertFatal(fp->ofdm_symbol_size > 127, "fp->ofdm_symbol_size %d<128\n",fp->ofdm_symbol_size);
AssertFatal(fp->symbols_per_tti > 11, "fp->symbols_per_tti %d < 12\n",fp->symbols_per_tti);
AssertFatal(fp->N_RB_UL > 5, "fp->N_RB_UL %d < 6\n",fp->N_RB_UL);
for (i=0; i<2; i++) {
// RK 2 times because of output format of FFT!
// FIXME We should get rid of this
pusch_vars[UE_id]->rxdataF_ext[i] = (int32_t*)malloc16_clear( 2*sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->rxdataF_ext2[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->drs_ch_estimates[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->drs_ch_estimates_time[i] = (int32_t*)malloc16_clear( 2*2*sizeof(int32_t)*fp->ofdm_symbol_size );
pusch_vars[UE_id]->rxdataF_comp[i] = (int32_t*)malloc16_clear( sizeof(int32_t)*fp->N_RB_UL*12*fp->symbols_per_tti );
pusch_vars[UE_id]->ul_ch_mag[i] = (int32_t*)malloc16_clear( fp->symbols_per_tti*sizeof(int32_t)*fp->N_RB_UL*12 );
pusch_vars[UE_id]->ul_ch_magb[i] = (int32_t*)malloc16_clear( fp->symbols_per_tti*sizeof(int32_t)*fp->N_RB_UL*12 );
}
pusch_vars[UE_id]->llr = (int16_t*)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) );
} // abstraction_flag
......
......@@ -304,6 +304,11 @@ void freq_equalization(LTE_DL_FRAME_PARMS *frame_parms,
ul_ch_magb128 = (int16x8_t*)&ul_ch_magb[0][symbol*frame_parms->N_RB_DL*12];
#endif
AssertFatal(symbol<frame_parms->symbols_per_tti,"symbol %d >= %d\n",
symbol,frame_parms->symbols_per_tti);
AssertFatal(Msc_RS<frame_parms->N_RB_UL*12,"Msc_RS %d >= %d\n",
Msc_RS,frame_parms->N_RB_UL*12);
for (re=0; re<(Msc_RS>>2); re++) {
amp=(*((int16_t*)&ul_ch_mag128[re]));
......
......@@ -210,7 +210,9 @@ int lte_est_timing_advance_pusch(PHY_VARS_eNB* eNB,uint8_t UE_id)
uint8_t cyclic_shift = 0;
int sync_pos = (frame_parms->ofdm_symbol_size-cyclic_shift*frame_parms->ofdm_symbol_size/12)%(frame_parms->ofdm_symbol_size);
AssertFatal(frame_parms->ofdm_symbol_size > 127,"frame_parms->ofdm_symbol_size %d<128\n",frame_parms->ofdm_symbol_size);
AssertFatal(frame_parms->nb_antennas_rx >0 && frame_parms->nb_antennas_rx<3,"frame_parms->nb_antennas_rx %d not in [0,1]\n",
frame_parms->nb_antennas_rx);
for (i = 0; i < frame_parms->ofdm_symbol_size; i++) {
temp = 0;
......@@ -236,9 +238,9 @@ int lte_est_timing_advance_pusch(PHY_VARS_eNB* eNB,uint8_t UE_id)
} else
max_pos_fil2 = ((max_pos_fil2 * coef) + (max_pos * ncoef)) >> 15;
#ifdef DEBUG_PHY
LOG_D(PHY,"frame %d: max_pos = %d, max_pos_fil = %d, sync_pos=%d\n",eNB->proc.frame_rx,max_pos,max_pos_fil2,sync_pos);
#endif //DEBUG_PHY
//#ifdef DEBUG_PHY
LOG_I(PHY,"frame %d: max_pos = %d, max_pos_fil = %d, sync_pos=%d\n",eNB->proc.frame_rx,max_pos,max_pos_fil2,sync_pos);
//#endif //DEBUG_PHY
return(max_pos_fil2-sync_pos);
}
......@@ -216,12 +216,14 @@ uint8_t *generate_dci0(uint8_t *dci,
uint16_t coded_bits;
uint8_t dci_flip[8];
if (aggregation_level>3) {
printf("dci.c: generate_dci FATAL, illegal aggregation_level %d\n",aggregation_level);
return NULL;
}
AssertFatal((aggregation_level==1) ||
(aggregation_level==2) ||
(aggregation_level==4) ||
(aggregation_level==8),
"generate_dci FATAL, illegal aggregation_level %d\n",aggregation_level);
coded_bits = 72 * (1<<aggregation_level);
coded_bits = 72 * aggregation_level;
/*
......@@ -1967,7 +1969,7 @@ void pdcch_unscrambling(LTE_DL_FRAME_PARMS *frame_parms,
}
}
/*
uint8_t get_num_pdcch_symbols(uint8_t num_dci,
DCI_ALLOC_t *dci_alloc,
LTE_DL_FRAME_PARMS *frame_parms,
......@@ -2036,8 +2038,10 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,
//exit(-1);
return(0);
}
*/
uint8_t generate_dci_top(uint8_t num_dci,
uint8_t generate_dci_top(uint8_t num_pdcch_symbols,
uint8_t num_dci,
DCI_ALLOC_t *dci_alloc,
uint32_t n_rnti,
int16_t amp,
......@@ -2046,7 +2050,7 @@ uint8_t generate_dci_top(uint8_t num_dci,
uint32_t subframe)
{
uint8_t *e_ptr,num_pdcch_symbols;
uint8_t *e_ptr;
int8_t L;
uint32_t i, lprime;
uint32_t gain_lin_QPSK,kprime,kprime_mod12,mprime,nsymb,symbol_offset,tti_offset;
......@@ -2093,8 +2097,7 @@ uint8_t generate_dci_top(uint8_t num_dci,
break;
}
num_pdcch_symbols = get_num_pdcch_symbols(num_dci,dci_alloc,frame_parms,subframe);
generate_pcfich(num_pdcch_symbols,
amp,
frame_parms,
......@@ -2115,13 +2118,13 @@ uint8_t generate_dci_top(uint8_t num_dci,
// generate DCIs in order of decreasing aggregation level, then common/ue spec
// MAC is assumed to have ordered the UE spec DCI according to the RNTI-based randomization
for (L=3; L>=0; L--) {
for (L=8; L>=1; L>>=1) {
for (i=0; i<num_dci; i++) {
if (dci_alloc[i].L == (uint8_t)L) {
//#ifdef DEBUG_DCI_ENCODING
LOG_I(PHY,"Generating DCI %d/%d (nCCE %d) of length %d, aggregation %d (%x)\n",i,num_dci,dci_alloc[i].firstCCE,dci_alloc[i].dci_length,1<<dci_alloc[i].L,
LOG_I(PHY,"Generating DCI %d/%d (nCCE %d) of length %d, aggregation %d (%x)\n",i,num_dci,dci_alloc[i].firstCCE,dci_alloc[i].dci_length,dci_alloc[i].L,
*(unsigned int*)dci_alloc[i].dci_pdu);
dump_dci(frame_parms,&dci_alloc[i]);
//#endif
......@@ -2360,10 +2363,8 @@ void dci_decoding(uint8_t DCI_LENGTH,
int32_t i;
#endif
if (aggregation_level>3) {
LOG_I(PHY," dci.c: dci_decoding FATAL, illegal aggregation_level %d\n",aggregation_level);
return;
}
AssertFatal(aggregation_level<4,
"dci_decoding FATAL, illegal aggregation_level %d\n",aggregation_level);
coded_bits = 72 * (1<<aggregation_level);
......
......@@ -802,9 +802,9 @@ int8_t find_ulsch(uint16_t rnti, PHY_VARS_eNB *eNB,find_type_t type)
uint8_t i;
int8_t first_free_index=-1;
AssertFatal(eNB==NULL,"eNB is null\n");
AssertFatal(eNB!=NULL,"eNB is null\n");
for (i=0; i<NUMBER_OF_UE_MAX; i++) {
AssertFatal(eNB->ulsch[i]==NULL,"eNB->dlsch[%d] is null\n",i);
AssertFatal(eNB->ulsch[i]!=NULL,"eNB->dlsch[%d] is null\n",i);
if ((eNB->ulsch[i]->harq_mask >0) &&
(eNB->ulsch[i]->rnti==rnti)) return(i);
else if ((eNB->ulsch[i]->harq_mask == 0) && (first_free_index==-1)) first_free_index=i;
......@@ -960,7 +960,7 @@ int fill_dci_and_dlsch(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_
((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
dci_alloc->dci_length = sizeof_DCI1A_20MHz_FDD_t;
dci_alloc->dci_length = sizeof_DCI1A_10MHz_FDD_t;
((DCI1A_10MHz_FDD_t *)dci_pdu)->type = 1;
((DCI1A_10MHz_FDD_t *)dci_pdu)->vrb_type = rel8->virtual_resource_block_assignment_flag;
((DCI1A_10MHz_FDD_t *)dci_pdu)->mcs = rel8->mcs_1;
......@@ -7489,15 +7489,6 @@ int generate_ue_dlsch_params_from_dci(int frame,
uint8_t subframe2harq_pid(LTE_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t subframe)
{
/*
#ifdef DEBUG_DCI
if (frame_parms->frame_type == TDD)
printf("dci_tools.c: subframe2_harq_pid, subframe %d for TDD configuration %d\n",subframe,frame_parms->tdd_config);
else
printf("dci_tools.c: subframe2_harq_pid, subframe %d for FDD \n",subframe);
#endif
*/
uint8_t ret = 255;
if (frame_parms->frame_type == FDD) {
......
......@@ -374,8 +374,12 @@ typedef struct {
uint8_t rar_alloc;
/// Status Flag indicating for this ULSCH (idle,active,disabled)
SCH_status_t status;
/// Subframe scheduling indicator (i.e. Transmission opportunity indicator)
uint8_t subframe_scheduling_flag;
/// Flag to indicate that eNB should decode UE Msg3
uint8_t Msg3_flag;
/// Subframe for reception
uint8_t subframe;
/// Frame for reception
uint32_t frame;
/// Subframe cba scheduling indicator (i.e. CBA Transmission opportunity indicator)
uint8_t subframe_cba_scheduling_flag;
/// PHICH active flag
......@@ -505,12 +509,6 @@ typedef struct {
uint16_t beta_offset_harqack_times8;
/// Flag to indicate that eNB awaits UE Msg3
uint8_t Msg3_active;
/// Flag to indicate that eNB should decode UE Msg3
uint8_t Msg3_flag;
/// Subframe for Msg3
uint8_t Msg3_subframe;
/// Frame for Msg3
uint32_t Msg3_frame;
/// RNTI attributed to this ULSCH
uint16_t rnti;
/// cyclic shift for DM RS
......
......@@ -151,9 +151,9 @@ LTE_eNB_DLSCH_t *new_eNB_dlsch(unsigned char Kmimo,unsigned char Mdlharq,uint32_
dlsch->Nsoft = Nsoft;
for (layer=0; layer<4; layer++) {
dlsch->ue_spec_bf_weights[layer] = (int32_t**)malloc16(frame_parms->nb_antennas_tx*sizeof(int32_t*));
dlsch->ue_spec_bf_weights[layer] = (int32_t**)malloc16(64*sizeof(int32_t*));
for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
for (aa=0; aa<64; aa++) {
dlsch->ue_spec_bf_weights[layer][aa] = (int32_t *)malloc16(OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES*sizeof(int32_t));
for (re=0;re<OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES; re++) {
dlsch->ue_spec_bf_weights[layer][aa][re] = 0x00007fff;
......
......@@ -2216,7 +2216,9 @@ int dlsch_modulation(PHY_VARS_eNB* phy_vars_eNB,
for (eNB_id=0;eNB_id<ru->num_eNB;eNB_id++){
if (phy_vars_eNB == ru->eNB_list[eNB_id]) {
for (aa=0;aa<ru->nb_tx;aa++){
memcpy(ru->beam_weights[eNB_id][5][aa],dlsch0->ue_spec_bf_weights[ru_id][0][aa],frame_parms->ofdm_symbol_size*sizeof(int32_t));
memcpy(ru->beam_weights[eNB_id][5][aa],
dlsch0->ue_spec_bf_weights[ru_id][0],
frame_parms->ofdm_symbol_size*sizeof(int32_t));
}
}
}
......@@ -2454,6 +2456,7 @@ int dlsch_modulation_SIC(int32_t **sic_buffer,
int G)
{
AssertFatal(1==0,"This function needs to be reintegrated ...\n");
uint8_t harq_pid = -1;//dlsch0->current_harq_pid;
LTE_DL_eNB_HARQ_t *dlsch0_harq = dlsch0->harq_processes[harq_pid];
uint32_t i,jj,re_allocated=0;
......
......@@ -385,14 +385,22 @@ void malloc_IF4p5_buffer(RU_t *ru) {
int i;
if (eth->flags == ETH_RAW_IF4p5_MODE) {
for (i=0;i<10;i++)
for (i=0;i<10;i++) {
ru->ifbuffer.tx[i] = malloc(RAW_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.tx[i],0,RAW_IF4p5_PRACH_SIZE_BYTES);
}
ru->ifbuffer.tx_prach = malloc(RAW_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.tx_prach,0,RAW_IF4p5_PRACH_SIZE_BYTES);
ru->ifbuffer.rx = malloc(RAW_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.rx,0,RAW_IF4p5_PRACH_SIZE_BYTES);
} else {
for (i=0;i<10;i++)
for (i=0;i<10;i++) {
ru->ifbuffer.tx[i] = malloc(UDP_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.tx[i],0,UDP_IF4p5_PRACH_SIZE_BYTES);
}
ru->ifbuffer.tx_prach = malloc(UDP_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.tx_prach,0,UDP_IF4p5_PRACH_SIZE_BYTES);
ru->ifbuffer.rx = malloc(UDP_IF4p5_PRACH_SIZE_BYTES);
memset((void*)ru->ifbuffer.rx,0,UDP_IF4p5_PRACH_SIZE_BYTES);
}
}
......@@ -67,9 +67,9 @@ void generate_pcfich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms)
}
#ifdef DEBUG_PCFICH
//#ifdef DEBUG_PCFICH
printf("pcfich_reg : %d,%d,%d,%d\n",pcfich_reg[0],pcfich_reg[1],pcfich_reg[2],pcfich_reg[3]);
#endif
//#endif
}
void pcfich_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
......@@ -144,7 +144,8 @@ void generate_pcfich(uint8_t num_pdcch_symbols,
int nushiftmod3 = frame_parms->nushift%3;
#ifdef DEBUG_PCFICH
printf("[PHY] Generating PCFICH for %d PDCCH symbols, AMP %d\n",num_pdcch_symbols,amp);
LOG_D(PHY,"Generating PCFICH in subfrmae %d for %d PDCCH symbols, AMP %d, p %d, Ncp %d\n",
subframe,num_pdcch_symbols,amp,frame_parms->nb_antenna_ports_eNB,frame_parms->Ncp);
#endif
// scrambling
......@@ -199,7 +200,6 @@ void generate_pcfich(uint8_t num_pdcch_symbols,
if (reg_offset>=frame_parms->ofdm_symbol_size)
reg_offset=1 + reg_offset-frame_parms->ofdm_symbol_size;
// printf("mapping pcfich reg_offset %d\n",reg_offset);
for (i=0; i<6; i++) {
if ((i!=nushiftmod3)&&(i!=(nushiftmod3+3))) {
txdataF[0][symbol_offset+reg_offset+i] = pcfich_d[0][m];
......
......@@ -318,7 +318,7 @@ void generate_phich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms)
Ngroup_PHICH<<=1;
}
// #ifdef DEBUG_PHICH
#ifdef DEBUG_PHICH
LOG_I(PHY,"Ngroup_PHICH %d (phich_config_common.phich_resource %d,phich_config_common.phich_duration %s, NidCell %d,Ncp %d, frame_type %d), smallest pcfich REG %d, n0 %d, n1 %d (first PHICH REG %d)\n",
((frame_parms->Ncp == NORMAL)?Ngroup_PHICH:(Ngroup_PHICH>>1)),
frame_parms->phich_config_common.phich_resource,
......@@ -328,7 +328,7 @@ void generate_phich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms)
n0,
n1,
((frame_parms->Nid_cell))%n0);
//#endif
#endif
// This is the algorithm from Section 6.9.3 in 36-211, it works only for normal PHICH duration for now ...
......@@ -382,9 +382,9 @@ void generate_phich_reg_mapping(LTE_DL_FRAME_PARMS *frame_parms)
if (frame_parms->phich_reg[mprime][2]>=pcfich_reg[(frame_parms->pcfich_first_reg_idx+3)&3])
frame_parms->phich_reg[mprime][2]++;
#ifdef DEBUG_PHICH
#ifdef DEBUG_PHICH
printf("phich_reg :%d => %d,%d,%d\n",mprime,frame_parms->phich_reg[mprime][0],frame_parms->phich_reg[mprime][1],frame_parms->phich_reg[mprime][2]);
#endif
#endif
} else { // extended PHICH duration
frame_parms->phich_reg[mprime<<1][0] = (frame_parms->Nid_cell + mprime)%n0;
frame_parms->phich_reg[1+(mprime<<1)][0] = (frame_parms->Nid_cell + mprime)%n0;
......@@ -1473,7 +1473,7 @@ void rx_phich(PHY_VARS_UE *ue,
// harqId-8 corresponds to the temporary struct. In total we have 8 harq process(0 ..7) + 1 temporary harq process()
//ulsch->harq_processes[8] = ulsch->harq_processes[harq_pid];
ulsch->harq_processes[harq_pid]->subframe_scheduling_flag =0;
ulsch->harq_processes[harq_pid]->status = SCH_IDLE;
ulsch->harq_processes[harq_pid]->round = 0;
// inform MAC?
......@@ -1524,7 +1524,7 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
if ((ulsch[UE_id])&&(ulsch[UE_id]->rnti>0)) {
if (ulsch[UE_id]->harq_processes[harq_pid]->phich_active == 1) {
LOG_D(PHY,"[eNB][PUSCH %d/%x] Frame %d subframe %d (pusch_subframe %d,pusch_frame %d) phich active %d\n",
LOG_I(PHY,"[eNB][PUSCH %d/%x] Frame %d subframe %d (pusch_subframe %d,pusch_frame %d) phich active %d\n",
harq_pid,ulsch[UE_id]->rnti,proc->frame_tx,subframe,pusch_subframe,pusch_frame,ulsch[UE_id]->harq_processes[harq_pid]->phich_active);
/* the HARQ process may have been reused by a new scheduling, so we use
......@@ -1542,7 +1542,7 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
nseq_PHICH = ((ulsch[UE_id]->harq_processes[harq_pid]->previous_first_rb/Ngroup_PHICH) +
ulsch[UE_id]->harq_processes[harq_pid]->previous_n_DMRS)%(2*NSF_PHICH);
LOG_D(PHY,"[eNB %d][PUSCH %d] Frame %d subframe %d Generating PHICH, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d dci_alloc %d)\n",
LOG_I(PHY,"[eNB %d][PUSCH %d] Frame %d subframe %d Generating PHICH, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d dci_alloc %d)\n",
eNB->Mod_id,harq_pid,proc->frame_tx,
subframe,ngroup_PHICH,Ngroup_PHICH,nseq_PHICH,
ulsch[UE_id]->harq_processes[harq_pid]->phich_ACK,
......@@ -1558,7 +1558,7 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
T_INT(ulsch[UE_id]->harq_processes[harq_pid]->previous_n_DMRS));
if (ulsch[UE_id]->Msg3_active == 1) {
LOG_D(PHY,"[eNB %d][PUSCH %d][RAPROC] Frame %d, subframe %d: Generating Msg3 PHICH for UE %d, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d\n",
LOG_I(PHY,"[eNB %d][PUSCH %d][RAPROC] Frame %d, subframe %d: Generating Msg3 PHICH for UE %d, ngroup_PHICH %d/%d, nseq_PHICH %d : HI %d, first_rb %d\n",
eNB->Mod_id,harq_pid,proc->frame_tx,subframe,
UE_id,ngroup_PHICH,Ngroup_PHICH,nseq_PHICH,ulsch[UE_id]->harq_processes[harq_pid]->phich_ACK,
ulsch[UE_id]->harq_processes[harq_pid]->previous_first_rb);
......@@ -1591,9 +1591,11 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
if (ulsch[UE_id]->harq_processes[harq_pid]->phich_ACK==0 ) {
T(T_ENB_PHY_ULSCH_UE_NO_DCI_RETRANSMISSION, T_INT(eNB->Mod_id), T_INT(proc->frame_tx),
T_INT(subframe), T_INT(UE_id), T_INT(ulsch[UE_id]->rnti), T_INT(harq_pid));
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH NACK / (no format0 DCI) Setting subframe_scheduling_flag\n",
LOG_I(PHY,"[eNB %d][PUSCH %d] frame %d, subframe %d : PHICH NACK / (no format0 DCI) Setting subframe_scheduling_flag\n",
eNB->Mod_id,harq_pid,proc->frame_tx,subframe);
ulsch[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
// ulsch[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 1;
ulsch[UE_id]->harq_processes[harq_pid]->subframe = (subframe + 4)%10;
if (subframe>5) ulsch[UE_id]->harq_processes[harq_pid]->frame++;
ulsch[UE_id]->harq_processes[harq_pid]->rvidx = rv_table[ulsch[UE_id]->harq_processes[harq_pid]->round&3];
ulsch[UE_id]->harq_processes[harq_pid]->O_RI = 0;
ulsch[UE_id]->harq_processes[harq_pid]->Or2 = 0;
......@@ -1601,9 +1603,9 @@ void generate_phich_top(PHY_VARS_eNB *eNB,
ulsch[UE_id]->harq_processes[harq_pid]->uci_format = HLC_subband_cqi_nopmi;
} else {
LOG_D(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d PHICH ACK (no format0 DCI) Clearing subframe_scheduling_flag, setting round to 0\n",
LOG_I(PHY,"[eNB %d][PUSCH %d] frame %d subframe %d PHICH ACK (no format0 DCI) Clearing subframe_scheduling_flag, setting round to 0\n",
eNB->Mod_id,harq_pid,proc->frame_tx,subframe);
ulsch[UE_id]->harq_processes[harq_pid]->subframe_scheduling_flag = 0;
ulsch[UE_id]->harq_processes[harq_pid]->status = SCH_IDLE;
ulsch[UE_id]->harq_processes[harq_pid]->round=0;
}
}
......
......@@ -1403,6 +1403,7 @@ void dci_encoding(uint8_t *a,
uint16_t rnti);
/*! \brief Top-level DCI entry point. This routine codes an set of DCI PDUs and performs PDCCH modulation, interleaving and mapping.
\param num_dci Number of pdcch symbols
\param num_dci Number of DCI pdus to encode
\param dci_alloc Allocation vectors for each DCI pdu
\param n_rnti n_RNTI (see )
......@@ -1412,7 +1413,8 @@ void dci_encoding(uint8_t *a,
\param sub_frame_offset subframe offset in frame
@returns Number of PDCCH symbols
*/
uint8_t generate_dci_top(uint8_t num_dci,
uint8_t generate_dci_top(uint8_t num_pdcch_symbols,
uint8_t num_dci,
DCI_ALLOC_t *dci_alloc,
uint32_t n_rnti,
int16_t amp,
......@@ -1679,11 +1681,10 @@ int32_t generate_eNB_dlsch_params_from_dci(int frame,
uint16_t DL_pmi_single,
uint8_t beamforming_mode);
int32_t generate_eNB_ulsch_params_from_rar(uint8_t *rar_pdu,
frame_t frame,
uint8_t subframe,
LTE_eNB_ULSCH_t *ulsch,
LTE_DL_FRAME_PARMS *frame_parms);
int generate_eNB_ulsch_params_from_rar(PHY_VARS_eNB *eNB,
unsigned char *rar_pdu,
uint32_t frame,
unsigned char subframe);
int generate_ue_ulsch_params_from_dci(void *dci_pdu,
rnti_t rnti,
......
......@@ -52,15 +52,15 @@ extern uint16_t RIV_max6,RIV_max25,RIV_max50,RIV_max100;
//#define DEBUG_RAR
#ifdef OPENAIR2
int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
int generate_eNB_ulsch_params_from_rar(PHY_VARS_eNB *eNB,
unsigned char *rar_pdu,
uint32_t frame,
unsigned char subframe,
LTE_eNB_ULSCH_t *ulsch,
LTE_DL_FRAME_PARMS *frame_parms)
{
unsigned char subframe){
LTE_DL_FRAME_PARMS *frame_parms = &eNB->frame_parms;
// RA_HEADER_RAPID *rarh = (RA_HEADER_RAPID *)rar_pdu;
// RAR_PDU *rar = (RAR_PDU *)(rar_pdu+1);
......@@ -71,8 +71,20 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
uint16_t *RIV2nb_rb_LUT, *RIV2first_rb_LUT;
uint16_t RIV_max;
uint16_t use_srs=0;
uint16_t rnti;
LTE_eNB_ULSCH_t *ulsch;
LTE_UL_eNB_HARQ_t *ulsch_harq;
int8_t UE_id;
LOG_I(PHY,"[eNB][RAPROC] generate_eNB_ulsch_params_from_rar: subframe %d (harq_pid %d)\n",subframe,harq_pid);
rnti = (((uint16_t)rar[4])<<8)+rar[5];
LOG_D(PHY,"[eNB][RAPROC] generate_eNB_ulsch_params_from_rar: subframe %d (harq_pid %d)\n",subframe,harq_pid);
AssertFatal((UE_id = find_ulsch(rnti,eNB,SEARCH_EXIST_OR_FREE))>=0,
"Cannot get UE id for RAR (rnti %x)\n",rnti);
ulsch = eNB->ulsch[UE_id];
ulsch_harq = ulsch->harq_processes[harq_pid];
switch (frame_parms->N_RB_DL) {
case 6:
......@@ -104,7 +116,7 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
break;
}
ulsch->harq_processes[harq_pid]->TPC = (rar[3]>>2)&7;//rar->TPC;
ulsch_harq->TPC = (rar[3]>>2)&7;//rar->TPC;
rballoc = (((uint16_t)(rar[1]&7))<<7)|(rar[2]>>1);
if (rballoc>RIV_max) {
......@@ -112,43 +124,44 @@ int generate_eNB_ulsch_params_from_rar(unsigned char *rar_pdu,
return(-1);
}
ulsch->harq_processes[harq_pid]->rar_alloc = 1;
ulsch->harq_processes[harq_pid]->first_rb = RIV2first_rb_LUT[rballoc];
ulsch->harq_processes[harq_pid]->nb_rb = RIV2nb_rb_LUT[rballoc];
// ulsch->harq_processes[harq_pid]->Ndi = 1;
ulsch_harq->rar_alloc = 1;
ulsch_harq->first_rb = RIV2first_rb_LUT[rballoc];
ulsch_harq->nb_rb = RIV2nb_rb_LUT[rballoc];
// ulsch_harq->Ndi = 1;
cqireq = rar[3]&1;
if (cqireq==1) {
ulsch->harq_processes[harq_pid]->Or2 = sizeof_wideband_cqi_rank2_2A_5MHz;
ulsch->harq_processes[harq_pid]->Or1 = sizeof_wideband_cqi_rank1_2A_5MHz;
ulsch->harq_processes[harq_pid]->O_RI = 1;
ulsch_harq->Or2 = sizeof_wideband_cqi_rank2_2A_5MHz;
ulsch_harq->Or1 = sizeof_wideband_cqi_rank1_2A_5MHz;
ulsch_harq->O_RI = 1;
} else {
ulsch->harq_processes[harq_pid]->O_RI = 0;//1;
ulsch->harq_processes[harq_pid]->Or2 = 0;
ulsch->harq_processes[harq_pid]->Or1 = 0;
ulsch_harq->O_RI = 0;//1;
ulsch_harq->Or2 = 0;
ulsch_harq->Or1 = 0;
}
ulsch->harq_processes[harq_pid]->O_ACK = 0;//2;
ulsch_harq->O_ACK = 0;//2;
ulsch->beta_offset_cqi_times8 = 18;
ulsch->beta_offset_ri_times8 = 10;
ulsch->beta_offset_harqack_times8 = 16;
ulsch->rnti = (((uint16_t)rar[4])<<8)+rar[5];
if (ulsch->harq_processes[harq_pid]->round == 0) {
ulsch->harq_processes[harq_pid]->status = ACTIVE;
ulsch->harq_processes[harq_pid]->rvidx = 0;
ulsch->harq_processes[harq_pid]->mcs = ((rar[2]&1)<<3)|(rar[3]>>5);
//ulsch->harq_processes[harq_pid]->TBS = dlsch_tbs25[ulsch->harq_processes[harq_pid]->mcs][ulsch->harq_processes[harq_pid]->nb_rb-1];
ulsch->harq_processes[harq_pid]->TBS = TBStable[get_I_TBS_UL(ulsch->harq_processes[harq_pid]->mcs)][ulsch->harq_processes[harq_pid]->nb_rb-1];
ulsch->harq_processes[harq_pid]->Msc_initial = 12*ulsch->harq_processes[harq_pid]->nb_rb;
ulsch->harq_processes[harq_pid]->Nsymb_initial = 9;
ulsch->harq_processes[harq_pid]->round = 0;
ulsch->rnti = rnti;
ulsch->harq_mask = 1<<harq_pid;